1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
82 // Limit the width of DAG chains. This is important in general to prevent
83 // prevent DAG-based analysis from blowing up. For example, alias analysis and
84 // load clustering may not complete in reasonable time. It is difficult to
85 // recognize and avoid this situation within each individual analysis, and
86 // future analyses are likely to have the same behavior. Limiting DAG width is
87 // the safe approach, and will be especially important with global DAGs.
89 // MaxParallelChains default is arbitrarily high to avoid affecting
90 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
91 // sequence over this should have been converted to llvm.memcpy by the
92 // frontend. It easy to induce this behavior with .ll code such as:
93 // %buffer = alloca [4096 x i8]
94 // %data = load [4096 x i8]* %argPtr
95 // store [4096 x i8] %data, [4096 x i8]* %buffer
96 static const unsigned MaxParallelChains = 64;
98 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
99 const SDValue *Parts, unsigned NumParts,
100 MVT PartVT, EVT ValueVT, const Value *V);
102 /// getCopyFromParts - Create a value that contains the specified legal parts
103 /// combined into the value they represent. If the parts combine to a type
104 /// larger then ValueVT then AssertOp can be used to specify whether the extra
105 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
106 /// (ISD::AssertSext).
107 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
108 const SDValue *Parts,
109 unsigned NumParts, MVT PartVT, EVT ValueVT,
111 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
112 if (ValueVT.isVector())
113 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
116 assert(NumParts > 0 && "No parts to assemble!");
117 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
118 SDValue Val = Parts[0];
121 // Assemble the value from multiple parts.
122 if (ValueVT.isInteger()) {
123 unsigned PartBits = PartVT.getSizeInBits();
124 unsigned ValueBits = ValueVT.getSizeInBits();
126 // Assemble the power of 2 part.
127 unsigned RoundParts = NumParts & (NumParts - 1) ?
128 1 << Log2_32(NumParts) : NumParts;
129 unsigned RoundBits = PartBits * RoundParts;
130 EVT RoundVT = RoundBits == ValueBits ?
131 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
134 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
136 if (RoundParts > 2) {
137 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
139 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
140 RoundParts / 2, PartVT, HalfVT, V);
142 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
143 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
146 if (TLI.isBigEndian())
149 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
151 if (RoundParts < NumParts) {
152 // Assemble the trailing non-power-of-2 part.
153 unsigned OddParts = NumParts - RoundParts;
154 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
155 Hi = getCopyFromParts(DAG, DL,
156 Parts + RoundParts, OddParts, PartVT, OddVT, V);
158 // Combine the round and odd parts.
160 if (TLI.isBigEndian())
162 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
163 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
164 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
165 DAG.getConstant(Lo.getValueType().getSizeInBits(),
166 TLI.getPointerTy()));
167 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
168 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
170 } else if (PartVT.isFloatingPoint()) {
171 // FP split into multiple FP parts (for ppcf128)
172 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
175 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
176 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
177 if (TLI.hasBigEndianPartOrdering(ValueVT))
179 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
181 // FP split into integer parts (soft fp)
182 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
183 !PartVT.isVector() && "Unexpected split");
184 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
185 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
189 // There is now one part, held in Val. Correct it to match ValueVT.
190 EVT PartEVT = Val.getValueType();
192 if (PartEVT == ValueVT)
195 if (PartEVT.isInteger() && ValueVT.isInteger()) {
196 if (ValueVT.bitsLT(PartEVT)) {
197 // For a truncate, see if we have any information to
198 // indicate whether the truncated bits will always be
199 // zero or sign-extension.
200 if (AssertOp != ISD::DELETED_NODE)
201 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
202 DAG.getValueType(ValueVT));
203 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
205 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
208 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
209 // FP_ROUND's are always exact here.
210 if (ValueVT.bitsLT(Val.getValueType()))
211 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
212 DAG.getTargetConstant(1, TLI.getPointerTy()));
214 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
217 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
218 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
220 llvm_unreachable("Unknown mismatch!");
223 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
224 const Twine &ErrMsg) {
225 const Instruction *I = dyn_cast_or_null<Instruction>(V);
227 return Ctx.emitError(ErrMsg);
229 const char *AsmError = ", possible invalid constraint for vector type";
230 if (const CallInst *CI = dyn_cast<CallInst>(I))
231 if (isa<InlineAsm>(CI->getCalledValue()))
232 return Ctx.emitError(I, ErrMsg + AsmError);
234 return Ctx.emitError(I, ErrMsg);
237 /// getCopyFromPartsVector - Create a value that contains the specified legal
238 /// parts combined into the value they represent. If the parts combine to a
239 /// type larger then ValueVT then AssertOp can be used to specify whether the
240 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
241 /// ValueVT (ISD::AssertSext).
242 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
243 const SDValue *Parts, unsigned NumParts,
244 MVT PartVT, EVT ValueVT, const Value *V) {
245 assert(ValueVT.isVector() && "Not a vector value");
246 assert(NumParts > 0 && "No parts to assemble!");
247 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
248 SDValue Val = Parts[0];
250 // Handle a multi-element vector.
254 unsigned NumIntermediates;
256 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
257 NumIntermediates, RegisterVT);
258 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
259 NumParts = NumRegs; // Silence a compiler warning.
260 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
261 assert(RegisterVT == Parts[0].getSimpleValueType() &&
262 "Part type doesn't match part!");
264 // Assemble the parts into intermediate operands.
265 SmallVector<SDValue, 8> Ops(NumIntermediates);
266 if (NumIntermediates == NumParts) {
267 // If the register was not expanded, truncate or copy the value,
269 for (unsigned i = 0; i != NumParts; ++i)
270 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
271 PartVT, IntermediateVT, V);
272 } else if (NumParts > 0) {
273 // If the intermediate type was expanded, build the intermediate
274 // operands from the parts.
275 assert(NumParts % NumIntermediates == 0 &&
276 "Must expand into a divisible number of parts!");
277 unsigned Factor = NumParts / NumIntermediates;
278 for (unsigned i = 0; i != NumIntermediates; ++i)
279 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
280 PartVT, IntermediateVT, V);
283 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
284 // intermediate operands.
285 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
290 // There is now one part, held in Val. Correct it to match ValueVT.
291 EVT PartEVT = Val.getValueType();
293 if (PartEVT == ValueVT)
296 if (PartEVT.isVector()) {
297 // If the element type of the source/dest vectors are the same, but the
298 // parts vector has more elements than the value vector, then we have a
299 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
301 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
302 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
303 "Cannot narrow, it would be a lossy transformation");
304 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
305 DAG.getConstant(0, TLI.getVectorIdxTy()));
308 // Vector/Vector bitcast.
309 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
310 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
312 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
313 "Cannot handle this kind of promotion");
314 // Promoted vector extract
315 bool Smaller = ValueVT.bitsLE(PartEVT);
316 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
321 // Trivial bitcast if the types are the same size and the destination
322 // vector type is legal.
323 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
324 TLI.isTypeLegal(ValueVT))
325 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
327 // Handle cases such as i8 -> <1 x i1>
328 if (ValueVT.getVectorNumElements() != 1) {
329 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
330 "non-trivial scalar-to-vector conversion");
331 return DAG.getUNDEF(ValueVT);
334 if (ValueVT.getVectorNumElements() == 1 &&
335 ValueVT.getVectorElementType() != PartEVT) {
336 bool Smaller = ValueVT.bitsLE(PartEVT);
337 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
338 DL, ValueVT.getScalarType(), Val);
341 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
344 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
345 SDValue Val, SDValue *Parts, unsigned NumParts,
346 MVT PartVT, const Value *V);
348 /// getCopyToParts - Create a series of nodes that contain the specified value
349 /// split into legal parts. If the parts contain more bits than Val, then, for
350 /// integers, ExtendKind can be used to specify how to generate the extra bits.
351 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
352 SDValue Val, SDValue *Parts, unsigned NumParts,
353 MVT PartVT, const Value *V,
354 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
355 EVT ValueVT = Val.getValueType();
357 // Handle the vector case separately.
358 if (ValueVT.isVector())
359 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
361 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
362 unsigned PartBits = PartVT.getSizeInBits();
363 unsigned OrigNumParts = NumParts;
364 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
369 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
370 EVT PartEVT = PartVT;
371 if (PartEVT == ValueVT) {
372 assert(NumParts == 1 && "No-op copy with multiple parts!");
377 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
378 // If the parts cover more bits than the value has, promote the value.
379 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
380 assert(NumParts == 1 && "Do not know what to promote to!");
381 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
383 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
384 ValueVT.isInteger() &&
385 "Unknown mismatch!");
386 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
387 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
388 if (PartVT == MVT::x86mmx)
389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
391 } else if (PartBits == ValueVT.getSizeInBits()) {
392 // Different types of the same size.
393 assert(NumParts == 1 && PartEVT != ValueVT);
394 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
395 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
396 // If the parts cover less bits than value has, truncate the value.
397 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
398 ValueVT.isInteger() &&
399 "Unknown mismatch!");
400 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
401 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
402 if (PartVT == MVT::x86mmx)
403 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
406 // The value may have changed - recompute ValueVT.
407 ValueVT = Val.getValueType();
408 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
409 "Failed to tile the value with PartVT!");
412 if (PartEVT != ValueVT)
413 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
414 "scalar-to-vector conversion failed");
420 // Expand the value into multiple parts.
421 if (NumParts & (NumParts - 1)) {
422 // The number of parts is not a power of 2. Split off and copy the tail.
423 assert(PartVT.isInteger() && ValueVT.isInteger() &&
424 "Do not know what to expand to!");
425 unsigned RoundParts = 1 << Log2_32(NumParts);
426 unsigned RoundBits = RoundParts * PartBits;
427 unsigned OddParts = NumParts - RoundParts;
428 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
429 DAG.getIntPtrConstant(RoundBits));
430 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
432 if (TLI.isBigEndian())
433 // The odd parts were reversed by getCopyToParts - unreverse them.
434 std::reverse(Parts + RoundParts, Parts + NumParts);
436 NumParts = RoundParts;
437 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
438 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
441 // The number of parts is a power of 2. Repeatedly bisect the value using
443 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
444 EVT::getIntegerVT(*DAG.getContext(),
445 ValueVT.getSizeInBits()),
448 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
449 for (unsigned i = 0; i < NumParts; i += StepSize) {
450 unsigned ThisBits = StepSize * PartBits / 2;
451 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
452 SDValue &Part0 = Parts[i];
453 SDValue &Part1 = Parts[i+StepSize/2];
455 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
456 ThisVT, Part0, DAG.getIntPtrConstant(1));
457 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
458 ThisVT, Part0, DAG.getIntPtrConstant(0));
460 if (ThisBits == PartBits && ThisVT != PartVT) {
461 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
462 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
467 if (TLI.isBigEndian())
468 std::reverse(Parts, Parts + OrigNumParts);
472 /// getCopyToPartsVector - Create a series of nodes that contain the specified
473 /// value split into legal parts.
474 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
475 SDValue Val, SDValue *Parts, unsigned NumParts,
476 MVT PartVT, const Value *V) {
477 EVT ValueVT = Val.getValueType();
478 assert(ValueVT.isVector() && "Not a vector");
479 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
482 EVT PartEVT = PartVT;
483 if (PartEVT == ValueVT) {
485 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
486 // Bitconvert vector->vector case.
487 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
488 } else if (PartVT.isVector() &&
489 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
490 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
491 EVT ElementVT = PartVT.getVectorElementType();
492 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
494 SmallVector<SDValue, 16> Ops;
495 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
496 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
497 ElementVT, Val, DAG.getConstant(i,
498 TLI.getVectorIdxTy())));
500 for (unsigned i = ValueVT.getVectorNumElements(),
501 e = PartVT.getVectorNumElements(); i != e; ++i)
502 Ops.push_back(DAG.getUNDEF(ElementVT));
504 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
506 // FIXME: Use CONCAT for 2x -> 4x.
508 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
509 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
510 } else if (PartVT.isVector() &&
511 PartEVT.getVectorElementType().bitsGE(
512 ValueVT.getVectorElementType()) &&
513 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
515 // Promoted vector extract
516 bool Smaller = PartEVT.bitsLE(ValueVT);
517 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
520 // Vector -> scalar conversion.
521 assert(ValueVT.getVectorNumElements() == 1 &&
522 "Only trivial vector-to-scalar conversions should get here!");
523 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
524 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
526 bool Smaller = ValueVT.bitsLE(PartVT);
527 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
552 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
554 DAG.getConstant(i * (NumElements / NumIntermediates),
555 TLI.getVectorIdxTy()));
557 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
559 DAG.getConstant(i, TLI.getVectorIdxTy()));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
581 /// RegsForValue - This struct represents the registers (physical or virtual)
582 /// that a particular set of values is assigned, and the type information
583 /// about the value. The most common situation is to represent one value at a
584 /// time, but struct or array values are handled element-wise as multiple
585 /// values. The splitting of aggregates is performed recursively, so that we
586 /// never have aggregate-typed registers. The values at this point do not
587 /// necessarily have legal types, so each value may require one or more
588 /// registers of some legal type.
590 struct RegsForValue {
591 /// ValueVTs - The value types of the values, which may not be legal, and
592 /// may need be promoted or synthesized from one or more registers.
594 SmallVector<EVT, 4> ValueVTs;
596 /// RegVTs - The value types of the registers. This is the same size as
597 /// ValueVTs and it records, for each value, what the type of the assigned
598 /// register or registers are. (Individual values are never synthesized
599 /// from more than one type of register.)
601 /// With virtual registers, the contents of RegVTs is redundant with TLI's
602 /// getRegisterType member function, however when with physical registers
603 /// it is necessary to have a separate record of the types.
605 SmallVector<MVT, 4> RegVTs;
607 /// Regs - This list holds the registers assigned to the values.
608 /// Each legal or promoted value requires one register, and each
609 /// expanded value requires multiple registers.
611 SmallVector<unsigned, 4> Regs;
615 RegsForValue(const SmallVector<unsigned, 4> ®s,
616 MVT regvt, EVT valuevt)
617 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
619 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
620 unsigned Reg, Type *Ty) {
621 ComputeValueVTs(tli, Ty, ValueVTs);
623 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
624 EVT ValueVT = ValueVTs[Value];
625 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
626 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
627 for (unsigned i = 0; i != NumRegs; ++i)
628 Regs.push_back(Reg + i);
629 RegVTs.push_back(RegisterVT);
634 /// append - Add the specified values to this one.
635 void append(const RegsForValue &RHS) {
636 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
637 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
638 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
641 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
642 /// this value and returns the result as a ValueVTs value. This uses
643 /// Chain/Flag as the input and updates them for the output Chain/Flag.
644 /// If the Flag pointer is NULL, no flag is used.
645 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
647 SDValue &Chain, SDValue *Flag,
648 const Value *V = nullptr) const;
650 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
651 /// specified value into the registers specified by this object. This uses
652 /// Chain/Flag as the input and updates them for the output Chain/Flag.
653 /// If the Flag pointer is NULL, no flag is used.
655 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
656 SDValue *Flag, const Value *V,
657 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
659 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
660 /// operand list. This adds the code marker, matching input operand index
661 /// (if applicable), and includes the number of values added into it.
662 void AddInlineAsmOperands(unsigned Kind,
663 bool HasMatching, unsigned MatchingIdx,
665 std::vector<SDValue> &Ops) const;
669 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
670 /// this value and returns the result as a ValueVT value. This uses
671 /// Chain/Flag as the input and updates them for the output Chain/Flag.
672 /// If the Flag pointer is NULL, no flag is used.
673 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
674 FunctionLoweringInfo &FuncInfo,
676 SDValue &Chain, SDValue *Flag,
677 const Value *V) const {
678 // A Value with type {} or [0 x %t] needs no registers.
679 if (ValueVTs.empty())
682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
684 // Assemble the legal parts into the final values.
685 SmallVector<SDValue, 4> Values(ValueVTs.size());
686 SmallVector<SDValue, 8> Parts;
687 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
688 // Copy the legal parts from the registers.
689 EVT ValueVT = ValueVTs[Value];
690 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
691 MVT RegisterVT = RegVTs[Value];
693 Parts.resize(NumRegs);
694 for (unsigned i = 0; i != NumRegs; ++i) {
697 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
699 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
700 *Flag = P.getValue(2);
703 Chain = P.getValue(1);
706 // If the source register was virtual and if we know something about it,
707 // add an assert node.
708 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
709 !RegisterVT.isInteger() || RegisterVT.isVector())
712 const FunctionLoweringInfo::LiveOutInfo *LOI =
713 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
717 unsigned RegSize = RegisterVT.getSizeInBits();
718 unsigned NumSignBits = LOI->NumSignBits;
719 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
721 if (NumZeroBits == RegSize) {
722 // The current value is a zero.
723 // Explicitly express that as it would be easier for
724 // optimizations to kick in.
725 Parts[i] = DAG.getConstant(0, RegisterVT);
729 // FIXME: We capture more information than the dag can represent. For
730 // now, just use the tightest assertzext/assertsext possible.
732 EVT FromVT(MVT::Other);
733 if (NumSignBits == RegSize)
734 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
735 else if (NumZeroBits >= RegSize-1)
736 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
737 else if (NumSignBits > RegSize-8)
738 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
739 else if (NumZeroBits >= RegSize-8)
740 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
741 else if (NumSignBits > RegSize-16)
742 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
743 else if (NumZeroBits >= RegSize-16)
744 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
745 else if (NumSignBits > RegSize-32)
746 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
747 else if (NumZeroBits >= RegSize-32)
748 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
752 // Add an assertion node.
753 assert(FromVT != MVT::Other);
754 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
755 RegisterVT, P, DAG.getValueType(FromVT));
758 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
759 NumRegs, RegisterVT, ValueVT, V);
764 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
767 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
768 /// specified value into the registers specified by this object. This uses
769 /// Chain/Flag as the input and updates them for the output Chain/Flag.
770 /// If the Flag pointer is NULL, no flag is used.
771 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
772 SDValue &Chain, SDValue *Flag, const Value *V,
773 ISD::NodeType PreferredExtendType) const {
774 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
775 ISD::NodeType ExtendKind = PreferredExtendType;
777 // Get the list of the values's legal parts.
778 unsigned NumRegs = Regs.size();
779 SmallVector<SDValue, 8> Parts(NumRegs);
780 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
781 EVT ValueVT = ValueVTs[Value];
782 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
783 MVT RegisterVT = RegVTs[Value];
785 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
786 ExtendKind = ISD::ZERO_EXTEND;
788 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
789 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
793 // Copy the parts into the registers.
794 SmallVector<SDValue, 8> Chains(NumRegs);
795 for (unsigned i = 0; i != NumRegs; ++i) {
798 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
800 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
801 *Flag = Part.getValue(1);
804 Chains[i] = Part.getValue(0);
807 if (NumRegs == 1 || Flag)
808 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
809 // flagged to it. That is the CopyToReg nodes and the user are considered
810 // a single scheduling unit. If we create a TokenFactor and return it as
811 // chain, then the TokenFactor is both a predecessor (operand) of the
812 // user as well as a successor (the TF operands are flagged to the user).
813 // c1, f1 = CopyToReg
814 // c2, f2 = CopyToReg
815 // c3 = TokenFactor c1, c2
818 Chain = Chains[NumRegs-1];
820 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
823 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
824 /// operand list. This adds the code marker and includes the number of
825 /// values added into it.
826 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
827 unsigned MatchingIdx,
829 std::vector<SDValue> &Ops) const {
830 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
832 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
834 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
835 else if (!Regs.empty() &&
836 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
837 // Put the register class of the virtual registers in the flag word. That
838 // way, later passes can recompute register class constraints for inline
839 // assembly as well as normal instructions.
840 // Don't do this for tied operands that can use the regclass information
842 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
843 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
844 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
847 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
850 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
851 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
852 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
853 MVT RegisterVT = RegVTs[Value];
854 for (unsigned i = 0; i != NumRegs; ++i) {
855 assert(Reg < Regs.size() && "Mismatch in # registers expected");
856 unsigned TheReg = Regs[Reg++];
857 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
859 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
860 // If we clobbered the stack pointer, MFI should know about it.
861 assert(DAG.getMachineFunction().getFrameInfo()->
862 hasInlineAsmWithSPAdjust());
868 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
869 const TargetLibraryInfo *li) {
873 DL = DAG.getTarget().getDataLayout();
874 Context = DAG.getContext();
875 LPadToCallSiteMap.clear();
878 /// clear - Clear out the current SelectionDAG and the associated
879 /// state and prepare this SelectionDAGBuilder object to be used
880 /// for a new block. This doesn't clear out information about
881 /// additional blocks that are needed to complete switch lowering
882 /// or PHI node updating; that information is cleared out as it is
884 void SelectionDAGBuilder::clear() {
886 UnusedArgNodeMap.clear();
887 PendingLoads.clear();
888 PendingExports.clear();
891 SDNodeOrder = LowestSDNodeOrder;
892 StatepointLowering.clear();
895 /// clearDanglingDebugInfo - Clear the dangling debug information
896 /// map. This function is separated from the clear so that debug
897 /// information that is dangling in a basic block can be properly
898 /// resolved in a different basic block. This allows the
899 /// SelectionDAG to resolve dangling debug information attached
901 void SelectionDAGBuilder::clearDanglingDebugInfo() {
902 DanglingDebugInfoMap.clear();
905 /// getRoot - Return the current virtual root of the Selection DAG,
906 /// flushing any PendingLoad items. This must be done before emitting
907 /// a store or any other node that may need to be ordered after any
908 /// prior load instructions.
910 SDValue SelectionDAGBuilder::getRoot() {
911 if (PendingLoads.empty())
912 return DAG.getRoot();
914 if (PendingLoads.size() == 1) {
915 SDValue Root = PendingLoads[0];
917 PendingLoads.clear();
921 // Otherwise, we have to make a token factor node.
922 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
924 PendingLoads.clear();
929 /// getControlRoot - Similar to getRoot, but instead of flushing all the
930 /// PendingLoad items, flush all the PendingExports items. It is necessary
931 /// to do this before emitting a terminator instruction.
933 SDValue SelectionDAGBuilder::getControlRoot() {
934 SDValue Root = DAG.getRoot();
936 if (PendingExports.empty())
939 // Turn all of the CopyToReg chains into one factored node.
940 if (Root.getOpcode() != ISD::EntryToken) {
941 unsigned i = 0, e = PendingExports.size();
942 for (; i != e; ++i) {
943 assert(PendingExports[i].getNode()->getNumOperands() > 1);
944 if (PendingExports[i].getNode()->getOperand(0) == Root)
945 break; // Don't add the root if we already indirectly depend on it.
949 PendingExports.push_back(Root);
952 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
954 PendingExports.clear();
959 void SelectionDAGBuilder::visit(const Instruction &I) {
960 // Set up outgoing PHI node register values before emitting the terminator.
961 if (isa<TerminatorInst>(&I))
962 HandlePHINodesInSuccessorBlocks(I.getParent());
968 visit(I.getOpcode(), I);
970 if (!isa<TerminatorInst>(&I) && !HasTailCall)
971 CopyToExportRegsIfNeeded(&I);
976 void SelectionDAGBuilder::visitPHI(const PHINode &) {
977 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
980 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
981 // Note: this doesn't use InstVisitor, because it has to work with
982 // ConstantExpr's in addition to instructions.
984 default: llvm_unreachable("Unknown instruction type encountered!");
985 // Build the switch statement using the Instruction.def file.
986 #define HANDLE_INST(NUM, OPCODE, CLASS) \
987 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
988 #include "llvm/IR/Instruction.def"
992 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
993 // generate the debug data structures now that we've seen its definition.
994 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
996 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
998 const DbgValueInst *DI = DDI.getDI();
999 DebugLoc dl = DDI.getdl();
1000 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1001 MDLocalVariable *Variable = DI->getVariable();
1002 MDExpression *Expr = DI->getExpression();
1003 assert(Variable->isValidLocationForIntrinsic(dl) &&
1004 "Expected inlined-at fields to agree");
1005 uint64_t Offset = DI->getOffset();
1006 // A dbg.value for an alloca is always indirect.
1007 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1009 if (Val.getNode()) {
1010 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
1012 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1013 IsIndirect, Offset, dl, DbgSDNodeOrder);
1014 DAG.AddDbgValue(SDV, Val.getNode(), false);
1017 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1018 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1022 /// getCopyFromRegs - If there was virtual register allocated for the value V
1023 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1024 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1025 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1028 if (It != FuncInfo.ValueMap.end()) {
1029 unsigned InReg = It->second;
1030 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1032 SDValue Chain = DAG.getEntryNode();
1033 res = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1034 resolveDanglingDebugInfo(V, res);
1040 /// getValue - Return an SDValue for the given Value.
1041 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1042 // If we already have an SDValue for this value, use it. It's important
1043 // to do this first, so that we don't create a CopyFromReg if we already
1044 // have a regular SDValue.
1045 SDValue &N = NodeMap[V];
1046 if (N.getNode()) return N;
1048 // If there's a virtual register allocated and initialized for this
1050 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
1051 if (copyFromReg.getNode()) {
1055 // Otherwise create a new SDValue and remember it.
1056 SDValue Val = getValueImpl(V);
1058 resolveDanglingDebugInfo(V, Val);
1062 // Return true if SDValue exists for the given Value
1063 bool SelectionDAGBuilder::findValue(const Value *V) const {
1064 return (NodeMap.find(V) != NodeMap.end()) ||
1065 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1068 /// getNonRegisterValue - Return an SDValue for the given Value, but
1069 /// don't look in FuncInfo.ValueMap for a virtual register.
1070 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1071 // If we already have an SDValue for this value, use it.
1072 SDValue &N = NodeMap[V];
1073 if (N.getNode()) return N;
1075 // Otherwise create a new SDValue and remember it.
1076 SDValue Val = getValueImpl(V);
1078 resolveDanglingDebugInfo(V, Val);
1082 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1083 /// Create an SDValue for the given value.
1084 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1085 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1087 if (const Constant *C = dyn_cast<Constant>(V)) {
1088 EVT VT = TLI.getValueType(V->getType(), true);
1090 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1091 return DAG.getConstant(*CI, VT);
1093 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1094 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1096 if (isa<ConstantPointerNull>(C)) {
1097 unsigned AS = V->getType()->getPointerAddressSpace();
1098 return DAG.getConstant(0, TLI.getPointerTy(AS));
1101 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1102 return DAG.getConstantFP(*CFP, VT);
1104 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1105 return DAG.getUNDEF(VT);
1107 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1108 visit(CE->getOpcode(), *CE);
1109 SDValue N1 = NodeMap[V];
1110 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1114 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1115 SmallVector<SDValue, 4> Constants;
1116 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1118 SDNode *Val = getValue(*OI).getNode();
1119 // If the operand is an empty aggregate, there are no values.
1121 // Add each leaf value from the operand to the Constants list
1122 // to form a flattened list of all the values.
1123 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1124 Constants.push_back(SDValue(Val, i));
1127 return DAG.getMergeValues(Constants, getCurSDLoc());
1130 if (const ConstantDataSequential *CDS =
1131 dyn_cast<ConstantDataSequential>(C)) {
1132 SmallVector<SDValue, 4> Ops;
1133 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1134 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1135 // Add each leaf value from the operand to the Constants list
1136 // to form a flattened list of all the values.
1137 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1138 Ops.push_back(SDValue(Val, i));
1141 if (isa<ArrayType>(CDS->getType()))
1142 return DAG.getMergeValues(Ops, getCurSDLoc());
1143 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1147 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1148 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1149 "Unknown struct or array constant!");
1151 SmallVector<EVT, 4> ValueVTs;
1152 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1153 unsigned NumElts = ValueVTs.size();
1155 return SDValue(); // empty struct
1156 SmallVector<SDValue, 4> Constants(NumElts);
1157 for (unsigned i = 0; i != NumElts; ++i) {
1158 EVT EltVT = ValueVTs[i];
1159 if (isa<UndefValue>(C))
1160 Constants[i] = DAG.getUNDEF(EltVT);
1161 else if (EltVT.isFloatingPoint())
1162 Constants[i] = DAG.getConstantFP(0, EltVT);
1164 Constants[i] = DAG.getConstant(0, EltVT);
1167 return DAG.getMergeValues(Constants, getCurSDLoc());
1170 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1171 return DAG.getBlockAddress(BA, VT);
1173 VectorType *VecTy = cast<VectorType>(V->getType());
1174 unsigned NumElements = VecTy->getNumElements();
1176 // Now that we know the number and type of the elements, get that number of
1177 // elements into the Ops array based on what kind of constant it is.
1178 SmallVector<SDValue, 16> Ops;
1179 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1180 for (unsigned i = 0; i != NumElements; ++i)
1181 Ops.push_back(getValue(CV->getOperand(i)));
1183 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1184 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1187 if (EltVT.isFloatingPoint())
1188 Op = DAG.getConstantFP(0, EltVT);
1190 Op = DAG.getConstant(0, EltVT);
1191 Ops.assign(NumElements, Op);
1194 // Create a BUILD_VECTOR node.
1195 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1198 // If this is a static alloca, generate it as the frameindex instead of
1200 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1201 DenseMap<const AllocaInst*, int>::iterator SI =
1202 FuncInfo.StaticAllocaMap.find(AI);
1203 if (SI != FuncInfo.StaticAllocaMap.end())
1204 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1207 // If this is an instruction which fast-isel has deferred, select it now.
1208 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1209 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1210 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1211 SDValue Chain = DAG.getEntryNode();
1212 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1215 llvm_unreachable("Can't get register for value!");
1218 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1219 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1220 SDValue Chain = getControlRoot();
1221 SmallVector<ISD::OutputArg, 8> Outs;
1222 SmallVector<SDValue, 8> OutVals;
1224 if (!FuncInfo.CanLowerReturn) {
1225 unsigned DemoteReg = FuncInfo.DemoteRegister;
1226 const Function *F = I.getParent()->getParent();
1228 // Emit a store of the return value through the virtual register.
1229 // Leave Outs empty so that LowerReturn won't try to load return
1230 // registers the usual way.
1231 SmallVector<EVT, 1> PtrValueVTs;
1232 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1235 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1236 SDValue RetOp = getValue(I.getOperand(0));
1238 SmallVector<EVT, 4> ValueVTs;
1239 SmallVector<uint64_t, 4> Offsets;
1240 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1241 unsigned NumValues = ValueVTs.size();
1243 SmallVector<SDValue, 4> Chains(NumValues);
1244 for (unsigned i = 0; i != NumValues; ++i) {
1245 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1246 RetPtr.getValueType(), RetPtr,
1247 DAG.getIntPtrConstant(Offsets[i]));
1249 DAG.getStore(Chain, getCurSDLoc(),
1250 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1251 // FIXME: better loc info would be nice.
1252 Add, MachinePointerInfo(), false, false, 0);
1255 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1256 MVT::Other, Chains);
1257 } else if (I.getNumOperands() != 0) {
1258 SmallVector<EVT, 4> ValueVTs;
1259 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1260 unsigned NumValues = ValueVTs.size();
1262 SDValue RetOp = getValue(I.getOperand(0));
1264 const Function *F = I.getParent()->getParent();
1266 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1267 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1269 ExtendKind = ISD::SIGN_EXTEND;
1270 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1272 ExtendKind = ISD::ZERO_EXTEND;
1274 LLVMContext &Context = F->getContext();
1275 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1278 for (unsigned j = 0; j != NumValues; ++j) {
1279 EVT VT = ValueVTs[j];
1281 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1282 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1284 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1285 MVT PartVT = TLI.getRegisterType(Context, VT);
1286 SmallVector<SDValue, 4> Parts(NumParts);
1287 getCopyToParts(DAG, getCurSDLoc(),
1288 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1289 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1291 // 'inreg' on function refers to return value
1292 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1296 // Propagate extension type if any
1297 if (ExtendKind == ISD::SIGN_EXTEND)
1299 else if (ExtendKind == ISD::ZERO_EXTEND)
1302 for (unsigned i = 0; i < NumParts; ++i) {
1303 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1304 VT, /*isfixed=*/true, 0, 0));
1305 OutVals.push_back(Parts[i]);
1311 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1312 CallingConv::ID CallConv =
1313 DAG.getMachineFunction().getFunction()->getCallingConv();
1314 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1315 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1317 // Verify that the target's LowerReturn behaved as expected.
1318 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1319 "LowerReturn didn't return a valid chain!");
1321 // Update the DAG with the new chain value resulting from return lowering.
1325 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1326 /// created for it, emit nodes to copy the value into the virtual
1328 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1330 if (V->getType()->isEmptyTy())
1333 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1334 if (VMI != FuncInfo.ValueMap.end()) {
1335 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1336 CopyValueToVirtualRegister(V, VMI->second);
1340 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1341 /// the current basic block, add it to ValueMap now so that we'll get a
1343 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1344 // No need to export constants.
1345 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1347 // Already exported?
1348 if (FuncInfo.isExportedInst(V)) return;
1350 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1351 CopyValueToVirtualRegister(V, Reg);
1354 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1355 const BasicBlock *FromBB) {
1356 // The operands of the setcc have to be in this block. We don't know
1357 // how to export them from some other block.
1358 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1359 // Can export from current BB.
1360 if (VI->getParent() == FromBB)
1363 // Is already exported, noop.
1364 return FuncInfo.isExportedInst(V);
1367 // If this is an argument, we can export it if the BB is the entry block or
1368 // if it is already exported.
1369 if (isa<Argument>(V)) {
1370 if (FromBB == &FromBB->getParent()->getEntryBlock())
1373 // Otherwise, can only export this if it is already exported.
1374 return FuncInfo.isExportedInst(V);
1377 // Otherwise, constants can always be exported.
1381 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1382 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1383 const MachineBasicBlock *Dst) const {
1384 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1387 const BasicBlock *SrcBB = Src->getBasicBlock();
1388 const BasicBlock *DstBB = Dst->getBasicBlock();
1389 return BPI->getEdgeWeight(SrcBB, DstBB);
1392 void SelectionDAGBuilder::
1393 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1394 uint32_t Weight /* = 0 */) {
1396 Weight = getEdgeWeight(Src, Dst);
1397 Src->addSuccessor(Dst, Weight);
1401 static bool InBlock(const Value *V, const BasicBlock *BB) {
1402 if (const Instruction *I = dyn_cast<Instruction>(V))
1403 return I->getParent() == BB;
1407 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1408 /// This function emits a branch and is used at the leaves of an OR or an
1409 /// AND operator tree.
1412 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1413 MachineBasicBlock *TBB,
1414 MachineBasicBlock *FBB,
1415 MachineBasicBlock *CurBB,
1416 MachineBasicBlock *SwitchBB,
1419 const BasicBlock *BB = CurBB->getBasicBlock();
1421 // If the leaf of the tree is a comparison, merge the condition into
1423 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1424 // The operands of the cmp have to be in this block. We don't know
1425 // how to export them from some other block. If this is the first block
1426 // of the sequence, no exporting is needed.
1427 if (CurBB == SwitchBB ||
1428 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1429 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1430 ISD::CondCode Condition;
1431 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1432 Condition = getICmpCondCode(IC->getPredicate());
1433 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1434 Condition = getFCmpCondCode(FC->getPredicate());
1435 if (TM.Options.NoNaNsFPMath)
1436 Condition = getFCmpCodeWithoutNaN(Condition);
1438 (void)Condition; // silence warning.
1439 llvm_unreachable("Unknown compare instruction");
1442 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1443 TBB, FBB, CurBB, TWeight, FWeight);
1444 SwitchCases.push_back(CB);
1449 // Create a CaseBlock record representing this branch.
1450 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1451 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1452 SwitchCases.push_back(CB);
1455 /// Scale down both weights to fit into uint32_t.
1456 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1457 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1458 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1459 NewTrue = NewTrue / Scale;
1460 NewFalse = NewFalse / Scale;
1463 /// FindMergedConditions - If Cond is an expression like
1464 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1465 MachineBasicBlock *TBB,
1466 MachineBasicBlock *FBB,
1467 MachineBasicBlock *CurBB,
1468 MachineBasicBlock *SwitchBB,
1469 unsigned Opc, uint32_t TWeight,
1471 // If this node is not part of the or/and tree, emit it as a branch.
1472 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1473 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1474 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1475 BOp->getParent() != CurBB->getBasicBlock() ||
1476 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1477 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1478 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1483 // Create TmpBB after CurBB.
1484 MachineFunction::iterator BBI = CurBB;
1485 MachineFunction &MF = DAG.getMachineFunction();
1486 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1487 CurBB->getParent()->insert(++BBI, TmpBB);
1489 if (Opc == Instruction::Or) {
1490 // Codegen X | Y as:
1499 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1500 // The requirement is that
1501 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1502 // = TrueProb for orignal BB.
1503 // Assuming the orignal weights are A and B, one choice is to set BB1's
1504 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1506 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1507 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1508 // TmpBB, but the math is more complicated.
1510 uint64_t NewTrueWeight = TWeight;
1511 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1512 ScaleWeights(NewTrueWeight, NewFalseWeight);
1513 // Emit the LHS condition.
1514 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1515 NewTrueWeight, NewFalseWeight);
1517 NewTrueWeight = TWeight;
1518 NewFalseWeight = 2 * (uint64_t)FWeight;
1519 ScaleWeights(NewTrueWeight, NewFalseWeight);
1520 // Emit the RHS condition into TmpBB.
1521 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1522 NewTrueWeight, NewFalseWeight);
1524 assert(Opc == Instruction::And && "Unknown merge op!");
1525 // Codegen X & Y as:
1533 // This requires creation of TmpBB after CurBB.
1535 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1536 // The requirement is that
1537 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1538 // = FalseProb for orignal BB.
1539 // Assuming the orignal weights are A and B, one choice is to set BB1's
1540 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1542 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1544 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1545 uint64_t NewFalseWeight = FWeight;
1546 ScaleWeights(NewTrueWeight, NewFalseWeight);
1547 // Emit the LHS condition.
1548 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1549 NewTrueWeight, NewFalseWeight);
1551 NewTrueWeight = 2 * (uint64_t)TWeight;
1552 NewFalseWeight = FWeight;
1553 ScaleWeights(NewTrueWeight, NewFalseWeight);
1554 // Emit the RHS condition into TmpBB.
1555 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1556 NewTrueWeight, NewFalseWeight);
1560 /// If the set of cases should be emitted as a series of branches, return true.
1561 /// If we should emit this as a bunch of and/or'd together conditions, return
1564 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1565 if (Cases.size() != 2) return true;
1567 // If this is two comparisons of the same values or'd or and'd together, they
1568 // will get folded into a single comparison, so don't emit two blocks.
1569 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1570 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1571 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1572 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1576 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1577 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1578 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1579 Cases[0].CC == Cases[1].CC &&
1580 isa<Constant>(Cases[0].CmpRHS) &&
1581 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1582 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1584 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1591 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1592 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1594 // Update machine-CFG edges.
1595 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1597 if (I.isUnconditional()) {
1598 // Update machine-CFG edges.
1599 BrMBB->addSuccessor(Succ0MBB);
1601 // If this is not a fall-through branch or optimizations are switched off,
1603 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1604 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1605 MVT::Other, getControlRoot(),
1606 DAG.getBasicBlock(Succ0MBB)));
1611 // If this condition is one of the special cases we handle, do special stuff
1613 const Value *CondVal = I.getCondition();
1614 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1616 // If this is a series of conditions that are or'd or and'd together, emit
1617 // this as a sequence of branches instead of setcc's with and/or operations.
1618 // As long as jumps are not expensive, this should improve performance.
1619 // For example, instead of something like:
1632 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1633 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1634 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1635 BOp->getOpcode() == Instruction::Or)) {
1636 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1637 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1638 getEdgeWeight(BrMBB, Succ1MBB));
1639 // If the compares in later blocks need to use values not currently
1640 // exported from this block, export them now. This block should always
1641 // be the first entry.
1642 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1644 // Allow some cases to be rejected.
1645 if (ShouldEmitAsBranches(SwitchCases)) {
1646 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1647 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1648 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1651 // Emit the branch for this block.
1652 visitSwitchCase(SwitchCases[0], BrMBB);
1653 SwitchCases.erase(SwitchCases.begin());
1657 // Okay, we decided not to do this, remove any inserted MBB's and clear
1659 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1660 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1662 SwitchCases.clear();
1666 // Create a CaseBlock record representing this branch.
1667 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1668 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1670 // Use visitSwitchCase to actually insert the fast branch sequence for this
1672 visitSwitchCase(CB, BrMBB);
1675 /// visitSwitchCase - Emits the necessary code to represent a single node in
1676 /// the binary search tree resulting from lowering a switch instruction.
1677 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1678 MachineBasicBlock *SwitchBB) {
1680 SDValue CondLHS = getValue(CB.CmpLHS);
1681 SDLoc dl = getCurSDLoc();
1683 // Build the setcc now.
1685 // Fold "(X == true)" to X and "(X == false)" to !X to
1686 // handle common cases produced by branch lowering.
1687 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1688 CB.CC == ISD::SETEQ)
1690 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1691 CB.CC == ISD::SETEQ) {
1692 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1693 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1695 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1697 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1699 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1700 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1702 SDValue CmpOp = getValue(CB.CmpMHS);
1703 EVT VT = CmpOp.getValueType();
1705 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1706 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1709 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1710 VT, CmpOp, DAG.getConstant(Low, VT));
1711 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1712 DAG.getConstant(High-Low, VT), ISD::SETULE);
1716 // Update successor info
1717 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1718 // TrueBB and FalseBB are always different unless the incoming IR is
1719 // degenerate. This only happens when running llc on weird IR.
1720 if (CB.TrueBB != CB.FalseBB)
1721 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1723 // If the lhs block is the next block, invert the condition so that we can
1724 // fall through to the lhs instead of the rhs block.
1725 if (CB.TrueBB == NextBlock(SwitchBB)) {
1726 std::swap(CB.TrueBB, CB.FalseBB);
1727 SDValue True = DAG.getConstant(1, Cond.getValueType());
1728 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1731 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1732 MVT::Other, getControlRoot(), Cond,
1733 DAG.getBasicBlock(CB.TrueBB));
1735 // Insert the false branch. Do this even if it's a fall through branch,
1736 // this makes it easier to do DAG optimizations which require inverting
1737 // the branch condition.
1738 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1739 DAG.getBasicBlock(CB.FalseBB));
1741 DAG.setRoot(BrCond);
1744 /// visitJumpTable - Emit JumpTable node in the current MBB
1745 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1746 // Emit the code for the jump table
1747 assert(JT.Reg != -1U && "Should lower JT Header first!");
1748 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1749 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1751 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1752 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1753 MVT::Other, Index.getValue(1),
1755 DAG.setRoot(BrJumpTable);
1758 /// visitJumpTableHeader - This function emits necessary code to produce index
1759 /// in the JumpTable from switch case.
1760 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1761 JumpTableHeader &JTH,
1762 MachineBasicBlock *SwitchBB) {
1763 // Subtract the lowest switch case value from the value being switched on and
1764 // conditional branch to default mbb if the result is greater than the
1765 // difference between smallest and largest cases.
1766 SDValue SwitchOp = getValue(JTH.SValue);
1767 EVT VT = SwitchOp.getValueType();
1768 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1769 DAG.getConstant(JTH.First, VT));
1771 // The SDNode we just created, which holds the value being switched on minus
1772 // the smallest case value, needs to be copied to a virtual register so it
1773 // can be used as an index into the jump table in a subsequent basic block.
1774 // This value may be smaller or larger than the target's pointer type, and
1775 // therefore require extension or truncating.
1776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1777 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1779 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1780 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1781 JumpTableReg, SwitchOp);
1782 JT.Reg = JumpTableReg;
1784 // Emit the range check for the jump table, and branch to the default block
1785 // for the switch statement if the value being switched on exceeds the largest
1786 // case in the switch.
1788 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1789 Sub.getValueType()),
1790 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1792 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1793 MVT::Other, CopyTo, CMP,
1794 DAG.getBasicBlock(JT.Default));
1796 // Avoid emitting unnecessary branches to the next block.
1797 if (JT.MBB != NextBlock(SwitchBB))
1798 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1799 DAG.getBasicBlock(JT.MBB));
1801 DAG.setRoot(BrCond);
1804 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1805 /// tail spliced into a stack protector check success bb.
1807 /// For a high level explanation of how this fits into the stack protector
1808 /// generation see the comment on the declaration of class
1809 /// StackProtectorDescriptor.
1810 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1811 MachineBasicBlock *ParentBB) {
1813 // First create the loads to the guard/stack slot for the comparison.
1814 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1815 EVT PtrTy = TLI.getPointerTy();
1817 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1818 int FI = MFI->getStackProtectorIndex();
1820 const Value *IRGuard = SPD.getGuard();
1821 SDValue GuardPtr = getValue(IRGuard);
1822 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1825 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1829 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1830 // guard value from the virtual register holding the value. Otherwise, emit a
1831 // volatile load to retrieve the stack guard value.
1832 unsigned GuardReg = SPD.getGuardReg();
1834 if (GuardReg && TLI.useLoadStackGuardNode())
1835 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1838 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1839 GuardPtr, MachinePointerInfo(IRGuard, 0),
1840 true, false, false, Align);
1842 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1844 MachinePointerInfo::getFixedStack(FI),
1845 true, false, false, Align);
1847 // Perform the comparison via a subtract/getsetcc.
1848 EVT VT = Guard.getValueType();
1849 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1852 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1853 Sub.getValueType()),
1854 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1856 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1857 // branch to failure MBB.
1858 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1859 MVT::Other, StackSlot.getOperand(0),
1860 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1861 // Otherwise branch to success MBB.
1862 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1864 DAG.getBasicBlock(SPD.getSuccessMBB()));
1869 /// Codegen the failure basic block for a stack protector check.
1871 /// A failure stack protector machine basic block consists simply of a call to
1872 /// __stack_chk_fail().
1874 /// For a high level explanation of how this fits into the stack protector
1875 /// generation see the comment on the declaration of class
1876 /// StackProtectorDescriptor.
1878 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1879 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1881 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1882 nullptr, 0, false, getCurSDLoc(), false, false).second;
1886 /// visitBitTestHeader - This function emits necessary code to produce value
1887 /// suitable for "bit tests"
1888 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1889 MachineBasicBlock *SwitchBB) {
1890 // Subtract the minimum value
1891 SDValue SwitchOp = getValue(B.SValue);
1892 EVT VT = SwitchOp.getValueType();
1893 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1894 DAG.getConstant(B.First, VT));
1897 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1899 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1900 Sub.getValueType()),
1901 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1903 // Determine the type of the test operands.
1904 bool UsePtrType = false;
1905 if (!TLI.isTypeLegal(VT))
1908 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1909 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1910 // Switch table case range are encoded into series of masks.
1911 // Just use pointer type, it's guaranteed to fit.
1917 VT = TLI.getPointerTy();
1918 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1921 B.RegVT = VT.getSimpleVT();
1922 B.Reg = FuncInfo.CreateReg(B.RegVT);
1923 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1926 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1928 addSuccessorWithWeight(SwitchBB, B.Default);
1929 addSuccessorWithWeight(SwitchBB, MBB);
1931 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1932 MVT::Other, CopyTo, RangeCmp,
1933 DAG.getBasicBlock(B.Default));
1935 // Avoid emitting unnecessary branches to the next block.
1936 if (MBB != NextBlock(SwitchBB))
1937 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrRange,
1938 DAG.getBasicBlock(MBB));
1940 DAG.setRoot(BrRange);
1943 /// visitBitTestCase - this function produces one "bit test"
1944 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1945 MachineBasicBlock* NextMBB,
1946 uint32_t BranchWeightToNext,
1949 MachineBasicBlock *SwitchBB) {
1951 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1954 unsigned PopCount = countPopulation(B.Mask);
1955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1956 if (PopCount == 1) {
1957 // Testing for a single bit; just compare the shift count with what it
1958 // would need to be to shift a 1 bit in that position.
1960 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1961 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1962 } else if (PopCount == BB.Range) {
1963 // There is only one zero bit in the range, test for it directly.
1965 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1966 DAG.getConstant(countTrailingOnes(B.Mask), VT), ISD::SETNE);
1968 // Make desired shift
1969 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1970 DAG.getConstant(1, VT), ShiftOp);
1972 // Emit bit tests and jumps
1973 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1974 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1975 Cmp = DAG.getSetCC(getCurSDLoc(),
1976 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1977 DAG.getConstant(0, VT), ISD::SETNE);
1980 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1981 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1982 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1983 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1985 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1986 MVT::Other, getControlRoot(),
1987 Cmp, DAG.getBasicBlock(B.TargetBB));
1989 // Avoid emitting unnecessary branches to the next block.
1990 if (NextMBB != NextBlock(SwitchBB))
1991 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1992 DAG.getBasicBlock(NextMBB));
1997 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1998 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2000 // Retrieve successors.
2001 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2002 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2004 const Value *Callee(I.getCalledValue());
2005 const Function *Fn = dyn_cast<Function>(Callee);
2006 if (isa<InlineAsm>(Callee))
2008 else if (Fn && Fn->isIntrinsic()) {
2009 switch (Fn->getIntrinsicID()) {
2011 llvm_unreachable("Cannot invoke this intrinsic");
2012 case Intrinsic::donothing:
2013 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2015 case Intrinsic::experimental_patchpoint_void:
2016 case Intrinsic::experimental_patchpoint_i64:
2017 visitPatchpoint(&I, LandingPad);
2019 case Intrinsic::experimental_gc_statepoint:
2020 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
2024 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2026 // If the value of the invoke is used outside of its defining block, make it
2027 // available as a virtual register.
2028 // We already took care of the exported value for the statepoint instruction
2029 // during call to the LowerStatepoint.
2030 if (!isStatepoint(I)) {
2031 CopyToExportRegsIfNeeded(&I);
2034 // Update successor info
2035 addSuccessorWithWeight(InvokeMBB, Return);
2036 addSuccessorWithWeight(InvokeMBB, LandingPad);
2038 // Drop into normal successor.
2039 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2040 MVT::Other, getControlRoot(),
2041 DAG.getBasicBlock(Return)));
2044 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2045 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2048 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2049 assert(FuncInfo.MBB->isLandingPad() &&
2050 "Call to landingpad not in landing pad!");
2052 MachineBasicBlock *MBB = FuncInfo.MBB;
2053 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2054 AddLandingPadInfo(LP, MMI, MBB);
2056 // If there aren't registers to copy the values into (e.g., during SjLj
2057 // exceptions), then don't bother to create these DAG nodes.
2058 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2059 if (TLI.getExceptionPointerRegister() == 0 &&
2060 TLI.getExceptionSelectorRegister() == 0)
2063 SmallVector<EVT, 2> ValueVTs;
2064 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2065 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2067 // Get the two live-in registers as SDValues. The physregs have already been
2068 // copied into virtual registers.
2070 if (FuncInfo.ExceptionPointerVirtReg) {
2071 Ops[0] = DAG.getZExtOrTrunc(
2072 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2073 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2074 getCurSDLoc(), ValueVTs[0]);
2076 Ops[0] = DAG.getConstant(0, TLI.getPointerTy());
2078 Ops[1] = DAG.getZExtOrTrunc(
2079 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2080 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2081 getCurSDLoc(), ValueVTs[1]);
2084 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2085 DAG.getVTList(ValueVTs), Ops);
2090 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2091 MachineBasicBlock *LPadBB) {
2092 SDValue Chain = getControlRoot();
2094 // Get the typeid that we will dispatch on later.
2095 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2096 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2097 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2098 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2099 SDValue Sel = DAG.getConstant(TypeID, TLI.getPointerTy());
2100 Chain = DAG.getCopyToReg(Chain, getCurSDLoc(), VReg, Sel);
2102 // Branch to the main landing pad block.
2103 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2104 ClauseMBB->addSuccessor(LPadBB);
2105 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain,
2106 DAG.getBasicBlock(LPadBB)));
2110 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2112 for (const CaseCluster &CC : Clusters)
2113 assert(CC.Low == CC.High && "Input clusters must be single-case");
2116 std::sort(Clusters.begin(), Clusters.end(),
2117 [](const CaseCluster &a, const CaseCluster &b) {
2118 return a.Low->getValue().slt(b.Low->getValue());
2121 // Merge adjacent clusters with the same destination.
2122 const unsigned N = Clusters.size();
2123 unsigned DstIndex = 0;
2124 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2125 CaseCluster &CC = Clusters[SrcIndex];
2126 const ConstantInt *CaseVal = CC.Low;
2127 MachineBasicBlock *Succ = CC.MBB;
2129 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2130 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2131 // If this case has the same successor and is a neighbour, merge it into
2132 // the previous cluster.
2133 Clusters[DstIndex - 1].High = CaseVal;
2134 Clusters[DstIndex - 1].Weight += CC.Weight;
2135 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2137 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2138 sizeof(Clusters[SrcIndex]));
2141 Clusters.resize(DstIndex);
2144 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2145 MachineBasicBlock *Last) {
2147 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2148 if (JTCases[i].first.HeaderBB == First)
2149 JTCases[i].first.HeaderBB = Last;
2151 // Update BitTestCases.
2152 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2153 if (BitTestCases[i].Parent == First)
2154 BitTestCases[i].Parent = Last;
2157 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2158 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2160 // Update machine-CFG edges with unique successors.
2161 SmallSet<BasicBlock*, 32> Done;
2162 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2163 BasicBlock *BB = I.getSuccessor(i);
2164 bool Inserted = Done.insert(BB).second;
2168 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2169 addSuccessorWithWeight(IndirectBrMBB, Succ);
2172 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2173 MVT::Other, getControlRoot(),
2174 getValue(I.getAddress())));
2177 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2178 if (DAG.getTarget().Options.TrapUnreachable)
2179 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2182 void SelectionDAGBuilder::visitFSub(const User &I) {
2183 // -0.0 - X --> fneg
2184 Type *Ty = I.getType();
2185 if (isa<Constant>(I.getOperand(0)) &&
2186 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2187 SDValue Op2 = getValue(I.getOperand(1));
2188 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2189 Op2.getValueType(), Op2));
2193 visitBinary(I, ISD::FSUB);
2196 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2197 SDValue Op1 = getValue(I.getOperand(0));
2198 SDValue Op2 = getValue(I.getOperand(1));
2203 if (const OverflowingBinaryOperator *OFBinOp =
2204 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2205 nuw = OFBinOp->hasNoUnsignedWrap();
2206 nsw = OFBinOp->hasNoSignedWrap();
2208 if (const PossiblyExactOperator *ExactOp =
2209 dyn_cast<const PossiblyExactOperator>(&I))
2210 exact = ExactOp->isExact();
2212 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2213 Op1, Op2, nuw, nsw, exact);
2214 setValue(&I, BinNodeValue);
2217 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2218 SDValue Op1 = getValue(I.getOperand(0));
2219 SDValue Op2 = getValue(I.getOperand(1));
2222 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2224 // Coerce the shift amount to the right type if we can.
2225 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2226 unsigned ShiftSize = ShiftTy.getSizeInBits();
2227 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2228 SDLoc DL = getCurSDLoc();
2230 // If the operand is smaller than the shift count type, promote it.
2231 if (ShiftSize > Op2Size)
2232 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2234 // If the operand is larger than the shift count type but the shift
2235 // count type has enough bits to represent any shift value, truncate
2236 // it now. This is a common case and it exposes the truncate to
2237 // optimization early.
2238 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2239 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2240 // Otherwise we'll need to temporarily settle for some other convenient
2241 // type. Type legalization will make adjustments once the shiftee is split.
2243 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2250 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2252 if (const OverflowingBinaryOperator *OFBinOp =
2253 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2254 nuw = OFBinOp->hasNoUnsignedWrap();
2255 nsw = OFBinOp->hasNoSignedWrap();
2257 if (const PossiblyExactOperator *ExactOp =
2258 dyn_cast<const PossiblyExactOperator>(&I))
2259 exact = ExactOp->isExact();
2262 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2267 void SelectionDAGBuilder::visitSDiv(const User &I) {
2268 SDValue Op1 = getValue(I.getOperand(0));
2269 SDValue Op2 = getValue(I.getOperand(1));
2271 // Turn exact SDivs into multiplications.
2272 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2274 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2275 !isa<ConstantSDNode>(Op1) &&
2276 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2277 setValue(&I, DAG.getTargetLoweringInfo()
2278 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2280 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2284 void SelectionDAGBuilder::visitICmp(const User &I) {
2285 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2286 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2287 predicate = IC->getPredicate();
2288 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2289 predicate = ICmpInst::Predicate(IC->getPredicate());
2290 SDValue Op1 = getValue(I.getOperand(0));
2291 SDValue Op2 = getValue(I.getOperand(1));
2292 ISD::CondCode Opcode = getICmpCondCode(predicate);
2294 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2295 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2298 void SelectionDAGBuilder::visitFCmp(const User &I) {
2299 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2300 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2301 predicate = FC->getPredicate();
2302 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2303 predicate = FCmpInst::Predicate(FC->getPredicate());
2304 SDValue Op1 = getValue(I.getOperand(0));
2305 SDValue Op2 = getValue(I.getOperand(1));
2306 ISD::CondCode Condition = getFCmpCondCode(predicate);
2307 if (TM.Options.NoNaNsFPMath)
2308 Condition = getFCmpCodeWithoutNaN(Condition);
2309 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2310 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2313 void SelectionDAGBuilder::visitSelect(const User &I) {
2314 SmallVector<EVT, 4> ValueVTs;
2315 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2316 unsigned NumValues = ValueVTs.size();
2317 if (NumValues == 0) return;
2319 SmallVector<SDValue, 4> Values(NumValues);
2320 SDValue Cond = getValue(I.getOperand(0));
2321 SDValue TrueVal = getValue(I.getOperand(1));
2322 SDValue FalseVal = getValue(I.getOperand(2));
2323 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2324 ISD::VSELECT : ISD::SELECT;
2326 for (unsigned i = 0; i != NumValues; ++i)
2327 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2328 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2330 SDValue(TrueVal.getNode(),
2331 TrueVal.getResNo() + i),
2332 SDValue(FalseVal.getNode(),
2333 FalseVal.getResNo() + i));
2335 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2336 DAG.getVTList(ValueVTs), Values));
2339 void SelectionDAGBuilder::visitTrunc(const User &I) {
2340 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2341 SDValue N = getValue(I.getOperand(0));
2342 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2343 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2346 void SelectionDAGBuilder::visitZExt(const User &I) {
2347 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2348 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2349 SDValue N = getValue(I.getOperand(0));
2350 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2351 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2354 void SelectionDAGBuilder::visitSExt(const User &I) {
2355 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2356 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2357 SDValue N = getValue(I.getOperand(0));
2358 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2359 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2362 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2363 // FPTrunc is never a no-op cast, no need to check
2364 SDValue N = getValue(I.getOperand(0));
2365 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2366 EVT DestVT = TLI.getValueType(I.getType());
2367 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
2368 DAG.getTargetConstant(0, TLI.getPointerTy())));
2371 void SelectionDAGBuilder::visitFPExt(const User &I) {
2372 // FPExt is never a no-op cast, no need to check
2373 SDValue N = getValue(I.getOperand(0));
2374 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2375 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2378 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2379 // FPToUI is never a no-op cast, no need to check
2380 SDValue N = getValue(I.getOperand(0));
2381 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2382 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2385 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2386 // FPToSI is never a no-op cast, no need to check
2387 SDValue N = getValue(I.getOperand(0));
2388 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2389 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2392 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2393 // UIToFP is never a no-op cast, no need to check
2394 SDValue N = getValue(I.getOperand(0));
2395 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2396 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2399 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2400 // SIToFP is never a no-op cast, no need to check
2401 SDValue N = getValue(I.getOperand(0));
2402 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2403 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2406 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2407 // What to do depends on the size of the integer and the size of the pointer.
2408 // We can either truncate, zero extend, or no-op, accordingly.
2409 SDValue N = getValue(I.getOperand(0));
2410 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2411 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2414 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2415 // What to do depends on the size of the integer and the size of the pointer.
2416 // We can either truncate, zero extend, or no-op, accordingly.
2417 SDValue N = getValue(I.getOperand(0));
2418 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2419 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2422 void SelectionDAGBuilder::visitBitCast(const User &I) {
2423 SDValue N = getValue(I.getOperand(0));
2424 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2426 // BitCast assures us that source and destination are the same size so this is
2427 // either a BITCAST or a no-op.
2428 if (DestVT != N.getValueType())
2429 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
2430 DestVT, N)); // convert types.
2431 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2432 // might fold any kind of constant expression to an integer constant and that
2433 // is not what we are looking for. Only regcognize a bitcast of a genuine
2434 // constant integer as an opaque constant.
2435 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2436 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
2439 setValue(&I, N); // noop cast.
2442 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2443 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2444 const Value *SV = I.getOperand(0);
2445 SDValue N = getValue(SV);
2446 EVT DestVT = TLI.getValueType(I.getType());
2448 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2449 unsigned DestAS = I.getType()->getPointerAddressSpace();
2451 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2452 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2457 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2458 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2459 SDValue InVec = getValue(I.getOperand(0));
2460 SDValue InVal = getValue(I.getOperand(1));
2461 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
2462 getCurSDLoc(), TLI.getVectorIdxTy());
2463 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2464 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
2467 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2468 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2469 SDValue InVec = getValue(I.getOperand(0));
2470 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
2471 getCurSDLoc(), TLI.getVectorIdxTy());
2472 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2473 TLI.getValueType(I.getType()), InVec, InIdx));
2476 // Utility for visitShuffleVector - Return true if every element in Mask,
2477 // beginning from position Pos and ending in Pos+Size, falls within the
2478 // specified sequential range [L, L+Pos). or is undef.
2479 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2480 unsigned Pos, unsigned Size, int Low) {
2481 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2482 if (Mask[i] >= 0 && Mask[i] != Low)
2487 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2488 SDValue Src1 = getValue(I.getOperand(0));
2489 SDValue Src2 = getValue(I.getOperand(1));
2491 SmallVector<int, 8> Mask;
2492 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2493 unsigned MaskNumElts = Mask.size();
2495 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2496 EVT VT = TLI.getValueType(I.getType());
2497 EVT SrcVT = Src1.getValueType();
2498 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2500 if (SrcNumElts == MaskNumElts) {
2501 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2506 // Normalize the shuffle vector since mask and vector length don't match.
2507 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2508 // Mask is longer than the source vectors and is a multiple of the source
2509 // vectors. We can use concatenate vector to make the mask and vectors
2511 if (SrcNumElts*2 == MaskNumElts) {
2512 // First check for Src1 in low and Src2 in high
2513 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2514 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2515 // The shuffle is concatenating two vectors together.
2516 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2520 // Then check for Src2 in low and Src1 in high
2521 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2522 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2523 // The shuffle is concatenating two vectors together.
2524 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2530 // Pad both vectors with undefs to make them the same length as the mask.
2531 unsigned NumConcat = MaskNumElts / SrcNumElts;
2532 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2533 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2534 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2536 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2537 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2541 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2542 getCurSDLoc(), VT, MOps1);
2543 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2544 getCurSDLoc(), VT, MOps2);
2546 // Readjust mask for new input vector length.
2547 SmallVector<int, 8> MappedOps;
2548 for (unsigned i = 0; i != MaskNumElts; ++i) {
2550 if (Idx >= (int)SrcNumElts)
2551 Idx -= SrcNumElts - MaskNumElts;
2552 MappedOps.push_back(Idx);
2555 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2560 if (SrcNumElts > MaskNumElts) {
2561 // Analyze the access pattern of the vector to see if we can extract
2562 // two subvectors and do the shuffle. The analysis is done by calculating
2563 // the range of elements the mask access on both vectors.
2564 int MinRange[2] = { static_cast<int>(SrcNumElts),
2565 static_cast<int>(SrcNumElts)};
2566 int MaxRange[2] = {-1, -1};
2568 for (unsigned i = 0; i != MaskNumElts; ++i) {
2574 if (Idx >= (int)SrcNumElts) {
2578 if (Idx > MaxRange[Input])
2579 MaxRange[Input] = Idx;
2580 if (Idx < MinRange[Input])
2581 MinRange[Input] = Idx;
2584 // Check if the access is smaller than the vector size and can we find
2585 // a reasonable extract index.
2586 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2588 int StartIdx[2]; // StartIdx to extract from
2589 for (unsigned Input = 0; Input < 2; ++Input) {
2590 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2591 RangeUse[Input] = 0; // Unused
2592 StartIdx[Input] = 0;
2596 // Find a good start index that is a multiple of the mask length. Then
2597 // see if the rest of the elements are in range.
2598 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2599 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2600 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2601 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2604 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2605 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2608 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2609 // Extract appropriate subvector and generate a vector shuffle
2610 for (unsigned Input = 0; Input < 2; ++Input) {
2611 SDValue &Src = Input == 0 ? Src1 : Src2;
2612 if (RangeUse[Input] == 0)
2613 Src = DAG.getUNDEF(VT);
2616 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
2617 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
2620 // Calculate new mask.
2621 SmallVector<int, 8> MappedOps;
2622 for (unsigned i = 0; i != MaskNumElts; ++i) {
2625 if (Idx < (int)SrcNumElts)
2628 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2630 MappedOps.push_back(Idx);
2633 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2639 // We can't use either concat vectors or extract subvectors so fall back to
2640 // replacing the shuffle with extract and build vector.
2641 // to insert and build vector.
2642 EVT EltVT = VT.getVectorElementType();
2643 EVT IdxVT = TLI.getVectorIdxTy();
2644 SmallVector<SDValue,8> Ops;
2645 for (unsigned i = 0; i != MaskNumElts; ++i) {
2650 Res = DAG.getUNDEF(EltVT);
2652 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2653 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2655 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2656 EltVT, Src, DAG.getConstant(Idx, IdxVT));
2662 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
2665 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2666 const Value *Op0 = I.getOperand(0);
2667 const Value *Op1 = I.getOperand(1);
2668 Type *AggTy = I.getType();
2669 Type *ValTy = Op1->getType();
2670 bool IntoUndef = isa<UndefValue>(Op0);
2671 bool FromUndef = isa<UndefValue>(Op1);
2673 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2675 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2676 SmallVector<EVT, 4> AggValueVTs;
2677 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2678 SmallVector<EVT, 4> ValValueVTs;
2679 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2681 unsigned NumAggValues = AggValueVTs.size();
2682 unsigned NumValValues = ValValueVTs.size();
2683 SmallVector<SDValue, 4> Values(NumAggValues);
2685 // Ignore an insertvalue that produces an empty object
2686 if (!NumAggValues) {
2687 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2691 SDValue Agg = getValue(Op0);
2693 // Copy the beginning value(s) from the original aggregate.
2694 for (; i != LinearIndex; ++i)
2695 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2696 SDValue(Agg.getNode(), Agg.getResNo() + i);
2697 // Copy values from the inserted value(s).
2699 SDValue Val = getValue(Op1);
2700 for (; i != LinearIndex + NumValValues; ++i)
2701 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2702 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2704 // Copy remaining value(s) from the original aggregate.
2705 for (; i != NumAggValues; ++i)
2706 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2707 SDValue(Agg.getNode(), Agg.getResNo() + i);
2709 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2710 DAG.getVTList(AggValueVTs), Values));
2713 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2714 const Value *Op0 = I.getOperand(0);
2715 Type *AggTy = Op0->getType();
2716 Type *ValTy = I.getType();
2717 bool OutOfUndef = isa<UndefValue>(Op0);
2719 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2721 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2722 SmallVector<EVT, 4> ValValueVTs;
2723 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2725 unsigned NumValValues = ValValueVTs.size();
2727 // Ignore a extractvalue that produces an empty object
2728 if (!NumValValues) {
2729 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2733 SmallVector<SDValue, 4> Values(NumValValues);
2735 SDValue Agg = getValue(Op0);
2736 // Copy out the selected value(s).
2737 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2738 Values[i - LinearIndex] =
2740 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2741 SDValue(Agg.getNode(), Agg.getResNo() + i);
2743 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2744 DAG.getVTList(ValValueVTs), Values));
2747 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2748 Value *Op0 = I.getOperand(0);
2749 // Note that the pointer operand may be a vector of pointers. Take the scalar
2750 // element which holds a pointer.
2751 Type *Ty = Op0->getType()->getScalarType();
2752 unsigned AS = Ty->getPointerAddressSpace();
2753 SDValue N = getValue(Op0);
2755 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2757 const Value *Idx = *OI;
2758 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2759 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2762 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2763 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
2764 DAG.getConstant(Offset, N.getValueType()));
2767 Ty = StTy->getElementType(Field);
2769 Ty = cast<SequentialType>(Ty)->getElementType();
2770 MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
2771 unsigned PtrSize = PtrTy.getSizeInBits();
2772 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2774 // If this is a constant subscript, handle it quickly.
2775 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
2778 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2779 SDValue OffsVal = DAG.getConstant(Offs, PtrTy);
2780 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, OffsVal);
2784 // N = N + Idx * ElementSize;
2785 SDValue IdxN = getValue(Idx);
2787 // If the index is smaller or larger than intptr_t, truncate or extend
2789 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
2791 // If this is a multiply by a power of two, turn it into a shl
2792 // immediately. This is a very common case.
2793 if (ElementSize != 1) {
2794 if (ElementSize.isPowerOf2()) {
2795 unsigned Amt = ElementSize.logBase2();
2796 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
2797 N.getValueType(), IdxN,
2798 DAG.getConstant(Amt, IdxN.getValueType()));
2800 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
2801 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
2802 N.getValueType(), IdxN, Scale);
2806 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
2807 N.getValueType(), N, IdxN);
2814 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2815 // If this is a fixed sized alloca in the entry block of the function,
2816 // allocate it statically on the stack.
2817 if (FuncInfo.StaticAllocaMap.count(&I))
2818 return; // getValue will auto-populate this.
2820 Type *Ty = I.getAllocatedType();
2821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2822 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
2824 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
2827 SDValue AllocSize = getValue(I.getArraySize());
2829 EVT IntPtr = TLI.getPointerTy();
2830 if (AllocSize.getValueType() != IntPtr)
2831 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
2833 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
2835 DAG.getConstant(TySize, IntPtr));
2837 // Handle alignment. If the requested alignment is less than or equal to
2838 // the stack alignment, ignore it. If the size is greater than or equal to
2839 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2840 unsigned StackAlign =
2841 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2842 if (Align <= StackAlign)
2845 // Round the size of the allocation up to the stack alignment size
2846 // by add SA-1 to the size.
2847 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
2848 AllocSize.getValueType(), AllocSize,
2849 DAG.getIntPtrConstant(StackAlign-1));
2851 // Mask out the low bits for alignment purposes.
2852 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
2853 AllocSize.getValueType(), AllocSize,
2854 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2856 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2857 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2858 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
2860 DAG.setRoot(DSA.getValue(1));
2862 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2865 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2867 return visitAtomicLoad(I);
2869 const Value *SV = I.getOperand(0);
2870 SDValue Ptr = getValue(SV);
2872 Type *Ty = I.getType();
2874 bool isVolatile = I.isVolatile();
2875 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2876 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
2877 unsigned Alignment = I.getAlignment();
2880 I.getAAMetadata(AAInfo);
2881 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2883 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2884 SmallVector<EVT, 4> ValueVTs;
2885 SmallVector<uint64_t, 4> Offsets;
2886 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2887 unsigned NumValues = ValueVTs.size();
2892 bool ConstantMemory = false;
2893 if (isVolatile || NumValues > MaxParallelChains)
2894 // Serialize volatile loads with other side effects.
2896 else if (AA->pointsToConstantMemory(
2897 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
2898 // Do not serialize (non-volatile) loads of constant memory with anything.
2899 Root = DAG.getEntryNode();
2900 ConstantMemory = true;
2902 // Do not serialize non-volatile loads against each other.
2903 Root = DAG.getRoot();
2907 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
2909 SmallVector<SDValue, 4> Values(NumValues);
2910 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2912 EVT PtrVT = Ptr.getValueType();
2913 unsigned ChainI = 0;
2914 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2915 // Serializing loads here may result in excessive register pressure, and
2916 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2917 // could recover a bit by hoisting nodes upward in the chain by recognizing
2918 // they are side-effect free or do not alias. The optimizer should really
2919 // avoid this case by converting large object/array copies to llvm.memcpy
2920 // (MaxParallelChains should always remain as failsafe).
2921 if (ChainI == MaxParallelChains) {
2922 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2923 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
2924 makeArrayRef(Chains.data(), ChainI));
2928 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
2930 DAG.getConstant(Offsets[i], PtrVT));
2931 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
2932 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
2933 isNonTemporal, isInvariant, Alignment, AAInfo,
2937 Chains[ChainI] = L.getValue(1);
2940 if (!ConstantMemory) {
2941 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
2942 makeArrayRef(Chains.data(), ChainI));
2946 PendingLoads.push_back(Chain);
2949 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2950 DAG.getVTList(ValueVTs), Values));
2953 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2955 return visitAtomicStore(I);
2957 const Value *SrcV = I.getOperand(0);
2958 const Value *PtrV = I.getOperand(1);
2960 SmallVector<EVT, 4> ValueVTs;
2961 SmallVector<uint64_t, 4> Offsets;
2962 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
2963 ValueVTs, &Offsets);
2964 unsigned NumValues = ValueVTs.size();
2968 // Get the lowered operands. Note that we do this after
2969 // checking if NumResults is zero, because with zero results
2970 // the operands won't have values in the map.
2971 SDValue Src = getValue(SrcV);
2972 SDValue Ptr = getValue(PtrV);
2974 SDValue Root = getRoot();
2975 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2977 EVT PtrVT = Ptr.getValueType();
2978 bool isVolatile = I.isVolatile();
2979 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2980 unsigned Alignment = I.getAlignment();
2983 I.getAAMetadata(AAInfo);
2985 unsigned ChainI = 0;
2986 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2987 // See visitLoad comments.
2988 if (ChainI == MaxParallelChains) {
2989 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
2990 makeArrayRef(Chains.data(), ChainI));
2994 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
2995 DAG.getConstant(Offsets[i], PtrVT));
2996 SDValue St = DAG.getStore(Root, getCurSDLoc(),
2997 SDValue(Src.getNode(), Src.getResNo() + i),
2998 Add, MachinePointerInfo(PtrV, Offsets[i]),
2999 isVolatile, isNonTemporal, Alignment, AAInfo);
3000 Chains[ChainI] = St;
3003 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3004 makeArrayRef(Chains.data(), ChainI));
3005 DAG.setRoot(StoreNode);
3008 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3009 SDLoc sdl = getCurSDLoc();
3011 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3012 Value *PtrOperand = I.getArgOperand(1);
3013 SDValue Ptr = getValue(PtrOperand);
3014 SDValue Src0 = getValue(I.getArgOperand(0));
3015 SDValue Mask = getValue(I.getArgOperand(3));
3016 EVT VT = Src0.getValueType();
3017 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3019 Alignment = DAG.getEVTAlignment(VT);
3022 I.getAAMetadata(AAInfo);
3024 MachineMemOperand *MMO =
3025 DAG.getMachineFunction().
3026 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3027 MachineMemOperand::MOStore, VT.getStoreSize(),
3029 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3031 DAG.setRoot(StoreNode);
3032 setValue(&I, StoreNode);
3035 // Gather/scatter receive a vector of pointers.
3036 // This vector of pointers may be represented as a base pointer + vector of
3037 // indices, it depends on GEP and instruction preceeding GEP
3038 // that calculates indices
3039 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3040 SelectionDAGBuilder* SDB) {
3042 assert (Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3043 GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(Ptr);
3044 if (!Gep || Gep->getNumOperands() > 2)
3046 ShuffleVectorInst *ShuffleInst =
3047 dyn_cast<ShuffleVectorInst>(Gep->getPointerOperand());
3048 if (!ShuffleInst || !ShuffleInst->getMask()->isNullValue() ||
3049 cast<Instruction>(ShuffleInst->getOperand(0))->getOpcode() !=
3050 Instruction::InsertElement)
3053 Ptr = cast<InsertElementInst>(ShuffleInst->getOperand(0))->getOperand(1);
3055 SelectionDAG& DAG = SDB->DAG;
3056 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3057 // Check is the Ptr is inside current basic block
3058 // If not, look for the shuffle instruction
3059 if (SDB->findValue(Ptr))
3060 Base = SDB->getValue(Ptr);
3061 else if (SDB->findValue(ShuffleInst)) {
3062 SDValue ShuffleNode = SDB->getValue(ShuffleInst);
3063 Base = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(ShuffleNode),
3064 ShuffleNode.getValueType().getScalarType(), ShuffleNode,
3065 DAG.getConstant(0, TLI.getVectorIdxTy()));
3066 SDB->setValue(Ptr, Base);
3071 Value *IndexVal = Gep->getOperand(1);
3072 if (SDB->findValue(IndexVal)) {
3073 Index = SDB->getValue(IndexVal);
3075 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3076 IndexVal = Sext->getOperand(0);
3077 if (SDB->findValue(IndexVal))
3078 Index = SDB->getValue(IndexVal);
3085 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3086 SDLoc sdl = getCurSDLoc();
3088 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3089 Value *Ptr = I.getArgOperand(1);
3090 SDValue Src0 = getValue(I.getArgOperand(0));
3091 SDValue Mask = getValue(I.getArgOperand(3));
3092 EVT VT = Src0.getValueType();
3093 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3095 Alignment = DAG.getEVTAlignment(VT);
3096 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3099 I.getAAMetadata(AAInfo);
3103 Value *BasePtr = Ptr;
3104 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3106 Value *MemOpBasePtr = UniformBase ? BasePtr : NULL;
3107 MachineMemOperand *MMO = DAG.getMachineFunction().
3108 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3109 MachineMemOperand::MOStore, VT.getStoreSize(),
3112 Base = DAG.getTargetConstant(0, TLI.getPointerTy());
3113 Index = getValue(Ptr);
3115 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3116 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl, Ops, MMO);
3117 DAG.setRoot(Scatter);
3118 setValue(&I, Scatter);
3121 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3122 SDLoc sdl = getCurSDLoc();
3124 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3125 Value *PtrOperand = I.getArgOperand(0);
3126 SDValue Ptr = getValue(PtrOperand);
3127 SDValue Src0 = getValue(I.getArgOperand(3));
3128 SDValue Mask = getValue(I.getArgOperand(2));
3130 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3131 EVT VT = TLI.getValueType(I.getType());
3132 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3134 Alignment = DAG.getEVTAlignment(VT);
3137 I.getAAMetadata(AAInfo);
3138 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3140 SDValue InChain = DAG.getRoot();
3141 if (AA->pointsToConstantMemory(
3142 AliasAnalysis::Location(PtrOperand,
3143 AA->getTypeStoreSize(I.getType()),
3145 // Do not serialize (non-volatile) loads of constant memory with anything.
3146 InChain = DAG.getEntryNode();
3149 MachineMemOperand *MMO =
3150 DAG.getMachineFunction().
3151 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3152 MachineMemOperand::MOLoad, VT.getStoreSize(),
3153 Alignment, AAInfo, Ranges);
3155 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3157 SDValue OutChain = Load.getValue(1);
3158 DAG.setRoot(OutChain);
3162 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3163 SDLoc sdl = getCurSDLoc();
3165 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3166 Value *Ptr = I.getArgOperand(0);
3167 SDValue Src0 = getValue(I.getArgOperand(3));
3168 SDValue Mask = getValue(I.getArgOperand(2));
3170 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3171 EVT VT = TLI.getValueType(I.getType());
3172 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3174 Alignment = DAG.getEVTAlignment(VT);
3177 I.getAAMetadata(AAInfo);
3178 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3180 SDValue Root = DAG.getRoot();
3183 Value *BasePtr = Ptr;
3184 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3185 bool ConstantMemory = false;
3186 if (UniformBase && AA->pointsToConstantMemory(
3187 AliasAnalysis::Location(BasePtr,
3188 AA->getTypeStoreSize(I.getType()),
3190 // Do not serialize (non-volatile) loads of constant memory with anything.
3191 Root = DAG.getEntryNode();
3192 ConstantMemory = true;
3195 MachineMemOperand *MMO =
3196 DAG.getMachineFunction().
3197 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : NULL),
3198 MachineMemOperand::MOLoad, VT.getStoreSize(),
3199 Alignment, AAInfo, Ranges);
3202 Base = DAG.getTargetConstant(0, TLI.getPointerTy());
3203 Index = getValue(Ptr);
3206 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3207 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3210 SDValue OutChain = Gather.getValue(1);
3211 if (!ConstantMemory)
3212 PendingLoads.push_back(OutChain);
3213 setValue(&I, Gather);
3216 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3217 SDLoc dl = getCurSDLoc();
3218 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3219 AtomicOrdering FailureOrder = I.getFailureOrdering();
3220 SynchronizationScope Scope = I.getSynchScope();
3222 SDValue InChain = getRoot();
3224 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3225 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3226 SDValue L = DAG.getAtomicCmpSwap(
3227 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3228 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3229 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3230 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3232 SDValue OutChain = L.getValue(2);
3235 DAG.setRoot(OutChain);
3238 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3239 SDLoc dl = getCurSDLoc();
3241 switch (I.getOperation()) {
3242 default: llvm_unreachable("Unknown atomicrmw operation");
3243 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3244 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3245 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3246 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3247 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3248 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3249 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3250 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3251 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3252 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3253 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3255 AtomicOrdering Order = I.getOrdering();
3256 SynchronizationScope Scope = I.getSynchScope();
3258 SDValue InChain = getRoot();
3261 DAG.getAtomic(NT, dl,
3262 getValue(I.getValOperand()).getSimpleValueType(),
3264 getValue(I.getPointerOperand()),
3265 getValue(I.getValOperand()),
3266 I.getPointerOperand(),
3267 /* Alignment=*/ 0, Order, Scope);
3269 SDValue OutChain = L.getValue(1);
3272 DAG.setRoot(OutChain);
3275 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3276 SDLoc dl = getCurSDLoc();
3277 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3280 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3281 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3282 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3285 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3286 SDLoc dl = getCurSDLoc();
3287 AtomicOrdering Order = I.getOrdering();
3288 SynchronizationScope Scope = I.getSynchScope();
3290 SDValue InChain = getRoot();
3292 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3293 EVT VT = TLI.getValueType(I.getType());
3295 if (I.getAlignment() < VT.getSizeInBits() / 8)
3296 report_fatal_error("Cannot generate unaligned atomic load");
3298 MachineMemOperand *MMO =
3299 DAG.getMachineFunction().
3300 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3301 MachineMemOperand::MOVolatile |
3302 MachineMemOperand::MOLoad,
3304 I.getAlignment() ? I.getAlignment() :
3305 DAG.getEVTAlignment(VT));
3307 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3309 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3310 getValue(I.getPointerOperand()), MMO,
3313 SDValue OutChain = L.getValue(1);
3316 DAG.setRoot(OutChain);
3319 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3320 SDLoc dl = getCurSDLoc();
3322 AtomicOrdering Order = I.getOrdering();
3323 SynchronizationScope Scope = I.getSynchScope();
3325 SDValue InChain = getRoot();
3327 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3328 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3330 if (I.getAlignment() < VT.getSizeInBits() / 8)
3331 report_fatal_error("Cannot generate unaligned atomic store");
3334 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3336 getValue(I.getPointerOperand()),
3337 getValue(I.getValueOperand()),
3338 I.getPointerOperand(), I.getAlignment(),
3341 DAG.setRoot(OutChain);
3344 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3346 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3347 unsigned Intrinsic) {
3348 bool HasChain = !I.doesNotAccessMemory();
3349 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3351 // Build the operand list.
3352 SmallVector<SDValue, 8> Ops;
3353 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3355 // We don't need to serialize loads against other loads.
3356 Ops.push_back(DAG.getRoot());
3358 Ops.push_back(getRoot());
3362 // Info is set by getTgtMemInstrinsic
3363 TargetLowering::IntrinsicInfo Info;
3364 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3365 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3367 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3368 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3369 Info.opc == ISD::INTRINSIC_W_CHAIN)
3370 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3372 // Add all operands of the call to the operand list.
3373 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3374 SDValue Op = getValue(I.getArgOperand(i));
3378 SmallVector<EVT, 4> ValueVTs;
3379 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3382 ValueVTs.push_back(MVT::Other);
3384 SDVTList VTs = DAG.getVTList(ValueVTs);
3388 if (IsTgtIntrinsic) {
3389 // This is target intrinsic that touches memory
3390 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3391 VTs, Ops, Info.memVT,
3392 MachinePointerInfo(Info.ptrVal, Info.offset),
3393 Info.align, Info.vol,
3394 Info.readMem, Info.writeMem, Info.size);
3395 } else if (!HasChain) {
3396 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3397 } else if (!I.getType()->isVoidTy()) {
3398 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3400 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3404 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3406 PendingLoads.push_back(Chain);
3411 if (!I.getType()->isVoidTy()) {
3412 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3413 EVT VT = TLI.getValueType(PTy);
3414 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3417 setValue(&I, Result);
3421 /// GetSignificand - Get the significand and build it into a floating-point
3422 /// number with exponent of 1:
3424 /// Op = (Op & 0x007fffff) | 0x3f800000;
3426 /// where Op is the hexadecimal representation of floating point value.
3428 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3429 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3430 DAG.getConstant(0x007fffff, MVT::i32));
3431 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3432 DAG.getConstant(0x3f800000, MVT::i32));
3433 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3436 /// GetExponent - Get the exponent:
3438 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3440 /// where Op is the hexadecimal representation of floating point value.
3442 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3444 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3445 DAG.getConstant(0x7f800000, MVT::i32));
3446 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3447 DAG.getConstant(23, TLI.getPointerTy()));
3448 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3449 DAG.getConstant(127, MVT::i32));
3450 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3453 /// getF32Constant - Get 32-bit floating point constant.
3455 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3456 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3460 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3461 SelectionDAG &DAG) {
3462 // IntegerPartOfX = ((int32_t)(t0);
3463 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3465 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3466 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3467 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3469 // IntegerPartOfX <<= 23;
3470 IntegerPartOfX = DAG.getNode(
3471 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3472 DAG.getConstant(23, DAG.getTargetLoweringInfo().getPointerTy()));
3474 SDValue TwoToFractionalPartOfX;
3475 if (LimitFloatPrecision <= 6) {
3476 // For floating-point precision of 6:
3478 // TwoToFractionalPartOfX =
3480 // (0.735607626f + 0.252464424f * x) * x;
3482 // error 0.0144103317, which is 6 bits
3483 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3484 getF32Constant(DAG, 0x3e814304));
3485 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3486 getF32Constant(DAG, 0x3f3c50c8));
3487 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3488 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3489 getF32Constant(DAG, 0x3f7f5e7e));
3490 } else if (LimitFloatPrecision <= 12) {
3491 // For floating-point precision of 12:
3493 // TwoToFractionalPartOfX =
3496 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3498 // error 0.000107046256, which is 13 to 14 bits
3499 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3500 getF32Constant(DAG, 0x3da235e3));
3501 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3502 getF32Constant(DAG, 0x3e65b8f3));
3503 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3504 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3505 getF32Constant(DAG, 0x3f324b07));
3506 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3507 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3508 getF32Constant(DAG, 0x3f7ff8fd));
3509 } else { // LimitFloatPrecision <= 18
3510 // For floating-point precision of 18:
3512 // TwoToFractionalPartOfX =
3516 // (0.554906021e-1f +
3517 // (0.961591928e-2f +
3518 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3519 // error 2.47208000*10^(-7), which is better than 18 bits
3520 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3521 getF32Constant(DAG, 0x3924b03e));
3522 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3523 getF32Constant(DAG, 0x3ab24b87));
3524 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3525 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3526 getF32Constant(DAG, 0x3c1d8c17));
3527 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3528 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3529 getF32Constant(DAG, 0x3d634a1d));
3530 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3531 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3532 getF32Constant(DAG, 0x3e75fe14));
3533 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3534 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3535 getF32Constant(DAG, 0x3f317234));
3536 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3537 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3538 getF32Constant(DAG, 0x3f800000));
3541 // Add the exponent into the result in integer domain.
3542 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3543 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3544 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3547 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3548 /// limited-precision mode.
3549 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3550 const TargetLowering &TLI) {
3551 if (Op.getValueType() == MVT::f32 &&
3552 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3554 // Put the exponent in the right bit position for later addition to the
3557 // #define LOG2OFe 1.4426950f
3558 // t0 = Op * LOG2OFe
3559 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3560 getF32Constant(DAG, 0x3fb8aa3b));
3561 return getLimitedPrecisionExp2(t0, dl, DAG);
3564 // No special expansion.
3565 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3568 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3569 /// limited-precision mode.
3570 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3571 const TargetLowering &TLI) {
3572 if (Op.getValueType() == MVT::f32 &&
3573 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3574 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3576 // Scale the exponent by log(2) [0.69314718f].
3577 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3578 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3579 getF32Constant(DAG, 0x3f317218));
3581 // Get the significand and build it into a floating-point number with
3583 SDValue X = GetSignificand(DAG, Op1, dl);
3585 SDValue LogOfMantissa;
3586 if (LimitFloatPrecision <= 6) {
3587 // For floating-point precision of 6:
3591 // (1.4034025f - 0.23903021f * x) * x;
3593 // error 0.0034276066, which is better than 8 bits
3594 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3595 getF32Constant(DAG, 0xbe74c456));
3596 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3597 getF32Constant(DAG, 0x3fb3a2b1));
3598 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3599 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3600 getF32Constant(DAG, 0x3f949a29));
3601 } else if (LimitFloatPrecision <= 12) {
3602 // For floating-point precision of 12:
3608 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3610 // error 0.000061011436, which is 14 bits
3611 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3612 getF32Constant(DAG, 0xbd67b6d6));
3613 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3614 getF32Constant(DAG, 0x3ee4f4b8));
3615 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3616 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3617 getF32Constant(DAG, 0x3fbc278b));
3618 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3619 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3620 getF32Constant(DAG, 0x40348e95));
3621 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3622 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3623 getF32Constant(DAG, 0x3fdef31a));
3624 } else { // LimitFloatPrecision <= 18
3625 // For floating-point precision of 18:
3633 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3635 // error 0.0000023660568, which is better than 18 bits
3636 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3637 getF32Constant(DAG, 0xbc91e5ac));
3638 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3639 getF32Constant(DAG, 0x3e4350aa));
3640 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3641 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3642 getF32Constant(DAG, 0x3f60d3e3));
3643 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3644 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3645 getF32Constant(DAG, 0x4011cdf0));
3646 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3647 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3648 getF32Constant(DAG, 0x406cfd1c));
3649 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3650 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3651 getF32Constant(DAG, 0x408797cb));
3652 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3653 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3654 getF32Constant(DAG, 0x4006dcab));
3657 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3660 // No special expansion.
3661 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3664 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3665 /// limited-precision mode.
3666 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3667 const TargetLowering &TLI) {
3668 if (Op.getValueType() == MVT::f32 &&
3669 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3670 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3672 // Get the exponent.
3673 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3675 // Get the significand and build it into a floating-point number with
3677 SDValue X = GetSignificand(DAG, Op1, dl);
3679 // Different possible minimax approximations of significand in
3680 // floating-point for various degrees of accuracy over [1,2].
3681 SDValue Log2ofMantissa;
3682 if (LimitFloatPrecision <= 6) {
3683 // For floating-point precision of 6:
3685 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3687 // error 0.0049451742, which is more than 7 bits
3688 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3689 getF32Constant(DAG, 0xbeb08fe0));
3690 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3691 getF32Constant(DAG, 0x40019463));
3692 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3693 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3694 getF32Constant(DAG, 0x3fd6633d));
3695 } else if (LimitFloatPrecision <= 12) {
3696 // For floating-point precision of 12:
3702 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3704 // error 0.0000876136000, which is better than 13 bits
3705 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3706 getF32Constant(DAG, 0xbda7262e));
3707 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3708 getF32Constant(DAG, 0x3f25280b));
3709 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3710 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3711 getF32Constant(DAG, 0x4007b923));
3712 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3713 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3714 getF32Constant(DAG, 0x40823e2f));
3715 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3716 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3717 getF32Constant(DAG, 0x4020d29c));
3718 } else { // LimitFloatPrecision <= 18
3719 // For floating-point precision of 18:
3728 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3730 // error 0.0000018516, which is better than 18 bits
3731 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3732 getF32Constant(DAG, 0xbcd2769e));
3733 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3734 getF32Constant(DAG, 0x3e8ce0b9));
3735 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3736 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3737 getF32Constant(DAG, 0x3fa22ae7));
3738 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3739 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3740 getF32Constant(DAG, 0x40525723));
3741 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3742 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3743 getF32Constant(DAG, 0x40aaf200));
3744 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3745 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3746 getF32Constant(DAG, 0x40c39dad));
3747 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3748 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3749 getF32Constant(DAG, 0x4042902c));
3752 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3755 // No special expansion.
3756 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3759 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3760 /// limited-precision mode.
3761 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3762 const TargetLowering &TLI) {
3763 if (Op.getValueType() == MVT::f32 &&
3764 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3765 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3767 // Scale the exponent by log10(2) [0.30102999f].
3768 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3769 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3770 getF32Constant(DAG, 0x3e9a209a));
3772 // Get the significand and build it into a floating-point number with
3774 SDValue X = GetSignificand(DAG, Op1, dl);
3776 SDValue Log10ofMantissa;
3777 if (LimitFloatPrecision <= 6) {
3778 // For floating-point precision of 6:
3780 // Log10ofMantissa =
3782 // (0.60948995f - 0.10380950f * x) * x;
3784 // error 0.0014886165, which is 6 bits
3785 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3786 getF32Constant(DAG, 0xbdd49a13));
3787 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3788 getF32Constant(DAG, 0x3f1c0789));
3789 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3790 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3791 getF32Constant(DAG, 0x3f011300));
3792 } else if (LimitFloatPrecision <= 12) {
3793 // For floating-point precision of 12:
3795 // Log10ofMantissa =
3798 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3800 // error 0.00019228036, which is better than 12 bits
3801 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3802 getF32Constant(DAG, 0x3d431f31));
3803 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3804 getF32Constant(DAG, 0x3ea21fb2));
3805 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3806 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3807 getF32Constant(DAG, 0x3f6ae232));
3808 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3809 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3810 getF32Constant(DAG, 0x3f25f7c3));
3811 } else { // LimitFloatPrecision <= 18
3812 // For floating-point precision of 18:
3814 // Log10ofMantissa =
3819 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3821 // error 0.0000037995730, which is better than 18 bits
3822 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3823 getF32Constant(DAG, 0x3c5d51ce));
3824 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3825 getF32Constant(DAG, 0x3e00685a));
3826 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3827 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3828 getF32Constant(DAG, 0x3efb6798));
3829 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3830 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3831 getF32Constant(DAG, 0x3f88d192));
3832 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3833 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3834 getF32Constant(DAG, 0x3fc4316c));
3835 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3836 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3837 getF32Constant(DAG, 0x3f57ce70));
3840 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3843 // No special expansion.
3844 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3847 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3848 /// limited-precision mode.
3849 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3850 const TargetLowering &TLI) {
3851 if (Op.getValueType() == MVT::f32 &&
3852 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3853 return getLimitedPrecisionExp2(Op, dl, DAG);
3855 // No special expansion.
3856 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3859 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3860 /// limited-precision mode with x == 10.0f.
3861 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3862 SelectionDAG &DAG, const TargetLowering &TLI) {
3863 bool IsExp10 = false;
3864 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3865 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3866 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3868 IsExp10 = LHSC->isExactlyValue(Ten);
3873 // Put the exponent in the right bit position for later addition to the
3876 // #define LOG2OF10 3.3219281f
3877 // t0 = Op * LOG2OF10;
3878 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3879 getF32Constant(DAG, 0x40549a78));
3880 return getLimitedPrecisionExp2(t0, dl, DAG);
3883 // No special expansion.
3884 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
3888 /// ExpandPowI - Expand a llvm.powi intrinsic.
3889 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
3890 SelectionDAG &DAG) {
3891 // If RHS is a constant, we can expand this out to a multiplication tree,
3892 // otherwise we end up lowering to a call to __powidf2 (for example). When
3893 // optimizing for size, we only want to do this if the expansion would produce
3894 // a small number of multiplies, otherwise we do the full expansion.
3895 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3896 // Get the exponent as a positive value.
3897 unsigned Val = RHSC->getSExtValue();
3898 if ((int)Val < 0) Val = -Val;
3900 // powi(x, 0) -> 1.0
3902 return DAG.getConstantFP(1.0, LHS.getValueType());
3904 const Function *F = DAG.getMachineFunction().getFunction();
3905 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
3906 // If optimizing for size, don't insert too many multiplies. This
3907 // inserts up to 5 multiplies.
3908 countPopulation(Val) + Log2_32(Val) < 7) {
3909 // We use the simple binary decomposition method to generate the multiply
3910 // sequence. There are more optimal ways to do this (for example,
3911 // powi(x,15) generates one more multiply than it should), but this has
3912 // the benefit of being both really simple and much better than a libcall.
3913 SDValue Res; // Logically starts equal to 1.0
3914 SDValue CurSquare = LHS;
3918 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3920 Res = CurSquare; // 1.0*CurSquare.
3923 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3924 CurSquare, CurSquare);
3928 // If the original was negative, invert the result, producing 1/(x*x*x).
3929 if (RHSC->getSExtValue() < 0)
3930 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3931 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3936 // Otherwise, expand to a libcall.
3937 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3940 // getTruncatedArgReg - Find underlying register used for an truncated
3942 static unsigned getTruncatedArgReg(const SDValue &N) {
3943 if (N.getOpcode() != ISD::TRUNCATE)
3946 const SDValue &Ext = N.getOperand(0);
3947 if (Ext.getOpcode() == ISD::AssertZext ||
3948 Ext.getOpcode() == ISD::AssertSext) {
3949 const SDValue &CFR = Ext.getOperand(0);
3950 if (CFR.getOpcode() == ISD::CopyFromReg)
3951 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
3952 if (CFR.getOpcode() == ISD::TRUNCATE)
3953 return getTruncatedArgReg(CFR);
3958 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3959 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3960 /// At the end of instruction selection, they will be inserted to the entry BB.
3961 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
3962 const Value *V, MDLocalVariable *Variable, MDExpression *Expr,
3963 MDLocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
3964 const Argument *Arg = dyn_cast<Argument>(V);
3968 MachineFunction &MF = DAG.getMachineFunction();
3969 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
3971 // Ignore inlined function arguments here.
3973 // FIXME: Should we be checking DL->inlinedAt() to determine this?
3974 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
3977 Optional<MachineOperand> Op;
3978 // Some arguments' frame index is recorded during argument lowering.
3979 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
3980 Op = MachineOperand::CreateFI(FI);
3982 if (!Op && N.getNode()) {
3984 if (N.getOpcode() == ISD::CopyFromReg)
3985 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
3987 Reg = getTruncatedArgReg(N);
3988 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
3989 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3990 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
3995 Op = MachineOperand::CreateReg(Reg, false);
3999 // Check if ValueMap has reg number.
4000 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4001 if (VMI != FuncInfo.ValueMap.end())
4002 Op = MachineOperand::CreateReg(VMI->second, false);
4005 if (!Op && N.getNode())
4006 // Check if frame index is available.
4007 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4008 if (FrameIndexSDNode *FINode =
4009 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4010 Op = MachineOperand::CreateFI(FINode->getIndex());
4015 assert(Variable->isValidLocationForIntrinsic(DL) &&
4016 "Expected inlined-at fields to agree");
4018 FuncInfo.ArgDbgValues.push_back(
4019 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4020 Op->getReg(), Offset, Variable, Expr));
4022 FuncInfo.ArgDbgValues.push_back(
4023 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4026 .addMetadata(Variable)
4027 .addMetadata(Expr));
4032 // VisualStudio defines setjmp as _setjmp
4033 #if defined(_MSC_VER) && defined(setjmp) && \
4034 !defined(setjmp_undefined_for_msvc)
4035 # pragma push_macro("setjmp")
4037 # define setjmp_undefined_for_msvc
4040 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4041 /// we want to emit this as a call to a named external function, return the name
4042 /// otherwise lower it and return null.
4044 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4045 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4046 SDLoc sdl = getCurSDLoc();
4047 DebugLoc dl = getCurDebugLoc();
4050 switch (Intrinsic) {
4052 // By default, turn this into a target intrinsic node.
4053 visitTargetIntrinsic(I, Intrinsic);
4055 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4056 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4057 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4058 case Intrinsic::returnaddress:
4059 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4060 getValue(I.getArgOperand(0))));
4062 case Intrinsic::frameaddress:
4063 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4064 getValue(I.getArgOperand(0))));
4066 case Intrinsic::read_register: {
4067 Value *Reg = I.getArgOperand(0);
4069 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4070 EVT VT = TLI.getValueType(I.getType());
4071 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4074 case Intrinsic::write_register: {
4075 Value *Reg = I.getArgOperand(0);
4076 Value *RegValue = I.getArgOperand(1);
4077 SDValue Chain = getValue(RegValue).getOperand(0);
4079 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4080 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4081 RegName, getValue(RegValue)));
4084 case Intrinsic::setjmp:
4085 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4086 case Intrinsic::longjmp:
4087 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4088 case Intrinsic::memcpy: {
4089 // FIXME: this definition of "user defined address space" is x86-specific
4090 // Assert for address < 256 since we support only user defined address
4092 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4094 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4096 "Unknown address space");
4097 SDValue Op1 = getValue(I.getArgOperand(0));
4098 SDValue Op2 = getValue(I.getArgOperand(1));
4099 SDValue Op3 = getValue(I.getArgOperand(2));
4100 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4102 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4103 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4104 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4105 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4107 MachinePointerInfo(I.getArgOperand(0)),
4108 MachinePointerInfo(I.getArgOperand(1)));
4109 updateDAGForMaybeTailCall(MC);
4112 case Intrinsic::memset: {
4113 // FIXME: this definition of "user defined address space" is x86-specific
4114 // Assert for address < 256 since we support only user defined address
4116 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4118 "Unknown address space");
4119 SDValue Op1 = getValue(I.getArgOperand(0));
4120 SDValue Op2 = getValue(I.getArgOperand(1));
4121 SDValue Op3 = getValue(I.getArgOperand(2));
4122 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4124 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4125 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4126 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4127 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4128 isTC, MachinePointerInfo(I.getArgOperand(0)));
4129 updateDAGForMaybeTailCall(MS);
4132 case Intrinsic::memmove: {
4133 // FIXME: this definition of "user defined address space" is x86-specific
4134 // Assert for address < 256 since we support only user defined address
4136 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4138 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4140 "Unknown address space");
4141 SDValue Op1 = getValue(I.getArgOperand(0));
4142 SDValue Op2 = getValue(I.getArgOperand(1));
4143 SDValue Op3 = getValue(I.getArgOperand(2));
4144 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4146 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4147 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4148 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4149 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4150 isTC, MachinePointerInfo(I.getArgOperand(0)),
4151 MachinePointerInfo(I.getArgOperand(1)));
4152 updateDAGForMaybeTailCall(MM);
4155 case Intrinsic::dbg_declare: {
4156 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4157 MDLocalVariable *Variable = DI.getVariable();
4158 MDExpression *Expression = DI.getExpression();
4159 const Value *Address = DI.getAddress();
4160 assert(Variable && "Missing variable");
4162 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4166 // Check if address has undef value.
4167 if (isa<UndefValue>(Address) ||
4168 (Address->use_empty() && !isa<Argument>(Address))) {
4169 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4173 SDValue &N = NodeMap[Address];
4174 if (!N.getNode() && isa<Argument>(Address))
4175 // Check unused arguments map.
4176 N = UnusedArgNodeMap[Address];
4179 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4180 Address = BCI->getOperand(0);
4181 // Parameters are handled specially.
4182 bool isParameter = Variable->getTag() == dwarf::DW_TAG_arg_variable ||
4183 isa<Argument>(Address);
4185 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4187 if (isParameter && !AI) {
4188 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4190 // Byval parameter. We have a frame index at this point.
4191 SDV = DAG.getFrameIndexDbgValue(
4192 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4194 // Address is an argument, so try to emit its dbg value using
4195 // virtual register info from the FuncInfo.ValueMap.
4196 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4201 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4202 true, 0, dl, SDNodeOrder);
4204 // Can't do anything with other non-AI cases yet.
4205 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4206 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4207 DEBUG(Address->dump());
4210 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4212 // If Address is an argument then try to emit its dbg value using
4213 // virtual register info from the FuncInfo.ValueMap.
4214 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4216 // If variable is pinned by a alloca in dominating bb then
4217 // use StaticAllocaMap.
4218 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4219 if (AI->getParent() != DI.getParent()) {
4220 DenseMap<const AllocaInst*, int>::iterator SI =
4221 FuncInfo.StaticAllocaMap.find(AI);
4222 if (SI != FuncInfo.StaticAllocaMap.end()) {
4223 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4224 0, dl, SDNodeOrder);
4225 DAG.AddDbgValue(SDV, nullptr, false);
4230 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4235 case Intrinsic::dbg_value: {
4236 const DbgValueInst &DI = cast<DbgValueInst>(I);
4237 assert(DI.getVariable() && "Missing variable");
4239 MDLocalVariable *Variable = DI.getVariable();
4240 MDExpression *Expression = DI.getExpression();
4241 uint64_t Offset = DI.getOffset();
4242 const Value *V = DI.getValue();
4247 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4248 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4250 DAG.AddDbgValue(SDV, nullptr, false);
4252 // Do not use getValue() in here; we don't want to generate code at
4253 // this point if it hasn't been done yet.
4254 SDValue N = NodeMap[V];
4255 if (!N.getNode() && isa<Argument>(V))
4256 // Check unused arguments map.
4257 N = UnusedArgNodeMap[V];
4259 // A dbg.value for an alloca is always indirect.
4260 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4261 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4263 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4264 IsIndirect, Offset, dl, SDNodeOrder);
4265 DAG.AddDbgValue(SDV, N.getNode(), false);
4267 } else if (!V->use_empty() ) {
4268 // Do not call getValue(V) yet, as we don't want to generate code.
4269 // Remember it for later.
4270 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4271 DanglingDebugInfoMap[V] = DDI;
4273 // We may expand this to cover more cases. One case where we have no
4274 // data available is an unreferenced parameter.
4275 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4279 // Build a debug info table entry.
4280 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4281 V = BCI->getOperand(0);
4282 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4283 // Don't handle byval struct arguments or VLAs, for example.
4285 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4286 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4289 DenseMap<const AllocaInst*, int>::iterator SI =
4290 FuncInfo.StaticAllocaMap.find(AI);
4291 if (SI == FuncInfo.StaticAllocaMap.end())
4292 return nullptr; // VLAs.
4296 case Intrinsic::eh_typeid_for: {
4297 // Find the type id for the given typeinfo.
4298 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4299 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4300 Res = DAG.getConstant(TypeID, MVT::i32);
4305 case Intrinsic::eh_return_i32:
4306 case Intrinsic::eh_return_i64:
4307 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4308 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4311 getValue(I.getArgOperand(0)),
4312 getValue(I.getArgOperand(1))));
4314 case Intrinsic::eh_unwind_init:
4315 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4317 case Intrinsic::eh_dwarf_cfa: {
4318 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4319 TLI.getPointerTy());
4320 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4321 CfaArg.getValueType(),
4322 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4323 CfaArg.getValueType()),
4325 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4326 DAG.getConstant(0, TLI.getPointerTy()));
4327 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4331 case Intrinsic::eh_sjlj_callsite: {
4332 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4333 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4334 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4335 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4337 MMI.setCurrentCallSite(CI->getZExtValue());
4340 case Intrinsic::eh_sjlj_functioncontext: {
4341 // Get and store the index of the function context.
4342 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4344 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4345 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4346 MFI->setFunctionContextIndex(FI);
4349 case Intrinsic::eh_sjlj_setjmp: {
4352 Ops[1] = getValue(I.getArgOperand(0));
4353 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4354 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4355 setValue(&I, Op.getValue(0));
4356 DAG.setRoot(Op.getValue(1));
4359 case Intrinsic::eh_sjlj_longjmp: {
4360 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4361 getRoot(), getValue(I.getArgOperand(0))));
4365 case Intrinsic::masked_gather:
4366 visitMaskedGather(I);
4367 case Intrinsic::masked_load:
4370 case Intrinsic::masked_scatter:
4371 visitMaskedScatter(I);
4372 case Intrinsic::masked_store:
4373 visitMaskedStore(I);
4375 case Intrinsic::x86_mmx_pslli_w:
4376 case Intrinsic::x86_mmx_pslli_d:
4377 case Intrinsic::x86_mmx_pslli_q:
4378 case Intrinsic::x86_mmx_psrli_w:
4379 case Intrinsic::x86_mmx_psrli_d:
4380 case Intrinsic::x86_mmx_psrli_q:
4381 case Intrinsic::x86_mmx_psrai_w:
4382 case Intrinsic::x86_mmx_psrai_d: {
4383 SDValue ShAmt = getValue(I.getArgOperand(1));
4384 if (isa<ConstantSDNode>(ShAmt)) {
4385 visitTargetIntrinsic(I, Intrinsic);
4388 unsigned NewIntrinsic = 0;
4389 EVT ShAmtVT = MVT::v2i32;
4390 switch (Intrinsic) {
4391 case Intrinsic::x86_mmx_pslli_w:
4392 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4394 case Intrinsic::x86_mmx_pslli_d:
4395 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4397 case Intrinsic::x86_mmx_pslli_q:
4398 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4400 case Intrinsic::x86_mmx_psrli_w:
4401 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4403 case Intrinsic::x86_mmx_psrli_d:
4404 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4406 case Intrinsic::x86_mmx_psrli_q:
4407 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4409 case Intrinsic::x86_mmx_psrai_w:
4410 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4412 case Intrinsic::x86_mmx_psrai_d:
4413 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4415 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4418 // The vector shift intrinsics with scalars uses 32b shift amounts but
4419 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4421 // We must do this early because v2i32 is not a legal type.
4424 ShOps[1] = DAG.getConstant(0, MVT::i32);
4425 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4426 EVT DestVT = TLI.getValueType(I.getType());
4427 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4428 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4429 DAG.getConstant(NewIntrinsic, MVT::i32),
4430 getValue(I.getArgOperand(0)), ShAmt);
4434 case Intrinsic::convertff:
4435 case Intrinsic::convertfsi:
4436 case Intrinsic::convertfui:
4437 case Intrinsic::convertsif:
4438 case Intrinsic::convertuif:
4439 case Intrinsic::convertss:
4440 case Intrinsic::convertsu:
4441 case Intrinsic::convertus:
4442 case Intrinsic::convertuu: {
4443 ISD::CvtCode Code = ISD::CVT_INVALID;
4444 switch (Intrinsic) {
4445 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4446 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4447 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4448 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4449 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4450 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4451 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4452 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4453 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4454 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4456 EVT DestVT = TLI.getValueType(I.getType());
4457 const Value *Op1 = I.getArgOperand(0);
4458 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4459 DAG.getValueType(DestVT),
4460 DAG.getValueType(getValue(Op1).getValueType()),
4461 getValue(I.getArgOperand(1)),
4462 getValue(I.getArgOperand(2)),
4467 case Intrinsic::powi:
4468 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4469 getValue(I.getArgOperand(1)), DAG));
4471 case Intrinsic::log:
4472 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4474 case Intrinsic::log2:
4475 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4477 case Intrinsic::log10:
4478 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4480 case Intrinsic::exp:
4481 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4483 case Intrinsic::exp2:
4484 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4486 case Intrinsic::pow:
4487 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4488 getValue(I.getArgOperand(1)), DAG, TLI));
4490 case Intrinsic::sqrt:
4491 case Intrinsic::fabs:
4492 case Intrinsic::sin:
4493 case Intrinsic::cos:
4494 case Intrinsic::floor:
4495 case Intrinsic::ceil:
4496 case Intrinsic::trunc:
4497 case Intrinsic::rint:
4498 case Intrinsic::nearbyint:
4499 case Intrinsic::round: {
4501 switch (Intrinsic) {
4502 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4503 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4504 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4505 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4506 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4507 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4508 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4509 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4510 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4511 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4512 case Intrinsic::round: Opcode = ISD::FROUND; break;
4515 setValue(&I, DAG.getNode(Opcode, sdl,
4516 getValue(I.getArgOperand(0)).getValueType(),
4517 getValue(I.getArgOperand(0))));
4520 case Intrinsic::minnum:
4521 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4522 getValue(I.getArgOperand(0)).getValueType(),
4523 getValue(I.getArgOperand(0)),
4524 getValue(I.getArgOperand(1))));
4526 case Intrinsic::maxnum:
4527 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4528 getValue(I.getArgOperand(0)).getValueType(),
4529 getValue(I.getArgOperand(0)),
4530 getValue(I.getArgOperand(1))));
4532 case Intrinsic::copysign:
4533 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4534 getValue(I.getArgOperand(0)).getValueType(),
4535 getValue(I.getArgOperand(0)),
4536 getValue(I.getArgOperand(1))));
4538 case Intrinsic::fma:
4539 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4540 getValue(I.getArgOperand(0)).getValueType(),
4541 getValue(I.getArgOperand(0)),
4542 getValue(I.getArgOperand(1)),
4543 getValue(I.getArgOperand(2))));
4545 case Intrinsic::fmuladd: {
4546 EVT VT = TLI.getValueType(I.getType());
4547 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4548 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4549 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4550 getValue(I.getArgOperand(0)).getValueType(),
4551 getValue(I.getArgOperand(0)),
4552 getValue(I.getArgOperand(1)),
4553 getValue(I.getArgOperand(2))));
4555 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4556 getValue(I.getArgOperand(0)).getValueType(),
4557 getValue(I.getArgOperand(0)),
4558 getValue(I.getArgOperand(1)));
4559 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4560 getValue(I.getArgOperand(0)).getValueType(),
4562 getValue(I.getArgOperand(2)));
4567 case Intrinsic::convert_to_fp16:
4568 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4569 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4570 getValue(I.getArgOperand(0)),
4571 DAG.getTargetConstant(0, MVT::i32))));
4573 case Intrinsic::convert_from_fp16:
4575 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
4576 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4577 getValue(I.getArgOperand(0)))));
4579 case Intrinsic::pcmarker: {
4580 SDValue Tmp = getValue(I.getArgOperand(0));
4581 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4584 case Intrinsic::readcyclecounter: {
4585 SDValue Op = getRoot();
4586 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4587 DAG.getVTList(MVT::i64, MVT::Other), Op);
4589 DAG.setRoot(Res.getValue(1));
4592 case Intrinsic::bswap:
4593 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4594 getValue(I.getArgOperand(0)).getValueType(),
4595 getValue(I.getArgOperand(0))));
4597 case Intrinsic::cttz: {
4598 SDValue Arg = getValue(I.getArgOperand(0));
4599 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4600 EVT Ty = Arg.getValueType();
4601 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4605 case Intrinsic::ctlz: {
4606 SDValue Arg = getValue(I.getArgOperand(0));
4607 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4608 EVT Ty = Arg.getValueType();
4609 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4613 case Intrinsic::ctpop: {
4614 SDValue Arg = getValue(I.getArgOperand(0));
4615 EVT Ty = Arg.getValueType();
4616 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4619 case Intrinsic::stacksave: {
4620 SDValue Op = getRoot();
4621 Res = DAG.getNode(ISD::STACKSAVE, sdl,
4622 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
4624 DAG.setRoot(Res.getValue(1));
4627 case Intrinsic::stackrestore: {
4628 Res = getValue(I.getArgOperand(0));
4629 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4632 case Intrinsic::stackprotector: {
4633 // Emit code into the DAG to store the stack guard onto the stack.
4634 MachineFunction &MF = DAG.getMachineFunction();
4635 MachineFrameInfo *MFI = MF.getFrameInfo();
4636 EVT PtrTy = TLI.getPointerTy();
4637 SDValue Src, Chain = getRoot();
4638 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4639 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4641 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4642 // global variable __stack_chk_guard.
4644 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4645 if (BC->getOpcode() == Instruction::BitCast)
4646 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4648 if (GV && TLI.useLoadStackGuardNode()) {
4649 // Emit a LOAD_STACK_GUARD node.
4650 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4652 MachinePointerInfo MPInfo(GV);
4653 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4654 unsigned Flags = MachineMemOperand::MOLoad |
4655 MachineMemOperand::MOInvariant;
4656 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4657 PtrTy.getSizeInBits() / 8,
4658 DAG.getEVTAlignment(PtrTy));
4659 Node->setMemRefs(MemRefs, MemRefs + 1);
4661 // Copy the guard value to a virtual register so that it can be
4662 // retrieved in the epilogue.
4663 Src = SDValue(Node, 0);
4664 const TargetRegisterClass *RC =
4665 TLI.getRegClassFor(Src.getSimpleValueType());
4666 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4668 SPDescriptor.setGuardReg(Reg);
4669 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4671 Src = getValue(I.getArgOperand(0)); // The guard's value.
4674 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4676 int FI = FuncInfo.StaticAllocaMap[Slot];
4677 MFI->setStackProtectorIndex(FI);
4679 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4681 // Store the stack protector onto the stack.
4682 Res = DAG.getStore(Chain, sdl, Src, FIN,
4683 MachinePointerInfo::getFixedStack(FI),
4689 case Intrinsic::objectsize: {
4690 // If we don't know by now, we're never going to know.
4691 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4693 assert(CI && "Non-constant type in __builtin_object_size?");
4695 SDValue Arg = getValue(I.getCalledValue());
4696 EVT Ty = Arg.getValueType();
4699 Res = DAG.getConstant(-1ULL, Ty);
4701 Res = DAG.getConstant(0, Ty);
4706 case Intrinsic::annotation:
4707 case Intrinsic::ptr_annotation:
4708 // Drop the intrinsic, but forward the value
4709 setValue(&I, getValue(I.getOperand(0)));
4711 case Intrinsic::assume:
4712 case Intrinsic::var_annotation:
4713 // Discard annotate attributes and assumptions
4716 case Intrinsic::init_trampoline: {
4717 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4721 Ops[1] = getValue(I.getArgOperand(0));
4722 Ops[2] = getValue(I.getArgOperand(1));
4723 Ops[3] = getValue(I.getArgOperand(2));
4724 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4725 Ops[5] = DAG.getSrcValue(F);
4727 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4732 case Intrinsic::adjust_trampoline: {
4733 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4735 getValue(I.getArgOperand(0))));
4738 case Intrinsic::gcroot:
4740 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4741 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4743 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4744 GFI->addStackRoot(FI->getIndex(), TypeMap);
4747 case Intrinsic::gcread:
4748 case Intrinsic::gcwrite:
4749 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4750 case Intrinsic::flt_rounds:
4751 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4754 case Intrinsic::expect: {
4755 // Just replace __builtin_expect(exp, c) with EXP.
4756 setValue(&I, getValue(I.getArgOperand(0)));
4760 case Intrinsic::debugtrap:
4761 case Intrinsic::trap: {
4762 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
4763 if (TrapFuncName.empty()) {
4764 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4765 ISD::TRAP : ISD::DEBUGTRAP;
4766 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4769 TargetLowering::ArgListTy Args;
4771 TargetLowering::CallLoweringInfo CLI(DAG);
4772 CLI.setDebugLoc(sdl).setChain(getRoot())
4773 .setCallee(CallingConv::C, I.getType(),
4774 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
4775 std::move(Args), 0);
4777 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4778 DAG.setRoot(Result.second);
4782 case Intrinsic::uadd_with_overflow:
4783 case Intrinsic::sadd_with_overflow:
4784 case Intrinsic::usub_with_overflow:
4785 case Intrinsic::ssub_with_overflow:
4786 case Intrinsic::umul_with_overflow:
4787 case Intrinsic::smul_with_overflow: {
4789 switch (Intrinsic) {
4790 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4791 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4792 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4793 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4794 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4795 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4796 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4798 SDValue Op1 = getValue(I.getArgOperand(0));
4799 SDValue Op2 = getValue(I.getArgOperand(1));
4801 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4802 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4805 case Intrinsic::prefetch: {
4807 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4809 Ops[1] = getValue(I.getArgOperand(0));
4810 Ops[2] = getValue(I.getArgOperand(1));
4811 Ops[3] = getValue(I.getArgOperand(2));
4812 Ops[4] = getValue(I.getArgOperand(3));
4813 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4814 DAG.getVTList(MVT::Other), Ops,
4815 EVT::getIntegerVT(*Context, 8),
4816 MachinePointerInfo(I.getArgOperand(0)),
4818 false, /* volatile */
4820 rw==1)); /* write */
4823 case Intrinsic::lifetime_start:
4824 case Intrinsic::lifetime_end: {
4825 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4826 // Stack coloring is not enabled in O0, discard region information.
4827 if (TM.getOptLevel() == CodeGenOpt::None)
4830 SmallVector<Value *, 4> Allocas;
4831 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4833 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4834 E = Allocas.end(); Object != E; ++Object) {
4835 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4837 // Could not find an Alloca.
4838 if (!LifetimeObject)
4841 // First check that the Alloca is static, otherwise it won't have a
4842 // valid frame index.
4843 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4844 if (SI == FuncInfo.StaticAllocaMap.end())
4847 int FI = SI->second;
4851 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
4852 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4854 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
4859 case Intrinsic::invariant_start:
4860 // Discard region information.
4861 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4863 case Intrinsic::invariant_end:
4864 // Discard region information.
4866 case Intrinsic::stackprotectorcheck: {
4867 // Do not actually emit anything for this basic block. Instead we initialize
4868 // the stack protector descriptor and export the guard variable so we can
4869 // access it in FinishBasicBlock.
4870 const BasicBlock *BB = I.getParent();
4871 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
4872 ExportFromCurrentBlock(SPDescriptor.getGuard());
4874 // Flush our exports since we are going to process a terminator.
4875 (void)getControlRoot();
4878 case Intrinsic::clear_cache:
4879 return TLI.getClearCacheBuiltinName();
4880 case Intrinsic::eh_actions:
4881 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4883 case Intrinsic::donothing:
4886 case Intrinsic::experimental_stackmap: {
4890 case Intrinsic::experimental_patchpoint_void:
4891 case Intrinsic::experimental_patchpoint_i64: {
4892 visitPatchpoint(&I);
4895 case Intrinsic::experimental_gc_statepoint: {
4899 case Intrinsic::experimental_gc_result_int:
4900 case Intrinsic::experimental_gc_result_float:
4901 case Intrinsic::experimental_gc_result_ptr:
4902 case Intrinsic::experimental_gc_result: {
4906 case Intrinsic::experimental_gc_relocate: {
4910 case Intrinsic::instrprof_increment:
4911 llvm_unreachable("instrprof failed to lower an increment");
4913 case Intrinsic::frameescape: {
4914 MachineFunction &MF = DAG.getMachineFunction();
4915 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4917 // Directly emit some FRAME_ALLOC machine instrs. Label assignment emission
4918 // is the same on all targets.
4919 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
4920 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
4921 if (isa<ConstantPointerNull>(Arg))
4922 continue; // Skip null pointers. They represent a hole in index space.
4923 AllocaInst *Slot = cast<AllocaInst>(Arg);
4924 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
4925 "can only escape static allocas");
4926 int FI = FuncInfo.StaticAllocaMap[Slot];
4927 MCSymbol *FrameAllocSym =
4928 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4929 GlobalValue::getRealLinkageName(MF.getName()), Idx);
4930 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
4931 TII->get(TargetOpcode::FRAME_ALLOC))
4932 .addSym(FrameAllocSym)
4939 case Intrinsic::framerecover: {
4940 // i8* @llvm.framerecover(i8* %fn, i8* %fp, i32 %idx)
4941 MachineFunction &MF = DAG.getMachineFunction();
4942 MVT PtrVT = TLI.getPointerTy(0);
4944 // Get the symbol that defines the frame offset.
4945 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
4946 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
4947 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
4948 MCSymbol *FrameAllocSym =
4949 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4950 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
4952 // Create a TargetExternalSymbol for the label to avoid any target lowering
4953 // that would make this PC relative.
4954 StringRef Name = FrameAllocSym->getName();
4955 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
4956 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
4958 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
4960 // Add the offset to the FP.
4961 Value *FP = I.getArgOperand(1);
4962 SDValue FPVal = getValue(FP);
4963 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
4968 case Intrinsic::eh_begincatch:
4969 case Intrinsic::eh_endcatch:
4970 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
4971 case Intrinsic::eh_exceptioncode: {
4972 unsigned Reg = TLI.getExceptionPointerRegister();
4973 assert(Reg && "cannot get exception code on this platform");
4974 MVT PtrVT = TLI.getPointerTy();
4975 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
4976 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
4978 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
4979 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
4986 std::pair<SDValue, SDValue>
4987 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
4988 MachineBasicBlock *LandingPad) {
4989 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4990 MCSymbol *BeginLabel = nullptr;
4993 // Insert a label before the invoke call to mark the try range. This can be
4994 // used to detect deletion of the invoke via the MachineModuleInfo.
4995 BeginLabel = MMI.getContext().CreateTempSymbol();
4997 // For SjLj, keep track of which landing pads go with which invokes
4998 // so as to maintain the ordering of pads in the LSDA.
4999 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5000 if (CallSiteIndex) {
5001 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5002 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5004 // Now that the call site is handled, stop tracking it.
5005 MMI.setCurrentCallSite(0);
5008 // Both PendingLoads and PendingExports must be flushed here;
5009 // this call might not return.
5011 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5013 CLI.setChain(getRoot());
5015 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5016 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5018 assert((CLI.IsTailCall || Result.second.getNode()) &&
5019 "Non-null chain expected with non-tail call!");
5020 assert((Result.second.getNode() || !Result.first.getNode()) &&
5021 "Null value expected with tail call!");
5023 if (!Result.second.getNode()) {
5024 // As a special case, a null chain means that a tail call has been emitted
5025 // and the DAG root is already updated.
5028 // Since there's no actual continuation from this block, nothing can be
5029 // relying on us setting vregs for them.
5030 PendingExports.clear();
5032 DAG.setRoot(Result.second);
5036 // Insert a label at the end of the invoke call to mark the try range. This
5037 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5038 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5039 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5041 // Inform MachineModuleInfo of range.
5042 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5048 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5050 MachineBasicBlock *LandingPad) {
5051 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5052 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5053 Type *RetTy = FTy->getReturnType();
5055 TargetLowering::ArgListTy Args;
5056 TargetLowering::ArgListEntry Entry;
5057 Args.reserve(CS.arg_size());
5059 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5061 const Value *V = *i;
5064 if (V->getType()->isEmptyTy())
5067 SDValue ArgNode = getValue(V);
5068 Entry.Node = ArgNode; Entry.Ty = V->getType();
5070 // Skip the first return-type Attribute to get to params.
5071 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5072 Args.push_back(Entry);
5074 // If we have an explicit sret argument that is an Instruction, (i.e., it
5075 // might point to function-local memory), we can't meaningfully tail-call.
5076 if (Entry.isSRet && isa<Instruction>(V))
5080 // Check if target-independent constraints permit a tail call here.
5081 // Target-dependent constraints are checked within TLI->LowerCallTo.
5082 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5085 TargetLowering::CallLoweringInfo CLI(DAG);
5086 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5087 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5088 .setTailCall(isTailCall);
5089 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5091 if (Result.first.getNode())
5092 setValue(CS.getInstruction(), Result.first);
5095 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5096 /// value is equal or not-equal to zero.
5097 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5098 for (const User *U : V->users()) {
5099 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5100 if (IC->isEquality())
5101 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5102 if (C->isNullValue())
5104 // Unknown instruction.
5110 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5112 SelectionDAGBuilder &Builder) {
5114 // Check to see if this load can be trivially constant folded, e.g. if the
5115 // input is from a string literal.
5116 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5117 // Cast pointer to the type we really want to load.
5118 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5119 PointerType::getUnqual(LoadTy));
5121 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5122 const_cast<Constant *>(LoadInput), *Builder.DL))
5123 return Builder.getValue(LoadCst);
5126 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5127 // still constant memory, the input chain can be the entry node.
5129 bool ConstantMemory = false;
5131 // Do not serialize (non-volatile) loads of constant memory with anything.
5132 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5133 Root = Builder.DAG.getEntryNode();
5134 ConstantMemory = true;
5136 // Do not serialize non-volatile loads against each other.
5137 Root = Builder.DAG.getRoot();
5140 SDValue Ptr = Builder.getValue(PtrVal);
5141 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5142 Ptr, MachinePointerInfo(PtrVal),
5144 false /*nontemporal*/,
5145 false /*isinvariant*/, 1 /* align=1 */);
5147 if (!ConstantMemory)
5148 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5152 /// processIntegerCallValue - Record the value for an instruction that
5153 /// produces an integer result, converting the type where necessary.
5154 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5157 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5159 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5161 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5162 setValue(&I, Value);
5165 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5166 /// If so, return true and lower it, otherwise return false and it will be
5167 /// lowered like a normal call.
5168 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5169 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5170 if (I.getNumArgOperands() != 3)
5173 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5174 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5175 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5176 !I.getType()->isIntegerTy())
5179 const Value *Size = I.getArgOperand(2);
5180 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5181 if (CSize && CSize->getZExtValue() == 0) {
5182 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5183 setValue(&I, DAG.getConstant(0, CallVT));
5187 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5188 std::pair<SDValue, SDValue> Res =
5189 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5190 getValue(LHS), getValue(RHS), getValue(Size),
5191 MachinePointerInfo(LHS),
5192 MachinePointerInfo(RHS));
5193 if (Res.first.getNode()) {
5194 processIntegerCallValue(I, Res.first, true);
5195 PendingLoads.push_back(Res.second);
5199 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5200 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5201 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5202 bool ActuallyDoIt = true;
5205 switch (CSize->getZExtValue()) {
5207 LoadVT = MVT::Other;
5209 ActuallyDoIt = false;
5213 LoadTy = Type::getInt16Ty(CSize->getContext());
5217 LoadTy = Type::getInt32Ty(CSize->getContext());
5221 LoadTy = Type::getInt64Ty(CSize->getContext());
5225 LoadVT = MVT::v4i32;
5226 LoadTy = Type::getInt32Ty(CSize->getContext());
5227 LoadTy = VectorType::get(LoadTy, 4);
5232 // This turns into unaligned loads. We only do this if the target natively
5233 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5234 // we'll only produce a small number of byte loads.
5236 // Require that we can find a legal MVT, and only do this if the target
5237 // supports unaligned loads of that type. Expanding into byte loads would
5239 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5240 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5241 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5242 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5243 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5244 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5245 // TODO: Check alignment of src and dest ptrs.
5246 if (!TLI.isTypeLegal(LoadVT) ||
5247 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5248 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5249 ActuallyDoIt = false;
5253 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5254 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5256 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5258 processIntegerCallValue(I, Res, false);
5267 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5268 /// form. If so, return true and lower it, otherwise return false and it
5269 /// will be lowered like a normal call.
5270 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5271 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5272 if (I.getNumArgOperands() != 3)
5275 const Value *Src = I.getArgOperand(0);
5276 const Value *Char = I.getArgOperand(1);
5277 const Value *Length = I.getArgOperand(2);
5278 if (!Src->getType()->isPointerTy() ||
5279 !Char->getType()->isIntegerTy() ||
5280 !Length->getType()->isIntegerTy() ||
5281 !I.getType()->isPointerTy())
5284 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5285 std::pair<SDValue, SDValue> Res =
5286 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5287 getValue(Src), getValue(Char), getValue(Length),
5288 MachinePointerInfo(Src));
5289 if (Res.first.getNode()) {
5290 setValue(&I, Res.first);
5291 PendingLoads.push_back(Res.second);
5298 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5299 /// optimized form. If so, return true and lower it, otherwise return false
5300 /// and it will be lowered like a normal call.
5301 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5302 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5303 if (I.getNumArgOperands() != 2)
5306 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5307 if (!Arg0->getType()->isPointerTy() ||
5308 !Arg1->getType()->isPointerTy() ||
5309 !I.getType()->isPointerTy())
5312 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5313 std::pair<SDValue, SDValue> Res =
5314 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5315 getValue(Arg0), getValue(Arg1),
5316 MachinePointerInfo(Arg0),
5317 MachinePointerInfo(Arg1), isStpcpy);
5318 if (Res.first.getNode()) {
5319 setValue(&I, Res.first);
5320 DAG.setRoot(Res.second);
5327 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5328 /// If so, return true and lower it, otherwise return false and it will be
5329 /// lowered like a normal call.
5330 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5331 // Verify that the prototype makes sense. int strcmp(void*,void*)
5332 if (I.getNumArgOperands() != 2)
5335 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5336 if (!Arg0->getType()->isPointerTy() ||
5337 !Arg1->getType()->isPointerTy() ||
5338 !I.getType()->isIntegerTy())
5341 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5342 std::pair<SDValue, SDValue> Res =
5343 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5344 getValue(Arg0), getValue(Arg1),
5345 MachinePointerInfo(Arg0),
5346 MachinePointerInfo(Arg1));
5347 if (Res.first.getNode()) {
5348 processIntegerCallValue(I, Res.first, true);
5349 PendingLoads.push_back(Res.second);
5356 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5357 /// form. If so, return true and lower it, otherwise return false and it
5358 /// will be lowered like a normal call.
5359 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5360 // Verify that the prototype makes sense. size_t strlen(char *)
5361 if (I.getNumArgOperands() != 1)
5364 const Value *Arg0 = I.getArgOperand(0);
5365 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5368 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5369 std::pair<SDValue, SDValue> Res =
5370 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5371 getValue(Arg0), MachinePointerInfo(Arg0));
5372 if (Res.first.getNode()) {
5373 processIntegerCallValue(I, Res.first, false);
5374 PendingLoads.push_back(Res.second);
5381 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5382 /// form. If so, return true and lower it, otherwise return false and it
5383 /// will be lowered like a normal call.
5384 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5385 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5386 if (I.getNumArgOperands() != 2)
5389 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5390 if (!Arg0->getType()->isPointerTy() ||
5391 !Arg1->getType()->isIntegerTy() ||
5392 !I.getType()->isIntegerTy())
5395 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5396 std::pair<SDValue, SDValue> Res =
5397 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5398 getValue(Arg0), getValue(Arg1),
5399 MachinePointerInfo(Arg0));
5400 if (Res.first.getNode()) {
5401 processIntegerCallValue(I, Res.first, false);
5402 PendingLoads.push_back(Res.second);
5409 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5410 /// operation (as expected), translate it to an SDNode with the specified opcode
5411 /// and return true.
5412 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5414 // Sanity check that it really is a unary floating-point call.
5415 if (I.getNumArgOperands() != 1 ||
5416 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5417 I.getType() != I.getArgOperand(0)->getType() ||
5418 !I.onlyReadsMemory())
5421 SDValue Tmp = getValue(I.getArgOperand(0));
5422 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5426 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5427 /// operation (as expected), translate it to an SDNode with the specified opcode
5428 /// and return true.
5429 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5431 // Sanity check that it really is a binary floating-point call.
5432 if (I.getNumArgOperands() != 2 ||
5433 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5434 I.getType() != I.getArgOperand(0)->getType() ||
5435 I.getType() != I.getArgOperand(1)->getType() ||
5436 !I.onlyReadsMemory())
5439 SDValue Tmp0 = getValue(I.getArgOperand(0));
5440 SDValue Tmp1 = getValue(I.getArgOperand(1));
5441 EVT VT = Tmp0.getValueType();
5442 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5446 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5447 // Handle inline assembly differently.
5448 if (isa<InlineAsm>(I.getCalledValue())) {
5453 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5454 ComputeUsesVAFloatArgument(I, &MMI);
5456 const char *RenameFn = nullptr;
5457 if (Function *F = I.getCalledFunction()) {
5458 if (F->isDeclaration()) {
5459 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5460 if (unsigned IID = II->getIntrinsicID(F)) {
5461 RenameFn = visitIntrinsicCall(I, IID);
5466 if (unsigned IID = F->getIntrinsicID()) {
5467 RenameFn = visitIntrinsicCall(I, IID);
5473 // Check for well-known libc/libm calls. If the function is internal, it
5474 // can't be a library call.
5476 if (!F->hasLocalLinkage() && F->hasName() &&
5477 LibInfo->getLibFunc(F->getName(), Func) &&
5478 LibInfo->hasOptimizedCodeGen(Func)) {
5481 case LibFunc::copysign:
5482 case LibFunc::copysignf:
5483 case LibFunc::copysignl:
5484 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5485 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5486 I.getType() == I.getArgOperand(0)->getType() &&
5487 I.getType() == I.getArgOperand(1)->getType() &&
5488 I.onlyReadsMemory()) {
5489 SDValue LHS = getValue(I.getArgOperand(0));
5490 SDValue RHS = getValue(I.getArgOperand(1));
5491 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5492 LHS.getValueType(), LHS, RHS));
5497 case LibFunc::fabsf:
5498 case LibFunc::fabsl:
5499 if (visitUnaryFloatCall(I, ISD::FABS))
5503 case LibFunc::fminf:
5504 case LibFunc::fminl:
5505 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5509 case LibFunc::fmaxf:
5510 case LibFunc::fmaxl:
5511 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5517 if (visitUnaryFloatCall(I, ISD::FSIN))
5523 if (visitUnaryFloatCall(I, ISD::FCOS))
5527 case LibFunc::sqrtf:
5528 case LibFunc::sqrtl:
5529 case LibFunc::sqrt_finite:
5530 case LibFunc::sqrtf_finite:
5531 case LibFunc::sqrtl_finite:
5532 if (visitUnaryFloatCall(I, ISD::FSQRT))
5535 case LibFunc::floor:
5536 case LibFunc::floorf:
5537 case LibFunc::floorl:
5538 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5541 case LibFunc::nearbyint:
5542 case LibFunc::nearbyintf:
5543 case LibFunc::nearbyintl:
5544 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5548 case LibFunc::ceilf:
5549 case LibFunc::ceill:
5550 if (visitUnaryFloatCall(I, ISD::FCEIL))
5554 case LibFunc::rintf:
5555 case LibFunc::rintl:
5556 if (visitUnaryFloatCall(I, ISD::FRINT))
5559 case LibFunc::round:
5560 case LibFunc::roundf:
5561 case LibFunc::roundl:
5562 if (visitUnaryFloatCall(I, ISD::FROUND))
5565 case LibFunc::trunc:
5566 case LibFunc::truncf:
5567 case LibFunc::truncl:
5568 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5572 case LibFunc::log2f:
5573 case LibFunc::log2l:
5574 if (visitUnaryFloatCall(I, ISD::FLOG2))
5578 case LibFunc::exp2f:
5579 case LibFunc::exp2l:
5580 if (visitUnaryFloatCall(I, ISD::FEXP2))
5583 case LibFunc::memcmp:
5584 if (visitMemCmpCall(I))
5587 case LibFunc::memchr:
5588 if (visitMemChrCall(I))
5591 case LibFunc::strcpy:
5592 if (visitStrCpyCall(I, false))
5595 case LibFunc::stpcpy:
5596 if (visitStrCpyCall(I, true))
5599 case LibFunc::strcmp:
5600 if (visitStrCmpCall(I))
5603 case LibFunc::strlen:
5604 if (visitStrLenCall(I))
5607 case LibFunc::strnlen:
5608 if (visitStrNLenCall(I))
5617 Callee = getValue(I.getCalledValue());
5619 Callee = DAG.getExternalSymbol(RenameFn,
5620 DAG.getTargetLoweringInfo().getPointerTy());
5622 // Check if we can potentially perform a tail call. More detailed checking is
5623 // be done within LowerCallTo, after more information about the call is known.
5624 LowerCallTo(&I, Callee, I.isTailCall());
5629 /// AsmOperandInfo - This contains information for each constraint that we are
5631 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5633 /// CallOperand - If this is the result output operand or a clobber
5634 /// this is null, otherwise it is the incoming operand to the CallInst.
5635 /// This gets modified as the asm is processed.
5636 SDValue CallOperand;
5638 /// AssignedRegs - If this is a register or register class operand, this
5639 /// contains the set of register corresponding to the operand.
5640 RegsForValue AssignedRegs;
5642 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5643 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5646 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5647 /// corresponds to. If there is no Value* for this operand, it returns
5649 EVT getCallOperandValEVT(LLVMContext &Context,
5650 const TargetLowering &TLI,
5651 const DataLayout *DL) const {
5652 if (!CallOperandVal) return MVT::Other;
5654 if (isa<BasicBlock>(CallOperandVal))
5655 return TLI.getPointerTy();
5657 llvm::Type *OpTy = CallOperandVal->getType();
5659 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5660 // If this is an indirect operand, the operand is a pointer to the
5663 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5665 report_fatal_error("Indirect operand for inline asm not a pointer!");
5666 OpTy = PtrTy->getElementType();
5669 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5670 if (StructType *STy = dyn_cast<StructType>(OpTy))
5671 if (STy->getNumElements() == 1)
5672 OpTy = STy->getElementType(0);
5674 // If OpTy is not a single value, it may be a struct/union that we
5675 // can tile with integers.
5676 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5677 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
5686 OpTy = IntegerType::get(Context, BitSize);
5691 return TLI.getValueType(OpTy, true);
5695 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5697 } // end anonymous namespace
5699 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5700 /// specified operand. We prefer to assign virtual registers, to allow the
5701 /// register allocator to handle the assignment process. However, if the asm
5702 /// uses features that we can't model on machineinstrs, we have SDISel do the
5703 /// allocation. This produces generally horrible, but correct, code.
5705 /// OpInfo describes the operand.
5707 static void GetRegistersForValue(SelectionDAG &DAG,
5708 const TargetLowering &TLI,
5710 SDISelAsmOperandInfo &OpInfo) {
5711 LLVMContext &Context = *DAG.getContext();
5713 MachineFunction &MF = DAG.getMachineFunction();
5714 SmallVector<unsigned, 4> Regs;
5716 // If this is a constraint for a single physreg, or a constraint for a
5717 // register class, find it.
5718 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5719 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5720 OpInfo.ConstraintCode,
5721 OpInfo.ConstraintVT);
5723 unsigned NumRegs = 1;
5724 if (OpInfo.ConstraintVT != MVT::Other) {
5725 // If this is a FP input in an integer register (or visa versa) insert a bit
5726 // cast of the input value. More generally, handle any case where the input
5727 // value disagrees with the register class we plan to stick this in.
5728 if (OpInfo.Type == InlineAsm::isInput &&
5729 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5730 // Try to convert to the first EVT that the reg class contains. If the
5731 // types are identical size, use a bitcast to convert (e.g. two differing
5733 MVT RegVT = *PhysReg.second->vt_begin();
5734 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5735 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5736 RegVT, OpInfo.CallOperand);
5737 OpInfo.ConstraintVT = RegVT;
5738 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5739 // If the input is a FP value and we want it in FP registers, do a
5740 // bitcast to the corresponding integer type. This turns an f64 value
5741 // into i64, which can be passed with two i32 values on a 32-bit
5743 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5744 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5745 RegVT, OpInfo.CallOperand);
5746 OpInfo.ConstraintVT = RegVT;
5750 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5754 EVT ValueVT = OpInfo.ConstraintVT;
5756 // If this is a constraint for a specific physical register, like {r17},
5758 if (unsigned AssignedReg = PhysReg.first) {
5759 const TargetRegisterClass *RC = PhysReg.second;
5760 if (OpInfo.ConstraintVT == MVT::Other)
5761 ValueVT = *RC->vt_begin();
5763 // Get the actual register value type. This is important, because the user
5764 // may have asked for (e.g.) the AX register in i32 type. We need to
5765 // remember that AX is actually i16 to get the right extension.
5766 RegVT = *RC->vt_begin();
5768 // This is a explicit reference to a physical register.
5769 Regs.push_back(AssignedReg);
5771 // If this is an expanded reference, add the rest of the regs to Regs.
5773 TargetRegisterClass::iterator I = RC->begin();
5774 for (; *I != AssignedReg; ++I)
5775 assert(I != RC->end() && "Didn't find reg!");
5777 // Already added the first reg.
5779 for (; NumRegs; --NumRegs, ++I) {
5780 assert(I != RC->end() && "Ran out of registers to allocate!");
5785 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5789 // Otherwise, if this was a reference to an LLVM register class, create vregs
5790 // for this reference.
5791 if (const TargetRegisterClass *RC = PhysReg.second) {
5792 RegVT = *RC->vt_begin();
5793 if (OpInfo.ConstraintVT == MVT::Other)
5796 // Create the appropriate number of virtual registers.
5797 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5798 for (; NumRegs; --NumRegs)
5799 Regs.push_back(RegInfo.createVirtualRegister(RC));
5801 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5805 // Otherwise, we couldn't allocate enough registers for this.
5808 /// visitInlineAsm - Handle a call to an InlineAsm object.
5810 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5811 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5813 /// ConstraintOperands - Information about all of the constraints.
5814 SDISelAsmOperandInfoVector ConstraintOperands;
5816 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5817 TargetLowering::AsmOperandInfoVector TargetConstraints =
5818 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
5820 bool hasMemory = false;
5822 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5823 unsigned ResNo = 0; // ResNo - The result number of the next output.
5824 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5825 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5826 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5828 MVT OpVT = MVT::Other;
5830 // Compute the value type for each operand.
5831 switch (OpInfo.Type) {
5832 case InlineAsm::isOutput:
5833 // Indirect outputs just consume an argument.
5834 if (OpInfo.isIndirect) {
5835 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5839 // The return value of the call is this value. As such, there is no
5840 // corresponding argument.
5841 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5842 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5843 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
5845 assert(ResNo == 0 && "Asm only has one result!");
5846 OpVT = TLI.getSimpleValueType(CS.getType());
5850 case InlineAsm::isInput:
5851 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5853 case InlineAsm::isClobber:
5858 // If this is an input or an indirect output, process the call argument.
5859 // BasicBlocks are labels, currently appearing only in asm's.
5860 if (OpInfo.CallOperandVal) {
5861 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5862 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5864 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5868 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
5871 OpInfo.ConstraintVT = OpVT;
5873 // Indirect operand accesses access memory.
5874 if (OpInfo.isIndirect)
5877 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5878 TargetLowering::ConstraintType
5879 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5880 if (CType == TargetLowering::C_Memory) {
5888 SDValue Chain, Flag;
5890 // We won't need to flush pending loads if this asm doesn't touch
5891 // memory and is nonvolatile.
5892 if (hasMemory || IA->hasSideEffects())
5895 Chain = DAG.getRoot();
5897 // Second pass over the constraints: compute which constraint option to use
5898 // and assign registers to constraints that want a specific physreg.
5899 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5900 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5902 // If this is an output operand with a matching input operand, look up the
5903 // matching input. If their types mismatch, e.g. one is an integer, the
5904 // other is floating point, or their sizes are different, flag it as an
5906 if (OpInfo.hasMatchingInput()) {
5907 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5909 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5910 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
5911 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
5912 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
5913 OpInfo.ConstraintVT);
5914 std::pair<unsigned, const TargetRegisterClass *> InputRC =
5915 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
5916 Input.ConstraintVT);
5917 if ((OpInfo.ConstraintVT.isInteger() !=
5918 Input.ConstraintVT.isInteger()) ||
5919 (MatchRC.second != InputRC.second)) {
5920 report_fatal_error("Unsupported asm: input constraint"
5921 " with a matching output constraint of"
5922 " incompatible type!");
5924 Input.ConstraintVT = OpInfo.ConstraintVT;
5928 // Compute the constraint code and ConstraintType to use.
5929 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5931 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5932 OpInfo.Type == InlineAsm::isClobber)
5935 // If this is a memory input, and if the operand is not indirect, do what we
5936 // need to to provide an address for the memory input.
5937 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5938 !OpInfo.isIndirect) {
5939 assert((OpInfo.isMultipleAlternative ||
5940 (OpInfo.Type == InlineAsm::isInput)) &&
5941 "Can only indirectify direct input operands!");
5943 // Memory operands really want the address of the value. If we don't have
5944 // an indirect input, put it in the constpool if we can, otherwise spill
5945 // it to a stack slot.
5946 // TODO: This isn't quite right. We need to handle these according to
5947 // the addressing mode that the constraint wants. Also, this may take
5948 // an additional register for the computation and we don't want that
5951 // If the operand is a float, integer, or vector constant, spill to a
5952 // constant pool entry to get its address.
5953 const Value *OpVal = OpInfo.CallOperandVal;
5954 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5955 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5956 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5957 TLI.getPointerTy());
5959 // Otherwise, create a stack slot and emit a store to it before the
5961 Type *Ty = OpVal->getType();
5962 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5963 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5964 MachineFunction &MF = DAG.getMachineFunction();
5965 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5966 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5967 Chain = DAG.getStore(Chain, getCurSDLoc(),
5968 OpInfo.CallOperand, StackSlot,
5969 MachinePointerInfo::getFixedStack(SSFI),
5971 OpInfo.CallOperand = StackSlot;
5974 // There is no longer a Value* corresponding to this operand.
5975 OpInfo.CallOperandVal = nullptr;
5977 // It is now an indirect operand.
5978 OpInfo.isIndirect = true;
5981 // If this constraint is for a specific register, allocate it before
5983 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5984 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
5987 // Second pass - Loop over all of the operands, assigning virtual or physregs
5988 // to register class operands.
5989 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5990 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5992 // C_Register operands have already been allocated, Other/Memory don't need
5994 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5995 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
5998 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5999 std::vector<SDValue> AsmNodeOperands;
6000 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6001 AsmNodeOperands.push_back(
6002 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6003 TLI.getPointerTy()));
6005 // If we have a !srcloc metadata node associated with it, we want to attach
6006 // this to the ultimately generated inline asm machineinstr. To do this, we
6007 // pass in the third operand as this (potentially null) inline asm MDNode.
6008 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6009 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6011 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6012 // bits as operand 3.
6013 unsigned ExtraInfo = 0;
6014 if (IA->hasSideEffects())
6015 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6016 if (IA->isAlignStack())
6017 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6018 // Set the asm dialect.
6019 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6021 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6022 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6023 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6025 // Compute the constraint code and ConstraintType to use.
6026 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6028 // Ideally, we would only check against memory constraints. However, the
6029 // meaning of an other constraint can be target-specific and we can't easily
6030 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6031 // for other constriants as well.
6032 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6033 OpInfo.ConstraintType == TargetLowering::C_Other) {
6034 if (OpInfo.Type == InlineAsm::isInput)
6035 ExtraInfo |= InlineAsm::Extra_MayLoad;
6036 else if (OpInfo.Type == InlineAsm::isOutput)
6037 ExtraInfo |= InlineAsm::Extra_MayStore;
6038 else if (OpInfo.Type == InlineAsm::isClobber)
6039 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6043 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6044 TLI.getPointerTy()));
6046 // Loop over all of the inputs, copying the operand values into the
6047 // appropriate registers and processing the output regs.
6048 RegsForValue RetValRegs;
6050 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6051 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6053 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6054 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6056 switch (OpInfo.Type) {
6057 case InlineAsm::isOutput: {
6058 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6059 OpInfo.ConstraintType != TargetLowering::C_Register) {
6060 // Memory output, or 'other' output (e.g. 'X' constraint).
6061 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6063 unsigned ConstraintID =
6064 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6065 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6066 "Failed to convert memory constraint code to constraint id.");
6068 // Add information to the INLINEASM node to know about this output.
6069 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6070 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6071 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, MVT::i32));
6072 AsmNodeOperands.push_back(OpInfo.CallOperand);
6076 // Otherwise, this is a register or register class output.
6078 // Copy the output from the appropriate register. Find a register that
6080 if (OpInfo.AssignedRegs.Regs.empty()) {
6081 LLVMContext &Ctx = *DAG.getContext();
6082 Ctx.emitError(CS.getInstruction(),
6083 "couldn't allocate output register for constraint '" +
6084 Twine(OpInfo.ConstraintCode) + "'");
6088 // If this is an indirect operand, store through the pointer after the
6090 if (OpInfo.isIndirect) {
6091 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6092 OpInfo.CallOperandVal));
6094 // This is the result value of the call.
6095 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6096 // Concatenate this output onto the outputs list.
6097 RetValRegs.append(OpInfo.AssignedRegs);
6100 // Add information to the INLINEASM node to know that this register is
6103 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6104 ? InlineAsm::Kind_RegDefEarlyClobber
6105 : InlineAsm::Kind_RegDef,
6106 false, 0, DAG, AsmNodeOperands);
6109 case InlineAsm::isInput: {
6110 SDValue InOperandVal = OpInfo.CallOperand;
6112 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6113 // If this is required to match an output register we have already set,
6114 // just use its register.
6115 unsigned OperandNo = OpInfo.getMatchedOperand();
6117 // Scan until we find the definition we already emitted of this operand.
6118 // When we find it, create a RegsForValue operand.
6119 unsigned CurOp = InlineAsm::Op_FirstOperand;
6120 for (; OperandNo; --OperandNo) {
6121 // Advance to the next operand.
6123 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6124 assert((InlineAsm::isRegDefKind(OpFlag) ||
6125 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6126 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6127 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6131 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6132 if (InlineAsm::isRegDefKind(OpFlag) ||
6133 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6134 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6135 if (OpInfo.isIndirect) {
6136 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6137 LLVMContext &Ctx = *DAG.getContext();
6138 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6139 " don't know how to handle tied "
6140 "indirect register inputs");
6144 RegsForValue MatchedRegs;
6145 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6146 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6147 MatchedRegs.RegVTs.push_back(RegVT);
6148 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6149 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6151 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6152 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6154 LLVMContext &Ctx = *DAG.getContext();
6155 Ctx.emitError(CS.getInstruction(),
6156 "inline asm error: This value"
6157 " type register class is not natively supported!");
6161 // Use the produced MatchedRegs object to
6162 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6163 Chain, &Flag, CS.getInstruction());
6164 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6165 true, OpInfo.getMatchedOperand(),
6166 DAG, AsmNodeOperands);
6170 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6171 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6172 "Unexpected number of operands");
6173 // Add information to the INLINEASM node to know about this input.
6174 // See InlineAsm.h isUseOperandTiedToDef.
6175 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6176 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6177 OpInfo.getMatchedOperand());
6178 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6179 TLI.getPointerTy()));
6180 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6184 // Treat indirect 'X' constraint as memory.
6185 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6187 OpInfo.ConstraintType = TargetLowering::C_Memory;
6189 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6190 std::vector<SDValue> Ops;
6191 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6194 LLVMContext &Ctx = *DAG.getContext();
6195 Ctx.emitError(CS.getInstruction(),
6196 "invalid operand for inline asm constraint '" +
6197 Twine(OpInfo.ConstraintCode) + "'");
6201 // Add information to the INLINEASM node to know about this input.
6202 unsigned ResOpType =
6203 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6204 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6205 TLI.getPointerTy()));
6206 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6210 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6211 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6212 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6213 "Memory operands expect pointer values");
6215 unsigned ConstraintID =
6216 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6217 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6218 "Failed to convert memory constraint code to constraint id.");
6220 // Add information to the INLINEASM node to know about this input.
6221 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6222 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6223 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, MVT::i32));
6224 AsmNodeOperands.push_back(InOperandVal);
6228 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6229 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6230 "Unknown constraint type!");
6232 // TODO: Support this.
6233 if (OpInfo.isIndirect) {
6234 LLVMContext &Ctx = *DAG.getContext();
6235 Ctx.emitError(CS.getInstruction(),
6236 "Don't know how to handle indirect register inputs yet "
6237 "for constraint '" +
6238 Twine(OpInfo.ConstraintCode) + "'");
6242 // Copy the input into the appropriate registers.
6243 if (OpInfo.AssignedRegs.Regs.empty()) {
6244 LLVMContext &Ctx = *DAG.getContext();
6245 Ctx.emitError(CS.getInstruction(),
6246 "couldn't allocate input reg for constraint '" +
6247 Twine(OpInfo.ConstraintCode) + "'");
6251 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6252 Chain, &Flag, CS.getInstruction());
6254 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6255 DAG, AsmNodeOperands);
6258 case InlineAsm::isClobber: {
6259 // Add the clobbered value to the operand list, so that the register
6260 // allocator is aware that the physreg got clobbered.
6261 if (!OpInfo.AssignedRegs.Regs.empty())
6262 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6270 // Finish up input operands. Set the input chain and add the flag last.
6271 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6272 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6274 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6275 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6276 Flag = Chain.getValue(1);
6278 // If this asm returns a register value, copy the result from that register
6279 // and set it as the value of the call.
6280 if (!RetValRegs.Regs.empty()) {
6281 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6282 Chain, &Flag, CS.getInstruction());
6284 // FIXME: Why don't we do this for inline asms with MRVs?
6285 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6286 EVT ResultType = TLI.getValueType(CS.getType());
6288 // If any of the results of the inline asm is a vector, it may have the
6289 // wrong width/num elts. This can happen for register classes that can
6290 // contain multiple different value types. The preg or vreg allocated may
6291 // not have the same VT as was expected. Convert it to the right type
6292 // with bit_convert.
6293 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6294 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6297 } else if (ResultType != Val.getValueType() &&
6298 ResultType.isInteger() && Val.getValueType().isInteger()) {
6299 // If a result value was tied to an input value, the computed result may
6300 // have a wider width than the expected result. Extract the relevant
6302 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6305 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6308 setValue(CS.getInstruction(), Val);
6309 // Don't need to use this as a chain in this case.
6310 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6314 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6316 // Process indirect outputs, first output all of the flagged copies out of
6318 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6319 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6320 const Value *Ptr = IndirectStoresToEmit[i].second;
6321 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6323 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6326 // Emit the non-flagged stores from the physregs.
6327 SmallVector<SDValue, 8> OutChains;
6328 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6329 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6330 StoresToEmit[i].first,
6331 getValue(StoresToEmit[i].second),
6332 MachinePointerInfo(StoresToEmit[i].second),
6334 OutChains.push_back(Val);
6337 if (!OutChains.empty())
6338 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6343 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6344 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6345 MVT::Other, getRoot(),
6346 getValue(I.getArgOperand(0)),
6347 DAG.getSrcValue(I.getArgOperand(0))));
6350 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6351 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6352 const DataLayout &DL = *TLI.getDataLayout();
6353 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6354 getRoot(), getValue(I.getOperand(0)),
6355 DAG.getSrcValue(I.getOperand(0)),
6356 DL.getABITypeAlignment(I.getType()));
6358 DAG.setRoot(V.getValue(1));
6361 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6362 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6363 MVT::Other, getRoot(),
6364 getValue(I.getArgOperand(0)),
6365 DAG.getSrcValue(I.getArgOperand(0))));
6368 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6369 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6370 MVT::Other, getRoot(),
6371 getValue(I.getArgOperand(0)),
6372 getValue(I.getArgOperand(1)),
6373 DAG.getSrcValue(I.getArgOperand(0)),
6374 DAG.getSrcValue(I.getArgOperand(1))));
6377 /// \brief Lower an argument list according to the target calling convention.
6379 /// \return A tuple of <return-value, token-chain>
6381 /// This is a helper for lowering intrinsics that follow a target calling
6382 /// convention or require stack pointer adjustment. Only a subset of the
6383 /// intrinsic's operands need to participate in the calling convention.
6384 std::pair<SDValue, SDValue>
6385 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6386 unsigned NumArgs, SDValue Callee,
6388 MachineBasicBlock *LandingPad,
6389 bool IsPatchPoint) {
6390 TargetLowering::ArgListTy Args;
6391 Args.reserve(NumArgs);
6393 // Populate the argument list.
6394 // Attributes for args start at offset 1, after the return attribute.
6395 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6396 ArgI != ArgE; ++ArgI) {
6397 const Value *V = CS->getOperand(ArgI);
6399 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6401 TargetLowering::ArgListEntry Entry;
6402 Entry.Node = getValue(V);
6403 Entry.Ty = V->getType();
6404 Entry.setAttributes(&CS, AttrI);
6405 Args.push_back(Entry);
6408 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6409 TargetLowering::CallLoweringInfo CLI(DAG);
6410 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6411 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6412 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6414 return lowerInvokable(CLI, LandingPad);
6417 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6418 /// or patchpoint target node's operand list.
6420 /// Constants are converted to TargetConstants purely as an optimization to
6421 /// avoid constant materialization and register allocation.
6423 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6424 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6425 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6426 /// address materialization and register allocation, but may also be required
6427 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6428 /// alloca in the entry block, then the runtime may assume that the alloca's
6429 /// StackMap location can be read immediately after compilation and that the
6430 /// location is valid at any point during execution (this is similar to the
6431 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6432 /// only available in a register, then the runtime would need to trap when
6433 /// execution reaches the StackMap in order to read the alloca's location.
6434 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6435 SmallVectorImpl<SDValue> &Ops,
6436 SelectionDAGBuilder &Builder) {
6437 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6438 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6439 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6441 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6443 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6444 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6445 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6447 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6449 Ops.push_back(OpVal);
6453 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6454 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6455 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6456 // [live variables...])
6458 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6460 SDValue Chain, InFlag, Callee, NullPtr;
6461 SmallVector<SDValue, 32> Ops;
6463 SDLoc DL = getCurSDLoc();
6464 Callee = getValue(CI.getCalledValue());
6465 NullPtr = DAG.getIntPtrConstant(0, true);
6467 // The stackmap intrinsic only records the live variables (the arguemnts
6468 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6469 // intrinsic, this won't be lowered to a function call. This means we don't
6470 // have to worry about calling conventions and target specific lowering code.
6471 // Instead we perform the call lowering right here.
6473 // chain, flag = CALLSEQ_START(chain, 0)
6474 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6475 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6477 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6478 InFlag = Chain.getValue(1);
6480 // Add the <id> and <numBytes> constants.
6481 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6482 Ops.push_back(DAG.getTargetConstant(
6483 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6484 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6485 Ops.push_back(DAG.getTargetConstant(
6486 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6488 // Push live variables for the stack map.
6489 addStackMapLiveVars(&CI, 2, Ops, *this);
6491 // We are not pushing any register mask info here on the operands list,
6492 // because the stackmap doesn't clobber anything.
6494 // Push the chain and the glue flag.
6495 Ops.push_back(Chain);
6496 Ops.push_back(InFlag);
6498 // Create the STACKMAP node.
6499 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6500 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6501 Chain = SDValue(SM, 0);
6502 InFlag = Chain.getValue(1);
6504 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6506 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6508 // Set the root to the target-lowered call chain.
6511 // Inform the Frame Information that we have a stackmap in this function.
6512 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6515 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6516 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6517 MachineBasicBlock *LandingPad) {
6518 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6523 // [live variables...])
6525 CallingConv::ID CC = CS.getCallingConv();
6526 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6527 bool HasDef = !CS->getType()->isVoidTy();
6528 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6530 // Handle immediate and symbolic callees.
6531 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6532 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(),
6534 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6535 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6536 SDLoc(SymbolicCallee),
6537 SymbolicCallee->getValueType(0));
6539 // Get the real number of arguments participating in the call <numArgs>
6540 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6541 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6543 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6544 // Intrinsics include all meta-operands up to but not including CC.
6545 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6546 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6547 "Not enough arguments provided to the patchpoint intrinsic");
6549 // For AnyRegCC the arguments are lowered later on manually.
6550 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6551 std::pair<SDValue, SDValue> Result =
6552 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
6555 SDNode *CallEnd = Result.second.getNode();
6556 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6557 CallEnd = CallEnd->getOperand(0).getNode();
6559 /// Get a call instruction from the call sequence chain.
6560 /// Tail calls are not allowed.
6561 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6562 "Expected a callseq node.");
6563 SDNode *Call = CallEnd->getOperand(0).getNode();
6564 bool HasGlue = Call->getGluedNode();
6566 // Replace the target specific call node with the patchable intrinsic.
6567 SmallVector<SDValue, 8> Ops;
6569 // Add the <id> and <numBytes> constants.
6570 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6571 Ops.push_back(DAG.getTargetConstant(
6572 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6573 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6574 Ops.push_back(DAG.getTargetConstant(
6575 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6578 Ops.push_back(Callee);
6580 // Adjust <numArgs> to account for any arguments that have been passed on the
6582 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6583 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6584 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6585 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
6587 // Add the calling convention
6588 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
6590 // Add the arguments we omitted previously. The register allocator should
6591 // place these in any free register.
6593 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6594 Ops.push_back(getValue(CS.getArgument(i)));
6596 // Push the arguments from the call instruction up to the register mask.
6597 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6598 Ops.append(Call->op_begin() + 2, e);
6600 // Push live variables for the stack map.
6601 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this);
6603 // Push the register mask info.
6605 Ops.push_back(*(Call->op_end()-2));
6607 Ops.push_back(*(Call->op_end()-1));
6609 // Push the chain (this is originally the first operand of the call, but
6610 // becomes now the last or second to last operand).
6611 Ops.push_back(*(Call->op_begin()));
6613 // Push the glue flag (last operand).
6615 Ops.push_back(*(Call->op_end()-1));
6618 if (IsAnyRegCC && HasDef) {
6619 // Create the return types based on the intrinsic definition
6620 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6621 SmallVector<EVT, 3> ValueVTs;
6622 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
6623 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6625 // There is always a chain and a glue type at the end
6626 ValueVTs.push_back(MVT::Other);
6627 ValueVTs.push_back(MVT::Glue);
6628 NodeTys = DAG.getVTList(ValueVTs);
6630 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6632 // Replace the target specific call node with a PATCHPOINT node.
6633 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6634 getCurSDLoc(), NodeTys, Ops);
6636 // Update the NodeMap.
6639 setValue(CS.getInstruction(), SDValue(MN, 0));
6641 setValue(CS.getInstruction(), Result.first);
6644 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6645 // call sequence. Furthermore the location of the chain and glue can change
6646 // when the AnyReg calling convention is used and the intrinsic returns a
6648 if (IsAnyRegCC && HasDef) {
6649 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6650 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6651 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6653 DAG.ReplaceAllUsesWith(Call, MN);
6654 DAG.DeleteNode(Call);
6656 // Inform the Frame Information that we have a patchpoint in this function.
6657 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6660 /// Returns an AttributeSet representing the attributes applied to the return
6661 /// value of the given call.
6662 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6663 SmallVector<Attribute::AttrKind, 2> Attrs;
6665 Attrs.push_back(Attribute::SExt);
6667 Attrs.push_back(Attribute::ZExt);
6669 Attrs.push_back(Attribute::InReg);
6671 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6675 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6676 /// implementation, which just calls LowerCall.
6677 /// FIXME: When all targets are
6678 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6679 std::pair<SDValue, SDValue>
6680 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6681 // Handle the incoming return values from the call.
6683 Type *OrigRetTy = CLI.RetTy;
6684 SmallVector<EVT, 4> RetTys;
6685 SmallVector<uint64_t, 4> Offsets;
6686 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
6688 SmallVector<ISD::OutputArg, 4> Outs;
6689 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
6691 bool CanLowerReturn =
6692 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6693 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6695 SDValue DemoteStackSlot;
6696 int DemoteStackIdx = -100;
6697 if (!CanLowerReturn) {
6698 // FIXME: equivalent assert?
6699 // assert(!CS.hasInAllocaArgument() &&
6700 // "sret demotion is incompatible with inalloca");
6701 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
6702 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
6703 MachineFunction &MF = CLI.DAG.getMachineFunction();
6704 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6705 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6707 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
6709 Entry.Node = DemoteStackSlot;
6710 Entry.Ty = StackSlotPtrType;
6711 Entry.isSExt = false;
6712 Entry.isZExt = false;
6713 Entry.isInReg = false;
6714 Entry.isSRet = true;
6715 Entry.isNest = false;
6716 Entry.isByVal = false;
6717 Entry.isReturned = false;
6718 Entry.Alignment = Align;
6719 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6720 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6722 // sret demotion isn't compatible with tail-calls, since the sret argument
6723 // points into the callers stack frame.
6724 CLI.IsTailCall = false;
6726 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6728 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6729 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6730 for (unsigned i = 0; i != NumRegs; ++i) {
6731 ISD::InputArg MyFlags;
6732 MyFlags.VT = RegisterVT;
6734 MyFlags.Used = CLI.IsReturnValueUsed;
6736 MyFlags.Flags.setSExt();
6738 MyFlags.Flags.setZExt();
6740 MyFlags.Flags.setInReg();
6741 CLI.Ins.push_back(MyFlags);
6746 // Handle all of the outgoing arguments.
6748 CLI.OutVals.clear();
6749 ArgListTy &Args = CLI.getArgs();
6750 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6751 SmallVector<EVT, 4> ValueVTs;
6752 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6753 Type *FinalType = Args[i].Ty;
6754 if (Args[i].isByVal)
6755 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6756 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6757 FinalType, CLI.CallConv, CLI.IsVarArg);
6758 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6760 EVT VT = ValueVTs[Value];
6761 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6762 SDValue Op = SDValue(Args[i].Node.getNode(),
6763 Args[i].Node.getResNo() + Value);
6764 ISD::ArgFlagsTy Flags;
6765 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
6771 if (Args[i].isInReg)
6775 if (Args[i].isByVal)
6777 if (Args[i].isInAlloca) {
6778 Flags.setInAlloca();
6779 // Set the byval flag for CCAssignFn callbacks that don't know about
6780 // inalloca. This way we can know how many bytes we should've allocated
6781 // and how many bytes a callee cleanup function will pop. If we port
6782 // inalloca to more targets, we'll have to add custom inalloca handling
6783 // in the various CC lowering callbacks.
6786 if (Args[i].isByVal || Args[i].isInAlloca) {
6787 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6788 Type *ElementTy = Ty->getElementType();
6789 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6790 // For ByVal, alignment should come from FE. BE will guess if this
6791 // info is not there but there are cases it cannot get right.
6792 unsigned FrameAlign;
6793 if (Args[i].Alignment)
6794 FrameAlign = Args[i].Alignment;
6796 FrameAlign = getByValTypeAlignment(ElementTy);
6797 Flags.setByValAlign(FrameAlign);
6802 Flags.setInConsecutiveRegs();
6803 Flags.setOrigAlign(OriginalAlignment);
6805 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6806 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6807 SmallVector<SDValue, 4> Parts(NumParts);
6808 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6811 ExtendKind = ISD::SIGN_EXTEND;
6812 else if (Args[i].isZExt)
6813 ExtendKind = ISD::ZERO_EXTEND;
6815 // Conservatively only handle 'returned' on non-vectors for now
6816 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6817 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6818 "unexpected use of 'returned'");
6819 // Before passing 'returned' to the target lowering code, ensure that
6820 // either the register MVT and the actual EVT are the same size or that
6821 // the return value and argument are extended in the same way; in these
6822 // cases it's safe to pass the argument register value unchanged as the
6823 // return register value (although it's at the target's option whether
6825 // TODO: allow code generation to take advantage of partially preserved
6826 // registers rather than clobbering the entire register when the
6827 // parameter extension method is not compatible with the return
6829 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6830 (ExtendKind != ISD::ANY_EXTEND &&
6831 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6832 Flags.setReturned();
6835 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6836 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6838 for (unsigned j = 0; j != NumParts; ++j) {
6839 // if it isn't first piece, alignment must be 1
6840 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
6841 i < CLI.NumFixedArgs,
6842 i, j*Parts[j].getValueType().getStoreSize());
6843 if (NumParts > 1 && j == 0)
6844 MyFlags.Flags.setSplit();
6846 MyFlags.Flags.setOrigAlign(1);
6848 CLI.Outs.push_back(MyFlags);
6849 CLI.OutVals.push_back(Parts[j]);
6852 if (NeedsRegBlock && Value == NumValues - 1)
6853 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
6857 SmallVector<SDValue, 4> InVals;
6858 CLI.Chain = LowerCall(CLI, InVals);
6860 // Verify that the target's LowerCall behaved as expected.
6861 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6862 "LowerCall didn't return a valid chain!");
6863 assert((!CLI.IsTailCall || InVals.empty()) &&
6864 "LowerCall emitted a return value for a tail call!");
6865 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6866 "LowerCall didn't emit the correct number of values!");
6868 // For a tail call, the return value is merely live-out and there aren't
6869 // any nodes in the DAG representing it. Return a special value to
6870 // indicate that a tail call has been emitted and no more Instructions
6871 // should be processed in the current block.
6872 if (CLI.IsTailCall) {
6873 CLI.DAG.setRoot(CLI.Chain);
6874 return std::make_pair(SDValue(), SDValue());
6877 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6878 assert(InVals[i].getNode() &&
6879 "LowerCall emitted a null value!");
6880 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6881 "LowerCall emitted a value with the wrong type!");
6884 SmallVector<SDValue, 4> ReturnValues;
6885 if (!CanLowerReturn) {
6886 // The instruction result is the result of loading from the
6887 // hidden sret parameter.
6888 SmallVector<EVT, 1> PVTs;
6889 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
6891 ComputeValueVTs(*this, PtrRetTy, PVTs);
6892 assert(PVTs.size() == 1 && "Pointers should fit in one register");
6893 EVT PtrVT = PVTs[0];
6895 unsigned NumValues = RetTys.size();
6896 ReturnValues.resize(NumValues);
6897 SmallVector<SDValue, 4> Chains(NumValues);
6899 for (unsigned i = 0; i < NumValues; ++i) {
6900 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
6901 CLI.DAG.getConstant(Offsets[i], PtrVT));
6902 SDValue L = CLI.DAG.getLoad(
6903 RetTys[i], CLI.DL, CLI.Chain, Add,
6904 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
6906 ReturnValues[i] = L;
6907 Chains[i] = L.getValue(1);
6910 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
6912 // Collect the legal value parts into potentially illegal values
6913 // that correspond to the original function's return values.
6914 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6916 AssertOp = ISD::AssertSext;
6917 else if (CLI.RetZExt)
6918 AssertOp = ISD::AssertZext;
6919 unsigned CurReg = 0;
6920 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6922 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6923 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6925 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6926 NumRegs, RegisterVT, VT, nullptr,
6931 // For a function returning void, there is no return value. We can't create
6932 // such a node, so we just return a null return value in that case. In
6933 // that case, nothing will actually look at the value.
6934 if (ReturnValues.empty())
6935 return std::make_pair(SDValue(), CLI.Chain);
6938 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6939 CLI.DAG.getVTList(RetTys), ReturnValues);
6940 return std::make_pair(Res, CLI.Chain);
6943 void TargetLowering::LowerOperationWrapper(SDNode *N,
6944 SmallVectorImpl<SDValue> &Results,
6945 SelectionDAG &DAG) const {
6946 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6948 Results.push_back(Res);
6951 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6952 llvm_unreachable("LowerOperation not implemented for this target!");
6956 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6957 SDValue Op = getNonRegisterValue(V);
6958 assert((Op.getOpcode() != ISD::CopyFromReg ||
6959 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6960 "Copy from a reg to the same reg!");
6961 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6963 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6964 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6965 SDValue Chain = DAG.getEntryNode();
6967 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
6968 FuncInfo.PreferredExtendType.end())
6970 : FuncInfo.PreferredExtendType[V];
6971 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
6972 PendingExports.push_back(Chain);
6975 #include "llvm/CodeGen/SelectionDAGISel.h"
6977 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6978 /// entry block, return true. This includes arguments used by switches, since
6979 /// the switch may expand into multiple basic blocks.
6980 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6981 // With FastISel active, we may be splitting blocks, so force creation
6982 // of virtual registers for all non-dead arguments.
6984 return A->use_empty();
6986 const BasicBlock *Entry = A->getParent()->begin();
6987 for (const User *U : A->users())
6988 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6989 return false; // Use not in entry block.
6994 void SelectionDAGISel::LowerArguments(const Function &F) {
6995 SelectionDAG &DAG = SDB->DAG;
6996 SDLoc dl = SDB->getCurSDLoc();
6997 const DataLayout *DL = TLI->getDataLayout();
6998 SmallVector<ISD::InputArg, 16> Ins;
7000 if (!FuncInfo->CanLowerReturn) {
7001 // Put in an sret pointer parameter before all the other parameters.
7002 SmallVector<EVT, 1> ValueVTs;
7003 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7005 // NOTE: Assuming that a pointer will never break down to more than one VT
7007 ISD::ArgFlagsTy Flags;
7009 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7010 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7011 ISD::InputArg::NoArgIndex, 0);
7012 Ins.push_back(RetArg);
7015 // Set up the incoming argument description vector.
7017 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7018 I != E; ++I, ++Idx) {
7019 SmallVector<EVT, 4> ValueVTs;
7020 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7021 bool isArgValueUsed = !I->use_empty();
7022 unsigned PartBase = 0;
7023 Type *FinalType = I->getType();
7024 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7025 FinalType = cast<PointerType>(FinalType)->getElementType();
7026 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7027 FinalType, F.getCallingConv(), F.isVarArg());
7028 for (unsigned Value = 0, NumValues = ValueVTs.size();
7029 Value != NumValues; ++Value) {
7030 EVT VT = ValueVTs[Value];
7031 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7032 ISD::ArgFlagsTy Flags;
7033 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7035 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7037 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7039 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7041 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7043 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7045 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7046 Flags.setInAlloca();
7047 // Set the byval flag for CCAssignFn callbacks that don't know about
7048 // inalloca. This way we can know how many bytes we should've allocated
7049 // and how many bytes a callee cleanup function will pop. If we port
7050 // inalloca to more targets, we'll have to add custom inalloca handling
7051 // in the various CC lowering callbacks.
7054 if (Flags.isByVal() || Flags.isInAlloca()) {
7055 PointerType *Ty = cast<PointerType>(I->getType());
7056 Type *ElementTy = Ty->getElementType();
7057 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7058 // For ByVal, alignment should be passed from FE. BE will guess if
7059 // this info is not there but there are cases it cannot get right.
7060 unsigned FrameAlign;
7061 if (F.getParamAlignment(Idx))
7062 FrameAlign = F.getParamAlignment(Idx);
7064 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7065 Flags.setByValAlign(FrameAlign);
7067 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7070 Flags.setInConsecutiveRegs();
7071 Flags.setOrigAlign(OriginalAlignment);
7073 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7074 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7075 for (unsigned i = 0; i != NumRegs; ++i) {
7076 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7077 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7078 if (NumRegs > 1 && i == 0)
7079 MyFlags.Flags.setSplit();
7080 // if it isn't first piece, alignment must be 1
7082 MyFlags.Flags.setOrigAlign(1);
7083 Ins.push_back(MyFlags);
7085 if (NeedsRegBlock && Value == NumValues - 1)
7086 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7087 PartBase += VT.getStoreSize();
7091 // Call the target to set up the argument values.
7092 SmallVector<SDValue, 8> InVals;
7093 SDValue NewRoot = TLI->LowerFormalArguments(
7094 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7096 // Verify that the target's LowerFormalArguments behaved as expected.
7097 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7098 "LowerFormalArguments didn't return a valid chain!");
7099 assert(InVals.size() == Ins.size() &&
7100 "LowerFormalArguments didn't emit the correct number of values!");
7102 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7103 assert(InVals[i].getNode() &&
7104 "LowerFormalArguments emitted a null value!");
7105 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7106 "LowerFormalArguments emitted a value with the wrong type!");
7110 // Update the DAG with the new chain value resulting from argument lowering.
7111 DAG.setRoot(NewRoot);
7113 // Set up the argument values.
7116 if (!FuncInfo->CanLowerReturn) {
7117 // Create a virtual register for the sret pointer, and put in a copy
7118 // from the sret argument into it.
7119 SmallVector<EVT, 1> ValueVTs;
7120 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7121 MVT VT = ValueVTs[0].getSimpleVT();
7122 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7123 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7124 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7125 RegVT, VT, nullptr, AssertOp);
7127 MachineFunction& MF = SDB->DAG.getMachineFunction();
7128 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7129 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7130 FuncInfo->DemoteRegister = SRetReg;
7132 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7133 DAG.setRoot(NewRoot);
7135 // i indexes lowered arguments. Bump it past the hidden sret argument.
7136 // Idx indexes LLVM arguments. Don't touch it.
7140 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7142 SmallVector<SDValue, 4> ArgValues;
7143 SmallVector<EVT, 4> ValueVTs;
7144 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7145 unsigned NumValues = ValueVTs.size();
7147 // If this argument is unused then remember its value. It is used to generate
7148 // debugging information.
7149 if (I->use_empty() && NumValues) {
7150 SDB->setUnusedArgValue(I, InVals[i]);
7152 // Also remember any frame index for use in FastISel.
7153 if (FrameIndexSDNode *FI =
7154 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7155 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7158 for (unsigned Val = 0; Val != NumValues; ++Val) {
7159 EVT VT = ValueVTs[Val];
7160 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7161 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7163 if (!I->use_empty()) {
7164 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7165 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7166 AssertOp = ISD::AssertSext;
7167 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7168 AssertOp = ISD::AssertZext;
7170 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7171 NumParts, PartVT, VT,
7172 nullptr, AssertOp));
7178 // We don't need to do anything else for unused arguments.
7179 if (ArgValues.empty())
7182 // Note down frame index.
7183 if (FrameIndexSDNode *FI =
7184 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7185 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7187 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7188 SDB->getCurSDLoc());
7190 SDB->setValue(I, Res);
7191 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7192 if (LoadSDNode *LNode =
7193 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7194 if (FrameIndexSDNode *FI =
7195 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7196 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7199 // If this argument is live outside of the entry block, insert a copy from
7200 // wherever we got it to the vreg that other BB's will reference it as.
7201 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7202 // If we can, though, try to skip creating an unnecessary vreg.
7203 // FIXME: This isn't very clean... it would be nice to make this more
7204 // general. It's also subtly incompatible with the hacks FastISel
7206 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7207 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7208 FuncInfo->ValueMap[I] = Reg;
7212 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7213 FuncInfo->InitializeRegForValue(I);
7214 SDB->CopyToExportRegsIfNeeded(I);
7218 assert(i == InVals.size() && "Argument register count mismatch!");
7220 // Finally, if the target has anything special to do, allow it to do so.
7221 EmitFunctionEntryCode();
7224 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7225 /// ensure constants are generated when needed. Remember the virtual registers
7226 /// that need to be added to the Machine PHI nodes as input. We cannot just
7227 /// directly add them, because expansion might result in multiple MBB's for one
7228 /// BB. As such, the start of the BB might correspond to a different MBB than
7232 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7233 const TerminatorInst *TI = LLVMBB->getTerminator();
7235 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7237 // Check PHI nodes in successors that expect a value to be available from this
7239 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7240 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7241 if (!isa<PHINode>(SuccBB->begin())) continue;
7242 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7244 // If this terminator has multiple identical successors (common for
7245 // switches), only handle each succ once.
7246 if (!SuccsHandled.insert(SuccMBB).second)
7249 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7251 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7252 // nodes and Machine PHI nodes, but the incoming operands have not been
7254 for (BasicBlock::const_iterator I = SuccBB->begin();
7255 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7256 // Ignore dead phi's.
7257 if (PN->use_empty()) continue;
7260 if (PN->getType()->isEmptyTy())
7264 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7266 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7267 unsigned &RegOut = ConstantsOut[C];
7269 RegOut = FuncInfo.CreateRegs(C->getType());
7270 CopyValueToVirtualRegister(C, RegOut);
7274 DenseMap<const Value *, unsigned>::iterator I =
7275 FuncInfo.ValueMap.find(PHIOp);
7276 if (I != FuncInfo.ValueMap.end())
7279 assert(isa<AllocaInst>(PHIOp) &&
7280 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7281 "Didn't codegen value into a register!??");
7282 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7283 CopyValueToVirtualRegister(PHIOp, Reg);
7287 // Remember that this register needs to added to the machine PHI node as
7288 // the input for this MBB.
7289 SmallVector<EVT, 4> ValueVTs;
7290 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7291 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7292 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7293 EVT VT = ValueVTs[vti];
7294 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7295 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7296 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7297 Reg += NumRegisters;
7302 ConstantsOut.clear();
7305 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7308 SelectionDAGBuilder::StackProtectorDescriptor::
7309 AddSuccessorMBB(const BasicBlock *BB,
7310 MachineBasicBlock *ParentMBB,
7312 MachineBasicBlock *SuccMBB) {
7313 // If SuccBB has not been created yet, create it.
7315 MachineFunction *MF = ParentMBB->getParent();
7316 MachineFunction::iterator BBI = ParentMBB;
7317 SuccMBB = MF->CreateMachineBasicBlock(BB);
7318 MF->insert(++BBI, SuccMBB);
7320 // Add it as a successor of ParentMBB.
7321 ParentMBB->addSuccessor(
7322 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7326 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7327 MachineFunction::iterator I = MBB;
7328 if (++I == FuncInfo.MF->end())
7333 /// During lowering new call nodes can be created (such as memset, etc.).
7334 /// Those will become new roots of the current DAG, but complications arise
7335 /// when they are tail calls. In such cases, the call lowering will update
7336 /// the root, but the builder still needs to know that a tail call has been
7337 /// lowered in order to avoid generating an additional return.
7338 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7339 // If the node is null, we do have a tail call.
7340 if (MaybeTC.getNode() != nullptr)
7341 DAG.setRoot(MaybeTC);
7346 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7347 unsigned *TotalCases, unsigned First,
7349 assert(Last >= First);
7350 assert(TotalCases[Last] >= TotalCases[First]);
7352 APInt LowCase = Clusters[First].Low->getValue();
7353 APInt HighCase = Clusters[Last].High->getValue();
7354 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7356 // FIXME: A range of consecutive cases has 100% density, but only requires one
7357 // comparison to lower. We should discriminate against such consecutive ranges
7360 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7361 uint64_t Range = Diff + 1;
7364 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7366 assert(NumCases < UINT64_MAX / 100);
7367 assert(Range >= NumCases);
7369 return NumCases * 100 >= Range * MinJumpTableDensity;
7372 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7373 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7374 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7377 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7378 unsigned First, unsigned Last,
7379 const SwitchInst *SI,
7380 MachineBasicBlock *DefaultMBB,
7381 CaseCluster &JTCluster) {
7382 assert(First <= Last);
7384 uint32_t Weight = 0;
7385 unsigned NumCmps = 0;
7386 std::vector<MachineBasicBlock*> Table;
7387 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7388 for (unsigned I = First; I <= Last; ++I) {
7389 assert(Clusters[I].Kind == CC_Range);
7390 Weight += Clusters[I].Weight;
7391 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7392 APInt Low = Clusters[I].Low->getValue();
7393 APInt High = Clusters[I].High->getValue();
7394 NumCmps += (Low == High) ? 1 : 2;
7396 // Fill the gap between this and the previous cluster.
7397 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7398 assert(PreviousHigh.slt(Low));
7399 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7400 for (uint64_t J = 0; J < Gap; J++)
7401 Table.push_back(DefaultMBB);
7403 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7404 for (uint64_t J = 0; J < ClusterSize; ++J)
7405 Table.push_back(Clusters[I].MBB);
7406 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7409 unsigned NumDests = JTWeights.size();
7410 if (isSuitableForBitTests(NumDests, NumCmps,
7411 Clusters[First].Low->getValue(),
7412 Clusters[Last].High->getValue())) {
7413 // Clusters[First..Last] should be lowered as bit tests instead.
7417 // Create the MBB that will load from and jump through the table.
7418 // Note: We create it here, but it's not inserted into the function yet.
7419 MachineFunction *CurMF = FuncInfo.MF;
7420 MachineBasicBlock *JumpTableMBB =
7421 CurMF->CreateMachineBasicBlock(SI->getParent());
7423 // Add successors. Note: use table order for determinism.
7424 SmallPtrSet<MachineBasicBlock *, 8> Done;
7425 for (MachineBasicBlock *Succ : Table) {
7426 if (Done.count(Succ))
7428 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7432 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7433 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7434 ->createJumpTableIndex(Table);
7436 // Set up the jump table info.
7437 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7438 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7439 Clusters[Last].High->getValue(), SI->getCondition(),
7441 JTCases.push_back(JumpTableBlock(JTH, JT));
7443 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7444 JTCases.size() - 1, Weight);
7448 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7449 const SwitchInst *SI,
7450 MachineBasicBlock *DefaultMBB) {
7452 // Clusters must be non-empty, sorted, and only contain Range clusters.
7453 assert(!Clusters.empty());
7454 for (CaseCluster &C : Clusters)
7455 assert(C.Kind == CC_Range);
7456 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7457 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7460 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7461 if (!areJTsAllowed(TLI))
7464 const int64_t N = Clusters.size();
7465 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7467 // Split Clusters into minimum number of dense partitions. The algorithm uses
7468 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7469 // for the Case Statement'" (1994), but builds the MinPartitions array in
7470 // reverse order to make it easier to reconstruct the partitions in ascending
7471 // order. In the choice between two optimal partitionings, it picks the one
7472 // which yields more jump tables.
7474 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7475 SmallVector<unsigned, 8> MinPartitions(N);
7476 // LastElement[i] is the last element of the partition starting at i.
7477 SmallVector<unsigned, 8> LastElement(N);
7478 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7479 SmallVector<unsigned, 8> NumTables(N);
7480 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7481 SmallVector<unsigned, 8> TotalCases(N);
7483 for (unsigned i = 0; i < N; ++i) {
7484 APInt Hi = Clusters[i].High->getValue();
7485 APInt Lo = Clusters[i].Low->getValue();
7486 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7488 TotalCases[i] += TotalCases[i - 1];
7491 // Base case: There is only one way to partition Clusters[N-1].
7492 MinPartitions[N - 1] = 1;
7493 LastElement[N - 1] = N - 1;
7494 assert(MinJumpTableSize > 1);
7495 NumTables[N - 1] = 0;
7497 // Note: loop indexes are signed to avoid underflow.
7498 for (int64_t i = N - 2; i >= 0; i--) {
7499 // Find optimal partitioning of Clusters[i..N-1].
7500 // Baseline: Put Clusters[i] into a partition on its own.
7501 MinPartitions[i] = MinPartitions[i + 1] + 1;
7503 NumTables[i] = NumTables[i + 1];
7505 // Search for a solution that results in fewer partitions.
7506 for (int64_t j = N - 1; j > i; j--) {
7507 // Try building a partition from Clusters[i..j].
7508 if (isDense(Clusters, &TotalCases[0], i, j)) {
7509 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7510 bool IsTable = j - i + 1 >= MinJumpTableSize;
7511 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7513 // If this j leads to fewer partitions, or same number of partitions
7514 // with more lookup tables, it is a better partitioning.
7515 if (NumPartitions < MinPartitions[i] ||
7516 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7517 MinPartitions[i] = NumPartitions;
7519 NumTables[i] = Tables;
7525 // Iterate over the partitions, replacing some with jump tables in-place.
7526 unsigned DstIndex = 0;
7527 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7528 Last = LastElement[First];
7529 assert(Last >= First);
7530 assert(DstIndex <= First);
7531 unsigned NumClusters = Last - First + 1;
7533 CaseCluster JTCluster;
7534 if (NumClusters >= MinJumpTableSize &&
7535 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7536 Clusters[DstIndex++] = JTCluster;
7538 for (unsigned I = First; I <= Last; ++I)
7539 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7542 Clusters.resize(DstIndex);
7545 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7546 // FIXME: Using the pointer type doesn't seem ideal.
7547 uint64_t BW = DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7548 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7552 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7555 const APInt &High) {
7556 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7557 // range of cases both require only one branch to lower. Just looking at the
7558 // number of clusters and destinations should be enough to decide whether to
7561 // To lower a range with bit tests, the range must fit the bitwidth of a
7563 if (!rangeFitsInWord(Low, High))
7566 // Decide whether it's profitable to lower this range with bit tests. Each
7567 // destination requires a bit test and branch, and there is an overall range
7568 // check branch. For a small number of clusters, separate comparisons might be
7569 // cheaper, and for many destinations, splitting the range might be better.
7570 return (NumDests == 1 && NumCmps >= 3) ||
7571 (NumDests == 2 && NumCmps >= 5) ||
7572 (NumDests == 3 && NumCmps >= 6);
7575 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7576 unsigned First, unsigned Last,
7577 const SwitchInst *SI,
7578 CaseCluster &BTCluster) {
7579 assert(First <= Last);
7583 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7584 unsigned NumCmps = 0;
7585 for (int64_t I = First; I <= Last; ++I) {
7586 assert(Clusters[I].Kind == CC_Range);
7587 Dests.set(Clusters[I].MBB->getNumber());
7588 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7590 unsigned NumDests = Dests.count();
7592 APInt Low = Clusters[First].Low->getValue();
7593 APInt High = Clusters[Last].High->getValue();
7594 assert(Low.slt(High));
7596 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7602 const int BitWidth =
7603 DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7604 assert((High - Low + 1).sle(BitWidth) && "Case range must fit in bit mask!");
7606 if (Low.isNonNegative() && High.slt(BitWidth)) {
7607 // Optimize the case where all the case values fit in a
7608 // word without having to subtract minValue. In this case,
7609 // we can optimize away the subtraction.
7610 LowBound = APInt::getNullValue(Low.getBitWidth());
7614 CmpRange = High - Low;
7618 uint32_t TotalWeight = 0;
7619 for (unsigned i = First; i <= Last; ++i) {
7620 // Find the CaseBits for this destination.
7622 for (j = 0; j < CBV.size(); ++j)
7623 if (CBV[j].BB == Clusters[i].MBB)
7625 if (j == CBV.size())
7626 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7627 CaseBits *CB = &CBV[j];
7629 // Update Mask, Bits and ExtraWeight.
7630 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7631 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7632 for (uint64_t j = Lo; j <= Hi; ++j) {
7633 CB->Mask |= 1ULL << j;
7636 CB->ExtraWeight += Clusters[i].Weight;
7637 TotalWeight += Clusters[i].Weight;
7638 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7642 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7643 // Sort by weight first, number of bits second.
7644 if (a.ExtraWeight != b.ExtraWeight)
7645 return a.ExtraWeight > b.ExtraWeight;
7646 return a.Bits > b.Bits;
7649 for (auto &CB : CBV) {
7650 MachineBasicBlock *BitTestBB =
7651 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7652 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7654 BitTestCases.push_back(BitTestBlock(LowBound, CmpRange, SI->getCondition(),
7655 -1U, MVT::Other, false, nullptr,
7656 nullptr, std::move(BTI)));
7658 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7659 BitTestCases.size() - 1, TotalWeight);
7663 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7664 const SwitchInst *SI) {
7665 // Partition Clusters into as few subsets as possible, where each subset has a
7666 // range that fits in a machine word and has <= 3 unique destinations.
7669 // Clusters must be sorted and contain Range or JumpTable clusters.
7670 assert(!Clusters.empty());
7671 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7672 for (const CaseCluster &C : Clusters)
7673 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7674 for (unsigned i = 1; i < Clusters.size(); ++i)
7675 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7678 // If target does not have legal shift left, do not emit bit tests at all.
7679 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7680 EVT PTy = TLI.getPointerTy();
7681 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7684 int BitWidth = PTy.getSizeInBits();
7685 const int64_t N = Clusters.size();
7687 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7688 SmallVector<unsigned, 8> MinPartitions(N);
7689 // LastElement[i] is the last element of the partition starting at i.
7690 SmallVector<unsigned, 8> LastElement(N);
7692 // FIXME: This might not be the best algorithm for finding bit test clusters.
7694 // Base case: There is only one way to partition Clusters[N-1].
7695 MinPartitions[N - 1] = 1;
7696 LastElement[N - 1] = N - 1;
7698 // Note: loop indexes are signed to avoid underflow.
7699 for (int64_t i = N - 2; i >= 0; --i) {
7700 // Find optimal partitioning of Clusters[i..N-1].
7701 // Baseline: Put Clusters[i] into a partition on its own.
7702 MinPartitions[i] = MinPartitions[i + 1] + 1;
7705 // Search for a solution that results in fewer partitions.
7706 // Note: the search is limited by BitWidth, reducing time complexity.
7707 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7708 // Try building a partition from Clusters[i..j].
7711 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7712 Clusters[j].High->getValue()))
7715 // Check nbr of destinations and cluster types.
7716 // FIXME: This works, but doesn't seem very efficient.
7717 bool RangesOnly = true;
7718 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7719 for (int64_t k = i; k <= j; k++) {
7720 if (Clusters[k].Kind != CC_Range) {
7724 Dests.set(Clusters[k].MBB->getNumber());
7726 if (!RangesOnly || Dests.count() > 3)
7729 // Check if it's a better partition.
7730 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7731 if (NumPartitions < MinPartitions[i]) {
7732 // Found a better partition.
7733 MinPartitions[i] = NumPartitions;
7739 // Iterate over the partitions, replacing with bit-test clusters in-place.
7740 unsigned DstIndex = 0;
7741 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7742 Last = LastElement[First];
7743 assert(First <= Last);
7744 assert(DstIndex <= First);
7746 CaseCluster BitTestCluster;
7747 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7748 Clusters[DstIndex++] = BitTestCluster;
7750 for (unsigned I = First; I <= Last; ++I)
7751 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7754 Clusters.resize(DstIndex);
7757 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7758 MachineBasicBlock *SwitchMBB,
7759 MachineBasicBlock *DefaultMBB) {
7760 MachineFunction *CurMF = FuncInfo.MF;
7761 MachineBasicBlock *NextMBB = nullptr;
7762 MachineFunction::iterator BBI = W.MBB;
7763 if (++BBI != FuncInfo.MF->end())
7766 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7768 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7770 if (Size == 2 && W.MBB == SwitchMBB) {
7771 // If any two of the cases has the same destination, and if one value
7772 // is the same as the other, but has one bit unset that the other has set,
7773 // use bit manipulation to do two compares at once. For example:
7774 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7775 // TODO: This could be extended to merge any 2 cases in switches with 3
7777 // TODO: Handle cases where W.CaseBB != SwitchBB.
7778 CaseCluster &Small = *W.FirstCluster;
7779 CaseCluster &Big = *W.LastCluster;
7781 if (Small.Low == Small.High && Big.Low == Big.High &&
7782 Small.MBB == Big.MBB) {
7783 const APInt &SmallValue = Small.Low->getValue();
7784 const APInt &BigValue = Big.Low->getValue();
7786 // Check that there is only one bit different.
7787 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
7788 (SmallValue | BigValue) == BigValue) {
7789 // Isolate the common bit.
7790 APInt CommonBit = BigValue & ~SmallValue;
7791 assert((SmallValue | CommonBit) == BigValue &&
7792 CommonBit.countPopulation() == 1 && "Not a common bit?");
7794 SDValue CondLHS = getValue(Cond);
7795 EVT VT = CondLHS.getValueType();
7796 SDLoc DL = getCurSDLoc();
7798 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7799 DAG.getConstant(CommonBit, VT));
7800 SDValue Cond = DAG.getSetCC(DL, MVT::i1, Or,
7801 DAG.getConstant(BigValue, VT), ISD::SETEQ);
7803 // Update successor info.
7804 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7805 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7806 addSuccessorWithWeight(
7807 SwitchMBB, DefaultMBB,
7808 // The default destination is the first successor in IR.
7809 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
7812 // Insert the true branch.
7814 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
7815 DAG.getBasicBlock(Small.MBB));
7816 // Insert the false branch.
7817 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
7818 DAG.getBasicBlock(DefaultMBB));
7820 DAG.setRoot(BrCond);
7826 if (TM.getOptLevel() != CodeGenOpt::None) {
7827 // Order cases by weight so the most likely case will be checked first.
7828 std::sort(W.FirstCluster, W.LastCluster + 1,
7829 [](const CaseCluster &a, const CaseCluster &b) {
7830 return a.Weight > b.Weight;
7833 // Rearrange the case blocks so that the last one falls through if possible
7834 // without without changing the order of weights.
7835 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
7837 if (I->Weight > W.LastCluster->Weight)
7839 if (I->Kind == CC_Range && I->MBB == NextMBB) {
7840 std::swap(*I, *W.LastCluster);
7846 // Compute total weight.
7847 uint32_t UnhandledWeights = 0;
7848 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
7849 UnhandledWeights += I->Weight;
7850 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
7853 MachineBasicBlock *CurMBB = W.MBB;
7854 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
7855 MachineBasicBlock *Fallthrough;
7856 if (I == W.LastCluster) {
7857 // For the last cluster, fall through to the default destination.
7858 Fallthrough = DefaultMBB;
7860 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
7861 CurMF->insert(BBI, Fallthrough);
7862 // Put Cond in a virtual register to make it available from the new blocks.
7863 ExportFromCurrentBlock(Cond);
7867 case CC_JumpTable: {
7868 // FIXME: Optimize away range check based on pivot comparisons.
7869 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
7870 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
7872 // The jump block hasn't been inserted yet; insert it here.
7873 MachineBasicBlock *JumpMBB = JT->MBB;
7874 CurMF->insert(BBI, JumpMBB);
7875 addSuccessorWithWeight(CurMBB, Fallthrough);
7876 addSuccessorWithWeight(CurMBB, JumpMBB);
7878 // The jump table header will be inserted in our current block, do the
7879 // range check, and fall through to our fallthrough block.
7880 JTH->HeaderBB = CurMBB;
7881 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
7883 // If we're in the right place, emit the jump table header right now.
7884 if (CurMBB == SwitchMBB) {
7885 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
7886 JTH->Emitted = true;
7891 // FIXME: Optimize away range check based on pivot comparisons.
7892 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
7894 // The bit test blocks haven't been inserted yet; insert them here.
7895 for (BitTestCase &BTC : BTB->Cases)
7896 CurMF->insert(BBI, BTC.ThisBB);
7898 // Fill in fields of the BitTestBlock.
7899 BTB->Parent = CurMBB;
7900 BTB->Default = Fallthrough;
7902 // If we're in the right place, emit the bit test header header right now.
7903 if (CurMBB ==SwitchMBB) {
7904 visitBitTestHeader(*BTB, SwitchMBB);
7905 BTB->Emitted = true;
7910 const Value *RHS, *LHS, *MHS;
7912 if (I->Low == I->High) {
7913 // Check Cond == I->Low.
7919 // Check I->Low <= Cond <= I->High.
7926 // The false weight is the sum of all unhandled cases.
7927 UnhandledWeights -= I->Weight;
7928 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
7931 if (CurMBB == SwitchMBB)
7932 visitSwitchCase(CB, SwitchMBB);
7934 SwitchCases.push_back(CB);
7939 CurMBB = Fallthrough;
7943 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
7944 const SwitchWorkListItem &W,
7946 MachineBasicBlock *SwitchMBB) {
7947 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
7948 "Clusters not sorted?");
7950 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
7951 assert(NumClusters >= 2 && "Too small to split!");
7953 // FIXME: When we have profile info, we might want to balance the tree based
7954 // on weights instead of node count.
7956 CaseClusterIt PivotCluster = W.FirstCluster + NumClusters / 2;
7957 CaseClusterIt FirstLeft = W.FirstCluster;
7958 CaseClusterIt LastLeft = PivotCluster - 1;
7959 CaseClusterIt FirstRight = PivotCluster;
7960 CaseClusterIt LastRight = W.LastCluster;
7961 const ConstantInt *Pivot = PivotCluster->Low;
7963 // New blocks will be inserted immediately after the current one.
7964 MachineFunction::iterator BBI = W.MBB;
7967 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
7968 // we can branch to its destination directly if it's squeezed exactly in
7969 // between the known lower bound and Pivot - 1.
7970 MachineBasicBlock *LeftMBB;
7971 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
7972 FirstLeft->Low == W.GE &&
7973 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
7974 LeftMBB = FirstLeft->MBB;
7976 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
7977 FuncInfo.MF->insert(BBI, LeftMBB);
7978 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
7979 // Put Cond in a virtual register to make it available from the new blocks.
7980 ExportFromCurrentBlock(Cond);
7983 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
7984 // single cluster, RHS.Low == Pivot, and we can branch to its destination
7985 // directly if RHS.High equals the current upper bound.
7986 MachineBasicBlock *RightMBB;
7987 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
7988 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
7989 RightMBB = FirstRight->MBB;
7991 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
7992 FuncInfo.MF->insert(BBI, RightMBB);
7993 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
7994 // Put Cond in a virtual register to make it available from the new blocks.
7995 ExportFromCurrentBlock(Cond);
7998 // Create the CaseBlock record that will be used to lower the branch.
7999 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB);
8001 if (W.MBB == SwitchMBB)
8002 visitSwitchCase(CB, SwitchMBB);
8004 SwitchCases.push_back(CB);
8007 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8008 // Extract cases from the switch.
8009 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8010 CaseClusterVector Clusters;
8011 Clusters.reserve(SI.getNumCases());
8012 for (auto I : SI.cases()) {
8013 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8014 const ConstantInt *CaseVal = I.getCaseValue();
8015 uint32_t Weight = 0; // FIXME: Use 1 instead?
8017 Weight = BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex());
8018 assert(Weight <= UINT32_MAX / SI.getNumSuccessors());
8020 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8023 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8025 if (TM.getOptLevel() != CodeGenOpt::None) {
8026 // Cluster adjacent cases with the same destination.
8027 sortAndRangeify(Clusters);
8029 // Replace an unreachable default with the most popular destination.
8030 // FIXME: Exploit unreachable default more aggressively.
8031 bool UnreachableDefault =
8032 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8033 if (UnreachableDefault && !Clusters.empty()) {
8034 DenseMap<const BasicBlock *, unsigned> Popularity;
8035 unsigned MaxPop = 0;
8036 const BasicBlock *MaxBB = nullptr;
8037 for (auto I : SI.cases()) {
8038 const BasicBlock *BB = I.getCaseSuccessor();
8039 if (++Popularity[BB] > MaxPop) {
8040 MaxPop = Popularity[BB];
8045 assert(MaxPop > 0 && MaxBB);
8046 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8048 // Remove cases that were pointing to the destination that is now the
8050 CaseClusterVector New;
8051 New.reserve(Clusters.size());
8052 for (CaseCluster &CC : Clusters) {
8053 if (CC.MBB != DefaultMBB)
8056 Clusters = std::move(New);
8060 // If there is only the default destination, jump there directly.
8061 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8062 if (Clusters.empty()) {
8063 SwitchMBB->addSuccessor(DefaultMBB);
8064 if (DefaultMBB != NextBlock(SwitchMBB)) {
8065 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8066 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8071 if (TM.getOptLevel() != CodeGenOpt::None) {
8072 findJumpTables(Clusters, &SI, DefaultMBB);
8073 findBitTestClusters(Clusters, &SI);
8078 dbgs() << "Case clusters: ";
8079 for (const CaseCluster &C : Clusters) {
8080 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8081 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8083 C.Low->getValue().print(dbgs(), true);
8084 if (C.Low != C.High) {
8086 C.High->getValue().print(dbgs(), true);
8093 assert(!Clusters.empty());
8094 SwitchWorkList WorkList;
8095 CaseClusterIt First = Clusters.begin();
8096 CaseClusterIt Last = Clusters.end() - 1;
8097 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
8099 while (!WorkList.empty()) {
8100 SwitchWorkListItem W = WorkList.back();
8101 WorkList.pop_back();
8102 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8104 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8105 // For optimized builds, lower large range as a balanced binary tree.
8106 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8110 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);