1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1164 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1165 bool IsSEH = isAsynchronousEHPersonality(Pers);
1166 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1167 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1168 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1169 if (IsMSVCCXX || IsCoreCLR)
1170 CatchPadMBB->setIsEHFuncletEntry();
1172 MachineBasicBlock *NormalDestMBB = FuncInfo.MBBMap[I.getNormalDest()];
1174 // Update machine-CFG edge.
1175 FuncInfo.MBB->addSuccessor(NormalDestMBB);
1177 // CatchPads in SEH are not funclets, they are merely markers which indicate
1178 // where to insert register restoration code.
1180 DAG.setRoot(DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1181 getControlRoot(), DAG.getBasicBlock(NormalDestMBB),
1182 DAG.getBasicBlock(FuncInfo.MF->begin())));
1186 // If this is not a fall-through branch or optimizations are switched off,
1188 if (NormalDestMBB != NextBlock(CatchPadMBB) ||
1189 TM.getOptLevel() == CodeGenOpt::None)
1190 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1192 DAG.getBasicBlock(NormalDestMBB)));
1195 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1196 // Update machine-CFG edge.
1197 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1198 FuncInfo.MBB->addSuccessor(TargetMBB);
1200 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1201 bool IsSEH = isAsynchronousEHPersonality(Pers);
1203 // If this is not a fall-through branch or optimizations are switched off,
1205 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1206 TM.getOptLevel() == CodeGenOpt::None)
1207 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1208 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1212 // Figure out the funclet membership for the catchret's successor.
1213 // This will be used by the FuncletLayout pass to determine how to order the
1215 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1216 WinEHFuncInfo &EHInfo =
1217 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
1218 const BasicBlock *SuccessorColor = EHInfo.CatchRetSuccessorColorMap[&I];
1219 assert(SuccessorColor && "No parent funclet for catchret!");
1220 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1221 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1223 // Create the terminator node.
1224 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1225 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1226 DAG.getBasicBlock(SuccessorColorMBB));
1230 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1231 llvm_unreachable("should never codegen catchendpads");
1234 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1235 // Don't emit any special code for the cleanuppad instruction. It just marks
1236 // the start of a funclet.
1237 FuncInfo.MBB->setIsEHFuncletEntry();
1238 FuncInfo.MBB->setIsCleanupFuncletEntry();
1241 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1242 /// many places it could ultimately go. In the IR, we have a single unwind
1243 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1244 /// This function skips over imaginary basic blocks that hold catchpad,
1245 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1246 /// basic block destinations.
1248 findUnwindDestinations(FunctionLoweringInfo &FuncInfo,
1249 const BasicBlock *EHPadBB,
1250 SmallVectorImpl<MachineBasicBlock *> &UnwindDests) {
1251 EHPersonality Personality =
1252 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1253 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1254 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1256 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1257 if (isa<LandingPadInst>(Pad)) {
1258 // Stop on landingpads. They are not funclets.
1259 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1261 } else if (isa<CleanupPadInst>(Pad)) {
1262 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1264 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1265 UnwindDests.back()->setIsEHFuncletEntry();
1267 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1268 // Add the catchpad handler to the possible destinations.
1269 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1270 // In MSVC C++, catchblocks are funclets and need prologues.
1271 if (IsMSVCCXX || IsCoreCLR)
1272 UnwindDests.back()->setIsEHFuncletEntry();
1273 EHPadBB = CPI->getUnwindDest();
1274 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad)) {
1275 EHPadBB = CEPI->getUnwindDest();
1276 } else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad)) {
1277 EHPadBB = CEPI->getUnwindDest();
1282 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1283 // Update successor info.
1284 // FIXME: The weights for catchpads will be wrong.
1285 SmallVector<MachineBasicBlock *, 1> UnwindDests;
1286 findUnwindDestinations(FuncInfo, I.getUnwindDest(), UnwindDests);
1287 for (MachineBasicBlock *UnwindDest : UnwindDests) {
1288 UnwindDest->setIsEHPad();
1289 addSuccessorWithWeight(FuncInfo.MBB, UnwindDest);
1292 // Create the terminator node.
1294 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1298 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1299 report_fatal_error("visitCleanupEndPad not yet implemented!");
1302 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1303 report_fatal_error("visitTerminatePad not yet implemented!");
1306 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1307 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1308 auto &DL = DAG.getDataLayout();
1309 SDValue Chain = getControlRoot();
1310 SmallVector<ISD::OutputArg, 8> Outs;
1311 SmallVector<SDValue, 8> OutVals;
1313 if (!FuncInfo.CanLowerReturn) {
1314 unsigned DemoteReg = FuncInfo.DemoteRegister;
1315 const Function *F = I.getParent()->getParent();
1317 // Emit a store of the return value through the virtual register.
1318 // Leave Outs empty so that LowerReturn won't try to load return
1319 // registers the usual way.
1320 SmallVector<EVT, 1> PtrValueVTs;
1321 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1324 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1325 SDValue RetOp = getValue(I.getOperand(0));
1327 SmallVector<EVT, 4> ValueVTs;
1328 SmallVector<uint64_t, 4> Offsets;
1329 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1330 unsigned NumValues = ValueVTs.size();
1332 SmallVector<SDValue, 4> Chains(NumValues);
1333 for (unsigned i = 0; i != NumValues; ++i) {
1334 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1335 RetPtr.getValueType(), RetPtr,
1336 DAG.getIntPtrConstant(Offsets[i],
1339 DAG.getStore(Chain, getCurSDLoc(),
1340 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1341 // FIXME: better loc info would be nice.
1342 Add, MachinePointerInfo(), false, false, 0);
1345 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1346 MVT::Other, Chains);
1347 } else if (I.getNumOperands() != 0) {
1348 SmallVector<EVT, 4> ValueVTs;
1349 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1350 unsigned NumValues = ValueVTs.size();
1352 SDValue RetOp = getValue(I.getOperand(0));
1354 const Function *F = I.getParent()->getParent();
1356 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1357 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1359 ExtendKind = ISD::SIGN_EXTEND;
1360 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1362 ExtendKind = ISD::ZERO_EXTEND;
1364 LLVMContext &Context = F->getContext();
1365 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1368 for (unsigned j = 0; j != NumValues; ++j) {
1369 EVT VT = ValueVTs[j];
1371 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1372 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1374 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1375 MVT PartVT = TLI.getRegisterType(Context, VT);
1376 SmallVector<SDValue, 4> Parts(NumParts);
1377 getCopyToParts(DAG, getCurSDLoc(),
1378 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1379 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1381 // 'inreg' on function refers to return value
1382 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1386 // Propagate extension type if any
1387 if (ExtendKind == ISD::SIGN_EXTEND)
1389 else if (ExtendKind == ISD::ZERO_EXTEND)
1392 for (unsigned i = 0; i < NumParts; ++i) {
1393 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1394 VT, /*isfixed=*/true, 0, 0));
1395 OutVals.push_back(Parts[i]);
1401 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1402 CallingConv::ID CallConv =
1403 DAG.getMachineFunction().getFunction()->getCallingConv();
1404 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1405 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1407 // Verify that the target's LowerReturn behaved as expected.
1408 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1409 "LowerReturn didn't return a valid chain!");
1411 // Update the DAG with the new chain value resulting from return lowering.
1415 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1416 /// created for it, emit nodes to copy the value into the virtual
1418 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1420 if (V->getType()->isEmptyTy())
1423 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1424 if (VMI != FuncInfo.ValueMap.end()) {
1425 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1426 CopyValueToVirtualRegister(V, VMI->second);
1430 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1431 /// the current basic block, add it to ValueMap now so that we'll get a
1433 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1434 // No need to export constants.
1435 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1437 // Already exported?
1438 if (FuncInfo.isExportedInst(V)) return;
1440 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1441 CopyValueToVirtualRegister(V, Reg);
1444 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1445 const BasicBlock *FromBB) {
1446 // The operands of the setcc have to be in this block. We don't know
1447 // how to export them from some other block.
1448 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1449 // Can export from current BB.
1450 if (VI->getParent() == FromBB)
1453 // Is already exported, noop.
1454 return FuncInfo.isExportedInst(V);
1457 // If this is an argument, we can export it if the BB is the entry block or
1458 // if it is already exported.
1459 if (isa<Argument>(V)) {
1460 if (FromBB == &FromBB->getParent()->getEntryBlock())
1463 // Otherwise, can only export this if it is already exported.
1464 return FuncInfo.isExportedInst(V);
1467 // Otherwise, constants can always be exported.
1471 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1472 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1473 const MachineBasicBlock *Dst) const {
1474 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1477 const BasicBlock *SrcBB = Src->getBasicBlock();
1478 const BasicBlock *DstBB = Dst->getBasicBlock();
1479 return BPI->getEdgeWeight(SrcBB, DstBB);
1482 void SelectionDAGBuilder::
1483 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1484 uint32_t Weight /* = 0 */) {
1486 Weight = getEdgeWeight(Src, Dst);
1487 Src->addSuccessor(Dst, Weight);
1491 static bool InBlock(const Value *V, const BasicBlock *BB) {
1492 if (const Instruction *I = dyn_cast<Instruction>(V))
1493 return I->getParent() == BB;
1497 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1498 /// This function emits a branch and is used at the leaves of an OR or an
1499 /// AND operator tree.
1502 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1503 MachineBasicBlock *TBB,
1504 MachineBasicBlock *FBB,
1505 MachineBasicBlock *CurBB,
1506 MachineBasicBlock *SwitchBB,
1509 const BasicBlock *BB = CurBB->getBasicBlock();
1511 // If the leaf of the tree is a comparison, merge the condition into
1513 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1514 // The operands of the cmp have to be in this block. We don't know
1515 // how to export them from some other block. If this is the first block
1516 // of the sequence, no exporting is needed.
1517 if (CurBB == SwitchBB ||
1518 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1519 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1520 ISD::CondCode Condition;
1521 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1522 Condition = getICmpCondCode(IC->getPredicate());
1524 const FCmpInst *FC = cast<FCmpInst>(Cond);
1525 Condition = getFCmpCondCode(FC->getPredicate());
1526 if (TM.Options.NoNaNsFPMath)
1527 Condition = getFCmpCodeWithoutNaN(Condition);
1530 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1531 TBB, FBB, CurBB, TWeight, FWeight);
1532 SwitchCases.push_back(CB);
1537 // Create a CaseBlock record representing this branch.
1538 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1539 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1540 SwitchCases.push_back(CB);
1543 /// Scale down both weights to fit into uint32_t.
1544 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1545 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1546 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1547 NewTrue = NewTrue / Scale;
1548 NewFalse = NewFalse / Scale;
1551 /// FindMergedConditions - If Cond is an expression like
1552 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1553 MachineBasicBlock *TBB,
1554 MachineBasicBlock *FBB,
1555 MachineBasicBlock *CurBB,
1556 MachineBasicBlock *SwitchBB,
1557 Instruction::BinaryOps Opc,
1560 // If this node is not part of the or/and tree, emit it as a branch.
1561 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1562 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1563 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1564 BOp->getParent() != CurBB->getBasicBlock() ||
1565 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1566 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1567 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1572 // Create TmpBB after CurBB.
1573 MachineFunction::iterator BBI = CurBB;
1574 MachineFunction &MF = DAG.getMachineFunction();
1575 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1576 CurBB->getParent()->insert(++BBI, TmpBB);
1578 if (Opc == Instruction::Or) {
1579 // Codegen X | Y as:
1588 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1589 // The requirement is that
1590 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1591 // = TrueProb for original BB.
1592 // Assuming the original weights are A and B, one choice is to set BB1's
1593 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1595 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1596 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1597 // TmpBB, but the math is more complicated.
1599 uint64_t NewTrueWeight = TWeight;
1600 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1601 ScaleWeights(NewTrueWeight, NewFalseWeight);
1602 // Emit the LHS condition.
1603 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1604 NewTrueWeight, NewFalseWeight);
1606 NewTrueWeight = TWeight;
1607 NewFalseWeight = 2 * (uint64_t)FWeight;
1608 ScaleWeights(NewTrueWeight, NewFalseWeight);
1609 // Emit the RHS condition into TmpBB.
1610 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1611 NewTrueWeight, NewFalseWeight);
1613 assert(Opc == Instruction::And && "Unknown merge op!");
1614 // Codegen X & Y as:
1622 // This requires creation of TmpBB after CurBB.
1624 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1625 // The requirement is that
1626 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1627 // = FalseProb for original BB.
1628 // Assuming the original weights are A and B, one choice is to set BB1's
1629 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1631 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1633 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1634 uint64_t NewFalseWeight = FWeight;
1635 ScaleWeights(NewTrueWeight, NewFalseWeight);
1636 // Emit the LHS condition.
1637 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1638 NewTrueWeight, NewFalseWeight);
1640 NewTrueWeight = 2 * (uint64_t)TWeight;
1641 NewFalseWeight = FWeight;
1642 ScaleWeights(NewTrueWeight, NewFalseWeight);
1643 // Emit the RHS condition into TmpBB.
1644 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1645 NewTrueWeight, NewFalseWeight);
1649 /// If the set of cases should be emitted as a series of branches, return true.
1650 /// If we should emit this as a bunch of and/or'd together conditions, return
1653 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1654 if (Cases.size() != 2) return true;
1656 // If this is two comparisons of the same values or'd or and'd together, they
1657 // will get folded into a single comparison, so don't emit two blocks.
1658 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1659 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1660 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1661 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1665 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1666 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1667 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1668 Cases[0].CC == Cases[1].CC &&
1669 isa<Constant>(Cases[0].CmpRHS) &&
1670 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1671 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1673 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1680 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1681 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1683 // Update machine-CFG edges.
1684 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1686 if (I.isUnconditional()) {
1687 // Update machine-CFG edges.
1688 BrMBB->addSuccessor(Succ0MBB);
1690 // If this is not a fall-through branch or optimizations are switched off,
1692 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1693 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1694 MVT::Other, getControlRoot(),
1695 DAG.getBasicBlock(Succ0MBB)));
1700 // If this condition is one of the special cases we handle, do special stuff
1702 const Value *CondVal = I.getCondition();
1703 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1705 // If this is a series of conditions that are or'd or and'd together, emit
1706 // this as a sequence of branches instead of setcc's with and/or operations.
1707 // As long as jumps are not expensive, this should improve performance.
1708 // For example, instead of something like:
1721 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1722 Instruction::BinaryOps Opcode = BOp->getOpcode();
1723 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1724 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1725 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1726 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1727 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1728 getEdgeWeight(BrMBB, Succ1MBB));
1729 // If the compares in later blocks need to use values not currently
1730 // exported from this block, export them now. This block should always
1731 // be the first entry.
1732 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1734 // Allow some cases to be rejected.
1735 if (ShouldEmitAsBranches(SwitchCases)) {
1736 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1737 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1738 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1741 // Emit the branch for this block.
1742 visitSwitchCase(SwitchCases[0], BrMBB);
1743 SwitchCases.erase(SwitchCases.begin());
1747 // Okay, we decided not to do this, remove any inserted MBB's and clear
1749 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1750 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1752 SwitchCases.clear();
1756 // Create a CaseBlock record representing this branch.
1757 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1758 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1760 // Use visitSwitchCase to actually insert the fast branch sequence for this
1762 visitSwitchCase(CB, BrMBB);
1765 /// visitSwitchCase - Emits the necessary code to represent a single node in
1766 /// the binary search tree resulting from lowering a switch instruction.
1767 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1768 MachineBasicBlock *SwitchBB) {
1770 SDValue CondLHS = getValue(CB.CmpLHS);
1771 SDLoc dl = getCurSDLoc();
1773 // Build the setcc now.
1775 // Fold "(X == true)" to X and "(X == false)" to !X to
1776 // handle common cases produced by branch lowering.
1777 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1778 CB.CC == ISD::SETEQ)
1780 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1781 CB.CC == ISD::SETEQ) {
1782 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1783 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1785 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1787 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1789 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1790 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1792 SDValue CmpOp = getValue(CB.CmpMHS);
1793 EVT VT = CmpOp.getValueType();
1795 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1796 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1799 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1800 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1801 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1802 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1806 // Update successor info
1807 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1808 // TrueBB and FalseBB are always different unless the incoming IR is
1809 // degenerate. This only happens when running llc on weird IR.
1810 if (CB.TrueBB != CB.FalseBB)
1811 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1813 // If the lhs block is the next block, invert the condition so that we can
1814 // fall through to the lhs instead of the rhs block.
1815 if (CB.TrueBB == NextBlock(SwitchBB)) {
1816 std::swap(CB.TrueBB, CB.FalseBB);
1817 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1818 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1821 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1822 MVT::Other, getControlRoot(), Cond,
1823 DAG.getBasicBlock(CB.TrueBB));
1825 // Insert the false branch. Do this even if it's a fall through branch,
1826 // this makes it easier to do DAG optimizations which require inverting
1827 // the branch condition.
1828 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1829 DAG.getBasicBlock(CB.FalseBB));
1831 DAG.setRoot(BrCond);
1834 /// visitJumpTable - Emit JumpTable node in the current MBB
1835 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1836 // Emit the code for the jump table
1837 assert(JT.Reg != -1U && "Should lower JT Header first!");
1838 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1839 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1841 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1842 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1843 MVT::Other, Index.getValue(1),
1845 DAG.setRoot(BrJumpTable);
1848 /// visitJumpTableHeader - This function emits necessary code to produce index
1849 /// in the JumpTable from switch case.
1850 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1851 JumpTableHeader &JTH,
1852 MachineBasicBlock *SwitchBB) {
1853 SDLoc dl = getCurSDLoc();
1855 // Subtract the lowest switch case value from the value being switched on and
1856 // conditional branch to default mbb if the result is greater than the
1857 // difference between smallest and largest cases.
1858 SDValue SwitchOp = getValue(JTH.SValue);
1859 EVT VT = SwitchOp.getValueType();
1860 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1861 DAG.getConstant(JTH.First, dl, VT));
1863 // The SDNode we just created, which holds the value being switched on minus
1864 // the smallest case value, needs to be copied to a virtual register so it
1865 // can be used as an index into the jump table in a subsequent basic block.
1866 // This value may be smaller or larger than the target's pointer type, and
1867 // therefore require extension or truncating.
1868 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1869 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1871 unsigned JumpTableReg =
1872 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1873 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1874 JumpTableReg, SwitchOp);
1875 JT.Reg = JumpTableReg;
1877 // Emit the range check for the jump table, and branch to the default block
1878 // for the switch statement if the value being switched on exceeds the largest
1879 // case in the switch.
1880 SDValue CMP = DAG.getSetCC(
1881 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1882 Sub.getValueType()),
1883 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1885 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1886 MVT::Other, CopyTo, CMP,
1887 DAG.getBasicBlock(JT.Default));
1889 // Avoid emitting unnecessary branches to the next block.
1890 if (JT.MBB != NextBlock(SwitchBB))
1891 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1892 DAG.getBasicBlock(JT.MBB));
1894 DAG.setRoot(BrCond);
1897 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1898 /// tail spliced into a stack protector check success bb.
1900 /// For a high level explanation of how this fits into the stack protector
1901 /// generation see the comment on the declaration of class
1902 /// StackProtectorDescriptor.
1903 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1904 MachineBasicBlock *ParentBB) {
1906 // First create the loads to the guard/stack slot for the comparison.
1907 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1908 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1910 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1911 int FI = MFI->getStackProtectorIndex();
1913 const Value *IRGuard = SPD.getGuard();
1914 SDValue GuardPtr = getValue(IRGuard);
1915 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1917 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1920 SDLoc dl = getCurSDLoc();
1922 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1923 // guard value from the virtual register holding the value. Otherwise, emit a
1924 // volatile load to retrieve the stack guard value.
1925 unsigned GuardReg = SPD.getGuardReg();
1927 if (GuardReg && TLI.useLoadStackGuardNode())
1928 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1931 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1932 GuardPtr, MachinePointerInfo(IRGuard, 0),
1933 true, false, false, Align);
1935 SDValue StackSlot = DAG.getLoad(
1936 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1937 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1938 false, false, Align);
1940 // Perform the comparison via a subtract/getsetcc.
1941 EVT VT = Guard.getValueType();
1942 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1944 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1946 Sub.getValueType()),
1947 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1949 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1950 // branch to failure MBB.
1951 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1952 MVT::Other, StackSlot.getOperand(0),
1953 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1954 // Otherwise branch to success MBB.
1955 SDValue Br = DAG.getNode(ISD::BR, dl,
1957 DAG.getBasicBlock(SPD.getSuccessMBB()));
1962 /// Codegen the failure basic block for a stack protector check.
1964 /// A failure stack protector machine basic block consists simply of a call to
1965 /// __stack_chk_fail().
1967 /// For a high level explanation of how this fits into the stack protector
1968 /// generation see the comment on the declaration of class
1969 /// StackProtectorDescriptor.
1971 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1974 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1975 nullptr, 0, false, getCurSDLoc(), false, false).second;
1979 /// visitBitTestHeader - This function emits necessary code to produce value
1980 /// suitable for "bit tests"
1981 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1982 MachineBasicBlock *SwitchBB) {
1983 SDLoc dl = getCurSDLoc();
1985 // Subtract the minimum value
1986 SDValue SwitchOp = getValue(B.SValue);
1987 EVT VT = SwitchOp.getValueType();
1988 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1989 DAG.getConstant(B.First, dl, VT));
1992 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1993 SDValue RangeCmp = DAG.getSetCC(
1994 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1995 Sub.getValueType()),
1996 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1998 // Determine the type of the test operands.
1999 bool UsePtrType = false;
2000 if (!TLI.isTypeLegal(VT))
2003 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2004 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2005 // Switch table case range are encoded into series of masks.
2006 // Just use pointer type, it's guaranteed to fit.
2012 VT = TLI.getPointerTy(DAG.getDataLayout());
2013 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2016 B.RegVT = VT.getSimpleVT();
2017 B.Reg = FuncInfo.CreateReg(B.RegVT);
2018 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2020 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2022 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
2023 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
2025 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2026 MVT::Other, CopyTo, RangeCmp,
2027 DAG.getBasicBlock(B.Default));
2029 // Avoid emitting unnecessary branches to the next block.
2030 if (MBB != NextBlock(SwitchBB))
2031 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2032 DAG.getBasicBlock(MBB));
2034 DAG.setRoot(BrRange);
2037 /// visitBitTestCase - this function produces one "bit test"
2038 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2039 MachineBasicBlock* NextMBB,
2040 uint32_t BranchWeightToNext,
2043 MachineBasicBlock *SwitchBB) {
2044 SDLoc dl = getCurSDLoc();
2046 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2048 unsigned PopCount = countPopulation(B.Mask);
2049 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2050 if (PopCount == 1) {
2051 // Testing for a single bit; just compare the shift count with what it
2052 // would need to be to shift a 1 bit in that position.
2054 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2055 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2057 } else if (PopCount == BB.Range) {
2058 // There is only one zero bit in the range, test for it directly.
2060 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2061 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2064 // Make desired shift
2065 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2066 DAG.getConstant(1, dl, VT), ShiftOp);
2068 // Emit bit tests and jumps
2069 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2070 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2072 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2073 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2076 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
2077 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
2078 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2079 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2081 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2082 MVT::Other, getControlRoot(),
2083 Cmp, DAG.getBasicBlock(B.TargetBB));
2085 // Avoid emitting unnecessary branches to the next block.
2086 if (NextMBB != NextBlock(SwitchBB))
2087 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2088 DAG.getBasicBlock(NextMBB));
2093 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2094 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2096 // Retrieve successors. Look through artificial IR level blocks like catchpads
2097 // and catchendpads for successors.
2098 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2099 const BasicBlock *EHPadBB = I.getSuccessor(1);
2101 const Value *Callee(I.getCalledValue());
2102 const Function *Fn = dyn_cast<Function>(Callee);
2103 if (isa<InlineAsm>(Callee))
2105 else if (Fn && Fn->isIntrinsic()) {
2106 switch (Fn->getIntrinsicID()) {
2108 llvm_unreachable("Cannot invoke this intrinsic");
2109 case Intrinsic::donothing:
2110 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2112 case Intrinsic::experimental_patchpoint_void:
2113 case Intrinsic::experimental_patchpoint_i64:
2114 visitPatchpoint(&I, EHPadBB);
2116 case Intrinsic::experimental_gc_statepoint:
2117 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2121 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2123 // If the value of the invoke is used outside of its defining block, make it
2124 // available as a virtual register.
2125 // We already took care of the exported value for the statepoint instruction
2126 // during call to the LowerStatepoint.
2127 if (!isStatepoint(I)) {
2128 CopyToExportRegsIfNeeded(&I);
2131 SmallVector<MachineBasicBlock *, 1> UnwindDests;
2132 findUnwindDestinations(FuncInfo, EHPadBB, UnwindDests);
2134 // Update successor info.
2135 // FIXME: The weights for catchpads will be wrong.
2136 addSuccessorWithWeight(InvokeMBB, Return);
2137 for (MachineBasicBlock *UnwindDest : UnwindDests) {
2138 UnwindDest->setIsEHPad();
2139 addSuccessorWithWeight(InvokeMBB, UnwindDest);
2142 // Drop into normal successor.
2143 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2144 MVT::Other, getControlRoot(),
2145 DAG.getBasicBlock(Return)));
2148 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2149 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2152 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2153 assert(FuncInfo.MBB->isEHPad() &&
2154 "Call to landingpad not in landing pad!");
2156 MachineBasicBlock *MBB = FuncInfo.MBB;
2157 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2158 AddLandingPadInfo(LP, MMI, MBB);
2160 // If there aren't registers to copy the values into (e.g., during SjLj
2161 // exceptions), then don't bother to create these DAG nodes.
2162 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2163 if (TLI.getExceptionPointerRegister() == 0 &&
2164 TLI.getExceptionSelectorRegister() == 0)
2167 SmallVector<EVT, 2> ValueVTs;
2168 SDLoc dl = getCurSDLoc();
2169 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2170 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2172 // Get the two live-in registers as SDValues. The physregs have already been
2173 // copied into virtual registers.
2175 if (FuncInfo.ExceptionPointerVirtReg) {
2176 Ops[0] = DAG.getZExtOrTrunc(
2177 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2178 FuncInfo.ExceptionPointerVirtReg,
2179 TLI.getPointerTy(DAG.getDataLayout())),
2182 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2184 Ops[1] = DAG.getZExtOrTrunc(
2185 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2186 FuncInfo.ExceptionSelectorVirtReg,
2187 TLI.getPointerTy(DAG.getDataLayout())),
2191 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2192 DAG.getVTList(ValueVTs), Ops);
2196 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2198 for (const CaseCluster &CC : Clusters)
2199 assert(CC.Low == CC.High && "Input clusters must be single-case");
2202 std::sort(Clusters.begin(), Clusters.end(),
2203 [](const CaseCluster &a, const CaseCluster &b) {
2204 return a.Low->getValue().slt(b.Low->getValue());
2207 // Merge adjacent clusters with the same destination.
2208 const unsigned N = Clusters.size();
2209 unsigned DstIndex = 0;
2210 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2211 CaseCluster &CC = Clusters[SrcIndex];
2212 const ConstantInt *CaseVal = CC.Low;
2213 MachineBasicBlock *Succ = CC.MBB;
2215 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2216 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2217 // If this case has the same successor and is a neighbour, merge it into
2218 // the previous cluster.
2219 Clusters[DstIndex - 1].High = CaseVal;
2220 Clusters[DstIndex - 1].Weight += CC.Weight;
2221 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2223 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2224 sizeof(Clusters[SrcIndex]));
2227 Clusters.resize(DstIndex);
2230 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2231 MachineBasicBlock *Last) {
2233 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2234 if (JTCases[i].first.HeaderBB == First)
2235 JTCases[i].first.HeaderBB = Last;
2237 // Update BitTestCases.
2238 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2239 if (BitTestCases[i].Parent == First)
2240 BitTestCases[i].Parent = Last;
2243 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2244 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2246 // Update machine-CFG edges with unique successors.
2247 SmallSet<BasicBlock*, 32> Done;
2248 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2249 BasicBlock *BB = I.getSuccessor(i);
2250 bool Inserted = Done.insert(BB).second;
2254 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2255 addSuccessorWithWeight(IndirectBrMBB, Succ);
2258 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2259 MVT::Other, getControlRoot(),
2260 getValue(I.getAddress())));
2263 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2264 if (DAG.getTarget().Options.TrapUnreachable)
2266 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2269 void SelectionDAGBuilder::visitFSub(const User &I) {
2270 // -0.0 - X --> fneg
2271 Type *Ty = I.getType();
2272 if (isa<Constant>(I.getOperand(0)) &&
2273 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2274 SDValue Op2 = getValue(I.getOperand(1));
2275 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2276 Op2.getValueType(), Op2));
2280 visitBinary(I, ISD::FSUB);
2283 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2284 SDValue Op1 = getValue(I.getOperand(0));
2285 SDValue Op2 = getValue(I.getOperand(1));
2292 if (const OverflowingBinaryOperator *OFBinOp =
2293 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2294 nuw = OFBinOp->hasNoUnsignedWrap();
2295 nsw = OFBinOp->hasNoSignedWrap();
2297 if (const PossiblyExactOperator *ExactOp =
2298 dyn_cast<const PossiblyExactOperator>(&I))
2299 exact = ExactOp->isExact();
2300 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2301 FMF = FPOp->getFastMathFlags();
2304 Flags.setExact(exact);
2305 Flags.setNoSignedWrap(nsw);
2306 Flags.setNoUnsignedWrap(nuw);
2307 if (EnableFMFInDAG) {
2308 Flags.setAllowReciprocal(FMF.allowReciprocal());
2309 Flags.setNoInfs(FMF.noInfs());
2310 Flags.setNoNaNs(FMF.noNaNs());
2311 Flags.setNoSignedZeros(FMF.noSignedZeros());
2312 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2314 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2316 setValue(&I, BinNodeValue);
2319 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2320 SDValue Op1 = getValue(I.getOperand(0));
2321 SDValue Op2 = getValue(I.getOperand(1));
2323 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2324 Op2.getValueType(), DAG.getDataLayout());
2326 // Coerce the shift amount to the right type if we can.
2327 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2328 unsigned ShiftSize = ShiftTy.getSizeInBits();
2329 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2330 SDLoc DL = getCurSDLoc();
2332 // If the operand is smaller than the shift count type, promote it.
2333 if (ShiftSize > Op2Size)
2334 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2336 // If the operand is larger than the shift count type but the shift
2337 // count type has enough bits to represent any shift value, truncate
2338 // it now. This is a common case and it exposes the truncate to
2339 // optimization early.
2340 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2341 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2342 // Otherwise we'll need to temporarily settle for some other convenient
2343 // type. Type legalization will make adjustments once the shiftee is split.
2345 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2352 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2354 if (const OverflowingBinaryOperator *OFBinOp =
2355 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2356 nuw = OFBinOp->hasNoUnsignedWrap();
2357 nsw = OFBinOp->hasNoSignedWrap();
2359 if (const PossiblyExactOperator *ExactOp =
2360 dyn_cast<const PossiblyExactOperator>(&I))
2361 exact = ExactOp->isExact();
2364 Flags.setExact(exact);
2365 Flags.setNoSignedWrap(nsw);
2366 Flags.setNoUnsignedWrap(nuw);
2367 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2372 void SelectionDAGBuilder::visitSDiv(const User &I) {
2373 SDValue Op1 = getValue(I.getOperand(0));
2374 SDValue Op2 = getValue(I.getOperand(1));
2377 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2378 cast<PossiblyExactOperator>(&I)->isExact());
2379 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2383 void SelectionDAGBuilder::visitICmp(const User &I) {
2384 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2385 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2386 predicate = IC->getPredicate();
2387 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2388 predicate = ICmpInst::Predicate(IC->getPredicate());
2389 SDValue Op1 = getValue(I.getOperand(0));
2390 SDValue Op2 = getValue(I.getOperand(1));
2391 ISD::CondCode Opcode = getICmpCondCode(predicate);
2393 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2395 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2398 void SelectionDAGBuilder::visitFCmp(const User &I) {
2399 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2400 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2401 predicate = FC->getPredicate();
2402 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2403 predicate = FCmpInst::Predicate(FC->getPredicate());
2404 SDValue Op1 = getValue(I.getOperand(0));
2405 SDValue Op2 = getValue(I.getOperand(1));
2406 ISD::CondCode Condition = getFCmpCondCode(predicate);
2408 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2409 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2410 // further optimization, but currently FMF is only applicable to binary nodes.
2411 if (TM.Options.NoNaNsFPMath)
2412 Condition = getFCmpCodeWithoutNaN(Condition);
2413 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2415 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2418 void SelectionDAGBuilder::visitSelect(const User &I) {
2419 SmallVector<EVT, 4> ValueVTs;
2420 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2422 unsigned NumValues = ValueVTs.size();
2423 if (NumValues == 0) return;
2425 SmallVector<SDValue, 4> Values(NumValues);
2426 SDValue Cond = getValue(I.getOperand(0));
2427 SDValue LHSVal = getValue(I.getOperand(1));
2428 SDValue RHSVal = getValue(I.getOperand(2));
2429 auto BaseOps = {Cond};
2430 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2431 ISD::VSELECT : ISD::SELECT;
2433 // Min/max matching is only viable if all output VTs are the same.
2434 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2435 EVT VT = ValueVTs[0];
2436 LLVMContext &Ctx = *DAG.getContext();
2437 auto &TLI = DAG.getTargetLoweringInfo();
2438 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2439 VT = TLI.getTypeToTransformTo(Ctx, VT);
2442 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2443 ISD::NodeType Opc = ISD::DELETED_NODE;
2444 switch (SPR.Flavor) {
2445 case SPF_UMAX: Opc = ISD::UMAX; break;
2446 case SPF_UMIN: Opc = ISD::UMIN; break;
2447 case SPF_SMAX: Opc = ISD::SMAX; break;
2448 case SPF_SMIN: Opc = ISD::SMIN; break;
2450 switch (SPR.NaNBehavior) {
2451 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2452 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2453 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2454 case SPNB_RETURNS_ANY:
2455 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2461 switch (SPR.NaNBehavior) {
2462 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2463 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2464 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2465 case SPNB_RETURNS_ANY:
2466 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2474 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2475 // If the underlying comparison instruction is used by any other instruction,
2476 // the consumed instructions won't be destroyed, so it is not profitable
2477 // to convert to a min/max.
2478 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2480 LHSVal = getValue(LHS);
2481 RHSVal = getValue(RHS);
2486 for (unsigned i = 0; i != NumValues; ++i) {
2487 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2488 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2489 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2490 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2491 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2495 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2496 DAG.getVTList(ValueVTs), Values));
2499 void SelectionDAGBuilder::visitTrunc(const User &I) {
2500 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2501 SDValue N = getValue(I.getOperand(0));
2502 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2504 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2507 void SelectionDAGBuilder::visitZExt(const User &I) {
2508 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2509 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2510 SDValue N = getValue(I.getOperand(0));
2511 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2513 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2516 void SelectionDAGBuilder::visitSExt(const User &I) {
2517 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2518 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2519 SDValue N = getValue(I.getOperand(0));
2520 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2522 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2525 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2526 // FPTrunc is never a no-op cast, no need to check
2527 SDValue N = getValue(I.getOperand(0));
2528 SDLoc dl = getCurSDLoc();
2529 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2530 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2531 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2532 DAG.getTargetConstant(
2533 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2536 void SelectionDAGBuilder::visitFPExt(const User &I) {
2537 // FPExt is never a no-op cast, no need to check
2538 SDValue N = getValue(I.getOperand(0));
2539 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2541 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2544 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2545 // FPToUI is never a no-op cast, no need to check
2546 SDValue N = getValue(I.getOperand(0));
2547 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2549 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2552 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2553 // FPToSI is never a no-op cast, no need to check
2554 SDValue N = getValue(I.getOperand(0));
2555 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2557 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2560 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2561 // UIToFP is never a no-op cast, no need to check
2562 SDValue N = getValue(I.getOperand(0));
2563 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2565 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2568 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2569 // SIToFP is never a no-op cast, no need to check
2570 SDValue N = getValue(I.getOperand(0));
2571 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2573 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2576 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2577 // What to do depends on the size of the integer and the size of the pointer.
2578 // We can either truncate, zero extend, or no-op, accordingly.
2579 SDValue N = getValue(I.getOperand(0));
2580 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2582 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2585 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2586 // What to do depends on the size of the integer and the size of the pointer.
2587 // We can either truncate, zero extend, or no-op, accordingly.
2588 SDValue N = getValue(I.getOperand(0));
2589 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2591 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2594 void SelectionDAGBuilder::visitBitCast(const User &I) {
2595 SDValue N = getValue(I.getOperand(0));
2596 SDLoc dl = getCurSDLoc();
2597 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2600 // BitCast assures us that source and destination are the same size so this is
2601 // either a BITCAST or a no-op.
2602 if (DestVT != N.getValueType())
2603 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2604 DestVT, N)); // convert types.
2605 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2606 // might fold any kind of constant expression to an integer constant and that
2607 // is not what we are looking for. Only regcognize a bitcast of a genuine
2608 // constant integer as an opaque constant.
2609 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2610 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2613 setValue(&I, N); // noop cast.
2616 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2618 const Value *SV = I.getOperand(0);
2619 SDValue N = getValue(SV);
2620 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2622 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2623 unsigned DestAS = I.getType()->getPointerAddressSpace();
2625 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2626 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2631 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2632 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2633 SDValue InVec = getValue(I.getOperand(0));
2634 SDValue InVal = getValue(I.getOperand(1));
2635 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2636 TLI.getVectorIdxTy(DAG.getDataLayout()));
2637 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2638 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2639 InVec, InVal, InIdx));
2642 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2643 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2644 SDValue InVec = getValue(I.getOperand(0));
2645 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2646 TLI.getVectorIdxTy(DAG.getDataLayout()));
2647 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2648 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2652 // Utility for visitShuffleVector - Return true if every element in Mask,
2653 // beginning from position Pos and ending in Pos+Size, falls within the
2654 // specified sequential range [L, L+Pos). or is undef.
2655 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2656 unsigned Pos, unsigned Size, int Low) {
2657 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2658 if (Mask[i] >= 0 && Mask[i] != Low)
2663 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2664 SDValue Src1 = getValue(I.getOperand(0));
2665 SDValue Src2 = getValue(I.getOperand(1));
2667 SmallVector<int, 8> Mask;
2668 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2669 unsigned MaskNumElts = Mask.size();
2671 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2672 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2673 EVT SrcVT = Src1.getValueType();
2674 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2676 if (SrcNumElts == MaskNumElts) {
2677 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2682 // Normalize the shuffle vector since mask and vector length don't match.
2683 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2684 // Mask is longer than the source vectors and is a multiple of the source
2685 // vectors. We can use concatenate vector to make the mask and vectors
2687 if (SrcNumElts*2 == MaskNumElts) {
2688 // First check for Src1 in low and Src2 in high
2689 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2690 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2691 // The shuffle is concatenating two vectors together.
2692 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2696 // Then check for Src2 in low and Src1 in high
2697 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2698 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2699 // The shuffle is concatenating two vectors together.
2700 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2706 // Pad both vectors with undefs to make them the same length as the mask.
2707 unsigned NumConcat = MaskNumElts / SrcNumElts;
2708 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2709 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2710 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2712 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2713 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2717 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2718 getCurSDLoc(), VT, MOps1);
2719 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2720 getCurSDLoc(), VT, MOps2);
2722 // Readjust mask for new input vector length.
2723 SmallVector<int, 8> MappedOps;
2724 for (unsigned i = 0; i != MaskNumElts; ++i) {
2726 if (Idx >= (int)SrcNumElts)
2727 Idx -= SrcNumElts - MaskNumElts;
2728 MappedOps.push_back(Idx);
2731 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2736 if (SrcNumElts > MaskNumElts) {
2737 // Analyze the access pattern of the vector to see if we can extract
2738 // two subvectors and do the shuffle. The analysis is done by calculating
2739 // the range of elements the mask access on both vectors.
2740 int MinRange[2] = { static_cast<int>(SrcNumElts),
2741 static_cast<int>(SrcNumElts)};
2742 int MaxRange[2] = {-1, -1};
2744 for (unsigned i = 0; i != MaskNumElts; ++i) {
2750 if (Idx >= (int)SrcNumElts) {
2754 if (Idx > MaxRange[Input])
2755 MaxRange[Input] = Idx;
2756 if (Idx < MinRange[Input])
2757 MinRange[Input] = Idx;
2760 // Check if the access is smaller than the vector size and can we find
2761 // a reasonable extract index.
2762 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2764 int StartIdx[2]; // StartIdx to extract from
2765 for (unsigned Input = 0; Input < 2; ++Input) {
2766 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2767 RangeUse[Input] = 0; // Unused
2768 StartIdx[Input] = 0;
2772 // Find a good start index that is a multiple of the mask length. Then
2773 // see if the rest of the elements are in range.
2774 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2775 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2776 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2777 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2780 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2781 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2784 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2785 // Extract appropriate subvector and generate a vector shuffle
2786 for (unsigned Input = 0; Input < 2; ++Input) {
2787 SDValue &Src = Input == 0 ? Src1 : Src2;
2788 if (RangeUse[Input] == 0)
2789 Src = DAG.getUNDEF(VT);
2791 SDLoc dl = getCurSDLoc();
2793 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2794 DAG.getConstant(StartIdx[Input], dl,
2795 TLI.getVectorIdxTy(DAG.getDataLayout())));
2799 // Calculate new mask.
2800 SmallVector<int, 8> MappedOps;
2801 for (unsigned i = 0; i != MaskNumElts; ++i) {
2804 if (Idx < (int)SrcNumElts)
2807 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2809 MappedOps.push_back(Idx);
2812 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2818 // We can't use either concat vectors or extract subvectors so fall back to
2819 // replacing the shuffle with extract and build vector.
2820 // to insert and build vector.
2821 EVT EltVT = VT.getVectorElementType();
2822 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2823 SDLoc dl = getCurSDLoc();
2824 SmallVector<SDValue,8> Ops;
2825 for (unsigned i = 0; i != MaskNumElts; ++i) {
2830 Res = DAG.getUNDEF(EltVT);
2832 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2833 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2835 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2836 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2842 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2845 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2846 const Value *Op0 = I.getOperand(0);
2847 const Value *Op1 = I.getOperand(1);
2848 Type *AggTy = I.getType();
2849 Type *ValTy = Op1->getType();
2850 bool IntoUndef = isa<UndefValue>(Op0);
2851 bool FromUndef = isa<UndefValue>(Op1);
2853 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2855 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2856 SmallVector<EVT, 4> AggValueVTs;
2857 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2858 SmallVector<EVT, 4> ValValueVTs;
2859 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2861 unsigned NumAggValues = AggValueVTs.size();
2862 unsigned NumValValues = ValValueVTs.size();
2863 SmallVector<SDValue, 4> Values(NumAggValues);
2865 // Ignore an insertvalue that produces an empty object
2866 if (!NumAggValues) {
2867 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2871 SDValue Agg = getValue(Op0);
2873 // Copy the beginning value(s) from the original aggregate.
2874 for (; i != LinearIndex; ++i)
2875 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2876 SDValue(Agg.getNode(), Agg.getResNo() + i);
2877 // Copy values from the inserted value(s).
2879 SDValue Val = getValue(Op1);
2880 for (; i != LinearIndex + NumValValues; ++i)
2881 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2882 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2884 // Copy remaining value(s) from the original aggregate.
2885 for (; i != NumAggValues; ++i)
2886 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2887 SDValue(Agg.getNode(), Agg.getResNo() + i);
2889 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2890 DAG.getVTList(AggValueVTs), Values));
2893 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2894 const Value *Op0 = I.getOperand(0);
2895 Type *AggTy = Op0->getType();
2896 Type *ValTy = I.getType();
2897 bool OutOfUndef = isa<UndefValue>(Op0);
2899 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2901 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2902 SmallVector<EVT, 4> ValValueVTs;
2903 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2905 unsigned NumValValues = ValValueVTs.size();
2907 // Ignore a extractvalue that produces an empty object
2908 if (!NumValValues) {
2909 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2913 SmallVector<SDValue, 4> Values(NumValValues);
2915 SDValue Agg = getValue(Op0);
2916 // Copy out the selected value(s).
2917 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2918 Values[i - LinearIndex] =
2920 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2921 SDValue(Agg.getNode(), Agg.getResNo() + i);
2923 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2924 DAG.getVTList(ValValueVTs), Values));
2927 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2928 Value *Op0 = I.getOperand(0);
2929 // Note that the pointer operand may be a vector of pointers. Take the scalar
2930 // element which holds a pointer.
2931 Type *Ty = Op0->getType()->getScalarType();
2932 unsigned AS = Ty->getPointerAddressSpace();
2933 SDValue N = getValue(Op0);
2934 SDLoc dl = getCurSDLoc();
2936 // Normalize Vector GEP - all scalar operands should be converted to the
2938 unsigned VectorWidth = I.getType()->isVectorTy() ?
2939 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2941 if (VectorWidth && !N.getValueType().isVector()) {
2942 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2943 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2944 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2946 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2948 const Value *Idx = *OI;
2949 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2950 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2953 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2954 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2955 DAG.getConstant(Offset, dl, N.getValueType()));
2958 Ty = StTy->getElementType(Field);
2960 Ty = cast<SequentialType>(Ty)->getElementType();
2962 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2963 unsigned PtrSize = PtrTy.getSizeInBits();
2964 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2966 // If this is a scalar constant or a splat vector of constants,
2967 // handle it quickly.
2968 const auto *CI = dyn_cast<ConstantInt>(Idx);
2969 if (!CI && isa<ConstantDataVector>(Idx) &&
2970 cast<ConstantDataVector>(Idx)->getSplatValue())
2971 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2976 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2977 SDValue OffsVal = VectorWidth ?
2978 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2979 DAG.getConstant(Offs, dl, PtrTy);
2980 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2984 // N = N + Idx * ElementSize;
2985 SDValue IdxN = getValue(Idx);
2987 if (!IdxN.getValueType().isVector() && VectorWidth) {
2988 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2989 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2990 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2992 // If the index is smaller or larger than intptr_t, truncate or extend
2994 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2996 // If this is a multiply by a power of two, turn it into a shl
2997 // immediately. This is a very common case.
2998 if (ElementSize != 1) {
2999 if (ElementSize.isPowerOf2()) {
3000 unsigned Amt = ElementSize.logBase2();
3001 IdxN = DAG.getNode(ISD::SHL, dl,
3002 N.getValueType(), IdxN,
3003 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3005 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3006 IdxN = DAG.getNode(ISD::MUL, dl,
3007 N.getValueType(), IdxN, Scale);
3011 N = DAG.getNode(ISD::ADD, dl,
3012 N.getValueType(), N, IdxN);
3019 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3020 // If this is a fixed sized alloca in the entry block of the function,
3021 // allocate it statically on the stack.
3022 if (FuncInfo.StaticAllocaMap.count(&I))
3023 return; // getValue will auto-populate this.
3025 SDLoc dl = getCurSDLoc();
3026 Type *Ty = I.getAllocatedType();
3027 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3028 auto &DL = DAG.getDataLayout();
3029 uint64_t TySize = DL.getTypeAllocSize(Ty);
3031 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3033 SDValue AllocSize = getValue(I.getArraySize());
3035 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3036 if (AllocSize.getValueType() != IntPtr)
3037 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3039 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3041 DAG.getConstant(TySize, dl, IntPtr));
3043 // Handle alignment. If the requested alignment is less than or equal to
3044 // the stack alignment, ignore it. If the size is greater than or equal to
3045 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3046 unsigned StackAlign =
3047 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3048 if (Align <= StackAlign)
3051 // Round the size of the allocation up to the stack alignment size
3052 // by add SA-1 to the size.
3053 AllocSize = DAG.getNode(ISD::ADD, dl,
3054 AllocSize.getValueType(), AllocSize,
3055 DAG.getIntPtrConstant(StackAlign - 1, dl));
3057 // Mask out the low bits for alignment purposes.
3058 AllocSize = DAG.getNode(ISD::AND, dl,
3059 AllocSize.getValueType(), AllocSize,
3060 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3063 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3064 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3065 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3067 DAG.setRoot(DSA.getValue(1));
3069 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3072 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3074 return visitAtomicLoad(I);
3076 const Value *SV = I.getOperand(0);
3077 SDValue Ptr = getValue(SV);
3079 Type *Ty = I.getType();
3081 bool isVolatile = I.isVolatile();
3082 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3084 // The IR notion of invariant_load only guarantees that all *non-faulting*
3085 // invariant loads result in the same value. The MI notion of invariant load
3086 // guarantees that the load can be legally moved to any location within its
3087 // containing function. The MI notion of invariant_load is stronger than the
3088 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3089 // with a guarantee that the location being loaded from is dereferenceable
3090 // throughout the function's lifetime.
3092 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3093 isDereferenceablePointer(SV, DAG.getDataLayout());
3094 unsigned Alignment = I.getAlignment();
3097 I.getAAMetadata(AAInfo);
3098 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3100 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3101 SmallVector<EVT, 4> ValueVTs;
3102 SmallVector<uint64_t, 4> Offsets;
3103 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3104 unsigned NumValues = ValueVTs.size();
3109 bool ConstantMemory = false;
3110 if (isVolatile || NumValues > MaxParallelChains)
3111 // Serialize volatile loads with other side effects.
3113 else if (AA->pointsToConstantMemory(MemoryLocation(
3114 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3115 // Do not serialize (non-volatile) loads of constant memory with anything.
3116 Root = DAG.getEntryNode();
3117 ConstantMemory = true;
3119 // Do not serialize non-volatile loads against each other.
3120 Root = DAG.getRoot();
3123 SDLoc dl = getCurSDLoc();
3126 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3128 SmallVector<SDValue, 4> Values(NumValues);
3129 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3130 EVT PtrVT = Ptr.getValueType();
3131 unsigned ChainI = 0;
3132 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3133 // Serializing loads here may result in excessive register pressure, and
3134 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3135 // could recover a bit by hoisting nodes upward in the chain by recognizing
3136 // they are side-effect free or do not alias. The optimizer should really
3137 // avoid this case by converting large object/array copies to llvm.memcpy
3138 // (MaxParallelChains should always remain as failsafe).
3139 if (ChainI == MaxParallelChains) {
3140 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3141 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3142 makeArrayRef(Chains.data(), ChainI));
3146 SDValue A = DAG.getNode(ISD::ADD, dl,
3148 DAG.getConstant(Offsets[i], dl, PtrVT));
3149 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3150 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3151 isNonTemporal, isInvariant, Alignment, AAInfo,
3155 Chains[ChainI] = L.getValue(1);
3158 if (!ConstantMemory) {
3159 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3160 makeArrayRef(Chains.data(), ChainI));
3164 PendingLoads.push_back(Chain);
3167 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3168 DAG.getVTList(ValueVTs), Values));
3171 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3173 return visitAtomicStore(I);
3175 const Value *SrcV = I.getOperand(0);
3176 const Value *PtrV = I.getOperand(1);
3178 SmallVector<EVT, 4> ValueVTs;
3179 SmallVector<uint64_t, 4> Offsets;
3180 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3181 SrcV->getType(), ValueVTs, &Offsets);
3182 unsigned NumValues = ValueVTs.size();
3186 // Get the lowered operands. Note that we do this after
3187 // checking if NumResults is zero, because with zero results
3188 // the operands won't have values in the map.
3189 SDValue Src = getValue(SrcV);
3190 SDValue Ptr = getValue(PtrV);
3192 SDValue Root = getRoot();
3193 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3194 EVT PtrVT = Ptr.getValueType();
3195 bool isVolatile = I.isVolatile();
3196 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3197 unsigned Alignment = I.getAlignment();
3198 SDLoc dl = getCurSDLoc();
3201 I.getAAMetadata(AAInfo);
3203 unsigned ChainI = 0;
3204 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3205 // See visitLoad comments.
3206 if (ChainI == MaxParallelChains) {
3207 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3208 makeArrayRef(Chains.data(), ChainI));
3212 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3213 DAG.getConstant(Offsets[i], dl, PtrVT));
3214 SDValue St = DAG.getStore(Root, dl,
3215 SDValue(Src.getNode(), Src.getResNo() + i),
3216 Add, MachinePointerInfo(PtrV, Offsets[i]),
3217 isVolatile, isNonTemporal, Alignment, AAInfo);
3218 Chains[ChainI] = St;
3221 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3222 makeArrayRef(Chains.data(), ChainI));
3223 DAG.setRoot(StoreNode);
3226 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3227 SDLoc sdl = getCurSDLoc();
3229 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3230 Value *PtrOperand = I.getArgOperand(1);
3231 SDValue Ptr = getValue(PtrOperand);
3232 SDValue Src0 = getValue(I.getArgOperand(0));
3233 SDValue Mask = getValue(I.getArgOperand(3));
3234 EVT VT = Src0.getValueType();
3235 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3237 Alignment = DAG.getEVTAlignment(VT);
3240 I.getAAMetadata(AAInfo);
3242 MachineMemOperand *MMO =
3243 DAG.getMachineFunction().
3244 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3245 MachineMemOperand::MOStore, VT.getStoreSize(),
3247 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3249 DAG.setRoot(StoreNode);
3250 setValue(&I, StoreNode);
3253 // Get a uniform base for the Gather/Scatter intrinsic.
3254 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3255 // We try to represent it as a base pointer + vector of indices.
3256 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3257 // The first operand of the GEP may be a single pointer or a vector of pointers
3259 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3261 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3262 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3264 // When the first GEP operand is a single pointer - it is the uniform base we
3265 // are looking for. If first operand of the GEP is a splat vector - we
3266 // extract the spalt value and use it as a uniform base.
3267 // In all other cases the function returns 'false'.
3269 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3270 SelectionDAGBuilder* SDB) {
3272 SelectionDAG& DAG = SDB->DAG;
3273 LLVMContext &Context = *DAG.getContext();
3275 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3276 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3277 if (!GEP || GEP->getNumOperands() > 2)
3280 Value *GEPPtr = GEP->getPointerOperand();
3281 if (!GEPPtr->getType()->isVectorTy())
3283 else if (!(Ptr = getSplatValue(GEPPtr)))
3286 Value *IndexVal = GEP->getOperand(1);
3288 // The operands of the GEP may be defined in another basic block.
3289 // In this case we'll not find nodes for the operands.
3290 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3293 Base = SDB->getValue(Ptr);
3294 Index = SDB->getValue(IndexVal);
3296 // Suppress sign extension.
3297 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3298 if (SDB->findValue(Sext->getOperand(0))) {
3299 IndexVal = Sext->getOperand(0);
3300 Index = SDB->getValue(IndexVal);
3303 if (!Index.getValueType().isVector()) {
3304 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3305 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3306 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3307 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3312 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3313 SDLoc sdl = getCurSDLoc();
3315 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3316 Value *Ptr = I.getArgOperand(1);
3317 SDValue Src0 = getValue(I.getArgOperand(0));
3318 SDValue Mask = getValue(I.getArgOperand(3));
3319 EVT VT = Src0.getValueType();
3320 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3322 Alignment = DAG.getEVTAlignment(VT);
3323 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3326 I.getAAMetadata(AAInfo);
3330 Value *BasePtr = Ptr;
3331 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3333 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3334 MachineMemOperand *MMO = DAG.getMachineFunction().
3335 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3336 MachineMemOperand::MOStore, VT.getStoreSize(),
3339 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3340 Index = getValue(Ptr);
3342 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3343 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3345 DAG.setRoot(Scatter);
3346 setValue(&I, Scatter);
3349 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3350 SDLoc sdl = getCurSDLoc();
3352 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3353 Value *PtrOperand = I.getArgOperand(0);
3354 SDValue Ptr = getValue(PtrOperand);
3355 SDValue Src0 = getValue(I.getArgOperand(3));
3356 SDValue Mask = getValue(I.getArgOperand(2));
3358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3359 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3360 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3362 Alignment = DAG.getEVTAlignment(VT);
3365 I.getAAMetadata(AAInfo);
3366 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3368 SDValue InChain = DAG.getRoot();
3369 if (AA->pointsToConstantMemory(MemoryLocation(
3370 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3372 // Do not serialize (non-volatile) loads of constant memory with anything.
3373 InChain = DAG.getEntryNode();
3376 MachineMemOperand *MMO =
3377 DAG.getMachineFunction().
3378 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3379 MachineMemOperand::MOLoad, VT.getStoreSize(),
3380 Alignment, AAInfo, Ranges);
3382 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3384 SDValue OutChain = Load.getValue(1);
3385 DAG.setRoot(OutChain);
3389 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3390 SDLoc sdl = getCurSDLoc();
3392 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3393 Value *Ptr = I.getArgOperand(0);
3394 SDValue Src0 = getValue(I.getArgOperand(3));
3395 SDValue Mask = getValue(I.getArgOperand(2));
3397 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3398 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3399 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3401 Alignment = DAG.getEVTAlignment(VT);
3404 I.getAAMetadata(AAInfo);
3405 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3407 SDValue Root = DAG.getRoot();
3410 Value *BasePtr = Ptr;
3411 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3412 bool ConstantMemory = false;
3414 AA->pointsToConstantMemory(MemoryLocation(
3415 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3417 // Do not serialize (non-volatile) loads of constant memory with anything.
3418 Root = DAG.getEntryNode();
3419 ConstantMemory = true;
3422 MachineMemOperand *MMO =
3423 DAG.getMachineFunction().
3424 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3425 MachineMemOperand::MOLoad, VT.getStoreSize(),
3426 Alignment, AAInfo, Ranges);
3429 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3430 Index = getValue(Ptr);
3432 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3433 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3436 SDValue OutChain = Gather.getValue(1);
3437 if (!ConstantMemory)
3438 PendingLoads.push_back(OutChain);
3439 setValue(&I, Gather);
3442 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3443 SDLoc dl = getCurSDLoc();
3444 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3445 AtomicOrdering FailureOrder = I.getFailureOrdering();
3446 SynchronizationScope Scope = I.getSynchScope();
3448 SDValue InChain = getRoot();
3450 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3451 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3452 SDValue L = DAG.getAtomicCmpSwap(
3453 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3454 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3455 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3456 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3458 SDValue OutChain = L.getValue(2);
3461 DAG.setRoot(OutChain);
3464 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3465 SDLoc dl = getCurSDLoc();
3467 switch (I.getOperation()) {
3468 default: llvm_unreachable("Unknown atomicrmw operation");
3469 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3470 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3471 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3472 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3473 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3474 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3475 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3476 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3477 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3478 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3479 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3481 AtomicOrdering Order = I.getOrdering();
3482 SynchronizationScope Scope = I.getSynchScope();
3484 SDValue InChain = getRoot();
3487 DAG.getAtomic(NT, dl,
3488 getValue(I.getValOperand()).getSimpleValueType(),
3490 getValue(I.getPointerOperand()),
3491 getValue(I.getValOperand()),
3492 I.getPointerOperand(),
3493 /* Alignment=*/ 0, Order, Scope);
3495 SDValue OutChain = L.getValue(1);
3498 DAG.setRoot(OutChain);
3501 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3502 SDLoc dl = getCurSDLoc();
3503 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3506 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3507 TLI.getPointerTy(DAG.getDataLayout()));
3508 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3509 TLI.getPointerTy(DAG.getDataLayout()));
3510 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3513 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3514 SDLoc dl = getCurSDLoc();
3515 AtomicOrdering Order = I.getOrdering();
3516 SynchronizationScope Scope = I.getSynchScope();
3518 SDValue InChain = getRoot();
3520 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3521 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3523 if (I.getAlignment() < VT.getSizeInBits() / 8)
3524 report_fatal_error("Cannot generate unaligned atomic load");
3526 MachineMemOperand *MMO =
3527 DAG.getMachineFunction().
3528 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3529 MachineMemOperand::MOVolatile |
3530 MachineMemOperand::MOLoad,
3532 I.getAlignment() ? I.getAlignment() :
3533 DAG.getEVTAlignment(VT));
3535 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3537 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3538 getValue(I.getPointerOperand()), MMO,
3541 SDValue OutChain = L.getValue(1);
3544 DAG.setRoot(OutChain);
3547 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3548 SDLoc dl = getCurSDLoc();
3550 AtomicOrdering Order = I.getOrdering();
3551 SynchronizationScope Scope = I.getSynchScope();
3553 SDValue InChain = getRoot();
3555 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3557 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3559 if (I.getAlignment() < VT.getSizeInBits() / 8)
3560 report_fatal_error("Cannot generate unaligned atomic store");
3563 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3565 getValue(I.getPointerOperand()),
3566 getValue(I.getValueOperand()),
3567 I.getPointerOperand(), I.getAlignment(),
3570 DAG.setRoot(OutChain);
3573 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3575 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3576 unsigned Intrinsic) {
3577 bool HasChain = !I.doesNotAccessMemory();
3578 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3580 // Build the operand list.
3581 SmallVector<SDValue, 8> Ops;
3582 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3584 // We don't need to serialize loads against other loads.
3585 Ops.push_back(DAG.getRoot());
3587 Ops.push_back(getRoot());
3591 // Info is set by getTgtMemInstrinsic
3592 TargetLowering::IntrinsicInfo Info;
3593 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3594 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3596 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3597 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3598 Info.opc == ISD::INTRINSIC_W_CHAIN)
3599 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3600 TLI.getPointerTy(DAG.getDataLayout())));
3602 // Add all operands of the call to the operand list.
3603 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3604 SDValue Op = getValue(I.getArgOperand(i));
3608 SmallVector<EVT, 4> ValueVTs;
3609 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3612 ValueVTs.push_back(MVT::Other);
3614 SDVTList VTs = DAG.getVTList(ValueVTs);
3618 if (IsTgtIntrinsic) {
3619 // This is target intrinsic that touches memory
3620 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3621 VTs, Ops, Info.memVT,
3622 MachinePointerInfo(Info.ptrVal, Info.offset),
3623 Info.align, Info.vol,
3624 Info.readMem, Info.writeMem, Info.size);
3625 } else if (!HasChain) {
3626 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3627 } else if (!I.getType()->isVoidTy()) {
3628 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3630 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3634 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3636 PendingLoads.push_back(Chain);
3641 if (!I.getType()->isVoidTy()) {
3642 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3643 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3644 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3647 setValue(&I, Result);
3651 /// GetSignificand - Get the significand and build it into a floating-point
3652 /// number with exponent of 1:
3654 /// Op = (Op & 0x007fffff) | 0x3f800000;
3656 /// where Op is the hexadecimal representation of floating point value.
3658 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3659 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3660 DAG.getConstant(0x007fffff, dl, MVT::i32));
3661 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3662 DAG.getConstant(0x3f800000, dl, MVT::i32));
3663 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3666 /// GetExponent - Get the exponent:
3668 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3670 /// where Op is the hexadecimal representation of floating point value.
3672 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3674 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3675 DAG.getConstant(0x7f800000, dl, MVT::i32));
3676 SDValue t1 = DAG.getNode(
3677 ISD::SRL, dl, MVT::i32, t0,
3678 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3679 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3680 DAG.getConstant(127, dl, MVT::i32));
3681 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3684 /// getF32Constant - Get 32-bit floating point constant.
3686 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3687 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3691 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3692 SelectionDAG &DAG) {
3693 // TODO: What fast-math-flags should be set on the floating-point nodes?
3695 // IntegerPartOfX = ((int32_t)(t0);
3696 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3698 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3699 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3700 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3702 // IntegerPartOfX <<= 23;
3703 IntegerPartOfX = DAG.getNode(
3704 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3705 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3706 DAG.getDataLayout())));
3708 SDValue TwoToFractionalPartOfX;
3709 if (LimitFloatPrecision <= 6) {
3710 // For floating-point precision of 6:
3712 // TwoToFractionalPartOfX =
3714 // (0.735607626f + 0.252464424f * x) * x;
3716 // error 0.0144103317, which is 6 bits
3717 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3718 getF32Constant(DAG, 0x3e814304, dl));
3719 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3720 getF32Constant(DAG, 0x3f3c50c8, dl));
3721 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3722 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3723 getF32Constant(DAG, 0x3f7f5e7e, dl));
3724 } else if (LimitFloatPrecision <= 12) {
3725 // For floating-point precision of 12:
3727 // TwoToFractionalPartOfX =
3730 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3732 // error 0.000107046256, which is 13 to 14 bits
3733 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3734 getF32Constant(DAG, 0x3da235e3, dl));
3735 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3736 getF32Constant(DAG, 0x3e65b8f3, dl));
3737 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3738 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3739 getF32Constant(DAG, 0x3f324b07, dl));
3740 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3741 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3742 getF32Constant(DAG, 0x3f7ff8fd, dl));
3743 } else { // LimitFloatPrecision <= 18
3744 // For floating-point precision of 18:
3746 // TwoToFractionalPartOfX =
3750 // (0.554906021e-1f +
3751 // (0.961591928e-2f +
3752 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3753 // error 2.47208000*10^(-7), which is better than 18 bits
3754 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3755 getF32Constant(DAG, 0x3924b03e, dl));
3756 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3757 getF32Constant(DAG, 0x3ab24b87, dl));
3758 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3759 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3760 getF32Constant(DAG, 0x3c1d8c17, dl));
3761 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3762 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3763 getF32Constant(DAG, 0x3d634a1d, dl));
3764 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3765 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3766 getF32Constant(DAG, 0x3e75fe14, dl));
3767 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3768 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3769 getF32Constant(DAG, 0x3f317234, dl));
3770 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3771 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3772 getF32Constant(DAG, 0x3f800000, dl));
3775 // Add the exponent into the result in integer domain.
3776 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3777 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3778 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3781 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3782 /// limited-precision mode.
3783 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3784 const TargetLowering &TLI) {
3785 if (Op.getValueType() == MVT::f32 &&
3786 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3788 // Put the exponent in the right bit position for later addition to the
3791 // #define LOG2OFe 1.4426950f
3792 // t0 = Op * LOG2OFe
3794 // TODO: What fast-math-flags should be set here?
3795 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3796 getF32Constant(DAG, 0x3fb8aa3b, dl));
3797 return getLimitedPrecisionExp2(t0, dl, DAG);
3800 // No special expansion.
3801 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3804 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3805 /// limited-precision mode.
3806 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3807 const TargetLowering &TLI) {
3809 // TODO: What fast-math-flags should be set on the floating-point nodes?
3811 if (Op.getValueType() == MVT::f32 &&
3812 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3813 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3815 // Scale the exponent by log(2) [0.69314718f].
3816 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3817 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3818 getF32Constant(DAG, 0x3f317218, dl));
3820 // Get the significand and build it into a floating-point number with
3822 SDValue X = GetSignificand(DAG, Op1, dl);
3824 SDValue LogOfMantissa;
3825 if (LimitFloatPrecision <= 6) {
3826 // For floating-point precision of 6:
3830 // (1.4034025f - 0.23903021f * x) * x;
3832 // error 0.0034276066, which is better than 8 bits
3833 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3834 getF32Constant(DAG, 0xbe74c456, dl));
3835 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3836 getF32Constant(DAG, 0x3fb3a2b1, dl));
3837 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3838 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3839 getF32Constant(DAG, 0x3f949a29, dl));
3840 } else if (LimitFloatPrecision <= 12) {
3841 // For floating-point precision of 12:
3847 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3849 // error 0.000061011436, which is 14 bits
3850 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3851 getF32Constant(DAG, 0xbd67b6d6, dl));
3852 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3853 getF32Constant(DAG, 0x3ee4f4b8, dl));
3854 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3855 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3856 getF32Constant(DAG, 0x3fbc278b, dl));
3857 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3858 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3859 getF32Constant(DAG, 0x40348e95, dl));
3860 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3861 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3862 getF32Constant(DAG, 0x3fdef31a, dl));
3863 } else { // LimitFloatPrecision <= 18
3864 // For floating-point precision of 18:
3872 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3874 // error 0.0000023660568, which is better than 18 bits
3875 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3876 getF32Constant(DAG, 0xbc91e5ac, dl));
3877 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3878 getF32Constant(DAG, 0x3e4350aa, dl));
3879 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3880 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3881 getF32Constant(DAG, 0x3f60d3e3, dl));
3882 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3883 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3884 getF32Constant(DAG, 0x4011cdf0, dl));
3885 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3886 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3887 getF32Constant(DAG, 0x406cfd1c, dl));
3888 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3889 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3890 getF32Constant(DAG, 0x408797cb, dl));
3891 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3892 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3893 getF32Constant(DAG, 0x4006dcab, dl));
3896 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3899 // No special expansion.
3900 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3903 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3904 /// limited-precision mode.
3905 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3906 const TargetLowering &TLI) {
3908 // TODO: What fast-math-flags should be set on the floating-point nodes?
3910 if (Op.getValueType() == MVT::f32 &&
3911 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3912 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3914 // Get the exponent.
3915 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3917 // Get the significand and build it into a floating-point number with
3919 SDValue X = GetSignificand(DAG, Op1, dl);
3921 // Different possible minimax approximations of significand in
3922 // floating-point for various degrees of accuracy over [1,2].
3923 SDValue Log2ofMantissa;
3924 if (LimitFloatPrecision <= 6) {
3925 // For floating-point precision of 6:
3927 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3929 // error 0.0049451742, which is more than 7 bits
3930 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3931 getF32Constant(DAG, 0xbeb08fe0, dl));
3932 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3933 getF32Constant(DAG, 0x40019463, dl));
3934 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3935 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3936 getF32Constant(DAG, 0x3fd6633d, dl));
3937 } else if (LimitFloatPrecision <= 12) {
3938 // For floating-point precision of 12:
3944 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3946 // error 0.0000876136000, which is better than 13 bits
3947 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3948 getF32Constant(DAG, 0xbda7262e, dl));
3949 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3950 getF32Constant(DAG, 0x3f25280b, dl));
3951 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3952 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3953 getF32Constant(DAG, 0x4007b923, dl));
3954 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3955 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3956 getF32Constant(DAG, 0x40823e2f, dl));
3957 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3958 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3959 getF32Constant(DAG, 0x4020d29c, dl));
3960 } else { // LimitFloatPrecision <= 18
3961 // For floating-point precision of 18:
3970 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3972 // error 0.0000018516, which is better than 18 bits
3973 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3974 getF32Constant(DAG, 0xbcd2769e, dl));
3975 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3976 getF32Constant(DAG, 0x3e8ce0b9, dl));
3977 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3978 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3979 getF32Constant(DAG, 0x3fa22ae7, dl));
3980 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3981 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3982 getF32Constant(DAG, 0x40525723, dl));
3983 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3984 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3985 getF32Constant(DAG, 0x40aaf200, dl));
3986 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3987 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3988 getF32Constant(DAG, 0x40c39dad, dl));
3989 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3990 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3991 getF32Constant(DAG, 0x4042902c, dl));
3994 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3997 // No special expansion.
3998 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4001 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4002 /// limited-precision mode.
4003 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4004 const TargetLowering &TLI) {
4006 // TODO: What fast-math-flags should be set on the floating-point nodes?
4008 if (Op.getValueType() == MVT::f32 &&
4009 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4010 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4012 // Scale the exponent by log10(2) [0.30102999f].
4013 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4014 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4015 getF32Constant(DAG, 0x3e9a209a, dl));
4017 // Get the significand and build it into a floating-point number with
4019 SDValue X = GetSignificand(DAG, Op1, dl);
4021 SDValue Log10ofMantissa;
4022 if (LimitFloatPrecision <= 6) {
4023 // For floating-point precision of 6:
4025 // Log10ofMantissa =
4027 // (0.60948995f - 0.10380950f * x) * x;
4029 // error 0.0014886165, which is 6 bits
4030 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4031 getF32Constant(DAG, 0xbdd49a13, dl));
4032 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4033 getF32Constant(DAG, 0x3f1c0789, dl));
4034 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4035 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4036 getF32Constant(DAG, 0x3f011300, dl));
4037 } else if (LimitFloatPrecision <= 12) {
4038 // For floating-point precision of 12:
4040 // Log10ofMantissa =
4043 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4045 // error 0.00019228036, which is better than 12 bits
4046 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4047 getF32Constant(DAG, 0x3d431f31, dl));
4048 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4049 getF32Constant(DAG, 0x3ea21fb2, dl));
4050 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4051 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4052 getF32Constant(DAG, 0x3f6ae232, dl));
4053 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4054 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4055 getF32Constant(DAG, 0x3f25f7c3, dl));
4056 } else { // LimitFloatPrecision <= 18
4057 // For floating-point precision of 18:
4059 // Log10ofMantissa =
4064 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4066 // error 0.0000037995730, which is better than 18 bits
4067 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4068 getF32Constant(DAG, 0x3c5d51ce, dl));
4069 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4070 getF32Constant(DAG, 0x3e00685a, dl));
4071 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4072 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4073 getF32Constant(DAG, 0x3efb6798, dl));
4074 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4075 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4076 getF32Constant(DAG, 0x3f88d192, dl));
4077 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4078 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4079 getF32Constant(DAG, 0x3fc4316c, dl));
4080 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4081 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4082 getF32Constant(DAG, 0x3f57ce70, dl));
4085 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4088 // No special expansion.
4089 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4092 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4093 /// limited-precision mode.
4094 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4095 const TargetLowering &TLI) {
4096 if (Op.getValueType() == MVT::f32 &&
4097 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4098 return getLimitedPrecisionExp2(Op, dl, DAG);
4100 // No special expansion.
4101 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4104 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4105 /// limited-precision mode with x == 10.0f.
4106 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4107 SelectionDAG &DAG, const TargetLowering &TLI) {
4108 bool IsExp10 = false;
4109 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4110 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4111 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4113 IsExp10 = LHSC->isExactlyValue(Ten);
4117 // TODO: What fast-math-flags should be set on the FMUL node?
4119 // Put the exponent in the right bit position for later addition to the
4122 // #define LOG2OF10 3.3219281f
4123 // t0 = Op * LOG2OF10;
4124 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4125 getF32Constant(DAG, 0x40549a78, dl));
4126 return getLimitedPrecisionExp2(t0, dl, DAG);
4129 // No special expansion.
4130 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4134 /// ExpandPowI - Expand a llvm.powi intrinsic.
4135 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4136 SelectionDAG &DAG) {
4137 // If RHS is a constant, we can expand this out to a multiplication tree,
4138 // otherwise we end up lowering to a call to __powidf2 (for example). When
4139 // optimizing for size, we only want to do this if the expansion would produce
4140 // a small number of multiplies, otherwise we do the full expansion.
4141 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4142 // Get the exponent as a positive value.
4143 unsigned Val = RHSC->getSExtValue();
4144 if ((int)Val < 0) Val = -Val;
4146 // powi(x, 0) -> 1.0
4148 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4150 const Function *F = DAG.getMachineFunction().getFunction();
4151 if (!F->optForSize() ||
4152 // If optimizing for size, don't insert too many multiplies.
4153 // This inserts up to 5 multiplies.
4154 countPopulation(Val) + Log2_32(Val) < 7) {
4155 // We use the simple binary decomposition method to generate the multiply
4156 // sequence. There are more optimal ways to do this (for example,
4157 // powi(x,15) generates one more multiply than it should), but this has
4158 // the benefit of being both really simple and much better than a libcall.
4159 SDValue Res; // Logically starts equal to 1.0
4160 SDValue CurSquare = LHS;
4161 // TODO: Intrinsics should have fast-math-flags that propagate to these
4166 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4168 Res = CurSquare; // 1.0*CurSquare.
4171 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4172 CurSquare, CurSquare);
4176 // If the original was negative, invert the result, producing 1/(x*x*x).
4177 if (RHSC->getSExtValue() < 0)
4178 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4179 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4184 // Otherwise, expand to a libcall.
4185 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4188 // getTruncatedArgReg - Find underlying register used for an truncated
4190 static unsigned getTruncatedArgReg(const SDValue &N) {
4191 if (N.getOpcode() != ISD::TRUNCATE)
4194 const SDValue &Ext = N.getOperand(0);
4195 if (Ext.getOpcode() == ISD::AssertZext ||
4196 Ext.getOpcode() == ISD::AssertSext) {
4197 const SDValue &CFR = Ext.getOperand(0);
4198 if (CFR.getOpcode() == ISD::CopyFromReg)
4199 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4200 if (CFR.getOpcode() == ISD::TRUNCATE)
4201 return getTruncatedArgReg(CFR);
4206 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4207 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4208 /// At the end of instruction selection, they will be inserted to the entry BB.
4209 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4210 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4211 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4212 const Argument *Arg = dyn_cast<Argument>(V);
4216 MachineFunction &MF = DAG.getMachineFunction();
4217 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4219 // Ignore inlined function arguments here.
4221 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4222 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4225 Optional<MachineOperand> Op;
4226 // Some arguments' frame index is recorded during argument lowering.
4227 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4228 Op = MachineOperand::CreateFI(FI);
4230 if (!Op && N.getNode()) {
4232 if (N.getOpcode() == ISD::CopyFromReg)
4233 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4235 Reg = getTruncatedArgReg(N);
4236 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4237 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4238 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4243 Op = MachineOperand::CreateReg(Reg, false);
4247 // Check if ValueMap has reg number.
4248 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4249 if (VMI != FuncInfo.ValueMap.end())
4250 Op = MachineOperand::CreateReg(VMI->second, false);
4253 if (!Op && N.getNode())
4254 // Check if frame index is available.
4255 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4256 if (FrameIndexSDNode *FINode =
4257 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4258 Op = MachineOperand::CreateFI(FINode->getIndex());
4263 assert(Variable->isValidLocationForIntrinsic(DL) &&
4264 "Expected inlined-at fields to agree");
4266 FuncInfo.ArgDbgValues.push_back(
4267 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4268 Op->getReg(), Offset, Variable, Expr));
4270 FuncInfo.ArgDbgValues.push_back(
4271 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4274 .addMetadata(Variable)
4275 .addMetadata(Expr));
4280 // VisualStudio defines setjmp as _setjmp
4281 #if defined(_MSC_VER) && defined(setjmp) && \
4282 !defined(setjmp_undefined_for_msvc)
4283 # pragma push_macro("setjmp")
4285 # define setjmp_undefined_for_msvc
4288 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4289 /// we want to emit this as a call to a named external function, return the name
4290 /// otherwise lower it and return null.
4292 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4293 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4294 SDLoc sdl = getCurSDLoc();
4295 DebugLoc dl = getCurDebugLoc();
4298 switch (Intrinsic) {
4300 // By default, turn this into a target intrinsic node.
4301 visitTargetIntrinsic(I, Intrinsic);
4303 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4304 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4305 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4306 case Intrinsic::returnaddress:
4307 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4308 TLI.getPointerTy(DAG.getDataLayout()),
4309 getValue(I.getArgOperand(0))));
4311 case Intrinsic::frameaddress:
4312 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4313 TLI.getPointerTy(DAG.getDataLayout()),
4314 getValue(I.getArgOperand(0))));
4316 case Intrinsic::read_register: {
4317 Value *Reg = I.getArgOperand(0);
4318 SDValue Chain = getRoot();
4320 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4321 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4322 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4323 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4325 DAG.setRoot(Res.getValue(1));
4328 case Intrinsic::write_register: {
4329 Value *Reg = I.getArgOperand(0);
4330 Value *RegValue = I.getArgOperand(1);
4331 SDValue Chain = getRoot();
4333 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4334 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4335 RegName, getValue(RegValue)));
4338 case Intrinsic::setjmp:
4339 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4340 case Intrinsic::longjmp:
4341 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4342 case Intrinsic::memcpy: {
4343 // FIXME: this definition of "user defined address space" is x86-specific
4344 // Assert for address < 256 since we support only user defined address
4346 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4348 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4350 "Unknown address space");
4351 SDValue Op1 = getValue(I.getArgOperand(0));
4352 SDValue Op2 = getValue(I.getArgOperand(1));
4353 SDValue Op3 = getValue(I.getArgOperand(2));
4354 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4356 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4357 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4358 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4359 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4361 MachinePointerInfo(I.getArgOperand(0)),
4362 MachinePointerInfo(I.getArgOperand(1)));
4363 updateDAGForMaybeTailCall(MC);
4366 case Intrinsic::memset: {
4367 // FIXME: this definition of "user defined address space" is x86-specific
4368 // Assert for address < 256 since we support only user defined address
4370 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4372 "Unknown address space");
4373 SDValue Op1 = getValue(I.getArgOperand(0));
4374 SDValue Op2 = getValue(I.getArgOperand(1));
4375 SDValue Op3 = getValue(I.getArgOperand(2));
4376 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4378 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4379 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4380 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4381 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4382 isTC, MachinePointerInfo(I.getArgOperand(0)));
4383 updateDAGForMaybeTailCall(MS);
4386 case Intrinsic::memmove: {
4387 // FIXME: this definition of "user defined address space" is x86-specific
4388 // Assert for address < 256 since we support only user defined address
4390 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4392 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4394 "Unknown address space");
4395 SDValue Op1 = getValue(I.getArgOperand(0));
4396 SDValue Op2 = getValue(I.getArgOperand(1));
4397 SDValue Op3 = getValue(I.getArgOperand(2));
4398 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4400 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4401 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4402 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4403 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4404 isTC, MachinePointerInfo(I.getArgOperand(0)),
4405 MachinePointerInfo(I.getArgOperand(1)));
4406 updateDAGForMaybeTailCall(MM);
4409 case Intrinsic::dbg_declare: {
4410 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4411 DILocalVariable *Variable = DI.getVariable();
4412 DIExpression *Expression = DI.getExpression();
4413 const Value *Address = DI.getAddress();
4414 assert(Variable && "Missing variable");
4416 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4420 // Check if address has undef value.
4421 if (isa<UndefValue>(Address) ||
4422 (Address->use_empty() && !isa<Argument>(Address))) {
4423 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4427 SDValue &N = NodeMap[Address];
4428 if (!N.getNode() && isa<Argument>(Address))
4429 // Check unused arguments map.
4430 N = UnusedArgNodeMap[Address];
4433 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4434 Address = BCI->getOperand(0);
4435 // Parameters are handled specially.
4436 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4438 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4440 if (isParameter && !AI) {
4441 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4443 // Byval parameter. We have a frame index at this point.
4444 SDV = DAG.getFrameIndexDbgValue(
4445 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4447 // Address is an argument, so try to emit its dbg value using
4448 // virtual register info from the FuncInfo.ValueMap.
4449 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4454 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4455 true, 0, dl, SDNodeOrder);
4457 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4459 // If Address is an argument then try to emit its dbg value using
4460 // virtual register info from the FuncInfo.ValueMap.
4461 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4463 // If variable is pinned by a alloca in dominating bb then
4464 // use StaticAllocaMap.
4465 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4466 if (AI->getParent() != DI.getParent()) {
4467 DenseMap<const AllocaInst*, int>::iterator SI =
4468 FuncInfo.StaticAllocaMap.find(AI);
4469 if (SI != FuncInfo.StaticAllocaMap.end()) {
4470 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4471 0, dl, SDNodeOrder);
4472 DAG.AddDbgValue(SDV, nullptr, false);
4477 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4482 case Intrinsic::dbg_value: {
4483 const DbgValueInst &DI = cast<DbgValueInst>(I);
4484 assert(DI.getVariable() && "Missing variable");
4486 DILocalVariable *Variable = DI.getVariable();
4487 DIExpression *Expression = DI.getExpression();
4488 uint64_t Offset = DI.getOffset();
4489 const Value *V = DI.getValue();
4494 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4495 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4497 DAG.AddDbgValue(SDV, nullptr, false);
4499 // Do not use getValue() in here; we don't want to generate code at
4500 // this point if it hasn't been done yet.
4501 SDValue N = NodeMap[V];
4502 if (!N.getNode() && isa<Argument>(V))
4503 // Check unused arguments map.
4504 N = UnusedArgNodeMap[V];
4506 // A dbg.value for an alloca is always indirect.
4507 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4508 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4510 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4511 IsIndirect, Offset, dl, SDNodeOrder);
4512 DAG.AddDbgValue(SDV, N.getNode(), false);
4514 } else if (!V->use_empty() ) {
4515 // Do not call getValue(V) yet, as we don't want to generate code.
4516 // Remember it for later.
4517 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4518 DanglingDebugInfoMap[V] = DDI;
4520 // We may expand this to cover more cases. One case where we have no
4521 // data available is an unreferenced parameter.
4522 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4526 // Build a debug info table entry.
4527 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4528 V = BCI->getOperand(0);
4529 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4530 // Don't handle byval struct arguments or VLAs, for example.
4532 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4533 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4536 DenseMap<const AllocaInst*, int>::iterator SI =
4537 FuncInfo.StaticAllocaMap.find(AI);
4538 if (SI == FuncInfo.StaticAllocaMap.end())
4539 return nullptr; // VLAs.
4543 case Intrinsic::eh_typeid_for: {
4544 // Find the type id for the given typeinfo.
4545 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4546 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4547 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4552 case Intrinsic::eh_return_i32:
4553 case Intrinsic::eh_return_i64:
4554 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4555 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4558 getValue(I.getArgOperand(0)),
4559 getValue(I.getArgOperand(1))));
4561 case Intrinsic::eh_unwind_init:
4562 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4564 case Intrinsic::eh_dwarf_cfa: {
4565 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4566 TLI.getPointerTy(DAG.getDataLayout()));
4567 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4568 CfaArg.getValueType(),
4569 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4570 CfaArg.getValueType()),
4572 SDValue FA = DAG.getNode(
4573 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4574 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4575 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4579 case Intrinsic::eh_sjlj_callsite: {
4580 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4581 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4582 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4583 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4585 MMI.setCurrentCallSite(CI->getZExtValue());
4588 case Intrinsic::eh_sjlj_functioncontext: {
4589 // Get and store the index of the function context.
4590 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4592 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4593 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4594 MFI->setFunctionContextIndex(FI);
4597 case Intrinsic::eh_sjlj_setjmp: {
4600 Ops[1] = getValue(I.getArgOperand(0));
4601 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4602 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4603 setValue(&I, Op.getValue(0));
4604 DAG.setRoot(Op.getValue(1));
4607 case Intrinsic::eh_sjlj_longjmp: {
4608 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4609 getRoot(), getValue(I.getArgOperand(0))));
4612 case Intrinsic::eh_sjlj_setup_dispatch: {
4613 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4618 case Intrinsic::masked_gather:
4619 visitMaskedGather(I);
4621 case Intrinsic::masked_load:
4624 case Intrinsic::masked_scatter:
4625 visitMaskedScatter(I);
4627 case Intrinsic::masked_store:
4628 visitMaskedStore(I);
4630 case Intrinsic::x86_mmx_pslli_w:
4631 case Intrinsic::x86_mmx_pslli_d:
4632 case Intrinsic::x86_mmx_pslli_q:
4633 case Intrinsic::x86_mmx_psrli_w:
4634 case Intrinsic::x86_mmx_psrli_d:
4635 case Intrinsic::x86_mmx_psrli_q:
4636 case Intrinsic::x86_mmx_psrai_w:
4637 case Intrinsic::x86_mmx_psrai_d: {
4638 SDValue ShAmt = getValue(I.getArgOperand(1));
4639 if (isa<ConstantSDNode>(ShAmt)) {
4640 visitTargetIntrinsic(I, Intrinsic);
4643 unsigned NewIntrinsic = 0;
4644 EVT ShAmtVT = MVT::v2i32;
4645 switch (Intrinsic) {
4646 case Intrinsic::x86_mmx_pslli_w:
4647 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4649 case Intrinsic::x86_mmx_pslli_d:
4650 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4652 case Intrinsic::x86_mmx_pslli_q:
4653 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4655 case Intrinsic::x86_mmx_psrli_w:
4656 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4658 case Intrinsic::x86_mmx_psrli_d:
4659 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4661 case Intrinsic::x86_mmx_psrli_q:
4662 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4664 case Intrinsic::x86_mmx_psrai_w:
4665 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4667 case Intrinsic::x86_mmx_psrai_d:
4668 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4670 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4673 // The vector shift intrinsics with scalars uses 32b shift amounts but
4674 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4676 // We must do this early because v2i32 is not a legal type.
4679 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4680 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4681 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4682 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4683 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4684 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4685 getValue(I.getArgOperand(0)), ShAmt);
4689 case Intrinsic::convertff:
4690 case Intrinsic::convertfsi:
4691 case Intrinsic::convertfui:
4692 case Intrinsic::convertsif:
4693 case Intrinsic::convertuif:
4694 case Intrinsic::convertss:
4695 case Intrinsic::convertsu:
4696 case Intrinsic::convertus:
4697 case Intrinsic::convertuu: {
4698 ISD::CvtCode Code = ISD::CVT_INVALID;
4699 switch (Intrinsic) {
4700 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4701 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4702 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4703 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4704 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4705 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4706 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4707 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4708 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4709 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4711 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4712 const Value *Op1 = I.getArgOperand(0);
4713 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4714 DAG.getValueType(DestVT),
4715 DAG.getValueType(getValue(Op1).getValueType()),
4716 getValue(I.getArgOperand(1)),
4717 getValue(I.getArgOperand(2)),
4722 case Intrinsic::powi:
4723 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4724 getValue(I.getArgOperand(1)), DAG));
4726 case Intrinsic::log:
4727 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4729 case Intrinsic::log2:
4730 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4732 case Intrinsic::log10:
4733 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4735 case Intrinsic::exp:
4736 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4738 case Intrinsic::exp2:
4739 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4741 case Intrinsic::pow:
4742 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4743 getValue(I.getArgOperand(1)), DAG, TLI));
4745 case Intrinsic::sqrt:
4746 case Intrinsic::fabs:
4747 case Intrinsic::sin:
4748 case Intrinsic::cos:
4749 case Intrinsic::floor:
4750 case Intrinsic::ceil:
4751 case Intrinsic::trunc:
4752 case Intrinsic::rint:
4753 case Intrinsic::nearbyint:
4754 case Intrinsic::round: {
4756 switch (Intrinsic) {
4757 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4758 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4759 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4760 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4761 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4762 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4763 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4764 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4765 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4766 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4767 case Intrinsic::round: Opcode = ISD::FROUND; break;
4770 setValue(&I, DAG.getNode(Opcode, sdl,
4771 getValue(I.getArgOperand(0)).getValueType(),
4772 getValue(I.getArgOperand(0))));
4775 case Intrinsic::minnum:
4776 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4777 getValue(I.getArgOperand(0)).getValueType(),
4778 getValue(I.getArgOperand(0)),
4779 getValue(I.getArgOperand(1))));
4781 case Intrinsic::maxnum:
4782 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4783 getValue(I.getArgOperand(0)).getValueType(),
4784 getValue(I.getArgOperand(0)),
4785 getValue(I.getArgOperand(1))));
4787 case Intrinsic::copysign:
4788 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4789 getValue(I.getArgOperand(0)).getValueType(),
4790 getValue(I.getArgOperand(0)),
4791 getValue(I.getArgOperand(1))));
4793 case Intrinsic::fma:
4794 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4795 getValue(I.getArgOperand(0)).getValueType(),
4796 getValue(I.getArgOperand(0)),
4797 getValue(I.getArgOperand(1)),
4798 getValue(I.getArgOperand(2))));
4800 case Intrinsic::fmuladd: {
4801 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4802 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4803 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4804 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4805 getValue(I.getArgOperand(0)).getValueType(),
4806 getValue(I.getArgOperand(0)),
4807 getValue(I.getArgOperand(1)),
4808 getValue(I.getArgOperand(2))));
4810 // TODO: Intrinsic calls should have fast-math-flags.
4811 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4812 getValue(I.getArgOperand(0)).getValueType(),
4813 getValue(I.getArgOperand(0)),
4814 getValue(I.getArgOperand(1)));
4815 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4816 getValue(I.getArgOperand(0)).getValueType(),
4818 getValue(I.getArgOperand(2)));
4823 case Intrinsic::convert_to_fp16:
4824 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4825 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4826 getValue(I.getArgOperand(0)),
4827 DAG.getTargetConstant(0, sdl,
4830 case Intrinsic::convert_from_fp16:
4831 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4832 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4833 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4834 getValue(I.getArgOperand(0)))));
4836 case Intrinsic::pcmarker: {
4837 SDValue Tmp = getValue(I.getArgOperand(0));
4838 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4841 case Intrinsic::readcyclecounter: {
4842 SDValue Op = getRoot();
4843 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4844 DAG.getVTList(MVT::i64, MVT::Other), Op);
4846 DAG.setRoot(Res.getValue(1));
4849 case Intrinsic::bswap:
4850 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4851 getValue(I.getArgOperand(0)).getValueType(),
4852 getValue(I.getArgOperand(0))));
4854 case Intrinsic::uabsdiff:
4855 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4856 getValue(I.getArgOperand(0)).getValueType(),
4857 getValue(I.getArgOperand(0)),
4858 getValue(I.getArgOperand(1))));
4860 case Intrinsic::sabsdiff:
4861 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4862 getValue(I.getArgOperand(0)).getValueType(),
4863 getValue(I.getArgOperand(0)),
4864 getValue(I.getArgOperand(1))));
4866 case Intrinsic::cttz: {
4867 SDValue Arg = getValue(I.getArgOperand(0));
4868 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4869 EVT Ty = Arg.getValueType();
4870 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4874 case Intrinsic::ctlz: {
4875 SDValue Arg = getValue(I.getArgOperand(0));
4876 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4877 EVT Ty = Arg.getValueType();
4878 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4882 case Intrinsic::ctpop: {
4883 SDValue Arg = getValue(I.getArgOperand(0));
4884 EVT Ty = Arg.getValueType();
4885 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4888 case Intrinsic::stacksave: {
4889 SDValue Op = getRoot();
4891 ISD::STACKSAVE, sdl,
4892 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4894 DAG.setRoot(Res.getValue(1));
4897 case Intrinsic::stackrestore: {
4898 Res = getValue(I.getArgOperand(0));
4899 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4902 case Intrinsic::stackprotector: {
4903 // Emit code into the DAG to store the stack guard onto the stack.
4904 MachineFunction &MF = DAG.getMachineFunction();
4905 MachineFrameInfo *MFI = MF.getFrameInfo();
4906 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4907 SDValue Src, Chain = getRoot();
4908 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4909 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4911 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4912 // global variable __stack_chk_guard.
4914 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4915 if (BC->getOpcode() == Instruction::BitCast)
4916 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4918 if (GV && TLI.useLoadStackGuardNode()) {
4919 // Emit a LOAD_STACK_GUARD node.
4920 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4922 MachinePointerInfo MPInfo(GV);
4923 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4924 unsigned Flags = MachineMemOperand::MOLoad |
4925 MachineMemOperand::MOInvariant;
4926 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4927 PtrTy.getSizeInBits() / 8,
4928 DAG.getEVTAlignment(PtrTy));
4929 Node->setMemRefs(MemRefs, MemRefs + 1);
4931 // Copy the guard value to a virtual register so that it can be
4932 // retrieved in the epilogue.
4933 Src = SDValue(Node, 0);
4934 const TargetRegisterClass *RC =
4935 TLI.getRegClassFor(Src.getSimpleValueType());
4936 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4938 SPDescriptor.setGuardReg(Reg);
4939 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4941 Src = getValue(I.getArgOperand(0)); // The guard's value.
4944 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4946 int FI = FuncInfo.StaticAllocaMap[Slot];
4947 MFI->setStackProtectorIndex(FI);
4949 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4951 // Store the stack protector onto the stack.
4952 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4953 DAG.getMachineFunction(), FI),
4959 case Intrinsic::objectsize: {
4960 // If we don't know by now, we're never going to know.
4961 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4963 assert(CI && "Non-constant type in __builtin_object_size?");
4965 SDValue Arg = getValue(I.getCalledValue());
4966 EVT Ty = Arg.getValueType();
4969 Res = DAG.getConstant(-1ULL, sdl, Ty);
4971 Res = DAG.getConstant(0, sdl, Ty);
4976 case Intrinsic::annotation:
4977 case Intrinsic::ptr_annotation:
4978 // Drop the intrinsic, but forward the value
4979 setValue(&I, getValue(I.getOperand(0)));
4981 case Intrinsic::assume:
4982 case Intrinsic::var_annotation:
4983 // Discard annotate attributes and assumptions
4986 case Intrinsic::init_trampoline: {
4987 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4991 Ops[1] = getValue(I.getArgOperand(0));
4992 Ops[2] = getValue(I.getArgOperand(1));
4993 Ops[3] = getValue(I.getArgOperand(2));
4994 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4995 Ops[5] = DAG.getSrcValue(F);
4997 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5002 case Intrinsic::adjust_trampoline: {
5003 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5004 TLI.getPointerTy(DAG.getDataLayout()),
5005 getValue(I.getArgOperand(0))));
5008 case Intrinsic::gcroot:
5010 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5011 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5013 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5014 GFI->addStackRoot(FI->getIndex(), TypeMap);
5017 case Intrinsic::gcread:
5018 case Intrinsic::gcwrite:
5019 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5020 case Intrinsic::flt_rounds:
5021 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5024 case Intrinsic::expect: {
5025 // Just replace __builtin_expect(exp, c) with EXP.
5026 setValue(&I, getValue(I.getArgOperand(0)));
5030 case Intrinsic::debugtrap:
5031 case Intrinsic::trap: {
5032 StringRef TrapFuncName =
5034 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5035 .getValueAsString();
5036 if (TrapFuncName.empty()) {
5037 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5038 ISD::TRAP : ISD::DEBUGTRAP;
5039 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5042 TargetLowering::ArgListTy Args;
5044 TargetLowering::CallLoweringInfo CLI(DAG);
5045 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5046 CallingConv::C, I.getType(),
5047 DAG.getExternalSymbol(TrapFuncName.data(),
5048 TLI.getPointerTy(DAG.getDataLayout())),
5049 std::move(Args), 0);
5051 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5052 DAG.setRoot(Result.second);
5056 case Intrinsic::uadd_with_overflow:
5057 case Intrinsic::sadd_with_overflow:
5058 case Intrinsic::usub_with_overflow:
5059 case Intrinsic::ssub_with_overflow:
5060 case Intrinsic::umul_with_overflow:
5061 case Intrinsic::smul_with_overflow: {
5063 switch (Intrinsic) {
5064 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5065 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5066 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5067 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5068 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5069 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5070 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5072 SDValue Op1 = getValue(I.getArgOperand(0));
5073 SDValue Op2 = getValue(I.getArgOperand(1));
5075 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5076 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5079 case Intrinsic::prefetch: {
5081 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5083 Ops[1] = getValue(I.getArgOperand(0));
5084 Ops[2] = getValue(I.getArgOperand(1));
5085 Ops[3] = getValue(I.getArgOperand(2));
5086 Ops[4] = getValue(I.getArgOperand(3));
5087 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5088 DAG.getVTList(MVT::Other), Ops,
5089 EVT::getIntegerVT(*Context, 8),
5090 MachinePointerInfo(I.getArgOperand(0)),
5092 false, /* volatile */
5094 rw==1)); /* write */
5097 case Intrinsic::lifetime_start:
5098 case Intrinsic::lifetime_end: {
5099 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5100 // Stack coloring is not enabled in O0, discard region information.
5101 if (TM.getOptLevel() == CodeGenOpt::None)
5104 SmallVector<Value *, 4> Allocas;
5105 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5107 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5108 E = Allocas.end(); Object != E; ++Object) {
5109 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5111 // Could not find an Alloca.
5112 if (!LifetimeObject)
5115 // First check that the Alloca is static, otherwise it won't have a
5116 // valid frame index.
5117 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5118 if (SI == FuncInfo.StaticAllocaMap.end())
5121 int FI = SI->second;
5126 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5127 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5129 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5134 case Intrinsic::invariant_start:
5135 // Discard region information.
5136 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5138 case Intrinsic::invariant_end:
5139 // Discard region information.
5141 case Intrinsic::stackprotectorcheck: {
5142 // Do not actually emit anything for this basic block. Instead we initialize
5143 // the stack protector descriptor and export the guard variable so we can
5144 // access it in FinishBasicBlock.
5145 const BasicBlock *BB = I.getParent();
5146 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5147 ExportFromCurrentBlock(SPDescriptor.getGuard());
5149 // Flush our exports since we are going to process a terminator.
5150 (void)getControlRoot();
5153 case Intrinsic::clear_cache:
5154 return TLI.getClearCacheBuiltinName();
5155 case Intrinsic::eh_actions:
5156 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5158 case Intrinsic::donothing:
5161 case Intrinsic::experimental_stackmap: {
5165 case Intrinsic::experimental_patchpoint_void:
5166 case Intrinsic::experimental_patchpoint_i64: {
5167 visitPatchpoint(&I);
5170 case Intrinsic::experimental_gc_statepoint: {
5174 case Intrinsic::experimental_gc_result_int:
5175 case Intrinsic::experimental_gc_result_float:
5176 case Intrinsic::experimental_gc_result_ptr:
5177 case Intrinsic::experimental_gc_result: {
5181 case Intrinsic::experimental_gc_relocate: {
5185 case Intrinsic::instrprof_increment:
5186 llvm_unreachable("instrprof failed to lower an increment");
5188 case Intrinsic::localescape: {
5189 MachineFunction &MF = DAG.getMachineFunction();
5190 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5192 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5193 // is the same on all targets.
5194 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5195 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5196 if (isa<ConstantPointerNull>(Arg))
5197 continue; // Skip null pointers. They represent a hole in index space.
5198 AllocaInst *Slot = cast<AllocaInst>(Arg);
5199 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5200 "can only escape static allocas");
5201 int FI = FuncInfo.StaticAllocaMap[Slot];
5202 MCSymbol *FrameAllocSym =
5203 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5204 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5205 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5206 TII->get(TargetOpcode::LOCAL_ESCAPE))
5207 .addSym(FrameAllocSym)
5214 case Intrinsic::localrecover: {
5215 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5216 MachineFunction &MF = DAG.getMachineFunction();
5217 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5219 // Get the symbol that defines the frame offset.
5220 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5221 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5222 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5223 MCSymbol *FrameAllocSym =
5224 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5225 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5227 // Create a MCSymbol for the label to avoid any target lowering
5228 // that would make this PC relative.
5229 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5231 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5233 // Add the offset to the FP.
5234 Value *FP = I.getArgOperand(1);
5235 SDValue FPVal = getValue(FP);
5236 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5241 case Intrinsic::eh_begincatch:
5242 case Intrinsic::eh_endcatch:
5243 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5244 case Intrinsic::eh_exceptioncode_old: {
5245 unsigned Reg = TLI.getExceptionPointerRegister();
5246 assert(Reg && "cannot get exception code on this platform");
5247 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5248 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5249 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5250 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5252 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5253 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5258 case Intrinsic::eh_exceptionpointer:
5259 case Intrinsic::eh_exceptioncode: {
5260 // Get the exception pointer vreg, copy from it, and resize it to fit.
5261 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
5262 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5263 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5264 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
5266 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5267 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5274 std::pair<SDValue, SDValue>
5275 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5276 const BasicBlock *EHPadBB) {
5277 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5278 MCSymbol *BeginLabel = nullptr;
5281 // Insert a label before the invoke call to mark the try range. This can be
5282 // used to detect deletion of the invoke via the MachineModuleInfo.
5283 BeginLabel = MMI.getContext().createTempSymbol();
5285 // For SjLj, keep track of which landing pads go with which invokes
5286 // so as to maintain the ordering of pads in the LSDA.
5287 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5288 if (CallSiteIndex) {
5289 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5290 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5292 // Now that the call site is handled, stop tracking it.
5293 MMI.setCurrentCallSite(0);
5296 // Both PendingLoads and PendingExports must be flushed here;
5297 // this call might not return.
5299 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5301 CLI.setChain(getRoot());
5303 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5304 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5306 assert((CLI.IsTailCall || Result.second.getNode()) &&
5307 "Non-null chain expected with non-tail call!");
5308 assert((Result.second.getNode() || !Result.first.getNode()) &&
5309 "Null value expected with tail call!");
5311 if (!Result.second.getNode()) {
5312 // As a special case, a null chain means that a tail call has been emitted
5313 // and the DAG root is already updated.
5316 // Since there's no actual continuation from this block, nothing can be
5317 // relying on us setting vregs for them.
5318 PendingExports.clear();
5320 DAG.setRoot(Result.second);
5324 // Insert a label at the end of the invoke call to mark the try range. This
5325 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5326 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5327 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5329 // Inform MachineModuleInfo of range.
5330 if (MMI.hasEHFunclets()) {
5331 WinEHFuncInfo &EHInfo =
5332 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
5333 EHInfo.addIPToStateRange(EHPadBB, BeginLabel, EndLabel);
5335 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5342 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5344 const BasicBlock *EHPadBB) {
5345 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5346 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5347 Type *RetTy = FTy->getReturnType();
5349 TargetLowering::ArgListTy Args;
5350 TargetLowering::ArgListEntry Entry;
5351 Args.reserve(CS.arg_size());
5353 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5355 const Value *V = *i;
5358 if (V->getType()->isEmptyTy())
5361 SDValue ArgNode = getValue(V);
5362 Entry.Node = ArgNode; Entry.Ty = V->getType();
5364 // Skip the first return-type Attribute to get to params.
5365 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5366 Args.push_back(Entry);
5368 // If we have an explicit sret argument that is an Instruction, (i.e., it
5369 // might point to function-local memory), we can't meaningfully tail-call.
5370 if (Entry.isSRet && isa<Instruction>(V))
5374 // Check if target-independent constraints permit a tail call here.
5375 // Target-dependent constraints are checked within TLI->LowerCallTo.
5376 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5379 TargetLowering::CallLoweringInfo CLI(DAG);
5380 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5381 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5382 .setTailCall(isTailCall);
5383 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5385 if (Result.first.getNode())
5386 setValue(CS.getInstruction(), Result.first);
5389 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5390 /// value is equal or not-equal to zero.
5391 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5392 for (const User *U : V->users()) {
5393 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5394 if (IC->isEquality())
5395 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5396 if (C->isNullValue())
5398 // Unknown instruction.
5404 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5406 SelectionDAGBuilder &Builder) {
5408 // Check to see if this load can be trivially constant folded, e.g. if the
5409 // input is from a string literal.
5410 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5411 // Cast pointer to the type we really want to load.
5412 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5413 PointerType::getUnqual(LoadTy));
5415 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5416 const_cast<Constant *>(LoadInput), *Builder.DL))
5417 return Builder.getValue(LoadCst);
5420 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5421 // still constant memory, the input chain can be the entry node.
5423 bool ConstantMemory = false;
5425 // Do not serialize (non-volatile) loads of constant memory with anything.
5426 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5427 Root = Builder.DAG.getEntryNode();
5428 ConstantMemory = true;
5430 // Do not serialize non-volatile loads against each other.
5431 Root = Builder.DAG.getRoot();
5434 SDValue Ptr = Builder.getValue(PtrVal);
5435 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5436 Ptr, MachinePointerInfo(PtrVal),
5438 false /*nontemporal*/,
5439 false /*isinvariant*/, 1 /* align=1 */);
5441 if (!ConstantMemory)
5442 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5446 /// processIntegerCallValue - Record the value for an instruction that
5447 /// produces an integer result, converting the type where necessary.
5448 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5451 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5454 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5456 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5457 setValue(&I, Value);
5460 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5461 /// If so, return true and lower it, otherwise return false and it will be
5462 /// lowered like a normal call.
5463 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5464 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5465 if (I.getNumArgOperands() != 3)
5468 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5469 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5470 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5471 !I.getType()->isIntegerTy())
5474 const Value *Size = I.getArgOperand(2);
5475 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5476 if (CSize && CSize->getZExtValue() == 0) {
5477 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5479 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5483 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5484 std::pair<SDValue, SDValue> Res =
5485 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5486 getValue(LHS), getValue(RHS), getValue(Size),
5487 MachinePointerInfo(LHS),
5488 MachinePointerInfo(RHS));
5489 if (Res.first.getNode()) {
5490 processIntegerCallValue(I, Res.first, true);
5491 PendingLoads.push_back(Res.second);
5495 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5496 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5497 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5498 bool ActuallyDoIt = true;
5501 switch (CSize->getZExtValue()) {
5503 LoadVT = MVT::Other;
5505 ActuallyDoIt = false;
5509 LoadTy = Type::getInt16Ty(CSize->getContext());
5513 LoadTy = Type::getInt32Ty(CSize->getContext());
5517 LoadTy = Type::getInt64Ty(CSize->getContext());
5521 LoadVT = MVT::v4i32;
5522 LoadTy = Type::getInt32Ty(CSize->getContext());
5523 LoadTy = VectorType::get(LoadTy, 4);
5528 // This turns into unaligned loads. We only do this if the target natively
5529 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5530 // we'll only produce a small number of byte loads.
5532 // Require that we can find a legal MVT, and only do this if the target
5533 // supports unaligned loads of that type. Expanding into byte loads would
5535 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5536 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5537 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5538 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5539 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5540 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5541 // TODO: Check alignment of src and dest ptrs.
5542 if (!TLI.isTypeLegal(LoadVT) ||
5543 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5544 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5545 ActuallyDoIt = false;
5549 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5550 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5552 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5554 processIntegerCallValue(I, Res, false);
5563 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5564 /// form. If so, return true and lower it, otherwise return false and it
5565 /// will be lowered like a normal call.
5566 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5567 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5568 if (I.getNumArgOperands() != 3)
5571 const Value *Src = I.getArgOperand(0);
5572 const Value *Char = I.getArgOperand(1);
5573 const Value *Length = I.getArgOperand(2);
5574 if (!Src->getType()->isPointerTy() ||
5575 !Char->getType()->isIntegerTy() ||
5576 !Length->getType()->isIntegerTy() ||
5577 !I.getType()->isPointerTy())
5580 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5581 std::pair<SDValue, SDValue> Res =
5582 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5583 getValue(Src), getValue(Char), getValue(Length),
5584 MachinePointerInfo(Src));
5585 if (Res.first.getNode()) {
5586 setValue(&I, Res.first);
5587 PendingLoads.push_back(Res.second);
5594 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5595 /// optimized form. If so, return true and lower it, otherwise return false
5596 /// and it will be lowered like a normal call.
5597 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5598 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5599 if (I.getNumArgOperands() != 2)
5602 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5603 if (!Arg0->getType()->isPointerTy() ||
5604 !Arg1->getType()->isPointerTy() ||
5605 !I.getType()->isPointerTy())
5608 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5609 std::pair<SDValue, SDValue> Res =
5610 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5611 getValue(Arg0), getValue(Arg1),
5612 MachinePointerInfo(Arg0),
5613 MachinePointerInfo(Arg1), isStpcpy);
5614 if (Res.first.getNode()) {
5615 setValue(&I, Res.first);
5616 DAG.setRoot(Res.second);
5623 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5624 /// If so, return true and lower it, otherwise return false and it will be
5625 /// lowered like a normal call.
5626 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5627 // Verify that the prototype makes sense. int strcmp(void*,void*)
5628 if (I.getNumArgOperands() != 2)
5631 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5632 if (!Arg0->getType()->isPointerTy() ||
5633 !Arg1->getType()->isPointerTy() ||
5634 !I.getType()->isIntegerTy())
5637 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5638 std::pair<SDValue, SDValue> Res =
5639 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5640 getValue(Arg0), getValue(Arg1),
5641 MachinePointerInfo(Arg0),
5642 MachinePointerInfo(Arg1));
5643 if (Res.first.getNode()) {
5644 processIntegerCallValue(I, Res.first, true);
5645 PendingLoads.push_back(Res.second);
5652 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5653 /// form. If so, return true and lower it, otherwise return false and it
5654 /// will be lowered like a normal call.
5655 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5656 // Verify that the prototype makes sense. size_t strlen(char *)
5657 if (I.getNumArgOperands() != 1)
5660 const Value *Arg0 = I.getArgOperand(0);
5661 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5664 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5665 std::pair<SDValue, SDValue> Res =
5666 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5667 getValue(Arg0), MachinePointerInfo(Arg0));
5668 if (Res.first.getNode()) {
5669 processIntegerCallValue(I, Res.first, false);
5670 PendingLoads.push_back(Res.second);
5677 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5678 /// form. If so, return true and lower it, otherwise return false and it
5679 /// will be lowered like a normal call.
5680 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5681 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5682 if (I.getNumArgOperands() != 2)
5685 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5686 if (!Arg0->getType()->isPointerTy() ||
5687 !Arg1->getType()->isIntegerTy() ||
5688 !I.getType()->isIntegerTy())
5691 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5692 std::pair<SDValue, SDValue> Res =
5693 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5694 getValue(Arg0), getValue(Arg1),
5695 MachinePointerInfo(Arg0));
5696 if (Res.first.getNode()) {
5697 processIntegerCallValue(I, Res.first, false);
5698 PendingLoads.push_back(Res.second);
5705 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5706 /// operation (as expected), translate it to an SDNode with the specified opcode
5707 /// and return true.
5708 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5710 // Sanity check that it really is a unary floating-point call.
5711 if (I.getNumArgOperands() != 1 ||
5712 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5713 I.getType() != I.getArgOperand(0)->getType() ||
5714 !I.onlyReadsMemory())
5717 SDValue Tmp = getValue(I.getArgOperand(0));
5718 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5722 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5723 /// operation (as expected), translate it to an SDNode with the specified opcode
5724 /// and return true.
5725 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5727 // Sanity check that it really is a binary floating-point call.
5728 if (I.getNumArgOperands() != 2 ||
5729 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5730 I.getType() != I.getArgOperand(0)->getType() ||
5731 I.getType() != I.getArgOperand(1)->getType() ||
5732 !I.onlyReadsMemory())
5735 SDValue Tmp0 = getValue(I.getArgOperand(0));
5736 SDValue Tmp1 = getValue(I.getArgOperand(1));
5737 EVT VT = Tmp0.getValueType();
5738 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5742 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5743 // Handle inline assembly differently.
5744 if (isa<InlineAsm>(I.getCalledValue())) {
5749 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5750 ComputeUsesVAFloatArgument(I, &MMI);
5752 const char *RenameFn = nullptr;
5753 if (Function *F = I.getCalledFunction()) {
5754 if (F->isDeclaration()) {
5755 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5756 if (unsigned IID = II->getIntrinsicID(F)) {
5757 RenameFn = visitIntrinsicCall(I, IID);
5762 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5763 RenameFn = visitIntrinsicCall(I, IID);
5769 // Check for well-known libc/libm calls. If the function is internal, it
5770 // can't be a library call.
5772 if (!F->hasLocalLinkage() && F->hasName() &&
5773 LibInfo->getLibFunc(F->getName(), Func) &&
5774 LibInfo->hasOptimizedCodeGen(Func)) {
5777 case LibFunc::copysign:
5778 case LibFunc::copysignf:
5779 case LibFunc::copysignl:
5780 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5781 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5782 I.getType() == I.getArgOperand(0)->getType() &&
5783 I.getType() == I.getArgOperand(1)->getType() &&
5784 I.onlyReadsMemory()) {
5785 SDValue LHS = getValue(I.getArgOperand(0));
5786 SDValue RHS = getValue(I.getArgOperand(1));
5787 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5788 LHS.getValueType(), LHS, RHS));
5793 case LibFunc::fabsf:
5794 case LibFunc::fabsl:
5795 if (visitUnaryFloatCall(I, ISD::FABS))
5799 case LibFunc::fminf:
5800 case LibFunc::fminl:
5801 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5805 case LibFunc::fmaxf:
5806 case LibFunc::fmaxl:
5807 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5813 if (visitUnaryFloatCall(I, ISD::FSIN))
5819 if (visitUnaryFloatCall(I, ISD::FCOS))
5823 case LibFunc::sqrtf:
5824 case LibFunc::sqrtl:
5825 case LibFunc::sqrt_finite:
5826 case LibFunc::sqrtf_finite:
5827 case LibFunc::sqrtl_finite:
5828 if (visitUnaryFloatCall(I, ISD::FSQRT))
5831 case LibFunc::floor:
5832 case LibFunc::floorf:
5833 case LibFunc::floorl:
5834 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5837 case LibFunc::nearbyint:
5838 case LibFunc::nearbyintf:
5839 case LibFunc::nearbyintl:
5840 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5844 case LibFunc::ceilf:
5845 case LibFunc::ceill:
5846 if (visitUnaryFloatCall(I, ISD::FCEIL))
5850 case LibFunc::rintf:
5851 case LibFunc::rintl:
5852 if (visitUnaryFloatCall(I, ISD::FRINT))
5855 case LibFunc::round:
5856 case LibFunc::roundf:
5857 case LibFunc::roundl:
5858 if (visitUnaryFloatCall(I, ISD::FROUND))
5861 case LibFunc::trunc:
5862 case LibFunc::truncf:
5863 case LibFunc::truncl:
5864 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5868 case LibFunc::log2f:
5869 case LibFunc::log2l:
5870 if (visitUnaryFloatCall(I, ISD::FLOG2))
5874 case LibFunc::exp2f:
5875 case LibFunc::exp2l:
5876 if (visitUnaryFloatCall(I, ISD::FEXP2))
5879 case LibFunc::memcmp:
5880 if (visitMemCmpCall(I))
5883 case LibFunc::memchr:
5884 if (visitMemChrCall(I))
5887 case LibFunc::strcpy:
5888 if (visitStrCpyCall(I, false))
5891 case LibFunc::stpcpy:
5892 if (visitStrCpyCall(I, true))
5895 case LibFunc::strcmp:
5896 if (visitStrCmpCall(I))
5899 case LibFunc::strlen:
5900 if (visitStrLenCall(I))
5903 case LibFunc::strnlen:
5904 if (visitStrNLenCall(I))
5913 Callee = getValue(I.getCalledValue());
5915 Callee = DAG.getExternalSymbol(
5917 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5919 // Check if we can potentially perform a tail call. More detailed checking is
5920 // be done within LowerCallTo, after more information about the call is known.
5921 LowerCallTo(&I, Callee, I.isTailCall());
5926 /// AsmOperandInfo - This contains information for each constraint that we are
5928 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5930 /// CallOperand - If this is the result output operand or a clobber
5931 /// this is null, otherwise it is the incoming operand to the CallInst.
5932 /// This gets modified as the asm is processed.
5933 SDValue CallOperand;
5935 /// AssignedRegs - If this is a register or register class operand, this
5936 /// contains the set of register corresponding to the operand.
5937 RegsForValue AssignedRegs;
5939 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5940 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5943 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5944 /// corresponds to. If there is no Value* for this operand, it returns
5946 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5947 const DataLayout &DL) const {
5948 if (!CallOperandVal) return MVT::Other;
5950 if (isa<BasicBlock>(CallOperandVal))
5951 return TLI.getPointerTy(DL);
5953 llvm::Type *OpTy = CallOperandVal->getType();
5955 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5956 // If this is an indirect operand, the operand is a pointer to the
5959 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5961 report_fatal_error("Indirect operand for inline asm not a pointer!");
5962 OpTy = PtrTy->getElementType();
5965 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5966 if (StructType *STy = dyn_cast<StructType>(OpTy))
5967 if (STy->getNumElements() == 1)
5968 OpTy = STy->getElementType(0);
5970 // If OpTy is not a single value, it may be a struct/union that we
5971 // can tile with integers.
5972 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5973 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5982 OpTy = IntegerType::get(Context, BitSize);
5987 return TLI.getValueType(DL, OpTy, true);
5991 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5993 } // end anonymous namespace
5995 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5996 /// specified operand. We prefer to assign virtual registers, to allow the
5997 /// register allocator to handle the assignment process. However, if the asm
5998 /// uses features that we can't model on machineinstrs, we have SDISel do the
5999 /// allocation. This produces generally horrible, but correct, code.
6001 /// OpInfo describes the operand.
6003 static void GetRegistersForValue(SelectionDAG &DAG,
6004 const TargetLowering &TLI,
6006 SDISelAsmOperandInfo &OpInfo) {
6007 LLVMContext &Context = *DAG.getContext();
6009 MachineFunction &MF = DAG.getMachineFunction();
6010 SmallVector<unsigned, 4> Regs;
6012 // If this is a constraint for a single physreg, or a constraint for a
6013 // register class, find it.
6014 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6015 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6016 OpInfo.ConstraintCode,
6017 OpInfo.ConstraintVT);
6019 unsigned NumRegs = 1;
6020 if (OpInfo.ConstraintVT != MVT::Other) {
6021 // If this is a FP input in an integer register (or visa versa) insert a bit
6022 // cast of the input value. More generally, handle any case where the input
6023 // value disagrees with the register class we plan to stick this in.
6024 if (OpInfo.Type == InlineAsm::isInput &&
6025 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6026 // Try to convert to the first EVT that the reg class contains. If the
6027 // types are identical size, use a bitcast to convert (e.g. two differing
6029 MVT RegVT = *PhysReg.second->vt_begin();
6030 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6031 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6032 RegVT, OpInfo.CallOperand);
6033 OpInfo.ConstraintVT = RegVT;
6034 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6035 // If the input is a FP value and we want it in FP registers, do a
6036 // bitcast to the corresponding integer type. This turns an f64 value
6037 // into i64, which can be passed with two i32 values on a 32-bit
6039 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6040 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6041 RegVT, OpInfo.CallOperand);
6042 OpInfo.ConstraintVT = RegVT;
6046 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6050 EVT ValueVT = OpInfo.ConstraintVT;
6052 // If this is a constraint for a specific physical register, like {r17},
6054 if (unsigned AssignedReg = PhysReg.first) {
6055 const TargetRegisterClass *RC = PhysReg.second;
6056 if (OpInfo.ConstraintVT == MVT::Other)
6057 ValueVT = *RC->vt_begin();
6059 // Get the actual register value type. This is important, because the user
6060 // may have asked for (e.g.) the AX register in i32 type. We need to
6061 // remember that AX is actually i16 to get the right extension.
6062 RegVT = *RC->vt_begin();
6064 // This is a explicit reference to a physical register.
6065 Regs.push_back(AssignedReg);
6067 // If this is an expanded reference, add the rest of the regs to Regs.
6069 TargetRegisterClass::iterator I = RC->begin();
6070 for (; *I != AssignedReg; ++I)
6071 assert(I != RC->end() && "Didn't find reg!");
6073 // Already added the first reg.
6075 for (; NumRegs; --NumRegs, ++I) {
6076 assert(I != RC->end() && "Ran out of registers to allocate!");
6081 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6085 // Otherwise, if this was a reference to an LLVM register class, create vregs
6086 // for this reference.
6087 if (const TargetRegisterClass *RC = PhysReg.second) {
6088 RegVT = *RC->vt_begin();
6089 if (OpInfo.ConstraintVT == MVT::Other)
6092 // Create the appropriate number of virtual registers.
6093 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6094 for (; NumRegs; --NumRegs)
6095 Regs.push_back(RegInfo.createVirtualRegister(RC));
6097 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6101 // Otherwise, we couldn't allocate enough registers for this.
6104 /// visitInlineAsm - Handle a call to an InlineAsm object.
6106 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6107 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6109 /// ConstraintOperands - Information about all of the constraints.
6110 SDISelAsmOperandInfoVector ConstraintOperands;
6112 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6113 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6114 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6116 bool hasMemory = false;
6118 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6119 unsigned ResNo = 0; // ResNo - The result number of the next output.
6120 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6121 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6122 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6124 MVT OpVT = MVT::Other;
6126 // Compute the value type for each operand.
6127 switch (OpInfo.Type) {
6128 case InlineAsm::isOutput:
6129 // Indirect outputs just consume an argument.
6130 if (OpInfo.isIndirect) {
6131 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6135 // The return value of the call is this value. As such, there is no
6136 // corresponding argument.
6137 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6138 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6139 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6140 STy->getElementType(ResNo));
6142 assert(ResNo == 0 && "Asm only has one result!");
6143 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6147 case InlineAsm::isInput:
6148 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6150 case InlineAsm::isClobber:
6155 // If this is an input or an indirect output, process the call argument.
6156 // BasicBlocks are labels, currently appearing only in asm's.
6157 if (OpInfo.CallOperandVal) {
6158 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6159 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6161 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6164 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6165 DAG.getDataLayout()).getSimpleVT();
6168 OpInfo.ConstraintVT = OpVT;
6170 // Indirect operand accesses access memory.
6171 if (OpInfo.isIndirect)
6174 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6175 TargetLowering::ConstraintType
6176 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6177 if (CType == TargetLowering::C_Memory) {
6185 SDValue Chain, Flag;
6187 // We won't need to flush pending loads if this asm doesn't touch
6188 // memory and is nonvolatile.
6189 if (hasMemory || IA->hasSideEffects())
6192 Chain = DAG.getRoot();
6194 // Second pass over the constraints: compute which constraint option to use
6195 // and assign registers to constraints that want a specific physreg.
6196 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6197 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6199 // If this is an output operand with a matching input operand, look up the
6200 // matching input. If their types mismatch, e.g. one is an integer, the
6201 // other is floating point, or their sizes are different, flag it as an
6203 if (OpInfo.hasMatchingInput()) {
6204 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6206 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6207 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6208 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6209 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6210 OpInfo.ConstraintVT);
6211 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6212 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6213 Input.ConstraintVT);
6214 if ((OpInfo.ConstraintVT.isInteger() !=
6215 Input.ConstraintVT.isInteger()) ||
6216 (MatchRC.second != InputRC.second)) {
6217 report_fatal_error("Unsupported asm: input constraint"
6218 " with a matching output constraint of"
6219 " incompatible type!");
6221 Input.ConstraintVT = OpInfo.ConstraintVT;
6225 // Compute the constraint code and ConstraintType to use.
6226 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6228 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6229 OpInfo.Type == InlineAsm::isClobber)
6232 // If this is a memory input, and if the operand is not indirect, do what we
6233 // need to to provide an address for the memory input.
6234 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6235 !OpInfo.isIndirect) {
6236 assert((OpInfo.isMultipleAlternative ||
6237 (OpInfo.Type == InlineAsm::isInput)) &&
6238 "Can only indirectify direct input operands!");
6240 // Memory operands really want the address of the value. If we don't have
6241 // an indirect input, put it in the constpool if we can, otherwise spill
6242 // it to a stack slot.
6243 // TODO: This isn't quite right. We need to handle these according to
6244 // the addressing mode that the constraint wants. Also, this may take
6245 // an additional register for the computation and we don't want that
6248 // If the operand is a float, integer, or vector constant, spill to a
6249 // constant pool entry to get its address.
6250 const Value *OpVal = OpInfo.CallOperandVal;
6251 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6252 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6253 OpInfo.CallOperand = DAG.getConstantPool(
6254 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6256 // Otherwise, create a stack slot and emit a store to it before the
6258 Type *Ty = OpVal->getType();
6259 auto &DL = DAG.getDataLayout();
6260 uint64_t TySize = DL.getTypeAllocSize(Ty);
6261 unsigned Align = DL.getPrefTypeAlignment(Ty);
6262 MachineFunction &MF = DAG.getMachineFunction();
6263 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6265 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6266 Chain = DAG.getStore(
6267 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6268 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6270 OpInfo.CallOperand = StackSlot;
6273 // There is no longer a Value* corresponding to this operand.
6274 OpInfo.CallOperandVal = nullptr;
6276 // It is now an indirect operand.
6277 OpInfo.isIndirect = true;
6280 // If this constraint is for a specific register, allocate it before
6282 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6283 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6286 // Second pass - Loop over all of the operands, assigning virtual or physregs
6287 // to register class operands.
6288 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6289 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6291 // C_Register operands have already been allocated, Other/Memory don't need
6293 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6294 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6297 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6298 std::vector<SDValue> AsmNodeOperands;
6299 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6300 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6301 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6303 // If we have a !srcloc metadata node associated with it, we want to attach
6304 // this to the ultimately generated inline asm machineinstr. To do this, we
6305 // pass in the third operand as this (potentially null) inline asm MDNode.
6306 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6307 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6309 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6310 // bits as operand 3.
6311 unsigned ExtraInfo = 0;
6312 if (IA->hasSideEffects())
6313 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6314 if (IA->isAlignStack())
6315 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6316 // Set the asm dialect.
6317 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6319 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6320 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6321 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6323 // Compute the constraint code and ConstraintType to use.
6324 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6326 // Ideally, we would only check against memory constraints. However, the
6327 // meaning of an other constraint can be target-specific and we can't easily
6328 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6329 // for other constriants as well.
6330 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6331 OpInfo.ConstraintType == TargetLowering::C_Other) {
6332 if (OpInfo.Type == InlineAsm::isInput)
6333 ExtraInfo |= InlineAsm::Extra_MayLoad;
6334 else if (OpInfo.Type == InlineAsm::isOutput)
6335 ExtraInfo |= InlineAsm::Extra_MayStore;
6336 else if (OpInfo.Type == InlineAsm::isClobber)
6337 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6341 AsmNodeOperands.push_back(DAG.getTargetConstant(
6342 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6344 // Loop over all of the inputs, copying the operand values into the
6345 // appropriate registers and processing the output regs.
6346 RegsForValue RetValRegs;
6348 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6349 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6351 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6352 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6354 switch (OpInfo.Type) {
6355 case InlineAsm::isOutput: {
6356 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6357 OpInfo.ConstraintType != TargetLowering::C_Register) {
6358 // Memory output, or 'other' output (e.g. 'X' constraint).
6359 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6361 unsigned ConstraintID =
6362 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6363 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6364 "Failed to convert memory constraint code to constraint id.");
6366 // Add information to the INLINEASM node to know about this output.
6367 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6368 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6369 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6371 AsmNodeOperands.push_back(OpInfo.CallOperand);
6375 // Otherwise, this is a register or register class output.
6377 // Copy the output from the appropriate register. Find a register that
6379 if (OpInfo.AssignedRegs.Regs.empty()) {
6380 LLVMContext &Ctx = *DAG.getContext();
6381 Ctx.emitError(CS.getInstruction(),
6382 "couldn't allocate output register for constraint '" +
6383 Twine(OpInfo.ConstraintCode) + "'");
6387 // If this is an indirect operand, store through the pointer after the
6389 if (OpInfo.isIndirect) {
6390 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6391 OpInfo.CallOperandVal));
6393 // This is the result value of the call.
6394 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6395 // Concatenate this output onto the outputs list.
6396 RetValRegs.append(OpInfo.AssignedRegs);
6399 // Add information to the INLINEASM node to know that this register is
6402 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6403 ? InlineAsm::Kind_RegDefEarlyClobber
6404 : InlineAsm::Kind_RegDef,
6405 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6408 case InlineAsm::isInput: {
6409 SDValue InOperandVal = OpInfo.CallOperand;
6411 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6412 // If this is required to match an output register we have already set,
6413 // just use its register.
6414 unsigned OperandNo = OpInfo.getMatchedOperand();
6416 // Scan until we find the definition we already emitted of this operand.
6417 // When we find it, create a RegsForValue operand.
6418 unsigned CurOp = InlineAsm::Op_FirstOperand;
6419 for (; OperandNo; --OperandNo) {
6420 // Advance to the next operand.
6422 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6423 assert((InlineAsm::isRegDefKind(OpFlag) ||
6424 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6425 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6426 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6430 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6431 if (InlineAsm::isRegDefKind(OpFlag) ||
6432 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6433 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6434 if (OpInfo.isIndirect) {
6435 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6436 LLVMContext &Ctx = *DAG.getContext();
6437 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6438 " don't know how to handle tied "
6439 "indirect register inputs");
6443 RegsForValue MatchedRegs;
6444 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6445 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6446 MatchedRegs.RegVTs.push_back(RegVT);
6447 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6448 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6450 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6451 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6453 LLVMContext &Ctx = *DAG.getContext();
6454 Ctx.emitError(CS.getInstruction(),
6455 "inline asm error: This value"
6456 " type register class is not natively supported!");
6460 SDLoc dl = getCurSDLoc();
6461 // Use the produced MatchedRegs object to
6462 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6463 Chain, &Flag, CS.getInstruction());
6464 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6465 true, OpInfo.getMatchedOperand(), dl,
6466 DAG, AsmNodeOperands);
6470 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6471 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6472 "Unexpected number of operands");
6473 // Add information to the INLINEASM node to know about this input.
6474 // See InlineAsm.h isUseOperandTiedToDef.
6475 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6476 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6477 OpInfo.getMatchedOperand());
6478 AsmNodeOperands.push_back(DAG.getTargetConstant(
6479 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6480 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6484 // Treat indirect 'X' constraint as memory.
6485 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6487 OpInfo.ConstraintType = TargetLowering::C_Memory;
6489 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6490 std::vector<SDValue> Ops;
6491 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6494 LLVMContext &Ctx = *DAG.getContext();
6495 Ctx.emitError(CS.getInstruction(),
6496 "invalid operand for inline asm constraint '" +
6497 Twine(OpInfo.ConstraintCode) + "'");
6501 // Add information to the INLINEASM node to know about this input.
6502 unsigned ResOpType =
6503 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6504 AsmNodeOperands.push_back(DAG.getTargetConstant(
6505 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6506 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6510 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6511 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6512 assert(InOperandVal.getValueType() ==
6513 TLI.getPointerTy(DAG.getDataLayout()) &&
6514 "Memory operands expect pointer values");
6516 unsigned ConstraintID =
6517 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6518 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6519 "Failed to convert memory constraint code to constraint id.");
6521 // Add information to the INLINEASM node to know about this input.
6522 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6523 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6524 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6527 AsmNodeOperands.push_back(InOperandVal);
6531 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6532 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6533 "Unknown constraint type!");
6535 // TODO: Support this.
6536 if (OpInfo.isIndirect) {
6537 LLVMContext &Ctx = *DAG.getContext();
6538 Ctx.emitError(CS.getInstruction(),
6539 "Don't know how to handle indirect register inputs yet "
6540 "for constraint '" +
6541 Twine(OpInfo.ConstraintCode) + "'");
6545 // Copy the input into the appropriate registers.
6546 if (OpInfo.AssignedRegs.Regs.empty()) {
6547 LLVMContext &Ctx = *DAG.getContext();
6548 Ctx.emitError(CS.getInstruction(),
6549 "couldn't allocate input reg for constraint '" +
6550 Twine(OpInfo.ConstraintCode) + "'");
6554 SDLoc dl = getCurSDLoc();
6556 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6557 Chain, &Flag, CS.getInstruction());
6559 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6560 dl, DAG, AsmNodeOperands);
6563 case InlineAsm::isClobber: {
6564 // Add the clobbered value to the operand list, so that the register
6565 // allocator is aware that the physreg got clobbered.
6566 if (!OpInfo.AssignedRegs.Regs.empty())
6567 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6568 false, 0, getCurSDLoc(), DAG,
6575 // Finish up input operands. Set the input chain and add the flag last.
6576 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6577 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6579 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6580 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6581 Flag = Chain.getValue(1);
6583 // If this asm returns a register value, copy the result from that register
6584 // and set it as the value of the call.
6585 if (!RetValRegs.Regs.empty()) {
6586 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6587 Chain, &Flag, CS.getInstruction());
6589 // FIXME: Why don't we do this for inline asms with MRVs?
6590 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6591 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6593 // If any of the results of the inline asm is a vector, it may have the
6594 // wrong width/num elts. This can happen for register classes that can
6595 // contain multiple different value types. The preg or vreg allocated may
6596 // not have the same VT as was expected. Convert it to the right type
6597 // with bit_convert.
6598 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6599 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6602 } else if (ResultType != Val.getValueType() &&
6603 ResultType.isInteger() && Val.getValueType().isInteger()) {
6604 // If a result value was tied to an input value, the computed result may
6605 // have a wider width than the expected result. Extract the relevant
6607 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6610 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6613 setValue(CS.getInstruction(), Val);
6614 // Don't need to use this as a chain in this case.
6615 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6619 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6621 // Process indirect outputs, first output all of the flagged copies out of
6623 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6624 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6625 const Value *Ptr = IndirectStoresToEmit[i].second;
6626 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6628 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6631 // Emit the non-flagged stores from the physregs.
6632 SmallVector<SDValue, 8> OutChains;
6633 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6634 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6635 StoresToEmit[i].first,
6636 getValue(StoresToEmit[i].second),
6637 MachinePointerInfo(StoresToEmit[i].second),
6639 OutChains.push_back(Val);
6642 if (!OutChains.empty())
6643 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6648 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6649 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6650 MVT::Other, getRoot(),
6651 getValue(I.getArgOperand(0)),
6652 DAG.getSrcValue(I.getArgOperand(0))));
6655 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6656 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6657 const DataLayout &DL = DAG.getDataLayout();
6658 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6659 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6660 DAG.getSrcValue(I.getOperand(0)),
6661 DL.getABITypeAlignment(I.getType()));
6663 DAG.setRoot(V.getValue(1));
6666 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6667 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6668 MVT::Other, getRoot(),
6669 getValue(I.getArgOperand(0)),
6670 DAG.getSrcValue(I.getArgOperand(0))));
6673 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6674 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6675 MVT::Other, getRoot(),
6676 getValue(I.getArgOperand(0)),
6677 getValue(I.getArgOperand(1)),
6678 DAG.getSrcValue(I.getArgOperand(0)),
6679 DAG.getSrcValue(I.getArgOperand(1))));
6682 /// \brief Lower an argument list according to the target calling convention.
6684 /// \return A tuple of <return-value, token-chain>
6686 /// This is a helper for lowering intrinsics that follow a target calling
6687 /// convention or require stack pointer adjustment. Only a subset of the
6688 /// intrinsic's operands need to participate in the calling convention.
6689 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6690 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6691 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6692 TargetLowering::ArgListTy Args;
6693 Args.reserve(NumArgs);
6695 // Populate the argument list.
6696 // Attributes for args start at offset 1, after the return attribute.
6697 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6698 ArgI != ArgE; ++ArgI) {
6699 const Value *V = CS->getOperand(ArgI);
6701 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6703 TargetLowering::ArgListEntry Entry;
6704 Entry.Node = getValue(V);
6705 Entry.Ty = V->getType();
6706 Entry.setAttributes(&CS, AttrI);
6707 Args.push_back(Entry);
6710 TargetLowering::CallLoweringInfo CLI(DAG);
6711 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6712 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6713 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6715 return lowerInvokable(CLI, EHPadBB);
6718 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6719 /// or patchpoint target node's operand list.
6721 /// Constants are converted to TargetConstants purely as an optimization to
6722 /// avoid constant materialization and register allocation.
6724 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6725 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6726 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6727 /// address materialization and register allocation, but may also be required
6728 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6729 /// alloca in the entry block, then the runtime may assume that the alloca's
6730 /// StackMap location can be read immediately after compilation and that the
6731 /// location is valid at any point during execution (this is similar to the
6732 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6733 /// only available in a register, then the runtime would need to trap when
6734 /// execution reaches the StackMap in order to read the alloca's location.
6735 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6736 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6737 SelectionDAGBuilder &Builder) {
6738 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6739 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6740 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6742 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6744 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6745 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6746 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6747 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6748 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6750 Ops.push_back(OpVal);
6754 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6755 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6756 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6757 // [live variables...])
6759 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6761 SDValue Chain, InFlag, Callee, NullPtr;
6762 SmallVector<SDValue, 32> Ops;
6764 SDLoc DL = getCurSDLoc();
6765 Callee = getValue(CI.getCalledValue());
6766 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6768 // The stackmap intrinsic only records the live variables (the arguemnts
6769 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6770 // intrinsic, this won't be lowered to a function call. This means we don't
6771 // have to worry about calling conventions and target specific lowering code.
6772 // Instead we perform the call lowering right here.
6774 // chain, flag = CALLSEQ_START(chain, 0)
6775 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6776 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6778 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6779 InFlag = Chain.getValue(1);
6781 // Add the <id> and <numBytes> constants.
6782 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6783 Ops.push_back(DAG.getTargetConstant(
6784 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6785 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6786 Ops.push_back(DAG.getTargetConstant(
6787 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6790 // Push live variables for the stack map.
6791 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6793 // We are not pushing any register mask info here on the operands list,
6794 // because the stackmap doesn't clobber anything.
6796 // Push the chain and the glue flag.
6797 Ops.push_back(Chain);
6798 Ops.push_back(InFlag);
6800 // Create the STACKMAP node.
6801 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6802 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6803 Chain = SDValue(SM, 0);
6804 InFlag = Chain.getValue(1);
6806 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6808 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6810 // Set the root to the target-lowered call chain.
6813 // Inform the Frame Information that we have a stackmap in this function.
6814 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6817 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6818 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6819 const BasicBlock *EHPadBB) {
6820 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6825 // [live variables...])
6827 CallingConv::ID CC = CS.getCallingConv();
6828 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6829 bool HasDef = !CS->getType()->isVoidTy();
6830 SDLoc dl = getCurSDLoc();
6831 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6833 // Handle immediate and symbolic callees.
6834 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6835 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6837 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6838 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6839 SDLoc(SymbolicCallee),
6840 SymbolicCallee->getValueType(0));
6842 // Get the real number of arguments participating in the call <numArgs>
6843 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6844 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6846 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6847 // Intrinsics include all meta-operands up to but not including CC.
6848 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6849 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6850 "Not enough arguments provided to the patchpoint intrinsic");
6852 // For AnyRegCC the arguments are lowered later on manually.
6853 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6855 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6856 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6857 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6859 SDNode *CallEnd = Result.second.getNode();
6860 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6861 CallEnd = CallEnd->getOperand(0).getNode();
6863 /// Get a call instruction from the call sequence chain.
6864 /// Tail calls are not allowed.
6865 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6866 "Expected a callseq node.");
6867 SDNode *Call = CallEnd->getOperand(0).getNode();
6868 bool HasGlue = Call->getGluedNode();
6870 // Replace the target specific call node with the patchable intrinsic.
6871 SmallVector<SDValue, 8> Ops;
6873 // Add the <id> and <numBytes> constants.
6874 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6875 Ops.push_back(DAG.getTargetConstant(
6876 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6877 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6878 Ops.push_back(DAG.getTargetConstant(
6879 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6883 Ops.push_back(Callee);
6885 // Adjust <numArgs> to account for any arguments that have been passed on the
6887 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6888 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6889 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6890 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6892 // Add the calling convention
6893 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6895 // Add the arguments we omitted previously. The register allocator should
6896 // place these in any free register.
6898 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6899 Ops.push_back(getValue(CS.getArgument(i)));
6901 // Push the arguments from the call instruction up to the register mask.
6902 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6903 Ops.append(Call->op_begin() + 2, e);
6905 // Push live variables for the stack map.
6906 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6908 // Push the register mask info.
6910 Ops.push_back(*(Call->op_end()-2));
6912 Ops.push_back(*(Call->op_end()-1));
6914 // Push the chain (this is originally the first operand of the call, but
6915 // becomes now the last or second to last operand).
6916 Ops.push_back(*(Call->op_begin()));
6918 // Push the glue flag (last operand).
6920 Ops.push_back(*(Call->op_end()-1));
6923 if (IsAnyRegCC && HasDef) {
6924 // Create the return types based on the intrinsic definition
6925 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6926 SmallVector<EVT, 3> ValueVTs;
6927 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6928 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6930 // There is always a chain and a glue type at the end
6931 ValueVTs.push_back(MVT::Other);
6932 ValueVTs.push_back(MVT::Glue);
6933 NodeTys = DAG.getVTList(ValueVTs);
6935 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6937 // Replace the target specific call node with a PATCHPOINT node.
6938 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6941 // Update the NodeMap.
6944 setValue(CS.getInstruction(), SDValue(MN, 0));
6946 setValue(CS.getInstruction(), Result.first);
6949 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6950 // call sequence. Furthermore the location of the chain and glue can change
6951 // when the AnyReg calling convention is used and the intrinsic returns a
6953 if (IsAnyRegCC && HasDef) {
6954 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6955 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6956 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6958 DAG.ReplaceAllUsesWith(Call, MN);
6959 DAG.DeleteNode(Call);
6961 // Inform the Frame Information that we have a patchpoint in this function.
6962 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6965 /// Returns an AttributeSet representing the attributes applied to the return
6966 /// value of the given call.
6967 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6968 SmallVector<Attribute::AttrKind, 2> Attrs;
6970 Attrs.push_back(Attribute::SExt);
6972 Attrs.push_back(Attribute::ZExt);
6974 Attrs.push_back(Attribute::InReg);
6976 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6980 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6981 /// implementation, which just calls LowerCall.
6982 /// FIXME: When all targets are
6983 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6984 std::pair<SDValue, SDValue>
6985 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6986 // Handle the incoming return values from the call.
6988 Type *OrigRetTy = CLI.RetTy;
6989 SmallVector<EVT, 4> RetTys;
6990 SmallVector<uint64_t, 4> Offsets;
6991 auto &DL = CLI.DAG.getDataLayout();
6992 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6994 SmallVector<ISD::OutputArg, 4> Outs;
6995 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6997 bool CanLowerReturn =
6998 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6999 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7001 SDValue DemoteStackSlot;
7002 int DemoteStackIdx = -100;
7003 if (!CanLowerReturn) {
7004 // FIXME: equivalent assert?
7005 // assert(!CS.hasInAllocaArgument() &&
7006 // "sret demotion is incompatible with inalloca");
7007 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
7008 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
7009 MachineFunction &MF = CLI.DAG.getMachineFunction();
7010 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7011 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7013 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7015 Entry.Node = DemoteStackSlot;
7016 Entry.Ty = StackSlotPtrType;
7017 Entry.isSExt = false;
7018 Entry.isZExt = false;
7019 Entry.isInReg = false;
7020 Entry.isSRet = true;
7021 Entry.isNest = false;
7022 Entry.isByVal = false;
7023 Entry.isReturned = false;
7024 Entry.Alignment = Align;
7025 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7026 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7028 // sret demotion isn't compatible with tail-calls, since the sret argument
7029 // points into the callers stack frame.
7030 CLI.IsTailCall = false;
7032 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7034 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7035 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7036 for (unsigned i = 0; i != NumRegs; ++i) {
7037 ISD::InputArg MyFlags;
7038 MyFlags.VT = RegisterVT;
7040 MyFlags.Used = CLI.IsReturnValueUsed;
7042 MyFlags.Flags.setSExt();
7044 MyFlags.Flags.setZExt();
7046 MyFlags.Flags.setInReg();
7047 CLI.Ins.push_back(MyFlags);
7052 // Handle all of the outgoing arguments.
7054 CLI.OutVals.clear();
7055 ArgListTy &Args = CLI.getArgs();
7056 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7057 SmallVector<EVT, 4> ValueVTs;
7058 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7059 Type *FinalType = Args[i].Ty;
7060 if (Args[i].isByVal)
7061 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7062 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7063 FinalType, CLI.CallConv, CLI.IsVarArg);
7064 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7066 EVT VT = ValueVTs[Value];
7067 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7068 SDValue Op = SDValue(Args[i].Node.getNode(),
7069 Args[i].Node.getResNo() + Value);
7070 ISD::ArgFlagsTy Flags;
7071 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7077 if (Args[i].isInReg)
7081 if (Args[i].isByVal)
7083 if (Args[i].isInAlloca) {
7084 Flags.setInAlloca();
7085 // Set the byval flag for CCAssignFn callbacks that don't know about
7086 // inalloca. This way we can know how many bytes we should've allocated
7087 // and how many bytes a callee cleanup function will pop. If we port
7088 // inalloca to more targets, we'll have to add custom inalloca handling
7089 // in the various CC lowering callbacks.
7092 if (Args[i].isByVal || Args[i].isInAlloca) {
7093 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7094 Type *ElementTy = Ty->getElementType();
7095 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7096 // For ByVal, alignment should come from FE. BE will guess if this
7097 // info is not there but there are cases it cannot get right.
7098 unsigned FrameAlign;
7099 if (Args[i].Alignment)
7100 FrameAlign = Args[i].Alignment;
7102 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7103 Flags.setByValAlign(FrameAlign);
7108 Flags.setInConsecutiveRegs();
7109 Flags.setOrigAlign(OriginalAlignment);
7111 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7112 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7113 SmallVector<SDValue, 4> Parts(NumParts);
7114 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7117 ExtendKind = ISD::SIGN_EXTEND;
7118 else if (Args[i].isZExt)
7119 ExtendKind = ISD::ZERO_EXTEND;
7121 // Conservatively only handle 'returned' on non-vectors for now
7122 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7123 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7124 "unexpected use of 'returned'");
7125 // Before passing 'returned' to the target lowering code, ensure that
7126 // either the register MVT and the actual EVT are the same size or that
7127 // the return value and argument are extended in the same way; in these
7128 // cases it's safe to pass the argument register value unchanged as the
7129 // return register value (although it's at the target's option whether
7131 // TODO: allow code generation to take advantage of partially preserved
7132 // registers rather than clobbering the entire register when the
7133 // parameter extension method is not compatible with the return
7135 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7136 (ExtendKind != ISD::ANY_EXTEND &&
7137 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7138 Flags.setReturned();
7141 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7142 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7144 for (unsigned j = 0; j != NumParts; ++j) {
7145 // if it isn't first piece, alignment must be 1
7146 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7147 i < CLI.NumFixedArgs,
7148 i, j*Parts[j].getValueType().getStoreSize());
7149 if (NumParts > 1 && j == 0)
7150 MyFlags.Flags.setSplit();
7152 MyFlags.Flags.setOrigAlign(1);
7154 CLI.Outs.push_back(MyFlags);
7155 CLI.OutVals.push_back(Parts[j]);
7158 if (NeedsRegBlock && Value == NumValues - 1)
7159 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7163 SmallVector<SDValue, 4> InVals;
7164 CLI.Chain = LowerCall(CLI, InVals);
7166 // Verify that the target's LowerCall behaved as expected.
7167 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7168 "LowerCall didn't return a valid chain!");
7169 assert((!CLI.IsTailCall || InVals.empty()) &&
7170 "LowerCall emitted a return value for a tail call!");
7171 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7172 "LowerCall didn't emit the correct number of values!");
7174 // For a tail call, the return value is merely live-out and there aren't
7175 // any nodes in the DAG representing it. Return a special value to
7176 // indicate that a tail call has been emitted and no more Instructions
7177 // should be processed in the current block.
7178 if (CLI.IsTailCall) {
7179 CLI.DAG.setRoot(CLI.Chain);
7180 return std::make_pair(SDValue(), SDValue());
7183 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7184 assert(InVals[i].getNode() &&
7185 "LowerCall emitted a null value!");
7186 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7187 "LowerCall emitted a value with the wrong type!");
7190 SmallVector<SDValue, 4> ReturnValues;
7191 if (!CanLowerReturn) {
7192 // The instruction result is the result of loading from the
7193 // hidden sret parameter.
7194 SmallVector<EVT, 1> PVTs;
7195 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7197 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7198 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7199 EVT PtrVT = PVTs[0];
7201 unsigned NumValues = RetTys.size();
7202 ReturnValues.resize(NumValues);
7203 SmallVector<SDValue, 4> Chains(NumValues);
7205 for (unsigned i = 0; i < NumValues; ++i) {
7206 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7207 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7209 SDValue L = CLI.DAG.getLoad(
7210 RetTys[i], CLI.DL, CLI.Chain, Add,
7211 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7212 DemoteStackIdx, Offsets[i]),
7213 false, false, false, 1);
7214 ReturnValues[i] = L;
7215 Chains[i] = L.getValue(1);
7218 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7220 // Collect the legal value parts into potentially illegal values
7221 // that correspond to the original function's return values.
7222 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7224 AssertOp = ISD::AssertSext;
7225 else if (CLI.RetZExt)
7226 AssertOp = ISD::AssertZext;
7227 unsigned CurReg = 0;
7228 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7230 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7231 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7233 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7234 NumRegs, RegisterVT, VT, nullptr,
7239 // For a function returning void, there is no return value. We can't create
7240 // such a node, so we just return a null return value in that case. In
7241 // that case, nothing will actually look at the value.
7242 if (ReturnValues.empty())
7243 return std::make_pair(SDValue(), CLI.Chain);
7246 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7247 CLI.DAG.getVTList(RetTys), ReturnValues);
7248 return std::make_pair(Res, CLI.Chain);
7251 void TargetLowering::LowerOperationWrapper(SDNode *N,
7252 SmallVectorImpl<SDValue> &Results,
7253 SelectionDAG &DAG) const {
7254 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7256 Results.push_back(Res);
7259 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7260 llvm_unreachable("LowerOperation not implemented for this target!");
7264 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7265 SDValue Op = getNonRegisterValue(V);
7266 assert((Op.getOpcode() != ISD::CopyFromReg ||
7267 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7268 "Copy from a reg to the same reg!");
7269 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7271 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7272 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7274 SDValue Chain = DAG.getEntryNode();
7276 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7277 FuncInfo.PreferredExtendType.end())
7279 : FuncInfo.PreferredExtendType[V];
7280 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7281 PendingExports.push_back(Chain);
7284 #include "llvm/CodeGen/SelectionDAGISel.h"
7286 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7287 /// entry block, return true. This includes arguments used by switches, since
7288 /// the switch may expand into multiple basic blocks.
7289 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7290 // With FastISel active, we may be splitting blocks, so force creation
7291 // of virtual registers for all non-dead arguments.
7293 return A->use_empty();
7295 const BasicBlock *Entry = A->getParent()->begin();
7296 for (const User *U : A->users())
7297 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7298 return false; // Use not in entry block.
7303 void SelectionDAGISel::LowerArguments(const Function &F) {
7304 SelectionDAG &DAG = SDB->DAG;
7305 SDLoc dl = SDB->getCurSDLoc();
7306 const DataLayout &DL = DAG.getDataLayout();
7307 SmallVector<ISD::InputArg, 16> Ins;
7309 if (!FuncInfo->CanLowerReturn) {
7310 // Put in an sret pointer parameter before all the other parameters.
7311 SmallVector<EVT, 1> ValueVTs;
7312 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7313 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7315 // NOTE: Assuming that a pointer will never break down to more than one VT
7317 ISD::ArgFlagsTy Flags;
7319 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7320 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7321 ISD::InputArg::NoArgIndex, 0);
7322 Ins.push_back(RetArg);
7325 // Set up the incoming argument description vector.
7327 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7328 I != E; ++I, ++Idx) {
7329 SmallVector<EVT, 4> ValueVTs;
7330 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7331 bool isArgValueUsed = !I->use_empty();
7332 unsigned PartBase = 0;
7333 Type *FinalType = I->getType();
7334 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7335 FinalType = cast<PointerType>(FinalType)->getElementType();
7336 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7337 FinalType, F.getCallingConv(), F.isVarArg());
7338 for (unsigned Value = 0, NumValues = ValueVTs.size();
7339 Value != NumValues; ++Value) {
7340 EVT VT = ValueVTs[Value];
7341 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7342 ISD::ArgFlagsTy Flags;
7343 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7345 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7347 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7349 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7351 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7353 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7355 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7356 Flags.setInAlloca();
7357 // Set the byval flag for CCAssignFn callbacks that don't know about
7358 // inalloca. This way we can know how many bytes we should've allocated
7359 // and how many bytes a callee cleanup function will pop. If we port
7360 // inalloca to more targets, we'll have to add custom inalloca handling
7361 // in the various CC lowering callbacks.
7364 if (Flags.isByVal() || Flags.isInAlloca()) {
7365 PointerType *Ty = cast<PointerType>(I->getType());
7366 Type *ElementTy = Ty->getElementType();
7367 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7368 // For ByVal, alignment should be passed from FE. BE will guess if
7369 // this info is not there but there are cases it cannot get right.
7370 unsigned FrameAlign;
7371 if (F.getParamAlignment(Idx))
7372 FrameAlign = F.getParamAlignment(Idx);
7374 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7375 Flags.setByValAlign(FrameAlign);
7377 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7380 Flags.setInConsecutiveRegs();
7381 Flags.setOrigAlign(OriginalAlignment);
7383 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7384 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7385 for (unsigned i = 0; i != NumRegs; ++i) {
7386 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7387 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7388 if (NumRegs > 1 && i == 0)
7389 MyFlags.Flags.setSplit();
7390 // if it isn't first piece, alignment must be 1
7392 MyFlags.Flags.setOrigAlign(1);
7393 Ins.push_back(MyFlags);
7395 if (NeedsRegBlock && Value == NumValues - 1)
7396 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7397 PartBase += VT.getStoreSize();
7401 // Call the target to set up the argument values.
7402 SmallVector<SDValue, 8> InVals;
7403 SDValue NewRoot = TLI->LowerFormalArguments(
7404 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7406 // Verify that the target's LowerFormalArguments behaved as expected.
7407 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7408 "LowerFormalArguments didn't return a valid chain!");
7409 assert(InVals.size() == Ins.size() &&
7410 "LowerFormalArguments didn't emit the correct number of values!");
7412 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7413 assert(InVals[i].getNode() &&
7414 "LowerFormalArguments emitted a null value!");
7415 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7416 "LowerFormalArguments emitted a value with the wrong type!");
7420 // Update the DAG with the new chain value resulting from argument lowering.
7421 DAG.setRoot(NewRoot);
7423 // Set up the argument values.
7426 if (!FuncInfo->CanLowerReturn) {
7427 // Create a virtual register for the sret pointer, and put in a copy
7428 // from the sret argument into it.
7429 SmallVector<EVT, 1> ValueVTs;
7430 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7431 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7432 MVT VT = ValueVTs[0].getSimpleVT();
7433 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7434 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7435 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7436 RegVT, VT, nullptr, AssertOp);
7438 MachineFunction& MF = SDB->DAG.getMachineFunction();
7439 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7440 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7441 FuncInfo->DemoteRegister = SRetReg;
7443 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7444 DAG.setRoot(NewRoot);
7446 // i indexes lowered arguments. Bump it past the hidden sret argument.
7447 // Idx indexes LLVM arguments. Don't touch it.
7451 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7453 SmallVector<SDValue, 4> ArgValues;
7454 SmallVector<EVT, 4> ValueVTs;
7455 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7456 unsigned NumValues = ValueVTs.size();
7458 // If this argument is unused then remember its value. It is used to generate
7459 // debugging information.
7460 if (I->use_empty() && NumValues) {
7461 SDB->setUnusedArgValue(I, InVals[i]);
7463 // Also remember any frame index for use in FastISel.
7464 if (FrameIndexSDNode *FI =
7465 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7466 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7469 for (unsigned Val = 0; Val != NumValues; ++Val) {
7470 EVT VT = ValueVTs[Val];
7471 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7472 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7474 if (!I->use_empty()) {
7475 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7476 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7477 AssertOp = ISD::AssertSext;
7478 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7479 AssertOp = ISD::AssertZext;
7481 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7482 NumParts, PartVT, VT,
7483 nullptr, AssertOp));
7489 // We don't need to do anything else for unused arguments.
7490 if (ArgValues.empty())
7493 // Note down frame index.
7494 if (FrameIndexSDNode *FI =
7495 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7496 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7498 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7499 SDB->getCurSDLoc());
7501 SDB->setValue(I, Res);
7502 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7503 if (LoadSDNode *LNode =
7504 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7505 if (FrameIndexSDNode *FI =
7506 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7507 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7510 // If this argument is live outside of the entry block, insert a copy from
7511 // wherever we got it to the vreg that other BB's will reference it as.
7512 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7513 // If we can, though, try to skip creating an unnecessary vreg.
7514 // FIXME: This isn't very clean... it would be nice to make this more
7515 // general. It's also subtly incompatible with the hacks FastISel
7517 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7518 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7519 FuncInfo->ValueMap[I] = Reg;
7523 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7524 FuncInfo->InitializeRegForValue(I);
7525 SDB->CopyToExportRegsIfNeeded(I);
7529 assert(i == InVals.size() && "Argument register count mismatch!");
7531 // Finally, if the target has anything special to do, allow it to do so.
7532 EmitFunctionEntryCode();
7535 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7536 /// ensure constants are generated when needed. Remember the virtual registers
7537 /// that need to be added to the Machine PHI nodes as input. We cannot just
7538 /// directly add them, because expansion might result in multiple MBB's for one
7539 /// BB. As such, the start of the BB might correspond to a different MBB than
7543 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7544 const TerminatorInst *TI = LLVMBB->getTerminator();
7546 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7548 // Check PHI nodes in successors that expect a value to be available from this
7550 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7551 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7552 if (!isa<PHINode>(SuccBB->begin())) continue;
7553 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7555 // If this terminator has multiple identical successors (common for
7556 // switches), only handle each succ once.
7557 if (!SuccsHandled.insert(SuccMBB).second)
7560 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7562 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7563 // nodes and Machine PHI nodes, but the incoming operands have not been
7565 for (BasicBlock::const_iterator I = SuccBB->begin();
7566 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7567 // Ignore dead phi's.
7568 if (PN->use_empty()) continue;
7571 if (PN->getType()->isEmptyTy())
7575 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7577 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7578 unsigned &RegOut = ConstantsOut[C];
7580 RegOut = FuncInfo.CreateRegs(C->getType());
7581 CopyValueToVirtualRegister(C, RegOut);
7585 DenseMap<const Value *, unsigned>::iterator I =
7586 FuncInfo.ValueMap.find(PHIOp);
7587 if (I != FuncInfo.ValueMap.end())
7590 assert(isa<AllocaInst>(PHIOp) &&
7591 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7592 "Didn't codegen value into a register!??");
7593 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7594 CopyValueToVirtualRegister(PHIOp, Reg);
7598 // Remember that this register needs to added to the machine PHI node as
7599 // the input for this MBB.
7600 SmallVector<EVT, 4> ValueVTs;
7601 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7602 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7603 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7604 EVT VT = ValueVTs[vti];
7605 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7606 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7607 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7608 Reg += NumRegisters;
7613 ConstantsOut.clear();
7616 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7619 SelectionDAGBuilder::StackProtectorDescriptor::
7620 AddSuccessorMBB(const BasicBlock *BB,
7621 MachineBasicBlock *ParentMBB,
7623 MachineBasicBlock *SuccMBB) {
7624 // If SuccBB has not been created yet, create it.
7626 MachineFunction *MF = ParentMBB->getParent();
7627 MachineFunction::iterator BBI = ParentMBB;
7628 SuccMBB = MF->CreateMachineBasicBlock(BB);
7629 MF->insert(++BBI, SuccMBB);
7631 // Add it as a successor of ParentMBB.
7632 ParentMBB->addSuccessor(
7633 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7637 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7638 MachineFunction::iterator I = MBB;
7639 if (++I == FuncInfo.MF->end())
7644 /// During lowering new call nodes can be created (such as memset, etc.).
7645 /// Those will become new roots of the current DAG, but complications arise
7646 /// when they are tail calls. In such cases, the call lowering will update
7647 /// the root, but the builder still needs to know that a tail call has been
7648 /// lowered in order to avoid generating an additional return.
7649 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7650 // If the node is null, we do have a tail call.
7651 if (MaybeTC.getNode() != nullptr)
7652 DAG.setRoot(MaybeTC);
7657 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7658 unsigned *TotalCases, unsigned First,
7660 assert(Last >= First);
7661 assert(TotalCases[Last] >= TotalCases[First]);
7663 APInt LowCase = Clusters[First].Low->getValue();
7664 APInt HighCase = Clusters[Last].High->getValue();
7665 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7667 // FIXME: A range of consecutive cases has 100% density, but only requires one
7668 // comparison to lower. We should discriminate against such consecutive ranges
7671 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7672 uint64_t Range = Diff + 1;
7675 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7677 assert(NumCases < UINT64_MAX / 100);
7678 assert(Range >= NumCases);
7680 return NumCases * 100 >= Range * MinJumpTableDensity;
7683 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7684 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7685 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7688 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7689 unsigned First, unsigned Last,
7690 const SwitchInst *SI,
7691 MachineBasicBlock *DefaultMBB,
7692 CaseCluster &JTCluster) {
7693 assert(First <= Last);
7695 uint32_t Weight = 0;
7696 unsigned NumCmps = 0;
7697 std::vector<MachineBasicBlock*> Table;
7698 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7699 for (unsigned I = First; I <= Last; ++I) {
7700 assert(Clusters[I].Kind == CC_Range);
7701 Weight += Clusters[I].Weight;
7702 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7703 APInt Low = Clusters[I].Low->getValue();
7704 APInt High = Clusters[I].High->getValue();
7705 NumCmps += (Low == High) ? 1 : 2;
7707 // Fill the gap between this and the previous cluster.
7708 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7709 assert(PreviousHigh.slt(Low));
7710 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7711 for (uint64_t J = 0; J < Gap; J++)
7712 Table.push_back(DefaultMBB);
7714 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7715 for (uint64_t J = 0; J < ClusterSize; ++J)
7716 Table.push_back(Clusters[I].MBB);
7717 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7720 unsigned NumDests = JTWeights.size();
7721 if (isSuitableForBitTests(NumDests, NumCmps,
7722 Clusters[First].Low->getValue(),
7723 Clusters[Last].High->getValue())) {
7724 // Clusters[First..Last] should be lowered as bit tests instead.
7728 // Create the MBB that will load from and jump through the table.
7729 // Note: We create it here, but it's not inserted into the function yet.
7730 MachineFunction *CurMF = FuncInfo.MF;
7731 MachineBasicBlock *JumpTableMBB =
7732 CurMF->CreateMachineBasicBlock(SI->getParent());
7734 // Add successors. Note: use table order for determinism.
7735 SmallPtrSet<MachineBasicBlock *, 8> Done;
7736 for (MachineBasicBlock *Succ : Table) {
7737 if (Done.count(Succ))
7739 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7743 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7744 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7745 ->createJumpTableIndex(Table);
7747 // Set up the jump table info.
7748 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7749 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7750 Clusters[Last].High->getValue(), SI->getCondition(),
7752 JTCases.emplace_back(std::move(JTH), std::move(JT));
7754 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7755 JTCases.size() - 1, Weight);
7759 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7760 const SwitchInst *SI,
7761 MachineBasicBlock *DefaultMBB) {
7763 // Clusters must be non-empty, sorted, and only contain Range clusters.
7764 assert(!Clusters.empty());
7765 for (CaseCluster &C : Clusters)
7766 assert(C.Kind == CC_Range);
7767 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7768 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7771 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7772 if (!areJTsAllowed(TLI))
7775 const int64_t N = Clusters.size();
7776 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7778 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7779 SmallVector<unsigned, 8> TotalCases(N);
7781 for (unsigned i = 0; i < N; ++i) {
7782 APInt Hi = Clusters[i].High->getValue();
7783 APInt Lo = Clusters[i].Low->getValue();
7784 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7786 TotalCases[i] += TotalCases[i - 1];
7789 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7790 // Cheap case: the whole range might be suitable for jump table.
7791 CaseCluster JTCluster;
7792 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7793 Clusters[0] = JTCluster;
7799 // The algorithm below is not suitable for -O0.
7800 if (TM.getOptLevel() == CodeGenOpt::None)
7803 // Split Clusters into minimum number of dense partitions. The algorithm uses
7804 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7805 // for the Case Statement'" (1994), but builds the MinPartitions array in
7806 // reverse order to make it easier to reconstruct the partitions in ascending
7807 // order. In the choice between two optimal partitionings, it picks the one
7808 // which yields more jump tables.
7810 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7811 SmallVector<unsigned, 8> MinPartitions(N);
7812 // LastElement[i] is the last element of the partition starting at i.
7813 SmallVector<unsigned, 8> LastElement(N);
7814 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7815 SmallVector<unsigned, 8> NumTables(N);
7817 // Base case: There is only one way to partition Clusters[N-1].
7818 MinPartitions[N - 1] = 1;
7819 LastElement[N - 1] = N - 1;
7820 assert(MinJumpTableSize > 1);
7821 NumTables[N - 1] = 0;
7823 // Note: loop indexes are signed to avoid underflow.
7824 for (int64_t i = N - 2; i >= 0; i--) {
7825 // Find optimal partitioning of Clusters[i..N-1].
7826 // Baseline: Put Clusters[i] into a partition on its own.
7827 MinPartitions[i] = MinPartitions[i + 1] + 1;
7829 NumTables[i] = NumTables[i + 1];
7831 // Search for a solution that results in fewer partitions.
7832 for (int64_t j = N - 1; j > i; j--) {
7833 // Try building a partition from Clusters[i..j].
7834 if (isDense(Clusters, &TotalCases[0], i, j)) {
7835 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7836 bool IsTable = j - i + 1 >= MinJumpTableSize;
7837 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7839 // If this j leads to fewer partitions, or same number of partitions
7840 // with more lookup tables, it is a better partitioning.
7841 if (NumPartitions < MinPartitions[i] ||
7842 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7843 MinPartitions[i] = NumPartitions;
7845 NumTables[i] = Tables;
7851 // Iterate over the partitions, replacing some with jump tables in-place.
7852 unsigned DstIndex = 0;
7853 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7854 Last = LastElement[First];
7855 assert(Last >= First);
7856 assert(DstIndex <= First);
7857 unsigned NumClusters = Last - First + 1;
7859 CaseCluster JTCluster;
7860 if (NumClusters >= MinJumpTableSize &&
7861 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7862 Clusters[DstIndex++] = JTCluster;
7864 for (unsigned I = First; I <= Last; ++I)
7865 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7868 Clusters.resize(DstIndex);
7871 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7872 // FIXME: Using the pointer type doesn't seem ideal.
7873 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7874 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7878 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7881 const APInt &High) {
7882 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7883 // range of cases both require only one branch to lower. Just looking at the
7884 // number of clusters and destinations should be enough to decide whether to
7887 // To lower a range with bit tests, the range must fit the bitwidth of a
7889 if (!rangeFitsInWord(Low, High))
7892 // Decide whether it's profitable to lower this range with bit tests. Each
7893 // destination requires a bit test and branch, and there is an overall range
7894 // check branch. For a small number of clusters, separate comparisons might be
7895 // cheaper, and for many destinations, splitting the range might be better.
7896 return (NumDests == 1 && NumCmps >= 3) ||
7897 (NumDests == 2 && NumCmps >= 5) ||
7898 (NumDests == 3 && NumCmps >= 6);
7901 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7902 unsigned First, unsigned Last,
7903 const SwitchInst *SI,
7904 CaseCluster &BTCluster) {
7905 assert(First <= Last);
7909 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7910 unsigned NumCmps = 0;
7911 for (int64_t I = First; I <= Last; ++I) {
7912 assert(Clusters[I].Kind == CC_Range);
7913 Dests.set(Clusters[I].MBB->getNumber());
7914 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7916 unsigned NumDests = Dests.count();
7918 APInt Low = Clusters[First].Low->getValue();
7919 APInt High = Clusters[Last].High->getValue();
7920 assert(Low.slt(High));
7922 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7928 const int BitWidth = DAG.getTargetLoweringInfo()
7929 .getPointerTy(DAG.getDataLayout())
7931 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7933 // Check if the clusters cover a contiguous range such that no value in the
7934 // range will jump to the default statement.
7935 bool ContiguousRange = true;
7936 for (int64_t I = First + 1; I <= Last; ++I) {
7937 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7938 ContiguousRange = false;
7943 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7944 // Optimize the case where all the case values fit in a word without having
7945 // to subtract minValue. In this case, we can optimize away the subtraction.
7946 LowBound = APInt::getNullValue(Low.getBitWidth());
7948 ContiguousRange = false;
7951 CmpRange = High - Low;
7955 uint32_t TotalWeight = 0;
7956 for (unsigned i = First; i <= Last; ++i) {
7957 // Find the CaseBits for this destination.
7959 for (j = 0; j < CBV.size(); ++j)
7960 if (CBV[j].BB == Clusters[i].MBB)
7962 if (j == CBV.size())
7963 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7964 CaseBits *CB = &CBV[j];
7966 // Update Mask, Bits and ExtraWeight.
7967 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7968 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7969 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7970 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7971 CB->Bits += Hi - Lo + 1;
7972 CB->ExtraWeight += Clusters[i].Weight;
7973 TotalWeight += Clusters[i].Weight;
7974 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7978 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7979 // Sort by weight first, number of bits second.
7980 if (a.ExtraWeight != b.ExtraWeight)
7981 return a.ExtraWeight > b.ExtraWeight;
7982 return a.Bits > b.Bits;
7985 for (auto &CB : CBV) {
7986 MachineBasicBlock *BitTestBB =
7987 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7988 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7990 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7991 SI->getCondition(), -1U, MVT::Other, false,
7992 ContiguousRange, nullptr, nullptr, std::move(BTI),
7995 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7996 BitTestCases.size() - 1, TotalWeight);
8000 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
8001 const SwitchInst *SI) {
8002 // Partition Clusters into as few subsets as possible, where each subset has a
8003 // range that fits in a machine word and has <= 3 unique destinations.
8006 // Clusters must be sorted and contain Range or JumpTable clusters.
8007 assert(!Clusters.empty());
8008 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
8009 for (const CaseCluster &C : Clusters)
8010 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
8011 for (unsigned i = 1; i < Clusters.size(); ++i)
8012 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
8015 // The algorithm below is not suitable for -O0.
8016 if (TM.getOptLevel() == CodeGenOpt::None)
8019 // If target does not have legal shift left, do not emit bit tests at all.
8020 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8021 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
8022 if (!TLI.isOperationLegal(ISD::SHL, PTy))
8025 int BitWidth = PTy.getSizeInBits();
8026 const int64_t N = Clusters.size();
8028 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8029 SmallVector<unsigned, 8> MinPartitions(N);
8030 // LastElement[i] is the last element of the partition starting at i.
8031 SmallVector<unsigned, 8> LastElement(N);
8033 // FIXME: This might not be the best algorithm for finding bit test clusters.
8035 // Base case: There is only one way to partition Clusters[N-1].
8036 MinPartitions[N - 1] = 1;
8037 LastElement[N - 1] = N - 1;
8039 // Note: loop indexes are signed to avoid underflow.
8040 for (int64_t i = N - 2; i >= 0; --i) {
8041 // Find optimal partitioning of Clusters[i..N-1].
8042 // Baseline: Put Clusters[i] into a partition on its own.
8043 MinPartitions[i] = MinPartitions[i + 1] + 1;
8046 // Search for a solution that results in fewer partitions.
8047 // Note: the search is limited by BitWidth, reducing time complexity.
8048 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
8049 // Try building a partition from Clusters[i..j].
8052 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
8053 Clusters[j].High->getValue()))
8056 // Check nbr of destinations and cluster types.
8057 // FIXME: This works, but doesn't seem very efficient.
8058 bool RangesOnly = true;
8059 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8060 for (int64_t k = i; k <= j; k++) {
8061 if (Clusters[k].Kind != CC_Range) {
8065 Dests.set(Clusters[k].MBB->getNumber());
8067 if (!RangesOnly || Dests.count() > 3)
8070 // Check if it's a better partition.
8071 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8072 if (NumPartitions < MinPartitions[i]) {
8073 // Found a better partition.
8074 MinPartitions[i] = NumPartitions;
8080 // Iterate over the partitions, replacing with bit-test clusters in-place.
8081 unsigned DstIndex = 0;
8082 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8083 Last = LastElement[First];
8084 assert(First <= Last);
8085 assert(DstIndex <= First);
8087 CaseCluster BitTestCluster;
8088 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8089 Clusters[DstIndex++] = BitTestCluster;
8091 size_t NumClusters = Last - First + 1;
8092 std::memmove(&Clusters[DstIndex], &Clusters[First],
8093 sizeof(Clusters[0]) * NumClusters);
8094 DstIndex += NumClusters;
8097 Clusters.resize(DstIndex);
8100 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8101 MachineBasicBlock *SwitchMBB,
8102 MachineBasicBlock *DefaultMBB) {
8103 MachineFunction *CurMF = FuncInfo.MF;
8104 MachineBasicBlock *NextMBB = nullptr;
8105 MachineFunction::iterator BBI = W.MBB;
8106 if (++BBI != FuncInfo.MF->end())
8109 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8111 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8113 if (Size == 2 && W.MBB == SwitchMBB) {
8114 // If any two of the cases has the same destination, and if one value
8115 // is the same as the other, but has one bit unset that the other has set,
8116 // use bit manipulation to do two compares at once. For example:
8117 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8118 // TODO: This could be extended to merge any 2 cases in switches with 3
8120 // TODO: Handle cases where W.CaseBB != SwitchBB.
8121 CaseCluster &Small = *W.FirstCluster;
8122 CaseCluster &Big = *W.LastCluster;
8124 if (Small.Low == Small.High && Big.Low == Big.High &&
8125 Small.MBB == Big.MBB) {
8126 const APInt &SmallValue = Small.Low->getValue();
8127 const APInt &BigValue = Big.Low->getValue();
8129 // Check that there is only one bit different.
8130 APInt CommonBit = BigValue ^ SmallValue;
8131 if (CommonBit.isPowerOf2()) {
8132 SDValue CondLHS = getValue(Cond);
8133 EVT VT = CondLHS.getValueType();
8134 SDLoc DL = getCurSDLoc();
8136 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8137 DAG.getConstant(CommonBit, DL, VT));
8138 SDValue Cond = DAG.getSetCC(
8139 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8142 // Update successor info.
8143 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8144 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8145 addSuccessorWithWeight(
8146 SwitchMBB, DefaultMBB,
8147 // The default destination is the first successor in IR.
8148 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8151 // Insert the true branch.
8153 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8154 DAG.getBasicBlock(Small.MBB));
8155 // Insert the false branch.
8156 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8157 DAG.getBasicBlock(DefaultMBB));
8159 DAG.setRoot(BrCond);
8165 if (TM.getOptLevel() != CodeGenOpt::None) {
8166 // Order cases by weight so the most likely case will be checked first.
8167 std::sort(W.FirstCluster, W.LastCluster + 1,
8168 [](const CaseCluster &a, const CaseCluster &b) {
8169 return a.Weight > b.Weight;
8172 // Rearrange the case blocks so that the last one falls through if possible
8173 // without without changing the order of weights.
8174 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8176 if (I->Weight > W.LastCluster->Weight)
8178 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8179 std::swap(*I, *W.LastCluster);
8185 // Compute total weight.
8186 uint32_t DefaultWeight = W.DefaultWeight;
8187 uint32_t UnhandledWeights = DefaultWeight;
8188 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8189 UnhandledWeights += I->Weight;
8190 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8193 MachineBasicBlock *CurMBB = W.MBB;
8194 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8195 MachineBasicBlock *Fallthrough;
8196 if (I == W.LastCluster) {
8197 // For the last cluster, fall through to the default destination.
8198 Fallthrough = DefaultMBB;
8200 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8201 CurMF->insert(BBI, Fallthrough);
8202 // Put Cond in a virtual register to make it available from the new blocks.
8203 ExportFromCurrentBlock(Cond);
8205 UnhandledWeights -= I->Weight;
8208 case CC_JumpTable: {
8209 // FIXME: Optimize away range check based on pivot comparisons.
8210 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8211 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8213 // The jump block hasn't been inserted yet; insert it here.
8214 MachineBasicBlock *JumpMBB = JT->MBB;
8215 CurMF->insert(BBI, JumpMBB);
8217 uint32_t JumpWeight = I->Weight;
8218 uint32_t FallthroughWeight = UnhandledWeights;
8220 // If the default statement is a target of the jump table, we evenly
8221 // distribute the default weight to successors of CurMBB. Also update
8222 // the weight on the edge from JumpMBB to Fallthrough.
8223 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8224 SE = JumpMBB->succ_end();
8226 if (*SI == DefaultMBB) {
8227 JumpWeight += DefaultWeight / 2;
8228 FallthroughWeight -= DefaultWeight / 2;
8229 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8234 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8235 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8237 // The jump table header will be inserted in our current block, do the
8238 // range check, and fall through to our fallthrough block.
8239 JTH->HeaderBB = CurMBB;
8240 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8242 // If we're in the right place, emit the jump table header right now.
8243 if (CurMBB == SwitchMBB) {
8244 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8245 JTH->Emitted = true;
8250 // FIXME: Optimize away range check based on pivot comparisons.
8251 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8253 // The bit test blocks haven't been inserted yet; insert them here.
8254 for (BitTestCase &BTC : BTB->Cases)
8255 CurMF->insert(BBI, BTC.ThisBB);
8257 // Fill in fields of the BitTestBlock.
8258 BTB->Parent = CurMBB;
8259 BTB->Default = Fallthrough;
8261 BTB->DefaultWeight = UnhandledWeights;
8262 // If the cases in bit test don't form a contiguous range, we evenly
8263 // distribute the weight on the edge to Fallthrough to two successors
8265 if (!BTB->ContiguousRange) {
8266 BTB->Weight += DefaultWeight / 2;
8267 BTB->DefaultWeight -= DefaultWeight / 2;
8270 // If we're in the right place, emit the bit test header right now.
8271 if (CurMBB == SwitchMBB) {
8272 visitBitTestHeader(*BTB, SwitchMBB);
8273 BTB->Emitted = true;
8278 const Value *RHS, *LHS, *MHS;
8280 if (I->Low == I->High) {
8281 // Check Cond == I->Low.
8287 // Check I->Low <= Cond <= I->High.
8294 // The false weight is the sum of all unhandled cases.
8295 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8298 if (CurMBB == SwitchMBB)
8299 visitSwitchCase(CB, SwitchMBB);
8301 SwitchCases.push_back(CB);
8306 CurMBB = Fallthrough;
8310 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8311 CaseClusterIt First,
8312 CaseClusterIt Last) {
8313 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8314 if (X.Weight != CC.Weight)
8315 return X.Weight > CC.Weight;
8317 // Ties are broken by comparing the case value.
8318 return X.Low->getValue().slt(CC.Low->getValue());
8322 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8323 const SwitchWorkListItem &W,
8325 MachineBasicBlock *SwitchMBB) {
8326 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8327 "Clusters not sorted?");
8329 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8331 // Balance the tree based on branch weights to create a near-optimal (in terms
8332 // of search time given key frequency) binary search tree. See e.g. Kurt
8333 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8334 CaseClusterIt LastLeft = W.FirstCluster;
8335 CaseClusterIt FirstRight = W.LastCluster;
8336 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8337 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8339 // Move LastLeft and FirstRight towards each other from opposite directions to
8340 // find a partitioning of the clusters which balances the weight on both
8341 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8342 // taken to ensure 0-weight nodes are distributed evenly.
8344 while (LastLeft + 1 < FirstRight) {
8345 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8346 LeftWeight += (++LastLeft)->Weight;
8348 RightWeight += (--FirstRight)->Weight;
8353 // Our binary search tree differs from a typical BST in that ours can have up
8354 // to three values in each leaf. The pivot selection above doesn't take that
8355 // into account, which means the tree might require more nodes and be less
8356 // efficient. We compensate for this here.
8358 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8359 unsigned NumRight = W.LastCluster - FirstRight + 1;
8361 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8362 // If one side has less than 3 clusters, and the other has more than 3,
8363 // consider taking a cluster from the other side.
8365 if (NumLeft < NumRight) {
8366 // Consider moving the first cluster on the right to the left side.
8367 CaseCluster &CC = *FirstRight;
8368 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8369 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8370 if (LeftSideRank <= RightSideRank) {
8371 // Moving the cluster to the left does not demote it.
8377 assert(NumRight < NumLeft);
8378 // Consider moving the last element on the left to the right side.
8379 CaseCluster &CC = *LastLeft;
8380 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8381 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8382 if (RightSideRank <= LeftSideRank) {
8383 // Moving the cluster to the right does not demot it.
8393 assert(LastLeft + 1 == FirstRight);
8394 assert(LastLeft >= W.FirstCluster);
8395 assert(FirstRight <= W.LastCluster);
8397 // Use the first element on the right as pivot since we will make less-than
8398 // comparisons against it.
8399 CaseClusterIt PivotCluster = FirstRight;
8400 assert(PivotCluster > W.FirstCluster);
8401 assert(PivotCluster <= W.LastCluster);
8403 CaseClusterIt FirstLeft = W.FirstCluster;
8404 CaseClusterIt LastRight = W.LastCluster;
8406 const ConstantInt *Pivot = PivotCluster->Low;
8408 // New blocks will be inserted immediately after the current one.
8409 MachineFunction::iterator BBI = W.MBB;
8412 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8413 // we can branch to its destination directly if it's squeezed exactly in
8414 // between the known lower bound and Pivot - 1.
8415 MachineBasicBlock *LeftMBB;
8416 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8417 FirstLeft->Low == W.GE &&
8418 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8419 LeftMBB = FirstLeft->MBB;
8421 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8422 FuncInfo.MF->insert(BBI, LeftMBB);
8424 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8425 // Put Cond in a virtual register to make it available from the new blocks.
8426 ExportFromCurrentBlock(Cond);
8429 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8430 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8431 // directly if RHS.High equals the current upper bound.
8432 MachineBasicBlock *RightMBB;
8433 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8434 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8435 RightMBB = FirstRight->MBB;
8437 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8438 FuncInfo.MF->insert(BBI, RightMBB);
8440 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8441 // Put Cond in a virtual register to make it available from the new blocks.
8442 ExportFromCurrentBlock(Cond);
8445 // Create the CaseBlock record that will be used to lower the branch.
8446 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8447 LeftWeight, RightWeight);
8449 if (W.MBB == SwitchMBB)
8450 visitSwitchCase(CB, SwitchMBB);
8452 SwitchCases.push_back(CB);
8455 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8456 // Extract cases from the switch.
8457 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8458 CaseClusterVector Clusters;
8459 Clusters.reserve(SI.getNumCases());
8460 for (auto I : SI.cases()) {
8461 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8462 const ConstantInt *CaseVal = I.getCaseValue();
8464 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8465 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8468 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8470 // Cluster adjacent cases with the same destination. We do this at all
8471 // optimization levels because it's cheap to do and will make codegen faster
8472 // if there are many clusters.
8473 sortAndRangeify(Clusters);
8475 if (TM.getOptLevel() != CodeGenOpt::None) {
8476 // Replace an unreachable default with the most popular destination.
8477 // FIXME: Exploit unreachable default more aggressively.
8478 bool UnreachableDefault =
8479 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8480 if (UnreachableDefault && !Clusters.empty()) {
8481 DenseMap<const BasicBlock *, unsigned> Popularity;
8482 unsigned MaxPop = 0;
8483 const BasicBlock *MaxBB = nullptr;
8484 for (auto I : SI.cases()) {
8485 const BasicBlock *BB = I.getCaseSuccessor();
8486 if (++Popularity[BB] > MaxPop) {
8487 MaxPop = Popularity[BB];
8492 assert(MaxPop > 0 && MaxBB);
8493 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8495 // Remove cases that were pointing to the destination that is now the
8497 CaseClusterVector New;
8498 New.reserve(Clusters.size());
8499 for (CaseCluster &CC : Clusters) {
8500 if (CC.MBB != DefaultMBB)
8503 Clusters = std::move(New);
8507 // If there is only the default destination, jump there directly.
8508 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8509 if (Clusters.empty()) {
8510 SwitchMBB->addSuccessor(DefaultMBB);
8511 if (DefaultMBB != NextBlock(SwitchMBB)) {
8512 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8513 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8518 findJumpTables(Clusters, &SI, DefaultMBB);
8519 findBitTestClusters(Clusters, &SI);
8522 dbgs() << "Case clusters: ";
8523 for (const CaseCluster &C : Clusters) {
8524 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8525 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8527 C.Low->getValue().print(dbgs(), true);
8528 if (C.Low != C.High) {
8530 C.High->getValue().print(dbgs(), true);
8537 assert(!Clusters.empty());
8538 SwitchWorkList WorkList;
8539 CaseClusterIt First = Clusters.begin();
8540 CaseClusterIt Last = Clusters.end() - 1;
8541 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8542 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8544 while (!WorkList.empty()) {
8545 SwitchWorkListItem W = WorkList.back();
8546 WorkList.pop_back();
8547 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8549 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8550 // For optimized builds, lower large range as a balanced binary tree.
8551 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8555 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);