1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/ValueTracking.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/DebugInfo.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/InlineAsm.h"
45 #include "llvm/IR/Instructions.h"
46 #include "llvm/IR/IntrinsicInst.h"
47 #include "llvm/IR/Intrinsics.h"
48 #include "llvm/IR/LLVMContext.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/IR/Statepoint.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/MathExtras.h"
55 #include "llvm/Support/raw_ostream.h"
56 #include "llvm/Target/TargetFrameLowering.h"
57 #include "llvm/Target/TargetInstrInfo.h"
58 #include "llvm/Target/TargetIntrinsicInfo.h"
59 #include "llvm/Target/TargetLibraryInfo.h"
60 #include "llvm/Target/TargetLowering.h"
61 #include "llvm/Target/TargetOptions.h"
62 #include "llvm/Target/TargetSelectionDAGInfo.h"
63 #include "llvm/Target/TargetSubtargetInfo.h"
67 #define DEBUG_TYPE "isel"
69 /// LimitFloatPrecision - Generate low-precision inline sequences for
70 /// some float libcalls (6, 8 or 12 bits).
71 static unsigned LimitFloatPrecision;
73 static cl::opt<unsigned, true>
74 LimitFPPrecision("limit-float-precision",
75 cl::desc("Generate low-precision inline sequences "
76 "for some float libcalls"),
77 cl::location(LimitFloatPrecision),
80 // Limit the width of DAG chains. This is important in general to prevent
81 // prevent DAG-based analysis from blowing up. For example, alias analysis and
82 // load clustering may not complete in reasonable time. It is difficult to
83 // recognize and avoid this situation within each individual analysis, and
84 // future analyses are likely to have the same behavior. Limiting DAG width is
85 // the safe approach, and will be especially important with global DAGs.
87 // MaxParallelChains default is arbitrarily high to avoid affecting
88 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
89 // sequence over this should have been converted to llvm.memcpy by the
90 // frontend. It easy to induce this behavior with .ll code such as:
91 // %buffer = alloca [4096 x i8]
92 // %data = load [4096 x i8]* %argPtr
93 // store [4096 x i8] %data, [4096 x i8]* %buffer
94 static const unsigned MaxParallelChains = 64;
96 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
97 const SDValue *Parts, unsigned NumParts,
98 MVT PartVT, EVT ValueVT, const Value *V);
100 /// getCopyFromParts - Create a value that contains the specified legal parts
101 /// combined into the value they represent. If the parts combine to a type
102 /// larger then ValueVT then AssertOp can be used to specify whether the extra
103 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
104 /// (ISD::AssertSext).
105 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
106 const SDValue *Parts,
107 unsigned NumParts, MVT PartVT, EVT ValueVT,
109 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
110 if (ValueVT.isVector())
111 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
114 assert(NumParts > 0 && "No parts to assemble!");
115 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
116 SDValue Val = Parts[0];
119 // Assemble the value from multiple parts.
120 if (ValueVT.isInteger()) {
121 unsigned PartBits = PartVT.getSizeInBits();
122 unsigned ValueBits = ValueVT.getSizeInBits();
124 // Assemble the power of 2 part.
125 unsigned RoundParts = NumParts & (NumParts - 1) ?
126 1 << Log2_32(NumParts) : NumParts;
127 unsigned RoundBits = PartBits * RoundParts;
128 EVT RoundVT = RoundBits == ValueBits ?
129 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
132 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
134 if (RoundParts > 2) {
135 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
137 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
138 RoundParts / 2, PartVT, HalfVT, V);
140 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
141 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
144 if (TLI.isBigEndian())
147 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
149 if (RoundParts < NumParts) {
150 // Assemble the trailing non-power-of-2 part.
151 unsigned OddParts = NumParts - RoundParts;
152 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
153 Hi = getCopyFromParts(DAG, DL,
154 Parts + RoundParts, OddParts, PartVT, OddVT, V);
156 // Combine the round and odd parts.
158 if (TLI.isBigEndian())
160 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
161 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
162 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
163 DAG.getConstant(Lo.getValueType().getSizeInBits(),
164 TLI.getPointerTy()));
165 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
166 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
168 } else if (PartVT.isFloatingPoint()) {
169 // FP split into multiple FP parts (for ppcf128)
170 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
173 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
174 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
175 if (TLI.hasBigEndianPartOrdering(ValueVT))
177 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
179 // FP split into integer parts (soft fp)
180 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
181 !PartVT.isVector() && "Unexpected split");
182 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
183 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
187 // There is now one part, held in Val. Correct it to match ValueVT.
188 EVT PartEVT = Val.getValueType();
190 if (PartEVT == ValueVT)
193 if (PartEVT.isInteger() && ValueVT.isInteger()) {
194 if (ValueVT.bitsLT(PartEVT)) {
195 // For a truncate, see if we have any information to
196 // indicate whether the truncated bits will always be
197 // zero or sign-extension.
198 if (AssertOp != ISD::DELETED_NODE)
199 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
200 DAG.getValueType(ValueVT));
201 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
203 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
206 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
207 // FP_ROUND's are always exact here.
208 if (ValueVT.bitsLT(Val.getValueType()))
209 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
210 DAG.getTargetConstant(1, TLI.getPointerTy()));
212 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
215 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
216 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
218 llvm_unreachable("Unknown mismatch!");
221 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
222 const Twine &ErrMsg) {
223 const Instruction *I = dyn_cast_or_null<Instruction>(V);
225 return Ctx.emitError(ErrMsg);
227 const char *AsmError = ", possible invalid constraint for vector type";
228 if (const CallInst *CI = dyn_cast<CallInst>(I))
229 if (isa<InlineAsm>(CI->getCalledValue()))
230 return Ctx.emitError(I, ErrMsg + AsmError);
232 return Ctx.emitError(I, ErrMsg);
235 /// getCopyFromPartsVector - Create a value that contains the specified legal
236 /// parts combined into the value they represent. If the parts combine to a
237 /// type larger then ValueVT then AssertOp can be used to specify whether the
238 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
239 /// ValueVT (ISD::AssertSext).
240 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
241 const SDValue *Parts, unsigned NumParts,
242 MVT PartVT, EVT ValueVT, const Value *V) {
243 assert(ValueVT.isVector() && "Not a vector value");
244 assert(NumParts > 0 && "No parts to assemble!");
245 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
246 SDValue Val = Parts[0];
248 // Handle a multi-element vector.
252 unsigned NumIntermediates;
254 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
255 NumIntermediates, RegisterVT);
256 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
257 NumParts = NumRegs; // Silence a compiler warning.
258 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
259 assert(RegisterVT == Parts[0].getSimpleValueType() &&
260 "Part type doesn't match part!");
262 // Assemble the parts into intermediate operands.
263 SmallVector<SDValue, 8> Ops(NumIntermediates);
264 if (NumIntermediates == NumParts) {
265 // If the register was not expanded, truncate or copy the value,
267 for (unsigned i = 0; i != NumParts; ++i)
268 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
269 PartVT, IntermediateVT, V);
270 } else if (NumParts > 0) {
271 // If the intermediate type was expanded, build the intermediate
272 // operands from the parts.
273 assert(NumParts % NumIntermediates == 0 &&
274 "Must expand into a divisible number of parts!");
275 unsigned Factor = NumParts / NumIntermediates;
276 for (unsigned i = 0; i != NumIntermediates; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
278 PartVT, IntermediateVT, V);
281 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
282 // intermediate operands.
283 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
288 // There is now one part, held in Val. Correct it to match ValueVT.
289 EVT PartEVT = Val.getValueType();
291 if (PartEVT == ValueVT)
294 if (PartEVT.isVector()) {
295 // If the element type of the source/dest vectors are the same, but the
296 // parts vector has more elements than the value vector, then we have a
297 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
299 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
300 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
301 "Cannot narrow, it would be a lossy transformation");
302 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
303 DAG.getConstant(0, TLI.getVectorIdxTy()));
306 // Vector/Vector bitcast.
307 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
308 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
310 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
311 "Cannot handle this kind of promotion");
312 // Promoted vector extract
313 bool Smaller = ValueVT.bitsLE(PartEVT);
314 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
319 // Trivial bitcast if the types are the same size and the destination
320 // vector type is legal.
321 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
322 TLI.isTypeLegal(ValueVT))
323 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
325 // Handle cases such as i8 -> <1 x i1>
326 if (ValueVT.getVectorNumElements() != 1) {
327 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
328 "non-trivial scalar-to-vector conversion");
329 return DAG.getUNDEF(ValueVT);
332 if (ValueVT.getVectorNumElements() == 1 &&
333 ValueVT.getVectorElementType() != PartEVT) {
334 bool Smaller = ValueVT.bitsLE(PartEVT);
335 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
336 DL, ValueVT.getScalarType(), Val);
339 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
342 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
343 SDValue Val, SDValue *Parts, unsigned NumParts,
344 MVT PartVT, const Value *V);
346 /// getCopyToParts - Create a series of nodes that contain the specified value
347 /// split into legal parts. If the parts contain more bits than Val, then, for
348 /// integers, ExtendKind can be used to specify how to generate the extra bits.
349 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
350 SDValue Val, SDValue *Parts, unsigned NumParts,
351 MVT PartVT, const Value *V,
352 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
353 EVT ValueVT = Val.getValueType();
355 // Handle the vector case separately.
356 if (ValueVT.isVector())
357 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
359 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
360 unsigned PartBits = PartVT.getSizeInBits();
361 unsigned OrigNumParts = NumParts;
362 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
367 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
368 EVT PartEVT = PartVT;
369 if (PartEVT == ValueVT) {
370 assert(NumParts == 1 && "No-op copy with multiple parts!");
375 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
376 // If the parts cover more bits than the value has, promote the value.
377 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
378 assert(NumParts == 1 && "Do not know what to promote to!");
379 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
381 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
382 ValueVT.isInteger() &&
383 "Unknown mismatch!");
384 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
385 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
386 if (PartVT == MVT::x86mmx)
387 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
389 } else if (PartBits == ValueVT.getSizeInBits()) {
390 // Different types of the same size.
391 assert(NumParts == 1 && PartEVT != ValueVT);
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
393 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
394 // If the parts cover less bits than value has, truncate the value.
395 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
396 ValueVT.isInteger() &&
397 "Unknown mismatch!");
398 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
399 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
400 if (PartVT == MVT::x86mmx)
401 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
404 // The value may have changed - recompute ValueVT.
405 ValueVT = Val.getValueType();
406 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
407 "Failed to tile the value with PartVT!");
410 if (PartEVT != ValueVT)
411 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
412 "scalar-to-vector conversion failed");
418 // Expand the value into multiple parts.
419 if (NumParts & (NumParts - 1)) {
420 // The number of parts is not a power of 2. Split off and copy the tail.
421 assert(PartVT.isInteger() && ValueVT.isInteger() &&
422 "Do not know what to expand to!");
423 unsigned RoundParts = 1 << Log2_32(NumParts);
424 unsigned RoundBits = RoundParts * PartBits;
425 unsigned OddParts = NumParts - RoundParts;
426 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
427 DAG.getIntPtrConstant(RoundBits));
428 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
430 if (TLI.isBigEndian())
431 // The odd parts were reversed by getCopyToParts - unreverse them.
432 std::reverse(Parts + RoundParts, Parts + NumParts);
434 NumParts = RoundParts;
435 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
436 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
439 // The number of parts is a power of 2. Repeatedly bisect the value using
441 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
442 EVT::getIntegerVT(*DAG.getContext(),
443 ValueVT.getSizeInBits()),
446 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
447 for (unsigned i = 0; i < NumParts; i += StepSize) {
448 unsigned ThisBits = StepSize * PartBits / 2;
449 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
450 SDValue &Part0 = Parts[i];
451 SDValue &Part1 = Parts[i+StepSize/2];
453 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
454 ThisVT, Part0, DAG.getIntPtrConstant(1));
455 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
456 ThisVT, Part0, DAG.getIntPtrConstant(0));
458 if (ThisBits == PartBits && ThisVT != PartVT) {
459 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
460 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
465 if (TLI.isBigEndian())
466 std::reverse(Parts, Parts + OrigNumParts);
470 /// getCopyToPartsVector - Create a series of nodes that contain the specified
471 /// value split into legal parts.
472 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
473 SDValue Val, SDValue *Parts, unsigned NumParts,
474 MVT PartVT, const Value *V) {
475 EVT ValueVT = Val.getValueType();
476 assert(ValueVT.isVector() && "Not a vector");
477 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
480 EVT PartEVT = PartVT;
481 if (PartEVT == ValueVT) {
483 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
484 // Bitconvert vector->vector case.
485 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
486 } else if (PartVT.isVector() &&
487 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
488 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
489 EVT ElementVT = PartVT.getVectorElementType();
490 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
492 SmallVector<SDValue, 16> Ops;
493 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
494 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
495 ElementVT, Val, DAG.getConstant(i,
496 TLI.getVectorIdxTy())));
498 for (unsigned i = ValueVT.getVectorNumElements(),
499 e = PartVT.getVectorNumElements(); i != e; ++i)
500 Ops.push_back(DAG.getUNDEF(ElementVT));
502 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
504 // FIXME: Use CONCAT for 2x -> 4x.
506 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
507 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
508 } else if (PartVT.isVector() &&
509 PartEVT.getVectorElementType().bitsGE(
510 ValueVT.getVectorElementType()) &&
511 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
513 // Promoted vector extract
514 bool Smaller = PartEVT.bitsLE(ValueVT);
515 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
518 // Vector -> scalar conversion.
519 assert(ValueVT.getVectorNumElements() == 1 &&
520 "Only trivial vector-to-scalar conversions should get here!");
521 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
522 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
524 bool Smaller = ValueVT.bitsLE(PartVT);
525 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
533 // Handle a multi-element vector.
536 unsigned NumIntermediates;
537 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
539 NumIntermediates, RegisterVT);
540 unsigned NumElements = ValueVT.getVectorNumElements();
542 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
543 NumParts = NumRegs; // Silence a compiler warning.
544 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
546 // Split the vector into intermediate operands.
547 SmallVector<SDValue, 8> Ops(NumIntermediates);
548 for (unsigned i = 0; i != NumIntermediates; ++i) {
549 if (IntermediateVT.isVector())
550 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
552 DAG.getConstant(i * (NumElements / NumIntermediates),
553 TLI.getVectorIdxTy()));
555 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
557 DAG.getConstant(i, TLI.getVectorIdxTy()));
560 // Split the intermediate operands into legal parts.
561 if (NumParts == NumIntermediates) {
562 // If the register was not expanded, promote or copy the value,
564 for (unsigned i = 0; i != NumParts; ++i)
565 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
566 } else if (NumParts > 0) {
567 // If the intermediate type was expanded, split each the value into
569 assert(NumIntermediates != 0 && "division by zero");
570 assert(NumParts % NumIntermediates == 0 &&
571 "Must expand into a divisible number of parts!");
572 unsigned Factor = NumParts / NumIntermediates;
573 for (unsigned i = 0; i != NumIntermediates; ++i)
574 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
579 /// RegsForValue - This struct represents the registers (physical or virtual)
580 /// that a particular set of values is assigned, and the type information
581 /// about the value. The most common situation is to represent one value at a
582 /// time, but struct or array values are handled element-wise as multiple
583 /// values. The splitting of aggregates is performed recursively, so that we
584 /// never have aggregate-typed registers. The values at this point do not
585 /// necessarily have legal types, so each value may require one or more
586 /// registers of some legal type.
588 struct RegsForValue {
589 /// ValueVTs - The value types of the values, which may not be legal, and
590 /// may need be promoted or synthesized from one or more registers.
592 SmallVector<EVT, 4> ValueVTs;
594 /// RegVTs - The value types of the registers. This is the same size as
595 /// ValueVTs and it records, for each value, what the type of the assigned
596 /// register or registers are. (Individual values are never synthesized
597 /// from more than one type of register.)
599 /// With virtual registers, the contents of RegVTs is redundant with TLI's
600 /// getRegisterType member function, however when with physical registers
601 /// it is necessary to have a separate record of the types.
603 SmallVector<MVT, 4> RegVTs;
605 /// Regs - This list holds the registers assigned to the values.
606 /// Each legal or promoted value requires one register, and each
607 /// expanded value requires multiple registers.
609 SmallVector<unsigned, 4> Regs;
613 RegsForValue(const SmallVector<unsigned, 4> ®s,
614 MVT regvt, EVT valuevt)
615 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
617 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
618 unsigned Reg, Type *Ty) {
619 ComputeValueVTs(tli, Ty, ValueVTs);
621 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
622 EVT ValueVT = ValueVTs[Value];
623 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
624 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
625 for (unsigned i = 0; i != NumRegs; ++i)
626 Regs.push_back(Reg + i);
627 RegVTs.push_back(RegisterVT);
632 /// append - Add the specified values to this one.
633 void append(const RegsForValue &RHS) {
634 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
635 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
636 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
639 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
640 /// this value and returns the result as a ValueVTs value. This uses
641 /// Chain/Flag as the input and updates them for the output Chain/Flag.
642 /// If the Flag pointer is NULL, no flag is used.
643 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
645 SDValue &Chain, SDValue *Flag,
646 const Value *V = nullptr) const;
648 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
649 /// specified value into the registers specified by this object. This uses
650 /// Chain/Flag as the input and updates them for the output Chain/Flag.
651 /// If the Flag pointer is NULL, no flag is used.
653 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
654 SDValue *Flag, const Value *V,
655 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
657 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
658 /// operand list. This adds the code marker, matching input operand index
659 /// (if applicable), and includes the number of values added into it.
660 void AddInlineAsmOperands(unsigned Kind,
661 bool HasMatching, unsigned MatchingIdx,
663 std::vector<SDValue> &Ops) const;
667 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
668 /// this value and returns the result as a ValueVT value. This uses
669 /// Chain/Flag as the input and updates them for the output Chain/Flag.
670 /// If the Flag pointer is NULL, no flag is used.
671 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
672 FunctionLoweringInfo &FuncInfo,
674 SDValue &Chain, SDValue *Flag,
675 const Value *V) const {
676 // A Value with type {} or [0 x %t] needs no registers.
677 if (ValueVTs.empty())
680 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
682 // Assemble the legal parts into the final values.
683 SmallVector<SDValue, 4> Values(ValueVTs.size());
684 SmallVector<SDValue, 8> Parts;
685 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
686 // Copy the legal parts from the registers.
687 EVT ValueVT = ValueVTs[Value];
688 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
689 MVT RegisterVT = RegVTs[Value];
691 Parts.resize(NumRegs);
692 for (unsigned i = 0; i != NumRegs; ++i) {
695 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
697 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
698 *Flag = P.getValue(2);
701 Chain = P.getValue(1);
704 // If the source register was virtual and if we know something about it,
705 // add an assert node.
706 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
707 !RegisterVT.isInteger() || RegisterVT.isVector())
710 const FunctionLoweringInfo::LiveOutInfo *LOI =
711 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
715 unsigned RegSize = RegisterVT.getSizeInBits();
716 unsigned NumSignBits = LOI->NumSignBits;
717 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
719 if (NumZeroBits == RegSize) {
720 // The current value is a zero.
721 // Explicitly express that as it would be easier for
722 // optimizations to kick in.
723 Parts[i] = DAG.getConstant(0, RegisterVT);
727 // FIXME: We capture more information than the dag can represent. For
728 // now, just use the tightest assertzext/assertsext possible.
730 EVT FromVT(MVT::Other);
731 if (NumSignBits == RegSize)
732 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
733 else if (NumZeroBits >= RegSize-1)
734 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
735 else if (NumSignBits > RegSize-8)
736 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
737 else if (NumZeroBits >= RegSize-8)
738 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
739 else if (NumSignBits > RegSize-16)
740 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
741 else if (NumZeroBits >= RegSize-16)
742 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
743 else if (NumSignBits > RegSize-32)
744 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
745 else if (NumZeroBits >= RegSize-32)
746 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
750 // Add an assertion node.
751 assert(FromVT != MVT::Other);
752 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
753 RegisterVT, P, DAG.getValueType(FromVT));
756 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
757 NumRegs, RegisterVT, ValueVT, V);
762 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
765 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
766 /// specified value into the registers specified by this object. This uses
767 /// Chain/Flag as the input and updates them for the output Chain/Flag.
768 /// If the Flag pointer is NULL, no flag is used.
769 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
770 SDValue &Chain, SDValue *Flag, const Value *V,
771 ISD::NodeType PreferredExtendType) const {
772 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
773 ISD::NodeType ExtendKind = PreferredExtendType;
775 // Get the list of the values's legal parts.
776 unsigned NumRegs = Regs.size();
777 SmallVector<SDValue, 8> Parts(NumRegs);
778 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
779 EVT ValueVT = ValueVTs[Value];
780 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
781 MVT RegisterVT = RegVTs[Value];
783 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
784 ExtendKind = ISD::ZERO_EXTEND;
786 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
787 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
791 // Copy the parts into the registers.
792 SmallVector<SDValue, 8> Chains(NumRegs);
793 for (unsigned i = 0; i != NumRegs; ++i) {
796 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
798 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
799 *Flag = Part.getValue(1);
802 Chains[i] = Part.getValue(0);
805 if (NumRegs == 1 || Flag)
806 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
807 // flagged to it. That is the CopyToReg nodes and the user are considered
808 // a single scheduling unit. If we create a TokenFactor and return it as
809 // chain, then the TokenFactor is both a predecessor (operand) of the
810 // user as well as a successor (the TF operands are flagged to the user).
811 // c1, f1 = CopyToReg
812 // c2, f2 = CopyToReg
813 // c3 = TokenFactor c1, c2
816 Chain = Chains[NumRegs-1];
818 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
821 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
822 /// operand list. This adds the code marker and includes the number of
823 /// values added into it.
824 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
825 unsigned MatchingIdx,
827 std::vector<SDValue> &Ops) const {
828 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
830 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
832 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
833 else if (!Regs.empty() &&
834 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
835 // Put the register class of the virtual registers in the flag word. That
836 // way, later passes can recompute register class constraints for inline
837 // assembly as well as normal instructions.
838 // Don't do this for tied operands that can use the regclass information
840 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
841 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
842 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
845 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
848 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
849 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
850 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
851 MVT RegisterVT = RegVTs[Value];
852 for (unsigned i = 0; i != NumRegs; ++i) {
853 assert(Reg < Regs.size() && "Mismatch in # registers expected");
854 unsigned TheReg = Regs[Reg++];
855 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
857 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
858 // If we clobbered the stack pointer, MFI should know about it.
859 assert(DAG.getMachineFunction().getFrameInfo()->
860 hasInlineAsmWithSPAdjust());
866 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
867 const TargetLibraryInfo *li) {
871 DL = DAG.getSubtarget().getDataLayout();
872 Context = DAG.getContext();
873 LPadToCallSiteMap.clear();
876 /// clear - Clear out the current SelectionDAG and the associated
877 /// state and prepare this SelectionDAGBuilder object to be used
878 /// for a new block. This doesn't clear out information about
879 /// additional blocks that are needed to complete switch lowering
880 /// or PHI node updating; that information is cleared out as it is
882 void SelectionDAGBuilder::clear() {
884 UnusedArgNodeMap.clear();
885 PendingLoads.clear();
886 PendingExports.clear();
889 SDNodeOrder = LowestSDNodeOrder;
890 StatepointLowering.clear();
893 /// clearDanglingDebugInfo - Clear the dangling debug information
894 /// map. This function is separated from the clear so that debug
895 /// information that is dangling in a basic block can be properly
896 /// resolved in a different basic block. This allows the
897 /// SelectionDAG to resolve dangling debug information attached
899 void SelectionDAGBuilder::clearDanglingDebugInfo() {
900 DanglingDebugInfoMap.clear();
903 /// getRoot - Return the current virtual root of the Selection DAG,
904 /// flushing any PendingLoad items. This must be done before emitting
905 /// a store or any other node that may need to be ordered after any
906 /// prior load instructions.
908 SDValue SelectionDAGBuilder::getRoot() {
909 if (PendingLoads.empty())
910 return DAG.getRoot();
912 if (PendingLoads.size() == 1) {
913 SDValue Root = PendingLoads[0];
915 PendingLoads.clear();
919 // Otherwise, we have to make a token factor node.
920 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
922 PendingLoads.clear();
927 /// getControlRoot - Similar to getRoot, but instead of flushing all the
928 /// PendingLoad items, flush all the PendingExports items. It is necessary
929 /// to do this before emitting a terminator instruction.
931 SDValue SelectionDAGBuilder::getControlRoot() {
932 SDValue Root = DAG.getRoot();
934 if (PendingExports.empty())
937 // Turn all of the CopyToReg chains into one factored node.
938 if (Root.getOpcode() != ISD::EntryToken) {
939 unsigned i = 0, e = PendingExports.size();
940 for (; i != e; ++i) {
941 assert(PendingExports[i].getNode()->getNumOperands() > 1);
942 if (PendingExports[i].getNode()->getOperand(0) == Root)
943 break; // Don't add the root if we already indirectly depend on it.
947 PendingExports.push_back(Root);
950 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
952 PendingExports.clear();
957 void SelectionDAGBuilder::visit(const Instruction &I) {
958 // Set up outgoing PHI node register values before emitting the terminator.
959 if (isa<TerminatorInst>(&I))
960 HandlePHINodesInSuccessorBlocks(I.getParent());
966 visit(I.getOpcode(), I);
968 if (!isa<TerminatorInst>(&I) && !HasTailCall)
969 CopyToExportRegsIfNeeded(&I);
974 void SelectionDAGBuilder::visitPHI(const PHINode &) {
975 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
978 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
979 // Note: this doesn't use InstVisitor, because it has to work with
980 // ConstantExpr's in addition to instructions.
982 default: llvm_unreachable("Unknown instruction type encountered!");
983 // Build the switch statement using the Instruction.def file.
984 #define HANDLE_INST(NUM, OPCODE, CLASS) \
985 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
986 #include "llvm/IR/Instruction.def"
990 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
991 // generate the debug data structures now that we've seen its definition.
992 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
994 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
996 const DbgValueInst *DI = DDI.getDI();
997 DebugLoc dl = DDI.getdl();
998 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
999 MDNode *Variable = DI->getVariable();
1000 MDNode *Expr = DI->getExpression();
1001 uint64_t Offset = DI->getOffset();
1002 // A dbg.value for an alloca is always indirect.
1003 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1005 if (Val.getNode()) {
1006 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, Offset, IsIndirect,
1008 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1009 IsIndirect, Offset, dl, DbgSDNodeOrder);
1010 DAG.AddDbgValue(SDV, Val.getNode(), false);
1013 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1014 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1018 /// getValue - Return an SDValue for the given Value.
1019 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1020 // If we already have an SDValue for this value, use it. It's important
1021 // to do this first, so that we don't create a CopyFromReg if we already
1022 // have a regular SDValue.
1023 SDValue &N = NodeMap[V];
1024 if (N.getNode()) return N;
1026 // If there's a virtual register allocated and initialized for this
1028 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1029 if (It != FuncInfo.ValueMap.end()) {
1030 unsigned InReg = It->second;
1031 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1033 SDValue Chain = DAG.getEntryNode();
1034 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1035 resolveDanglingDebugInfo(V, N);
1039 // Otherwise create a new SDValue and remember it.
1040 SDValue Val = getValueImpl(V);
1042 resolveDanglingDebugInfo(V, Val);
1046 /// getNonRegisterValue - Return an SDValue for the given Value, but
1047 /// don't look in FuncInfo.ValueMap for a virtual register.
1048 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1049 // If we already have an SDValue for this value, use it.
1050 SDValue &N = NodeMap[V];
1051 if (N.getNode()) return N;
1053 // Otherwise create a new SDValue and remember it.
1054 SDValue Val = getValueImpl(V);
1056 resolveDanglingDebugInfo(V, Val);
1060 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1061 /// Create an SDValue for the given value.
1062 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1063 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1065 if (const Constant *C = dyn_cast<Constant>(V)) {
1066 EVT VT = TLI.getValueType(V->getType(), true);
1068 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1069 return DAG.getConstant(*CI, VT);
1071 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1072 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1074 if (isa<ConstantPointerNull>(C)) {
1075 unsigned AS = V->getType()->getPointerAddressSpace();
1076 return DAG.getConstant(0, TLI.getPointerTy(AS));
1079 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1080 return DAG.getConstantFP(*CFP, VT);
1082 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1083 return DAG.getUNDEF(VT);
1085 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1086 visit(CE->getOpcode(), *CE);
1087 SDValue N1 = NodeMap[V];
1088 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1092 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1093 SmallVector<SDValue, 4> Constants;
1094 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1096 SDNode *Val = getValue(*OI).getNode();
1097 // If the operand is an empty aggregate, there are no values.
1099 // Add each leaf value from the operand to the Constants list
1100 // to form a flattened list of all the values.
1101 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1102 Constants.push_back(SDValue(Val, i));
1105 return DAG.getMergeValues(Constants, getCurSDLoc());
1108 if (const ConstantDataSequential *CDS =
1109 dyn_cast<ConstantDataSequential>(C)) {
1110 SmallVector<SDValue, 4> Ops;
1111 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1112 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1113 // Add each leaf value from the operand to the Constants list
1114 // to form a flattened list of all the values.
1115 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1116 Ops.push_back(SDValue(Val, i));
1119 if (isa<ArrayType>(CDS->getType()))
1120 return DAG.getMergeValues(Ops, getCurSDLoc());
1121 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1125 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1126 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1127 "Unknown struct or array constant!");
1129 SmallVector<EVT, 4> ValueVTs;
1130 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1131 unsigned NumElts = ValueVTs.size();
1133 return SDValue(); // empty struct
1134 SmallVector<SDValue, 4> Constants(NumElts);
1135 for (unsigned i = 0; i != NumElts; ++i) {
1136 EVT EltVT = ValueVTs[i];
1137 if (isa<UndefValue>(C))
1138 Constants[i] = DAG.getUNDEF(EltVT);
1139 else if (EltVT.isFloatingPoint())
1140 Constants[i] = DAG.getConstantFP(0, EltVT);
1142 Constants[i] = DAG.getConstant(0, EltVT);
1145 return DAG.getMergeValues(Constants, getCurSDLoc());
1148 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1149 return DAG.getBlockAddress(BA, VT);
1151 VectorType *VecTy = cast<VectorType>(V->getType());
1152 unsigned NumElements = VecTy->getNumElements();
1154 // Now that we know the number and type of the elements, get that number of
1155 // elements into the Ops array based on what kind of constant it is.
1156 SmallVector<SDValue, 16> Ops;
1157 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1158 for (unsigned i = 0; i != NumElements; ++i)
1159 Ops.push_back(getValue(CV->getOperand(i)));
1161 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1162 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1165 if (EltVT.isFloatingPoint())
1166 Op = DAG.getConstantFP(0, EltVT);
1168 Op = DAG.getConstant(0, EltVT);
1169 Ops.assign(NumElements, Op);
1172 // Create a BUILD_VECTOR node.
1173 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1176 // If this is a static alloca, generate it as the frameindex instead of
1178 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1179 DenseMap<const AllocaInst*, int>::iterator SI =
1180 FuncInfo.StaticAllocaMap.find(AI);
1181 if (SI != FuncInfo.StaticAllocaMap.end())
1182 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1185 // If this is an instruction which fast-isel has deferred, select it now.
1186 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1187 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1188 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1189 SDValue Chain = DAG.getEntryNode();
1190 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1193 llvm_unreachable("Can't get register for value!");
1196 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1197 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1198 SDValue Chain = getControlRoot();
1199 SmallVector<ISD::OutputArg, 8> Outs;
1200 SmallVector<SDValue, 8> OutVals;
1202 if (!FuncInfo.CanLowerReturn) {
1203 unsigned DemoteReg = FuncInfo.DemoteRegister;
1204 const Function *F = I.getParent()->getParent();
1206 // Emit a store of the return value through the virtual register.
1207 // Leave Outs empty so that LowerReturn won't try to load return
1208 // registers the usual way.
1209 SmallVector<EVT, 1> PtrValueVTs;
1210 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1213 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1214 SDValue RetOp = getValue(I.getOperand(0));
1216 SmallVector<EVT, 4> ValueVTs;
1217 SmallVector<uint64_t, 4> Offsets;
1218 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1219 unsigned NumValues = ValueVTs.size();
1221 SmallVector<SDValue, 4> Chains(NumValues);
1222 for (unsigned i = 0; i != NumValues; ++i) {
1223 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1224 RetPtr.getValueType(), RetPtr,
1225 DAG.getIntPtrConstant(Offsets[i]));
1227 DAG.getStore(Chain, getCurSDLoc(),
1228 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1229 // FIXME: better loc info would be nice.
1230 Add, MachinePointerInfo(), false, false, 0);
1233 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1234 MVT::Other, Chains);
1235 } else if (I.getNumOperands() != 0) {
1236 SmallVector<EVT, 4> ValueVTs;
1237 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1238 unsigned NumValues = ValueVTs.size();
1240 SDValue RetOp = getValue(I.getOperand(0));
1241 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1242 EVT VT = ValueVTs[j];
1244 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1246 const Function *F = I.getParent()->getParent();
1247 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1249 ExtendKind = ISD::SIGN_EXTEND;
1250 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1252 ExtendKind = ISD::ZERO_EXTEND;
1254 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1255 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1257 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1258 MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1259 SmallVector<SDValue, 4> Parts(NumParts);
1260 getCopyToParts(DAG, getCurSDLoc(),
1261 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1262 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1264 // 'inreg' on function refers to return value
1265 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1266 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1270 // Propagate extension type if any
1271 if (ExtendKind == ISD::SIGN_EXTEND)
1273 else if (ExtendKind == ISD::ZERO_EXTEND)
1276 for (unsigned i = 0; i < NumParts; ++i) {
1277 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1278 VT, /*isfixed=*/true, 0, 0));
1279 OutVals.push_back(Parts[i]);
1285 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1286 CallingConv::ID CallConv =
1287 DAG.getMachineFunction().getFunction()->getCallingConv();
1288 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1289 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1291 // Verify that the target's LowerReturn behaved as expected.
1292 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1293 "LowerReturn didn't return a valid chain!");
1295 // Update the DAG with the new chain value resulting from return lowering.
1299 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1300 /// created for it, emit nodes to copy the value into the virtual
1302 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1304 if (V->getType()->isEmptyTy())
1307 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1308 if (VMI != FuncInfo.ValueMap.end()) {
1309 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1310 CopyValueToVirtualRegister(V, VMI->second);
1314 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1315 /// the current basic block, add it to ValueMap now so that we'll get a
1317 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1318 // No need to export constants.
1319 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1321 // Already exported?
1322 if (FuncInfo.isExportedInst(V)) return;
1324 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1325 CopyValueToVirtualRegister(V, Reg);
1328 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1329 const BasicBlock *FromBB) {
1330 // The operands of the setcc have to be in this block. We don't know
1331 // how to export them from some other block.
1332 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1333 // Can export from current BB.
1334 if (VI->getParent() == FromBB)
1337 // Is already exported, noop.
1338 return FuncInfo.isExportedInst(V);
1341 // If this is an argument, we can export it if the BB is the entry block or
1342 // if it is already exported.
1343 if (isa<Argument>(V)) {
1344 if (FromBB == &FromBB->getParent()->getEntryBlock())
1347 // Otherwise, can only export this if it is already exported.
1348 return FuncInfo.isExportedInst(V);
1351 // Otherwise, constants can always be exported.
1355 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1356 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1357 const MachineBasicBlock *Dst) const {
1358 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1361 const BasicBlock *SrcBB = Src->getBasicBlock();
1362 const BasicBlock *DstBB = Dst->getBasicBlock();
1363 return BPI->getEdgeWeight(SrcBB, DstBB);
1366 void SelectionDAGBuilder::
1367 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1368 uint32_t Weight /* = 0 */) {
1370 Weight = getEdgeWeight(Src, Dst);
1371 Src->addSuccessor(Dst, Weight);
1375 static bool InBlock(const Value *V, const BasicBlock *BB) {
1376 if (const Instruction *I = dyn_cast<Instruction>(V))
1377 return I->getParent() == BB;
1381 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1382 /// This function emits a branch and is used at the leaves of an OR or an
1383 /// AND operator tree.
1386 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1387 MachineBasicBlock *TBB,
1388 MachineBasicBlock *FBB,
1389 MachineBasicBlock *CurBB,
1390 MachineBasicBlock *SwitchBB,
1393 const BasicBlock *BB = CurBB->getBasicBlock();
1395 // If the leaf of the tree is a comparison, merge the condition into
1397 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1398 // The operands of the cmp have to be in this block. We don't know
1399 // how to export them from some other block. If this is the first block
1400 // of the sequence, no exporting is needed.
1401 if (CurBB == SwitchBB ||
1402 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1403 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1404 ISD::CondCode Condition;
1405 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1406 Condition = getICmpCondCode(IC->getPredicate());
1407 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1408 Condition = getFCmpCondCode(FC->getPredicate());
1409 if (TM.Options.NoNaNsFPMath)
1410 Condition = getFCmpCodeWithoutNaN(Condition);
1412 (void)Condition; // silence warning.
1413 llvm_unreachable("Unknown compare instruction");
1416 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1417 TBB, FBB, CurBB, TWeight, FWeight);
1418 SwitchCases.push_back(CB);
1423 // Create a CaseBlock record representing this branch.
1424 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1425 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1426 SwitchCases.push_back(CB);
1429 /// Scale down both weights to fit into uint32_t.
1430 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1431 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1432 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1433 NewTrue = NewTrue / Scale;
1434 NewFalse = NewFalse / Scale;
1437 /// FindMergedConditions - If Cond is an expression like
1438 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1439 MachineBasicBlock *TBB,
1440 MachineBasicBlock *FBB,
1441 MachineBasicBlock *CurBB,
1442 MachineBasicBlock *SwitchBB,
1443 unsigned Opc, uint32_t TWeight,
1445 // If this node is not part of the or/and tree, emit it as a branch.
1446 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1447 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1448 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1449 BOp->getParent() != CurBB->getBasicBlock() ||
1450 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1451 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1452 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1457 // Create TmpBB after CurBB.
1458 MachineFunction::iterator BBI = CurBB;
1459 MachineFunction &MF = DAG.getMachineFunction();
1460 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1461 CurBB->getParent()->insert(++BBI, TmpBB);
1463 if (Opc == Instruction::Or) {
1464 // Codegen X | Y as:
1473 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1474 // The requirement is that
1475 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1476 // = TrueProb for orignal BB.
1477 // Assuming the orignal weights are A and B, one choice is to set BB1's
1478 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1480 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1481 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1482 // TmpBB, but the math is more complicated.
1484 uint64_t NewTrueWeight = TWeight;
1485 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1486 ScaleWeights(NewTrueWeight, NewFalseWeight);
1487 // Emit the LHS condition.
1488 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1489 NewTrueWeight, NewFalseWeight);
1491 NewTrueWeight = TWeight;
1492 NewFalseWeight = 2 * (uint64_t)FWeight;
1493 ScaleWeights(NewTrueWeight, NewFalseWeight);
1494 // Emit the RHS condition into TmpBB.
1495 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1496 NewTrueWeight, NewFalseWeight);
1498 assert(Opc == Instruction::And && "Unknown merge op!");
1499 // Codegen X & Y as:
1507 // This requires creation of TmpBB after CurBB.
1509 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1510 // The requirement is that
1511 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1512 // = FalseProb for orignal BB.
1513 // Assuming the orignal weights are A and B, one choice is to set BB1's
1514 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1516 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1518 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1519 uint64_t NewFalseWeight = FWeight;
1520 ScaleWeights(NewTrueWeight, NewFalseWeight);
1521 // Emit the LHS condition.
1522 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1523 NewTrueWeight, NewFalseWeight);
1525 NewTrueWeight = 2 * (uint64_t)TWeight;
1526 NewFalseWeight = FWeight;
1527 ScaleWeights(NewTrueWeight, NewFalseWeight);
1528 // Emit the RHS condition into TmpBB.
1529 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1530 NewTrueWeight, NewFalseWeight);
1534 /// If the set of cases should be emitted as a series of branches, return true.
1535 /// If we should emit this as a bunch of and/or'd together conditions, return
1538 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1539 if (Cases.size() != 2) return true;
1541 // If this is two comparisons of the same values or'd or and'd together, they
1542 // will get folded into a single comparison, so don't emit two blocks.
1543 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1544 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1545 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1546 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1550 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1551 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1552 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1553 Cases[0].CC == Cases[1].CC &&
1554 isa<Constant>(Cases[0].CmpRHS) &&
1555 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1556 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1558 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1565 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1566 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1568 // Update machine-CFG edges.
1569 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1571 // Figure out which block is immediately after the current one.
1572 MachineBasicBlock *NextBlock = nullptr;
1573 MachineFunction::iterator BBI = BrMBB;
1574 if (++BBI != FuncInfo.MF->end())
1577 if (I.isUnconditional()) {
1578 // Update machine-CFG edges.
1579 BrMBB->addSuccessor(Succ0MBB);
1581 // If this is not a fall-through branch or optimizations are switched off,
1583 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1584 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1585 MVT::Other, getControlRoot(),
1586 DAG.getBasicBlock(Succ0MBB)));
1591 // If this condition is one of the special cases we handle, do special stuff
1593 const Value *CondVal = I.getCondition();
1594 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1596 // If this is a series of conditions that are or'd or and'd together, emit
1597 // this as a sequence of branches instead of setcc's with and/or operations.
1598 // As long as jumps are not expensive, this should improve performance.
1599 // For example, instead of something like:
1612 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1613 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1614 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1615 BOp->getOpcode() == Instruction::Or)) {
1616 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1617 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1618 getEdgeWeight(BrMBB, Succ1MBB));
1619 // If the compares in later blocks need to use values not currently
1620 // exported from this block, export them now. This block should always
1621 // be the first entry.
1622 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1624 // Allow some cases to be rejected.
1625 if (ShouldEmitAsBranches(SwitchCases)) {
1626 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1627 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1628 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1631 // Emit the branch for this block.
1632 visitSwitchCase(SwitchCases[0], BrMBB);
1633 SwitchCases.erase(SwitchCases.begin());
1637 // Okay, we decided not to do this, remove any inserted MBB's and clear
1639 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1640 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1642 SwitchCases.clear();
1646 // Create a CaseBlock record representing this branch.
1647 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1648 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1650 // Use visitSwitchCase to actually insert the fast branch sequence for this
1652 visitSwitchCase(CB, BrMBB);
1655 /// visitSwitchCase - Emits the necessary code to represent a single node in
1656 /// the binary search tree resulting from lowering a switch instruction.
1657 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1658 MachineBasicBlock *SwitchBB) {
1660 SDValue CondLHS = getValue(CB.CmpLHS);
1661 SDLoc dl = getCurSDLoc();
1663 // Build the setcc now.
1665 // Fold "(X == true)" to X and "(X == false)" to !X to
1666 // handle common cases produced by branch lowering.
1667 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1668 CB.CC == ISD::SETEQ)
1670 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1671 CB.CC == ISD::SETEQ) {
1672 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1673 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1675 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1677 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1679 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1680 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1682 SDValue CmpOp = getValue(CB.CmpMHS);
1683 EVT VT = CmpOp.getValueType();
1685 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1686 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1689 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1690 VT, CmpOp, DAG.getConstant(Low, VT));
1691 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1692 DAG.getConstant(High-Low, VT), ISD::SETULE);
1696 // Update successor info
1697 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1698 // TrueBB and FalseBB are always different unless the incoming IR is
1699 // degenerate. This only happens when running llc on weird IR.
1700 if (CB.TrueBB != CB.FalseBB)
1701 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1703 // Set NextBlock to be the MBB immediately after the current one, if any.
1704 // This is used to avoid emitting unnecessary branches to the next block.
1705 MachineBasicBlock *NextBlock = nullptr;
1706 MachineFunction::iterator BBI = SwitchBB;
1707 if (++BBI != FuncInfo.MF->end())
1710 // If the lhs block is the next block, invert the condition so that we can
1711 // fall through to the lhs instead of the rhs block.
1712 if (CB.TrueBB == NextBlock) {
1713 std::swap(CB.TrueBB, CB.FalseBB);
1714 SDValue True = DAG.getConstant(1, Cond.getValueType());
1715 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1718 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1719 MVT::Other, getControlRoot(), Cond,
1720 DAG.getBasicBlock(CB.TrueBB));
1722 // Insert the false branch. Do this even if it's a fall through branch,
1723 // this makes it easier to do DAG optimizations which require inverting
1724 // the branch condition.
1725 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1726 DAG.getBasicBlock(CB.FalseBB));
1728 DAG.setRoot(BrCond);
1731 /// visitJumpTable - Emit JumpTable node in the current MBB
1732 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1733 // Emit the code for the jump table
1734 assert(JT.Reg != -1U && "Should lower JT Header first!");
1735 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1736 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1738 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1739 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1740 MVT::Other, Index.getValue(1),
1742 DAG.setRoot(BrJumpTable);
1745 /// visitJumpTableHeader - This function emits necessary code to produce index
1746 /// in the JumpTable from switch case.
1747 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1748 JumpTableHeader &JTH,
1749 MachineBasicBlock *SwitchBB) {
1750 // Subtract the lowest switch case value from the value being switched on and
1751 // conditional branch to default mbb if the result is greater than the
1752 // difference between smallest and largest cases.
1753 SDValue SwitchOp = getValue(JTH.SValue);
1754 EVT VT = SwitchOp.getValueType();
1755 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1756 DAG.getConstant(JTH.First, VT));
1758 // The SDNode we just created, which holds the value being switched on minus
1759 // the smallest case value, needs to be copied to a virtual register so it
1760 // can be used as an index into the jump table in a subsequent basic block.
1761 // This value may be smaller or larger than the target's pointer type, and
1762 // therefore require extension or truncating.
1763 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1764 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1766 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1767 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1768 JumpTableReg, SwitchOp);
1769 JT.Reg = JumpTableReg;
1771 // Emit the range check for the jump table, and branch to the default block
1772 // for the switch statement if the value being switched on exceeds the largest
1773 // case in the switch.
1775 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1776 Sub.getValueType()),
1777 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1779 // Set NextBlock to be the MBB immediately after the current one, if any.
1780 // This is used to avoid emitting unnecessary branches to the next block.
1781 MachineBasicBlock *NextBlock = nullptr;
1782 MachineFunction::iterator BBI = SwitchBB;
1784 if (++BBI != FuncInfo.MF->end())
1787 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1788 MVT::Other, CopyTo, CMP,
1789 DAG.getBasicBlock(JT.Default));
1791 if (JT.MBB != NextBlock)
1792 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1793 DAG.getBasicBlock(JT.MBB));
1795 DAG.setRoot(BrCond);
1798 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1799 /// tail spliced into a stack protector check success bb.
1801 /// For a high level explanation of how this fits into the stack protector
1802 /// generation see the comment on the declaration of class
1803 /// StackProtectorDescriptor.
1804 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1805 MachineBasicBlock *ParentBB) {
1807 // First create the loads to the guard/stack slot for the comparison.
1808 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1809 EVT PtrTy = TLI.getPointerTy();
1811 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1812 int FI = MFI->getStackProtectorIndex();
1814 const Value *IRGuard = SPD.getGuard();
1815 SDValue GuardPtr = getValue(IRGuard);
1816 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1819 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1823 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1824 // guard value from the virtual register holding the value. Otherwise, emit a
1825 // volatile load to retrieve the stack guard value.
1826 unsigned GuardReg = SPD.getGuardReg();
1828 if (GuardReg && TLI.useLoadStackGuardNode())
1829 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1832 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1833 GuardPtr, MachinePointerInfo(IRGuard, 0),
1834 true, false, false, Align);
1836 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1838 MachinePointerInfo::getFixedStack(FI),
1839 true, false, false, Align);
1841 // Perform the comparison via a subtract/getsetcc.
1842 EVT VT = Guard.getValueType();
1843 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1846 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1847 Sub.getValueType()),
1848 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1850 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1851 // branch to failure MBB.
1852 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1853 MVT::Other, StackSlot.getOperand(0),
1854 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1855 // Otherwise branch to success MBB.
1856 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1858 DAG.getBasicBlock(SPD.getSuccessMBB()));
1863 /// Codegen the failure basic block for a stack protector check.
1865 /// A failure stack protector machine basic block consists simply of a call to
1866 /// __stack_chk_fail().
1868 /// For a high level explanation of how this fits into the stack protector
1869 /// generation see the comment on the declaration of class
1870 /// StackProtectorDescriptor.
1872 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1873 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1875 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1876 nullptr, 0, false, getCurSDLoc(), false, false).second;
1880 /// visitBitTestHeader - This function emits necessary code to produce value
1881 /// suitable for "bit tests"
1882 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1883 MachineBasicBlock *SwitchBB) {
1884 // Subtract the minimum value
1885 SDValue SwitchOp = getValue(B.SValue);
1886 EVT VT = SwitchOp.getValueType();
1887 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1888 DAG.getConstant(B.First, VT));
1891 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1893 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1894 Sub.getValueType()),
1895 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1897 // Determine the type of the test operands.
1898 bool UsePtrType = false;
1899 if (!TLI.isTypeLegal(VT))
1902 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1903 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1904 // Switch table case range are encoded into series of masks.
1905 // Just use pointer type, it's guaranteed to fit.
1911 VT = TLI.getPointerTy();
1912 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1915 B.RegVT = VT.getSimpleVT();
1916 B.Reg = FuncInfo.CreateReg(B.RegVT);
1917 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1920 // Set NextBlock to be the MBB immediately after the current one, if any.
1921 // This is used to avoid emitting unnecessary branches to the next block.
1922 MachineBasicBlock *NextBlock = nullptr;
1923 MachineFunction::iterator BBI = SwitchBB;
1924 if (++BBI != FuncInfo.MF->end())
1927 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1929 addSuccessorWithWeight(SwitchBB, B.Default);
1930 addSuccessorWithWeight(SwitchBB, MBB);
1932 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1933 MVT::Other, CopyTo, RangeCmp,
1934 DAG.getBasicBlock(B.Default));
1936 if (MBB != NextBlock)
1937 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1938 DAG.getBasicBlock(MBB));
1940 DAG.setRoot(BrRange);
1943 /// visitBitTestCase - this function produces one "bit test"
1944 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1945 MachineBasicBlock* NextMBB,
1946 uint32_t BranchWeightToNext,
1949 MachineBasicBlock *SwitchBB) {
1951 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1954 unsigned PopCount = CountPopulation_64(B.Mask);
1955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1956 if (PopCount == 1) {
1957 // Testing for a single bit; just compare the shift count with what it
1958 // would need to be to shift a 1 bit in that position.
1960 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1961 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1962 } else if (PopCount == BB.Range) {
1963 // There is only one zero bit in the range, test for it directly.
1965 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1966 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), ISD::SETNE);
1968 // Make desired shift
1969 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1970 DAG.getConstant(1, VT), ShiftOp);
1972 // Emit bit tests and jumps
1973 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1974 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1975 Cmp = DAG.getSetCC(getCurSDLoc(),
1976 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1977 DAG.getConstant(0, VT), ISD::SETNE);
1980 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1981 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1982 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1983 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1985 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1986 MVT::Other, getControlRoot(),
1987 Cmp, DAG.getBasicBlock(B.TargetBB));
1989 // Set NextBlock to be the MBB immediately after the current one, if any.
1990 // This is used to avoid emitting unnecessary branches to the next block.
1991 MachineBasicBlock *NextBlock = nullptr;
1992 MachineFunction::iterator BBI = SwitchBB;
1993 if (++BBI != FuncInfo.MF->end())
1996 if (NextMBB != NextBlock)
1997 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1998 DAG.getBasicBlock(NextMBB));
2003 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2004 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2006 // Retrieve successors.
2007 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2008 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2010 const Value *Callee(I.getCalledValue());
2011 const Function *Fn = dyn_cast<Function>(Callee);
2012 if (isa<InlineAsm>(Callee))
2014 else if (Fn && Fn->isIntrinsic()) {
2015 switch (Fn->getIntrinsicID()) {
2017 llvm_unreachable("Cannot invoke this intrinsic");
2018 case Intrinsic::donothing:
2019 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2021 case Intrinsic::experimental_patchpoint_void:
2022 case Intrinsic::experimental_patchpoint_i64:
2023 visitPatchpoint(&I, LandingPad);
2027 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2029 // If the value of the invoke is used outside of its defining block, make it
2030 // available as a virtual register.
2031 CopyToExportRegsIfNeeded(&I);
2033 // Update successor info
2034 addSuccessorWithWeight(InvokeMBB, Return);
2035 addSuccessorWithWeight(InvokeMBB, LandingPad);
2037 // Drop into normal successor.
2038 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2039 MVT::Other, getControlRoot(),
2040 DAG.getBasicBlock(Return)));
2043 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2044 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2047 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2048 assert(FuncInfo.MBB->isLandingPad() &&
2049 "Call to landingpad not in landing pad!");
2051 MachineBasicBlock *MBB = FuncInfo.MBB;
2052 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2053 AddLandingPadInfo(LP, MMI, MBB);
2055 // If there aren't registers to copy the values into (e.g., during SjLj
2056 // exceptions), then don't bother to create these DAG nodes.
2057 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2058 if (TLI.getExceptionPointerRegister() == 0 &&
2059 TLI.getExceptionSelectorRegister() == 0)
2062 SmallVector<EVT, 2> ValueVTs;
2063 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2064 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2066 // Get the two live-in registers as SDValues. The physregs have already been
2067 // copied into virtual registers.
2069 Ops[0] = DAG.getZExtOrTrunc(
2070 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2071 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2072 getCurSDLoc(), ValueVTs[0]);
2073 Ops[1] = DAG.getZExtOrTrunc(
2074 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2075 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2076 getCurSDLoc(), ValueVTs[1]);
2079 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2080 DAG.getVTList(ValueVTs), Ops);
2084 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2085 /// small case ranges).
2086 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2087 CaseRecVector& WorkList,
2089 MachineBasicBlock *Default,
2090 MachineBasicBlock *SwitchBB) {
2091 // Size is the number of Cases represented by this range.
2092 size_t Size = CR.Range.second - CR.Range.first;
2096 // Get the MachineFunction which holds the current MBB. This is used when
2097 // inserting any additional MBBs necessary to represent the switch.
2098 MachineFunction *CurMF = FuncInfo.MF;
2100 // Figure out which block is immediately after the current one.
2101 MachineBasicBlock *NextBlock = nullptr;
2102 MachineFunction::iterator BBI = CR.CaseBB;
2104 if (++BBI != FuncInfo.MF->end())
2107 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2108 // If any two of the cases has the same destination, and if one value
2109 // is the same as the other, but has one bit unset that the other has set,
2110 // use bit manipulation to do two compares at once. For example:
2111 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2112 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2113 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2114 if (Size == 2 && CR.CaseBB == SwitchBB) {
2115 Case &Small = *CR.Range.first;
2116 Case &Big = *(CR.Range.second-1);
2118 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2119 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2120 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2122 // Check that there is only one bit different.
2123 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2124 (SmallValue | BigValue) == BigValue) {
2125 // Isolate the common bit.
2126 APInt CommonBit = BigValue & ~SmallValue;
2127 assert((SmallValue | CommonBit) == BigValue &&
2128 CommonBit.countPopulation() == 1 && "Not a common bit?");
2130 SDValue CondLHS = getValue(SV);
2131 EVT VT = CondLHS.getValueType();
2132 SDLoc DL = getCurSDLoc();
2134 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2135 DAG.getConstant(CommonBit, VT));
2136 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2137 Or, DAG.getConstant(BigValue, VT),
2140 // Update successor info.
2141 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2142 addSuccessorWithWeight(SwitchBB, Small.BB,
2143 Small.ExtraWeight + Big.ExtraWeight);
2144 addSuccessorWithWeight(SwitchBB, Default,
2145 // The default destination is the first successor in IR.
2146 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2148 // Insert the true branch.
2149 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2150 getControlRoot(), Cond,
2151 DAG.getBasicBlock(Small.BB));
2153 // Insert the false branch.
2154 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2155 DAG.getBasicBlock(Default));
2157 DAG.setRoot(BrCond);
2163 // Order cases by weight so the most likely case will be checked first.
2164 uint32_t UnhandledWeights = 0;
2166 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2167 uint32_t IWeight = I->ExtraWeight;
2168 UnhandledWeights += IWeight;
2169 for (CaseItr J = CR.Range.first; J < I; ++J) {
2170 uint32_t JWeight = J->ExtraWeight;
2171 if (IWeight > JWeight)
2176 // Rearrange the case blocks so that the last one falls through if possible.
2177 Case &BackCase = *(CR.Range.second-1);
2179 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2180 // The last case block won't fall through into 'NextBlock' if we emit the
2181 // branches in this order. See if rearranging a case value would help.
2182 // We start at the bottom as it's the case with the least weight.
2183 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2184 if (I->BB == NextBlock) {
2185 std::swap(*I, BackCase);
2190 // Create a CaseBlock record representing a conditional branch to
2191 // the Case's target mbb if the value being switched on SV is equal
2193 MachineBasicBlock *CurBlock = CR.CaseBB;
2194 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2195 MachineBasicBlock *FallThrough;
2197 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2198 CurMF->insert(BBI, FallThrough);
2200 // Put SV in a virtual register to make it available from the new blocks.
2201 ExportFromCurrentBlock(SV);
2203 // If the last case doesn't match, go to the default block.
2204 FallThrough = Default;
2207 const Value *RHS, *LHS, *MHS;
2209 if (I->High == I->Low) {
2210 // This is just small small case range :) containing exactly 1 case
2212 LHS = SV; RHS = I->High; MHS = nullptr;
2215 LHS = I->Low; MHS = SV; RHS = I->High;
2218 // The false weight should be sum of all un-handled cases.
2219 UnhandledWeights -= I->ExtraWeight;
2220 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2222 /* trueweight */ I->ExtraWeight,
2223 /* falseweight */ UnhandledWeights);
2225 // If emitting the first comparison, just call visitSwitchCase to emit the
2226 // code into the current block. Otherwise, push the CaseBlock onto the
2227 // vector to be later processed by SDISel, and insert the node's MBB
2228 // before the next MBB.
2229 if (CurBlock == SwitchBB)
2230 visitSwitchCase(CB, SwitchBB);
2232 SwitchCases.push_back(CB);
2234 CurBlock = FallThrough;
2240 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2241 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2242 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2245 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2246 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2247 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2248 return (LastExt - FirstExt + 1ULL);
2251 /// handleJTSwitchCase - Emit jumptable for current switch case range
2252 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2253 CaseRecVector &WorkList,
2255 MachineBasicBlock *Default,
2256 MachineBasicBlock *SwitchBB) {
2257 Case& FrontCase = *CR.Range.first;
2258 Case& BackCase = *(CR.Range.second-1);
2260 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2261 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2263 APInt TSize(First.getBitWidth(), 0);
2264 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2267 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2268 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2271 APInt Range = ComputeRange(First, Last);
2272 // The density is TSize / Range. Require at least 40%.
2273 // It should not be possible for IntTSize to saturate for sane code, but make
2274 // sure we handle Range saturation correctly.
2275 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2276 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2277 if (IntTSize * 10 < IntRange * 4)
2280 DEBUG(dbgs() << "Lowering jump table\n"
2281 << "First entry: " << First << ". Last entry: " << Last << '\n'
2282 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2284 // Get the MachineFunction which holds the current MBB. This is used when
2285 // inserting any additional MBBs necessary to represent the switch.
2286 MachineFunction *CurMF = FuncInfo.MF;
2288 // Figure out which block is immediately after the current one.
2289 MachineFunction::iterator BBI = CR.CaseBB;
2292 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2294 // Create a new basic block to hold the code for loading the address
2295 // of the jump table, and jumping to it. Update successor information;
2296 // we will either branch to the default case for the switch, or the jump
2298 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2299 CurMF->insert(BBI, JumpTableBB);
2301 addSuccessorWithWeight(CR.CaseBB, Default);
2302 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2304 // Build a vector of destination BBs, corresponding to each target
2305 // of the jump table. If the value of the jump table slot corresponds to
2306 // a case statement, push the case's BB onto the vector, otherwise, push
2308 std::vector<MachineBasicBlock*> DestBBs;
2310 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2311 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2312 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2314 if (Low.sle(TEI) && TEI.sle(High)) {
2315 DestBBs.push_back(I->BB);
2319 DestBBs.push_back(Default);
2323 // Calculate weight for each unique destination in CR.
2324 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2326 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2327 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2328 DestWeights.find(I->BB);
2329 if (Itr != DestWeights.end())
2330 Itr->second += I->ExtraWeight;
2332 DestWeights[I->BB] = I->ExtraWeight;
2335 // Update successor info. Add one edge to each unique successor.
2336 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2337 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2338 E = DestBBs.end(); I != E; ++I) {
2339 if (!SuccsHandled[(*I)->getNumber()]) {
2340 SuccsHandled[(*I)->getNumber()] = true;
2341 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2342 DestWeights.find(*I);
2343 addSuccessorWithWeight(JumpTableBB, *I,
2344 Itr != DestWeights.end() ? Itr->second : 0);
2348 // Create a jump table index for this jump table.
2349 unsigned JTEncoding = TLI.getJumpTableEncoding();
2350 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2351 ->createJumpTableIndex(DestBBs);
2353 // Set the jump table information so that we can codegen it as a second
2354 // MachineBasicBlock
2355 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2356 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2357 if (CR.CaseBB == SwitchBB)
2358 visitJumpTableHeader(JT, JTH, SwitchBB);
2360 JTCases.push_back(JumpTableBlock(JTH, JT));
2364 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2366 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2367 CaseRecVector& WorkList,
2369 MachineBasicBlock* SwitchBB) {
2370 // Get the MachineFunction which holds the current MBB. This is used when
2371 // inserting any additional MBBs necessary to represent the switch.
2372 MachineFunction *CurMF = FuncInfo.MF;
2374 // Figure out which block is immediately after the current one.
2375 MachineFunction::iterator BBI = CR.CaseBB;
2378 Case& FrontCase = *CR.Range.first;
2379 Case& BackCase = *(CR.Range.second-1);
2380 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2382 // Size is the number of Cases represented by this range.
2383 unsigned Size = CR.Range.second - CR.Range.first;
2385 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2386 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2388 CaseItr Pivot = CR.Range.first + Size/2;
2390 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2391 // (heuristically) allow us to emit JumpTable's later.
2392 APInt TSize(First.getBitWidth(), 0);
2393 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2397 APInt LSize = FrontCase.size();
2398 APInt RSize = TSize-LSize;
2399 DEBUG(dbgs() << "Selecting best pivot: \n"
2400 << "First: " << First << ", Last: " << Last <<'\n'
2401 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2402 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2404 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2405 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2406 APInt Range = ComputeRange(LEnd, RBegin);
2407 assert((Range - 2ULL).isNonNegative() &&
2408 "Invalid case distance");
2409 // Use volatile double here to avoid excess precision issues on some hosts,
2410 // e.g. that use 80-bit X87 registers.
2411 volatile double LDensity =
2412 (double)LSize.roundToDouble() /
2413 (LEnd - First + 1ULL).roundToDouble();
2414 volatile double RDensity =
2415 (double)RSize.roundToDouble() /
2416 (Last - RBegin + 1ULL).roundToDouble();
2417 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2418 // Should always split in some non-trivial place
2419 DEBUG(dbgs() <<"=>Step\n"
2420 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2421 << "LDensity: " << LDensity
2422 << ", RDensity: " << RDensity << '\n'
2423 << "Metric: " << Metric << '\n');
2424 if (FMetric < Metric) {
2427 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2434 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2435 if (areJTsAllowed(TLI)) {
2436 // If our case is dense we *really* should handle it earlier!
2437 assert((FMetric > 0) && "Should handle dense range earlier!");
2439 Pivot = CR.Range.first + Size/2;
2442 CaseRange LHSR(CR.Range.first, Pivot);
2443 CaseRange RHSR(Pivot, CR.Range.second);
2444 const Constant *C = Pivot->Low;
2445 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2447 // We know that we branch to the LHS if the Value being switched on is
2448 // less than the Pivot value, C. We use this to optimize our binary
2449 // tree a bit, by recognizing that if SV is greater than or equal to the
2450 // LHS's Case Value, and that Case Value is exactly one less than the
2451 // Pivot's Value, then we can branch directly to the LHS's Target,
2452 // rather than creating a leaf node for it.
2453 if ((LHSR.second - LHSR.first) == 1 &&
2454 LHSR.first->High == CR.GE &&
2455 cast<ConstantInt>(C)->getValue() ==
2456 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2457 TrueBB = LHSR.first->BB;
2459 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2460 CurMF->insert(BBI, TrueBB);
2461 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2463 // Put SV in a virtual register to make it available from the new blocks.
2464 ExportFromCurrentBlock(SV);
2467 // Similar to the optimization above, if the Value being switched on is
2468 // known to be less than the Constant CR.LT, and the current Case Value
2469 // is CR.LT - 1, then we can branch directly to the target block for
2470 // the current Case Value, rather than emitting a RHS leaf node for it.
2471 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2472 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2473 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2474 FalseBB = RHSR.first->BB;
2476 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2477 CurMF->insert(BBI, FalseBB);
2478 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2480 // Put SV in a virtual register to make it available from the new blocks.
2481 ExportFromCurrentBlock(SV);
2484 // Create a CaseBlock record representing a conditional branch to
2485 // the LHS node if the value being switched on SV is less than C.
2486 // Otherwise, branch to LHS.
2487 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2489 if (CR.CaseBB == SwitchBB)
2490 visitSwitchCase(CB, SwitchBB);
2492 SwitchCases.push_back(CB);
2497 /// handleBitTestsSwitchCase - if current case range has few destination and
2498 /// range span less, than machine word bitwidth, encode case range into series
2499 /// of masks and emit bit tests with these masks.
2500 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2501 CaseRecVector& WorkList,
2503 MachineBasicBlock* Default,
2504 MachineBasicBlock* SwitchBB) {
2505 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2506 EVT PTy = TLI.getPointerTy();
2507 unsigned IntPtrBits = PTy.getSizeInBits();
2509 Case& FrontCase = *CR.Range.first;
2510 Case& BackCase = *(CR.Range.second-1);
2512 // Get the MachineFunction which holds the current MBB. This is used when
2513 // inserting any additional MBBs necessary to represent the switch.
2514 MachineFunction *CurMF = FuncInfo.MF;
2516 // If target does not have legal shift left, do not emit bit tests at all.
2517 if (!TLI.isOperationLegal(ISD::SHL, PTy))
2521 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2522 // Single case counts one, case range - two.
2523 numCmps += (I->Low == I->High ? 1 : 2);
2526 // Count unique destinations
2527 SmallSet<MachineBasicBlock*, 4> Dests;
2528 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2529 Dests.insert(I->BB);
2530 if (Dests.size() > 3)
2531 // Don't bother the code below, if there are too much unique destinations
2534 DEBUG(dbgs() << "Total number of unique destinations: "
2535 << Dests.size() << '\n'
2536 << "Total number of comparisons: " << numCmps << '\n');
2538 // Compute span of values.
2539 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2540 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2541 APInt cmpRange = maxValue - minValue;
2543 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2544 << "Low bound: " << minValue << '\n'
2545 << "High bound: " << maxValue << '\n');
2547 if (cmpRange.uge(IntPtrBits) ||
2548 (!(Dests.size() == 1 && numCmps >= 3) &&
2549 !(Dests.size() == 2 && numCmps >= 5) &&
2550 !(Dests.size() >= 3 && numCmps >= 6)))
2553 DEBUG(dbgs() << "Emitting bit tests\n");
2554 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2556 // Optimize the case where all the case values fit in a
2557 // word without having to subtract minValue. In this case,
2558 // we can optimize away the subtraction.
2559 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2560 cmpRange = maxValue;
2562 lowBound = minValue;
2565 CaseBitsVector CasesBits;
2566 unsigned i, count = 0;
2568 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2569 MachineBasicBlock* Dest = I->BB;
2570 for (i = 0; i < count; ++i)
2571 if (Dest == CasesBits[i].BB)
2575 assert((count < 3) && "Too much destinations to test!");
2576 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2580 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2581 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2583 uint64_t lo = (lowValue - lowBound).getZExtValue();
2584 uint64_t hi = (highValue - lowBound).getZExtValue();
2585 CasesBits[i].ExtraWeight += I->ExtraWeight;
2587 for (uint64_t j = lo; j <= hi; j++) {
2588 CasesBits[i].Mask |= 1ULL << j;
2589 CasesBits[i].Bits++;
2593 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2597 // Figure out which block is immediately after the current one.
2598 MachineFunction::iterator BBI = CR.CaseBB;
2601 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2603 DEBUG(dbgs() << "Cases:\n");
2604 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2605 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2606 << ", Bits: " << CasesBits[i].Bits
2607 << ", BB: " << CasesBits[i].BB << '\n');
2609 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2610 CurMF->insert(BBI, CaseBB);
2611 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2613 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2615 // Put SV in a virtual register to make it available from the new blocks.
2616 ExportFromCurrentBlock(SV);
2619 BitTestBlock BTB(lowBound, cmpRange, SV,
2620 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2621 CR.CaseBB, Default, std::move(BTC));
2623 if (CR.CaseBB == SwitchBB)
2624 visitBitTestHeader(BTB, SwitchBB);
2626 BitTestCases.push_back(std::move(BTB));
2631 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2632 void SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2633 const SwitchInst& SI) {
2634 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2635 // Start with "simple" cases.
2636 for (SwitchInst::ConstCaseIt i : SI.cases()) {
2637 const BasicBlock *SuccBB = i.getCaseSuccessor();
2638 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2640 uint32_t ExtraWeight =
2641 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2643 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2644 SMBB, ExtraWeight));
2646 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2648 // Merge case into clusters
2649 if (Cases.size() >= 2)
2650 // Must recompute end() each iteration because it may be
2651 // invalidated by erase if we hold on to it
2652 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2653 J != Cases.end(); ) {
2654 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2655 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2656 MachineBasicBlock* nextBB = J->BB;
2657 MachineBasicBlock* currentBB = I->BB;
2659 // If the two neighboring cases go to the same destination, merge them
2660 // into a single case.
2661 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2663 I->ExtraWeight += J->ExtraWeight;
2672 for (auto &I : Cases)
2673 // A range counts double, since it requires two compares.
2674 numCmps += I.Low != I.High ? 2 : 1;
2676 dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2677 << ". Total compares: " << numCmps << '\n';
2681 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2682 MachineBasicBlock *Last) {
2684 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2685 if (JTCases[i].first.HeaderBB == First)
2686 JTCases[i].first.HeaderBB = Last;
2688 // Update BitTestCases.
2689 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2690 if (BitTestCases[i].Parent == First)
2691 BitTestCases[i].Parent = Last;
2694 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2695 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2697 // Figure out which block is immediately after the current one.
2698 MachineBasicBlock *NextBlock = nullptr;
2699 if (SwitchMBB + 1 != FuncInfo.MF->end())
2700 NextBlock = SwitchMBB + 1;
2703 // Create a vector of Cases, sorted so that we can efficiently create a binary
2704 // search tree from them.
2706 Clusterify(Cases, SI);
2708 // Get the default destination MBB.
2709 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2711 if (isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg()) &&
2713 // Replace an unreachable default destination with the most popular case
2715 DenseMap<const BasicBlock *, uint64_t> Popularity;
2716 uint64_t MaxPop = 0;
2717 const BasicBlock *MaxBB = nullptr;
2718 for (auto I : SI.cases()) {
2719 const BasicBlock *BB = I.getCaseSuccessor();
2720 if (++Popularity[BB] > MaxPop) {
2721 MaxPop = Popularity[BB];
2729 Default = FuncInfo.MBBMap[MaxBB];
2731 // Remove cases that were pointing to the destination that is now the default.
2732 Cases.erase(std::remove_if(Cases.begin(), Cases.end(),
2733 [&](const Case &C) { return C.BB == Default; }),
2737 // If there is only the default destination, go there directly.
2738 if (Cases.empty()) {
2739 // Update machine-CFG edges.
2740 SwitchMBB->addSuccessor(Default);
2742 // If this is not a fall-through branch, emit the branch.
2743 if (Default != NextBlock) {
2744 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2745 getControlRoot(), DAG.getBasicBlock(Default)));
2750 // Get the Value to be switched on.
2751 const Value *SV = SI.getCondition();
2753 // Push the initial CaseRec onto the worklist
2754 CaseRecVector WorkList;
2755 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2756 CaseRange(Cases.begin(),Cases.end())));
2758 while (!WorkList.empty()) {
2759 // Grab a record representing a case range to process off the worklist
2760 CaseRec CR = WorkList.back();
2761 WorkList.pop_back();
2763 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2766 // If the range has few cases (two or less) emit a series of specific
2768 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2771 // If the switch has more than N blocks, and is at least 40% dense, and the
2772 // target supports indirect branches, then emit a jump table rather than
2773 // lowering the switch to a binary tree of conditional branches.
2774 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2775 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2778 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2779 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2780 handleBTSplitSwitchCase(CR, WorkList, SV, SwitchMBB);
2784 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2785 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2787 // Update machine-CFG edges with unique successors.
2788 SmallSet<BasicBlock*, 32> Done;
2789 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2790 BasicBlock *BB = I.getSuccessor(i);
2791 bool Inserted = Done.insert(BB).second;
2795 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2796 addSuccessorWithWeight(IndirectBrMBB, Succ);
2799 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2800 MVT::Other, getControlRoot(),
2801 getValue(I.getAddress())));
2804 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2805 if (DAG.getTarget().Options.TrapUnreachable)
2806 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2809 void SelectionDAGBuilder::visitFSub(const User &I) {
2810 // -0.0 - X --> fneg
2811 Type *Ty = I.getType();
2812 if (isa<Constant>(I.getOperand(0)) &&
2813 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2814 SDValue Op2 = getValue(I.getOperand(1));
2815 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2816 Op2.getValueType(), Op2));
2820 visitBinary(I, ISD::FSUB);
2823 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2824 SDValue Op1 = getValue(I.getOperand(0));
2825 SDValue Op2 = getValue(I.getOperand(1));
2830 if (const OverflowingBinaryOperator *OFBinOp =
2831 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2832 nuw = OFBinOp->hasNoUnsignedWrap();
2833 nsw = OFBinOp->hasNoSignedWrap();
2835 if (const PossiblyExactOperator *ExactOp =
2836 dyn_cast<const PossiblyExactOperator>(&I))
2837 exact = ExactOp->isExact();
2839 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2840 Op1, Op2, nuw, nsw, exact);
2841 setValue(&I, BinNodeValue);
2844 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2845 SDValue Op1 = getValue(I.getOperand(0));
2846 SDValue Op2 = getValue(I.getOperand(1));
2849 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2851 // Coerce the shift amount to the right type if we can.
2852 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2853 unsigned ShiftSize = ShiftTy.getSizeInBits();
2854 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2855 SDLoc DL = getCurSDLoc();
2857 // If the operand is smaller than the shift count type, promote it.
2858 if (ShiftSize > Op2Size)
2859 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2861 // If the operand is larger than the shift count type but the shift
2862 // count type has enough bits to represent any shift value, truncate
2863 // it now. This is a common case and it exposes the truncate to
2864 // optimization early.
2865 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2866 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2867 // Otherwise we'll need to temporarily settle for some other convenient
2868 // type. Type legalization will make adjustments once the shiftee is split.
2870 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2877 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2879 if (const OverflowingBinaryOperator *OFBinOp =
2880 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2881 nuw = OFBinOp->hasNoUnsignedWrap();
2882 nsw = OFBinOp->hasNoSignedWrap();
2884 if (const PossiblyExactOperator *ExactOp =
2885 dyn_cast<const PossiblyExactOperator>(&I))
2886 exact = ExactOp->isExact();
2889 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2894 void SelectionDAGBuilder::visitSDiv(const User &I) {
2895 SDValue Op1 = getValue(I.getOperand(0));
2896 SDValue Op2 = getValue(I.getOperand(1));
2898 // Turn exact SDivs into multiplications.
2899 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2901 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2902 !isa<ConstantSDNode>(Op1) &&
2903 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2904 setValue(&I, DAG.getTargetLoweringInfo()
2905 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2907 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2911 void SelectionDAGBuilder::visitICmp(const User &I) {
2912 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2913 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2914 predicate = IC->getPredicate();
2915 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2916 predicate = ICmpInst::Predicate(IC->getPredicate());
2917 SDValue Op1 = getValue(I.getOperand(0));
2918 SDValue Op2 = getValue(I.getOperand(1));
2919 ISD::CondCode Opcode = getICmpCondCode(predicate);
2921 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2922 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2925 void SelectionDAGBuilder::visitFCmp(const User &I) {
2926 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2927 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2928 predicate = FC->getPredicate();
2929 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2930 predicate = FCmpInst::Predicate(FC->getPredicate());
2931 SDValue Op1 = getValue(I.getOperand(0));
2932 SDValue Op2 = getValue(I.getOperand(1));
2933 ISD::CondCode Condition = getFCmpCondCode(predicate);
2934 if (TM.Options.NoNaNsFPMath)
2935 Condition = getFCmpCodeWithoutNaN(Condition);
2936 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2937 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2940 void SelectionDAGBuilder::visitSelect(const User &I) {
2941 SmallVector<EVT, 4> ValueVTs;
2942 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2943 unsigned NumValues = ValueVTs.size();
2944 if (NumValues == 0) return;
2946 SmallVector<SDValue, 4> Values(NumValues);
2947 SDValue Cond = getValue(I.getOperand(0));
2948 SDValue TrueVal = getValue(I.getOperand(1));
2949 SDValue FalseVal = getValue(I.getOperand(2));
2950 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2951 ISD::VSELECT : ISD::SELECT;
2953 for (unsigned i = 0; i != NumValues; ++i)
2954 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2955 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2957 SDValue(TrueVal.getNode(),
2958 TrueVal.getResNo() + i),
2959 SDValue(FalseVal.getNode(),
2960 FalseVal.getResNo() + i));
2962 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2963 DAG.getVTList(ValueVTs), Values));
2966 void SelectionDAGBuilder::visitTrunc(const User &I) {
2967 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2968 SDValue N = getValue(I.getOperand(0));
2969 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2970 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2973 void SelectionDAGBuilder::visitZExt(const User &I) {
2974 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2975 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2976 SDValue N = getValue(I.getOperand(0));
2977 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2978 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2981 void SelectionDAGBuilder::visitSExt(const User &I) {
2982 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2983 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2984 SDValue N = getValue(I.getOperand(0));
2985 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2986 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2989 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2990 // FPTrunc is never a no-op cast, no need to check
2991 SDValue N = getValue(I.getOperand(0));
2992 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2993 EVT DestVT = TLI.getValueType(I.getType());
2994 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
2995 DAG.getTargetConstant(0, TLI.getPointerTy())));
2998 void SelectionDAGBuilder::visitFPExt(const User &I) {
2999 // FPExt is never a no-op cast, no need to check
3000 SDValue N = getValue(I.getOperand(0));
3001 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3002 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3005 void SelectionDAGBuilder::visitFPToUI(const User &I) {
3006 // FPToUI is never a no-op cast, no need to check
3007 SDValue N = getValue(I.getOperand(0));
3008 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3009 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3012 void SelectionDAGBuilder::visitFPToSI(const User &I) {
3013 // FPToSI is never a no-op cast, no need to check
3014 SDValue N = getValue(I.getOperand(0));
3015 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3016 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3019 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3020 // UIToFP is never a no-op cast, no need to check
3021 SDValue N = getValue(I.getOperand(0));
3022 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3023 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3026 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3027 // SIToFP is never a no-op cast, no need to check
3028 SDValue N = getValue(I.getOperand(0));
3029 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3030 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3033 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3034 // What to do depends on the size of the integer and the size of the pointer.
3035 // We can either truncate, zero extend, or no-op, accordingly.
3036 SDValue N = getValue(I.getOperand(0));
3037 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3038 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3041 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3042 // What to do depends on the size of the integer and the size of the pointer.
3043 // We can either truncate, zero extend, or no-op, accordingly.
3044 SDValue N = getValue(I.getOperand(0));
3045 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3046 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3049 void SelectionDAGBuilder::visitBitCast(const User &I) {
3050 SDValue N = getValue(I.getOperand(0));
3051 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3053 // BitCast assures us that source and destination are the same size so this is
3054 // either a BITCAST or a no-op.
3055 if (DestVT != N.getValueType())
3056 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3057 DestVT, N)); // convert types.
3058 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3059 // might fold any kind of constant expression to an integer constant and that
3060 // is not what we are looking for. Only regcognize a bitcast of a genuine
3061 // constant integer as an opaque constant.
3062 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3063 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3066 setValue(&I, N); // noop cast.
3069 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3070 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3071 const Value *SV = I.getOperand(0);
3072 SDValue N = getValue(SV);
3073 EVT DestVT = TLI.getValueType(I.getType());
3075 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3076 unsigned DestAS = I.getType()->getPointerAddressSpace();
3078 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3079 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3084 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3085 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3086 SDValue InVec = getValue(I.getOperand(0));
3087 SDValue InVal = getValue(I.getOperand(1));
3088 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3089 getCurSDLoc(), TLI.getVectorIdxTy());
3090 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3091 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
3094 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3095 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3096 SDValue InVec = getValue(I.getOperand(0));
3097 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3098 getCurSDLoc(), TLI.getVectorIdxTy());
3099 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3100 TLI.getValueType(I.getType()), InVec, InIdx));
3103 // Utility for visitShuffleVector - Return true if every element in Mask,
3104 // beginning from position Pos and ending in Pos+Size, falls within the
3105 // specified sequential range [L, L+Pos). or is undef.
3106 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3107 unsigned Pos, unsigned Size, int Low) {
3108 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3109 if (Mask[i] >= 0 && Mask[i] != Low)
3114 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3115 SDValue Src1 = getValue(I.getOperand(0));
3116 SDValue Src2 = getValue(I.getOperand(1));
3118 SmallVector<int, 8> Mask;
3119 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3120 unsigned MaskNumElts = Mask.size();
3122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3123 EVT VT = TLI.getValueType(I.getType());
3124 EVT SrcVT = Src1.getValueType();
3125 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3127 if (SrcNumElts == MaskNumElts) {
3128 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3133 // Normalize the shuffle vector since mask and vector length don't match.
3134 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3135 // Mask is longer than the source vectors and is a multiple of the source
3136 // vectors. We can use concatenate vector to make the mask and vectors
3138 if (SrcNumElts*2 == MaskNumElts) {
3139 // First check for Src1 in low and Src2 in high
3140 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3141 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3142 // The shuffle is concatenating two vectors together.
3143 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3147 // Then check for Src2 in low and Src1 in high
3148 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3149 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3150 // The shuffle is concatenating two vectors together.
3151 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3157 // Pad both vectors with undefs to make them the same length as the mask.
3158 unsigned NumConcat = MaskNumElts / SrcNumElts;
3159 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3160 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3161 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3163 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3164 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3168 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3169 getCurSDLoc(), VT, MOps1);
3170 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3171 getCurSDLoc(), VT, MOps2);
3173 // Readjust mask for new input vector length.
3174 SmallVector<int, 8> MappedOps;
3175 for (unsigned i = 0; i != MaskNumElts; ++i) {
3177 if (Idx >= (int)SrcNumElts)
3178 Idx -= SrcNumElts - MaskNumElts;
3179 MappedOps.push_back(Idx);
3182 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3187 if (SrcNumElts > MaskNumElts) {
3188 // Analyze the access pattern of the vector to see if we can extract
3189 // two subvectors and do the shuffle. The analysis is done by calculating
3190 // the range of elements the mask access on both vectors.
3191 int MinRange[2] = { static_cast<int>(SrcNumElts),
3192 static_cast<int>(SrcNumElts)};
3193 int MaxRange[2] = {-1, -1};
3195 for (unsigned i = 0; i != MaskNumElts; ++i) {
3201 if (Idx >= (int)SrcNumElts) {
3205 if (Idx > MaxRange[Input])
3206 MaxRange[Input] = Idx;
3207 if (Idx < MinRange[Input])
3208 MinRange[Input] = Idx;
3211 // Check if the access is smaller than the vector size and can we find
3212 // a reasonable extract index.
3213 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3215 int StartIdx[2]; // StartIdx to extract from
3216 for (unsigned Input = 0; Input < 2; ++Input) {
3217 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3218 RangeUse[Input] = 0; // Unused
3219 StartIdx[Input] = 0;
3223 // Find a good start index that is a multiple of the mask length. Then
3224 // see if the rest of the elements are in range.
3225 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3226 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3227 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3228 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3231 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3232 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3235 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3236 // Extract appropriate subvector and generate a vector shuffle
3237 for (unsigned Input = 0; Input < 2; ++Input) {
3238 SDValue &Src = Input == 0 ? Src1 : Src2;
3239 if (RangeUse[Input] == 0)
3240 Src = DAG.getUNDEF(VT);
3243 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
3244 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
3247 // Calculate new mask.
3248 SmallVector<int, 8> MappedOps;
3249 for (unsigned i = 0; i != MaskNumElts; ++i) {
3252 if (Idx < (int)SrcNumElts)
3255 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3257 MappedOps.push_back(Idx);
3260 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3266 // We can't use either concat vectors or extract subvectors so fall back to
3267 // replacing the shuffle with extract and build vector.
3268 // to insert and build vector.
3269 EVT EltVT = VT.getVectorElementType();
3270 EVT IdxVT = TLI.getVectorIdxTy();
3271 SmallVector<SDValue,8> Ops;
3272 for (unsigned i = 0; i != MaskNumElts; ++i) {
3277 Res = DAG.getUNDEF(EltVT);
3279 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3280 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3282 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3283 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3289 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3292 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3293 const Value *Op0 = I.getOperand(0);
3294 const Value *Op1 = I.getOperand(1);
3295 Type *AggTy = I.getType();
3296 Type *ValTy = Op1->getType();
3297 bool IntoUndef = isa<UndefValue>(Op0);
3298 bool FromUndef = isa<UndefValue>(Op1);
3300 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3302 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3303 SmallVector<EVT, 4> AggValueVTs;
3304 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3305 SmallVector<EVT, 4> ValValueVTs;
3306 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3308 unsigned NumAggValues = AggValueVTs.size();
3309 unsigned NumValValues = ValValueVTs.size();
3310 SmallVector<SDValue, 4> Values(NumAggValues);
3312 // Ignore an insertvalue that produces an empty object
3313 if (!NumAggValues) {
3314 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3318 SDValue Agg = getValue(Op0);
3320 // Copy the beginning value(s) from the original aggregate.
3321 for (; i != LinearIndex; ++i)
3322 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3323 SDValue(Agg.getNode(), Agg.getResNo() + i);
3324 // Copy values from the inserted value(s).
3326 SDValue Val = getValue(Op1);
3327 for (; i != LinearIndex + NumValValues; ++i)
3328 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3329 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3331 // Copy remaining value(s) from the original aggregate.
3332 for (; i != NumAggValues; ++i)
3333 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3334 SDValue(Agg.getNode(), Agg.getResNo() + i);
3336 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3337 DAG.getVTList(AggValueVTs), Values));
3340 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3341 const Value *Op0 = I.getOperand(0);
3342 Type *AggTy = Op0->getType();
3343 Type *ValTy = I.getType();
3344 bool OutOfUndef = isa<UndefValue>(Op0);
3346 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3348 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3349 SmallVector<EVT, 4> ValValueVTs;
3350 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3352 unsigned NumValValues = ValValueVTs.size();
3354 // Ignore a extractvalue that produces an empty object
3355 if (!NumValValues) {
3356 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3360 SmallVector<SDValue, 4> Values(NumValValues);
3362 SDValue Agg = getValue(Op0);
3363 // Copy out the selected value(s).
3364 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3365 Values[i - LinearIndex] =
3367 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3368 SDValue(Agg.getNode(), Agg.getResNo() + i);
3370 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3371 DAG.getVTList(ValValueVTs), Values));
3374 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3375 Value *Op0 = I.getOperand(0);
3376 // Note that the pointer operand may be a vector of pointers. Take the scalar
3377 // element which holds a pointer.
3378 Type *Ty = Op0->getType()->getScalarType();
3379 unsigned AS = Ty->getPointerAddressSpace();
3380 SDValue N = getValue(Op0);
3382 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3384 const Value *Idx = *OI;
3385 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3386 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3389 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3390 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3391 DAG.getConstant(Offset, N.getValueType()));
3394 Ty = StTy->getElementType(Field);
3396 Ty = cast<SequentialType>(Ty)->getElementType();
3398 // If this is a constant subscript, handle it quickly.
3399 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3400 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3401 if (CI->isZero()) continue;
3403 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3405 EVT PTy = TLI.getPointerTy(AS);
3406 unsigned PtrBits = PTy.getSizeInBits();
3408 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3409 DAG.getConstant(Offs, MVT::i64));
3411 OffsVal = DAG.getConstant(Offs, PTy);
3413 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3418 // N = N + Idx * ElementSize;
3420 APInt(TLI.getPointerSizeInBits(AS), DL->getTypeAllocSize(Ty));
3421 SDValue IdxN = getValue(Idx);
3423 // If the index is smaller or larger than intptr_t, truncate or extend
3425 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3427 // If this is a multiply by a power of two, turn it into a shl
3428 // immediately. This is a very common case.
3429 if (ElementSize != 1) {
3430 if (ElementSize.isPowerOf2()) {
3431 unsigned Amt = ElementSize.logBase2();
3432 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3433 N.getValueType(), IdxN,
3434 DAG.getConstant(Amt, IdxN.getValueType()));
3436 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3437 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3438 N.getValueType(), IdxN, Scale);
3442 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3443 N.getValueType(), N, IdxN);
3450 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3451 // If this is a fixed sized alloca in the entry block of the function,
3452 // allocate it statically on the stack.
3453 if (FuncInfo.StaticAllocaMap.count(&I))
3454 return; // getValue will auto-populate this.
3456 Type *Ty = I.getAllocatedType();
3457 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3458 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3460 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3463 SDValue AllocSize = getValue(I.getArraySize());
3465 EVT IntPtr = TLI.getPointerTy();
3466 if (AllocSize.getValueType() != IntPtr)
3467 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3469 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3471 DAG.getConstant(TySize, IntPtr));
3473 // Handle alignment. If the requested alignment is less than or equal to
3474 // the stack alignment, ignore it. If the size is greater than or equal to
3475 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3476 unsigned StackAlign =
3477 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3478 if (Align <= StackAlign)
3481 // Round the size of the allocation up to the stack alignment size
3482 // by add SA-1 to the size.
3483 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3484 AllocSize.getValueType(), AllocSize,
3485 DAG.getIntPtrConstant(StackAlign-1));
3487 // Mask out the low bits for alignment purposes.
3488 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3489 AllocSize.getValueType(), AllocSize,
3490 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3492 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3493 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3494 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3496 DAG.setRoot(DSA.getValue(1));
3498 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3501 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3503 return visitAtomicLoad(I);
3505 const Value *SV = I.getOperand(0);
3506 SDValue Ptr = getValue(SV);
3508 Type *Ty = I.getType();
3510 bool isVolatile = I.isVolatile();
3511 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3512 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3513 unsigned Alignment = I.getAlignment();
3516 I.getAAMetadata(AAInfo);
3517 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3519 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3520 SmallVector<EVT, 4> ValueVTs;
3521 SmallVector<uint64_t, 4> Offsets;
3522 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3523 unsigned NumValues = ValueVTs.size();
3528 bool ConstantMemory = false;
3529 if (isVolatile || NumValues > MaxParallelChains)
3530 // Serialize volatile loads with other side effects.
3532 else if (AA->pointsToConstantMemory(
3533 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3534 // Do not serialize (non-volatile) loads of constant memory with anything.
3535 Root = DAG.getEntryNode();
3536 ConstantMemory = true;
3538 // Do not serialize non-volatile loads against each other.
3539 Root = DAG.getRoot();
3543 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3545 SmallVector<SDValue, 4> Values(NumValues);
3546 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3548 EVT PtrVT = Ptr.getValueType();
3549 unsigned ChainI = 0;
3550 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3551 // Serializing loads here may result in excessive register pressure, and
3552 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3553 // could recover a bit by hoisting nodes upward in the chain by recognizing
3554 // they are side-effect free or do not alias. The optimizer should really
3555 // avoid this case by converting large object/array copies to llvm.memcpy
3556 // (MaxParallelChains should always remain as failsafe).
3557 if (ChainI == MaxParallelChains) {
3558 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3559 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3560 makeArrayRef(Chains.data(), ChainI));
3564 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3566 DAG.getConstant(Offsets[i], PtrVT));
3567 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3568 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3569 isNonTemporal, isInvariant, Alignment, AAInfo,
3573 Chains[ChainI] = L.getValue(1);
3576 if (!ConstantMemory) {
3577 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3578 makeArrayRef(Chains.data(), ChainI));
3582 PendingLoads.push_back(Chain);
3585 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3586 DAG.getVTList(ValueVTs), Values));
3589 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3591 return visitAtomicStore(I);
3593 const Value *SrcV = I.getOperand(0);
3594 const Value *PtrV = I.getOperand(1);
3596 SmallVector<EVT, 4> ValueVTs;
3597 SmallVector<uint64_t, 4> Offsets;
3598 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
3599 ValueVTs, &Offsets);
3600 unsigned NumValues = ValueVTs.size();
3604 // Get the lowered operands. Note that we do this after
3605 // checking if NumResults is zero, because with zero results
3606 // the operands won't have values in the map.
3607 SDValue Src = getValue(SrcV);
3608 SDValue Ptr = getValue(PtrV);
3610 SDValue Root = getRoot();
3611 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3613 EVT PtrVT = Ptr.getValueType();
3614 bool isVolatile = I.isVolatile();
3615 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3616 unsigned Alignment = I.getAlignment();
3619 I.getAAMetadata(AAInfo);
3621 unsigned ChainI = 0;
3622 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3623 // See visitLoad comments.
3624 if (ChainI == MaxParallelChains) {
3625 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3626 makeArrayRef(Chains.data(), ChainI));
3630 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3631 DAG.getConstant(Offsets[i], PtrVT));
3632 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3633 SDValue(Src.getNode(), Src.getResNo() + i),
3634 Add, MachinePointerInfo(PtrV, Offsets[i]),
3635 isVolatile, isNonTemporal, Alignment, AAInfo);
3636 Chains[ChainI] = St;
3639 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3640 makeArrayRef(Chains.data(), ChainI));
3641 DAG.setRoot(StoreNode);
3644 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3645 SDLoc sdl = getCurSDLoc();
3647 Value *PtrOperand = I.getArgOperand(0);
3648 SDValue Ptr = getValue(PtrOperand);
3649 SDValue Src0 = getValue(I.getArgOperand(1));
3650 SDValue Mask = getValue(I.getArgOperand(3));
3651 EVT VT = Src0.getValueType();
3652 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3654 Alignment = DAG.getEVTAlignment(VT);
3657 I.getAAMetadata(AAInfo);
3659 MachineMemOperand *MMO =
3660 DAG.getMachineFunction().
3661 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3662 MachineMemOperand::MOStore, VT.getStoreSize(),
3664 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, MMO);
3665 DAG.setRoot(StoreNode);
3666 setValue(&I, StoreNode);
3669 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3670 SDLoc sdl = getCurSDLoc();
3672 Value *PtrOperand = I.getArgOperand(0);
3673 SDValue Ptr = getValue(PtrOperand);
3674 SDValue Src0 = getValue(I.getArgOperand(1));
3675 SDValue Mask = getValue(I.getArgOperand(3));
3677 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3678 EVT VT = TLI.getValueType(I.getType());
3679 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3681 Alignment = DAG.getEVTAlignment(VT);
3684 I.getAAMetadata(AAInfo);
3685 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3687 SDValue InChain = DAG.getRoot();
3688 if (AA->pointsToConstantMemory(
3689 AliasAnalysis::Location(PtrOperand,
3690 AA->getTypeStoreSize(I.getType()),
3692 // Do not serialize (non-volatile) loads of constant memory with anything.
3693 InChain = DAG.getEntryNode();
3696 MachineMemOperand *MMO =
3697 DAG.getMachineFunction().
3698 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3699 MachineMemOperand::MOLoad, VT.getStoreSize(),
3700 Alignment, AAInfo, Ranges);
3702 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, MMO);
3703 SDValue OutChain = Load.getValue(1);
3704 DAG.setRoot(OutChain);
3708 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3709 SDLoc dl = getCurSDLoc();
3710 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3711 AtomicOrdering FailureOrder = I.getFailureOrdering();
3712 SynchronizationScope Scope = I.getSynchScope();
3714 SDValue InChain = getRoot();
3716 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3717 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3718 SDValue L = DAG.getAtomicCmpSwap(
3719 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3720 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3721 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3722 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3724 SDValue OutChain = L.getValue(2);
3727 DAG.setRoot(OutChain);
3730 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3731 SDLoc dl = getCurSDLoc();
3733 switch (I.getOperation()) {
3734 default: llvm_unreachable("Unknown atomicrmw operation");
3735 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3736 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3737 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3738 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3739 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3740 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3741 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3742 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3743 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3744 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3745 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3747 AtomicOrdering Order = I.getOrdering();
3748 SynchronizationScope Scope = I.getSynchScope();
3750 SDValue InChain = getRoot();
3753 DAG.getAtomic(NT, dl,
3754 getValue(I.getValOperand()).getSimpleValueType(),
3756 getValue(I.getPointerOperand()),
3757 getValue(I.getValOperand()),
3758 I.getPointerOperand(),
3759 /* Alignment=*/ 0, Order, Scope);
3761 SDValue OutChain = L.getValue(1);
3764 DAG.setRoot(OutChain);
3767 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3768 SDLoc dl = getCurSDLoc();
3769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3772 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3773 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3774 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3777 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3778 SDLoc dl = getCurSDLoc();
3779 AtomicOrdering Order = I.getOrdering();
3780 SynchronizationScope Scope = I.getSynchScope();
3782 SDValue InChain = getRoot();
3784 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3785 EVT VT = TLI.getValueType(I.getType());
3787 if (I.getAlignment() < VT.getSizeInBits() / 8)
3788 report_fatal_error("Cannot generate unaligned atomic load");
3790 MachineMemOperand *MMO =
3791 DAG.getMachineFunction().
3792 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3793 MachineMemOperand::MOVolatile |
3794 MachineMemOperand::MOLoad,
3796 I.getAlignment() ? I.getAlignment() :
3797 DAG.getEVTAlignment(VT));
3799 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3801 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3802 getValue(I.getPointerOperand()), MMO,
3805 SDValue OutChain = L.getValue(1);
3808 DAG.setRoot(OutChain);
3811 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3812 SDLoc dl = getCurSDLoc();
3814 AtomicOrdering Order = I.getOrdering();
3815 SynchronizationScope Scope = I.getSynchScope();
3817 SDValue InChain = getRoot();
3819 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3820 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3822 if (I.getAlignment() < VT.getSizeInBits() / 8)
3823 report_fatal_error("Cannot generate unaligned atomic store");
3826 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3828 getValue(I.getPointerOperand()),
3829 getValue(I.getValueOperand()),
3830 I.getPointerOperand(), I.getAlignment(),
3833 DAG.setRoot(OutChain);
3836 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3838 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3839 unsigned Intrinsic) {
3840 bool HasChain = !I.doesNotAccessMemory();
3841 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3843 // Build the operand list.
3844 SmallVector<SDValue, 8> Ops;
3845 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3847 // We don't need to serialize loads against other loads.
3848 Ops.push_back(DAG.getRoot());
3850 Ops.push_back(getRoot());
3854 // Info is set by getTgtMemInstrinsic
3855 TargetLowering::IntrinsicInfo Info;
3856 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3857 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3859 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3860 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3861 Info.opc == ISD::INTRINSIC_W_CHAIN)
3862 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3864 // Add all operands of the call to the operand list.
3865 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3866 SDValue Op = getValue(I.getArgOperand(i));
3870 SmallVector<EVT, 4> ValueVTs;
3871 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3874 ValueVTs.push_back(MVT::Other);
3876 SDVTList VTs = DAG.getVTList(ValueVTs);
3880 if (IsTgtIntrinsic) {
3881 // This is target intrinsic that touches memory
3882 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3883 VTs, Ops, Info.memVT,
3884 MachinePointerInfo(Info.ptrVal, Info.offset),
3885 Info.align, Info.vol,
3886 Info.readMem, Info.writeMem, Info.size);
3887 } else if (!HasChain) {
3888 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3889 } else if (!I.getType()->isVoidTy()) {
3890 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3892 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3896 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3898 PendingLoads.push_back(Chain);
3903 if (!I.getType()->isVoidTy()) {
3904 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3905 EVT VT = TLI.getValueType(PTy);
3906 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3909 setValue(&I, Result);
3913 /// GetSignificand - Get the significand and build it into a floating-point
3914 /// number with exponent of 1:
3916 /// Op = (Op & 0x007fffff) | 0x3f800000;
3918 /// where Op is the hexadecimal representation of floating point value.
3920 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3921 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3922 DAG.getConstant(0x007fffff, MVT::i32));
3923 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3924 DAG.getConstant(0x3f800000, MVT::i32));
3925 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3928 /// GetExponent - Get the exponent:
3930 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3932 /// where Op is the hexadecimal representation of floating point value.
3934 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3936 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3937 DAG.getConstant(0x7f800000, MVT::i32));
3938 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3939 DAG.getConstant(23, TLI.getPointerTy()));
3940 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3941 DAG.getConstant(127, MVT::i32));
3942 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3945 /// getF32Constant - Get 32-bit floating point constant.
3947 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3948 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3952 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3953 /// limited-precision mode.
3954 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3955 const TargetLowering &TLI) {
3956 if (Op.getValueType() == MVT::f32 &&
3957 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3959 // Put the exponent in the right bit position for later addition to the
3962 // #define LOG2OFe 1.4426950f
3963 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3964 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3965 getF32Constant(DAG, 0x3fb8aa3b));
3966 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3968 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3969 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3970 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3972 // IntegerPartOfX <<= 23;
3973 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3974 DAG.getConstant(23, TLI.getPointerTy()));
3976 SDValue TwoToFracPartOfX;
3977 if (LimitFloatPrecision <= 6) {
3978 // For floating-point precision of 6:
3980 // TwoToFractionalPartOfX =
3982 // (0.735607626f + 0.252464424f * x) * x;
3984 // error 0.0144103317, which is 6 bits
3985 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3986 getF32Constant(DAG, 0x3e814304));
3987 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3988 getF32Constant(DAG, 0x3f3c50c8));
3989 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3990 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3991 getF32Constant(DAG, 0x3f7f5e7e));
3992 } else if (LimitFloatPrecision <= 12) {
3993 // For floating-point precision of 12:
3995 // TwoToFractionalPartOfX =
3998 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4000 // 0.000107046256 error, which is 13 to 14 bits
4001 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4002 getF32Constant(DAG, 0x3da235e3));
4003 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4004 getF32Constant(DAG, 0x3e65b8f3));
4005 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4006 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4007 getF32Constant(DAG, 0x3f324b07));
4008 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4009 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4010 getF32Constant(DAG, 0x3f7ff8fd));
4011 } else { // LimitFloatPrecision <= 18
4012 // For floating-point precision of 18:
4014 // TwoToFractionalPartOfX =
4018 // (0.554906021e-1f +
4019 // (0.961591928e-2f +
4020 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4022 // error 2.47208000*10^(-7), which is better than 18 bits
4023 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4024 getF32Constant(DAG, 0x3924b03e));
4025 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4026 getF32Constant(DAG, 0x3ab24b87));
4027 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4028 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4029 getF32Constant(DAG, 0x3c1d8c17));
4030 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4031 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4032 getF32Constant(DAG, 0x3d634a1d));
4033 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4034 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4035 getF32Constant(DAG, 0x3e75fe14));
4036 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4037 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4038 getF32Constant(DAG, 0x3f317234));
4039 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4040 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4041 getF32Constant(DAG, 0x3f800000));
4044 // Add the exponent into the result in integer domain.
4045 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
4046 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4047 DAG.getNode(ISD::ADD, dl, MVT::i32,
4048 t13, IntegerPartOfX));
4051 // No special expansion.
4052 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4055 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4056 /// limited-precision mode.
4057 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4058 const TargetLowering &TLI) {
4059 if (Op.getValueType() == MVT::f32 &&
4060 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4061 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4063 // Scale the exponent by log(2) [0.69314718f].
4064 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4065 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4066 getF32Constant(DAG, 0x3f317218));
4068 // Get the significand and build it into a floating-point number with
4070 SDValue X = GetSignificand(DAG, Op1, dl);
4072 SDValue LogOfMantissa;
4073 if (LimitFloatPrecision <= 6) {
4074 // For floating-point precision of 6:
4078 // (1.4034025f - 0.23903021f * x) * x;
4080 // error 0.0034276066, which is better than 8 bits
4081 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4082 getF32Constant(DAG, 0xbe74c456));
4083 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4084 getF32Constant(DAG, 0x3fb3a2b1));
4085 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4086 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4087 getF32Constant(DAG, 0x3f949a29));
4088 } else if (LimitFloatPrecision <= 12) {
4089 // For floating-point precision of 12:
4095 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4097 // error 0.000061011436, which is 14 bits
4098 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4099 getF32Constant(DAG, 0xbd67b6d6));
4100 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4101 getF32Constant(DAG, 0x3ee4f4b8));
4102 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4103 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4104 getF32Constant(DAG, 0x3fbc278b));
4105 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4106 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4107 getF32Constant(DAG, 0x40348e95));
4108 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4109 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4110 getF32Constant(DAG, 0x3fdef31a));
4111 } else { // LimitFloatPrecision <= 18
4112 // For floating-point precision of 18:
4120 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4122 // error 0.0000023660568, which is better than 18 bits
4123 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4124 getF32Constant(DAG, 0xbc91e5ac));
4125 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4126 getF32Constant(DAG, 0x3e4350aa));
4127 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4128 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4129 getF32Constant(DAG, 0x3f60d3e3));
4130 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4131 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4132 getF32Constant(DAG, 0x4011cdf0));
4133 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4134 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4135 getF32Constant(DAG, 0x406cfd1c));
4136 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4137 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4138 getF32Constant(DAG, 0x408797cb));
4139 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4140 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4141 getF32Constant(DAG, 0x4006dcab));
4144 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4147 // No special expansion.
4148 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4151 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4152 /// limited-precision mode.
4153 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4154 const TargetLowering &TLI) {
4155 if (Op.getValueType() == MVT::f32 &&
4156 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4157 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4159 // Get the exponent.
4160 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4162 // Get the significand and build it into a floating-point number with
4164 SDValue X = GetSignificand(DAG, Op1, dl);
4166 // Different possible minimax approximations of significand in
4167 // floating-point for various degrees of accuracy over [1,2].
4168 SDValue Log2ofMantissa;
4169 if (LimitFloatPrecision <= 6) {
4170 // For floating-point precision of 6:
4172 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4174 // error 0.0049451742, which is more than 7 bits
4175 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4176 getF32Constant(DAG, 0xbeb08fe0));
4177 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4178 getF32Constant(DAG, 0x40019463));
4179 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4180 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4181 getF32Constant(DAG, 0x3fd6633d));
4182 } else if (LimitFloatPrecision <= 12) {
4183 // For floating-point precision of 12:
4189 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4191 // error 0.0000876136000, which is better than 13 bits
4192 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4193 getF32Constant(DAG, 0xbda7262e));
4194 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4195 getF32Constant(DAG, 0x3f25280b));
4196 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4197 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4198 getF32Constant(DAG, 0x4007b923));
4199 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4200 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4201 getF32Constant(DAG, 0x40823e2f));
4202 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4203 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4204 getF32Constant(DAG, 0x4020d29c));
4205 } else { // LimitFloatPrecision <= 18
4206 // For floating-point precision of 18:
4215 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4217 // error 0.0000018516, which is better than 18 bits
4218 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4219 getF32Constant(DAG, 0xbcd2769e));
4220 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4221 getF32Constant(DAG, 0x3e8ce0b9));
4222 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4223 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4224 getF32Constant(DAG, 0x3fa22ae7));
4225 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4226 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4227 getF32Constant(DAG, 0x40525723));
4228 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4229 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4230 getF32Constant(DAG, 0x40aaf200));
4231 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4232 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4233 getF32Constant(DAG, 0x40c39dad));
4234 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4235 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4236 getF32Constant(DAG, 0x4042902c));
4239 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4242 // No special expansion.
4243 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4246 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4247 /// limited-precision mode.
4248 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4249 const TargetLowering &TLI) {
4250 if (Op.getValueType() == MVT::f32 &&
4251 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4252 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4254 // Scale the exponent by log10(2) [0.30102999f].
4255 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4256 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4257 getF32Constant(DAG, 0x3e9a209a));
4259 // Get the significand and build it into a floating-point number with
4261 SDValue X = GetSignificand(DAG, Op1, dl);
4263 SDValue Log10ofMantissa;
4264 if (LimitFloatPrecision <= 6) {
4265 // For floating-point precision of 6:
4267 // Log10ofMantissa =
4269 // (0.60948995f - 0.10380950f * x) * x;
4271 // error 0.0014886165, which is 6 bits
4272 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4273 getF32Constant(DAG, 0xbdd49a13));
4274 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4275 getF32Constant(DAG, 0x3f1c0789));
4276 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4277 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4278 getF32Constant(DAG, 0x3f011300));
4279 } else if (LimitFloatPrecision <= 12) {
4280 // For floating-point precision of 12:
4282 // Log10ofMantissa =
4285 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4287 // error 0.00019228036, which is better than 12 bits
4288 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4289 getF32Constant(DAG, 0x3d431f31));
4290 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4291 getF32Constant(DAG, 0x3ea21fb2));
4292 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4293 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4294 getF32Constant(DAG, 0x3f6ae232));
4295 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4296 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4297 getF32Constant(DAG, 0x3f25f7c3));
4298 } else { // LimitFloatPrecision <= 18
4299 // For floating-point precision of 18:
4301 // Log10ofMantissa =
4306 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4308 // error 0.0000037995730, which is better than 18 bits
4309 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4310 getF32Constant(DAG, 0x3c5d51ce));
4311 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4312 getF32Constant(DAG, 0x3e00685a));
4313 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4314 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4315 getF32Constant(DAG, 0x3efb6798));
4316 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4317 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4318 getF32Constant(DAG, 0x3f88d192));
4319 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4320 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4321 getF32Constant(DAG, 0x3fc4316c));
4322 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4323 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4324 getF32Constant(DAG, 0x3f57ce70));
4327 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4330 // No special expansion.
4331 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4334 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4335 /// limited-precision mode.
4336 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4337 const TargetLowering &TLI) {
4338 if (Op.getValueType() == MVT::f32 &&
4339 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4340 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4342 // FractionalPartOfX = x - (float)IntegerPartOfX;
4343 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4344 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4346 // IntegerPartOfX <<= 23;
4347 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4348 DAG.getConstant(23, TLI.getPointerTy()));
4350 SDValue TwoToFractionalPartOfX;
4351 if (LimitFloatPrecision <= 6) {
4352 // For floating-point precision of 6:
4354 // TwoToFractionalPartOfX =
4356 // (0.735607626f + 0.252464424f * x) * x;
4358 // error 0.0144103317, which is 6 bits
4359 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4360 getF32Constant(DAG, 0x3e814304));
4361 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4362 getF32Constant(DAG, 0x3f3c50c8));
4363 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4364 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4365 getF32Constant(DAG, 0x3f7f5e7e));
4366 } else if (LimitFloatPrecision <= 12) {
4367 // For floating-point precision of 12:
4369 // TwoToFractionalPartOfX =
4372 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4374 // error 0.000107046256, which is 13 to 14 bits
4375 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4376 getF32Constant(DAG, 0x3da235e3));
4377 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4378 getF32Constant(DAG, 0x3e65b8f3));
4379 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4380 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4381 getF32Constant(DAG, 0x3f324b07));
4382 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4383 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4384 getF32Constant(DAG, 0x3f7ff8fd));
4385 } else { // LimitFloatPrecision <= 18
4386 // For floating-point precision of 18:
4388 // TwoToFractionalPartOfX =
4392 // (0.554906021e-1f +
4393 // (0.961591928e-2f +
4394 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4395 // error 2.47208000*10^(-7), which is better than 18 bits
4396 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4397 getF32Constant(DAG, 0x3924b03e));
4398 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4399 getF32Constant(DAG, 0x3ab24b87));
4400 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4401 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4402 getF32Constant(DAG, 0x3c1d8c17));
4403 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4404 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4405 getF32Constant(DAG, 0x3d634a1d));
4406 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4407 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4408 getF32Constant(DAG, 0x3e75fe14));
4409 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4410 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4411 getF32Constant(DAG, 0x3f317234));
4412 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4413 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4414 getF32Constant(DAG, 0x3f800000));
4417 // Add the exponent into the result in integer domain.
4418 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4419 TwoToFractionalPartOfX);
4420 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4421 DAG.getNode(ISD::ADD, dl, MVT::i32,
4422 t13, IntegerPartOfX));
4425 // No special expansion.
4426 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4429 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4430 /// limited-precision mode with x == 10.0f.
4431 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4432 SelectionDAG &DAG, const TargetLowering &TLI) {
4433 bool IsExp10 = false;
4434 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4435 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4436 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4438 IsExp10 = LHSC->isExactlyValue(Ten);
4443 // Put the exponent in the right bit position for later addition to the
4446 // #define LOG2OF10 3.3219281f
4447 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4448 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4449 getF32Constant(DAG, 0x40549a78));
4450 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4452 // FractionalPartOfX = x - (float)IntegerPartOfX;
4453 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4454 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4456 // IntegerPartOfX <<= 23;
4457 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4458 DAG.getConstant(23, TLI.getPointerTy()));
4460 SDValue TwoToFractionalPartOfX;
4461 if (LimitFloatPrecision <= 6) {
4462 // For floating-point precision of 6:
4464 // twoToFractionalPartOfX =
4466 // (0.735607626f + 0.252464424f * x) * x;
4468 // error 0.0144103317, which is 6 bits
4469 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4470 getF32Constant(DAG, 0x3e814304));
4471 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4472 getF32Constant(DAG, 0x3f3c50c8));
4473 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4474 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4475 getF32Constant(DAG, 0x3f7f5e7e));
4476 } else if (LimitFloatPrecision <= 12) {
4477 // For floating-point precision of 12:
4479 // TwoToFractionalPartOfX =
4482 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4484 // error 0.000107046256, which is 13 to 14 bits
4485 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4486 getF32Constant(DAG, 0x3da235e3));
4487 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4488 getF32Constant(DAG, 0x3e65b8f3));
4489 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4490 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4491 getF32Constant(DAG, 0x3f324b07));
4492 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4493 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4494 getF32Constant(DAG, 0x3f7ff8fd));
4495 } else { // LimitFloatPrecision <= 18
4496 // For floating-point precision of 18:
4498 // TwoToFractionalPartOfX =
4502 // (0.554906021e-1f +
4503 // (0.961591928e-2f +
4504 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4505 // error 2.47208000*10^(-7), which is better than 18 bits
4506 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4507 getF32Constant(DAG, 0x3924b03e));
4508 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4509 getF32Constant(DAG, 0x3ab24b87));
4510 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4511 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4512 getF32Constant(DAG, 0x3c1d8c17));
4513 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4514 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4515 getF32Constant(DAG, 0x3d634a1d));
4516 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4517 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4518 getF32Constant(DAG, 0x3e75fe14));
4519 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4520 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4521 getF32Constant(DAG, 0x3f317234));
4522 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4523 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4524 getF32Constant(DAG, 0x3f800000));
4527 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4528 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4529 DAG.getNode(ISD::ADD, dl, MVT::i32,
4530 t13, IntegerPartOfX));
4533 // No special expansion.
4534 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4538 /// ExpandPowI - Expand a llvm.powi intrinsic.
4539 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4540 SelectionDAG &DAG) {
4541 // If RHS is a constant, we can expand this out to a multiplication tree,
4542 // otherwise we end up lowering to a call to __powidf2 (for example). When
4543 // optimizing for size, we only want to do this if the expansion would produce
4544 // a small number of multiplies, otherwise we do the full expansion.
4545 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4546 // Get the exponent as a positive value.
4547 unsigned Val = RHSC->getSExtValue();
4548 if ((int)Val < 0) Val = -Val;
4550 // powi(x, 0) -> 1.0
4552 return DAG.getConstantFP(1.0, LHS.getValueType());
4554 const Function *F = DAG.getMachineFunction().getFunction();
4555 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4556 Attribute::OptimizeForSize) ||
4557 // If optimizing for size, don't insert too many multiplies. This
4558 // inserts up to 5 multiplies.
4559 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4560 // We use the simple binary decomposition method to generate the multiply
4561 // sequence. There are more optimal ways to do this (for example,
4562 // powi(x,15) generates one more multiply than it should), but this has
4563 // the benefit of being both really simple and much better than a libcall.
4564 SDValue Res; // Logically starts equal to 1.0
4565 SDValue CurSquare = LHS;
4569 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4571 Res = CurSquare; // 1.0*CurSquare.
4574 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4575 CurSquare, CurSquare);
4579 // If the original was negative, invert the result, producing 1/(x*x*x).
4580 if (RHSC->getSExtValue() < 0)
4581 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4582 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4587 // Otherwise, expand to a libcall.
4588 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4591 // getTruncatedArgReg - Find underlying register used for an truncated
4593 static unsigned getTruncatedArgReg(const SDValue &N) {
4594 if (N.getOpcode() != ISD::TRUNCATE)
4597 const SDValue &Ext = N.getOperand(0);
4598 if (Ext.getOpcode() == ISD::AssertZext ||
4599 Ext.getOpcode() == ISD::AssertSext) {
4600 const SDValue &CFR = Ext.getOperand(0);
4601 if (CFR.getOpcode() == ISD::CopyFromReg)
4602 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4603 if (CFR.getOpcode() == ISD::TRUNCATE)
4604 return getTruncatedArgReg(CFR);
4609 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4610 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4611 /// At the end of instruction selection, they will be inserted to the entry BB.
4612 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V,
4614 MDNode *Expr, int64_t Offset,
4617 const Argument *Arg = dyn_cast<Argument>(V);
4621 MachineFunction &MF = DAG.getMachineFunction();
4622 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4624 // Ignore inlined function arguments here.
4625 DIVariable DV(Variable);
4626 if (DV.isInlinedFnArgument(MF.getFunction()))
4629 Optional<MachineOperand> Op;
4630 // Some arguments' frame index is recorded during argument lowering.
4631 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4632 Op = MachineOperand::CreateFI(FI);
4634 if (!Op && N.getNode()) {
4636 if (N.getOpcode() == ISD::CopyFromReg)
4637 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4639 Reg = getTruncatedArgReg(N);
4640 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4641 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4642 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4647 Op = MachineOperand::CreateReg(Reg, false);
4651 // Check if ValueMap has reg number.
4652 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4653 if (VMI != FuncInfo.ValueMap.end())
4654 Op = MachineOperand::CreateReg(VMI->second, false);
4657 if (!Op && N.getNode())
4658 // Check if frame index is available.
4659 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4660 if (FrameIndexSDNode *FINode =
4661 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4662 Op = MachineOperand::CreateFI(FINode->getIndex());
4668 FuncInfo.ArgDbgValues.push_back(
4669 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE),
4670 IsIndirect, Op->getReg(), Offset, Variable, Expr));
4672 FuncInfo.ArgDbgValues.push_back(
4673 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4676 .addMetadata(Variable)
4677 .addMetadata(Expr));
4682 // VisualStudio defines setjmp as _setjmp
4683 #if defined(_MSC_VER) && defined(setjmp) && \
4684 !defined(setjmp_undefined_for_msvc)
4685 # pragma push_macro("setjmp")
4687 # define setjmp_undefined_for_msvc
4690 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4691 /// we want to emit this as a call to a named external function, return the name
4692 /// otherwise lower it and return null.
4694 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4695 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4696 SDLoc sdl = getCurSDLoc();
4697 DebugLoc dl = getCurDebugLoc();
4700 switch (Intrinsic) {
4702 // By default, turn this into a target intrinsic node.
4703 visitTargetIntrinsic(I, Intrinsic);
4705 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4706 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4707 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4708 case Intrinsic::returnaddress:
4709 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4710 getValue(I.getArgOperand(0))));
4712 case Intrinsic::frameaddress:
4713 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4714 getValue(I.getArgOperand(0))));
4716 case Intrinsic::read_register: {
4717 Value *Reg = I.getArgOperand(0);
4719 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4720 EVT VT = TLI.getValueType(I.getType());
4721 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4724 case Intrinsic::write_register: {
4725 Value *Reg = I.getArgOperand(0);
4726 Value *RegValue = I.getArgOperand(1);
4727 SDValue Chain = getValue(RegValue).getOperand(0);
4729 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4730 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4731 RegName, getValue(RegValue)));
4734 case Intrinsic::setjmp:
4735 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4736 case Intrinsic::longjmp:
4737 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4738 case Intrinsic::memcpy: {
4739 // Assert for address < 256 since we support only user defined address
4741 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4743 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4745 "Unknown address space");
4746 SDValue Op1 = getValue(I.getArgOperand(0));
4747 SDValue Op2 = getValue(I.getArgOperand(1));
4748 SDValue Op3 = getValue(I.getArgOperand(2));
4749 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4751 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4752 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4753 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4754 MachinePointerInfo(I.getArgOperand(0)),
4755 MachinePointerInfo(I.getArgOperand(1))));
4758 case Intrinsic::memset: {
4759 // Assert for address < 256 since we support only user defined address
4761 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4763 "Unknown address space");
4764 SDValue Op1 = getValue(I.getArgOperand(0));
4765 SDValue Op2 = getValue(I.getArgOperand(1));
4766 SDValue Op3 = getValue(I.getArgOperand(2));
4767 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4769 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4770 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4771 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4772 MachinePointerInfo(I.getArgOperand(0))));
4775 case Intrinsic::memmove: {
4776 // Assert for address < 256 since we support only user defined address
4778 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4780 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4782 "Unknown address space");
4783 SDValue Op1 = getValue(I.getArgOperand(0));
4784 SDValue Op2 = getValue(I.getArgOperand(1));
4785 SDValue Op3 = getValue(I.getArgOperand(2));
4786 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4788 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4789 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4790 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4791 MachinePointerInfo(I.getArgOperand(0)),
4792 MachinePointerInfo(I.getArgOperand(1))));
4795 case Intrinsic::dbg_declare: {
4796 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4797 MDNode *Variable = DI.getVariable();
4798 MDNode *Expression = DI.getExpression();
4799 const Value *Address = DI.getAddress();
4800 DIVariable DIVar(Variable);
4801 assert((!DIVar || DIVar.isVariable()) &&
4802 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4803 if (!Address || !DIVar) {
4804 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4808 // Check if address has undef value.
4809 if (isa<UndefValue>(Address) ||
4810 (Address->use_empty() && !isa<Argument>(Address))) {
4811 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4815 SDValue &N = NodeMap[Address];
4816 if (!N.getNode() && isa<Argument>(Address))
4817 // Check unused arguments map.
4818 N = UnusedArgNodeMap[Address];
4821 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4822 Address = BCI->getOperand(0);
4823 // Parameters are handled specially.
4825 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4826 isa<Argument>(Address));
4828 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4830 if (isParameter && !AI) {
4831 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4833 // Byval parameter. We have a frame index at this point.
4834 SDV = DAG.getFrameIndexDbgValue(
4835 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4837 // Address is an argument, so try to emit its dbg value using
4838 // virtual register info from the FuncInfo.ValueMap.
4839 EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false, N);
4843 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4844 true, 0, dl, SDNodeOrder);
4846 // Can't do anything with other non-AI cases yet.
4847 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4848 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4849 DEBUG(Address->dump());
4852 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4854 // If Address is an argument then try to emit its dbg value using
4855 // virtual register info from the FuncInfo.ValueMap.
4856 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false,
4858 // If variable is pinned by a alloca in dominating bb then
4859 // use StaticAllocaMap.
4860 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4861 if (AI->getParent() != DI.getParent()) {
4862 DenseMap<const AllocaInst*, int>::iterator SI =
4863 FuncInfo.StaticAllocaMap.find(AI);
4864 if (SI != FuncInfo.StaticAllocaMap.end()) {
4865 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4866 0, dl, SDNodeOrder);
4867 DAG.AddDbgValue(SDV, nullptr, false);
4872 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4877 case Intrinsic::dbg_value: {
4878 const DbgValueInst &DI = cast<DbgValueInst>(I);
4879 DIVariable DIVar(DI.getVariable());
4880 assert((!DIVar || DIVar.isVariable()) &&
4881 "Variable in DbgValueInst should be either null or a DIVariable.");
4885 MDNode *Variable = DI.getVariable();
4886 MDNode *Expression = DI.getExpression();
4887 uint64_t Offset = DI.getOffset();
4888 const Value *V = DI.getValue();
4893 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4894 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4896 DAG.AddDbgValue(SDV, nullptr, false);
4898 // Do not use getValue() in here; we don't want to generate code at
4899 // this point if it hasn't been done yet.
4900 SDValue N = NodeMap[V];
4901 if (!N.getNode() && isa<Argument>(V))
4902 // Check unused arguments map.
4903 N = UnusedArgNodeMap[V];
4905 // A dbg.value for an alloca is always indirect.
4906 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4907 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, Offset,
4909 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4910 IsIndirect, Offset, dl, SDNodeOrder);
4911 DAG.AddDbgValue(SDV, N.getNode(), false);
4913 } else if (!V->use_empty() ) {
4914 // Do not call getValue(V) yet, as we don't want to generate code.
4915 // Remember it for later.
4916 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4917 DanglingDebugInfoMap[V] = DDI;
4919 // We may expand this to cover more cases. One case where we have no
4920 // data available is an unreferenced parameter.
4921 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4925 // Build a debug info table entry.
4926 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4927 V = BCI->getOperand(0);
4928 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4929 // Don't handle byval struct arguments or VLAs, for example.
4931 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4932 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4935 DenseMap<const AllocaInst*, int>::iterator SI =
4936 FuncInfo.StaticAllocaMap.find(AI);
4937 if (SI == FuncInfo.StaticAllocaMap.end())
4938 return nullptr; // VLAs.
4942 case Intrinsic::eh_typeid_for: {
4943 // Find the type id for the given typeinfo.
4944 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4945 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4946 Res = DAG.getConstant(TypeID, MVT::i32);
4951 case Intrinsic::eh_return_i32:
4952 case Intrinsic::eh_return_i64:
4953 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4954 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4957 getValue(I.getArgOperand(0)),
4958 getValue(I.getArgOperand(1))));
4960 case Intrinsic::eh_unwind_init:
4961 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4963 case Intrinsic::eh_dwarf_cfa: {
4964 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4965 TLI.getPointerTy());
4966 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4967 CfaArg.getValueType(),
4968 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4969 CfaArg.getValueType()),
4971 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4972 DAG.getConstant(0, TLI.getPointerTy()));
4973 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4977 case Intrinsic::eh_sjlj_callsite: {
4978 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4979 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4980 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4981 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4983 MMI.setCurrentCallSite(CI->getZExtValue());
4986 case Intrinsic::eh_sjlj_functioncontext: {
4987 // Get and store the index of the function context.
4988 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4990 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4991 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4992 MFI->setFunctionContextIndex(FI);
4995 case Intrinsic::eh_sjlj_setjmp: {
4998 Ops[1] = getValue(I.getArgOperand(0));
4999 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
5000 DAG.getVTList(MVT::i32, MVT::Other), Ops);
5001 setValue(&I, Op.getValue(0));
5002 DAG.setRoot(Op.getValue(1));
5005 case Intrinsic::eh_sjlj_longjmp: {
5006 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
5007 getRoot(), getValue(I.getArgOperand(0))));
5011 case Intrinsic::masked_load:
5014 case Intrinsic::masked_store:
5015 visitMaskedStore(I);
5017 case Intrinsic::x86_mmx_pslli_w:
5018 case Intrinsic::x86_mmx_pslli_d:
5019 case Intrinsic::x86_mmx_pslli_q:
5020 case Intrinsic::x86_mmx_psrli_w:
5021 case Intrinsic::x86_mmx_psrli_d:
5022 case Intrinsic::x86_mmx_psrli_q:
5023 case Intrinsic::x86_mmx_psrai_w:
5024 case Intrinsic::x86_mmx_psrai_d: {
5025 SDValue ShAmt = getValue(I.getArgOperand(1));
5026 if (isa<ConstantSDNode>(ShAmt)) {
5027 visitTargetIntrinsic(I, Intrinsic);
5030 unsigned NewIntrinsic = 0;
5031 EVT ShAmtVT = MVT::v2i32;
5032 switch (Intrinsic) {
5033 case Intrinsic::x86_mmx_pslli_w:
5034 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
5036 case Intrinsic::x86_mmx_pslli_d:
5037 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
5039 case Intrinsic::x86_mmx_pslli_q:
5040 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
5042 case Intrinsic::x86_mmx_psrli_w:
5043 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
5045 case Intrinsic::x86_mmx_psrli_d:
5046 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
5048 case Intrinsic::x86_mmx_psrli_q:
5049 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
5051 case Intrinsic::x86_mmx_psrai_w:
5052 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
5054 case Intrinsic::x86_mmx_psrai_d:
5055 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
5057 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5060 // The vector shift intrinsics with scalars uses 32b shift amounts but
5061 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5063 // We must do this early because v2i32 is not a legal type.
5066 ShOps[1] = DAG.getConstant(0, MVT::i32);
5067 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
5068 EVT DestVT = TLI.getValueType(I.getType());
5069 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5070 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5071 DAG.getConstant(NewIntrinsic, MVT::i32),
5072 getValue(I.getArgOperand(0)), ShAmt);
5076 case Intrinsic::x86_avx_vinsertf128_pd_256:
5077 case Intrinsic::x86_avx_vinsertf128_ps_256:
5078 case Intrinsic::x86_avx_vinsertf128_si_256:
5079 case Intrinsic::x86_avx2_vinserti128: {
5080 EVT DestVT = TLI.getValueType(I.getType());
5081 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
5082 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
5083 ElVT.getVectorNumElements();
5085 DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
5086 getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)),
5087 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5091 case Intrinsic::x86_avx_vextractf128_pd_256:
5092 case Intrinsic::x86_avx_vextractf128_ps_256:
5093 case Intrinsic::x86_avx_vextractf128_si_256:
5094 case Intrinsic::x86_avx2_vextracti128: {
5095 EVT DestVT = TLI.getValueType(I.getType());
5096 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5097 DestVT.getVectorNumElements();
5098 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5099 getValue(I.getArgOperand(0)),
5100 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5104 case Intrinsic::convertff:
5105 case Intrinsic::convertfsi:
5106 case Intrinsic::convertfui:
5107 case Intrinsic::convertsif:
5108 case Intrinsic::convertuif:
5109 case Intrinsic::convertss:
5110 case Intrinsic::convertsu:
5111 case Intrinsic::convertus:
5112 case Intrinsic::convertuu: {
5113 ISD::CvtCode Code = ISD::CVT_INVALID;
5114 switch (Intrinsic) {
5115 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5116 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5117 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5118 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5119 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5120 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5121 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5122 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5123 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5124 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5126 EVT DestVT = TLI.getValueType(I.getType());
5127 const Value *Op1 = I.getArgOperand(0);
5128 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5129 DAG.getValueType(DestVT),
5130 DAG.getValueType(getValue(Op1).getValueType()),
5131 getValue(I.getArgOperand(1)),
5132 getValue(I.getArgOperand(2)),
5137 case Intrinsic::powi:
5138 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5139 getValue(I.getArgOperand(1)), DAG));
5141 case Intrinsic::log:
5142 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5144 case Intrinsic::log2:
5145 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5147 case Intrinsic::log10:
5148 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5150 case Intrinsic::exp:
5151 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5153 case Intrinsic::exp2:
5154 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5156 case Intrinsic::pow:
5157 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5158 getValue(I.getArgOperand(1)), DAG, TLI));
5160 case Intrinsic::sqrt:
5161 case Intrinsic::fabs:
5162 case Intrinsic::sin:
5163 case Intrinsic::cos:
5164 case Intrinsic::floor:
5165 case Intrinsic::ceil:
5166 case Intrinsic::trunc:
5167 case Intrinsic::rint:
5168 case Intrinsic::nearbyint:
5169 case Intrinsic::round: {
5171 switch (Intrinsic) {
5172 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5173 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5174 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5175 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5176 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5177 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5178 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5179 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5180 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5181 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5182 case Intrinsic::round: Opcode = ISD::FROUND; break;
5185 setValue(&I, DAG.getNode(Opcode, sdl,
5186 getValue(I.getArgOperand(0)).getValueType(),
5187 getValue(I.getArgOperand(0))));
5190 case Intrinsic::minnum:
5191 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
5192 getValue(I.getArgOperand(0)).getValueType(),
5193 getValue(I.getArgOperand(0)),
5194 getValue(I.getArgOperand(1))));
5196 case Intrinsic::maxnum:
5197 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
5198 getValue(I.getArgOperand(0)).getValueType(),
5199 getValue(I.getArgOperand(0)),
5200 getValue(I.getArgOperand(1))));
5202 case Intrinsic::copysign:
5203 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5204 getValue(I.getArgOperand(0)).getValueType(),
5205 getValue(I.getArgOperand(0)),
5206 getValue(I.getArgOperand(1))));
5208 case Intrinsic::fma:
5209 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5210 getValue(I.getArgOperand(0)).getValueType(),
5211 getValue(I.getArgOperand(0)),
5212 getValue(I.getArgOperand(1)),
5213 getValue(I.getArgOperand(2))));
5215 case Intrinsic::fmuladd: {
5216 EVT VT = TLI.getValueType(I.getType());
5217 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5218 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5219 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5220 getValue(I.getArgOperand(0)).getValueType(),
5221 getValue(I.getArgOperand(0)),
5222 getValue(I.getArgOperand(1)),
5223 getValue(I.getArgOperand(2))));
5225 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5226 getValue(I.getArgOperand(0)).getValueType(),
5227 getValue(I.getArgOperand(0)),
5228 getValue(I.getArgOperand(1)));
5229 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5230 getValue(I.getArgOperand(0)).getValueType(),
5232 getValue(I.getArgOperand(2)));
5237 case Intrinsic::convert_to_fp16:
5238 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5239 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5240 getValue(I.getArgOperand(0)),
5241 DAG.getTargetConstant(0, MVT::i32))));
5243 case Intrinsic::convert_from_fp16:
5245 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
5246 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5247 getValue(I.getArgOperand(0)))));
5249 case Intrinsic::pcmarker: {
5250 SDValue Tmp = getValue(I.getArgOperand(0));
5251 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5254 case Intrinsic::readcyclecounter: {
5255 SDValue Op = getRoot();
5256 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5257 DAG.getVTList(MVT::i64, MVT::Other), Op);
5259 DAG.setRoot(Res.getValue(1));
5262 case Intrinsic::bswap:
5263 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5264 getValue(I.getArgOperand(0)).getValueType(),
5265 getValue(I.getArgOperand(0))));
5267 case Intrinsic::cttz: {
5268 SDValue Arg = getValue(I.getArgOperand(0));
5269 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5270 EVT Ty = Arg.getValueType();
5271 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5275 case Intrinsic::ctlz: {
5276 SDValue Arg = getValue(I.getArgOperand(0));
5277 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5278 EVT Ty = Arg.getValueType();
5279 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5283 case Intrinsic::ctpop: {
5284 SDValue Arg = getValue(I.getArgOperand(0));
5285 EVT Ty = Arg.getValueType();
5286 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5289 case Intrinsic::stacksave: {
5290 SDValue Op = getRoot();
5291 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5292 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
5294 DAG.setRoot(Res.getValue(1));
5297 case Intrinsic::stackrestore: {
5298 Res = getValue(I.getArgOperand(0));
5299 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5302 case Intrinsic::stackprotector: {
5303 // Emit code into the DAG to store the stack guard onto the stack.
5304 MachineFunction &MF = DAG.getMachineFunction();
5305 MachineFrameInfo *MFI = MF.getFrameInfo();
5306 EVT PtrTy = TLI.getPointerTy();
5307 SDValue Src, Chain = getRoot();
5308 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5309 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5311 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5312 // global variable __stack_chk_guard.
5314 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5315 if (BC->getOpcode() == Instruction::BitCast)
5316 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5318 if (GV && TLI.useLoadStackGuardNode()) {
5319 // Emit a LOAD_STACK_GUARD node.
5320 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5322 MachinePointerInfo MPInfo(GV);
5323 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5324 unsigned Flags = MachineMemOperand::MOLoad |
5325 MachineMemOperand::MOInvariant;
5326 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5327 PtrTy.getSizeInBits() / 8,
5328 DAG.getEVTAlignment(PtrTy));
5329 Node->setMemRefs(MemRefs, MemRefs + 1);
5331 // Copy the guard value to a virtual register so that it can be
5332 // retrieved in the epilogue.
5333 Src = SDValue(Node, 0);
5334 const TargetRegisterClass *RC =
5335 TLI.getRegClassFor(Src.getSimpleValueType());
5336 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5338 SPDescriptor.setGuardReg(Reg);
5339 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5341 Src = getValue(I.getArgOperand(0)); // The guard's value.
5344 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5346 int FI = FuncInfo.StaticAllocaMap[Slot];
5347 MFI->setStackProtectorIndex(FI);
5349 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5351 // Store the stack protector onto the stack.
5352 Res = DAG.getStore(Chain, sdl, Src, FIN,
5353 MachinePointerInfo::getFixedStack(FI),
5359 case Intrinsic::objectsize: {
5360 // If we don't know by now, we're never going to know.
5361 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5363 assert(CI && "Non-constant type in __builtin_object_size?");
5365 SDValue Arg = getValue(I.getCalledValue());
5366 EVT Ty = Arg.getValueType();
5369 Res = DAG.getConstant(-1ULL, Ty);
5371 Res = DAG.getConstant(0, Ty);
5376 case Intrinsic::annotation:
5377 case Intrinsic::ptr_annotation:
5378 // Drop the intrinsic, but forward the value
5379 setValue(&I, getValue(I.getOperand(0)));
5381 case Intrinsic::assume:
5382 case Intrinsic::var_annotation:
5383 // Discard annotate attributes and assumptions
5386 case Intrinsic::init_trampoline: {
5387 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5391 Ops[1] = getValue(I.getArgOperand(0));
5392 Ops[2] = getValue(I.getArgOperand(1));
5393 Ops[3] = getValue(I.getArgOperand(2));
5394 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5395 Ops[5] = DAG.getSrcValue(F);
5397 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5402 case Intrinsic::adjust_trampoline: {
5403 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5405 getValue(I.getArgOperand(0))));
5408 case Intrinsic::gcroot:
5410 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5411 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5413 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5414 GFI->addStackRoot(FI->getIndex(), TypeMap);
5417 case Intrinsic::gcread:
5418 case Intrinsic::gcwrite:
5419 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5420 case Intrinsic::flt_rounds:
5421 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5424 case Intrinsic::expect: {
5425 // Just replace __builtin_expect(exp, c) with EXP.
5426 setValue(&I, getValue(I.getArgOperand(0)));
5430 case Intrinsic::debugtrap:
5431 case Intrinsic::trap: {
5432 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5433 if (TrapFuncName.empty()) {
5434 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5435 ISD::TRAP : ISD::DEBUGTRAP;
5436 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5439 TargetLowering::ArgListTy Args;
5441 TargetLowering::CallLoweringInfo CLI(DAG);
5442 CLI.setDebugLoc(sdl).setChain(getRoot())
5443 .setCallee(CallingConv::C, I.getType(),
5444 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5445 std::move(Args), 0);
5447 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5448 DAG.setRoot(Result.second);
5452 case Intrinsic::uadd_with_overflow:
5453 case Intrinsic::sadd_with_overflow:
5454 case Intrinsic::usub_with_overflow:
5455 case Intrinsic::ssub_with_overflow:
5456 case Intrinsic::umul_with_overflow:
5457 case Intrinsic::smul_with_overflow: {
5459 switch (Intrinsic) {
5460 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5461 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5462 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5463 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5464 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5465 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5466 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5468 SDValue Op1 = getValue(I.getArgOperand(0));
5469 SDValue Op2 = getValue(I.getArgOperand(1));
5471 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5472 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5475 case Intrinsic::prefetch: {
5477 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5479 Ops[1] = getValue(I.getArgOperand(0));
5480 Ops[2] = getValue(I.getArgOperand(1));
5481 Ops[3] = getValue(I.getArgOperand(2));
5482 Ops[4] = getValue(I.getArgOperand(3));
5483 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5484 DAG.getVTList(MVT::Other), Ops,
5485 EVT::getIntegerVT(*Context, 8),
5486 MachinePointerInfo(I.getArgOperand(0)),
5488 false, /* volatile */
5490 rw==1)); /* write */
5493 case Intrinsic::lifetime_start:
5494 case Intrinsic::lifetime_end: {
5495 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5496 // Stack coloring is not enabled in O0, discard region information.
5497 if (TM.getOptLevel() == CodeGenOpt::None)
5500 SmallVector<Value *, 4> Allocas;
5501 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5503 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5504 E = Allocas.end(); Object != E; ++Object) {
5505 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5507 // Could not find an Alloca.
5508 if (!LifetimeObject)
5511 // First check that the Alloca is static, otherwise it won't have a
5512 // valid frame index.
5513 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5514 if (SI == FuncInfo.StaticAllocaMap.end())
5517 int FI = SI->second;
5521 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5522 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5524 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5529 case Intrinsic::invariant_start:
5530 // Discard region information.
5531 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5533 case Intrinsic::invariant_end:
5534 // Discard region information.
5536 case Intrinsic::stackprotectorcheck: {
5537 // Do not actually emit anything for this basic block. Instead we initialize
5538 // the stack protector descriptor and export the guard variable so we can
5539 // access it in FinishBasicBlock.
5540 const BasicBlock *BB = I.getParent();
5541 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5542 ExportFromCurrentBlock(SPDescriptor.getGuard());
5544 // Flush our exports since we are going to process a terminator.
5545 (void)getControlRoot();
5548 case Intrinsic::clear_cache:
5549 return TLI.getClearCacheBuiltinName();
5550 case Intrinsic::donothing:
5553 case Intrinsic::experimental_stackmap: {
5557 case Intrinsic::experimental_patchpoint_void:
5558 case Intrinsic::experimental_patchpoint_i64: {
5559 visitPatchpoint(&I);
5562 case Intrinsic::experimental_gc_statepoint: {
5566 case Intrinsic::experimental_gc_result_int:
5567 case Intrinsic::experimental_gc_result_float:
5568 case Intrinsic::experimental_gc_result_ptr: {
5572 case Intrinsic::experimental_gc_relocate: {
5576 case Intrinsic::instrprof_increment:
5577 llvm_unreachable("instrprof failed to lower an increment");
5581 std::pair<SDValue, SDValue>
5582 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5583 MachineBasicBlock *LandingPad) {
5584 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5585 MCSymbol *BeginLabel = nullptr;
5588 // Insert a label before the invoke call to mark the try range. This can be
5589 // used to detect deletion of the invoke via the MachineModuleInfo.
5590 BeginLabel = MMI.getContext().CreateTempSymbol();
5592 // For SjLj, keep track of which landing pads go with which invokes
5593 // so as to maintain the ordering of pads in the LSDA.
5594 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5595 if (CallSiteIndex) {
5596 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5597 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5599 // Now that the call site is handled, stop tracking it.
5600 MMI.setCurrentCallSite(0);
5603 // Both PendingLoads and PendingExports must be flushed here;
5604 // this call might not return.
5606 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5608 CLI.setChain(getRoot());
5611 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
5612 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5614 assert((CLI.IsTailCall || Result.second.getNode()) &&
5615 "Non-null chain expected with non-tail call!");
5616 assert((Result.second.getNode() || !Result.first.getNode()) &&
5617 "Null value expected with tail call!");
5619 if (!Result.second.getNode()) {
5620 // As a special case, a null chain means that a tail call has been emitted
5621 // and the DAG root is already updated.
5624 // Since there's no actual continuation from this block, nothing can be
5625 // relying on us setting vregs for them.
5626 PendingExports.clear();
5628 DAG.setRoot(Result.second);
5632 // Insert a label at the end of the invoke call to mark the try range. This
5633 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5634 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5635 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5637 // Inform MachineModuleInfo of range.
5638 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5644 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5646 MachineBasicBlock *LandingPad) {
5647 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5648 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5649 Type *RetTy = FTy->getReturnType();
5651 TargetLowering::ArgListTy Args;
5652 TargetLowering::ArgListEntry Entry;
5653 Args.reserve(CS.arg_size());
5655 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5657 const Value *V = *i;
5660 if (V->getType()->isEmptyTy())
5663 SDValue ArgNode = getValue(V);
5664 Entry.Node = ArgNode; Entry.Ty = V->getType();
5666 // Skip the first return-type Attribute to get to params.
5667 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5668 Args.push_back(Entry);
5671 // Check if target-independent constraints permit a tail call here.
5672 // Target-dependent constraints are checked within TLI->LowerCallTo.
5673 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5676 TargetLowering::CallLoweringInfo CLI(DAG);
5677 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5678 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5679 .setTailCall(isTailCall);
5680 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5682 if (Result.first.getNode())
5683 setValue(CS.getInstruction(), Result.first);
5686 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5687 /// value is equal or not-equal to zero.
5688 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5689 for (const User *U : V->users()) {
5690 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5691 if (IC->isEquality())
5692 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5693 if (C->isNullValue())
5695 // Unknown instruction.
5701 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5703 SelectionDAGBuilder &Builder) {
5705 // Check to see if this load can be trivially constant folded, e.g. if the
5706 // input is from a string literal.
5707 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5708 // Cast pointer to the type we really want to load.
5709 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5710 PointerType::getUnqual(LoadTy));
5712 if (const Constant *LoadCst =
5713 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5715 return Builder.getValue(LoadCst);
5718 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5719 // still constant memory, the input chain can be the entry node.
5721 bool ConstantMemory = false;
5723 // Do not serialize (non-volatile) loads of constant memory with anything.
5724 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5725 Root = Builder.DAG.getEntryNode();
5726 ConstantMemory = true;
5728 // Do not serialize non-volatile loads against each other.
5729 Root = Builder.DAG.getRoot();
5732 SDValue Ptr = Builder.getValue(PtrVal);
5733 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5734 Ptr, MachinePointerInfo(PtrVal),
5736 false /*nontemporal*/,
5737 false /*isinvariant*/, 1 /* align=1 */);
5739 if (!ConstantMemory)
5740 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5744 /// processIntegerCallValue - Record the value for an instruction that
5745 /// produces an integer result, converting the type where necessary.
5746 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5749 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5751 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5753 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5754 setValue(&I, Value);
5757 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5758 /// If so, return true and lower it, otherwise return false and it will be
5759 /// lowered like a normal call.
5760 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5761 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5762 if (I.getNumArgOperands() != 3)
5765 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5766 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5767 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5768 !I.getType()->isIntegerTy())
5771 const Value *Size = I.getArgOperand(2);
5772 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5773 if (CSize && CSize->getZExtValue() == 0) {
5774 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5775 setValue(&I, DAG.getConstant(0, CallVT));
5779 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5780 std::pair<SDValue, SDValue> Res =
5781 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5782 getValue(LHS), getValue(RHS), getValue(Size),
5783 MachinePointerInfo(LHS),
5784 MachinePointerInfo(RHS));
5785 if (Res.first.getNode()) {
5786 processIntegerCallValue(I, Res.first, true);
5787 PendingLoads.push_back(Res.second);
5791 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5792 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5793 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5794 bool ActuallyDoIt = true;
5797 switch (CSize->getZExtValue()) {
5799 LoadVT = MVT::Other;
5801 ActuallyDoIt = false;
5805 LoadTy = Type::getInt16Ty(CSize->getContext());
5809 LoadTy = Type::getInt32Ty(CSize->getContext());
5813 LoadTy = Type::getInt64Ty(CSize->getContext());
5817 LoadVT = MVT::v4i32;
5818 LoadTy = Type::getInt32Ty(CSize->getContext());
5819 LoadTy = VectorType::get(LoadTy, 4);
5824 // This turns into unaligned loads. We only do this if the target natively
5825 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5826 // we'll only produce a small number of byte loads.
5828 // Require that we can find a legal MVT, and only do this if the target
5829 // supports unaligned loads of that type. Expanding into byte loads would
5831 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5832 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5833 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5834 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5835 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5836 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5837 // TODO: Check alignment of src and dest ptrs.
5838 if (!TLI.isTypeLegal(LoadVT) ||
5839 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5840 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5841 ActuallyDoIt = false;
5845 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5846 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5848 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5850 processIntegerCallValue(I, Res, false);
5859 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5860 /// form. If so, return true and lower it, otherwise return false and it
5861 /// will be lowered like a normal call.
5862 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5863 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5864 if (I.getNumArgOperands() != 3)
5867 const Value *Src = I.getArgOperand(0);
5868 const Value *Char = I.getArgOperand(1);
5869 const Value *Length = I.getArgOperand(2);
5870 if (!Src->getType()->isPointerTy() ||
5871 !Char->getType()->isIntegerTy() ||
5872 !Length->getType()->isIntegerTy() ||
5873 !I.getType()->isPointerTy())
5876 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5877 std::pair<SDValue, SDValue> Res =
5878 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5879 getValue(Src), getValue(Char), getValue(Length),
5880 MachinePointerInfo(Src));
5881 if (Res.first.getNode()) {
5882 setValue(&I, Res.first);
5883 PendingLoads.push_back(Res.second);
5890 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5891 /// optimized form. If so, return true and lower it, otherwise return false
5892 /// and it will be lowered like a normal call.
5893 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5894 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5895 if (I.getNumArgOperands() != 2)
5898 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5899 if (!Arg0->getType()->isPointerTy() ||
5900 !Arg1->getType()->isPointerTy() ||
5901 !I.getType()->isPointerTy())
5904 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5905 std::pair<SDValue, SDValue> Res =
5906 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5907 getValue(Arg0), getValue(Arg1),
5908 MachinePointerInfo(Arg0),
5909 MachinePointerInfo(Arg1), isStpcpy);
5910 if (Res.first.getNode()) {
5911 setValue(&I, Res.first);
5912 DAG.setRoot(Res.second);
5919 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5920 /// If so, return true and lower it, otherwise return false and it will be
5921 /// lowered like a normal call.
5922 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5923 // Verify that the prototype makes sense. int strcmp(void*,void*)
5924 if (I.getNumArgOperands() != 2)
5927 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5928 if (!Arg0->getType()->isPointerTy() ||
5929 !Arg1->getType()->isPointerTy() ||
5930 !I.getType()->isIntegerTy())
5933 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5934 std::pair<SDValue, SDValue> Res =
5935 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5936 getValue(Arg0), getValue(Arg1),
5937 MachinePointerInfo(Arg0),
5938 MachinePointerInfo(Arg1));
5939 if (Res.first.getNode()) {
5940 processIntegerCallValue(I, Res.first, true);
5941 PendingLoads.push_back(Res.second);
5948 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5949 /// form. If so, return true and lower it, otherwise return false and it
5950 /// will be lowered like a normal call.
5951 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5952 // Verify that the prototype makes sense. size_t strlen(char *)
5953 if (I.getNumArgOperands() != 1)
5956 const Value *Arg0 = I.getArgOperand(0);
5957 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5960 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5961 std::pair<SDValue, SDValue> Res =
5962 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5963 getValue(Arg0), MachinePointerInfo(Arg0));
5964 if (Res.first.getNode()) {
5965 processIntegerCallValue(I, Res.first, false);
5966 PendingLoads.push_back(Res.second);
5973 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5974 /// form. If so, return true and lower it, otherwise return false and it
5975 /// will be lowered like a normal call.
5976 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5977 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5978 if (I.getNumArgOperands() != 2)
5981 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5982 if (!Arg0->getType()->isPointerTy() ||
5983 !Arg1->getType()->isIntegerTy() ||
5984 !I.getType()->isIntegerTy())
5987 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5988 std::pair<SDValue, SDValue> Res =
5989 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5990 getValue(Arg0), getValue(Arg1),
5991 MachinePointerInfo(Arg0));
5992 if (Res.first.getNode()) {
5993 processIntegerCallValue(I, Res.first, false);
5994 PendingLoads.push_back(Res.second);
6001 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
6002 /// operation (as expected), translate it to an SDNode with the specified opcode
6003 /// and return true.
6004 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
6006 // Sanity check that it really is a unary floating-point call.
6007 if (I.getNumArgOperands() != 1 ||
6008 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
6009 I.getType() != I.getArgOperand(0)->getType() ||
6010 !I.onlyReadsMemory())
6013 SDValue Tmp = getValue(I.getArgOperand(0));
6014 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
6018 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
6019 /// operation (as expected), translate it to an SDNode with the specified opcode
6020 /// and return true.
6021 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
6023 // Sanity check that it really is a binary floating-point call.
6024 if (I.getNumArgOperands() != 2 ||
6025 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
6026 I.getType() != I.getArgOperand(0)->getType() ||
6027 I.getType() != I.getArgOperand(1)->getType() ||
6028 !I.onlyReadsMemory())
6031 SDValue Tmp0 = getValue(I.getArgOperand(0));
6032 SDValue Tmp1 = getValue(I.getArgOperand(1));
6033 EVT VT = Tmp0.getValueType();
6034 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
6038 void SelectionDAGBuilder::visitCall(const CallInst &I) {
6039 // Handle inline assembly differently.
6040 if (isa<InlineAsm>(I.getCalledValue())) {
6045 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
6046 ComputeUsesVAFloatArgument(I, &MMI);
6048 const char *RenameFn = nullptr;
6049 if (Function *F = I.getCalledFunction()) {
6050 if (F->isDeclaration()) {
6051 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
6052 if (unsigned IID = II->getIntrinsicID(F)) {
6053 RenameFn = visitIntrinsicCall(I, IID);
6058 if (unsigned IID = F->getIntrinsicID()) {
6059 RenameFn = visitIntrinsicCall(I, IID);
6065 // Check for well-known libc/libm calls. If the function is internal, it
6066 // can't be a library call.
6068 if (!F->hasLocalLinkage() && F->hasName() &&
6069 LibInfo->getLibFunc(F->getName(), Func) &&
6070 LibInfo->hasOptimizedCodeGen(Func)) {
6073 case LibFunc::copysign:
6074 case LibFunc::copysignf:
6075 case LibFunc::copysignl:
6076 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
6077 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
6078 I.getType() == I.getArgOperand(0)->getType() &&
6079 I.getType() == I.getArgOperand(1)->getType() &&
6080 I.onlyReadsMemory()) {
6081 SDValue LHS = getValue(I.getArgOperand(0));
6082 SDValue RHS = getValue(I.getArgOperand(1));
6083 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
6084 LHS.getValueType(), LHS, RHS));
6089 case LibFunc::fabsf:
6090 case LibFunc::fabsl:
6091 if (visitUnaryFloatCall(I, ISD::FABS))
6095 case LibFunc::fminf:
6096 case LibFunc::fminl:
6097 if (visitBinaryFloatCall(I, ISD::FMINNUM))
6101 case LibFunc::fmaxf:
6102 case LibFunc::fmaxl:
6103 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
6109 if (visitUnaryFloatCall(I, ISD::FSIN))
6115 if (visitUnaryFloatCall(I, ISD::FCOS))
6119 case LibFunc::sqrtf:
6120 case LibFunc::sqrtl:
6121 case LibFunc::sqrt_finite:
6122 case LibFunc::sqrtf_finite:
6123 case LibFunc::sqrtl_finite:
6124 if (visitUnaryFloatCall(I, ISD::FSQRT))
6127 case LibFunc::floor:
6128 case LibFunc::floorf:
6129 case LibFunc::floorl:
6130 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6133 case LibFunc::nearbyint:
6134 case LibFunc::nearbyintf:
6135 case LibFunc::nearbyintl:
6136 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6140 case LibFunc::ceilf:
6141 case LibFunc::ceill:
6142 if (visitUnaryFloatCall(I, ISD::FCEIL))
6146 case LibFunc::rintf:
6147 case LibFunc::rintl:
6148 if (visitUnaryFloatCall(I, ISD::FRINT))
6151 case LibFunc::round:
6152 case LibFunc::roundf:
6153 case LibFunc::roundl:
6154 if (visitUnaryFloatCall(I, ISD::FROUND))
6157 case LibFunc::trunc:
6158 case LibFunc::truncf:
6159 case LibFunc::truncl:
6160 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6164 case LibFunc::log2f:
6165 case LibFunc::log2l:
6166 if (visitUnaryFloatCall(I, ISD::FLOG2))
6170 case LibFunc::exp2f:
6171 case LibFunc::exp2l:
6172 if (visitUnaryFloatCall(I, ISD::FEXP2))
6175 case LibFunc::memcmp:
6176 if (visitMemCmpCall(I))
6179 case LibFunc::memchr:
6180 if (visitMemChrCall(I))
6183 case LibFunc::strcpy:
6184 if (visitStrCpyCall(I, false))
6187 case LibFunc::stpcpy:
6188 if (visitStrCpyCall(I, true))
6191 case LibFunc::strcmp:
6192 if (visitStrCmpCall(I))
6195 case LibFunc::strlen:
6196 if (visitStrLenCall(I))
6199 case LibFunc::strnlen:
6200 if (visitStrNLenCall(I))
6209 Callee = getValue(I.getCalledValue());
6211 Callee = DAG.getExternalSymbol(RenameFn,
6212 DAG.getTargetLoweringInfo().getPointerTy());
6214 // Check if we can potentially perform a tail call. More detailed checking is
6215 // be done within LowerCallTo, after more information about the call is known.
6216 LowerCallTo(&I, Callee, I.isTailCall());
6221 /// AsmOperandInfo - This contains information for each constraint that we are
6223 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6225 /// CallOperand - If this is the result output operand or a clobber
6226 /// this is null, otherwise it is the incoming operand to the CallInst.
6227 /// This gets modified as the asm is processed.
6228 SDValue CallOperand;
6230 /// AssignedRegs - If this is a register or register class operand, this
6231 /// contains the set of register corresponding to the operand.
6232 RegsForValue AssignedRegs;
6234 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6235 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6238 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6239 /// corresponds to. If there is no Value* for this operand, it returns
6241 EVT getCallOperandValEVT(LLVMContext &Context,
6242 const TargetLowering &TLI,
6243 const DataLayout *DL) const {
6244 if (!CallOperandVal) return MVT::Other;
6246 if (isa<BasicBlock>(CallOperandVal))
6247 return TLI.getPointerTy();
6249 llvm::Type *OpTy = CallOperandVal->getType();
6251 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6252 // If this is an indirect operand, the operand is a pointer to the
6255 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6257 report_fatal_error("Indirect operand for inline asm not a pointer!");
6258 OpTy = PtrTy->getElementType();
6261 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6262 if (StructType *STy = dyn_cast<StructType>(OpTy))
6263 if (STy->getNumElements() == 1)
6264 OpTy = STy->getElementType(0);
6266 // If OpTy is not a single value, it may be a struct/union that we
6267 // can tile with integers.
6268 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6269 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6278 OpTy = IntegerType::get(Context, BitSize);
6283 return TLI.getValueType(OpTy, true);
6287 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6289 } // end anonymous namespace
6291 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6292 /// specified operand. We prefer to assign virtual registers, to allow the
6293 /// register allocator to handle the assignment process. However, if the asm
6294 /// uses features that we can't model on machineinstrs, we have SDISel do the
6295 /// allocation. This produces generally horrible, but correct, code.
6297 /// OpInfo describes the operand.
6299 static void GetRegistersForValue(SelectionDAG &DAG,
6300 const TargetLowering &TLI,
6302 SDISelAsmOperandInfo &OpInfo) {
6303 LLVMContext &Context = *DAG.getContext();
6305 MachineFunction &MF = DAG.getMachineFunction();
6306 SmallVector<unsigned, 4> Regs;
6308 // If this is a constraint for a single physreg, or a constraint for a
6309 // register class, find it.
6310 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6311 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6312 OpInfo.ConstraintVT);
6314 unsigned NumRegs = 1;
6315 if (OpInfo.ConstraintVT != MVT::Other) {
6316 // If this is a FP input in an integer register (or visa versa) insert a bit
6317 // cast of the input value. More generally, handle any case where the input
6318 // value disagrees with the register class we plan to stick this in.
6319 if (OpInfo.Type == InlineAsm::isInput &&
6320 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6321 // Try to convert to the first EVT that the reg class contains. If the
6322 // types are identical size, use a bitcast to convert (e.g. two differing
6324 MVT RegVT = *PhysReg.second->vt_begin();
6325 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6326 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6327 RegVT, OpInfo.CallOperand);
6328 OpInfo.ConstraintVT = RegVT;
6329 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6330 // If the input is a FP value and we want it in FP registers, do a
6331 // bitcast to the corresponding integer type. This turns an f64 value
6332 // into i64, which can be passed with two i32 values on a 32-bit
6334 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6335 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6336 RegVT, OpInfo.CallOperand);
6337 OpInfo.ConstraintVT = RegVT;
6341 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6345 EVT ValueVT = OpInfo.ConstraintVT;
6347 // If this is a constraint for a specific physical register, like {r17},
6349 if (unsigned AssignedReg = PhysReg.first) {
6350 const TargetRegisterClass *RC = PhysReg.second;
6351 if (OpInfo.ConstraintVT == MVT::Other)
6352 ValueVT = *RC->vt_begin();
6354 // Get the actual register value type. This is important, because the user
6355 // may have asked for (e.g.) the AX register in i32 type. We need to
6356 // remember that AX is actually i16 to get the right extension.
6357 RegVT = *RC->vt_begin();
6359 // This is a explicit reference to a physical register.
6360 Regs.push_back(AssignedReg);
6362 // If this is an expanded reference, add the rest of the regs to Regs.
6364 TargetRegisterClass::iterator I = RC->begin();
6365 for (; *I != AssignedReg; ++I)
6366 assert(I != RC->end() && "Didn't find reg!");
6368 // Already added the first reg.
6370 for (; NumRegs; --NumRegs, ++I) {
6371 assert(I != RC->end() && "Ran out of registers to allocate!");
6376 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6380 // Otherwise, if this was a reference to an LLVM register class, create vregs
6381 // for this reference.
6382 if (const TargetRegisterClass *RC = PhysReg.second) {
6383 RegVT = *RC->vt_begin();
6384 if (OpInfo.ConstraintVT == MVT::Other)
6387 // Create the appropriate number of virtual registers.
6388 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6389 for (; NumRegs; --NumRegs)
6390 Regs.push_back(RegInfo.createVirtualRegister(RC));
6392 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6396 // Otherwise, we couldn't allocate enough registers for this.
6399 /// visitInlineAsm - Handle a call to an InlineAsm object.
6401 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6402 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6404 /// ConstraintOperands - Information about all of the constraints.
6405 SDISelAsmOperandInfoVector ConstraintOperands;
6407 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6408 TargetLowering::AsmOperandInfoVector
6409 TargetConstraints = TLI.ParseConstraints(CS);
6411 bool hasMemory = false;
6413 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6414 unsigned ResNo = 0; // ResNo - The result number of the next output.
6415 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6416 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6417 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6419 MVT OpVT = MVT::Other;
6421 // Compute the value type for each operand.
6422 switch (OpInfo.Type) {
6423 case InlineAsm::isOutput:
6424 // Indirect outputs just consume an argument.
6425 if (OpInfo.isIndirect) {
6426 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6430 // The return value of the call is this value. As such, there is no
6431 // corresponding argument.
6432 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6433 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6434 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
6436 assert(ResNo == 0 && "Asm only has one result!");
6437 OpVT = TLI.getSimpleValueType(CS.getType());
6441 case InlineAsm::isInput:
6442 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6444 case InlineAsm::isClobber:
6449 // If this is an input or an indirect output, process the call argument.
6450 // BasicBlocks are labels, currently appearing only in asm's.
6451 if (OpInfo.CallOperandVal) {
6452 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6453 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6455 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6459 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
6462 OpInfo.ConstraintVT = OpVT;
6464 // Indirect operand accesses access memory.
6465 if (OpInfo.isIndirect)
6468 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6469 TargetLowering::ConstraintType
6470 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6471 if (CType == TargetLowering::C_Memory) {
6479 SDValue Chain, Flag;
6481 // We won't need to flush pending loads if this asm doesn't touch
6482 // memory and is nonvolatile.
6483 if (hasMemory || IA->hasSideEffects())
6486 Chain = DAG.getRoot();
6488 // Second pass over the constraints: compute which constraint option to use
6489 // and assign registers to constraints that want a specific physreg.
6490 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6491 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6493 // If this is an output operand with a matching input operand, look up the
6494 // matching input. If their types mismatch, e.g. one is an integer, the
6495 // other is floating point, or their sizes are different, flag it as an
6497 if (OpInfo.hasMatchingInput()) {
6498 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6500 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6501 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6502 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6503 OpInfo.ConstraintVT);
6504 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6505 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
6506 Input.ConstraintVT);
6507 if ((OpInfo.ConstraintVT.isInteger() !=
6508 Input.ConstraintVT.isInteger()) ||
6509 (MatchRC.second != InputRC.second)) {
6510 report_fatal_error("Unsupported asm: input constraint"
6511 " with a matching output constraint of"
6512 " incompatible type!");
6514 Input.ConstraintVT = OpInfo.ConstraintVT;
6518 // Compute the constraint code and ConstraintType to use.
6519 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6521 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6522 OpInfo.Type == InlineAsm::isClobber)
6525 // If this is a memory input, and if the operand is not indirect, do what we
6526 // need to to provide an address for the memory input.
6527 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6528 !OpInfo.isIndirect) {
6529 assert((OpInfo.isMultipleAlternative ||
6530 (OpInfo.Type == InlineAsm::isInput)) &&
6531 "Can only indirectify direct input operands!");
6533 // Memory operands really want the address of the value. If we don't have
6534 // an indirect input, put it in the constpool if we can, otherwise spill
6535 // it to a stack slot.
6536 // TODO: This isn't quite right. We need to handle these according to
6537 // the addressing mode that the constraint wants. Also, this may take
6538 // an additional register for the computation and we don't want that
6541 // If the operand is a float, integer, or vector constant, spill to a
6542 // constant pool entry to get its address.
6543 const Value *OpVal = OpInfo.CallOperandVal;
6544 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6545 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6546 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6547 TLI.getPointerTy());
6549 // Otherwise, create a stack slot and emit a store to it before the
6551 Type *Ty = OpVal->getType();
6552 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
6553 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
6554 MachineFunction &MF = DAG.getMachineFunction();
6555 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6556 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6557 Chain = DAG.getStore(Chain, getCurSDLoc(),
6558 OpInfo.CallOperand, StackSlot,
6559 MachinePointerInfo::getFixedStack(SSFI),
6561 OpInfo.CallOperand = StackSlot;
6564 // There is no longer a Value* corresponding to this operand.
6565 OpInfo.CallOperandVal = nullptr;
6567 // It is now an indirect operand.
6568 OpInfo.isIndirect = true;
6571 // If this constraint is for a specific register, allocate it before
6573 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6574 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6577 // Second pass - Loop over all of the operands, assigning virtual or physregs
6578 // to register class operands.
6579 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6580 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6582 // C_Register operands have already been allocated, Other/Memory don't need
6584 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6585 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6588 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6589 std::vector<SDValue> AsmNodeOperands;
6590 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6591 AsmNodeOperands.push_back(
6592 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6593 TLI.getPointerTy()));
6595 // If we have a !srcloc metadata node associated with it, we want to attach
6596 // this to the ultimately generated inline asm machineinstr. To do this, we
6597 // pass in the third operand as this (potentially null) inline asm MDNode.
6598 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6599 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6601 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6602 // bits as operand 3.
6603 unsigned ExtraInfo = 0;
6604 if (IA->hasSideEffects())
6605 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6606 if (IA->isAlignStack())
6607 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6608 // Set the asm dialect.
6609 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6611 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6612 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6613 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6615 // Compute the constraint code and ConstraintType to use.
6616 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6618 // Ideally, we would only check against memory constraints. However, the
6619 // meaning of an other constraint can be target-specific and we can't easily
6620 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6621 // for other constriants as well.
6622 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6623 OpInfo.ConstraintType == TargetLowering::C_Other) {
6624 if (OpInfo.Type == InlineAsm::isInput)
6625 ExtraInfo |= InlineAsm::Extra_MayLoad;
6626 else if (OpInfo.Type == InlineAsm::isOutput)
6627 ExtraInfo |= InlineAsm::Extra_MayStore;
6628 else if (OpInfo.Type == InlineAsm::isClobber)
6629 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6633 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6634 TLI.getPointerTy()));
6636 // Loop over all of the inputs, copying the operand values into the
6637 // appropriate registers and processing the output regs.
6638 RegsForValue RetValRegs;
6640 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6641 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6643 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6644 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6646 switch (OpInfo.Type) {
6647 case InlineAsm::isOutput: {
6648 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6649 OpInfo.ConstraintType != TargetLowering::C_Register) {
6650 // Memory output, or 'other' output (e.g. 'X' constraint).
6651 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6653 // Add information to the INLINEASM node to know about this output.
6654 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6655 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6656 TLI.getPointerTy()));
6657 AsmNodeOperands.push_back(OpInfo.CallOperand);
6661 // Otherwise, this is a register or register class output.
6663 // Copy the output from the appropriate register. Find a register that
6665 if (OpInfo.AssignedRegs.Regs.empty()) {
6666 LLVMContext &Ctx = *DAG.getContext();
6667 Ctx.emitError(CS.getInstruction(),
6668 "couldn't allocate output register for constraint '" +
6669 Twine(OpInfo.ConstraintCode) + "'");
6673 // If this is an indirect operand, store through the pointer after the
6675 if (OpInfo.isIndirect) {
6676 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6677 OpInfo.CallOperandVal));
6679 // This is the result value of the call.
6680 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6681 // Concatenate this output onto the outputs list.
6682 RetValRegs.append(OpInfo.AssignedRegs);
6685 // Add information to the INLINEASM node to know that this register is
6688 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6689 ? InlineAsm::Kind_RegDefEarlyClobber
6690 : InlineAsm::Kind_RegDef,
6691 false, 0, DAG, AsmNodeOperands);
6694 case InlineAsm::isInput: {
6695 SDValue InOperandVal = OpInfo.CallOperand;
6697 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6698 // If this is required to match an output register we have already set,
6699 // just use its register.
6700 unsigned OperandNo = OpInfo.getMatchedOperand();
6702 // Scan until we find the definition we already emitted of this operand.
6703 // When we find it, create a RegsForValue operand.
6704 unsigned CurOp = InlineAsm::Op_FirstOperand;
6705 for (; OperandNo; --OperandNo) {
6706 // Advance to the next operand.
6708 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6709 assert((InlineAsm::isRegDefKind(OpFlag) ||
6710 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6711 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6712 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6716 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6717 if (InlineAsm::isRegDefKind(OpFlag) ||
6718 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6719 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6720 if (OpInfo.isIndirect) {
6721 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6722 LLVMContext &Ctx = *DAG.getContext();
6723 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6724 " don't know how to handle tied "
6725 "indirect register inputs");
6729 RegsForValue MatchedRegs;
6730 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6731 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6732 MatchedRegs.RegVTs.push_back(RegVT);
6733 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6734 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6736 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6737 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6739 LLVMContext &Ctx = *DAG.getContext();
6740 Ctx.emitError(CS.getInstruction(),
6741 "inline asm error: This value"
6742 " type register class is not natively supported!");
6746 // Use the produced MatchedRegs object to
6747 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6748 Chain, &Flag, CS.getInstruction());
6749 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6750 true, OpInfo.getMatchedOperand(),
6751 DAG, AsmNodeOperands);
6755 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6756 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6757 "Unexpected number of operands");
6758 // Add information to the INLINEASM node to know about this input.
6759 // See InlineAsm.h isUseOperandTiedToDef.
6760 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6761 OpInfo.getMatchedOperand());
6762 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6763 TLI.getPointerTy()));
6764 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6768 // Treat indirect 'X' constraint as memory.
6769 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6771 OpInfo.ConstraintType = TargetLowering::C_Memory;
6773 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6774 std::vector<SDValue> Ops;
6775 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6778 LLVMContext &Ctx = *DAG.getContext();
6779 Ctx.emitError(CS.getInstruction(),
6780 "invalid operand for inline asm constraint '" +
6781 Twine(OpInfo.ConstraintCode) + "'");
6785 // Add information to the INLINEASM node to know about this input.
6786 unsigned ResOpType =
6787 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6788 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6789 TLI.getPointerTy()));
6790 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6794 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6795 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6796 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6797 "Memory operands expect pointer values");
6799 // Add information to the INLINEASM node to know about this input.
6800 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6801 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6802 TLI.getPointerTy()));
6803 AsmNodeOperands.push_back(InOperandVal);
6807 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6808 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6809 "Unknown constraint type!");
6811 // TODO: Support this.
6812 if (OpInfo.isIndirect) {
6813 LLVMContext &Ctx = *DAG.getContext();
6814 Ctx.emitError(CS.getInstruction(),
6815 "Don't know how to handle indirect register inputs yet "
6816 "for constraint '" +
6817 Twine(OpInfo.ConstraintCode) + "'");
6821 // Copy the input into the appropriate registers.
6822 if (OpInfo.AssignedRegs.Regs.empty()) {
6823 LLVMContext &Ctx = *DAG.getContext();
6824 Ctx.emitError(CS.getInstruction(),
6825 "couldn't allocate input reg for constraint '" +
6826 Twine(OpInfo.ConstraintCode) + "'");
6830 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6831 Chain, &Flag, CS.getInstruction());
6833 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6834 DAG, AsmNodeOperands);
6837 case InlineAsm::isClobber: {
6838 // Add the clobbered value to the operand list, so that the register
6839 // allocator is aware that the physreg got clobbered.
6840 if (!OpInfo.AssignedRegs.Regs.empty())
6841 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6849 // Finish up input operands. Set the input chain and add the flag last.
6850 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6851 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6853 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6854 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6855 Flag = Chain.getValue(1);
6857 // If this asm returns a register value, copy the result from that register
6858 // and set it as the value of the call.
6859 if (!RetValRegs.Regs.empty()) {
6860 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6861 Chain, &Flag, CS.getInstruction());
6863 // FIXME: Why don't we do this for inline asms with MRVs?
6864 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6865 EVT ResultType = TLI.getValueType(CS.getType());
6867 // If any of the results of the inline asm is a vector, it may have the
6868 // wrong width/num elts. This can happen for register classes that can
6869 // contain multiple different value types. The preg or vreg allocated may
6870 // not have the same VT as was expected. Convert it to the right type
6871 // with bit_convert.
6872 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6873 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6876 } else if (ResultType != Val.getValueType() &&
6877 ResultType.isInteger() && Val.getValueType().isInteger()) {
6878 // If a result value was tied to an input value, the computed result may
6879 // have a wider width than the expected result. Extract the relevant
6881 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6884 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6887 setValue(CS.getInstruction(), Val);
6888 // Don't need to use this as a chain in this case.
6889 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6893 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6895 // Process indirect outputs, first output all of the flagged copies out of
6897 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6898 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6899 const Value *Ptr = IndirectStoresToEmit[i].second;
6900 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6902 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6905 // Emit the non-flagged stores from the physregs.
6906 SmallVector<SDValue, 8> OutChains;
6907 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6908 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6909 StoresToEmit[i].first,
6910 getValue(StoresToEmit[i].second),
6911 MachinePointerInfo(StoresToEmit[i].second),
6913 OutChains.push_back(Val);
6916 if (!OutChains.empty())
6917 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6922 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6923 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6924 MVT::Other, getRoot(),
6925 getValue(I.getArgOperand(0)),
6926 DAG.getSrcValue(I.getArgOperand(0))));
6929 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6930 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6931 const DataLayout &DL = *TLI.getDataLayout();
6932 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6933 getRoot(), getValue(I.getOperand(0)),
6934 DAG.getSrcValue(I.getOperand(0)),
6935 DL.getABITypeAlignment(I.getType()));
6937 DAG.setRoot(V.getValue(1));
6940 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6941 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6942 MVT::Other, getRoot(),
6943 getValue(I.getArgOperand(0)),
6944 DAG.getSrcValue(I.getArgOperand(0))));
6947 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6948 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6949 MVT::Other, getRoot(),
6950 getValue(I.getArgOperand(0)),
6951 getValue(I.getArgOperand(1)),
6952 DAG.getSrcValue(I.getArgOperand(0)),
6953 DAG.getSrcValue(I.getArgOperand(1))));
6956 /// \brief Lower an argument list according to the target calling convention.
6958 /// \return A tuple of <return-value, token-chain>
6960 /// This is a helper for lowering intrinsics that follow a target calling
6961 /// convention or require stack pointer adjustment. Only a subset of the
6962 /// intrinsic's operands need to participate in the calling convention.
6963 std::pair<SDValue, SDValue>
6964 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6965 unsigned NumArgs, SDValue Callee,
6967 MachineBasicBlock *LandingPad) {
6968 TargetLowering::ArgListTy Args;
6969 Args.reserve(NumArgs);
6971 // Populate the argument list.
6972 // Attributes for args start at offset 1, after the return attribute.
6973 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6974 ArgI != ArgE; ++ArgI) {
6975 const Value *V = CS->getOperand(ArgI);
6977 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6979 TargetLowering::ArgListEntry Entry;
6980 Entry.Node = getValue(V);
6981 Entry.Ty = V->getType();
6982 Entry.setAttributes(&CS, AttrI);
6983 Args.push_back(Entry);
6986 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6987 TargetLowering::CallLoweringInfo CLI(DAG);
6988 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6989 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6990 .setDiscardResult(CS->use_empty());
6992 return lowerInvokable(CLI, LandingPad);
6995 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6996 /// or patchpoint target node's operand list.
6998 /// Constants are converted to TargetConstants purely as an optimization to
6999 /// avoid constant materialization and register allocation.
7001 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
7002 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
7003 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
7004 /// address materialization and register allocation, but may also be required
7005 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
7006 /// alloca in the entry block, then the runtime may assume that the alloca's
7007 /// StackMap location can be read immediately after compilation and that the
7008 /// location is valid at any point during execution (this is similar to the
7009 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
7010 /// only available in a register, then the runtime would need to trap when
7011 /// execution reaches the StackMap in order to read the alloca's location.
7012 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
7013 SmallVectorImpl<SDValue> &Ops,
7014 SelectionDAGBuilder &Builder) {
7015 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
7016 SDValue OpVal = Builder.getValue(CS.getArgument(i));
7017 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
7019 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
7021 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
7022 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
7023 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
7025 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
7027 Ops.push_back(OpVal);
7031 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
7032 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
7033 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
7034 // [live variables...])
7036 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
7038 SDValue Chain, InFlag, Callee, NullPtr;
7039 SmallVector<SDValue, 32> Ops;
7041 SDLoc DL = getCurSDLoc();
7042 Callee = getValue(CI.getCalledValue());
7043 NullPtr = DAG.getIntPtrConstant(0, true);
7045 // The stackmap intrinsic only records the live variables (the arguemnts
7046 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
7047 // intrinsic, this won't be lowered to a function call. This means we don't
7048 // have to worry about calling conventions and target specific lowering code.
7049 // Instead we perform the call lowering right here.
7051 // chain, flag = CALLSEQ_START(chain, 0)
7052 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
7053 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
7055 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
7056 InFlag = Chain.getValue(1);
7058 // Add the <id> and <numBytes> constants.
7059 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7060 Ops.push_back(DAG.getTargetConstant(
7061 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7062 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7063 Ops.push_back(DAG.getTargetConstant(
7064 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7066 // Push live variables for the stack map.
7067 addStackMapLiveVars(&CI, 2, Ops, *this);
7069 // We are not pushing any register mask info here on the operands list,
7070 // because the stackmap doesn't clobber anything.
7072 // Push the chain and the glue flag.
7073 Ops.push_back(Chain);
7074 Ops.push_back(InFlag);
7076 // Create the STACKMAP node.
7077 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7078 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
7079 Chain = SDValue(SM, 0);
7080 InFlag = Chain.getValue(1);
7082 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
7084 // Stackmaps don't generate values, so nothing goes into the NodeMap.
7086 // Set the root to the target-lowered call chain.
7089 // Inform the Frame Information that we have a stackmap in this function.
7090 FuncInfo.MF->getFrameInfo()->setHasStackMap();
7093 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
7094 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
7095 MachineBasicBlock *LandingPad) {
7096 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
7101 // [live variables...])
7103 CallingConv::ID CC = CS.getCallingConv();
7104 bool IsAnyRegCC = CC == CallingConv::AnyReg;
7105 bool HasDef = !CS->getType()->isVoidTy();
7106 SDValue Callee = getValue(CS->getOperand(2)); // <target>
7108 // Get the real number of arguments participating in the call <numArgs>
7109 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
7110 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
7112 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
7113 // Intrinsics include all meta-operands up to but not including CC.
7114 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7115 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
7116 "Not enough arguments provided to the patchpoint intrinsic");
7118 // For AnyRegCC the arguments are lowered later on manually.
7119 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
7120 std::pair<SDValue, SDValue> Result =
7121 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
7124 SDNode *CallEnd = Result.second.getNode();
7125 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7126 CallEnd = CallEnd->getOperand(0).getNode();
7128 /// Get a call instruction from the call sequence chain.
7129 /// Tail calls are not allowed.
7130 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7131 "Expected a callseq node.");
7132 SDNode *Call = CallEnd->getOperand(0).getNode();
7133 bool HasGlue = Call->getGluedNode();
7135 // Replace the target specific call node with the patchable intrinsic.
7136 SmallVector<SDValue, 8> Ops;
7138 // Add the <id> and <numBytes> constants.
7139 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
7140 Ops.push_back(DAG.getTargetConstant(
7141 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7142 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
7143 Ops.push_back(DAG.getTargetConstant(
7144 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7146 // Assume that the Callee is a constant address.
7147 // FIXME: handle function symbols in the future.
7149 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7150 /*isTarget=*/true));
7152 // Adjust <numArgs> to account for any arguments that have been passed on the
7154 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7155 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
7156 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
7157 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7159 // Add the calling convention
7160 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7162 // Add the arguments we omitted previously. The register allocator should
7163 // place these in any free register.
7165 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7166 Ops.push_back(getValue(CS.getArgument(i)));
7168 // Push the arguments from the call instruction up to the register mask.
7169 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
7170 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7173 // Push live variables for the stack map.
7174 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this);
7176 // Push the register mask info.
7178 Ops.push_back(*(Call->op_end()-2));
7180 Ops.push_back(*(Call->op_end()-1));
7182 // Push the chain (this is originally the first operand of the call, but
7183 // becomes now the last or second to last operand).
7184 Ops.push_back(*(Call->op_begin()));
7186 // Push the glue flag (last operand).
7188 Ops.push_back(*(Call->op_end()-1));
7191 if (IsAnyRegCC && HasDef) {
7192 // Create the return types based on the intrinsic definition
7193 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7194 SmallVector<EVT, 3> ValueVTs;
7195 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
7196 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7198 // There is always a chain and a glue type at the end
7199 ValueVTs.push_back(MVT::Other);
7200 ValueVTs.push_back(MVT::Glue);
7201 NodeTys = DAG.getVTList(ValueVTs);
7203 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7205 // Replace the target specific call node with a PATCHPOINT node.
7206 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7207 getCurSDLoc(), NodeTys, Ops);
7209 // Update the NodeMap.
7212 setValue(CS.getInstruction(), SDValue(MN, 0));
7214 setValue(CS.getInstruction(), Result.first);
7217 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7218 // call sequence. Furthermore the location of the chain and glue can change
7219 // when the AnyReg calling convention is used and the intrinsic returns a
7221 if (IsAnyRegCC && HasDef) {
7222 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7223 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7224 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7226 DAG.ReplaceAllUsesWith(Call, MN);
7227 DAG.DeleteNode(Call);
7229 // Inform the Frame Information that we have a patchpoint in this function.
7230 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7233 /// Returns an AttributeSet representing the attributes applied to the return
7234 /// value of the given call.
7235 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7236 SmallVector<Attribute::AttrKind, 2> Attrs;
7238 Attrs.push_back(Attribute::SExt);
7240 Attrs.push_back(Attribute::ZExt);
7242 Attrs.push_back(Attribute::InReg);
7244 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7248 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7249 /// implementation, which just calls LowerCall.
7250 /// FIXME: When all targets are
7251 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7252 std::pair<SDValue, SDValue>
7253 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7254 // Handle the incoming return values from the call.
7256 Type *OrigRetTy = CLI.RetTy;
7257 SmallVector<EVT, 4> RetTys;
7258 SmallVector<uint64_t, 4> Offsets;
7259 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7261 SmallVector<ISD::OutputArg, 4> Outs;
7262 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7264 bool CanLowerReturn =
7265 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7266 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7268 SDValue DemoteStackSlot;
7269 int DemoteStackIdx = -100;
7270 if (!CanLowerReturn) {
7271 // FIXME: equivalent assert?
7272 // assert(!CS.hasInAllocaArgument() &&
7273 // "sret demotion is incompatible with inalloca");
7274 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7275 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7276 MachineFunction &MF = CLI.DAG.getMachineFunction();
7277 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7278 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7280 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7282 Entry.Node = DemoteStackSlot;
7283 Entry.Ty = StackSlotPtrType;
7284 Entry.isSExt = false;
7285 Entry.isZExt = false;
7286 Entry.isInReg = false;
7287 Entry.isSRet = true;
7288 Entry.isNest = false;
7289 Entry.isByVal = false;
7290 Entry.isReturned = false;
7291 Entry.Alignment = Align;
7292 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7293 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7295 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7297 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7298 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7299 for (unsigned i = 0; i != NumRegs; ++i) {
7300 ISD::InputArg MyFlags;
7301 MyFlags.VT = RegisterVT;
7303 MyFlags.Used = CLI.IsReturnValueUsed;
7305 MyFlags.Flags.setSExt();
7307 MyFlags.Flags.setZExt();
7309 MyFlags.Flags.setInReg();
7310 CLI.Ins.push_back(MyFlags);
7315 // Handle all of the outgoing arguments.
7317 CLI.OutVals.clear();
7318 ArgListTy &Args = CLI.getArgs();
7319 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7320 SmallVector<EVT, 4> ValueVTs;
7321 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7322 Type *FinalType = Args[i].Ty;
7323 if (Args[i].isByVal)
7324 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7325 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7326 FinalType, CLI.CallConv, CLI.IsVarArg);
7327 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7329 EVT VT = ValueVTs[Value];
7330 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7331 SDValue Op = SDValue(Args[i].Node.getNode(),
7332 Args[i].Node.getResNo() + Value);
7333 ISD::ArgFlagsTy Flags;
7334 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7340 if (Args[i].isInReg)
7344 if (Args[i].isByVal)
7346 if (Args[i].isInAlloca) {
7347 Flags.setInAlloca();
7348 // Set the byval flag for CCAssignFn callbacks that don't know about
7349 // inalloca. This way we can know how many bytes we should've allocated
7350 // and how many bytes a callee cleanup function will pop. If we port
7351 // inalloca to more targets, we'll have to add custom inalloca handling
7352 // in the various CC lowering callbacks.
7355 if (Args[i].isByVal || Args[i].isInAlloca) {
7356 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7357 Type *ElementTy = Ty->getElementType();
7358 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7359 // For ByVal, alignment should come from FE. BE will guess if this
7360 // info is not there but there are cases it cannot get right.
7361 unsigned FrameAlign;
7362 if (Args[i].Alignment)
7363 FrameAlign = Args[i].Alignment;
7365 FrameAlign = getByValTypeAlignment(ElementTy);
7366 Flags.setByValAlign(FrameAlign);
7370 if (NeedsRegBlock) {
7371 Flags.setInConsecutiveRegs();
7372 if (Value == NumValues - 1)
7373 Flags.setInConsecutiveRegsLast();
7375 Flags.setOrigAlign(OriginalAlignment);
7377 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7378 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7379 SmallVector<SDValue, 4> Parts(NumParts);
7380 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7383 ExtendKind = ISD::SIGN_EXTEND;
7384 else if (Args[i].isZExt)
7385 ExtendKind = ISD::ZERO_EXTEND;
7387 // Conservatively only handle 'returned' on non-vectors for now
7388 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7389 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7390 "unexpected use of 'returned'");
7391 // Before passing 'returned' to the target lowering code, ensure that
7392 // either the register MVT and the actual EVT are the same size or that
7393 // the return value and argument are extended in the same way; in these
7394 // cases it's safe to pass the argument register value unchanged as the
7395 // return register value (although it's at the target's option whether
7397 // TODO: allow code generation to take advantage of partially preserved
7398 // registers rather than clobbering the entire register when the
7399 // parameter extension method is not compatible with the return
7401 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7402 (ExtendKind != ISD::ANY_EXTEND &&
7403 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7404 Flags.setReturned();
7407 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7408 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7410 for (unsigned j = 0; j != NumParts; ++j) {
7411 // if it isn't first piece, alignment must be 1
7412 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7413 i < CLI.NumFixedArgs,
7414 i, j*Parts[j].getValueType().getStoreSize());
7415 if (NumParts > 1 && j == 0)
7416 MyFlags.Flags.setSplit();
7418 MyFlags.Flags.setOrigAlign(1);
7420 CLI.Outs.push_back(MyFlags);
7421 CLI.OutVals.push_back(Parts[j]);
7426 SmallVector<SDValue, 4> InVals;
7427 CLI.Chain = LowerCall(CLI, InVals);
7429 // Verify that the target's LowerCall behaved as expected.
7430 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7431 "LowerCall didn't return a valid chain!");
7432 assert((!CLI.IsTailCall || InVals.empty()) &&
7433 "LowerCall emitted a return value for a tail call!");
7434 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7435 "LowerCall didn't emit the correct number of values!");
7437 // For a tail call, the return value is merely live-out and there aren't
7438 // any nodes in the DAG representing it. Return a special value to
7439 // indicate that a tail call has been emitted and no more Instructions
7440 // should be processed in the current block.
7441 if (CLI.IsTailCall) {
7442 CLI.DAG.setRoot(CLI.Chain);
7443 return std::make_pair(SDValue(), SDValue());
7446 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7447 assert(InVals[i].getNode() &&
7448 "LowerCall emitted a null value!");
7449 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7450 "LowerCall emitted a value with the wrong type!");
7453 SmallVector<SDValue, 4> ReturnValues;
7454 if (!CanLowerReturn) {
7455 // The instruction result is the result of loading from the
7456 // hidden sret parameter.
7457 SmallVector<EVT, 1> PVTs;
7458 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7460 ComputeValueVTs(*this, PtrRetTy, PVTs);
7461 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7462 EVT PtrVT = PVTs[0];
7464 unsigned NumValues = RetTys.size();
7465 ReturnValues.resize(NumValues);
7466 SmallVector<SDValue, 4> Chains(NumValues);
7468 for (unsigned i = 0; i < NumValues; ++i) {
7469 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7470 CLI.DAG.getConstant(Offsets[i], PtrVT));
7471 SDValue L = CLI.DAG.getLoad(
7472 RetTys[i], CLI.DL, CLI.Chain, Add,
7473 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7475 ReturnValues[i] = L;
7476 Chains[i] = L.getValue(1);
7479 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7481 // Collect the legal value parts into potentially illegal values
7482 // that correspond to the original function's return values.
7483 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7485 AssertOp = ISD::AssertSext;
7486 else if (CLI.RetZExt)
7487 AssertOp = ISD::AssertZext;
7488 unsigned CurReg = 0;
7489 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7491 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7492 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7494 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7495 NumRegs, RegisterVT, VT, nullptr,
7500 // For a function returning void, there is no return value. We can't create
7501 // such a node, so we just return a null return value in that case. In
7502 // that case, nothing will actually look at the value.
7503 if (ReturnValues.empty())
7504 return std::make_pair(SDValue(), CLI.Chain);
7507 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7508 CLI.DAG.getVTList(RetTys), ReturnValues);
7509 return std::make_pair(Res, CLI.Chain);
7512 void TargetLowering::LowerOperationWrapper(SDNode *N,
7513 SmallVectorImpl<SDValue> &Results,
7514 SelectionDAG &DAG) const {
7515 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7517 Results.push_back(Res);
7520 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7521 llvm_unreachable("LowerOperation not implemented for this target!");
7525 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7526 SDValue Op = getNonRegisterValue(V);
7527 assert((Op.getOpcode() != ISD::CopyFromReg ||
7528 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7529 "Copy from a reg to the same reg!");
7530 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7532 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7533 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7534 SDValue Chain = DAG.getEntryNode();
7536 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7537 FuncInfo.PreferredExtendType.end())
7539 : FuncInfo.PreferredExtendType[V];
7540 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7541 PendingExports.push_back(Chain);
7544 #include "llvm/CodeGen/SelectionDAGISel.h"
7546 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7547 /// entry block, return true. This includes arguments used by switches, since
7548 /// the switch may expand into multiple basic blocks.
7549 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7550 // With FastISel active, we may be splitting blocks, so force creation
7551 // of virtual registers for all non-dead arguments.
7553 return A->use_empty();
7555 const BasicBlock *Entry = A->getParent()->begin();
7556 for (const User *U : A->users())
7557 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7558 return false; // Use not in entry block.
7563 void SelectionDAGISel::LowerArguments(const Function &F) {
7564 SelectionDAG &DAG = SDB->DAG;
7565 SDLoc dl = SDB->getCurSDLoc();
7566 const DataLayout *DL = TLI->getDataLayout();
7567 SmallVector<ISD::InputArg, 16> Ins;
7569 if (!FuncInfo->CanLowerReturn) {
7570 // Put in an sret pointer parameter before all the other parameters.
7571 SmallVector<EVT, 1> ValueVTs;
7572 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7574 // NOTE: Assuming that a pointer will never break down to more than one VT
7576 ISD::ArgFlagsTy Flags;
7578 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7579 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7580 Ins.push_back(RetArg);
7583 // Set up the incoming argument description vector.
7585 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7586 I != E; ++I, ++Idx) {
7587 SmallVector<EVT, 4> ValueVTs;
7588 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7589 bool isArgValueUsed = !I->use_empty();
7590 unsigned PartBase = 0;
7591 Type *FinalType = I->getType();
7592 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7593 FinalType = cast<PointerType>(FinalType)->getElementType();
7594 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7595 FinalType, F.getCallingConv(), F.isVarArg());
7596 for (unsigned Value = 0, NumValues = ValueVTs.size();
7597 Value != NumValues; ++Value) {
7598 EVT VT = ValueVTs[Value];
7599 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7600 ISD::ArgFlagsTy Flags;
7601 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7603 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7605 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7607 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7609 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7611 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7613 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7614 Flags.setInAlloca();
7615 // Set the byval flag for CCAssignFn callbacks that don't know about
7616 // inalloca. This way we can know how many bytes we should've allocated
7617 // and how many bytes a callee cleanup function will pop. If we port
7618 // inalloca to more targets, we'll have to add custom inalloca handling
7619 // in the various CC lowering callbacks.
7622 if (Flags.isByVal() || Flags.isInAlloca()) {
7623 PointerType *Ty = cast<PointerType>(I->getType());
7624 Type *ElementTy = Ty->getElementType();
7625 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7626 // For ByVal, alignment should be passed from FE. BE will guess if
7627 // this info is not there but there are cases it cannot get right.
7628 unsigned FrameAlign;
7629 if (F.getParamAlignment(Idx))
7630 FrameAlign = F.getParamAlignment(Idx);
7632 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7633 Flags.setByValAlign(FrameAlign);
7635 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7637 if (NeedsRegBlock) {
7638 Flags.setInConsecutiveRegs();
7639 if (Value == NumValues - 1)
7640 Flags.setInConsecutiveRegsLast();
7642 Flags.setOrigAlign(OriginalAlignment);
7644 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7645 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7646 for (unsigned i = 0; i != NumRegs; ++i) {
7647 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7648 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7649 if (NumRegs > 1 && i == 0)
7650 MyFlags.Flags.setSplit();
7651 // if it isn't first piece, alignment must be 1
7653 MyFlags.Flags.setOrigAlign(1);
7654 Ins.push_back(MyFlags);
7656 PartBase += VT.getStoreSize();
7660 // Call the target to set up the argument values.
7661 SmallVector<SDValue, 8> InVals;
7662 SDValue NewRoot = TLI->LowerFormalArguments(
7663 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7665 // Verify that the target's LowerFormalArguments behaved as expected.
7666 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7667 "LowerFormalArguments didn't return a valid chain!");
7668 assert(InVals.size() == Ins.size() &&
7669 "LowerFormalArguments didn't emit the correct number of values!");
7671 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7672 assert(InVals[i].getNode() &&
7673 "LowerFormalArguments emitted a null value!");
7674 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7675 "LowerFormalArguments emitted a value with the wrong type!");
7679 // Update the DAG with the new chain value resulting from argument lowering.
7680 DAG.setRoot(NewRoot);
7682 // Set up the argument values.
7685 if (!FuncInfo->CanLowerReturn) {
7686 // Create a virtual register for the sret pointer, and put in a copy
7687 // from the sret argument into it.
7688 SmallVector<EVT, 1> ValueVTs;
7689 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7690 MVT VT = ValueVTs[0].getSimpleVT();
7691 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7692 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7693 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7694 RegVT, VT, nullptr, AssertOp);
7696 MachineFunction& MF = SDB->DAG.getMachineFunction();
7697 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7698 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7699 FuncInfo->DemoteRegister = SRetReg;
7701 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7702 DAG.setRoot(NewRoot);
7704 // i indexes lowered arguments. Bump it past the hidden sret argument.
7705 // Idx indexes LLVM arguments. Don't touch it.
7709 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7711 SmallVector<SDValue, 4> ArgValues;
7712 SmallVector<EVT, 4> ValueVTs;
7713 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7714 unsigned NumValues = ValueVTs.size();
7716 // If this argument is unused then remember its value. It is used to generate
7717 // debugging information.
7718 if (I->use_empty() && NumValues) {
7719 SDB->setUnusedArgValue(I, InVals[i]);
7721 // Also remember any frame index for use in FastISel.
7722 if (FrameIndexSDNode *FI =
7723 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7724 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7727 for (unsigned Val = 0; Val != NumValues; ++Val) {
7728 EVT VT = ValueVTs[Val];
7729 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7730 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7732 if (!I->use_empty()) {
7733 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7734 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7735 AssertOp = ISD::AssertSext;
7736 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7737 AssertOp = ISD::AssertZext;
7739 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7740 NumParts, PartVT, VT,
7741 nullptr, AssertOp));
7747 // We don't need to do anything else for unused arguments.
7748 if (ArgValues.empty())
7751 // Note down frame index.
7752 if (FrameIndexSDNode *FI =
7753 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7754 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7756 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7757 SDB->getCurSDLoc());
7759 SDB->setValue(I, Res);
7760 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7761 if (LoadSDNode *LNode =
7762 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7763 if (FrameIndexSDNode *FI =
7764 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7765 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7768 // If this argument is live outside of the entry block, insert a copy from
7769 // wherever we got it to the vreg that other BB's will reference it as.
7770 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7771 // If we can, though, try to skip creating an unnecessary vreg.
7772 // FIXME: This isn't very clean... it would be nice to make this more
7773 // general. It's also subtly incompatible with the hacks FastISel
7775 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7776 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7777 FuncInfo->ValueMap[I] = Reg;
7781 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7782 FuncInfo->InitializeRegForValue(I);
7783 SDB->CopyToExportRegsIfNeeded(I);
7787 assert(i == InVals.size() && "Argument register count mismatch!");
7789 // Finally, if the target has anything special to do, allow it to do so.
7790 // FIXME: this should insert code into the DAG!
7791 EmitFunctionEntryCode();
7794 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7795 /// ensure constants are generated when needed. Remember the virtual registers
7796 /// that need to be added to the Machine PHI nodes as input. We cannot just
7797 /// directly add them, because expansion might result in multiple MBB's for one
7798 /// BB. As such, the start of the BB might correspond to a different MBB than
7802 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7803 const TerminatorInst *TI = LLVMBB->getTerminator();
7805 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7807 // Check successor nodes' PHI nodes that expect a constant to be available
7809 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7810 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7811 if (!isa<PHINode>(SuccBB->begin())) continue;
7812 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7814 // If this terminator has multiple identical successors (common for
7815 // switches), only handle each succ once.
7816 if (!SuccsHandled.insert(SuccMBB).second)
7819 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7821 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7822 // nodes and Machine PHI nodes, but the incoming operands have not been
7824 for (BasicBlock::const_iterator I = SuccBB->begin();
7825 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7826 // Ignore dead phi's.
7827 if (PN->use_empty()) continue;
7830 if (PN->getType()->isEmptyTy())
7834 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7836 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7837 unsigned &RegOut = ConstantsOut[C];
7839 RegOut = FuncInfo.CreateRegs(C->getType());
7840 CopyValueToVirtualRegister(C, RegOut);
7844 DenseMap<const Value *, unsigned>::iterator I =
7845 FuncInfo.ValueMap.find(PHIOp);
7846 if (I != FuncInfo.ValueMap.end())
7849 assert(isa<AllocaInst>(PHIOp) &&
7850 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7851 "Didn't codegen value into a register!??");
7852 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7853 CopyValueToVirtualRegister(PHIOp, Reg);
7857 // Remember that this register needs to added to the machine PHI node as
7858 // the input for this MBB.
7859 SmallVector<EVT, 4> ValueVTs;
7860 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7861 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7862 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7863 EVT VT = ValueVTs[vti];
7864 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7865 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7866 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7867 Reg += NumRegisters;
7872 ConstantsOut.clear();
7875 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7878 SelectionDAGBuilder::StackProtectorDescriptor::
7879 AddSuccessorMBB(const BasicBlock *BB,
7880 MachineBasicBlock *ParentMBB,
7882 MachineBasicBlock *SuccMBB) {
7883 // If SuccBB has not been created yet, create it.
7885 MachineFunction *MF = ParentMBB->getParent();
7886 MachineFunction::iterator BBI = ParentMBB;
7887 SuccMBB = MF->CreateMachineBasicBlock(BB);
7888 MF->insert(++BBI, SuccMBB);
7890 // Add it as a successor of ParentMBB.
7891 ParentMBB->addSuccessor(
7892 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));