1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/ValueTracking.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/DebugInfo.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/InlineAsm.h"
45 #include "llvm/IR/Instructions.h"
46 #include "llvm/IR/IntrinsicInst.h"
47 #include "llvm/IR/Intrinsics.h"
48 #include "llvm/IR/LLVMContext.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/IR/Statepoint.h"
51 #include "llvm/MC/MCSymbol.h"
52 #include "llvm/Support/CommandLine.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/MathExtras.h"
56 #include "llvm/Support/raw_ostream.h"
57 #include "llvm/Target/TargetFrameLowering.h"
58 #include "llvm/Target/TargetInstrInfo.h"
59 #include "llvm/Target/TargetIntrinsicInfo.h"
60 #include "llvm/Target/TargetLibraryInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
81 // Limit the width of DAG chains. This is important in general to prevent
82 // prevent DAG-based analysis from blowing up. For example, alias analysis and
83 // load clustering may not complete in reasonable time. It is difficult to
84 // recognize and avoid this situation within each individual analysis, and
85 // future analyses are likely to have the same behavior. Limiting DAG width is
86 // the safe approach, and will be especially important with global DAGs.
88 // MaxParallelChains default is arbitrarily high to avoid affecting
89 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
90 // sequence over this should have been converted to llvm.memcpy by the
91 // frontend. It easy to induce this behavior with .ll code such as:
92 // %buffer = alloca [4096 x i8]
93 // %data = load [4096 x i8]* %argPtr
94 // store [4096 x i8] %data, [4096 x i8]* %buffer
95 static const unsigned MaxParallelChains = 64;
97 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
98 const SDValue *Parts, unsigned NumParts,
99 MVT PartVT, EVT ValueVT, const Value *V);
101 /// getCopyFromParts - Create a value that contains the specified legal parts
102 /// combined into the value they represent. If the parts combine to a type
103 /// larger then ValueVT then AssertOp can be used to specify whether the extra
104 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
105 /// (ISD::AssertSext).
106 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
107 const SDValue *Parts,
108 unsigned NumParts, MVT PartVT, EVT ValueVT,
110 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
111 if (ValueVT.isVector())
112 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
115 assert(NumParts > 0 && "No parts to assemble!");
116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
117 SDValue Val = Parts[0];
120 // Assemble the value from multiple parts.
121 if (ValueVT.isInteger()) {
122 unsigned PartBits = PartVT.getSizeInBits();
123 unsigned ValueBits = ValueVT.getSizeInBits();
125 // Assemble the power of 2 part.
126 unsigned RoundParts = NumParts & (NumParts - 1) ?
127 1 << Log2_32(NumParts) : NumParts;
128 unsigned RoundBits = PartBits * RoundParts;
129 EVT RoundVT = RoundBits == ValueBits ?
130 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
133 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
135 if (RoundParts > 2) {
136 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
138 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
139 RoundParts / 2, PartVT, HalfVT, V);
141 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
142 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
145 if (TLI.isBigEndian())
148 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
150 if (RoundParts < NumParts) {
151 // Assemble the trailing non-power-of-2 part.
152 unsigned OddParts = NumParts - RoundParts;
153 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
154 Hi = getCopyFromParts(DAG, DL,
155 Parts + RoundParts, OddParts, PartVT, OddVT, V);
157 // Combine the round and odd parts.
159 if (TLI.isBigEndian())
161 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
162 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
163 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
164 DAG.getConstant(Lo.getValueType().getSizeInBits(),
165 TLI.getPointerTy()));
166 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
167 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
169 } else if (PartVT.isFloatingPoint()) {
170 // FP split into multiple FP parts (for ppcf128)
171 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
174 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
175 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
176 if (TLI.hasBigEndianPartOrdering(ValueVT))
178 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
180 // FP split into integer parts (soft fp)
181 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
182 !PartVT.isVector() && "Unexpected split");
183 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
184 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
188 // There is now one part, held in Val. Correct it to match ValueVT.
189 EVT PartEVT = Val.getValueType();
191 if (PartEVT == ValueVT)
194 if (PartEVT.isInteger() && ValueVT.isInteger()) {
195 if (ValueVT.bitsLT(PartEVT)) {
196 // For a truncate, see if we have any information to
197 // indicate whether the truncated bits will always be
198 // zero or sign-extension.
199 if (AssertOp != ISD::DELETED_NODE)
200 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
201 DAG.getValueType(ValueVT));
202 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
204 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
207 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
208 // FP_ROUND's are always exact here.
209 if (ValueVT.bitsLT(Val.getValueType()))
210 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
211 DAG.getTargetConstant(1, TLI.getPointerTy()));
213 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
216 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
217 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
219 llvm_unreachable("Unknown mismatch!");
222 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
223 const Twine &ErrMsg) {
224 const Instruction *I = dyn_cast_or_null<Instruction>(V);
226 return Ctx.emitError(ErrMsg);
228 const char *AsmError = ", possible invalid constraint for vector type";
229 if (const CallInst *CI = dyn_cast<CallInst>(I))
230 if (isa<InlineAsm>(CI->getCalledValue()))
231 return Ctx.emitError(I, ErrMsg + AsmError);
233 return Ctx.emitError(I, ErrMsg);
236 /// getCopyFromPartsVector - Create a value that contains the specified legal
237 /// parts combined into the value they represent. If the parts combine to a
238 /// type larger then ValueVT then AssertOp can be used to specify whether the
239 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
240 /// ValueVT (ISD::AssertSext).
241 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
242 const SDValue *Parts, unsigned NumParts,
243 MVT PartVT, EVT ValueVT, const Value *V) {
244 assert(ValueVT.isVector() && "Not a vector value");
245 assert(NumParts > 0 && "No parts to assemble!");
246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
247 SDValue Val = Parts[0];
249 // Handle a multi-element vector.
253 unsigned NumIntermediates;
255 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
256 NumIntermediates, RegisterVT);
257 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
258 NumParts = NumRegs; // Silence a compiler warning.
259 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
260 assert(RegisterVT == Parts[0].getSimpleValueType() &&
261 "Part type doesn't match part!");
263 // Assemble the parts into intermediate operands.
264 SmallVector<SDValue, 8> Ops(NumIntermediates);
265 if (NumIntermediates == NumParts) {
266 // If the register was not expanded, truncate or copy the value,
268 for (unsigned i = 0; i != NumParts; ++i)
269 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
270 PartVT, IntermediateVT, V);
271 } else if (NumParts > 0) {
272 // If the intermediate type was expanded, build the intermediate
273 // operands from the parts.
274 assert(NumParts % NumIntermediates == 0 &&
275 "Must expand into a divisible number of parts!");
276 unsigned Factor = NumParts / NumIntermediates;
277 for (unsigned i = 0; i != NumIntermediates; ++i)
278 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
279 PartVT, IntermediateVT, V);
282 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
283 // intermediate operands.
284 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
289 // There is now one part, held in Val. Correct it to match ValueVT.
290 EVT PartEVT = Val.getValueType();
292 if (PartEVT == ValueVT)
295 if (PartEVT.isVector()) {
296 // If the element type of the source/dest vectors are the same, but the
297 // parts vector has more elements than the value vector, then we have a
298 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
300 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
301 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
302 "Cannot narrow, it would be a lossy transformation");
303 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
304 DAG.getConstant(0, TLI.getVectorIdxTy()));
307 // Vector/Vector bitcast.
308 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
309 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
311 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
312 "Cannot handle this kind of promotion");
313 // Promoted vector extract
314 bool Smaller = ValueVT.bitsLE(PartEVT);
315 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
320 // Trivial bitcast if the types are the same size and the destination
321 // vector type is legal.
322 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
323 TLI.isTypeLegal(ValueVT))
324 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
326 // Handle cases such as i8 -> <1 x i1>
327 if (ValueVT.getVectorNumElements() != 1) {
328 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
329 "non-trivial scalar-to-vector conversion");
330 return DAG.getUNDEF(ValueVT);
333 if (ValueVT.getVectorNumElements() == 1 &&
334 ValueVT.getVectorElementType() != PartEVT) {
335 bool Smaller = ValueVT.bitsLE(PartEVT);
336 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
337 DL, ValueVT.getScalarType(), Val);
340 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
343 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
344 SDValue Val, SDValue *Parts, unsigned NumParts,
345 MVT PartVT, const Value *V);
347 /// getCopyToParts - Create a series of nodes that contain the specified value
348 /// split into legal parts. If the parts contain more bits than Val, then, for
349 /// integers, ExtendKind can be used to specify how to generate the extra bits.
350 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
351 SDValue Val, SDValue *Parts, unsigned NumParts,
352 MVT PartVT, const Value *V,
353 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
354 EVT ValueVT = Val.getValueType();
356 // Handle the vector case separately.
357 if (ValueVT.isVector())
358 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
360 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
361 unsigned PartBits = PartVT.getSizeInBits();
362 unsigned OrigNumParts = NumParts;
363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
368 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
369 EVT PartEVT = PartVT;
370 if (PartEVT == ValueVT) {
371 assert(NumParts == 1 && "No-op copy with multiple parts!");
376 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
377 // If the parts cover more bits than the value has, promote the value.
378 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
379 assert(NumParts == 1 && "Do not know what to promote to!");
380 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
382 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
383 ValueVT.isInteger() &&
384 "Unknown mismatch!");
385 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
386 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
387 if (PartVT == MVT::x86mmx)
388 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
390 } else if (PartBits == ValueVT.getSizeInBits()) {
391 // Different types of the same size.
392 assert(NumParts == 1 && PartEVT != ValueVT);
393 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
395 // If the parts cover less bits than value has, truncate the value.
396 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
397 ValueVT.isInteger() &&
398 "Unknown mismatch!");
399 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
400 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
401 if (PartVT == MVT::x86mmx)
402 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
405 // The value may have changed - recompute ValueVT.
406 ValueVT = Val.getValueType();
407 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
408 "Failed to tile the value with PartVT!");
411 if (PartEVT != ValueVT)
412 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
413 "scalar-to-vector conversion failed");
419 // Expand the value into multiple parts.
420 if (NumParts & (NumParts - 1)) {
421 // The number of parts is not a power of 2. Split off and copy the tail.
422 assert(PartVT.isInteger() && ValueVT.isInteger() &&
423 "Do not know what to expand to!");
424 unsigned RoundParts = 1 << Log2_32(NumParts);
425 unsigned RoundBits = RoundParts * PartBits;
426 unsigned OddParts = NumParts - RoundParts;
427 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
428 DAG.getIntPtrConstant(RoundBits));
429 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
431 if (TLI.isBigEndian())
432 // The odd parts were reversed by getCopyToParts - unreverse them.
433 std::reverse(Parts + RoundParts, Parts + NumParts);
435 NumParts = RoundParts;
436 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
437 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
440 // The number of parts is a power of 2. Repeatedly bisect the value using
442 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
443 EVT::getIntegerVT(*DAG.getContext(),
444 ValueVT.getSizeInBits()),
447 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
448 for (unsigned i = 0; i < NumParts; i += StepSize) {
449 unsigned ThisBits = StepSize * PartBits / 2;
450 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
451 SDValue &Part0 = Parts[i];
452 SDValue &Part1 = Parts[i+StepSize/2];
454 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
455 ThisVT, Part0, DAG.getIntPtrConstant(1));
456 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
457 ThisVT, Part0, DAG.getIntPtrConstant(0));
459 if (ThisBits == PartBits && ThisVT != PartVT) {
460 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
461 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
466 if (TLI.isBigEndian())
467 std::reverse(Parts, Parts + OrigNumParts);
471 /// getCopyToPartsVector - Create a series of nodes that contain the specified
472 /// value split into legal parts.
473 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
474 SDValue Val, SDValue *Parts, unsigned NumParts,
475 MVT PartVT, const Value *V) {
476 EVT ValueVT = Val.getValueType();
477 assert(ValueVT.isVector() && "Not a vector");
478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
481 EVT PartEVT = PartVT;
482 if (PartEVT == ValueVT) {
484 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
485 // Bitconvert vector->vector case.
486 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
487 } else if (PartVT.isVector() &&
488 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
489 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
490 EVT ElementVT = PartVT.getVectorElementType();
491 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
493 SmallVector<SDValue, 16> Ops;
494 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
495 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
496 ElementVT, Val, DAG.getConstant(i,
497 TLI.getVectorIdxTy())));
499 for (unsigned i = ValueVT.getVectorNumElements(),
500 e = PartVT.getVectorNumElements(); i != e; ++i)
501 Ops.push_back(DAG.getUNDEF(ElementVT));
503 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
505 // FIXME: Use CONCAT for 2x -> 4x.
507 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
508 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
509 } else if (PartVT.isVector() &&
510 PartEVT.getVectorElementType().bitsGE(
511 ValueVT.getVectorElementType()) &&
512 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
514 // Promoted vector extract
515 bool Smaller = PartEVT.bitsLE(ValueVT);
516 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
519 // Vector -> scalar conversion.
520 assert(ValueVT.getVectorNumElements() == 1 &&
521 "Only trivial vector-to-scalar conversions should get here!");
522 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
523 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
525 bool Smaller = ValueVT.bitsLE(PartVT);
526 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
534 // Handle a multi-element vector.
537 unsigned NumIntermediates;
538 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
540 NumIntermediates, RegisterVT);
541 unsigned NumElements = ValueVT.getVectorNumElements();
543 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
544 NumParts = NumRegs; // Silence a compiler warning.
545 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
547 // Split the vector into intermediate operands.
548 SmallVector<SDValue, 8> Ops(NumIntermediates);
549 for (unsigned i = 0; i != NumIntermediates; ++i) {
550 if (IntermediateVT.isVector())
551 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
553 DAG.getConstant(i * (NumElements / NumIntermediates),
554 TLI.getVectorIdxTy()));
556 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
558 DAG.getConstant(i, TLI.getVectorIdxTy()));
561 // Split the intermediate operands into legal parts.
562 if (NumParts == NumIntermediates) {
563 // If the register was not expanded, promote or copy the value,
565 for (unsigned i = 0; i != NumParts; ++i)
566 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
567 } else if (NumParts > 0) {
568 // If the intermediate type was expanded, split each the value into
570 assert(NumIntermediates != 0 && "division by zero");
571 assert(NumParts % NumIntermediates == 0 &&
572 "Must expand into a divisible number of parts!");
573 unsigned Factor = NumParts / NumIntermediates;
574 for (unsigned i = 0; i != NumIntermediates; ++i)
575 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 /// RegsForValue - This struct represents the registers (physical or virtual)
581 /// that a particular set of values is assigned, and the type information
582 /// about the value. The most common situation is to represent one value at a
583 /// time, but struct or array values are handled element-wise as multiple
584 /// values. The splitting of aggregates is performed recursively, so that we
585 /// never have aggregate-typed registers. The values at this point do not
586 /// necessarily have legal types, so each value may require one or more
587 /// registers of some legal type.
589 struct RegsForValue {
590 /// ValueVTs - The value types of the values, which may not be legal, and
591 /// may need be promoted or synthesized from one or more registers.
593 SmallVector<EVT, 4> ValueVTs;
595 /// RegVTs - The value types of the registers. This is the same size as
596 /// ValueVTs and it records, for each value, what the type of the assigned
597 /// register or registers are. (Individual values are never synthesized
598 /// from more than one type of register.)
600 /// With virtual registers, the contents of RegVTs is redundant with TLI's
601 /// getRegisterType member function, however when with physical registers
602 /// it is necessary to have a separate record of the types.
604 SmallVector<MVT, 4> RegVTs;
606 /// Regs - This list holds the registers assigned to the values.
607 /// Each legal or promoted value requires one register, and each
608 /// expanded value requires multiple registers.
610 SmallVector<unsigned, 4> Regs;
614 RegsForValue(const SmallVector<unsigned, 4> ®s,
615 MVT regvt, EVT valuevt)
616 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
618 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
619 unsigned Reg, Type *Ty) {
620 ComputeValueVTs(tli, Ty, ValueVTs);
622 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
623 EVT ValueVT = ValueVTs[Value];
624 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
625 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
626 for (unsigned i = 0; i != NumRegs; ++i)
627 Regs.push_back(Reg + i);
628 RegVTs.push_back(RegisterVT);
633 /// append - Add the specified values to this one.
634 void append(const RegsForValue &RHS) {
635 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
636 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
637 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
640 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
641 /// this value and returns the result as a ValueVTs value. This uses
642 /// Chain/Flag as the input and updates them for the output Chain/Flag.
643 /// If the Flag pointer is NULL, no flag is used.
644 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
646 SDValue &Chain, SDValue *Flag,
647 const Value *V = nullptr) const;
649 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
650 /// specified value into the registers specified by this object. This uses
651 /// Chain/Flag as the input and updates them for the output Chain/Flag.
652 /// If the Flag pointer is NULL, no flag is used.
654 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
655 SDValue *Flag, const Value *V,
656 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
659 /// operand list. This adds the code marker, matching input operand index
660 /// (if applicable), and includes the number of values added into it.
661 void AddInlineAsmOperands(unsigned Kind,
662 bool HasMatching, unsigned MatchingIdx,
664 std::vector<SDValue> &Ops) const;
668 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
669 /// this value and returns the result as a ValueVT value. This uses
670 /// Chain/Flag as the input and updates them for the output Chain/Flag.
671 /// If the Flag pointer is NULL, no flag is used.
672 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
673 FunctionLoweringInfo &FuncInfo,
675 SDValue &Chain, SDValue *Flag,
676 const Value *V) const {
677 // A Value with type {} or [0 x %t] needs no registers.
678 if (ValueVTs.empty())
681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
683 // Assemble the legal parts into the final values.
684 SmallVector<SDValue, 4> Values(ValueVTs.size());
685 SmallVector<SDValue, 8> Parts;
686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
687 // Copy the legal parts from the registers.
688 EVT ValueVT = ValueVTs[Value];
689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
690 MVT RegisterVT = RegVTs[Value];
692 Parts.resize(NumRegs);
693 for (unsigned i = 0; i != NumRegs; ++i) {
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
699 *Flag = P.getValue(2);
702 Chain = P.getValue(1);
705 // If the source register was virtual and if we know something about it,
706 // add an assert node.
707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
708 !RegisterVT.isInteger() || RegisterVT.isVector())
711 const FunctionLoweringInfo::LiveOutInfo *LOI =
712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
716 unsigned RegSize = RegisterVT.getSizeInBits();
717 unsigned NumSignBits = LOI->NumSignBits;
718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
720 if (NumZeroBits == RegSize) {
721 // The current value is a zero.
722 // Explicitly express that as it would be easier for
723 // optimizations to kick in.
724 Parts[i] = DAG.getConstant(0, RegisterVT);
728 // FIXME: We capture more information than the dag can represent. For
729 // now, just use the tightest assertzext/assertsext possible.
731 EVT FromVT(MVT::Other);
732 if (NumSignBits == RegSize)
733 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
734 else if (NumZeroBits >= RegSize-1)
735 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
736 else if (NumSignBits > RegSize-8)
737 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
738 else if (NumZeroBits >= RegSize-8)
739 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
740 else if (NumSignBits > RegSize-16)
741 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
742 else if (NumZeroBits >= RegSize-16)
743 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
744 else if (NumSignBits > RegSize-32)
745 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
746 else if (NumZeroBits >= RegSize-32)
747 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
751 // Add an assertion node.
752 assert(FromVT != MVT::Other);
753 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
754 RegisterVT, P, DAG.getValueType(FromVT));
757 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
758 NumRegs, RegisterVT, ValueVT, V);
763 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
766 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
767 /// specified value into the registers specified by this object. This uses
768 /// Chain/Flag as the input and updates them for the output Chain/Flag.
769 /// If the Flag pointer is NULL, no flag is used.
770 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
771 SDValue &Chain, SDValue *Flag, const Value *V,
772 ISD::NodeType PreferredExtendType) const {
773 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
774 ISD::NodeType ExtendKind = PreferredExtendType;
776 // Get the list of the values's legal parts.
777 unsigned NumRegs = Regs.size();
778 SmallVector<SDValue, 8> Parts(NumRegs);
779 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
780 EVT ValueVT = ValueVTs[Value];
781 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
782 MVT RegisterVT = RegVTs[Value];
784 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
785 ExtendKind = ISD::ZERO_EXTEND;
787 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
788 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
792 // Copy the parts into the registers.
793 SmallVector<SDValue, 8> Chains(NumRegs);
794 for (unsigned i = 0; i != NumRegs; ++i) {
797 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
799 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
800 *Flag = Part.getValue(1);
803 Chains[i] = Part.getValue(0);
806 if (NumRegs == 1 || Flag)
807 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
808 // flagged to it. That is the CopyToReg nodes and the user are considered
809 // a single scheduling unit. If we create a TokenFactor and return it as
810 // chain, then the TokenFactor is both a predecessor (operand) of the
811 // user as well as a successor (the TF operands are flagged to the user).
812 // c1, f1 = CopyToReg
813 // c2, f2 = CopyToReg
814 // c3 = TokenFactor c1, c2
817 Chain = Chains[NumRegs-1];
819 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
822 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
823 /// operand list. This adds the code marker and includes the number of
824 /// values added into it.
825 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
826 unsigned MatchingIdx,
828 std::vector<SDValue> &Ops) const {
829 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
831 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
833 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
834 else if (!Regs.empty() &&
835 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
836 // Put the register class of the virtual registers in the flag word. That
837 // way, later passes can recompute register class constraints for inline
838 // assembly as well as normal instructions.
839 // Don't do this for tied operands that can use the regclass information
841 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
842 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
843 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
846 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
849 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
850 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
851 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
852 MVT RegisterVT = RegVTs[Value];
853 for (unsigned i = 0; i != NumRegs; ++i) {
854 assert(Reg < Regs.size() && "Mismatch in # registers expected");
855 unsigned TheReg = Regs[Reg++];
856 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
858 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
859 // If we clobbered the stack pointer, MFI should know about it.
860 assert(DAG.getMachineFunction().getFrameInfo()->
861 hasInlineAsmWithSPAdjust());
867 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
868 const TargetLibraryInfo *li) {
872 DL = DAG.getSubtarget().getDataLayout();
873 Context = DAG.getContext();
874 LPadToCallSiteMap.clear();
877 /// clear - Clear out the current SelectionDAG and the associated
878 /// state and prepare this SelectionDAGBuilder object to be used
879 /// for a new block. This doesn't clear out information about
880 /// additional blocks that are needed to complete switch lowering
881 /// or PHI node updating; that information is cleared out as it is
883 void SelectionDAGBuilder::clear() {
885 UnusedArgNodeMap.clear();
886 PendingLoads.clear();
887 PendingExports.clear();
890 SDNodeOrder = LowestSDNodeOrder;
891 StatepointLowering.clear();
894 /// clearDanglingDebugInfo - Clear the dangling debug information
895 /// map. This function is separated from the clear so that debug
896 /// information that is dangling in a basic block can be properly
897 /// resolved in a different basic block. This allows the
898 /// SelectionDAG to resolve dangling debug information attached
900 void SelectionDAGBuilder::clearDanglingDebugInfo() {
901 DanglingDebugInfoMap.clear();
904 /// getRoot - Return the current virtual root of the Selection DAG,
905 /// flushing any PendingLoad items. This must be done before emitting
906 /// a store or any other node that may need to be ordered after any
907 /// prior load instructions.
909 SDValue SelectionDAGBuilder::getRoot() {
910 if (PendingLoads.empty())
911 return DAG.getRoot();
913 if (PendingLoads.size() == 1) {
914 SDValue Root = PendingLoads[0];
916 PendingLoads.clear();
920 // Otherwise, we have to make a token factor node.
921 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
923 PendingLoads.clear();
928 /// getControlRoot - Similar to getRoot, but instead of flushing all the
929 /// PendingLoad items, flush all the PendingExports items. It is necessary
930 /// to do this before emitting a terminator instruction.
932 SDValue SelectionDAGBuilder::getControlRoot() {
933 SDValue Root = DAG.getRoot();
935 if (PendingExports.empty())
938 // Turn all of the CopyToReg chains into one factored node.
939 if (Root.getOpcode() != ISD::EntryToken) {
940 unsigned i = 0, e = PendingExports.size();
941 for (; i != e; ++i) {
942 assert(PendingExports[i].getNode()->getNumOperands() > 1);
943 if (PendingExports[i].getNode()->getOperand(0) == Root)
944 break; // Don't add the root if we already indirectly depend on it.
948 PendingExports.push_back(Root);
951 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
953 PendingExports.clear();
958 void SelectionDAGBuilder::visit(const Instruction &I) {
959 // Set up outgoing PHI node register values before emitting the terminator.
960 if (isa<TerminatorInst>(&I))
961 HandlePHINodesInSuccessorBlocks(I.getParent());
967 visit(I.getOpcode(), I);
969 if (!isa<TerminatorInst>(&I) && !HasTailCall)
970 CopyToExportRegsIfNeeded(&I);
975 void SelectionDAGBuilder::visitPHI(const PHINode &) {
976 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
979 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
980 // Note: this doesn't use InstVisitor, because it has to work with
981 // ConstantExpr's in addition to instructions.
983 default: llvm_unreachable("Unknown instruction type encountered!");
984 // Build the switch statement using the Instruction.def file.
985 #define HANDLE_INST(NUM, OPCODE, CLASS) \
986 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
987 #include "llvm/IR/Instruction.def"
991 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
992 // generate the debug data structures now that we've seen its definition.
993 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
995 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
997 const DbgValueInst *DI = DDI.getDI();
998 DebugLoc dl = DDI.getdl();
999 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1000 MDNode *Variable = DI->getVariable();
1001 MDNode *Expr = DI->getExpression();
1002 uint64_t Offset = DI->getOffset();
1003 // A dbg.value for an alloca is always indirect.
1004 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1006 if (Val.getNode()) {
1007 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, Offset, IsIndirect,
1009 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1010 IsIndirect, Offset, dl, DbgSDNodeOrder);
1011 DAG.AddDbgValue(SDV, Val.getNode(), false);
1014 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1015 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1019 /// getValue - Return an SDValue for the given Value.
1020 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1021 // If we already have an SDValue for this value, use it. It's important
1022 // to do this first, so that we don't create a CopyFromReg if we already
1023 // have a regular SDValue.
1024 SDValue &N = NodeMap[V];
1025 if (N.getNode()) return N;
1027 // If there's a virtual register allocated and initialized for this
1029 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1030 if (It != FuncInfo.ValueMap.end()) {
1031 unsigned InReg = It->second;
1032 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1034 SDValue Chain = DAG.getEntryNode();
1035 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1036 resolveDanglingDebugInfo(V, N);
1040 // Otherwise create a new SDValue and remember it.
1041 SDValue Val = getValueImpl(V);
1043 resolveDanglingDebugInfo(V, Val);
1047 /// getNonRegisterValue - Return an SDValue for the given Value, but
1048 /// don't look in FuncInfo.ValueMap for a virtual register.
1049 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1050 // If we already have an SDValue for this value, use it.
1051 SDValue &N = NodeMap[V];
1052 if (N.getNode()) return N;
1054 // Otherwise create a new SDValue and remember it.
1055 SDValue Val = getValueImpl(V);
1057 resolveDanglingDebugInfo(V, Val);
1061 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1062 /// Create an SDValue for the given value.
1063 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1064 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1066 if (const Constant *C = dyn_cast<Constant>(V)) {
1067 EVT VT = TLI.getValueType(V->getType(), true);
1069 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1070 return DAG.getConstant(*CI, VT);
1072 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1073 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1075 if (isa<ConstantPointerNull>(C)) {
1076 unsigned AS = V->getType()->getPointerAddressSpace();
1077 return DAG.getConstant(0, TLI.getPointerTy(AS));
1080 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1081 return DAG.getConstantFP(*CFP, VT);
1083 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1084 return DAG.getUNDEF(VT);
1086 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1087 visit(CE->getOpcode(), *CE);
1088 SDValue N1 = NodeMap[V];
1089 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1093 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1094 SmallVector<SDValue, 4> Constants;
1095 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1097 SDNode *Val = getValue(*OI).getNode();
1098 // If the operand is an empty aggregate, there are no values.
1100 // Add each leaf value from the operand to the Constants list
1101 // to form a flattened list of all the values.
1102 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1103 Constants.push_back(SDValue(Val, i));
1106 return DAG.getMergeValues(Constants, getCurSDLoc());
1109 if (const ConstantDataSequential *CDS =
1110 dyn_cast<ConstantDataSequential>(C)) {
1111 SmallVector<SDValue, 4> Ops;
1112 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1113 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1114 // Add each leaf value from the operand to the Constants list
1115 // to form a flattened list of all the values.
1116 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1117 Ops.push_back(SDValue(Val, i));
1120 if (isa<ArrayType>(CDS->getType()))
1121 return DAG.getMergeValues(Ops, getCurSDLoc());
1122 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1126 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1127 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1128 "Unknown struct or array constant!");
1130 SmallVector<EVT, 4> ValueVTs;
1131 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1132 unsigned NumElts = ValueVTs.size();
1134 return SDValue(); // empty struct
1135 SmallVector<SDValue, 4> Constants(NumElts);
1136 for (unsigned i = 0; i != NumElts; ++i) {
1137 EVT EltVT = ValueVTs[i];
1138 if (isa<UndefValue>(C))
1139 Constants[i] = DAG.getUNDEF(EltVT);
1140 else if (EltVT.isFloatingPoint())
1141 Constants[i] = DAG.getConstantFP(0, EltVT);
1143 Constants[i] = DAG.getConstant(0, EltVT);
1146 return DAG.getMergeValues(Constants, getCurSDLoc());
1149 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1150 return DAG.getBlockAddress(BA, VT);
1152 VectorType *VecTy = cast<VectorType>(V->getType());
1153 unsigned NumElements = VecTy->getNumElements();
1155 // Now that we know the number and type of the elements, get that number of
1156 // elements into the Ops array based on what kind of constant it is.
1157 SmallVector<SDValue, 16> Ops;
1158 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1159 for (unsigned i = 0; i != NumElements; ++i)
1160 Ops.push_back(getValue(CV->getOperand(i)));
1162 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1163 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1166 if (EltVT.isFloatingPoint())
1167 Op = DAG.getConstantFP(0, EltVT);
1169 Op = DAG.getConstant(0, EltVT);
1170 Ops.assign(NumElements, Op);
1173 // Create a BUILD_VECTOR node.
1174 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1177 // If this is a static alloca, generate it as the frameindex instead of
1179 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1180 DenseMap<const AllocaInst*, int>::iterator SI =
1181 FuncInfo.StaticAllocaMap.find(AI);
1182 if (SI != FuncInfo.StaticAllocaMap.end())
1183 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1186 // If this is an instruction which fast-isel has deferred, select it now.
1187 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1188 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1189 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1190 SDValue Chain = DAG.getEntryNode();
1191 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1194 llvm_unreachable("Can't get register for value!");
1197 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1198 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1199 SDValue Chain = getControlRoot();
1200 SmallVector<ISD::OutputArg, 8> Outs;
1201 SmallVector<SDValue, 8> OutVals;
1203 if (!FuncInfo.CanLowerReturn) {
1204 unsigned DemoteReg = FuncInfo.DemoteRegister;
1205 const Function *F = I.getParent()->getParent();
1207 // Emit a store of the return value through the virtual register.
1208 // Leave Outs empty so that LowerReturn won't try to load return
1209 // registers the usual way.
1210 SmallVector<EVT, 1> PtrValueVTs;
1211 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1214 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1215 SDValue RetOp = getValue(I.getOperand(0));
1217 SmallVector<EVT, 4> ValueVTs;
1218 SmallVector<uint64_t, 4> Offsets;
1219 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1220 unsigned NumValues = ValueVTs.size();
1222 SmallVector<SDValue, 4> Chains(NumValues);
1223 for (unsigned i = 0; i != NumValues; ++i) {
1224 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1225 RetPtr.getValueType(), RetPtr,
1226 DAG.getIntPtrConstant(Offsets[i]));
1228 DAG.getStore(Chain, getCurSDLoc(),
1229 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1230 // FIXME: better loc info would be nice.
1231 Add, MachinePointerInfo(), false, false, 0);
1234 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1235 MVT::Other, Chains);
1236 } else if (I.getNumOperands() != 0) {
1237 SmallVector<EVT, 4> ValueVTs;
1238 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1239 unsigned NumValues = ValueVTs.size();
1241 SDValue RetOp = getValue(I.getOperand(0));
1243 const Function *F = I.getParent()->getParent();
1245 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1246 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1248 ExtendKind = ISD::SIGN_EXTEND;
1249 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1251 ExtendKind = ISD::ZERO_EXTEND;
1253 LLVMContext &Context = F->getContext();
1254 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1257 for (unsigned j = 0; j != NumValues; ++j) {
1258 EVT VT = ValueVTs[j];
1260 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1261 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1263 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1264 MVT PartVT = TLI.getRegisterType(Context, VT);
1265 SmallVector<SDValue, 4> Parts(NumParts);
1266 getCopyToParts(DAG, getCurSDLoc(),
1267 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1268 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1270 // 'inreg' on function refers to return value
1271 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1275 // Propagate extension type if any
1276 if (ExtendKind == ISD::SIGN_EXTEND)
1278 else if (ExtendKind == ISD::ZERO_EXTEND)
1281 for (unsigned i = 0; i < NumParts; ++i) {
1282 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1283 VT, /*isfixed=*/true, 0, 0));
1284 OutVals.push_back(Parts[i]);
1290 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1291 CallingConv::ID CallConv =
1292 DAG.getMachineFunction().getFunction()->getCallingConv();
1293 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1294 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1296 // Verify that the target's LowerReturn behaved as expected.
1297 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1298 "LowerReturn didn't return a valid chain!");
1300 // Update the DAG with the new chain value resulting from return lowering.
1304 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1305 /// created for it, emit nodes to copy the value into the virtual
1307 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1309 if (V->getType()->isEmptyTy())
1312 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1313 if (VMI != FuncInfo.ValueMap.end()) {
1314 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1315 CopyValueToVirtualRegister(V, VMI->second);
1319 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1320 /// the current basic block, add it to ValueMap now so that we'll get a
1322 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1323 // No need to export constants.
1324 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1326 // Already exported?
1327 if (FuncInfo.isExportedInst(V)) return;
1329 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1330 CopyValueToVirtualRegister(V, Reg);
1333 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1334 const BasicBlock *FromBB) {
1335 // The operands of the setcc have to be in this block. We don't know
1336 // how to export them from some other block.
1337 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1338 // Can export from current BB.
1339 if (VI->getParent() == FromBB)
1342 // Is already exported, noop.
1343 return FuncInfo.isExportedInst(V);
1346 // If this is an argument, we can export it if the BB is the entry block or
1347 // if it is already exported.
1348 if (isa<Argument>(V)) {
1349 if (FromBB == &FromBB->getParent()->getEntryBlock())
1352 // Otherwise, can only export this if it is already exported.
1353 return FuncInfo.isExportedInst(V);
1356 // Otherwise, constants can always be exported.
1360 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1361 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1362 const MachineBasicBlock *Dst) const {
1363 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1366 const BasicBlock *SrcBB = Src->getBasicBlock();
1367 const BasicBlock *DstBB = Dst->getBasicBlock();
1368 return BPI->getEdgeWeight(SrcBB, DstBB);
1371 void SelectionDAGBuilder::
1372 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1373 uint32_t Weight /* = 0 */) {
1375 Weight = getEdgeWeight(Src, Dst);
1376 Src->addSuccessor(Dst, Weight);
1380 static bool InBlock(const Value *V, const BasicBlock *BB) {
1381 if (const Instruction *I = dyn_cast<Instruction>(V))
1382 return I->getParent() == BB;
1386 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1387 /// This function emits a branch and is used at the leaves of an OR or an
1388 /// AND operator tree.
1391 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1392 MachineBasicBlock *TBB,
1393 MachineBasicBlock *FBB,
1394 MachineBasicBlock *CurBB,
1395 MachineBasicBlock *SwitchBB,
1398 const BasicBlock *BB = CurBB->getBasicBlock();
1400 // If the leaf of the tree is a comparison, merge the condition into
1402 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1403 // The operands of the cmp have to be in this block. We don't know
1404 // how to export them from some other block. If this is the first block
1405 // of the sequence, no exporting is needed.
1406 if (CurBB == SwitchBB ||
1407 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1408 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1409 ISD::CondCode Condition;
1410 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1411 Condition = getICmpCondCode(IC->getPredicate());
1412 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1413 Condition = getFCmpCondCode(FC->getPredicate());
1414 if (TM.Options.NoNaNsFPMath)
1415 Condition = getFCmpCodeWithoutNaN(Condition);
1417 (void)Condition; // silence warning.
1418 llvm_unreachable("Unknown compare instruction");
1421 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1422 TBB, FBB, CurBB, TWeight, FWeight);
1423 SwitchCases.push_back(CB);
1428 // Create a CaseBlock record representing this branch.
1429 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1430 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1431 SwitchCases.push_back(CB);
1434 /// Scale down both weights to fit into uint32_t.
1435 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1436 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1437 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1438 NewTrue = NewTrue / Scale;
1439 NewFalse = NewFalse / Scale;
1442 /// FindMergedConditions - If Cond is an expression like
1443 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1444 MachineBasicBlock *TBB,
1445 MachineBasicBlock *FBB,
1446 MachineBasicBlock *CurBB,
1447 MachineBasicBlock *SwitchBB,
1448 unsigned Opc, uint32_t TWeight,
1450 // If this node is not part of the or/and tree, emit it as a branch.
1451 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1452 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1453 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1454 BOp->getParent() != CurBB->getBasicBlock() ||
1455 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1456 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1457 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1462 // Create TmpBB after CurBB.
1463 MachineFunction::iterator BBI = CurBB;
1464 MachineFunction &MF = DAG.getMachineFunction();
1465 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1466 CurBB->getParent()->insert(++BBI, TmpBB);
1468 if (Opc == Instruction::Or) {
1469 // Codegen X | Y as:
1478 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1479 // The requirement is that
1480 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1481 // = TrueProb for orignal BB.
1482 // Assuming the orignal weights are A and B, one choice is to set BB1's
1483 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1485 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1486 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1487 // TmpBB, but the math is more complicated.
1489 uint64_t NewTrueWeight = TWeight;
1490 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1491 ScaleWeights(NewTrueWeight, NewFalseWeight);
1492 // Emit the LHS condition.
1493 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1494 NewTrueWeight, NewFalseWeight);
1496 NewTrueWeight = TWeight;
1497 NewFalseWeight = 2 * (uint64_t)FWeight;
1498 ScaleWeights(NewTrueWeight, NewFalseWeight);
1499 // Emit the RHS condition into TmpBB.
1500 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1501 NewTrueWeight, NewFalseWeight);
1503 assert(Opc == Instruction::And && "Unknown merge op!");
1504 // Codegen X & Y as:
1512 // This requires creation of TmpBB after CurBB.
1514 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1515 // The requirement is that
1516 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1517 // = FalseProb for orignal BB.
1518 // Assuming the orignal weights are A and B, one choice is to set BB1's
1519 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1521 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1523 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1524 uint64_t NewFalseWeight = FWeight;
1525 ScaleWeights(NewTrueWeight, NewFalseWeight);
1526 // Emit the LHS condition.
1527 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1528 NewTrueWeight, NewFalseWeight);
1530 NewTrueWeight = 2 * (uint64_t)TWeight;
1531 NewFalseWeight = FWeight;
1532 ScaleWeights(NewTrueWeight, NewFalseWeight);
1533 // Emit the RHS condition into TmpBB.
1534 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1535 NewTrueWeight, NewFalseWeight);
1539 /// If the set of cases should be emitted as a series of branches, return true.
1540 /// If we should emit this as a bunch of and/or'd together conditions, return
1543 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1544 if (Cases.size() != 2) return true;
1546 // If this is two comparisons of the same values or'd or and'd together, they
1547 // will get folded into a single comparison, so don't emit two blocks.
1548 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1549 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1550 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1551 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1555 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1556 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1557 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1558 Cases[0].CC == Cases[1].CC &&
1559 isa<Constant>(Cases[0].CmpRHS) &&
1560 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1561 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1563 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1570 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1571 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1573 // Update machine-CFG edges.
1574 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1576 // Figure out which block is immediately after the current one.
1577 MachineBasicBlock *NextBlock = nullptr;
1578 MachineFunction::iterator BBI = BrMBB;
1579 if (++BBI != FuncInfo.MF->end())
1582 if (I.isUnconditional()) {
1583 // Update machine-CFG edges.
1584 BrMBB->addSuccessor(Succ0MBB);
1586 // If this is not a fall-through branch or optimizations are switched off,
1588 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1589 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1590 MVT::Other, getControlRoot(),
1591 DAG.getBasicBlock(Succ0MBB)));
1596 // If this condition is one of the special cases we handle, do special stuff
1598 const Value *CondVal = I.getCondition();
1599 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1601 // If this is a series of conditions that are or'd or and'd together, emit
1602 // this as a sequence of branches instead of setcc's with and/or operations.
1603 // As long as jumps are not expensive, this should improve performance.
1604 // For example, instead of something like:
1617 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1618 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1619 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1620 BOp->getOpcode() == Instruction::Or)) {
1621 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1622 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1623 getEdgeWeight(BrMBB, Succ1MBB));
1624 // If the compares in later blocks need to use values not currently
1625 // exported from this block, export them now. This block should always
1626 // be the first entry.
1627 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1629 // Allow some cases to be rejected.
1630 if (ShouldEmitAsBranches(SwitchCases)) {
1631 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1632 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1633 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1636 // Emit the branch for this block.
1637 visitSwitchCase(SwitchCases[0], BrMBB);
1638 SwitchCases.erase(SwitchCases.begin());
1642 // Okay, we decided not to do this, remove any inserted MBB's and clear
1644 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1645 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1647 SwitchCases.clear();
1651 // Create a CaseBlock record representing this branch.
1652 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1653 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1655 // Use visitSwitchCase to actually insert the fast branch sequence for this
1657 visitSwitchCase(CB, BrMBB);
1660 /// visitSwitchCase - Emits the necessary code to represent a single node in
1661 /// the binary search tree resulting from lowering a switch instruction.
1662 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1663 MachineBasicBlock *SwitchBB) {
1665 SDValue CondLHS = getValue(CB.CmpLHS);
1666 SDLoc dl = getCurSDLoc();
1668 // Build the setcc now.
1670 // Fold "(X == true)" to X and "(X == false)" to !X to
1671 // handle common cases produced by branch lowering.
1672 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1673 CB.CC == ISD::SETEQ)
1675 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1676 CB.CC == ISD::SETEQ) {
1677 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1678 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1680 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1682 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1684 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1685 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1687 SDValue CmpOp = getValue(CB.CmpMHS);
1688 EVT VT = CmpOp.getValueType();
1690 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1691 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1694 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1695 VT, CmpOp, DAG.getConstant(Low, VT));
1696 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1697 DAG.getConstant(High-Low, VT), ISD::SETULE);
1701 // Update successor info
1702 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1703 // TrueBB and FalseBB are always different unless the incoming IR is
1704 // degenerate. This only happens when running llc on weird IR.
1705 if (CB.TrueBB != CB.FalseBB)
1706 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1708 // Set NextBlock to be the MBB immediately after the current one, if any.
1709 // This is used to avoid emitting unnecessary branches to the next block.
1710 MachineBasicBlock *NextBlock = nullptr;
1711 MachineFunction::iterator BBI = SwitchBB;
1712 if (++BBI != FuncInfo.MF->end())
1715 // If the lhs block is the next block, invert the condition so that we can
1716 // fall through to the lhs instead of the rhs block.
1717 if (CB.TrueBB == NextBlock) {
1718 std::swap(CB.TrueBB, CB.FalseBB);
1719 SDValue True = DAG.getConstant(1, Cond.getValueType());
1720 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1723 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1724 MVT::Other, getControlRoot(), Cond,
1725 DAG.getBasicBlock(CB.TrueBB));
1727 // Insert the false branch. Do this even if it's a fall through branch,
1728 // this makes it easier to do DAG optimizations which require inverting
1729 // the branch condition.
1730 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1731 DAG.getBasicBlock(CB.FalseBB));
1733 DAG.setRoot(BrCond);
1736 /// visitJumpTable - Emit JumpTable node in the current MBB
1737 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1738 // Emit the code for the jump table
1739 assert(JT.Reg != -1U && "Should lower JT Header first!");
1740 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1741 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1743 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1744 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1745 MVT::Other, Index.getValue(1),
1747 DAG.setRoot(BrJumpTable);
1750 /// visitJumpTableHeader - This function emits necessary code to produce index
1751 /// in the JumpTable from switch case.
1752 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1753 JumpTableHeader &JTH,
1754 MachineBasicBlock *SwitchBB) {
1755 // Subtract the lowest switch case value from the value being switched on and
1756 // conditional branch to default mbb if the result is greater than the
1757 // difference between smallest and largest cases.
1758 SDValue SwitchOp = getValue(JTH.SValue);
1759 EVT VT = SwitchOp.getValueType();
1760 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1761 DAG.getConstant(JTH.First, VT));
1763 // The SDNode we just created, which holds the value being switched on minus
1764 // the smallest case value, needs to be copied to a virtual register so it
1765 // can be used as an index into the jump table in a subsequent basic block.
1766 // This value may be smaller or larger than the target's pointer type, and
1767 // therefore require extension or truncating.
1768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1769 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1771 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1772 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1773 JumpTableReg, SwitchOp);
1774 JT.Reg = JumpTableReg;
1776 // Emit the range check for the jump table, and branch to the default block
1777 // for the switch statement if the value being switched on exceeds the largest
1778 // case in the switch.
1780 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1781 Sub.getValueType()),
1782 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1784 // Set NextBlock to be the MBB immediately after the current one, if any.
1785 // This is used to avoid emitting unnecessary branches to the next block.
1786 MachineBasicBlock *NextBlock = nullptr;
1787 MachineFunction::iterator BBI = SwitchBB;
1789 if (++BBI != FuncInfo.MF->end())
1792 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1793 MVT::Other, CopyTo, CMP,
1794 DAG.getBasicBlock(JT.Default));
1796 if (JT.MBB != NextBlock)
1797 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1798 DAG.getBasicBlock(JT.MBB));
1800 DAG.setRoot(BrCond);
1803 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1804 /// tail spliced into a stack protector check success bb.
1806 /// For a high level explanation of how this fits into the stack protector
1807 /// generation see the comment on the declaration of class
1808 /// StackProtectorDescriptor.
1809 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1810 MachineBasicBlock *ParentBB) {
1812 // First create the loads to the guard/stack slot for the comparison.
1813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1814 EVT PtrTy = TLI.getPointerTy();
1816 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1817 int FI = MFI->getStackProtectorIndex();
1819 const Value *IRGuard = SPD.getGuard();
1820 SDValue GuardPtr = getValue(IRGuard);
1821 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1824 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1828 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1829 // guard value from the virtual register holding the value. Otherwise, emit a
1830 // volatile load to retrieve the stack guard value.
1831 unsigned GuardReg = SPD.getGuardReg();
1833 if (GuardReg && TLI.useLoadStackGuardNode())
1834 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1837 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1838 GuardPtr, MachinePointerInfo(IRGuard, 0),
1839 true, false, false, Align);
1841 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1843 MachinePointerInfo::getFixedStack(FI),
1844 true, false, false, Align);
1846 // Perform the comparison via a subtract/getsetcc.
1847 EVT VT = Guard.getValueType();
1848 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1851 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1852 Sub.getValueType()),
1853 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1855 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1856 // branch to failure MBB.
1857 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1858 MVT::Other, StackSlot.getOperand(0),
1859 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1860 // Otherwise branch to success MBB.
1861 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1863 DAG.getBasicBlock(SPD.getSuccessMBB()));
1868 /// Codegen the failure basic block for a stack protector check.
1870 /// A failure stack protector machine basic block consists simply of a call to
1871 /// __stack_chk_fail().
1873 /// For a high level explanation of how this fits into the stack protector
1874 /// generation see the comment on the declaration of class
1875 /// StackProtectorDescriptor.
1877 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1878 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1880 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1881 nullptr, 0, false, getCurSDLoc(), false, false).second;
1885 /// visitBitTestHeader - This function emits necessary code to produce value
1886 /// suitable for "bit tests"
1887 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1888 MachineBasicBlock *SwitchBB) {
1889 // Subtract the minimum value
1890 SDValue SwitchOp = getValue(B.SValue);
1891 EVT VT = SwitchOp.getValueType();
1892 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1893 DAG.getConstant(B.First, VT));
1896 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1898 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1899 Sub.getValueType()),
1900 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1902 // Determine the type of the test operands.
1903 bool UsePtrType = false;
1904 if (!TLI.isTypeLegal(VT))
1907 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1908 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1909 // Switch table case range are encoded into series of masks.
1910 // Just use pointer type, it's guaranteed to fit.
1916 VT = TLI.getPointerTy();
1917 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1920 B.RegVT = VT.getSimpleVT();
1921 B.Reg = FuncInfo.CreateReg(B.RegVT);
1922 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1925 // Set NextBlock to be the MBB immediately after the current one, if any.
1926 // This is used to avoid emitting unnecessary branches to the next block.
1927 MachineBasicBlock *NextBlock = nullptr;
1928 MachineFunction::iterator BBI = SwitchBB;
1929 if (++BBI != FuncInfo.MF->end())
1932 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1934 addSuccessorWithWeight(SwitchBB, B.Default);
1935 addSuccessorWithWeight(SwitchBB, MBB);
1937 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1938 MVT::Other, CopyTo, RangeCmp,
1939 DAG.getBasicBlock(B.Default));
1941 if (MBB != NextBlock)
1942 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1943 DAG.getBasicBlock(MBB));
1945 DAG.setRoot(BrRange);
1948 /// visitBitTestCase - this function produces one "bit test"
1949 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1950 MachineBasicBlock* NextMBB,
1951 uint32_t BranchWeightToNext,
1954 MachineBasicBlock *SwitchBB) {
1956 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1959 unsigned PopCount = CountPopulation_64(B.Mask);
1960 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1961 if (PopCount == 1) {
1962 // Testing for a single bit; just compare the shift count with what it
1963 // would need to be to shift a 1 bit in that position.
1965 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1966 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1967 } else if (PopCount == BB.Range) {
1968 // There is only one zero bit in the range, test for it directly.
1970 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1971 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), ISD::SETNE);
1973 // Make desired shift
1974 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1975 DAG.getConstant(1, VT), ShiftOp);
1977 // Emit bit tests and jumps
1978 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1979 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1980 Cmp = DAG.getSetCC(getCurSDLoc(),
1981 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1982 DAG.getConstant(0, VT), ISD::SETNE);
1985 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1986 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1987 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1988 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1990 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1991 MVT::Other, getControlRoot(),
1992 Cmp, DAG.getBasicBlock(B.TargetBB));
1994 // Set NextBlock to be the MBB immediately after the current one, if any.
1995 // This is used to avoid emitting unnecessary branches to the next block.
1996 MachineBasicBlock *NextBlock = nullptr;
1997 MachineFunction::iterator BBI = SwitchBB;
1998 if (++BBI != FuncInfo.MF->end())
2001 if (NextMBB != NextBlock)
2002 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
2003 DAG.getBasicBlock(NextMBB));
2008 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2009 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2011 // Retrieve successors.
2012 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2013 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2015 const Value *Callee(I.getCalledValue());
2016 const Function *Fn = dyn_cast<Function>(Callee);
2017 if (isa<InlineAsm>(Callee))
2019 else if (Fn && Fn->isIntrinsic()) {
2020 switch (Fn->getIntrinsicID()) {
2022 llvm_unreachable("Cannot invoke this intrinsic");
2023 case Intrinsic::donothing:
2024 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2026 case Intrinsic::experimental_patchpoint_void:
2027 case Intrinsic::experimental_patchpoint_i64:
2028 visitPatchpoint(&I, LandingPad);
2032 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2034 // If the value of the invoke is used outside of its defining block, make it
2035 // available as a virtual register.
2036 CopyToExportRegsIfNeeded(&I);
2038 // Update successor info
2039 addSuccessorWithWeight(InvokeMBB, Return);
2040 addSuccessorWithWeight(InvokeMBB, LandingPad);
2042 // Drop into normal successor.
2043 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2044 MVT::Other, getControlRoot(),
2045 DAG.getBasicBlock(Return)));
2048 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2049 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2052 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2053 assert(FuncInfo.MBB->isLandingPad() &&
2054 "Call to landingpad not in landing pad!");
2056 MachineBasicBlock *MBB = FuncInfo.MBB;
2057 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2058 AddLandingPadInfo(LP, MMI, MBB);
2060 // If there aren't registers to copy the values into (e.g., during SjLj
2061 // exceptions), then don't bother to create these DAG nodes.
2062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2063 if (TLI.getExceptionPointerRegister() == 0 &&
2064 TLI.getExceptionSelectorRegister() == 0)
2067 SmallVector<EVT, 2> ValueVTs;
2068 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2069 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2071 // Get the two live-in registers as SDValues. The physregs have already been
2072 // copied into virtual registers.
2074 Ops[0] = DAG.getZExtOrTrunc(
2075 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2076 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2077 getCurSDLoc(), ValueVTs[0]);
2078 Ops[1] = DAG.getZExtOrTrunc(
2079 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2080 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2081 getCurSDLoc(), ValueVTs[1]);
2084 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2085 DAG.getVTList(ValueVTs), Ops);
2089 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2090 /// small case ranges).
2091 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2092 CaseRecVector& WorkList,
2094 MachineBasicBlock *Default,
2095 MachineBasicBlock *SwitchBB) {
2096 // Size is the number of Cases represented by this range.
2097 size_t Size = CR.Range.second - CR.Range.first;
2101 // Get the MachineFunction which holds the current MBB. This is used when
2102 // inserting any additional MBBs necessary to represent the switch.
2103 MachineFunction *CurMF = FuncInfo.MF;
2105 // Figure out which block is immediately after the current one.
2106 MachineBasicBlock *NextBlock = nullptr;
2107 MachineFunction::iterator BBI = CR.CaseBB;
2109 if (++BBI != FuncInfo.MF->end())
2112 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2113 // If any two of the cases has the same destination, and if one value
2114 // is the same as the other, but has one bit unset that the other has set,
2115 // use bit manipulation to do two compares at once. For example:
2116 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2117 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2118 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2119 if (Size == 2 && CR.CaseBB == SwitchBB) {
2120 Case &Small = *CR.Range.first;
2121 Case &Big = *(CR.Range.second-1);
2123 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2124 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2125 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2127 // Check that there is only one bit different.
2128 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2129 (SmallValue | BigValue) == BigValue) {
2130 // Isolate the common bit.
2131 APInt CommonBit = BigValue & ~SmallValue;
2132 assert((SmallValue | CommonBit) == BigValue &&
2133 CommonBit.countPopulation() == 1 && "Not a common bit?");
2135 SDValue CondLHS = getValue(SV);
2136 EVT VT = CondLHS.getValueType();
2137 SDLoc DL = getCurSDLoc();
2139 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2140 DAG.getConstant(CommonBit, VT));
2141 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2142 Or, DAG.getConstant(BigValue, VT),
2145 // Update successor info.
2146 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2147 addSuccessorWithWeight(SwitchBB, Small.BB,
2148 Small.ExtraWeight + Big.ExtraWeight);
2149 addSuccessorWithWeight(SwitchBB, Default,
2150 // The default destination is the first successor in IR.
2151 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2153 // Insert the true branch.
2154 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2155 getControlRoot(), Cond,
2156 DAG.getBasicBlock(Small.BB));
2158 // Insert the false branch.
2159 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2160 DAG.getBasicBlock(Default));
2162 DAG.setRoot(BrCond);
2168 // Order cases by weight so the most likely case will be checked first.
2169 uint32_t UnhandledWeights = 0;
2171 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2172 uint32_t IWeight = I->ExtraWeight;
2173 UnhandledWeights += IWeight;
2174 for (CaseItr J = CR.Range.first; J < I; ++J) {
2175 uint32_t JWeight = J->ExtraWeight;
2176 if (IWeight > JWeight)
2181 // Rearrange the case blocks so that the last one falls through if possible.
2182 Case &BackCase = *(CR.Range.second-1);
2184 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2185 // The last case block won't fall through into 'NextBlock' if we emit the
2186 // branches in this order. See if rearranging a case value would help.
2187 // We start at the bottom as it's the case with the least weight.
2188 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2189 if (I->BB == NextBlock) {
2190 std::swap(*I, BackCase);
2195 // Create a CaseBlock record representing a conditional branch to
2196 // the Case's target mbb if the value being switched on SV is equal
2198 MachineBasicBlock *CurBlock = CR.CaseBB;
2199 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2200 MachineBasicBlock *FallThrough;
2202 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2203 CurMF->insert(BBI, FallThrough);
2205 // Put SV in a virtual register to make it available from the new blocks.
2206 ExportFromCurrentBlock(SV);
2208 // If the last case doesn't match, go to the default block.
2209 FallThrough = Default;
2212 const Value *RHS, *LHS, *MHS;
2214 if (I->High == I->Low) {
2215 // This is just small small case range :) containing exactly 1 case
2217 LHS = SV; RHS = I->High; MHS = nullptr;
2220 LHS = I->Low; MHS = SV; RHS = I->High;
2223 // The false weight should be sum of all un-handled cases.
2224 UnhandledWeights -= I->ExtraWeight;
2225 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2227 /* trueweight */ I->ExtraWeight,
2228 /* falseweight */ UnhandledWeights);
2230 // If emitting the first comparison, just call visitSwitchCase to emit the
2231 // code into the current block. Otherwise, push the CaseBlock onto the
2232 // vector to be later processed by SDISel, and insert the node's MBB
2233 // before the next MBB.
2234 if (CurBlock == SwitchBB)
2235 visitSwitchCase(CB, SwitchBB);
2237 SwitchCases.push_back(CB);
2239 CurBlock = FallThrough;
2245 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2246 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2247 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2250 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2251 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2252 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2253 return (LastExt - FirstExt + 1ULL);
2256 /// handleJTSwitchCase - Emit jumptable for current switch case range
2257 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2258 CaseRecVector &WorkList,
2260 MachineBasicBlock *Default,
2261 MachineBasicBlock *SwitchBB) {
2262 Case& FrontCase = *CR.Range.first;
2263 Case& BackCase = *(CR.Range.second-1);
2265 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2266 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2268 APInt TSize(First.getBitWidth(), 0);
2269 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2272 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2273 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2276 APInt Range = ComputeRange(First, Last);
2277 // The density is TSize / Range. Require at least 40%.
2278 // It should not be possible for IntTSize to saturate for sane code, but make
2279 // sure we handle Range saturation correctly.
2280 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2281 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2282 if (IntTSize * 10 < IntRange * 4)
2285 DEBUG(dbgs() << "Lowering jump table\n"
2286 << "First entry: " << First << ". Last entry: " << Last << '\n'
2287 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2289 // Get the MachineFunction which holds the current MBB. This is used when
2290 // inserting any additional MBBs necessary to represent the switch.
2291 MachineFunction *CurMF = FuncInfo.MF;
2293 // Figure out which block is immediately after the current one.
2294 MachineFunction::iterator BBI = CR.CaseBB;
2297 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2299 // Create a new basic block to hold the code for loading the address
2300 // of the jump table, and jumping to it. Update successor information;
2301 // we will either branch to the default case for the switch, or the jump
2303 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2304 CurMF->insert(BBI, JumpTableBB);
2306 addSuccessorWithWeight(CR.CaseBB, Default);
2307 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2309 // Build a vector of destination BBs, corresponding to each target
2310 // of the jump table. If the value of the jump table slot corresponds to
2311 // a case statement, push the case's BB onto the vector, otherwise, push
2313 std::vector<MachineBasicBlock*> DestBBs;
2315 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2316 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2317 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2319 if (Low.sle(TEI) && TEI.sle(High)) {
2320 DestBBs.push_back(I->BB);
2324 DestBBs.push_back(Default);
2328 // Calculate weight for each unique destination in CR.
2329 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2331 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2332 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2333 DestWeights.find(I->BB);
2334 if (Itr != DestWeights.end())
2335 Itr->second += I->ExtraWeight;
2337 DestWeights[I->BB] = I->ExtraWeight;
2340 // Update successor info. Add one edge to each unique successor.
2341 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2342 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2343 E = DestBBs.end(); I != E; ++I) {
2344 if (!SuccsHandled[(*I)->getNumber()]) {
2345 SuccsHandled[(*I)->getNumber()] = true;
2346 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2347 DestWeights.find(*I);
2348 addSuccessorWithWeight(JumpTableBB, *I,
2349 Itr != DestWeights.end() ? Itr->second : 0);
2353 // Create a jump table index for this jump table.
2354 unsigned JTEncoding = TLI.getJumpTableEncoding();
2355 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2356 ->createJumpTableIndex(DestBBs);
2358 // Set the jump table information so that we can codegen it as a second
2359 // MachineBasicBlock
2360 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2361 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2362 if (CR.CaseBB == SwitchBB)
2363 visitJumpTableHeader(JT, JTH, SwitchBB);
2365 JTCases.push_back(JumpTableBlock(JTH, JT));
2369 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2371 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2372 CaseRecVector& WorkList,
2374 MachineBasicBlock* SwitchBB) {
2375 // Get the MachineFunction which holds the current MBB. This is used when
2376 // inserting any additional MBBs necessary to represent the switch.
2377 MachineFunction *CurMF = FuncInfo.MF;
2379 // Figure out which block is immediately after the current one.
2380 MachineFunction::iterator BBI = CR.CaseBB;
2383 Case& FrontCase = *CR.Range.first;
2384 Case& BackCase = *(CR.Range.second-1);
2385 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2387 // Size is the number of Cases represented by this range.
2388 unsigned Size = CR.Range.second - CR.Range.first;
2390 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2391 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2393 CaseItr Pivot = CR.Range.first + Size/2;
2395 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2396 // (heuristically) allow us to emit JumpTable's later.
2397 APInt TSize(First.getBitWidth(), 0);
2398 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2402 APInt LSize = FrontCase.size();
2403 APInt RSize = TSize-LSize;
2404 DEBUG(dbgs() << "Selecting best pivot: \n"
2405 << "First: " << First << ", Last: " << Last <<'\n'
2406 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2407 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2409 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2410 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2411 APInt Range = ComputeRange(LEnd, RBegin);
2412 assert((Range - 2ULL).isNonNegative() &&
2413 "Invalid case distance");
2414 // Use volatile double here to avoid excess precision issues on some hosts,
2415 // e.g. that use 80-bit X87 registers.
2416 volatile double LDensity =
2417 (double)LSize.roundToDouble() /
2418 (LEnd - First + 1ULL).roundToDouble();
2419 volatile double RDensity =
2420 (double)RSize.roundToDouble() /
2421 (Last - RBegin + 1ULL).roundToDouble();
2422 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2423 // Should always split in some non-trivial place
2424 DEBUG(dbgs() <<"=>Step\n"
2425 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2426 << "LDensity: " << LDensity
2427 << ", RDensity: " << RDensity << '\n'
2428 << "Metric: " << Metric << '\n');
2429 if (FMetric < Metric) {
2432 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2439 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2440 if (areJTsAllowed(TLI)) {
2441 // If our case is dense we *really* should handle it earlier!
2442 assert((FMetric > 0) && "Should handle dense range earlier!");
2444 Pivot = CR.Range.first + Size/2;
2447 CaseRange LHSR(CR.Range.first, Pivot);
2448 CaseRange RHSR(Pivot, CR.Range.second);
2449 const Constant *C = Pivot->Low;
2450 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2452 // We know that we branch to the LHS if the Value being switched on is
2453 // less than the Pivot value, C. We use this to optimize our binary
2454 // tree a bit, by recognizing that if SV is greater than or equal to the
2455 // LHS's Case Value, and that Case Value is exactly one less than the
2456 // Pivot's Value, then we can branch directly to the LHS's Target,
2457 // rather than creating a leaf node for it.
2458 if ((LHSR.second - LHSR.first) == 1 &&
2459 LHSR.first->High == CR.GE &&
2460 cast<ConstantInt>(C)->getValue() ==
2461 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2462 TrueBB = LHSR.first->BB;
2464 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2465 CurMF->insert(BBI, TrueBB);
2466 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2468 // Put SV in a virtual register to make it available from the new blocks.
2469 ExportFromCurrentBlock(SV);
2472 // Similar to the optimization above, if the Value being switched on is
2473 // known to be less than the Constant CR.LT, and the current Case Value
2474 // is CR.LT - 1, then we can branch directly to the target block for
2475 // the current Case Value, rather than emitting a RHS leaf node for it.
2476 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2477 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2478 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2479 FalseBB = RHSR.first->BB;
2481 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2482 CurMF->insert(BBI, FalseBB);
2483 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2485 // Put SV in a virtual register to make it available from the new blocks.
2486 ExportFromCurrentBlock(SV);
2489 // Create a CaseBlock record representing a conditional branch to
2490 // the LHS node if the value being switched on SV is less than C.
2491 // Otherwise, branch to LHS.
2492 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2494 if (CR.CaseBB == SwitchBB)
2495 visitSwitchCase(CB, SwitchBB);
2497 SwitchCases.push_back(CB);
2502 /// handleBitTestsSwitchCase - if current case range has few destination and
2503 /// range span less, than machine word bitwidth, encode case range into series
2504 /// of masks and emit bit tests with these masks.
2505 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2506 CaseRecVector& WorkList,
2508 MachineBasicBlock* Default,
2509 MachineBasicBlock* SwitchBB) {
2510 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2511 EVT PTy = TLI.getPointerTy();
2512 unsigned IntPtrBits = PTy.getSizeInBits();
2514 Case& FrontCase = *CR.Range.first;
2515 Case& BackCase = *(CR.Range.second-1);
2517 // Get the MachineFunction which holds the current MBB. This is used when
2518 // inserting any additional MBBs necessary to represent the switch.
2519 MachineFunction *CurMF = FuncInfo.MF;
2521 // If target does not have legal shift left, do not emit bit tests at all.
2522 if (!TLI.isOperationLegal(ISD::SHL, PTy))
2526 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2527 // Single case counts one, case range - two.
2528 numCmps += (I->Low == I->High ? 1 : 2);
2531 // Count unique destinations
2532 SmallSet<MachineBasicBlock*, 4> Dests;
2533 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2534 Dests.insert(I->BB);
2535 if (Dests.size() > 3)
2536 // Don't bother the code below, if there are too much unique destinations
2539 DEBUG(dbgs() << "Total number of unique destinations: "
2540 << Dests.size() << '\n'
2541 << "Total number of comparisons: " << numCmps << '\n');
2543 // Compute span of values.
2544 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2545 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2546 APInt cmpRange = maxValue - minValue;
2548 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2549 << "Low bound: " << minValue << '\n'
2550 << "High bound: " << maxValue << '\n');
2552 if (cmpRange.uge(IntPtrBits) ||
2553 (!(Dests.size() == 1 && numCmps >= 3) &&
2554 !(Dests.size() == 2 && numCmps >= 5) &&
2555 !(Dests.size() >= 3 && numCmps >= 6)))
2558 DEBUG(dbgs() << "Emitting bit tests\n");
2559 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2561 // Optimize the case where all the case values fit in a
2562 // word without having to subtract minValue. In this case,
2563 // we can optimize away the subtraction.
2564 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2565 cmpRange = maxValue;
2567 lowBound = minValue;
2570 CaseBitsVector CasesBits;
2571 unsigned i, count = 0;
2573 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2574 MachineBasicBlock* Dest = I->BB;
2575 for (i = 0; i < count; ++i)
2576 if (Dest == CasesBits[i].BB)
2580 assert((count < 3) && "Too much destinations to test!");
2581 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2585 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2586 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2588 uint64_t lo = (lowValue - lowBound).getZExtValue();
2589 uint64_t hi = (highValue - lowBound).getZExtValue();
2590 CasesBits[i].ExtraWeight += I->ExtraWeight;
2592 for (uint64_t j = lo; j <= hi; j++) {
2593 CasesBits[i].Mask |= 1ULL << j;
2594 CasesBits[i].Bits++;
2598 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2602 // Figure out which block is immediately after the current one.
2603 MachineFunction::iterator BBI = CR.CaseBB;
2606 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2608 DEBUG(dbgs() << "Cases:\n");
2609 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2610 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2611 << ", Bits: " << CasesBits[i].Bits
2612 << ", BB: " << CasesBits[i].BB << '\n');
2614 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2615 CurMF->insert(BBI, CaseBB);
2616 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2618 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2620 // Put SV in a virtual register to make it available from the new blocks.
2621 ExportFromCurrentBlock(SV);
2624 BitTestBlock BTB(lowBound, cmpRange, SV,
2625 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2626 CR.CaseBB, Default, std::move(BTC));
2628 if (CR.CaseBB == SwitchBB)
2629 visitBitTestHeader(BTB, SwitchBB);
2631 BitTestCases.push_back(std::move(BTB));
2636 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2637 void SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2638 const SwitchInst& SI) {
2639 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2640 // Start with "simple" cases.
2641 for (SwitchInst::ConstCaseIt i : SI.cases()) {
2642 const BasicBlock *SuccBB = i.getCaseSuccessor();
2643 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2645 uint32_t ExtraWeight =
2646 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2648 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2649 SMBB, ExtraWeight));
2651 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2653 // Merge case into clusters
2654 if (Cases.size() >= 2)
2655 // Must recompute end() each iteration because it may be
2656 // invalidated by erase if we hold on to it
2657 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2658 J != Cases.end(); ) {
2659 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2660 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2661 MachineBasicBlock* nextBB = J->BB;
2662 MachineBasicBlock* currentBB = I->BB;
2664 // If the two neighboring cases go to the same destination, merge them
2665 // into a single case.
2666 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2668 I->ExtraWeight += J->ExtraWeight;
2677 for (auto &I : Cases)
2678 // A range counts double, since it requires two compares.
2679 numCmps += I.Low != I.High ? 2 : 1;
2681 dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2682 << ". Total compares: " << numCmps << '\n';
2686 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2687 MachineBasicBlock *Last) {
2689 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2690 if (JTCases[i].first.HeaderBB == First)
2691 JTCases[i].first.HeaderBB = Last;
2693 // Update BitTestCases.
2694 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2695 if (BitTestCases[i].Parent == First)
2696 BitTestCases[i].Parent = Last;
2699 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2700 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2702 // Figure out which block is immediately after the current one.
2703 MachineBasicBlock *NextBlock = nullptr;
2704 if (SwitchMBB + 1 != FuncInfo.MF->end())
2705 NextBlock = SwitchMBB + 1;
2708 // Create a vector of Cases, sorted so that we can efficiently create a binary
2709 // search tree from them.
2711 Clusterify(Cases, SI);
2713 // Get the default destination MBB.
2714 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2716 if (isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg()) &&
2718 // Replace an unreachable default destination with the most popular case
2720 DenseMap<const BasicBlock *, unsigned> Popularity;
2721 unsigned MaxPop = 0;
2722 const BasicBlock *MaxBB = nullptr;
2723 for (auto I : SI.cases()) {
2724 const BasicBlock *BB = I.getCaseSuccessor();
2725 if (++Popularity[BB] > MaxPop) {
2726 MaxPop = Popularity[BB];
2734 Default = FuncInfo.MBBMap[MaxBB];
2736 // Remove cases that were pointing to the destination that is now the default.
2737 Cases.erase(std::remove_if(Cases.begin(), Cases.end(),
2738 [&](const Case &C) { return C.BB == Default; }),
2742 // If there is only the default destination, go there directly.
2743 if (Cases.empty()) {
2744 // Update machine-CFG edges.
2745 SwitchMBB->addSuccessor(Default);
2747 // If this is not a fall-through branch, emit the branch.
2748 if (Default != NextBlock) {
2749 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2750 getControlRoot(), DAG.getBasicBlock(Default)));
2755 // Get the Value to be switched on.
2756 const Value *SV = SI.getCondition();
2758 // Push the initial CaseRec onto the worklist
2759 CaseRecVector WorkList;
2760 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2761 CaseRange(Cases.begin(),Cases.end())));
2763 while (!WorkList.empty()) {
2764 // Grab a record representing a case range to process off the worklist
2765 CaseRec CR = WorkList.back();
2766 WorkList.pop_back();
2768 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2771 // If the range has few cases (two or less) emit a series of specific
2773 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2776 // If the switch has more than N blocks, and is at least 40% dense, and the
2777 // target supports indirect branches, then emit a jump table rather than
2778 // lowering the switch to a binary tree of conditional branches.
2779 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2780 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2783 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2784 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2785 handleBTSplitSwitchCase(CR, WorkList, SV, SwitchMBB);
2789 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2790 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2792 // Update machine-CFG edges with unique successors.
2793 SmallSet<BasicBlock*, 32> Done;
2794 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2795 BasicBlock *BB = I.getSuccessor(i);
2796 bool Inserted = Done.insert(BB).second;
2800 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2801 addSuccessorWithWeight(IndirectBrMBB, Succ);
2804 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2805 MVT::Other, getControlRoot(),
2806 getValue(I.getAddress())));
2809 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2810 if (DAG.getTarget().Options.TrapUnreachable)
2811 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2814 void SelectionDAGBuilder::visitFSub(const User &I) {
2815 // -0.0 - X --> fneg
2816 Type *Ty = I.getType();
2817 if (isa<Constant>(I.getOperand(0)) &&
2818 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2819 SDValue Op2 = getValue(I.getOperand(1));
2820 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2821 Op2.getValueType(), Op2));
2825 visitBinary(I, ISD::FSUB);
2828 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2829 SDValue Op1 = getValue(I.getOperand(0));
2830 SDValue Op2 = getValue(I.getOperand(1));
2835 if (const OverflowingBinaryOperator *OFBinOp =
2836 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2837 nuw = OFBinOp->hasNoUnsignedWrap();
2838 nsw = OFBinOp->hasNoSignedWrap();
2840 if (const PossiblyExactOperator *ExactOp =
2841 dyn_cast<const PossiblyExactOperator>(&I))
2842 exact = ExactOp->isExact();
2844 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2845 Op1, Op2, nuw, nsw, exact);
2846 setValue(&I, BinNodeValue);
2849 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2850 SDValue Op1 = getValue(I.getOperand(0));
2851 SDValue Op2 = getValue(I.getOperand(1));
2854 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2856 // Coerce the shift amount to the right type if we can.
2857 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2858 unsigned ShiftSize = ShiftTy.getSizeInBits();
2859 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2860 SDLoc DL = getCurSDLoc();
2862 // If the operand is smaller than the shift count type, promote it.
2863 if (ShiftSize > Op2Size)
2864 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2866 // If the operand is larger than the shift count type but the shift
2867 // count type has enough bits to represent any shift value, truncate
2868 // it now. This is a common case and it exposes the truncate to
2869 // optimization early.
2870 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2871 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2872 // Otherwise we'll need to temporarily settle for some other convenient
2873 // type. Type legalization will make adjustments once the shiftee is split.
2875 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2882 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2884 if (const OverflowingBinaryOperator *OFBinOp =
2885 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2886 nuw = OFBinOp->hasNoUnsignedWrap();
2887 nsw = OFBinOp->hasNoSignedWrap();
2889 if (const PossiblyExactOperator *ExactOp =
2890 dyn_cast<const PossiblyExactOperator>(&I))
2891 exact = ExactOp->isExact();
2894 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2899 void SelectionDAGBuilder::visitSDiv(const User &I) {
2900 SDValue Op1 = getValue(I.getOperand(0));
2901 SDValue Op2 = getValue(I.getOperand(1));
2903 // Turn exact SDivs into multiplications.
2904 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2906 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2907 !isa<ConstantSDNode>(Op1) &&
2908 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2909 setValue(&I, DAG.getTargetLoweringInfo()
2910 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2912 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2916 void SelectionDAGBuilder::visitICmp(const User &I) {
2917 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2918 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2919 predicate = IC->getPredicate();
2920 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2921 predicate = ICmpInst::Predicate(IC->getPredicate());
2922 SDValue Op1 = getValue(I.getOperand(0));
2923 SDValue Op2 = getValue(I.getOperand(1));
2924 ISD::CondCode Opcode = getICmpCondCode(predicate);
2926 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2927 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2930 void SelectionDAGBuilder::visitFCmp(const User &I) {
2931 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2932 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2933 predicate = FC->getPredicate();
2934 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2935 predicate = FCmpInst::Predicate(FC->getPredicate());
2936 SDValue Op1 = getValue(I.getOperand(0));
2937 SDValue Op2 = getValue(I.getOperand(1));
2938 ISD::CondCode Condition = getFCmpCondCode(predicate);
2939 if (TM.Options.NoNaNsFPMath)
2940 Condition = getFCmpCodeWithoutNaN(Condition);
2941 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2942 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2945 void SelectionDAGBuilder::visitSelect(const User &I) {
2946 SmallVector<EVT, 4> ValueVTs;
2947 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2948 unsigned NumValues = ValueVTs.size();
2949 if (NumValues == 0) return;
2951 SmallVector<SDValue, 4> Values(NumValues);
2952 SDValue Cond = getValue(I.getOperand(0));
2953 SDValue TrueVal = getValue(I.getOperand(1));
2954 SDValue FalseVal = getValue(I.getOperand(2));
2955 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2956 ISD::VSELECT : ISD::SELECT;
2958 for (unsigned i = 0; i != NumValues; ++i)
2959 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2960 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2962 SDValue(TrueVal.getNode(),
2963 TrueVal.getResNo() + i),
2964 SDValue(FalseVal.getNode(),
2965 FalseVal.getResNo() + i));
2967 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2968 DAG.getVTList(ValueVTs), Values));
2971 void SelectionDAGBuilder::visitTrunc(const User &I) {
2972 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2973 SDValue N = getValue(I.getOperand(0));
2974 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2975 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2978 void SelectionDAGBuilder::visitZExt(const User &I) {
2979 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2980 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2981 SDValue N = getValue(I.getOperand(0));
2982 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2983 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2986 void SelectionDAGBuilder::visitSExt(const User &I) {
2987 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2988 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2989 SDValue N = getValue(I.getOperand(0));
2990 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2991 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2994 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2995 // FPTrunc is never a no-op cast, no need to check
2996 SDValue N = getValue(I.getOperand(0));
2997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2998 EVT DestVT = TLI.getValueType(I.getType());
2999 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
3000 DAG.getTargetConstant(0, TLI.getPointerTy())));
3003 void SelectionDAGBuilder::visitFPExt(const User &I) {
3004 // FPExt is never a no-op cast, no need to check
3005 SDValue N = getValue(I.getOperand(0));
3006 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3007 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3010 void SelectionDAGBuilder::visitFPToUI(const User &I) {
3011 // FPToUI is never a no-op cast, no need to check
3012 SDValue N = getValue(I.getOperand(0));
3013 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3014 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3017 void SelectionDAGBuilder::visitFPToSI(const User &I) {
3018 // FPToSI is never a no-op cast, no need to check
3019 SDValue N = getValue(I.getOperand(0));
3020 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3021 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3024 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3025 // UIToFP is never a no-op cast, no need to check
3026 SDValue N = getValue(I.getOperand(0));
3027 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3028 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3031 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3032 // SIToFP is never a no-op cast, no need to check
3033 SDValue N = getValue(I.getOperand(0));
3034 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3035 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3038 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3039 // What to do depends on the size of the integer and the size of the pointer.
3040 // We can either truncate, zero extend, or no-op, accordingly.
3041 SDValue N = getValue(I.getOperand(0));
3042 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3043 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3046 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3047 // What to do depends on the size of the integer and the size of the pointer.
3048 // We can either truncate, zero extend, or no-op, accordingly.
3049 SDValue N = getValue(I.getOperand(0));
3050 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3051 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3054 void SelectionDAGBuilder::visitBitCast(const User &I) {
3055 SDValue N = getValue(I.getOperand(0));
3056 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3058 // BitCast assures us that source and destination are the same size so this is
3059 // either a BITCAST or a no-op.
3060 if (DestVT != N.getValueType())
3061 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3062 DestVT, N)); // convert types.
3063 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3064 // might fold any kind of constant expression to an integer constant and that
3065 // is not what we are looking for. Only regcognize a bitcast of a genuine
3066 // constant integer as an opaque constant.
3067 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3068 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3071 setValue(&I, N); // noop cast.
3074 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3075 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3076 const Value *SV = I.getOperand(0);
3077 SDValue N = getValue(SV);
3078 EVT DestVT = TLI.getValueType(I.getType());
3080 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3081 unsigned DestAS = I.getType()->getPointerAddressSpace();
3083 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3084 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3089 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3090 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3091 SDValue InVec = getValue(I.getOperand(0));
3092 SDValue InVal = getValue(I.getOperand(1));
3093 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3094 getCurSDLoc(), TLI.getVectorIdxTy());
3095 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3096 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
3099 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3100 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3101 SDValue InVec = getValue(I.getOperand(0));
3102 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3103 getCurSDLoc(), TLI.getVectorIdxTy());
3104 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3105 TLI.getValueType(I.getType()), InVec, InIdx));
3108 // Utility for visitShuffleVector - Return true if every element in Mask,
3109 // beginning from position Pos and ending in Pos+Size, falls within the
3110 // specified sequential range [L, L+Pos). or is undef.
3111 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3112 unsigned Pos, unsigned Size, int Low) {
3113 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3114 if (Mask[i] >= 0 && Mask[i] != Low)
3119 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3120 SDValue Src1 = getValue(I.getOperand(0));
3121 SDValue Src2 = getValue(I.getOperand(1));
3123 SmallVector<int, 8> Mask;
3124 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3125 unsigned MaskNumElts = Mask.size();
3127 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3128 EVT VT = TLI.getValueType(I.getType());
3129 EVT SrcVT = Src1.getValueType();
3130 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3132 if (SrcNumElts == MaskNumElts) {
3133 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3138 // Normalize the shuffle vector since mask and vector length don't match.
3139 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3140 // Mask is longer than the source vectors and is a multiple of the source
3141 // vectors. We can use concatenate vector to make the mask and vectors
3143 if (SrcNumElts*2 == MaskNumElts) {
3144 // First check for Src1 in low and Src2 in high
3145 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3146 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3147 // The shuffle is concatenating two vectors together.
3148 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3152 // Then check for Src2 in low and Src1 in high
3153 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3154 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3155 // The shuffle is concatenating two vectors together.
3156 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3162 // Pad both vectors with undefs to make them the same length as the mask.
3163 unsigned NumConcat = MaskNumElts / SrcNumElts;
3164 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3165 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3166 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3168 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3169 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3173 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3174 getCurSDLoc(), VT, MOps1);
3175 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3176 getCurSDLoc(), VT, MOps2);
3178 // Readjust mask for new input vector length.
3179 SmallVector<int, 8> MappedOps;
3180 for (unsigned i = 0; i != MaskNumElts; ++i) {
3182 if (Idx >= (int)SrcNumElts)
3183 Idx -= SrcNumElts - MaskNumElts;
3184 MappedOps.push_back(Idx);
3187 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3192 if (SrcNumElts > MaskNumElts) {
3193 // Analyze the access pattern of the vector to see if we can extract
3194 // two subvectors and do the shuffle. The analysis is done by calculating
3195 // the range of elements the mask access on both vectors.
3196 int MinRange[2] = { static_cast<int>(SrcNumElts),
3197 static_cast<int>(SrcNumElts)};
3198 int MaxRange[2] = {-1, -1};
3200 for (unsigned i = 0; i != MaskNumElts; ++i) {
3206 if (Idx >= (int)SrcNumElts) {
3210 if (Idx > MaxRange[Input])
3211 MaxRange[Input] = Idx;
3212 if (Idx < MinRange[Input])
3213 MinRange[Input] = Idx;
3216 // Check if the access is smaller than the vector size and can we find
3217 // a reasonable extract index.
3218 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3220 int StartIdx[2]; // StartIdx to extract from
3221 for (unsigned Input = 0; Input < 2; ++Input) {
3222 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3223 RangeUse[Input] = 0; // Unused
3224 StartIdx[Input] = 0;
3228 // Find a good start index that is a multiple of the mask length. Then
3229 // see if the rest of the elements are in range.
3230 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3231 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3232 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3233 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3236 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3237 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3240 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3241 // Extract appropriate subvector and generate a vector shuffle
3242 for (unsigned Input = 0; Input < 2; ++Input) {
3243 SDValue &Src = Input == 0 ? Src1 : Src2;
3244 if (RangeUse[Input] == 0)
3245 Src = DAG.getUNDEF(VT);
3248 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
3249 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
3252 // Calculate new mask.
3253 SmallVector<int, 8> MappedOps;
3254 for (unsigned i = 0; i != MaskNumElts; ++i) {
3257 if (Idx < (int)SrcNumElts)
3260 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3262 MappedOps.push_back(Idx);
3265 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3271 // We can't use either concat vectors or extract subvectors so fall back to
3272 // replacing the shuffle with extract and build vector.
3273 // to insert and build vector.
3274 EVT EltVT = VT.getVectorElementType();
3275 EVT IdxVT = TLI.getVectorIdxTy();
3276 SmallVector<SDValue,8> Ops;
3277 for (unsigned i = 0; i != MaskNumElts; ++i) {
3282 Res = DAG.getUNDEF(EltVT);
3284 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3285 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3287 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3288 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3294 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3297 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3298 const Value *Op0 = I.getOperand(0);
3299 const Value *Op1 = I.getOperand(1);
3300 Type *AggTy = I.getType();
3301 Type *ValTy = Op1->getType();
3302 bool IntoUndef = isa<UndefValue>(Op0);
3303 bool FromUndef = isa<UndefValue>(Op1);
3305 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3307 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3308 SmallVector<EVT, 4> AggValueVTs;
3309 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3310 SmallVector<EVT, 4> ValValueVTs;
3311 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3313 unsigned NumAggValues = AggValueVTs.size();
3314 unsigned NumValValues = ValValueVTs.size();
3315 SmallVector<SDValue, 4> Values(NumAggValues);
3317 // Ignore an insertvalue that produces an empty object
3318 if (!NumAggValues) {
3319 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3323 SDValue Agg = getValue(Op0);
3325 // Copy the beginning value(s) from the original aggregate.
3326 for (; i != LinearIndex; ++i)
3327 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3328 SDValue(Agg.getNode(), Agg.getResNo() + i);
3329 // Copy values from the inserted value(s).
3331 SDValue Val = getValue(Op1);
3332 for (; i != LinearIndex + NumValValues; ++i)
3333 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3334 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3336 // Copy remaining value(s) from the original aggregate.
3337 for (; i != NumAggValues; ++i)
3338 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3339 SDValue(Agg.getNode(), Agg.getResNo() + i);
3341 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3342 DAG.getVTList(AggValueVTs), Values));
3345 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3346 const Value *Op0 = I.getOperand(0);
3347 Type *AggTy = Op0->getType();
3348 Type *ValTy = I.getType();
3349 bool OutOfUndef = isa<UndefValue>(Op0);
3351 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3353 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3354 SmallVector<EVT, 4> ValValueVTs;
3355 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3357 unsigned NumValValues = ValValueVTs.size();
3359 // Ignore a extractvalue that produces an empty object
3360 if (!NumValValues) {
3361 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3365 SmallVector<SDValue, 4> Values(NumValValues);
3367 SDValue Agg = getValue(Op0);
3368 // Copy out the selected value(s).
3369 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3370 Values[i - LinearIndex] =
3372 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3373 SDValue(Agg.getNode(), Agg.getResNo() + i);
3375 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3376 DAG.getVTList(ValValueVTs), Values));
3379 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3380 Value *Op0 = I.getOperand(0);
3381 // Note that the pointer operand may be a vector of pointers. Take the scalar
3382 // element which holds a pointer.
3383 Type *Ty = Op0->getType()->getScalarType();
3384 unsigned AS = Ty->getPointerAddressSpace();
3385 SDValue N = getValue(Op0);
3387 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3389 const Value *Idx = *OI;
3390 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3391 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3394 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3395 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3396 DAG.getConstant(Offset, N.getValueType()));
3399 Ty = StTy->getElementType(Field);
3401 Ty = cast<SequentialType>(Ty)->getElementType();
3403 // If this is a constant subscript, handle it quickly.
3404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3405 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3406 if (CI->isZero()) continue;
3408 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3410 EVT PTy = TLI.getPointerTy(AS);
3411 unsigned PtrBits = PTy.getSizeInBits();
3413 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3414 DAG.getConstant(Offs, MVT::i64));
3416 OffsVal = DAG.getConstant(Offs, PTy);
3418 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3423 // N = N + Idx * ElementSize;
3425 APInt(TLI.getPointerSizeInBits(AS), DL->getTypeAllocSize(Ty));
3426 SDValue IdxN = getValue(Idx);
3428 // If the index is smaller or larger than intptr_t, truncate or extend
3430 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3432 // If this is a multiply by a power of two, turn it into a shl
3433 // immediately. This is a very common case.
3434 if (ElementSize != 1) {
3435 if (ElementSize.isPowerOf2()) {
3436 unsigned Amt = ElementSize.logBase2();
3437 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3438 N.getValueType(), IdxN,
3439 DAG.getConstant(Amt, IdxN.getValueType()));
3441 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3442 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3443 N.getValueType(), IdxN, Scale);
3447 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3448 N.getValueType(), N, IdxN);
3455 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3456 // If this is a fixed sized alloca in the entry block of the function,
3457 // allocate it statically on the stack.
3458 if (FuncInfo.StaticAllocaMap.count(&I))
3459 return; // getValue will auto-populate this.
3461 Type *Ty = I.getAllocatedType();
3462 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3463 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3465 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3468 SDValue AllocSize = getValue(I.getArraySize());
3470 EVT IntPtr = TLI.getPointerTy();
3471 if (AllocSize.getValueType() != IntPtr)
3472 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3474 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3476 DAG.getConstant(TySize, IntPtr));
3478 // Handle alignment. If the requested alignment is less than or equal to
3479 // the stack alignment, ignore it. If the size is greater than or equal to
3480 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3481 unsigned StackAlign =
3482 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3483 if (Align <= StackAlign)
3486 // Round the size of the allocation up to the stack alignment size
3487 // by add SA-1 to the size.
3488 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3489 AllocSize.getValueType(), AllocSize,
3490 DAG.getIntPtrConstant(StackAlign-1));
3492 // Mask out the low bits for alignment purposes.
3493 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3494 AllocSize.getValueType(), AllocSize,
3495 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3497 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3498 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3499 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3501 DAG.setRoot(DSA.getValue(1));
3503 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3506 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3508 return visitAtomicLoad(I);
3510 const Value *SV = I.getOperand(0);
3511 SDValue Ptr = getValue(SV);
3513 Type *Ty = I.getType();
3515 bool isVolatile = I.isVolatile();
3516 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3517 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3518 unsigned Alignment = I.getAlignment();
3521 I.getAAMetadata(AAInfo);
3522 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3524 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3525 SmallVector<EVT, 4> ValueVTs;
3526 SmallVector<uint64_t, 4> Offsets;
3527 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3528 unsigned NumValues = ValueVTs.size();
3533 bool ConstantMemory = false;
3534 if (isVolatile || NumValues > MaxParallelChains)
3535 // Serialize volatile loads with other side effects.
3537 else if (AA->pointsToConstantMemory(
3538 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3539 // Do not serialize (non-volatile) loads of constant memory with anything.
3540 Root = DAG.getEntryNode();
3541 ConstantMemory = true;
3543 // Do not serialize non-volatile loads against each other.
3544 Root = DAG.getRoot();
3548 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3550 SmallVector<SDValue, 4> Values(NumValues);
3551 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3553 EVT PtrVT = Ptr.getValueType();
3554 unsigned ChainI = 0;
3555 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3556 // Serializing loads here may result in excessive register pressure, and
3557 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3558 // could recover a bit by hoisting nodes upward in the chain by recognizing
3559 // they are side-effect free or do not alias. The optimizer should really
3560 // avoid this case by converting large object/array copies to llvm.memcpy
3561 // (MaxParallelChains should always remain as failsafe).
3562 if (ChainI == MaxParallelChains) {
3563 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3564 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3565 makeArrayRef(Chains.data(), ChainI));
3569 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3571 DAG.getConstant(Offsets[i], PtrVT));
3572 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3573 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3574 isNonTemporal, isInvariant, Alignment, AAInfo,
3578 Chains[ChainI] = L.getValue(1);
3581 if (!ConstantMemory) {
3582 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3583 makeArrayRef(Chains.data(), ChainI));
3587 PendingLoads.push_back(Chain);
3590 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3591 DAG.getVTList(ValueVTs), Values));
3594 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3596 return visitAtomicStore(I);
3598 const Value *SrcV = I.getOperand(0);
3599 const Value *PtrV = I.getOperand(1);
3601 SmallVector<EVT, 4> ValueVTs;
3602 SmallVector<uint64_t, 4> Offsets;
3603 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
3604 ValueVTs, &Offsets);
3605 unsigned NumValues = ValueVTs.size();
3609 // Get the lowered operands. Note that we do this after
3610 // checking if NumResults is zero, because with zero results
3611 // the operands won't have values in the map.
3612 SDValue Src = getValue(SrcV);
3613 SDValue Ptr = getValue(PtrV);
3615 SDValue Root = getRoot();
3616 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3618 EVT PtrVT = Ptr.getValueType();
3619 bool isVolatile = I.isVolatile();
3620 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3621 unsigned Alignment = I.getAlignment();
3624 I.getAAMetadata(AAInfo);
3626 unsigned ChainI = 0;
3627 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3628 // See visitLoad comments.
3629 if (ChainI == MaxParallelChains) {
3630 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3631 makeArrayRef(Chains.data(), ChainI));
3635 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3636 DAG.getConstant(Offsets[i], PtrVT));
3637 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3638 SDValue(Src.getNode(), Src.getResNo() + i),
3639 Add, MachinePointerInfo(PtrV, Offsets[i]),
3640 isVolatile, isNonTemporal, Alignment, AAInfo);
3641 Chains[ChainI] = St;
3644 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3645 makeArrayRef(Chains.data(), ChainI));
3646 DAG.setRoot(StoreNode);
3649 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3650 SDLoc sdl = getCurSDLoc();
3652 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3653 Value *PtrOperand = I.getArgOperand(1);
3654 SDValue Ptr = getValue(PtrOperand);
3655 SDValue Src0 = getValue(I.getArgOperand(0));
3656 SDValue Mask = getValue(I.getArgOperand(3));
3657 EVT VT = Src0.getValueType();
3658 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3660 Alignment = DAG.getEVTAlignment(VT);
3663 I.getAAMetadata(AAInfo);
3665 MachineMemOperand *MMO =
3666 DAG.getMachineFunction().
3667 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3668 MachineMemOperand::MOStore, VT.getStoreSize(),
3670 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, MMO);
3671 DAG.setRoot(StoreNode);
3672 setValue(&I, StoreNode);
3675 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3676 SDLoc sdl = getCurSDLoc();
3678 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3679 Value *PtrOperand = I.getArgOperand(0);
3680 SDValue Ptr = getValue(PtrOperand);
3681 SDValue Src0 = getValue(I.getArgOperand(3));
3682 SDValue Mask = getValue(I.getArgOperand(2));
3684 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3685 EVT VT = TLI.getValueType(I.getType());
3686 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3688 Alignment = DAG.getEVTAlignment(VT);
3691 I.getAAMetadata(AAInfo);
3692 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3694 SDValue InChain = DAG.getRoot();
3695 if (AA->pointsToConstantMemory(
3696 AliasAnalysis::Location(PtrOperand,
3697 AA->getTypeStoreSize(I.getType()),
3699 // Do not serialize (non-volatile) loads of constant memory with anything.
3700 InChain = DAG.getEntryNode();
3703 MachineMemOperand *MMO =
3704 DAG.getMachineFunction().
3705 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3706 MachineMemOperand::MOLoad, VT.getStoreSize(),
3707 Alignment, AAInfo, Ranges);
3709 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, MMO);
3710 SDValue OutChain = Load.getValue(1);
3711 DAG.setRoot(OutChain);
3715 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3716 SDLoc dl = getCurSDLoc();
3717 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3718 AtomicOrdering FailureOrder = I.getFailureOrdering();
3719 SynchronizationScope Scope = I.getSynchScope();
3721 SDValue InChain = getRoot();
3723 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3724 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3725 SDValue L = DAG.getAtomicCmpSwap(
3726 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3727 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3728 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3729 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3731 SDValue OutChain = L.getValue(2);
3734 DAG.setRoot(OutChain);
3737 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3738 SDLoc dl = getCurSDLoc();
3740 switch (I.getOperation()) {
3741 default: llvm_unreachable("Unknown atomicrmw operation");
3742 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3743 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3744 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3745 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3746 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3747 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3748 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3749 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3750 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3751 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3752 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3754 AtomicOrdering Order = I.getOrdering();
3755 SynchronizationScope Scope = I.getSynchScope();
3757 SDValue InChain = getRoot();
3760 DAG.getAtomic(NT, dl,
3761 getValue(I.getValOperand()).getSimpleValueType(),
3763 getValue(I.getPointerOperand()),
3764 getValue(I.getValOperand()),
3765 I.getPointerOperand(),
3766 /* Alignment=*/ 0, Order, Scope);
3768 SDValue OutChain = L.getValue(1);
3771 DAG.setRoot(OutChain);
3774 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3775 SDLoc dl = getCurSDLoc();
3776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3779 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3780 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3781 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3784 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3785 SDLoc dl = getCurSDLoc();
3786 AtomicOrdering Order = I.getOrdering();
3787 SynchronizationScope Scope = I.getSynchScope();
3789 SDValue InChain = getRoot();
3791 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3792 EVT VT = TLI.getValueType(I.getType());
3794 if (I.getAlignment() < VT.getSizeInBits() / 8)
3795 report_fatal_error("Cannot generate unaligned atomic load");
3797 MachineMemOperand *MMO =
3798 DAG.getMachineFunction().
3799 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3800 MachineMemOperand::MOVolatile |
3801 MachineMemOperand::MOLoad,
3803 I.getAlignment() ? I.getAlignment() :
3804 DAG.getEVTAlignment(VT));
3806 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3808 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3809 getValue(I.getPointerOperand()), MMO,
3812 SDValue OutChain = L.getValue(1);
3815 DAG.setRoot(OutChain);
3818 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3819 SDLoc dl = getCurSDLoc();
3821 AtomicOrdering Order = I.getOrdering();
3822 SynchronizationScope Scope = I.getSynchScope();
3824 SDValue InChain = getRoot();
3826 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3827 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3829 if (I.getAlignment() < VT.getSizeInBits() / 8)
3830 report_fatal_error("Cannot generate unaligned atomic store");
3833 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3835 getValue(I.getPointerOperand()),
3836 getValue(I.getValueOperand()),
3837 I.getPointerOperand(), I.getAlignment(),
3840 DAG.setRoot(OutChain);
3843 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3845 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3846 unsigned Intrinsic) {
3847 bool HasChain = !I.doesNotAccessMemory();
3848 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3850 // Build the operand list.
3851 SmallVector<SDValue, 8> Ops;
3852 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3854 // We don't need to serialize loads against other loads.
3855 Ops.push_back(DAG.getRoot());
3857 Ops.push_back(getRoot());
3861 // Info is set by getTgtMemInstrinsic
3862 TargetLowering::IntrinsicInfo Info;
3863 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3864 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3866 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3867 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3868 Info.opc == ISD::INTRINSIC_W_CHAIN)
3869 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3871 // Add all operands of the call to the operand list.
3872 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3873 SDValue Op = getValue(I.getArgOperand(i));
3877 SmallVector<EVT, 4> ValueVTs;
3878 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3881 ValueVTs.push_back(MVT::Other);
3883 SDVTList VTs = DAG.getVTList(ValueVTs);
3887 if (IsTgtIntrinsic) {
3888 // This is target intrinsic that touches memory
3889 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3890 VTs, Ops, Info.memVT,
3891 MachinePointerInfo(Info.ptrVal, Info.offset),
3892 Info.align, Info.vol,
3893 Info.readMem, Info.writeMem, Info.size);
3894 } else if (!HasChain) {
3895 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3896 } else if (!I.getType()->isVoidTy()) {
3897 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3899 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3903 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3905 PendingLoads.push_back(Chain);
3910 if (!I.getType()->isVoidTy()) {
3911 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3912 EVT VT = TLI.getValueType(PTy);
3913 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3916 setValue(&I, Result);
3920 /// GetSignificand - Get the significand and build it into a floating-point
3921 /// number with exponent of 1:
3923 /// Op = (Op & 0x007fffff) | 0x3f800000;
3925 /// where Op is the hexadecimal representation of floating point value.
3927 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3928 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3929 DAG.getConstant(0x007fffff, MVT::i32));
3930 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3931 DAG.getConstant(0x3f800000, MVT::i32));
3932 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3935 /// GetExponent - Get the exponent:
3937 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3939 /// where Op is the hexadecimal representation of floating point value.
3941 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3943 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3944 DAG.getConstant(0x7f800000, MVT::i32));
3945 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3946 DAG.getConstant(23, TLI.getPointerTy()));
3947 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3948 DAG.getConstant(127, MVT::i32));
3949 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3952 /// getF32Constant - Get 32-bit floating point constant.
3954 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3955 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3959 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3960 /// limited-precision mode.
3961 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3962 const TargetLowering &TLI) {
3963 if (Op.getValueType() == MVT::f32 &&
3964 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3966 // Put the exponent in the right bit position for later addition to the
3969 // #define LOG2OFe 1.4426950f
3970 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3971 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3972 getF32Constant(DAG, 0x3fb8aa3b));
3973 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3975 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3976 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3977 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3979 // IntegerPartOfX <<= 23;
3980 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3981 DAG.getConstant(23, TLI.getPointerTy()));
3983 SDValue TwoToFracPartOfX;
3984 if (LimitFloatPrecision <= 6) {
3985 // For floating-point precision of 6:
3987 // TwoToFractionalPartOfX =
3989 // (0.735607626f + 0.252464424f * x) * x;
3991 // error 0.0144103317, which is 6 bits
3992 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3993 getF32Constant(DAG, 0x3e814304));
3994 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3995 getF32Constant(DAG, 0x3f3c50c8));
3996 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3997 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3998 getF32Constant(DAG, 0x3f7f5e7e));
3999 } else if (LimitFloatPrecision <= 12) {
4000 // For floating-point precision of 12:
4002 // TwoToFractionalPartOfX =
4005 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4007 // 0.000107046256 error, which is 13 to 14 bits
4008 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4009 getF32Constant(DAG, 0x3da235e3));
4010 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4011 getF32Constant(DAG, 0x3e65b8f3));
4012 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4013 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4014 getF32Constant(DAG, 0x3f324b07));
4015 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4016 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4017 getF32Constant(DAG, 0x3f7ff8fd));
4018 } else { // LimitFloatPrecision <= 18
4019 // For floating-point precision of 18:
4021 // TwoToFractionalPartOfX =
4025 // (0.554906021e-1f +
4026 // (0.961591928e-2f +
4027 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4029 // error 2.47208000*10^(-7), which is better than 18 bits
4030 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4031 getF32Constant(DAG, 0x3924b03e));
4032 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4033 getF32Constant(DAG, 0x3ab24b87));
4034 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4035 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4036 getF32Constant(DAG, 0x3c1d8c17));
4037 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4038 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4039 getF32Constant(DAG, 0x3d634a1d));
4040 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4041 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4042 getF32Constant(DAG, 0x3e75fe14));
4043 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4044 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4045 getF32Constant(DAG, 0x3f317234));
4046 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4047 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4048 getF32Constant(DAG, 0x3f800000));
4051 // Add the exponent into the result in integer domain.
4052 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
4053 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4054 DAG.getNode(ISD::ADD, dl, MVT::i32,
4055 t13, IntegerPartOfX));
4058 // No special expansion.
4059 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4062 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4063 /// limited-precision mode.
4064 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4065 const TargetLowering &TLI) {
4066 if (Op.getValueType() == MVT::f32 &&
4067 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4068 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4070 // Scale the exponent by log(2) [0.69314718f].
4071 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4072 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4073 getF32Constant(DAG, 0x3f317218));
4075 // Get the significand and build it into a floating-point number with
4077 SDValue X = GetSignificand(DAG, Op1, dl);
4079 SDValue LogOfMantissa;
4080 if (LimitFloatPrecision <= 6) {
4081 // For floating-point precision of 6:
4085 // (1.4034025f - 0.23903021f * x) * x;
4087 // error 0.0034276066, which is better than 8 bits
4088 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4089 getF32Constant(DAG, 0xbe74c456));
4090 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4091 getF32Constant(DAG, 0x3fb3a2b1));
4092 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4093 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4094 getF32Constant(DAG, 0x3f949a29));
4095 } else if (LimitFloatPrecision <= 12) {
4096 // For floating-point precision of 12:
4102 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4104 // error 0.000061011436, which is 14 bits
4105 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4106 getF32Constant(DAG, 0xbd67b6d6));
4107 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4108 getF32Constant(DAG, 0x3ee4f4b8));
4109 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4110 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4111 getF32Constant(DAG, 0x3fbc278b));
4112 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4113 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4114 getF32Constant(DAG, 0x40348e95));
4115 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4116 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4117 getF32Constant(DAG, 0x3fdef31a));
4118 } else { // LimitFloatPrecision <= 18
4119 // For floating-point precision of 18:
4127 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4129 // error 0.0000023660568, which is better than 18 bits
4130 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4131 getF32Constant(DAG, 0xbc91e5ac));
4132 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4133 getF32Constant(DAG, 0x3e4350aa));
4134 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4135 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4136 getF32Constant(DAG, 0x3f60d3e3));
4137 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4138 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4139 getF32Constant(DAG, 0x4011cdf0));
4140 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4141 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4142 getF32Constant(DAG, 0x406cfd1c));
4143 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4144 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4145 getF32Constant(DAG, 0x408797cb));
4146 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4147 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4148 getF32Constant(DAG, 0x4006dcab));
4151 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4154 // No special expansion.
4155 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4158 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4159 /// limited-precision mode.
4160 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4161 const TargetLowering &TLI) {
4162 if (Op.getValueType() == MVT::f32 &&
4163 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4164 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4166 // Get the exponent.
4167 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4169 // Get the significand and build it into a floating-point number with
4171 SDValue X = GetSignificand(DAG, Op1, dl);
4173 // Different possible minimax approximations of significand in
4174 // floating-point for various degrees of accuracy over [1,2].
4175 SDValue Log2ofMantissa;
4176 if (LimitFloatPrecision <= 6) {
4177 // For floating-point precision of 6:
4179 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4181 // error 0.0049451742, which is more than 7 bits
4182 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4183 getF32Constant(DAG, 0xbeb08fe0));
4184 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4185 getF32Constant(DAG, 0x40019463));
4186 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4187 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4188 getF32Constant(DAG, 0x3fd6633d));
4189 } else if (LimitFloatPrecision <= 12) {
4190 // For floating-point precision of 12:
4196 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4198 // error 0.0000876136000, which is better than 13 bits
4199 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4200 getF32Constant(DAG, 0xbda7262e));
4201 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4202 getF32Constant(DAG, 0x3f25280b));
4203 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4204 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4205 getF32Constant(DAG, 0x4007b923));
4206 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4207 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4208 getF32Constant(DAG, 0x40823e2f));
4209 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4210 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4211 getF32Constant(DAG, 0x4020d29c));
4212 } else { // LimitFloatPrecision <= 18
4213 // For floating-point precision of 18:
4222 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4224 // error 0.0000018516, which is better than 18 bits
4225 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4226 getF32Constant(DAG, 0xbcd2769e));
4227 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4228 getF32Constant(DAG, 0x3e8ce0b9));
4229 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4230 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4231 getF32Constant(DAG, 0x3fa22ae7));
4232 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4233 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4234 getF32Constant(DAG, 0x40525723));
4235 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4236 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4237 getF32Constant(DAG, 0x40aaf200));
4238 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4239 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4240 getF32Constant(DAG, 0x40c39dad));
4241 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4242 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4243 getF32Constant(DAG, 0x4042902c));
4246 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4249 // No special expansion.
4250 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4253 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4254 /// limited-precision mode.
4255 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4256 const TargetLowering &TLI) {
4257 if (Op.getValueType() == MVT::f32 &&
4258 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4259 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4261 // Scale the exponent by log10(2) [0.30102999f].
4262 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4263 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4264 getF32Constant(DAG, 0x3e9a209a));
4266 // Get the significand and build it into a floating-point number with
4268 SDValue X = GetSignificand(DAG, Op1, dl);
4270 SDValue Log10ofMantissa;
4271 if (LimitFloatPrecision <= 6) {
4272 // For floating-point precision of 6:
4274 // Log10ofMantissa =
4276 // (0.60948995f - 0.10380950f * x) * x;
4278 // error 0.0014886165, which is 6 bits
4279 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4280 getF32Constant(DAG, 0xbdd49a13));
4281 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4282 getF32Constant(DAG, 0x3f1c0789));
4283 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4284 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4285 getF32Constant(DAG, 0x3f011300));
4286 } else if (LimitFloatPrecision <= 12) {
4287 // For floating-point precision of 12:
4289 // Log10ofMantissa =
4292 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4294 // error 0.00019228036, which is better than 12 bits
4295 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4296 getF32Constant(DAG, 0x3d431f31));
4297 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4298 getF32Constant(DAG, 0x3ea21fb2));
4299 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4300 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4301 getF32Constant(DAG, 0x3f6ae232));
4302 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4303 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4304 getF32Constant(DAG, 0x3f25f7c3));
4305 } else { // LimitFloatPrecision <= 18
4306 // For floating-point precision of 18:
4308 // Log10ofMantissa =
4313 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4315 // error 0.0000037995730, which is better than 18 bits
4316 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4317 getF32Constant(DAG, 0x3c5d51ce));
4318 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4319 getF32Constant(DAG, 0x3e00685a));
4320 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4321 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4322 getF32Constant(DAG, 0x3efb6798));
4323 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4324 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4325 getF32Constant(DAG, 0x3f88d192));
4326 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4327 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4328 getF32Constant(DAG, 0x3fc4316c));
4329 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4330 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4331 getF32Constant(DAG, 0x3f57ce70));
4334 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4337 // No special expansion.
4338 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4341 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4342 /// limited-precision mode.
4343 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4344 const TargetLowering &TLI) {
4345 if (Op.getValueType() == MVT::f32 &&
4346 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4347 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4349 // FractionalPartOfX = x - (float)IntegerPartOfX;
4350 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4351 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4353 // IntegerPartOfX <<= 23;
4354 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4355 DAG.getConstant(23, TLI.getPointerTy()));
4357 SDValue TwoToFractionalPartOfX;
4358 if (LimitFloatPrecision <= 6) {
4359 // For floating-point precision of 6:
4361 // TwoToFractionalPartOfX =
4363 // (0.735607626f + 0.252464424f * x) * x;
4365 // error 0.0144103317, which is 6 bits
4366 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4367 getF32Constant(DAG, 0x3e814304));
4368 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4369 getF32Constant(DAG, 0x3f3c50c8));
4370 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4371 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4372 getF32Constant(DAG, 0x3f7f5e7e));
4373 } else if (LimitFloatPrecision <= 12) {
4374 // For floating-point precision of 12:
4376 // TwoToFractionalPartOfX =
4379 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4381 // error 0.000107046256, which is 13 to 14 bits
4382 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4383 getF32Constant(DAG, 0x3da235e3));
4384 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4385 getF32Constant(DAG, 0x3e65b8f3));
4386 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4387 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4388 getF32Constant(DAG, 0x3f324b07));
4389 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4390 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4391 getF32Constant(DAG, 0x3f7ff8fd));
4392 } else { // LimitFloatPrecision <= 18
4393 // For floating-point precision of 18:
4395 // TwoToFractionalPartOfX =
4399 // (0.554906021e-1f +
4400 // (0.961591928e-2f +
4401 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4402 // error 2.47208000*10^(-7), which is better than 18 bits
4403 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4404 getF32Constant(DAG, 0x3924b03e));
4405 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4406 getF32Constant(DAG, 0x3ab24b87));
4407 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4408 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4409 getF32Constant(DAG, 0x3c1d8c17));
4410 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4411 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4412 getF32Constant(DAG, 0x3d634a1d));
4413 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4414 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4415 getF32Constant(DAG, 0x3e75fe14));
4416 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4417 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4418 getF32Constant(DAG, 0x3f317234));
4419 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4420 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4421 getF32Constant(DAG, 0x3f800000));
4424 // Add the exponent into the result in integer domain.
4425 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4426 TwoToFractionalPartOfX);
4427 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4428 DAG.getNode(ISD::ADD, dl, MVT::i32,
4429 t13, IntegerPartOfX));
4432 // No special expansion.
4433 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4436 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4437 /// limited-precision mode with x == 10.0f.
4438 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4439 SelectionDAG &DAG, const TargetLowering &TLI) {
4440 bool IsExp10 = false;
4441 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4442 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4443 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4445 IsExp10 = LHSC->isExactlyValue(Ten);
4450 // Put the exponent in the right bit position for later addition to the
4453 // #define LOG2OF10 3.3219281f
4454 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4455 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4456 getF32Constant(DAG, 0x40549a78));
4457 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4459 // FractionalPartOfX = x - (float)IntegerPartOfX;
4460 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4461 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4463 // IntegerPartOfX <<= 23;
4464 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4465 DAG.getConstant(23, TLI.getPointerTy()));
4467 SDValue TwoToFractionalPartOfX;
4468 if (LimitFloatPrecision <= 6) {
4469 // For floating-point precision of 6:
4471 // twoToFractionalPartOfX =
4473 // (0.735607626f + 0.252464424f * x) * x;
4475 // error 0.0144103317, which is 6 bits
4476 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4477 getF32Constant(DAG, 0x3e814304));
4478 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4479 getF32Constant(DAG, 0x3f3c50c8));
4480 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4481 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4482 getF32Constant(DAG, 0x3f7f5e7e));
4483 } else if (LimitFloatPrecision <= 12) {
4484 // For floating-point precision of 12:
4486 // TwoToFractionalPartOfX =
4489 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4491 // error 0.000107046256, which is 13 to 14 bits
4492 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4493 getF32Constant(DAG, 0x3da235e3));
4494 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4495 getF32Constant(DAG, 0x3e65b8f3));
4496 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4497 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4498 getF32Constant(DAG, 0x3f324b07));
4499 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4500 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4501 getF32Constant(DAG, 0x3f7ff8fd));
4502 } else { // LimitFloatPrecision <= 18
4503 // For floating-point precision of 18:
4505 // TwoToFractionalPartOfX =
4509 // (0.554906021e-1f +
4510 // (0.961591928e-2f +
4511 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4512 // error 2.47208000*10^(-7), which is better than 18 bits
4513 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4514 getF32Constant(DAG, 0x3924b03e));
4515 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4516 getF32Constant(DAG, 0x3ab24b87));
4517 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4518 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4519 getF32Constant(DAG, 0x3c1d8c17));
4520 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4521 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4522 getF32Constant(DAG, 0x3d634a1d));
4523 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4524 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4525 getF32Constant(DAG, 0x3e75fe14));
4526 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4527 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4528 getF32Constant(DAG, 0x3f317234));
4529 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4530 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4531 getF32Constant(DAG, 0x3f800000));
4534 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4535 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4536 DAG.getNode(ISD::ADD, dl, MVT::i32,
4537 t13, IntegerPartOfX));
4540 // No special expansion.
4541 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4545 /// ExpandPowI - Expand a llvm.powi intrinsic.
4546 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4547 SelectionDAG &DAG) {
4548 // If RHS is a constant, we can expand this out to a multiplication tree,
4549 // otherwise we end up lowering to a call to __powidf2 (for example). When
4550 // optimizing for size, we only want to do this if the expansion would produce
4551 // a small number of multiplies, otherwise we do the full expansion.
4552 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4553 // Get the exponent as a positive value.
4554 unsigned Val = RHSC->getSExtValue();
4555 if ((int)Val < 0) Val = -Val;
4557 // powi(x, 0) -> 1.0
4559 return DAG.getConstantFP(1.0, LHS.getValueType());
4561 const Function *F = DAG.getMachineFunction().getFunction();
4562 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4563 Attribute::OptimizeForSize) ||
4564 // If optimizing for size, don't insert too many multiplies. This
4565 // inserts up to 5 multiplies.
4566 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4567 // We use the simple binary decomposition method to generate the multiply
4568 // sequence. There are more optimal ways to do this (for example,
4569 // powi(x,15) generates one more multiply than it should), but this has
4570 // the benefit of being both really simple and much better than a libcall.
4571 SDValue Res; // Logically starts equal to 1.0
4572 SDValue CurSquare = LHS;
4576 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4578 Res = CurSquare; // 1.0*CurSquare.
4581 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4582 CurSquare, CurSquare);
4586 // If the original was negative, invert the result, producing 1/(x*x*x).
4587 if (RHSC->getSExtValue() < 0)
4588 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4589 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4594 // Otherwise, expand to a libcall.
4595 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4598 // getTruncatedArgReg - Find underlying register used for an truncated
4600 static unsigned getTruncatedArgReg(const SDValue &N) {
4601 if (N.getOpcode() != ISD::TRUNCATE)
4604 const SDValue &Ext = N.getOperand(0);
4605 if (Ext.getOpcode() == ISD::AssertZext ||
4606 Ext.getOpcode() == ISD::AssertSext) {
4607 const SDValue &CFR = Ext.getOperand(0);
4608 if (CFR.getOpcode() == ISD::CopyFromReg)
4609 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4610 if (CFR.getOpcode() == ISD::TRUNCATE)
4611 return getTruncatedArgReg(CFR);
4616 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4617 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4618 /// At the end of instruction selection, they will be inserted to the entry BB.
4619 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V,
4621 MDNode *Expr, int64_t Offset,
4624 const Argument *Arg = dyn_cast<Argument>(V);
4628 MachineFunction &MF = DAG.getMachineFunction();
4629 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4631 // Ignore inlined function arguments here.
4632 DIVariable DV(Variable);
4633 if (DV.isInlinedFnArgument(MF.getFunction()))
4636 Optional<MachineOperand> Op;
4637 // Some arguments' frame index is recorded during argument lowering.
4638 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4639 Op = MachineOperand::CreateFI(FI);
4641 if (!Op && N.getNode()) {
4643 if (N.getOpcode() == ISD::CopyFromReg)
4644 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4646 Reg = getTruncatedArgReg(N);
4647 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4648 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4649 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4654 Op = MachineOperand::CreateReg(Reg, false);
4658 // Check if ValueMap has reg number.
4659 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4660 if (VMI != FuncInfo.ValueMap.end())
4661 Op = MachineOperand::CreateReg(VMI->second, false);
4664 if (!Op && N.getNode())
4665 // Check if frame index is available.
4666 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4667 if (FrameIndexSDNode *FINode =
4668 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4669 Op = MachineOperand::CreateFI(FINode->getIndex());
4675 FuncInfo.ArgDbgValues.push_back(
4676 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE),
4677 IsIndirect, Op->getReg(), Offset, Variable, Expr));
4679 FuncInfo.ArgDbgValues.push_back(
4680 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4683 .addMetadata(Variable)
4684 .addMetadata(Expr));
4689 // VisualStudio defines setjmp as _setjmp
4690 #if defined(_MSC_VER) && defined(setjmp) && \
4691 !defined(setjmp_undefined_for_msvc)
4692 # pragma push_macro("setjmp")
4694 # define setjmp_undefined_for_msvc
4697 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4698 /// we want to emit this as a call to a named external function, return the name
4699 /// otherwise lower it and return null.
4701 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4702 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4703 SDLoc sdl = getCurSDLoc();
4704 DebugLoc dl = getCurDebugLoc();
4707 switch (Intrinsic) {
4709 // By default, turn this into a target intrinsic node.
4710 visitTargetIntrinsic(I, Intrinsic);
4712 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4713 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4714 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4715 case Intrinsic::returnaddress:
4716 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4717 getValue(I.getArgOperand(0))));
4719 case Intrinsic::frameaddress:
4720 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4721 getValue(I.getArgOperand(0))));
4723 case Intrinsic::read_register: {
4724 Value *Reg = I.getArgOperand(0);
4726 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4727 EVT VT = TLI.getValueType(I.getType());
4728 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4731 case Intrinsic::write_register: {
4732 Value *Reg = I.getArgOperand(0);
4733 Value *RegValue = I.getArgOperand(1);
4734 SDValue Chain = getValue(RegValue).getOperand(0);
4736 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4737 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4738 RegName, getValue(RegValue)));
4741 case Intrinsic::setjmp:
4742 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4743 case Intrinsic::longjmp:
4744 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4745 case Intrinsic::memcpy: {
4746 // Assert for address < 256 since we support only user defined address
4748 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4750 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4752 "Unknown address space");
4753 SDValue Op1 = getValue(I.getArgOperand(0));
4754 SDValue Op2 = getValue(I.getArgOperand(1));
4755 SDValue Op3 = getValue(I.getArgOperand(2));
4756 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4758 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4759 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4760 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4761 MachinePointerInfo(I.getArgOperand(0)),
4762 MachinePointerInfo(I.getArgOperand(1))));
4765 case Intrinsic::memset: {
4766 // Assert for address < 256 since we support only user defined address
4768 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4770 "Unknown address space");
4771 SDValue Op1 = getValue(I.getArgOperand(0));
4772 SDValue Op2 = getValue(I.getArgOperand(1));
4773 SDValue Op3 = getValue(I.getArgOperand(2));
4774 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4776 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4777 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4778 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4779 MachinePointerInfo(I.getArgOperand(0))));
4782 case Intrinsic::memmove: {
4783 // Assert for address < 256 since we support only user defined address
4785 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4787 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4789 "Unknown address space");
4790 SDValue Op1 = getValue(I.getArgOperand(0));
4791 SDValue Op2 = getValue(I.getArgOperand(1));
4792 SDValue Op3 = getValue(I.getArgOperand(2));
4793 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4795 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4796 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4797 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4798 MachinePointerInfo(I.getArgOperand(0)),
4799 MachinePointerInfo(I.getArgOperand(1))));
4802 case Intrinsic::dbg_declare: {
4803 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4804 MDNode *Variable = DI.getVariable();
4805 MDNode *Expression = DI.getExpression();
4806 const Value *Address = DI.getAddress();
4807 DIVariable DIVar(Variable);
4808 assert((!DIVar || DIVar.isVariable()) &&
4809 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4810 if (!Address || !DIVar) {
4811 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4815 // Check if address has undef value.
4816 if (isa<UndefValue>(Address) ||
4817 (Address->use_empty() && !isa<Argument>(Address))) {
4818 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4822 SDValue &N = NodeMap[Address];
4823 if (!N.getNode() && isa<Argument>(Address))
4824 // Check unused arguments map.
4825 N = UnusedArgNodeMap[Address];
4828 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4829 Address = BCI->getOperand(0);
4830 // Parameters are handled specially.
4832 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4833 isa<Argument>(Address));
4835 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4837 if (isParameter && !AI) {
4838 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4840 // Byval parameter. We have a frame index at this point.
4841 SDV = DAG.getFrameIndexDbgValue(
4842 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4844 // Address is an argument, so try to emit its dbg value using
4845 // virtual register info from the FuncInfo.ValueMap.
4846 EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false, N);
4850 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4851 true, 0, dl, SDNodeOrder);
4853 // Can't do anything with other non-AI cases yet.
4854 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4855 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4856 DEBUG(Address->dump());
4859 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4861 // If Address is an argument then try to emit its dbg value using
4862 // virtual register info from the FuncInfo.ValueMap.
4863 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false,
4865 // If variable is pinned by a alloca in dominating bb then
4866 // use StaticAllocaMap.
4867 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4868 if (AI->getParent() != DI.getParent()) {
4869 DenseMap<const AllocaInst*, int>::iterator SI =
4870 FuncInfo.StaticAllocaMap.find(AI);
4871 if (SI != FuncInfo.StaticAllocaMap.end()) {
4872 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4873 0, dl, SDNodeOrder);
4874 DAG.AddDbgValue(SDV, nullptr, false);
4879 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4884 case Intrinsic::dbg_value: {
4885 const DbgValueInst &DI = cast<DbgValueInst>(I);
4886 DIVariable DIVar(DI.getVariable());
4887 assert((!DIVar || DIVar.isVariable()) &&
4888 "Variable in DbgValueInst should be either null or a DIVariable.");
4892 MDNode *Variable = DI.getVariable();
4893 MDNode *Expression = DI.getExpression();
4894 uint64_t Offset = DI.getOffset();
4895 const Value *V = DI.getValue();
4900 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4901 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4903 DAG.AddDbgValue(SDV, nullptr, false);
4905 // Do not use getValue() in here; we don't want to generate code at
4906 // this point if it hasn't been done yet.
4907 SDValue N = NodeMap[V];
4908 if (!N.getNode() && isa<Argument>(V))
4909 // Check unused arguments map.
4910 N = UnusedArgNodeMap[V];
4912 // A dbg.value for an alloca is always indirect.
4913 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4914 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, Offset,
4916 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4917 IsIndirect, Offset, dl, SDNodeOrder);
4918 DAG.AddDbgValue(SDV, N.getNode(), false);
4920 } else if (!V->use_empty() ) {
4921 // Do not call getValue(V) yet, as we don't want to generate code.
4922 // Remember it for later.
4923 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4924 DanglingDebugInfoMap[V] = DDI;
4926 // We may expand this to cover more cases. One case where we have no
4927 // data available is an unreferenced parameter.
4928 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4932 // Build a debug info table entry.
4933 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4934 V = BCI->getOperand(0);
4935 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4936 // Don't handle byval struct arguments or VLAs, for example.
4938 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4939 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4942 DenseMap<const AllocaInst*, int>::iterator SI =
4943 FuncInfo.StaticAllocaMap.find(AI);
4944 if (SI == FuncInfo.StaticAllocaMap.end())
4945 return nullptr; // VLAs.
4949 case Intrinsic::eh_typeid_for: {
4950 // Find the type id for the given typeinfo.
4951 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4952 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4953 Res = DAG.getConstant(TypeID, MVT::i32);
4958 case Intrinsic::eh_return_i32:
4959 case Intrinsic::eh_return_i64:
4960 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4961 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4964 getValue(I.getArgOperand(0)),
4965 getValue(I.getArgOperand(1))));
4967 case Intrinsic::eh_unwind_init:
4968 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4970 case Intrinsic::eh_dwarf_cfa: {
4971 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4972 TLI.getPointerTy());
4973 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4974 CfaArg.getValueType(),
4975 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4976 CfaArg.getValueType()),
4978 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4979 DAG.getConstant(0, TLI.getPointerTy()));
4980 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4984 case Intrinsic::eh_sjlj_callsite: {
4985 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4986 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4987 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4988 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4990 MMI.setCurrentCallSite(CI->getZExtValue());
4993 case Intrinsic::eh_sjlj_functioncontext: {
4994 // Get and store the index of the function context.
4995 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4997 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4998 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4999 MFI->setFunctionContextIndex(FI);
5002 case Intrinsic::eh_sjlj_setjmp: {
5005 Ops[1] = getValue(I.getArgOperand(0));
5006 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
5007 DAG.getVTList(MVT::i32, MVT::Other), Ops);
5008 setValue(&I, Op.getValue(0));
5009 DAG.setRoot(Op.getValue(1));
5012 case Intrinsic::eh_sjlj_longjmp: {
5013 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
5014 getRoot(), getValue(I.getArgOperand(0))));
5018 case Intrinsic::masked_load:
5021 case Intrinsic::masked_store:
5022 visitMaskedStore(I);
5024 case Intrinsic::x86_mmx_pslli_w:
5025 case Intrinsic::x86_mmx_pslli_d:
5026 case Intrinsic::x86_mmx_pslli_q:
5027 case Intrinsic::x86_mmx_psrli_w:
5028 case Intrinsic::x86_mmx_psrli_d:
5029 case Intrinsic::x86_mmx_psrli_q:
5030 case Intrinsic::x86_mmx_psrai_w:
5031 case Intrinsic::x86_mmx_psrai_d: {
5032 SDValue ShAmt = getValue(I.getArgOperand(1));
5033 if (isa<ConstantSDNode>(ShAmt)) {
5034 visitTargetIntrinsic(I, Intrinsic);
5037 unsigned NewIntrinsic = 0;
5038 EVT ShAmtVT = MVT::v2i32;
5039 switch (Intrinsic) {
5040 case Intrinsic::x86_mmx_pslli_w:
5041 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
5043 case Intrinsic::x86_mmx_pslli_d:
5044 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
5046 case Intrinsic::x86_mmx_pslli_q:
5047 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
5049 case Intrinsic::x86_mmx_psrli_w:
5050 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
5052 case Intrinsic::x86_mmx_psrli_d:
5053 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
5055 case Intrinsic::x86_mmx_psrli_q:
5056 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
5058 case Intrinsic::x86_mmx_psrai_w:
5059 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
5061 case Intrinsic::x86_mmx_psrai_d:
5062 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
5064 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5067 // The vector shift intrinsics with scalars uses 32b shift amounts but
5068 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5070 // We must do this early because v2i32 is not a legal type.
5073 ShOps[1] = DAG.getConstant(0, MVT::i32);
5074 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
5075 EVT DestVT = TLI.getValueType(I.getType());
5076 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5077 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5078 DAG.getConstant(NewIntrinsic, MVT::i32),
5079 getValue(I.getArgOperand(0)), ShAmt);
5083 case Intrinsic::x86_avx_vinsertf128_pd_256:
5084 case Intrinsic::x86_avx_vinsertf128_ps_256:
5085 case Intrinsic::x86_avx_vinsertf128_si_256:
5086 case Intrinsic::x86_avx2_vinserti128: {
5087 EVT DestVT = TLI.getValueType(I.getType());
5088 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
5089 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
5090 ElVT.getVectorNumElements();
5092 DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
5093 getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)),
5094 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5098 case Intrinsic::x86_avx_vextractf128_pd_256:
5099 case Intrinsic::x86_avx_vextractf128_ps_256:
5100 case Intrinsic::x86_avx_vextractf128_si_256:
5101 case Intrinsic::x86_avx2_vextracti128: {
5102 EVT DestVT = TLI.getValueType(I.getType());
5103 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5104 DestVT.getVectorNumElements();
5105 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5106 getValue(I.getArgOperand(0)),
5107 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5111 case Intrinsic::convertff:
5112 case Intrinsic::convertfsi:
5113 case Intrinsic::convertfui:
5114 case Intrinsic::convertsif:
5115 case Intrinsic::convertuif:
5116 case Intrinsic::convertss:
5117 case Intrinsic::convertsu:
5118 case Intrinsic::convertus:
5119 case Intrinsic::convertuu: {
5120 ISD::CvtCode Code = ISD::CVT_INVALID;
5121 switch (Intrinsic) {
5122 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5123 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5124 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5125 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5126 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5127 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5128 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5129 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5130 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5131 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5133 EVT DestVT = TLI.getValueType(I.getType());
5134 const Value *Op1 = I.getArgOperand(0);
5135 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5136 DAG.getValueType(DestVT),
5137 DAG.getValueType(getValue(Op1).getValueType()),
5138 getValue(I.getArgOperand(1)),
5139 getValue(I.getArgOperand(2)),
5144 case Intrinsic::powi:
5145 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5146 getValue(I.getArgOperand(1)), DAG));
5148 case Intrinsic::log:
5149 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5151 case Intrinsic::log2:
5152 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5154 case Intrinsic::log10:
5155 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5157 case Intrinsic::exp:
5158 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5160 case Intrinsic::exp2:
5161 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5163 case Intrinsic::pow:
5164 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5165 getValue(I.getArgOperand(1)), DAG, TLI));
5167 case Intrinsic::sqrt:
5168 case Intrinsic::fabs:
5169 case Intrinsic::sin:
5170 case Intrinsic::cos:
5171 case Intrinsic::floor:
5172 case Intrinsic::ceil:
5173 case Intrinsic::trunc:
5174 case Intrinsic::rint:
5175 case Intrinsic::nearbyint:
5176 case Intrinsic::round: {
5178 switch (Intrinsic) {
5179 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5180 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5181 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5182 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5183 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5184 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5185 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5186 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5187 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5188 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5189 case Intrinsic::round: Opcode = ISD::FROUND; break;
5192 setValue(&I, DAG.getNode(Opcode, sdl,
5193 getValue(I.getArgOperand(0)).getValueType(),
5194 getValue(I.getArgOperand(0))));
5197 case Intrinsic::minnum:
5198 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
5199 getValue(I.getArgOperand(0)).getValueType(),
5200 getValue(I.getArgOperand(0)),
5201 getValue(I.getArgOperand(1))));
5203 case Intrinsic::maxnum:
5204 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
5205 getValue(I.getArgOperand(0)).getValueType(),
5206 getValue(I.getArgOperand(0)),
5207 getValue(I.getArgOperand(1))));
5209 case Intrinsic::copysign:
5210 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5211 getValue(I.getArgOperand(0)).getValueType(),
5212 getValue(I.getArgOperand(0)),
5213 getValue(I.getArgOperand(1))));
5215 case Intrinsic::fma:
5216 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5217 getValue(I.getArgOperand(0)).getValueType(),
5218 getValue(I.getArgOperand(0)),
5219 getValue(I.getArgOperand(1)),
5220 getValue(I.getArgOperand(2))));
5222 case Intrinsic::fmuladd: {
5223 EVT VT = TLI.getValueType(I.getType());
5224 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5225 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5226 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5227 getValue(I.getArgOperand(0)).getValueType(),
5228 getValue(I.getArgOperand(0)),
5229 getValue(I.getArgOperand(1)),
5230 getValue(I.getArgOperand(2))));
5232 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5233 getValue(I.getArgOperand(0)).getValueType(),
5234 getValue(I.getArgOperand(0)),
5235 getValue(I.getArgOperand(1)));
5236 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5237 getValue(I.getArgOperand(0)).getValueType(),
5239 getValue(I.getArgOperand(2)));
5244 case Intrinsic::convert_to_fp16:
5245 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5246 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5247 getValue(I.getArgOperand(0)),
5248 DAG.getTargetConstant(0, MVT::i32))));
5250 case Intrinsic::convert_from_fp16:
5252 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
5253 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5254 getValue(I.getArgOperand(0)))));
5256 case Intrinsic::pcmarker: {
5257 SDValue Tmp = getValue(I.getArgOperand(0));
5258 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5261 case Intrinsic::readcyclecounter: {
5262 SDValue Op = getRoot();
5263 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5264 DAG.getVTList(MVT::i64, MVT::Other), Op);
5266 DAG.setRoot(Res.getValue(1));
5269 case Intrinsic::bswap:
5270 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5271 getValue(I.getArgOperand(0)).getValueType(),
5272 getValue(I.getArgOperand(0))));
5274 case Intrinsic::cttz: {
5275 SDValue Arg = getValue(I.getArgOperand(0));
5276 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5277 EVT Ty = Arg.getValueType();
5278 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5282 case Intrinsic::ctlz: {
5283 SDValue Arg = getValue(I.getArgOperand(0));
5284 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5285 EVT Ty = Arg.getValueType();
5286 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5290 case Intrinsic::ctpop: {
5291 SDValue Arg = getValue(I.getArgOperand(0));
5292 EVT Ty = Arg.getValueType();
5293 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5296 case Intrinsic::stacksave: {
5297 SDValue Op = getRoot();
5298 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5299 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
5301 DAG.setRoot(Res.getValue(1));
5304 case Intrinsic::stackrestore: {
5305 Res = getValue(I.getArgOperand(0));
5306 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5309 case Intrinsic::stackprotector: {
5310 // Emit code into the DAG to store the stack guard onto the stack.
5311 MachineFunction &MF = DAG.getMachineFunction();
5312 MachineFrameInfo *MFI = MF.getFrameInfo();
5313 EVT PtrTy = TLI.getPointerTy();
5314 SDValue Src, Chain = getRoot();
5315 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5316 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5318 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5319 // global variable __stack_chk_guard.
5321 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5322 if (BC->getOpcode() == Instruction::BitCast)
5323 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5325 if (GV && TLI.useLoadStackGuardNode()) {
5326 // Emit a LOAD_STACK_GUARD node.
5327 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5329 MachinePointerInfo MPInfo(GV);
5330 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5331 unsigned Flags = MachineMemOperand::MOLoad |
5332 MachineMemOperand::MOInvariant;
5333 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5334 PtrTy.getSizeInBits() / 8,
5335 DAG.getEVTAlignment(PtrTy));
5336 Node->setMemRefs(MemRefs, MemRefs + 1);
5338 // Copy the guard value to a virtual register so that it can be
5339 // retrieved in the epilogue.
5340 Src = SDValue(Node, 0);
5341 const TargetRegisterClass *RC =
5342 TLI.getRegClassFor(Src.getSimpleValueType());
5343 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5345 SPDescriptor.setGuardReg(Reg);
5346 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5348 Src = getValue(I.getArgOperand(0)); // The guard's value.
5351 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5353 int FI = FuncInfo.StaticAllocaMap[Slot];
5354 MFI->setStackProtectorIndex(FI);
5356 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5358 // Store the stack protector onto the stack.
5359 Res = DAG.getStore(Chain, sdl, Src, FIN,
5360 MachinePointerInfo::getFixedStack(FI),
5366 case Intrinsic::objectsize: {
5367 // If we don't know by now, we're never going to know.
5368 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5370 assert(CI && "Non-constant type in __builtin_object_size?");
5372 SDValue Arg = getValue(I.getCalledValue());
5373 EVT Ty = Arg.getValueType();
5376 Res = DAG.getConstant(-1ULL, Ty);
5378 Res = DAG.getConstant(0, Ty);
5383 case Intrinsic::annotation:
5384 case Intrinsic::ptr_annotation:
5385 // Drop the intrinsic, but forward the value
5386 setValue(&I, getValue(I.getOperand(0)));
5388 case Intrinsic::assume:
5389 case Intrinsic::var_annotation:
5390 // Discard annotate attributes and assumptions
5393 case Intrinsic::init_trampoline: {
5394 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5398 Ops[1] = getValue(I.getArgOperand(0));
5399 Ops[2] = getValue(I.getArgOperand(1));
5400 Ops[3] = getValue(I.getArgOperand(2));
5401 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5402 Ops[5] = DAG.getSrcValue(F);
5404 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5409 case Intrinsic::adjust_trampoline: {
5410 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5412 getValue(I.getArgOperand(0))));
5415 case Intrinsic::gcroot:
5417 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5418 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5420 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5421 GFI->addStackRoot(FI->getIndex(), TypeMap);
5424 case Intrinsic::gcread:
5425 case Intrinsic::gcwrite:
5426 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5427 case Intrinsic::flt_rounds:
5428 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5431 case Intrinsic::expect: {
5432 // Just replace __builtin_expect(exp, c) with EXP.
5433 setValue(&I, getValue(I.getArgOperand(0)));
5437 case Intrinsic::debugtrap:
5438 case Intrinsic::trap: {
5439 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5440 if (TrapFuncName.empty()) {
5441 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5442 ISD::TRAP : ISD::DEBUGTRAP;
5443 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5446 TargetLowering::ArgListTy Args;
5448 TargetLowering::CallLoweringInfo CLI(DAG);
5449 CLI.setDebugLoc(sdl).setChain(getRoot())
5450 .setCallee(CallingConv::C, I.getType(),
5451 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5452 std::move(Args), 0);
5454 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5455 DAG.setRoot(Result.second);
5459 case Intrinsic::uadd_with_overflow:
5460 case Intrinsic::sadd_with_overflow:
5461 case Intrinsic::usub_with_overflow:
5462 case Intrinsic::ssub_with_overflow:
5463 case Intrinsic::umul_with_overflow:
5464 case Intrinsic::smul_with_overflow: {
5466 switch (Intrinsic) {
5467 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5468 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5469 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5470 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5471 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5472 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5473 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5475 SDValue Op1 = getValue(I.getArgOperand(0));
5476 SDValue Op2 = getValue(I.getArgOperand(1));
5478 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5479 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5482 case Intrinsic::prefetch: {
5484 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5486 Ops[1] = getValue(I.getArgOperand(0));
5487 Ops[2] = getValue(I.getArgOperand(1));
5488 Ops[3] = getValue(I.getArgOperand(2));
5489 Ops[4] = getValue(I.getArgOperand(3));
5490 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5491 DAG.getVTList(MVT::Other), Ops,
5492 EVT::getIntegerVT(*Context, 8),
5493 MachinePointerInfo(I.getArgOperand(0)),
5495 false, /* volatile */
5497 rw==1)); /* write */
5500 case Intrinsic::lifetime_start:
5501 case Intrinsic::lifetime_end: {
5502 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5503 // Stack coloring is not enabled in O0, discard region information.
5504 if (TM.getOptLevel() == CodeGenOpt::None)
5507 SmallVector<Value *, 4> Allocas;
5508 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5510 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5511 E = Allocas.end(); Object != E; ++Object) {
5512 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5514 // Could not find an Alloca.
5515 if (!LifetimeObject)
5518 // First check that the Alloca is static, otherwise it won't have a
5519 // valid frame index.
5520 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5521 if (SI == FuncInfo.StaticAllocaMap.end())
5524 int FI = SI->second;
5528 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5529 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5531 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5536 case Intrinsic::invariant_start:
5537 // Discard region information.
5538 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5540 case Intrinsic::invariant_end:
5541 // Discard region information.
5543 case Intrinsic::stackprotectorcheck: {
5544 // Do not actually emit anything for this basic block. Instead we initialize
5545 // the stack protector descriptor and export the guard variable so we can
5546 // access it in FinishBasicBlock.
5547 const BasicBlock *BB = I.getParent();
5548 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5549 ExportFromCurrentBlock(SPDescriptor.getGuard());
5551 // Flush our exports since we are going to process a terminator.
5552 (void)getControlRoot();
5555 case Intrinsic::clear_cache:
5556 return TLI.getClearCacheBuiltinName();
5557 case Intrinsic::donothing:
5560 case Intrinsic::experimental_stackmap: {
5564 case Intrinsic::experimental_patchpoint_void:
5565 case Intrinsic::experimental_patchpoint_i64: {
5566 visitPatchpoint(&I);
5569 case Intrinsic::experimental_gc_statepoint: {
5573 case Intrinsic::experimental_gc_result_int:
5574 case Intrinsic::experimental_gc_result_float:
5575 case Intrinsic::experimental_gc_result_ptr: {
5579 case Intrinsic::experimental_gc_relocate: {
5583 case Intrinsic::instrprof_increment:
5584 llvm_unreachable("instrprof failed to lower an increment");
5586 case Intrinsic::frameallocate: {
5587 MachineFunction &MF = DAG.getMachineFunction();
5588 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5590 // Do the allocation and map it as a normal value.
5591 // FIXME: Maybe we should add this to the alloca map so that we don't have
5592 // to register allocate it?
5593 uint64_t Size = cast<ConstantInt>(I.getArgOperand(0))->getZExtValue();
5594 int Alloc = MF.getFrameInfo()->CreateFrameAllocation(Size);
5595 MVT PtrVT = TLI.getPointerTy(0);
5596 SDValue FIVal = DAG.getFrameIndex(Alloc, PtrVT);
5597 setValue(&I, FIVal);
5599 // Directly emit a FRAME_ALLOC machine instr. Label assignment emission is
5600 // the same on all targets.
5601 MCSymbol *FrameAllocSym =
5602 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(MF.getName());
5603 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5604 TII->get(TargetOpcode::FRAME_ALLOC))
5605 .addSym(FrameAllocSym)
5606 .addFrameIndex(Alloc);
5611 case Intrinsic::framerecover: {
5612 // i8* @llvm.framerecover(i8* %fn, i8* %fp)
5613 MachineFunction &MF = DAG.getMachineFunction();
5614 MVT PtrVT = TLI.getPointerTy(0);
5616 // Get the symbol that defines the frame offset.
5617 Function *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5618 MCSymbol *FrameAllocSym =
5619 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(Fn->getName());
5621 // Create a TargetExternalSymbol for the label to avoid any target lowering
5622 // that would make this PC relative.
5623 StringRef Name = FrameAllocSym->getName();
5624 assert(Name.size() == strlen(Name.data()) && "not null terminated");
5625 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
5627 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
5629 // Add the offset to the FP.
5630 Value *FP = I.getArgOperand(1);
5631 SDValue FPVal = getValue(FP);
5632 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5640 std::pair<SDValue, SDValue>
5641 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5642 MachineBasicBlock *LandingPad) {
5643 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5644 MCSymbol *BeginLabel = nullptr;
5647 // Insert a label before the invoke call to mark the try range. This can be
5648 // used to detect deletion of the invoke via the MachineModuleInfo.
5649 BeginLabel = MMI.getContext().CreateTempSymbol();
5651 // For SjLj, keep track of which landing pads go with which invokes
5652 // so as to maintain the ordering of pads in the LSDA.
5653 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5654 if (CallSiteIndex) {
5655 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5656 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5658 // Now that the call site is handled, stop tracking it.
5659 MMI.setCurrentCallSite(0);
5662 // Both PendingLoads and PendingExports must be flushed here;
5663 // this call might not return.
5665 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5667 CLI.setChain(getRoot());
5670 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
5671 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5673 assert((CLI.IsTailCall || Result.second.getNode()) &&
5674 "Non-null chain expected with non-tail call!");
5675 assert((Result.second.getNode() || !Result.first.getNode()) &&
5676 "Null value expected with tail call!");
5678 if (!Result.second.getNode()) {
5679 // As a special case, a null chain means that a tail call has been emitted
5680 // and the DAG root is already updated.
5683 // Since there's no actual continuation from this block, nothing can be
5684 // relying on us setting vregs for them.
5685 PendingExports.clear();
5687 DAG.setRoot(Result.second);
5691 // Insert a label at the end of the invoke call to mark the try range. This
5692 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5693 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5694 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5696 // Inform MachineModuleInfo of range.
5697 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5703 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5705 MachineBasicBlock *LandingPad) {
5706 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5707 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5708 Type *RetTy = FTy->getReturnType();
5710 TargetLowering::ArgListTy Args;
5711 TargetLowering::ArgListEntry Entry;
5712 Args.reserve(CS.arg_size());
5714 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5716 const Value *V = *i;
5719 if (V->getType()->isEmptyTy())
5722 SDValue ArgNode = getValue(V);
5723 Entry.Node = ArgNode; Entry.Ty = V->getType();
5725 // Skip the first return-type Attribute to get to params.
5726 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5727 Args.push_back(Entry);
5730 // Check if target-independent constraints permit a tail call here.
5731 // Target-dependent constraints are checked within TLI->LowerCallTo.
5732 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5735 TargetLowering::CallLoweringInfo CLI(DAG);
5736 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5737 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5738 .setTailCall(isTailCall);
5739 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5741 if (Result.first.getNode())
5742 setValue(CS.getInstruction(), Result.first);
5745 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5746 /// value is equal or not-equal to zero.
5747 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5748 for (const User *U : V->users()) {
5749 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5750 if (IC->isEquality())
5751 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5752 if (C->isNullValue())
5754 // Unknown instruction.
5760 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5762 SelectionDAGBuilder &Builder) {
5764 // Check to see if this load can be trivially constant folded, e.g. if the
5765 // input is from a string literal.
5766 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5767 // Cast pointer to the type we really want to load.
5768 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5769 PointerType::getUnqual(LoadTy));
5771 if (const Constant *LoadCst =
5772 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5774 return Builder.getValue(LoadCst);
5777 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5778 // still constant memory, the input chain can be the entry node.
5780 bool ConstantMemory = false;
5782 // Do not serialize (non-volatile) loads of constant memory with anything.
5783 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5784 Root = Builder.DAG.getEntryNode();
5785 ConstantMemory = true;
5787 // Do not serialize non-volatile loads against each other.
5788 Root = Builder.DAG.getRoot();
5791 SDValue Ptr = Builder.getValue(PtrVal);
5792 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5793 Ptr, MachinePointerInfo(PtrVal),
5795 false /*nontemporal*/,
5796 false /*isinvariant*/, 1 /* align=1 */);
5798 if (!ConstantMemory)
5799 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5803 /// processIntegerCallValue - Record the value for an instruction that
5804 /// produces an integer result, converting the type where necessary.
5805 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5808 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5810 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5812 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5813 setValue(&I, Value);
5816 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5817 /// If so, return true and lower it, otherwise return false and it will be
5818 /// lowered like a normal call.
5819 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5820 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5821 if (I.getNumArgOperands() != 3)
5824 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5825 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5826 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5827 !I.getType()->isIntegerTy())
5830 const Value *Size = I.getArgOperand(2);
5831 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5832 if (CSize && CSize->getZExtValue() == 0) {
5833 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5834 setValue(&I, DAG.getConstant(0, CallVT));
5838 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5839 std::pair<SDValue, SDValue> Res =
5840 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5841 getValue(LHS), getValue(RHS), getValue(Size),
5842 MachinePointerInfo(LHS),
5843 MachinePointerInfo(RHS));
5844 if (Res.first.getNode()) {
5845 processIntegerCallValue(I, Res.first, true);
5846 PendingLoads.push_back(Res.second);
5850 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5851 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5852 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5853 bool ActuallyDoIt = true;
5856 switch (CSize->getZExtValue()) {
5858 LoadVT = MVT::Other;
5860 ActuallyDoIt = false;
5864 LoadTy = Type::getInt16Ty(CSize->getContext());
5868 LoadTy = Type::getInt32Ty(CSize->getContext());
5872 LoadTy = Type::getInt64Ty(CSize->getContext());
5876 LoadVT = MVT::v4i32;
5877 LoadTy = Type::getInt32Ty(CSize->getContext());
5878 LoadTy = VectorType::get(LoadTy, 4);
5883 // This turns into unaligned loads. We only do this if the target natively
5884 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5885 // we'll only produce a small number of byte loads.
5887 // Require that we can find a legal MVT, and only do this if the target
5888 // supports unaligned loads of that type. Expanding into byte loads would
5890 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5891 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5892 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5893 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5894 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5895 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5896 // TODO: Check alignment of src and dest ptrs.
5897 if (!TLI.isTypeLegal(LoadVT) ||
5898 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5899 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5900 ActuallyDoIt = false;
5904 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5905 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5907 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5909 processIntegerCallValue(I, Res, false);
5918 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5919 /// form. If so, return true and lower it, otherwise return false and it
5920 /// will be lowered like a normal call.
5921 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5922 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5923 if (I.getNumArgOperands() != 3)
5926 const Value *Src = I.getArgOperand(0);
5927 const Value *Char = I.getArgOperand(1);
5928 const Value *Length = I.getArgOperand(2);
5929 if (!Src->getType()->isPointerTy() ||
5930 !Char->getType()->isIntegerTy() ||
5931 !Length->getType()->isIntegerTy() ||
5932 !I.getType()->isPointerTy())
5935 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5936 std::pair<SDValue, SDValue> Res =
5937 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5938 getValue(Src), getValue(Char), getValue(Length),
5939 MachinePointerInfo(Src));
5940 if (Res.first.getNode()) {
5941 setValue(&I, Res.first);
5942 PendingLoads.push_back(Res.second);
5949 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5950 /// optimized form. If so, return true and lower it, otherwise return false
5951 /// and it will be lowered like a normal call.
5952 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5953 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5954 if (I.getNumArgOperands() != 2)
5957 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5958 if (!Arg0->getType()->isPointerTy() ||
5959 !Arg1->getType()->isPointerTy() ||
5960 !I.getType()->isPointerTy())
5963 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5964 std::pair<SDValue, SDValue> Res =
5965 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5966 getValue(Arg0), getValue(Arg1),
5967 MachinePointerInfo(Arg0),
5968 MachinePointerInfo(Arg1), isStpcpy);
5969 if (Res.first.getNode()) {
5970 setValue(&I, Res.first);
5971 DAG.setRoot(Res.second);
5978 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5979 /// If so, return true and lower it, otherwise return false and it will be
5980 /// lowered like a normal call.
5981 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5982 // Verify that the prototype makes sense. int strcmp(void*,void*)
5983 if (I.getNumArgOperands() != 2)
5986 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5987 if (!Arg0->getType()->isPointerTy() ||
5988 !Arg1->getType()->isPointerTy() ||
5989 !I.getType()->isIntegerTy())
5992 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5993 std::pair<SDValue, SDValue> Res =
5994 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5995 getValue(Arg0), getValue(Arg1),
5996 MachinePointerInfo(Arg0),
5997 MachinePointerInfo(Arg1));
5998 if (Res.first.getNode()) {
5999 processIntegerCallValue(I, Res.first, true);
6000 PendingLoads.push_back(Res.second);
6007 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
6008 /// form. If so, return true and lower it, otherwise return false and it
6009 /// will be lowered like a normal call.
6010 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
6011 // Verify that the prototype makes sense. size_t strlen(char *)
6012 if (I.getNumArgOperands() != 1)
6015 const Value *Arg0 = I.getArgOperand(0);
6016 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
6019 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6020 std::pair<SDValue, SDValue> Res =
6021 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
6022 getValue(Arg0), MachinePointerInfo(Arg0));
6023 if (Res.first.getNode()) {
6024 processIntegerCallValue(I, Res.first, false);
6025 PendingLoads.push_back(Res.second);
6032 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
6033 /// form. If so, return true and lower it, otherwise return false and it
6034 /// will be lowered like a normal call.
6035 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
6036 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
6037 if (I.getNumArgOperands() != 2)
6040 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6041 if (!Arg0->getType()->isPointerTy() ||
6042 !Arg1->getType()->isIntegerTy() ||
6043 !I.getType()->isIntegerTy())
6046 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6047 std::pair<SDValue, SDValue> Res =
6048 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
6049 getValue(Arg0), getValue(Arg1),
6050 MachinePointerInfo(Arg0));
6051 if (Res.first.getNode()) {
6052 processIntegerCallValue(I, Res.first, false);
6053 PendingLoads.push_back(Res.second);
6060 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
6061 /// operation (as expected), translate it to an SDNode with the specified opcode
6062 /// and return true.
6063 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
6065 // Sanity check that it really is a unary floating-point call.
6066 if (I.getNumArgOperands() != 1 ||
6067 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
6068 I.getType() != I.getArgOperand(0)->getType() ||
6069 !I.onlyReadsMemory())
6072 SDValue Tmp = getValue(I.getArgOperand(0));
6073 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
6077 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
6078 /// operation (as expected), translate it to an SDNode with the specified opcode
6079 /// and return true.
6080 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
6082 // Sanity check that it really is a binary floating-point call.
6083 if (I.getNumArgOperands() != 2 ||
6084 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
6085 I.getType() != I.getArgOperand(0)->getType() ||
6086 I.getType() != I.getArgOperand(1)->getType() ||
6087 !I.onlyReadsMemory())
6090 SDValue Tmp0 = getValue(I.getArgOperand(0));
6091 SDValue Tmp1 = getValue(I.getArgOperand(1));
6092 EVT VT = Tmp0.getValueType();
6093 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
6097 void SelectionDAGBuilder::visitCall(const CallInst &I) {
6098 // Handle inline assembly differently.
6099 if (isa<InlineAsm>(I.getCalledValue())) {
6104 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
6105 ComputeUsesVAFloatArgument(I, &MMI);
6107 const char *RenameFn = nullptr;
6108 if (Function *F = I.getCalledFunction()) {
6109 if (F->isDeclaration()) {
6110 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
6111 if (unsigned IID = II->getIntrinsicID(F)) {
6112 RenameFn = visitIntrinsicCall(I, IID);
6117 if (unsigned IID = F->getIntrinsicID()) {
6118 RenameFn = visitIntrinsicCall(I, IID);
6124 // Check for well-known libc/libm calls. If the function is internal, it
6125 // can't be a library call.
6127 if (!F->hasLocalLinkage() && F->hasName() &&
6128 LibInfo->getLibFunc(F->getName(), Func) &&
6129 LibInfo->hasOptimizedCodeGen(Func)) {
6132 case LibFunc::copysign:
6133 case LibFunc::copysignf:
6134 case LibFunc::copysignl:
6135 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
6136 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
6137 I.getType() == I.getArgOperand(0)->getType() &&
6138 I.getType() == I.getArgOperand(1)->getType() &&
6139 I.onlyReadsMemory()) {
6140 SDValue LHS = getValue(I.getArgOperand(0));
6141 SDValue RHS = getValue(I.getArgOperand(1));
6142 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
6143 LHS.getValueType(), LHS, RHS));
6148 case LibFunc::fabsf:
6149 case LibFunc::fabsl:
6150 if (visitUnaryFloatCall(I, ISD::FABS))
6154 case LibFunc::fminf:
6155 case LibFunc::fminl:
6156 if (visitBinaryFloatCall(I, ISD::FMINNUM))
6160 case LibFunc::fmaxf:
6161 case LibFunc::fmaxl:
6162 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
6168 if (visitUnaryFloatCall(I, ISD::FSIN))
6174 if (visitUnaryFloatCall(I, ISD::FCOS))
6178 case LibFunc::sqrtf:
6179 case LibFunc::sqrtl:
6180 case LibFunc::sqrt_finite:
6181 case LibFunc::sqrtf_finite:
6182 case LibFunc::sqrtl_finite:
6183 if (visitUnaryFloatCall(I, ISD::FSQRT))
6186 case LibFunc::floor:
6187 case LibFunc::floorf:
6188 case LibFunc::floorl:
6189 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6192 case LibFunc::nearbyint:
6193 case LibFunc::nearbyintf:
6194 case LibFunc::nearbyintl:
6195 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6199 case LibFunc::ceilf:
6200 case LibFunc::ceill:
6201 if (visitUnaryFloatCall(I, ISD::FCEIL))
6205 case LibFunc::rintf:
6206 case LibFunc::rintl:
6207 if (visitUnaryFloatCall(I, ISD::FRINT))
6210 case LibFunc::round:
6211 case LibFunc::roundf:
6212 case LibFunc::roundl:
6213 if (visitUnaryFloatCall(I, ISD::FROUND))
6216 case LibFunc::trunc:
6217 case LibFunc::truncf:
6218 case LibFunc::truncl:
6219 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6223 case LibFunc::log2f:
6224 case LibFunc::log2l:
6225 if (visitUnaryFloatCall(I, ISD::FLOG2))
6229 case LibFunc::exp2f:
6230 case LibFunc::exp2l:
6231 if (visitUnaryFloatCall(I, ISD::FEXP2))
6234 case LibFunc::memcmp:
6235 if (visitMemCmpCall(I))
6238 case LibFunc::memchr:
6239 if (visitMemChrCall(I))
6242 case LibFunc::strcpy:
6243 if (visitStrCpyCall(I, false))
6246 case LibFunc::stpcpy:
6247 if (visitStrCpyCall(I, true))
6250 case LibFunc::strcmp:
6251 if (visitStrCmpCall(I))
6254 case LibFunc::strlen:
6255 if (visitStrLenCall(I))
6258 case LibFunc::strnlen:
6259 if (visitStrNLenCall(I))
6268 Callee = getValue(I.getCalledValue());
6270 Callee = DAG.getExternalSymbol(RenameFn,
6271 DAG.getTargetLoweringInfo().getPointerTy());
6273 // Check if we can potentially perform a tail call. More detailed checking is
6274 // be done within LowerCallTo, after more information about the call is known.
6275 LowerCallTo(&I, Callee, I.isTailCall());
6280 /// AsmOperandInfo - This contains information for each constraint that we are
6282 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6284 /// CallOperand - If this is the result output operand or a clobber
6285 /// this is null, otherwise it is the incoming operand to the CallInst.
6286 /// This gets modified as the asm is processed.
6287 SDValue CallOperand;
6289 /// AssignedRegs - If this is a register or register class operand, this
6290 /// contains the set of register corresponding to the operand.
6291 RegsForValue AssignedRegs;
6293 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6294 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6297 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6298 /// corresponds to. If there is no Value* for this operand, it returns
6300 EVT getCallOperandValEVT(LLVMContext &Context,
6301 const TargetLowering &TLI,
6302 const DataLayout *DL) const {
6303 if (!CallOperandVal) return MVT::Other;
6305 if (isa<BasicBlock>(CallOperandVal))
6306 return TLI.getPointerTy();
6308 llvm::Type *OpTy = CallOperandVal->getType();
6310 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6311 // If this is an indirect operand, the operand is a pointer to the
6314 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6316 report_fatal_error("Indirect operand for inline asm not a pointer!");
6317 OpTy = PtrTy->getElementType();
6320 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6321 if (StructType *STy = dyn_cast<StructType>(OpTy))
6322 if (STy->getNumElements() == 1)
6323 OpTy = STy->getElementType(0);
6325 // If OpTy is not a single value, it may be a struct/union that we
6326 // can tile with integers.
6327 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6328 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6337 OpTy = IntegerType::get(Context, BitSize);
6342 return TLI.getValueType(OpTy, true);
6346 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6348 } // end anonymous namespace
6350 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6351 /// specified operand. We prefer to assign virtual registers, to allow the
6352 /// register allocator to handle the assignment process. However, if the asm
6353 /// uses features that we can't model on machineinstrs, we have SDISel do the
6354 /// allocation. This produces generally horrible, but correct, code.
6356 /// OpInfo describes the operand.
6358 static void GetRegistersForValue(SelectionDAG &DAG,
6359 const TargetLowering &TLI,
6361 SDISelAsmOperandInfo &OpInfo) {
6362 LLVMContext &Context = *DAG.getContext();
6364 MachineFunction &MF = DAG.getMachineFunction();
6365 SmallVector<unsigned, 4> Regs;
6367 // If this is a constraint for a single physreg, or a constraint for a
6368 // register class, find it.
6369 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6370 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6371 OpInfo.ConstraintVT);
6373 unsigned NumRegs = 1;
6374 if (OpInfo.ConstraintVT != MVT::Other) {
6375 // If this is a FP input in an integer register (or visa versa) insert a bit
6376 // cast of the input value. More generally, handle any case where the input
6377 // value disagrees with the register class we plan to stick this in.
6378 if (OpInfo.Type == InlineAsm::isInput &&
6379 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6380 // Try to convert to the first EVT that the reg class contains. If the
6381 // types are identical size, use a bitcast to convert (e.g. two differing
6383 MVT RegVT = *PhysReg.second->vt_begin();
6384 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6385 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6386 RegVT, OpInfo.CallOperand);
6387 OpInfo.ConstraintVT = RegVT;
6388 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6389 // If the input is a FP value and we want it in FP registers, do a
6390 // bitcast to the corresponding integer type. This turns an f64 value
6391 // into i64, which can be passed with two i32 values on a 32-bit
6393 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6394 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6395 RegVT, OpInfo.CallOperand);
6396 OpInfo.ConstraintVT = RegVT;
6400 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6404 EVT ValueVT = OpInfo.ConstraintVT;
6406 // If this is a constraint for a specific physical register, like {r17},
6408 if (unsigned AssignedReg = PhysReg.first) {
6409 const TargetRegisterClass *RC = PhysReg.second;
6410 if (OpInfo.ConstraintVT == MVT::Other)
6411 ValueVT = *RC->vt_begin();
6413 // Get the actual register value type. This is important, because the user
6414 // may have asked for (e.g.) the AX register in i32 type. We need to
6415 // remember that AX is actually i16 to get the right extension.
6416 RegVT = *RC->vt_begin();
6418 // This is a explicit reference to a physical register.
6419 Regs.push_back(AssignedReg);
6421 // If this is an expanded reference, add the rest of the regs to Regs.
6423 TargetRegisterClass::iterator I = RC->begin();
6424 for (; *I != AssignedReg; ++I)
6425 assert(I != RC->end() && "Didn't find reg!");
6427 // Already added the first reg.
6429 for (; NumRegs; --NumRegs, ++I) {
6430 assert(I != RC->end() && "Ran out of registers to allocate!");
6435 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6439 // Otherwise, if this was a reference to an LLVM register class, create vregs
6440 // for this reference.
6441 if (const TargetRegisterClass *RC = PhysReg.second) {
6442 RegVT = *RC->vt_begin();
6443 if (OpInfo.ConstraintVT == MVT::Other)
6446 // Create the appropriate number of virtual registers.
6447 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6448 for (; NumRegs; --NumRegs)
6449 Regs.push_back(RegInfo.createVirtualRegister(RC));
6451 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6455 // Otherwise, we couldn't allocate enough registers for this.
6458 /// visitInlineAsm - Handle a call to an InlineAsm object.
6460 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6461 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6463 /// ConstraintOperands - Information about all of the constraints.
6464 SDISelAsmOperandInfoVector ConstraintOperands;
6466 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6467 TargetLowering::AsmOperandInfoVector
6468 TargetConstraints = TLI.ParseConstraints(CS);
6470 bool hasMemory = false;
6472 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6473 unsigned ResNo = 0; // ResNo - The result number of the next output.
6474 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6475 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6476 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6478 MVT OpVT = MVT::Other;
6480 // Compute the value type for each operand.
6481 switch (OpInfo.Type) {
6482 case InlineAsm::isOutput:
6483 // Indirect outputs just consume an argument.
6484 if (OpInfo.isIndirect) {
6485 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6489 // The return value of the call is this value. As such, there is no
6490 // corresponding argument.
6491 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6492 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6493 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
6495 assert(ResNo == 0 && "Asm only has one result!");
6496 OpVT = TLI.getSimpleValueType(CS.getType());
6500 case InlineAsm::isInput:
6501 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6503 case InlineAsm::isClobber:
6508 // If this is an input or an indirect output, process the call argument.
6509 // BasicBlocks are labels, currently appearing only in asm's.
6510 if (OpInfo.CallOperandVal) {
6511 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6512 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6514 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6518 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
6521 OpInfo.ConstraintVT = OpVT;
6523 // Indirect operand accesses access memory.
6524 if (OpInfo.isIndirect)
6527 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6528 TargetLowering::ConstraintType
6529 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6530 if (CType == TargetLowering::C_Memory) {
6538 SDValue Chain, Flag;
6540 // We won't need to flush pending loads if this asm doesn't touch
6541 // memory and is nonvolatile.
6542 if (hasMemory || IA->hasSideEffects())
6545 Chain = DAG.getRoot();
6547 // Second pass over the constraints: compute which constraint option to use
6548 // and assign registers to constraints that want a specific physreg.
6549 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6550 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6552 // If this is an output operand with a matching input operand, look up the
6553 // matching input. If their types mismatch, e.g. one is an integer, the
6554 // other is floating point, or their sizes are different, flag it as an
6556 if (OpInfo.hasMatchingInput()) {
6557 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6559 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6560 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6561 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6562 OpInfo.ConstraintVT);
6563 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6564 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
6565 Input.ConstraintVT);
6566 if ((OpInfo.ConstraintVT.isInteger() !=
6567 Input.ConstraintVT.isInteger()) ||
6568 (MatchRC.second != InputRC.second)) {
6569 report_fatal_error("Unsupported asm: input constraint"
6570 " with a matching output constraint of"
6571 " incompatible type!");
6573 Input.ConstraintVT = OpInfo.ConstraintVT;
6577 // Compute the constraint code and ConstraintType to use.
6578 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6580 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6581 OpInfo.Type == InlineAsm::isClobber)
6584 // If this is a memory input, and if the operand is not indirect, do what we
6585 // need to to provide an address for the memory input.
6586 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6587 !OpInfo.isIndirect) {
6588 assert((OpInfo.isMultipleAlternative ||
6589 (OpInfo.Type == InlineAsm::isInput)) &&
6590 "Can only indirectify direct input operands!");
6592 // Memory operands really want the address of the value. If we don't have
6593 // an indirect input, put it in the constpool if we can, otherwise spill
6594 // it to a stack slot.
6595 // TODO: This isn't quite right. We need to handle these according to
6596 // the addressing mode that the constraint wants. Also, this may take
6597 // an additional register for the computation and we don't want that
6600 // If the operand is a float, integer, or vector constant, spill to a
6601 // constant pool entry to get its address.
6602 const Value *OpVal = OpInfo.CallOperandVal;
6603 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6604 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6605 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6606 TLI.getPointerTy());
6608 // Otherwise, create a stack slot and emit a store to it before the
6610 Type *Ty = OpVal->getType();
6611 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
6612 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
6613 MachineFunction &MF = DAG.getMachineFunction();
6614 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6615 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6616 Chain = DAG.getStore(Chain, getCurSDLoc(),
6617 OpInfo.CallOperand, StackSlot,
6618 MachinePointerInfo::getFixedStack(SSFI),
6620 OpInfo.CallOperand = StackSlot;
6623 // There is no longer a Value* corresponding to this operand.
6624 OpInfo.CallOperandVal = nullptr;
6626 // It is now an indirect operand.
6627 OpInfo.isIndirect = true;
6630 // If this constraint is for a specific register, allocate it before
6632 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6633 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6636 // Second pass - Loop over all of the operands, assigning virtual or physregs
6637 // to register class operands.
6638 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6639 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6641 // C_Register operands have already been allocated, Other/Memory don't need
6643 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6644 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6647 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6648 std::vector<SDValue> AsmNodeOperands;
6649 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6650 AsmNodeOperands.push_back(
6651 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6652 TLI.getPointerTy()));
6654 // If we have a !srcloc metadata node associated with it, we want to attach
6655 // this to the ultimately generated inline asm machineinstr. To do this, we
6656 // pass in the third operand as this (potentially null) inline asm MDNode.
6657 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6658 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6660 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6661 // bits as operand 3.
6662 unsigned ExtraInfo = 0;
6663 if (IA->hasSideEffects())
6664 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6665 if (IA->isAlignStack())
6666 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6667 // Set the asm dialect.
6668 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6670 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6671 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6672 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6674 // Compute the constraint code and ConstraintType to use.
6675 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6677 // Ideally, we would only check against memory constraints. However, the
6678 // meaning of an other constraint can be target-specific and we can't easily
6679 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6680 // for other constriants as well.
6681 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6682 OpInfo.ConstraintType == TargetLowering::C_Other) {
6683 if (OpInfo.Type == InlineAsm::isInput)
6684 ExtraInfo |= InlineAsm::Extra_MayLoad;
6685 else if (OpInfo.Type == InlineAsm::isOutput)
6686 ExtraInfo |= InlineAsm::Extra_MayStore;
6687 else if (OpInfo.Type == InlineAsm::isClobber)
6688 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6692 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6693 TLI.getPointerTy()));
6695 // Loop over all of the inputs, copying the operand values into the
6696 // appropriate registers and processing the output regs.
6697 RegsForValue RetValRegs;
6699 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6700 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6702 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6703 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6705 switch (OpInfo.Type) {
6706 case InlineAsm::isOutput: {
6707 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6708 OpInfo.ConstraintType != TargetLowering::C_Register) {
6709 // Memory output, or 'other' output (e.g. 'X' constraint).
6710 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6712 // Add information to the INLINEASM node to know about this output.
6713 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6714 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6715 TLI.getPointerTy()));
6716 AsmNodeOperands.push_back(OpInfo.CallOperand);
6720 // Otherwise, this is a register or register class output.
6722 // Copy the output from the appropriate register. Find a register that
6724 if (OpInfo.AssignedRegs.Regs.empty()) {
6725 LLVMContext &Ctx = *DAG.getContext();
6726 Ctx.emitError(CS.getInstruction(),
6727 "couldn't allocate output register for constraint '" +
6728 Twine(OpInfo.ConstraintCode) + "'");
6732 // If this is an indirect operand, store through the pointer after the
6734 if (OpInfo.isIndirect) {
6735 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6736 OpInfo.CallOperandVal));
6738 // This is the result value of the call.
6739 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6740 // Concatenate this output onto the outputs list.
6741 RetValRegs.append(OpInfo.AssignedRegs);
6744 // Add information to the INLINEASM node to know that this register is
6747 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6748 ? InlineAsm::Kind_RegDefEarlyClobber
6749 : InlineAsm::Kind_RegDef,
6750 false, 0, DAG, AsmNodeOperands);
6753 case InlineAsm::isInput: {
6754 SDValue InOperandVal = OpInfo.CallOperand;
6756 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6757 // If this is required to match an output register we have already set,
6758 // just use its register.
6759 unsigned OperandNo = OpInfo.getMatchedOperand();
6761 // Scan until we find the definition we already emitted of this operand.
6762 // When we find it, create a RegsForValue operand.
6763 unsigned CurOp = InlineAsm::Op_FirstOperand;
6764 for (; OperandNo; --OperandNo) {
6765 // Advance to the next operand.
6767 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6768 assert((InlineAsm::isRegDefKind(OpFlag) ||
6769 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6770 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6771 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6775 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6776 if (InlineAsm::isRegDefKind(OpFlag) ||
6777 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6778 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6779 if (OpInfo.isIndirect) {
6780 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6781 LLVMContext &Ctx = *DAG.getContext();
6782 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6783 " don't know how to handle tied "
6784 "indirect register inputs");
6788 RegsForValue MatchedRegs;
6789 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6790 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6791 MatchedRegs.RegVTs.push_back(RegVT);
6792 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6793 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6795 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6796 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6798 LLVMContext &Ctx = *DAG.getContext();
6799 Ctx.emitError(CS.getInstruction(),
6800 "inline asm error: This value"
6801 " type register class is not natively supported!");
6805 // Use the produced MatchedRegs object to
6806 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6807 Chain, &Flag, CS.getInstruction());
6808 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6809 true, OpInfo.getMatchedOperand(),
6810 DAG, AsmNodeOperands);
6814 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6815 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6816 "Unexpected number of operands");
6817 // Add information to the INLINEASM node to know about this input.
6818 // See InlineAsm.h isUseOperandTiedToDef.
6819 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6820 OpInfo.getMatchedOperand());
6821 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6822 TLI.getPointerTy()));
6823 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6827 // Treat indirect 'X' constraint as memory.
6828 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6830 OpInfo.ConstraintType = TargetLowering::C_Memory;
6832 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6833 std::vector<SDValue> Ops;
6834 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6837 LLVMContext &Ctx = *DAG.getContext();
6838 Ctx.emitError(CS.getInstruction(),
6839 "invalid operand for inline asm constraint '" +
6840 Twine(OpInfo.ConstraintCode) + "'");
6844 // Add information to the INLINEASM node to know about this input.
6845 unsigned ResOpType =
6846 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6847 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6848 TLI.getPointerTy()));
6849 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6853 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6854 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6855 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6856 "Memory operands expect pointer values");
6858 // Add information to the INLINEASM node to know about this input.
6859 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6860 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6861 TLI.getPointerTy()));
6862 AsmNodeOperands.push_back(InOperandVal);
6866 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6867 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6868 "Unknown constraint type!");
6870 // TODO: Support this.
6871 if (OpInfo.isIndirect) {
6872 LLVMContext &Ctx = *DAG.getContext();
6873 Ctx.emitError(CS.getInstruction(),
6874 "Don't know how to handle indirect register inputs yet "
6875 "for constraint '" +
6876 Twine(OpInfo.ConstraintCode) + "'");
6880 // Copy the input into the appropriate registers.
6881 if (OpInfo.AssignedRegs.Regs.empty()) {
6882 LLVMContext &Ctx = *DAG.getContext();
6883 Ctx.emitError(CS.getInstruction(),
6884 "couldn't allocate input reg for constraint '" +
6885 Twine(OpInfo.ConstraintCode) + "'");
6889 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6890 Chain, &Flag, CS.getInstruction());
6892 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6893 DAG, AsmNodeOperands);
6896 case InlineAsm::isClobber: {
6897 // Add the clobbered value to the operand list, so that the register
6898 // allocator is aware that the physreg got clobbered.
6899 if (!OpInfo.AssignedRegs.Regs.empty())
6900 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6908 // Finish up input operands. Set the input chain and add the flag last.
6909 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6910 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6912 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6913 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6914 Flag = Chain.getValue(1);
6916 // If this asm returns a register value, copy the result from that register
6917 // and set it as the value of the call.
6918 if (!RetValRegs.Regs.empty()) {
6919 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6920 Chain, &Flag, CS.getInstruction());
6922 // FIXME: Why don't we do this for inline asms with MRVs?
6923 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6924 EVT ResultType = TLI.getValueType(CS.getType());
6926 // If any of the results of the inline asm is a vector, it may have the
6927 // wrong width/num elts. This can happen for register classes that can
6928 // contain multiple different value types. The preg or vreg allocated may
6929 // not have the same VT as was expected. Convert it to the right type
6930 // with bit_convert.
6931 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6932 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6935 } else if (ResultType != Val.getValueType() &&
6936 ResultType.isInteger() && Val.getValueType().isInteger()) {
6937 // If a result value was tied to an input value, the computed result may
6938 // have a wider width than the expected result. Extract the relevant
6940 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6943 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6946 setValue(CS.getInstruction(), Val);
6947 // Don't need to use this as a chain in this case.
6948 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6952 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6954 // Process indirect outputs, first output all of the flagged copies out of
6956 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6957 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6958 const Value *Ptr = IndirectStoresToEmit[i].second;
6959 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6961 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6964 // Emit the non-flagged stores from the physregs.
6965 SmallVector<SDValue, 8> OutChains;
6966 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6967 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6968 StoresToEmit[i].first,
6969 getValue(StoresToEmit[i].second),
6970 MachinePointerInfo(StoresToEmit[i].second),
6972 OutChains.push_back(Val);
6975 if (!OutChains.empty())
6976 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6981 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6982 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6983 MVT::Other, getRoot(),
6984 getValue(I.getArgOperand(0)),
6985 DAG.getSrcValue(I.getArgOperand(0))));
6988 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6989 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6990 const DataLayout &DL = *TLI.getDataLayout();
6991 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6992 getRoot(), getValue(I.getOperand(0)),
6993 DAG.getSrcValue(I.getOperand(0)),
6994 DL.getABITypeAlignment(I.getType()));
6996 DAG.setRoot(V.getValue(1));
6999 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
7000 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
7001 MVT::Other, getRoot(),
7002 getValue(I.getArgOperand(0)),
7003 DAG.getSrcValue(I.getArgOperand(0))));
7006 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
7007 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
7008 MVT::Other, getRoot(),
7009 getValue(I.getArgOperand(0)),
7010 getValue(I.getArgOperand(1)),
7011 DAG.getSrcValue(I.getArgOperand(0)),
7012 DAG.getSrcValue(I.getArgOperand(1))));
7015 /// \brief Lower an argument list according to the target calling convention.
7017 /// \return A tuple of <return-value, token-chain>
7019 /// This is a helper for lowering intrinsics that follow a target calling
7020 /// convention or require stack pointer adjustment. Only a subset of the
7021 /// intrinsic's operands need to participate in the calling convention.
7022 std::pair<SDValue, SDValue>
7023 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
7024 unsigned NumArgs, SDValue Callee,
7026 MachineBasicBlock *LandingPad,
7027 bool IsPatchPoint) {
7028 TargetLowering::ArgListTy Args;
7029 Args.reserve(NumArgs);
7031 // Populate the argument list.
7032 // Attributes for args start at offset 1, after the return attribute.
7033 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
7034 ArgI != ArgE; ++ArgI) {
7035 const Value *V = CS->getOperand(ArgI);
7037 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
7039 TargetLowering::ArgListEntry Entry;
7040 Entry.Node = getValue(V);
7041 Entry.Ty = V->getType();
7042 Entry.setAttributes(&CS, AttrI);
7043 Args.push_back(Entry);
7046 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
7047 TargetLowering::CallLoweringInfo CLI(DAG);
7048 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
7049 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
7050 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
7052 return lowerInvokable(CLI, LandingPad);
7055 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
7056 /// or patchpoint target node's operand list.
7058 /// Constants are converted to TargetConstants purely as an optimization to
7059 /// avoid constant materialization and register allocation.
7061 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
7062 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
7063 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
7064 /// address materialization and register allocation, but may also be required
7065 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
7066 /// alloca in the entry block, then the runtime may assume that the alloca's
7067 /// StackMap location can be read immediately after compilation and that the
7068 /// location is valid at any point during execution (this is similar to the
7069 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
7070 /// only available in a register, then the runtime would need to trap when
7071 /// execution reaches the StackMap in order to read the alloca's location.
7072 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
7073 SmallVectorImpl<SDValue> &Ops,
7074 SelectionDAGBuilder &Builder) {
7075 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
7076 SDValue OpVal = Builder.getValue(CS.getArgument(i));
7077 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
7079 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
7081 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
7082 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
7083 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
7085 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
7087 Ops.push_back(OpVal);
7091 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
7092 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
7093 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
7094 // [live variables...])
7096 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
7098 SDValue Chain, InFlag, Callee, NullPtr;
7099 SmallVector<SDValue, 32> Ops;
7101 SDLoc DL = getCurSDLoc();
7102 Callee = getValue(CI.getCalledValue());
7103 NullPtr = DAG.getIntPtrConstant(0, true);
7105 // The stackmap intrinsic only records the live variables (the arguemnts
7106 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
7107 // intrinsic, this won't be lowered to a function call. This means we don't
7108 // have to worry about calling conventions and target specific lowering code.
7109 // Instead we perform the call lowering right here.
7111 // chain, flag = CALLSEQ_START(chain, 0)
7112 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
7113 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
7115 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
7116 InFlag = Chain.getValue(1);
7118 // Add the <id> and <numBytes> constants.
7119 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7120 Ops.push_back(DAG.getTargetConstant(
7121 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7122 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7123 Ops.push_back(DAG.getTargetConstant(
7124 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7126 // Push live variables for the stack map.
7127 addStackMapLiveVars(&CI, 2, Ops, *this);
7129 // We are not pushing any register mask info here on the operands list,
7130 // because the stackmap doesn't clobber anything.
7132 // Push the chain and the glue flag.
7133 Ops.push_back(Chain);
7134 Ops.push_back(InFlag);
7136 // Create the STACKMAP node.
7137 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7138 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
7139 Chain = SDValue(SM, 0);
7140 InFlag = Chain.getValue(1);
7142 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
7144 // Stackmaps don't generate values, so nothing goes into the NodeMap.
7146 // Set the root to the target-lowered call chain.
7149 // Inform the Frame Information that we have a stackmap in this function.
7150 FuncInfo.MF->getFrameInfo()->setHasStackMap();
7153 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
7154 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
7155 MachineBasicBlock *LandingPad) {
7156 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
7161 // [live variables...])
7163 CallingConv::ID CC = CS.getCallingConv();
7164 bool IsAnyRegCC = CC == CallingConv::AnyReg;
7165 bool HasDef = !CS->getType()->isVoidTy();
7166 SDValue Callee = getValue(CS->getOperand(2)); // <target>
7168 // Get the real number of arguments participating in the call <numArgs>
7169 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
7170 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
7172 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
7173 // Intrinsics include all meta-operands up to but not including CC.
7174 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7175 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
7176 "Not enough arguments provided to the patchpoint intrinsic");
7178 // For AnyRegCC the arguments are lowered later on manually.
7179 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
7180 std::pair<SDValue, SDValue> Result =
7181 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
7184 SDNode *CallEnd = Result.second.getNode();
7185 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7186 CallEnd = CallEnd->getOperand(0).getNode();
7188 /// Get a call instruction from the call sequence chain.
7189 /// Tail calls are not allowed.
7190 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7191 "Expected a callseq node.");
7192 SDNode *Call = CallEnd->getOperand(0).getNode();
7193 bool HasGlue = Call->getGluedNode();
7195 // Replace the target specific call node with the patchable intrinsic.
7196 SmallVector<SDValue, 8> Ops;
7198 // Add the <id> and <numBytes> constants.
7199 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
7200 Ops.push_back(DAG.getTargetConstant(
7201 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7202 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
7203 Ops.push_back(DAG.getTargetConstant(
7204 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7206 // Assume that the Callee is a constant address.
7207 // FIXME: handle function symbols in the future.
7209 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7210 /*isTarget=*/true));
7212 // Adjust <numArgs> to account for any arguments that have been passed on the
7214 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7215 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
7216 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
7217 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7219 // Add the calling convention
7220 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7222 // Add the arguments we omitted previously. The register allocator should
7223 // place these in any free register.
7225 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7226 Ops.push_back(getValue(CS.getArgument(i)));
7228 // Push the arguments from the call instruction up to the register mask.
7229 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
7230 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7233 // Push live variables for the stack map.
7234 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this);
7236 // Push the register mask info.
7238 Ops.push_back(*(Call->op_end()-2));
7240 Ops.push_back(*(Call->op_end()-1));
7242 // Push the chain (this is originally the first operand of the call, but
7243 // becomes now the last or second to last operand).
7244 Ops.push_back(*(Call->op_begin()));
7246 // Push the glue flag (last operand).
7248 Ops.push_back(*(Call->op_end()-1));
7251 if (IsAnyRegCC && HasDef) {
7252 // Create the return types based on the intrinsic definition
7253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7254 SmallVector<EVT, 3> ValueVTs;
7255 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
7256 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7258 // There is always a chain and a glue type at the end
7259 ValueVTs.push_back(MVT::Other);
7260 ValueVTs.push_back(MVT::Glue);
7261 NodeTys = DAG.getVTList(ValueVTs);
7263 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7265 // Replace the target specific call node with a PATCHPOINT node.
7266 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7267 getCurSDLoc(), NodeTys, Ops);
7269 // Update the NodeMap.
7272 setValue(CS.getInstruction(), SDValue(MN, 0));
7274 setValue(CS.getInstruction(), Result.first);
7277 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7278 // call sequence. Furthermore the location of the chain and glue can change
7279 // when the AnyReg calling convention is used and the intrinsic returns a
7281 if (IsAnyRegCC && HasDef) {
7282 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7283 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7284 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7286 DAG.ReplaceAllUsesWith(Call, MN);
7287 DAG.DeleteNode(Call);
7289 // Inform the Frame Information that we have a patchpoint in this function.
7290 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7293 /// Returns an AttributeSet representing the attributes applied to the return
7294 /// value of the given call.
7295 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7296 SmallVector<Attribute::AttrKind, 2> Attrs;
7298 Attrs.push_back(Attribute::SExt);
7300 Attrs.push_back(Attribute::ZExt);
7302 Attrs.push_back(Attribute::InReg);
7304 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7308 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7309 /// implementation, which just calls LowerCall.
7310 /// FIXME: When all targets are
7311 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7312 std::pair<SDValue, SDValue>
7313 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7314 // Handle the incoming return values from the call.
7316 Type *OrigRetTy = CLI.RetTy;
7317 SmallVector<EVT, 4> RetTys;
7318 SmallVector<uint64_t, 4> Offsets;
7319 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7321 SmallVector<ISD::OutputArg, 4> Outs;
7322 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7324 bool CanLowerReturn =
7325 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7326 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7328 SDValue DemoteStackSlot;
7329 int DemoteStackIdx = -100;
7330 if (!CanLowerReturn) {
7331 // FIXME: equivalent assert?
7332 // assert(!CS.hasInAllocaArgument() &&
7333 // "sret demotion is incompatible with inalloca");
7334 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7335 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7336 MachineFunction &MF = CLI.DAG.getMachineFunction();
7337 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7338 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7340 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7342 Entry.Node = DemoteStackSlot;
7343 Entry.Ty = StackSlotPtrType;
7344 Entry.isSExt = false;
7345 Entry.isZExt = false;
7346 Entry.isInReg = false;
7347 Entry.isSRet = true;
7348 Entry.isNest = false;
7349 Entry.isByVal = false;
7350 Entry.isReturned = false;
7351 Entry.Alignment = Align;
7352 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7353 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7355 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7357 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7358 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7359 for (unsigned i = 0; i != NumRegs; ++i) {
7360 ISD::InputArg MyFlags;
7361 MyFlags.VT = RegisterVT;
7363 MyFlags.Used = CLI.IsReturnValueUsed;
7365 MyFlags.Flags.setSExt();
7367 MyFlags.Flags.setZExt();
7369 MyFlags.Flags.setInReg();
7370 CLI.Ins.push_back(MyFlags);
7375 // Handle all of the outgoing arguments.
7377 CLI.OutVals.clear();
7378 ArgListTy &Args = CLI.getArgs();
7379 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7380 SmallVector<EVT, 4> ValueVTs;
7381 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7382 Type *FinalType = Args[i].Ty;
7383 if (Args[i].isByVal)
7384 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7385 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7386 FinalType, CLI.CallConv, CLI.IsVarArg);
7387 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7389 EVT VT = ValueVTs[Value];
7390 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7391 SDValue Op = SDValue(Args[i].Node.getNode(),
7392 Args[i].Node.getResNo() + Value);
7393 ISD::ArgFlagsTy Flags;
7394 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7400 if (Args[i].isInReg)
7404 if (Args[i].isByVal)
7406 if (Args[i].isInAlloca) {
7407 Flags.setInAlloca();
7408 // Set the byval flag for CCAssignFn callbacks that don't know about
7409 // inalloca. This way we can know how many bytes we should've allocated
7410 // and how many bytes a callee cleanup function will pop. If we port
7411 // inalloca to more targets, we'll have to add custom inalloca handling
7412 // in the various CC lowering callbacks.
7415 if (Args[i].isByVal || Args[i].isInAlloca) {
7416 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7417 Type *ElementTy = Ty->getElementType();
7418 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7419 // For ByVal, alignment should come from FE. BE will guess if this
7420 // info is not there but there are cases it cannot get right.
7421 unsigned FrameAlign;
7422 if (Args[i].Alignment)
7423 FrameAlign = Args[i].Alignment;
7425 FrameAlign = getByValTypeAlignment(ElementTy);
7426 Flags.setByValAlign(FrameAlign);
7430 if (NeedsRegBlock) {
7431 Flags.setInConsecutiveRegs();
7432 if (Value == NumValues - 1)
7433 Flags.setInConsecutiveRegsLast();
7435 Flags.setOrigAlign(OriginalAlignment);
7437 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7438 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7439 SmallVector<SDValue, 4> Parts(NumParts);
7440 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7443 ExtendKind = ISD::SIGN_EXTEND;
7444 else if (Args[i].isZExt)
7445 ExtendKind = ISD::ZERO_EXTEND;
7447 // Conservatively only handle 'returned' on non-vectors for now
7448 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7449 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7450 "unexpected use of 'returned'");
7451 // Before passing 'returned' to the target lowering code, ensure that
7452 // either the register MVT and the actual EVT are the same size or that
7453 // the return value and argument are extended in the same way; in these
7454 // cases it's safe to pass the argument register value unchanged as the
7455 // return register value (although it's at the target's option whether
7457 // TODO: allow code generation to take advantage of partially preserved
7458 // registers rather than clobbering the entire register when the
7459 // parameter extension method is not compatible with the return
7461 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7462 (ExtendKind != ISD::ANY_EXTEND &&
7463 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7464 Flags.setReturned();
7467 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7468 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7470 for (unsigned j = 0; j != NumParts; ++j) {
7471 // if it isn't first piece, alignment must be 1
7472 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7473 i < CLI.NumFixedArgs,
7474 i, j*Parts[j].getValueType().getStoreSize());
7475 if (NumParts > 1 && j == 0)
7476 MyFlags.Flags.setSplit();
7478 MyFlags.Flags.setOrigAlign(1);
7480 CLI.Outs.push_back(MyFlags);
7481 CLI.OutVals.push_back(Parts[j]);
7486 SmallVector<SDValue, 4> InVals;
7487 CLI.Chain = LowerCall(CLI, InVals);
7489 // Verify that the target's LowerCall behaved as expected.
7490 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7491 "LowerCall didn't return a valid chain!");
7492 assert((!CLI.IsTailCall || InVals.empty()) &&
7493 "LowerCall emitted a return value for a tail call!");
7494 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7495 "LowerCall didn't emit the correct number of values!");
7497 // For a tail call, the return value is merely live-out and there aren't
7498 // any nodes in the DAG representing it. Return a special value to
7499 // indicate that a tail call has been emitted and no more Instructions
7500 // should be processed in the current block.
7501 if (CLI.IsTailCall) {
7502 CLI.DAG.setRoot(CLI.Chain);
7503 return std::make_pair(SDValue(), SDValue());
7506 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7507 assert(InVals[i].getNode() &&
7508 "LowerCall emitted a null value!");
7509 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7510 "LowerCall emitted a value with the wrong type!");
7513 SmallVector<SDValue, 4> ReturnValues;
7514 if (!CanLowerReturn) {
7515 // The instruction result is the result of loading from the
7516 // hidden sret parameter.
7517 SmallVector<EVT, 1> PVTs;
7518 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7520 ComputeValueVTs(*this, PtrRetTy, PVTs);
7521 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7522 EVT PtrVT = PVTs[0];
7524 unsigned NumValues = RetTys.size();
7525 ReturnValues.resize(NumValues);
7526 SmallVector<SDValue, 4> Chains(NumValues);
7528 for (unsigned i = 0; i < NumValues; ++i) {
7529 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7530 CLI.DAG.getConstant(Offsets[i], PtrVT));
7531 SDValue L = CLI.DAG.getLoad(
7532 RetTys[i], CLI.DL, CLI.Chain, Add,
7533 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7535 ReturnValues[i] = L;
7536 Chains[i] = L.getValue(1);
7539 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7541 // Collect the legal value parts into potentially illegal values
7542 // that correspond to the original function's return values.
7543 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7545 AssertOp = ISD::AssertSext;
7546 else if (CLI.RetZExt)
7547 AssertOp = ISD::AssertZext;
7548 unsigned CurReg = 0;
7549 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7551 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7552 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7554 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7555 NumRegs, RegisterVT, VT, nullptr,
7560 // For a function returning void, there is no return value. We can't create
7561 // such a node, so we just return a null return value in that case. In
7562 // that case, nothing will actually look at the value.
7563 if (ReturnValues.empty())
7564 return std::make_pair(SDValue(), CLI.Chain);
7567 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7568 CLI.DAG.getVTList(RetTys), ReturnValues);
7569 return std::make_pair(Res, CLI.Chain);
7572 void TargetLowering::LowerOperationWrapper(SDNode *N,
7573 SmallVectorImpl<SDValue> &Results,
7574 SelectionDAG &DAG) const {
7575 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7577 Results.push_back(Res);
7580 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7581 llvm_unreachable("LowerOperation not implemented for this target!");
7585 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7586 SDValue Op = getNonRegisterValue(V);
7587 assert((Op.getOpcode() != ISD::CopyFromReg ||
7588 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7589 "Copy from a reg to the same reg!");
7590 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7592 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7593 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7594 SDValue Chain = DAG.getEntryNode();
7596 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7597 FuncInfo.PreferredExtendType.end())
7599 : FuncInfo.PreferredExtendType[V];
7600 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7601 PendingExports.push_back(Chain);
7604 #include "llvm/CodeGen/SelectionDAGISel.h"
7606 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7607 /// entry block, return true. This includes arguments used by switches, since
7608 /// the switch may expand into multiple basic blocks.
7609 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7610 // With FastISel active, we may be splitting blocks, so force creation
7611 // of virtual registers for all non-dead arguments.
7613 return A->use_empty();
7615 const BasicBlock *Entry = A->getParent()->begin();
7616 for (const User *U : A->users())
7617 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7618 return false; // Use not in entry block.
7623 void SelectionDAGISel::LowerArguments(const Function &F) {
7624 SelectionDAG &DAG = SDB->DAG;
7625 SDLoc dl = SDB->getCurSDLoc();
7626 const DataLayout *DL = TLI->getDataLayout();
7627 SmallVector<ISD::InputArg, 16> Ins;
7629 if (!FuncInfo->CanLowerReturn) {
7630 // Put in an sret pointer parameter before all the other parameters.
7631 SmallVector<EVT, 1> ValueVTs;
7632 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7634 // NOTE: Assuming that a pointer will never break down to more than one VT
7636 ISD::ArgFlagsTy Flags;
7638 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7639 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7640 Ins.push_back(RetArg);
7643 // Set up the incoming argument description vector.
7645 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7646 I != E; ++I, ++Idx) {
7647 SmallVector<EVT, 4> ValueVTs;
7648 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7649 bool isArgValueUsed = !I->use_empty();
7650 unsigned PartBase = 0;
7651 Type *FinalType = I->getType();
7652 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7653 FinalType = cast<PointerType>(FinalType)->getElementType();
7654 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7655 FinalType, F.getCallingConv(), F.isVarArg());
7656 for (unsigned Value = 0, NumValues = ValueVTs.size();
7657 Value != NumValues; ++Value) {
7658 EVT VT = ValueVTs[Value];
7659 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7660 ISD::ArgFlagsTy Flags;
7661 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7663 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7665 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7667 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7669 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7671 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7673 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7674 Flags.setInAlloca();
7675 // Set the byval flag for CCAssignFn callbacks that don't know about
7676 // inalloca. This way we can know how many bytes we should've allocated
7677 // and how many bytes a callee cleanup function will pop. If we port
7678 // inalloca to more targets, we'll have to add custom inalloca handling
7679 // in the various CC lowering callbacks.
7682 if (Flags.isByVal() || Flags.isInAlloca()) {
7683 PointerType *Ty = cast<PointerType>(I->getType());
7684 Type *ElementTy = Ty->getElementType();
7685 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7686 // For ByVal, alignment should be passed from FE. BE will guess if
7687 // this info is not there but there are cases it cannot get right.
7688 unsigned FrameAlign;
7689 if (F.getParamAlignment(Idx))
7690 FrameAlign = F.getParamAlignment(Idx);
7692 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7693 Flags.setByValAlign(FrameAlign);
7695 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7697 if (NeedsRegBlock) {
7698 Flags.setInConsecutiveRegs();
7699 if (Value == NumValues - 1)
7700 Flags.setInConsecutiveRegsLast();
7702 Flags.setOrigAlign(OriginalAlignment);
7704 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7705 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7706 for (unsigned i = 0; i != NumRegs; ++i) {
7707 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7708 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7709 if (NumRegs > 1 && i == 0)
7710 MyFlags.Flags.setSplit();
7711 // if it isn't first piece, alignment must be 1
7713 MyFlags.Flags.setOrigAlign(1);
7714 Ins.push_back(MyFlags);
7716 PartBase += VT.getStoreSize();
7720 // Call the target to set up the argument values.
7721 SmallVector<SDValue, 8> InVals;
7722 SDValue NewRoot = TLI->LowerFormalArguments(
7723 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7725 // Verify that the target's LowerFormalArguments behaved as expected.
7726 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7727 "LowerFormalArguments didn't return a valid chain!");
7728 assert(InVals.size() == Ins.size() &&
7729 "LowerFormalArguments didn't emit the correct number of values!");
7731 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7732 assert(InVals[i].getNode() &&
7733 "LowerFormalArguments emitted a null value!");
7734 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7735 "LowerFormalArguments emitted a value with the wrong type!");
7739 // Update the DAG with the new chain value resulting from argument lowering.
7740 DAG.setRoot(NewRoot);
7742 // Set up the argument values.
7745 if (!FuncInfo->CanLowerReturn) {
7746 // Create a virtual register for the sret pointer, and put in a copy
7747 // from the sret argument into it.
7748 SmallVector<EVT, 1> ValueVTs;
7749 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7750 MVT VT = ValueVTs[0].getSimpleVT();
7751 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7752 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7753 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7754 RegVT, VT, nullptr, AssertOp);
7756 MachineFunction& MF = SDB->DAG.getMachineFunction();
7757 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7758 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7759 FuncInfo->DemoteRegister = SRetReg;
7761 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7762 DAG.setRoot(NewRoot);
7764 // i indexes lowered arguments. Bump it past the hidden sret argument.
7765 // Idx indexes LLVM arguments. Don't touch it.
7769 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7771 SmallVector<SDValue, 4> ArgValues;
7772 SmallVector<EVT, 4> ValueVTs;
7773 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7774 unsigned NumValues = ValueVTs.size();
7776 // If this argument is unused then remember its value. It is used to generate
7777 // debugging information.
7778 if (I->use_empty() && NumValues) {
7779 SDB->setUnusedArgValue(I, InVals[i]);
7781 // Also remember any frame index for use in FastISel.
7782 if (FrameIndexSDNode *FI =
7783 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7784 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7787 for (unsigned Val = 0; Val != NumValues; ++Val) {
7788 EVT VT = ValueVTs[Val];
7789 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7790 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7792 if (!I->use_empty()) {
7793 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7794 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7795 AssertOp = ISD::AssertSext;
7796 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7797 AssertOp = ISD::AssertZext;
7799 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7800 NumParts, PartVT, VT,
7801 nullptr, AssertOp));
7807 // We don't need to do anything else for unused arguments.
7808 if (ArgValues.empty())
7811 // Note down frame index.
7812 if (FrameIndexSDNode *FI =
7813 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7814 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7816 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7817 SDB->getCurSDLoc());
7819 SDB->setValue(I, Res);
7820 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7821 if (LoadSDNode *LNode =
7822 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7823 if (FrameIndexSDNode *FI =
7824 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7825 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7828 // If this argument is live outside of the entry block, insert a copy from
7829 // wherever we got it to the vreg that other BB's will reference it as.
7830 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7831 // If we can, though, try to skip creating an unnecessary vreg.
7832 // FIXME: This isn't very clean... it would be nice to make this more
7833 // general. It's also subtly incompatible with the hacks FastISel
7835 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7836 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7837 FuncInfo->ValueMap[I] = Reg;
7841 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7842 FuncInfo->InitializeRegForValue(I);
7843 SDB->CopyToExportRegsIfNeeded(I);
7847 assert(i == InVals.size() && "Argument register count mismatch!");
7849 // Finally, if the target has anything special to do, allow it to do so.
7850 // FIXME: this should insert code into the DAG!
7851 EmitFunctionEntryCode();
7854 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7855 /// ensure constants are generated when needed. Remember the virtual registers
7856 /// that need to be added to the Machine PHI nodes as input. We cannot just
7857 /// directly add them, because expansion might result in multiple MBB's for one
7858 /// BB. As such, the start of the BB might correspond to a different MBB than
7862 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7863 const TerminatorInst *TI = LLVMBB->getTerminator();
7865 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7867 // Check successor nodes' PHI nodes that expect a constant to be available
7869 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7870 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7871 if (!isa<PHINode>(SuccBB->begin())) continue;
7872 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7874 // If this terminator has multiple identical successors (common for
7875 // switches), only handle each succ once.
7876 if (!SuccsHandled.insert(SuccMBB).second)
7879 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7881 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7882 // nodes and Machine PHI nodes, but the incoming operands have not been
7884 for (BasicBlock::const_iterator I = SuccBB->begin();
7885 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7886 // Ignore dead phi's.
7887 if (PN->use_empty()) continue;
7890 if (PN->getType()->isEmptyTy())
7894 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7896 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7897 unsigned &RegOut = ConstantsOut[C];
7899 RegOut = FuncInfo.CreateRegs(C->getType());
7900 CopyValueToVirtualRegister(C, RegOut);
7904 DenseMap<const Value *, unsigned>::iterator I =
7905 FuncInfo.ValueMap.find(PHIOp);
7906 if (I != FuncInfo.ValueMap.end())
7909 assert(isa<AllocaInst>(PHIOp) &&
7910 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7911 "Didn't codegen value into a register!??");
7912 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7913 CopyValueToVirtualRegister(PHIOp, Reg);
7917 // Remember that this register needs to added to the machine PHI node as
7918 // the input for this MBB.
7919 SmallVector<EVT, 4> ValueVTs;
7920 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7921 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7922 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7923 EVT VT = ValueVTs[vti];
7924 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7925 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7926 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7927 Reg += NumRegisters;
7932 ConstantsOut.clear();
7935 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7938 SelectionDAGBuilder::StackProtectorDescriptor::
7939 AddSuccessorMBB(const BasicBlock *BB,
7940 MachineBasicBlock *ParentMBB,
7942 MachineBasicBlock *SuccMBB) {
7943 // If SuccBB has not been created yet, create it.
7945 MachineFunction *MF = ParentMBB->getParent();
7946 MachineFunction::iterator BBI = ParentMBB;
7947 SuccMBB = MF->CreateMachineBasicBlock(BB);
7948 MF->insert(++BBI, SuccMBB);
7950 // Add it as a successor of ParentMBB.
7951 ParentMBB->addSuccessor(
7952 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));