1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Constants.h"
37 #include "llvm/DataLayout.h"
38 #include "llvm/DebugInfo.h"
39 #include "llvm/DerivedTypes.h"
40 #include "llvm/Function.h"
41 #include "llvm/GlobalVariable.h"
42 #include "llvm/InlineAsm.h"
43 #include "llvm/Instructions.h"
44 #include "llvm/IntrinsicInst.h"
45 #include "llvm/Intrinsics.h"
46 #include "llvm/LLVMContext.h"
47 #include "llvm/Module.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/IntegersSubsetMapping.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
63 /// LimitFloatPrecision - Generate low-precision inline sequences for
64 /// some float libcalls (6, 8 or 12 bits).
65 static unsigned LimitFloatPrecision;
67 static cl::opt<unsigned, true>
68 LimitFPPrecision("limit-float-precision",
69 cl::desc("Generate low-precision inline sequences "
70 "for some float libcalls"),
71 cl::location(LimitFloatPrecision),
74 // Limit the width of DAG chains. This is important in general to prevent
75 // prevent DAG-based analysis from blowing up. For example, alias analysis and
76 // load clustering may not complete in reasonable time. It is difficult to
77 // recognize and avoid this situation within each individual analysis, and
78 // future analyses are likely to have the same behavior. Limiting DAG width is
79 // the safe approach, and will be especially important with global DAGs.
81 // MaxParallelChains default is arbitrarily high to avoid affecting
82 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
83 // sequence over this should have been converted to llvm.memcpy by the
84 // frontend. It easy to induce this behavior with .ll code such as:
85 // %buffer = alloca [4096 x i8]
86 // %data = load [4096 x i8]* %argPtr
87 // store [4096 x i8] %data, [4096 x i8]* %buffer
88 static const unsigned MaxParallelChains = 64;
90 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
91 const SDValue *Parts, unsigned NumParts,
92 MVT PartVT, EVT ValueVT, const Value *V);
94 /// getCopyFromParts - Create a value that contains the specified legal parts
95 /// combined into the value they represent. If the parts combine to a type
96 /// larger then ValueVT then AssertOp can be used to specify whether the extra
97 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
98 /// (ISD::AssertSext).
99 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
100 const SDValue *Parts,
101 unsigned NumParts, MVT PartVT, EVT ValueVT,
103 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
104 if (ValueVT.isVector())
105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
108 assert(NumParts > 0 && "No parts to assemble!");
109 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
110 SDValue Val = Parts[0];
113 // Assemble the value from multiple parts.
114 if (ValueVT.isInteger()) {
115 unsigned PartBits = PartVT.getSizeInBits();
116 unsigned ValueBits = ValueVT.getSizeInBits();
118 // Assemble the power of 2 part.
119 unsigned RoundParts = NumParts & (NumParts - 1) ?
120 1 << Log2_32(NumParts) : NumParts;
121 unsigned RoundBits = PartBits * RoundParts;
122 EVT RoundVT = RoundBits == ValueBits ?
123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
128 if (RoundParts > 2) {
129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
131 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
132 RoundParts / 2, PartVT, HalfVT, V);
134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
138 if (TLI.isBigEndian())
141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
143 if (RoundParts < NumParts) {
144 // Assemble the trailing non-power-of-2 part.
145 unsigned OddParts = NumParts - RoundParts;
146 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
147 Hi = getCopyFromParts(DAG, DL,
148 Parts + RoundParts, OddParts, PartVT, OddVT, V);
150 // Combine the round and odd parts.
152 if (TLI.isBigEndian())
154 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
157 DAG.getConstant(Lo.getValueType().getSizeInBits(),
158 TLI.getPointerTy()));
159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
160 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
162 } else if (PartVT.isFloatingPoint()) {
163 // FP split into multiple FP parts (for ppcf128)
164 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
167 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
168 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
169 if (TLI.isBigEndian())
171 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
173 // FP split into integer parts (soft fp)
174 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
175 !PartVT.isVector() && "Unexpected split");
176 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
177 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
181 // There is now one part, held in Val. Correct it to match ValueVT.
182 EVT PartEVT = Val.getValueType();
184 if (PartEVT == ValueVT)
187 if (PartEVT.isInteger() && ValueVT.isInteger()) {
188 if (ValueVT.bitsLT(PartEVT)) {
189 // For a truncate, see if we have any information to
190 // indicate whether the truncated bits will always be
191 // zero or sign-extension.
192 if (AssertOp != ISD::DELETED_NODE)
193 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
194 DAG.getValueType(ValueVT));
195 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
197 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
200 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
201 // FP_ROUND's are always exact here.
202 if (ValueVT.bitsLT(Val.getValueType()))
203 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
204 DAG.getTargetConstant(1, TLI.getPointerTy()));
206 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
209 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
210 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
212 llvm_unreachable("Unknown mismatch!");
215 /// getCopyFromPartsVector - Create a value that contains the specified legal
216 /// parts combined into the value they represent. If the parts combine to a
217 /// type larger then ValueVT then AssertOp can be used to specify whether the
218 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
219 /// ValueVT (ISD::AssertSext).
220 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
221 const SDValue *Parts, unsigned NumParts,
222 MVT PartVT, EVT ValueVT, const Value *V) {
223 assert(ValueVT.isVector() && "Not a vector value");
224 assert(NumParts > 0 && "No parts to assemble!");
225 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
226 SDValue Val = Parts[0];
228 // Handle a multi-element vector.
232 unsigned NumIntermediates;
234 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
235 NumIntermediates, RegisterVT);
236 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
237 NumParts = NumRegs; // Silence a compiler warning.
238 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
239 assert(RegisterVT == Parts[0].getSimpleValueType() &&
240 "Part type doesn't match part!");
242 // Assemble the parts into intermediate operands.
243 SmallVector<SDValue, 8> Ops(NumIntermediates);
244 if (NumIntermediates == NumParts) {
245 // If the register was not expanded, truncate or copy the value,
247 for (unsigned i = 0; i != NumParts; ++i)
248 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
249 PartVT, IntermediateVT, V);
250 } else if (NumParts > 0) {
251 // If the intermediate type was expanded, build the intermediate
252 // operands from the parts.
253 assert(NumParts % NumIntermediates == 0 &&
254 "Must expand into a divisible number of parts!");
255 unsigned Factor = NumParts / NumIntermediates;
256 for (unsigned i = 0; i != NumIntermediates; ++i)
257 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
258 PartVT, IntermediateVT, V);
261 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
262 // intermediate operands.
263 Val = DAG.getNode(IntermediateVT.isVector() ?
264 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
265 ValueVT, &Ops[0], NumIntermediates);
268 // There is now one part, held in Val. Correct it to match ValueVT.
269 EVT PartEVT = Val.getValueType();
271 if (PartEVT == ValueVT)
274 if (PartEVT.isVector()) {
275 // If the element type of the source/dest vectors are the same, but the
276 // parts vector has more elements than the value vector, then we have a
277 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
279 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
280 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
281 "Cannot narrow, it would be a lossy transformation");
282 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
283 DAG.getIntPtrConstant(0));
286 // Vector/Vector bitcast.
287 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
288 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
290 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
291 "Cannot handle this kind of promotion");
292 // Promoted vector extract
293 bool Smaller = ValueVT.bitsLE(PartEVT);
294 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
299 // Trivial bitcast if the types are the same size and the destination
300 // vector type is legal.
301 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
302 TLI.isTypeLegal(ValueVT))
303 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
305 // Handle cases such as i8 -> <1 x i1>
306 if (ValueVT.getVectorNumElements() != 1) {
307 LLVMContext &Ctx = *DAG.getContext();
308 Twine ErrMsg("non-trivial scalar-to-vector conversion");
309 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
310 if (const CallInst *CI = dyn_cast<CallInst>(I))
311 if (isa<InlineAsm>(CI->getCalledValue()))
312 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
313 Ctx.emitError(I, ErrMsg);
315 Ctx.emitError(ErrMsg);
317 report_fatal_error("Cannot handle scalar-to-vector conversion!");
320 if (ValueVT.getVectorNumElements() == 1 &&
321 ValueVT.getVectorElementType() != PartEVT) {
322 bool Smaller = ValueVT.bitsLE(PartEVT);
323 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
324 DL, ValueVT.getScalarType(), Val);
327 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
330 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
331 SDValue Val, SDValue *Parts, unsigned NumParts,
332 MVT PartVT, const Value *V);
334 /// getCopyToParts - Create a series of nodes that contain the specified value
335 /// split into legal parts. If the parts contain more bits than Val, then, for
336 /// integers, ExtendKind can be used to specify how to generate the extra bits.
337 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
338 SDValue Val, SDValue *Parts, unsigned NumParts,
339 MVT PartVT, const Value *V,
340 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
341 EVT ValueVT = Val.getValueType();
343 // Handle the vector case separately.
344 if (ValueVT.isVector())
345 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
348 unsigned PartBits = PartVT.getSizeInBits();
349 unsigned OrigNumParts = NumParts;
350 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
355 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
356 EVT PartEVT = PartVT;
357 if (PartEVT == ValueVT) {
358 assert(NumParts == 1 && "No-op copy with multiple parts!");
363 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
364 // If the parts cover more bits than the value has, promote the value.
365 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
366 assert(NumParts == 1 && "Do not know what to promote to!");
367 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
369 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
370 ValueVT.isInteger() &&
371 "Unknown mismatch!");
372 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
373 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
374 if (PartVT == MVT::x86mmx)
375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
377 } else if (PartBits == ValueVT.getSizeInBits()) {
378 // Different types of the same size.
379 assert(NumParts == 1 && PartEVT != ValueVT);
380 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
381 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
382 // If the parts cover less bits than value has, truncate the value.
383 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
384 ValueVT.isInteger() &&
385 "Unknown mismatch!");
386 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
387 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
388 if (PartVT == MVT::x86mmx)
389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
392 // The value may have changed - recompute ValueVT.
393 ValueVT = Val.getValueType();
394 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
395 "Failed to tile the value with PartVT!");
398 if (PartEVT != ValueVT) {
399 LLVMContext &Ctx = *DAG.getContext();
400 Twine ErrMsg("scalar-to-vector conversion failed");
401 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
402 if (const CallInst *CI = dyn_cast<CallInst>(I))
403 if (isa<InlineAsm>(CI->getCalledValue()))
404 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
405 Ctx.emitError(I, ErrMsg);
407 Ctx.emitError(ErrMsg);
415 // Expand the value into multiple parts.
416 if (NumParts & (NumParts - 1)) {
417 // The number of parts is not a power of 2. Split off and copy the tail.
418 assert(PartVT.isInteger() && ValueVT.isInteger() &&
419 "Do not know what to expand to!");
420 unsigned RoundParts = 1 << Log2_32(NumParts);
421 unsigned RoundBits = RoundParts * PartBits;
422 unsigned OddParts = NumParts - RoundParts;
423 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
424 DAG.getIntPtrConstant(RoundBits));
425 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
427 if (TLI.isBigEndian())
428 // The odd parts were reversed by getCopyToParts - unreverse them.
429 std::reverse(Parts + RoundParts, Parts + NumParts);
431 NumParts = RoundParts;
432 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
433 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
436 // The number of parts is a power of 2. Repeatedly bisect the value using
438 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
439 EVT::getIntegerVT(*DAG.getContext(),
440 ValueVT.getSizeInBits()),
443 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
444 for (unsigned i = 0; i < NumParts; i += StepSize) {
445 unsigned ThisBits = StepSize * PartBits / 2;
446 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
447 SDValue &Part0 = Parts[i];
448 SDValue &Part1 = Parts[i+StepSize/2];
450 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
451 ThisVT, Part0, DAG.getIntPtrConstant(1));
452 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
453 ThisVT, Part0, DAG.getIntPtrConstant(0));
455 if (ThisBits == PartBits && ThisVT != PartVT) {
456 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
457 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
462 if (TLI.isBigEndian())
463 std::reverse(Parts, Parts + OrigNumParts);
467 /// getCopyToPartsVector - Create a series of nodes that contain the specified
468 /// value split into legal parts.
469 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
470 SDValue Val, SDValue *Parts, unsigned NumParts,
471 MVT PartVT, const Value *V) {
472 EVT ValueVT = Val.getValueType();
473 assert(ValueVT.isVector() && "Not a vector");
474 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
477 EVT PartEVT = PartVT;
478 if (PartEVT == ValueVT) {
480 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
481 // Bitconvert vector->vector case.
482 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
483 } else if (PartVT.isVector() &&
484 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
485 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
486 EVT ElementVT = PartVT.getVectorElementType();
487 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
489 SmallVector<SDValue, 16> Ops;
490 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
491 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
492 ElementVT, Val, DAG.getIntPtrConstant(i)));
494 for (unsigned i = ValueVT.getVectorNumElements(),
495 e = PartVT.getVectorNumElements(); i != e; ++i)
496 Ops.push_back(DAG.getUNDEF(ElementVT));
498 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
500 // FIXME: Use CONCAT for 2x -> 4x.
502 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
503 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
504 } else if (PartVT.isVector() &&
505 PartEVT.getVectorElementType().bitsGE(
506 ValueVT.getVectorElementType()) &&
507 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
509 // Promoted vector extract
510 bool Smaller = PartEVT.bitsLE(ValueVT);
511 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
514 // Vector -> scalar conversion.
515 assert(ValueVT.getVectorNumElements() == 1 &&
516 "Only trivial vector-to-scalar conversions should get here!");
517 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
518 PartVT, Val, DAG.getIntPtrConstant(0));
520 bool Smaller = ValueVT.bitsLE(PartVT);
521 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
529 // Handle a multi-element vector.
532 unsigned NumIntermediates;
533 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
535 NumIntermediates, RegisterVT);
536 unsigned NumElements = ValueVT.getVectorNumElements();
538 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
539 NumParts = NumRegs; // Silence a compiler warning.
540 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
542 // Split the vector into intermediate operands.
543 SmallVector<SDValue, 8> Ops(NumIntermediates);
544 for (unsigned i = 0; i != NumIntermediates; ++i) {
545 if (IntermediateVT.isVector())
546 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
548 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
550 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
551 IntermediateVT, Val, DAG.getIntPtrConstant(i));
554 // Split the intermediate operands into legal parts.
555 if (NumParts == NumIntermediates) {
556 // If the register was not expanded, promote or copy the value,
558 for (unsigned i = 0; i != NumParts; ++i)
559 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
560 } else if (NumParts > 0) {
561 // If the intermediate type was expanded, split each the value into
563 assert(NumParts % NumIntermediates == 0 &&
564 "Must expand into a divisible number of parts!");
565 unsigned Factor = NumParts / NumIntermediates;
566 for (unsigned i = 0; i != NumIntermediates; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
572 /// RegsForValue - This struct represents the registers (physical or virtual)
573 /// that a particular set of values is assigned, and the type information
574 /// about the value. The most common situation is to represent one value at a
575 /// time, but struct or array values are handled element-wise as multiple
576 /// values. The splitting of aggregates is performed recursively, so that we
577 /// never have aggregate-typed registers. The values at this point do not
578 /// necessarily have legal types, so each value may require one or more
579 /// registers of some legal type.
581 struct RegsForValue {
582 /// ValueVTs - The value types of the values, which may not be legal, and
583 /// may need be promoted or synthesized from one or more registers.
585 SmallVector<EVT, 4> ValueVTs;
587 /// RegVTs - The value types of the registers. This is the same size as
588 /// ValueVTs and it records, for each value, what the type of the assigned
589 /// register or registers are. (Individual values are never synthesized
590 /// from more than one type of register.)
592 /// With virtual registers, the contents of RegVTs is redundant with TLI's
593 /// getRegisterType member function, however when with physical registers
594 /// it is necessary to have a separate record of the types.
596 SmallVector<MVT, 4> RegVTs;
598 /// Regs - This list holds the registers assigned to the values.
599 /// Each legal or promoted value requires one register, and each
600 /// expanded value requires multiple registers.
602 SmallVector<unsigned, 4> Regs;
606 RegsForValue(const SmallVector<unsigned, 4> ®s,
607 MVT regvt, EVT valuevt)
608 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
610 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
611 unsigned Reg, Type *Ty) {
612 ComputeValueVTs(tli, Ty, ValueVTs);
614 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
615 EVT ValueVT = ValueVTs[Value];
616 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
617 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
618 for (unsigned i = 0; i != NumRegs; ++i)
619 Regs.push_back(Reg + i);
620 RegVTs.push_back(RegisterVT);
625 /// areValueTypesLegal - Return true if types of all the values are legal.
626 bool areValueTypesLegal(const TargetLowering &TLI) {
627 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
628 MVT RegisterVT = RegVTs[Value];
629 if (!TLI.isTypeLegal(RegisterVT))
635 /// append - Add the specified values to this one.
636 void append(const RegsForValue &RHS) {
637 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
638 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
639 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
642 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
643 /// this value and returns the result as a ValueVTs value. This uses
644 /// Chain/Flag as the input and updates them for the output Chain/Flag.
645 /// If the Flag pointer is NULL, no flag is used.
646 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
648 SDValue &Chain, SDValue *Flag,
649 const Value *V = 0) const;
651 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
652 /// specified value into the registers specified by this object. This uses
653 /// Chain/Flag as the input and updates them for the output Chain/Flag.
654 /// If the Flag pointer is NULL, no flag is used.
655 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
656 SDValue &Chain, SDValue *Flag, const Value *V) const;
658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
659 /// operand list. This adds the code marker, matching input operand index
660 /// (if applicable), and includes the number of values added into it.
661 void AddInlineAsmOperands(unsigned Kind,
662 bool HasMatching, unsigned MatchingIdx,
664 std::vector<SDValue> &Ops) const;
668 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
669 /// this value and returns the result as a ValueVT value. This uses
670 /// Chain/Flag as the input and updates them for the output Chain/Flag.
671 /// If the Flag pointer is NULL, no flag is used.
672 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
673 FunctionLoweringInfo &FuncInfo,
675 SDValue &Chain, SDValue *Flag,
676 const Value *V) const {
677 // A Value with type {} or [0 x %t] needs no registers.
678 if (ValueVTs.empty())
681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
683 // Assemble the legal parts into the final values.
684 SmallVector<SDValue, 4> Values(ValueVTs.size());
685 SmallVector<SDValue, 8> Parts;
686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
687 // Copy the legal parts from the registers.
688 EVT ValueVT = ValueVTs[Value];
689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
690 MVT RegisterVT = RegVTs[Value];
692 Parts.resize(NumRegs);
693 for (unsigned i = 0; i != NumRegs; ++i) {
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
699 *Flag = P.getValue(2);
702 Chain = P.getValue(1);
705 // If the source register was virtual and if we know something about it,
706 // add an assert node.
707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
708 !RegisterVT.isInteger() || RegisterVT.isVector())
711 const FunctionLoweringInfo::LiveOutInfo *LOI =
712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
716 unsigned RegSize = RegisterVT.getSizeInBits();
717 unsigned NumSignBits = LOI->NumSignBits;
718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
720 // FIXME: We capture more information than the dag can represent. For
721 // now, just use the tightest assertzext/assertsext possible.
723 EVT FromVT(MVT::Other);
724 if (NumSignBits == RegSize)
725 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
726 else if (NumZeroBits >= RegSize-1)
727 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
728 else if (NumSignBits > RegSize-8)
729 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
730 else if (NumZeroBits >= RegSize-8)
731 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
732 else if (NumSignBits > RegSize-16)
733 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
734 else if (NumZeroBits >= RegSize-16)
735 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
736 else if (NumSignBits > RegSize-32)
737 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
738 else if (NumZeroBits >= RegSize-32)
739 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
743 // Add an assertion node.
744 assert(FromVT != MVT::Other);
745 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
746 RegisterVT, P, DAG.getValueType(FromVT));
749 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
750 NumRegs, RegisterVT, ValueVT, V);
755 return DAG.getNode(ISD::MERGE_VALUES, dl,
756 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
757 &Values[0], ValueVTs.size());
760 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
761 /// specified value into the registers specified by this object. This uses
762 /// Chain/Flag as the input and updates them for the output Chain/Flag.
763 /// If the Flag pointer is NULL, no flag is used.
764 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
765 SDValue &Chain, SDValue *Flag,
766 const Value *V) const {
767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
769 // Get the list of the values's legal parts.
770 unsigned NumRegs = Regs.size();
771 SmallVector<SDValue, 8> Parts(NumRegs);
772 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
773 EVT ValueVT = ValueVTs[Value];
774 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
775 MVT RegisterVT = RegVTs[Value];
776 ISD::NodeType ExtendKind =
777 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
779 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
780 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
784 // Copy the parts into the registers.
785 SmallVector<SDValue, 8> Chains(NumRegs);
786 for (unsigned i = 0; i != NumRegs; ++i) {
789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
791 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
792 *Flag = Part.getValue(1);
795 Chains[i] = Part.getValue(0);
798 if (NumRegs == 1 || Flag)
799 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
800 // flagged to it. That is the CopyToReg nodes and the user are considered
801 // a single scheduling unit. If we create a TokenFactor and return it as
802 // chain, then the TokenFactor is both a predecessor (operand) of the
803 // user as well as a successor (the TF operands are flagged to the user).
804 // c1, f1 = CopyToReg
805 // c2, f2 = CopyToReg
806 // c3 = TokenFactor c1, c2
809 Chain = Chains[NumRegs-1];
811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
814 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
815 /// operand list. This adds the code marker and includes the number of
816 /// values added into it.
817 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
818 unsigned MatchingIdx,
820 std::vector<SDValue> &Ops) const {
821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
823 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
825 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
826 else if (!Regs.empty() &&
827 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
828 // Put the register class of the virtual registers in the flag word. That
829 // way, later passes can recompute register class constraints for inline
830 // assembly as well as normal instructions.
831 // Don't do this for tied operands that can use the regclass information
833 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
834 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
835 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
838 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
841 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
842 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
843 MVT RegisterVT = RegVTs[Value];
844 for (unsigned i = 0; i != NumRegs; ++i) {
845 assert(Reg < Regs.size() && "Mismatch in # registers expected");
846 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
851 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
852 const TargetLibraryInfo *li) {
856 TD = DAG.getTarget().getDataLayout();
857 Context = DAG.getContext();
858 LPadToCallSiteMap.clear();
861 /// clear - Clear out the current SelectionDAG and the associated
862 /// state and prepare this SelectionDAGBuilder object to be used
863 /// for a new block. This doesn't clear out information about
864 /// additional blocks that are needed to complete switch lowering
865 /// or PHI node updating; that information is cleared out as it is
867 void SelectionDAGBuilder::clear() {
869 UnusedArgNodeMap.clear();
870 PendingLoads.clear();
871 PendingExports.clear();
872 CurDebugLoc = DebugLoc();
876 /// clearDanglingDebugInfo - Clear the dangling debug information
877 /// map. This function is separated from the clear so that debug
878 /// information that is dangling in a basic block can be properly
879 /// resolved in a different basic block. This allows the
880 /// SelectionDAG to resolve dangling debug information attached
882 void SelectionDAGBuilder::clearDanglingDebugInfo() {
883 DanglingDebugInfoMap.clear();
886 /// getRoot - Return the current virtual root of the Selection DAG,
887 /// flushing any PendingLoad items. This must be done before emitting
888 /// a store or any other node that may need to be ordered after any
889 /// prior load instructions.
891 SDValue SelectionDAGBuilder::getRoot() {
892 if (PendingLoads.empty())
893 return DAG.getRoot();
895 if (PendingLoads.size() == 1) {
896 SDValue Root = PendingLoads[0];
898 PendingLoads.clear();
902 // Otherwise, we have to make a token factor node.
903 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
904 &PendingLoads[0], PendingLoads.size());
905 PendingLoads.clear();
910 /// getControlRoot - Similar to getRoot, but instead of flushing all the
911 /// PendingLoad items, flush all the PendingExports items. It is necessary
912 /// to do this before emitting a terminator instruction.
914 SDValue SelectionDAGBuilder::getControlRoot() {
915 SDValue Root = DAG.getRoot();
917 if (PendingExports.empty())
920 // Turn all of the CopyToReg chains into one factored node.
921 if (Root.getOpcode() != ISD::EntryToken) {
922 unsigned i = 0, e = PendingExports.size();
923 for (; i != e; ++i) {
924 assert(PendingExports[i].getNode()->getNumOperands() > 1);
925 if (PendingExports[i].getNode()->getOperand(0) == Root)
926 break; // Don't add the root if we already indirectly depend on it.
930 PendingExports.push_back(Root);
933 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
935 PendingExports.size());
936 PendingExports.clear();
941 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
942 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
943 DAG.AssignOrdering(Node, SDNodeOrder);
945 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
946 AssignOrderingToNode(Node->getOperand(I).getNode());
949 void SelectionDAGBuilder::visit(const Instruction &I) {
950 // Set up outgoing PHI node register values before emitting the terminator.
951 if (isa<TerminatorInst>(&I))
952 HandlePHINodesInSuccessorBlocks(I.getParent());
954 CurDebugLoc = I.getDebugLoc();
956 visit(I.getOpcode(), I);
958 if (!isa<TerminatorInst>(&I) && !HasTailCall)
959 CopyToExportRegsIfNeeded(&I);
961 CurDebugLoc = DebugLoc();
964 void SelectionDAGBuilder::visitPHI(const PHINode &) {
965 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
968 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
969 // Note: this doesn't use InstVisitor, because it has to work with
970 // ConstantExpr's in addition to instructions.
972 default: llvm_unreachable("Unknown instruction type encountered!");
973 // Build the switch statement using the Instruction.def file.
974 #define HANDLE_INST(NUM, OPCODE, CLASS) \
975 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
976 #include "llvm/Instruction.def"
979 // Assign the ordering to the freshly created DAG nodes.
980 if (NodeMap.count(&I)) {
982 AssignOrderingToNode(getValue(&I).getNode());
986 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
987 // generate the debug data structures now that we've seen its definition.
988 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
990 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
992 const DbgValueInst *DI = DDI.getDI();
993 DebugLoc dl = DDI.getdl();
994 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
995 MDNode *Variable = DI->getVariable();
996 uint64_t Offset = DI->getOffset();
999 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
1000 SDV = DAG.getDbgValue(Variable, Val.getNode(),
1001 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
1002 DAG.AddDbgValue(SDV, Val.getNode(), false);
1005 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
1006 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1010 /// getValue - Return an SDValue for the given Value.
1011 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1012 // If we already have an SDValue for this value, use it. It's important
1013 // to do this first, so that we don't create a CopyFromReg if we already
1014 // have a regular SDValue.
1015 SDValue &N = NodeMap[V];
1016 if (N.getNode()) return N;
1018 // If there's a virtual register allocated and initialized for this
1020 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1021 if (It != FuncInfo.ValueMap.end()) {
1022 unsigned InReg = It->second;
1023 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
1024 SDValue Chain = DAG.getEntryNode();
1025 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V);
1026 resolveDanglingDebugInfo(V, N);
1030 // Otherwise create a new SDValue and remember it.
1031 SDValue Val = getValueImpl(V);
1033 resolveDanglingDebugInfo(V, Val);
1037 /// getNonRegisterValue - Return an SDValue for the given Value, but
1038 /// don't look in FuncInfo.ValueMap for a virtual register.
1039 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1040 // If we already have an SDValue for this value, use it.
1041 SDValue &N = NodeMap[V];
1042 if (N.getNode()) return N;
1044 // Otherwise create a new SDValue and remember it.
1045 SDValue Val = getValueImpl(V);
1047 resolveDanglingDebugInfo(V, Val);
1051 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1052 /// Create an SDValue for the given value.
1053 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1054 if (const Constant *C = dyn_cast<Constant>(V)) {
1055 EVT VT = TLI.getValueType(V->getType(), true);
1057 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1058 return DAG.getConstant(*CI, VT);
1060 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1061 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1063 if (isa<ConstantPointerNull>(C))
1064 return DAG.getConstant(0, TLI.getPointerTy());
1066 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1067 return DAG.getConstantFP(*CFP, VT);
1069 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1070 return DAG.getUNDEF(VT);
1072 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1073 visit(CE->getOpcode(), *CE);
1074 SDValue N1 = NodeMap[V];
1075 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1079 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1080 SmallVector<SDValue, 4> Constants;
1081 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1083 SDNode *Val = getValue(*OI).getNode();
1084 // If the operand is an empty aggregate, there are no values.
1086 // Add each leaf value from the operand to the Constants list
1087 // to form a flattened list of all the values.
1088 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1089 Constants.push_back(SDValue(Val, i));
1092 return DAG.getMergeValues(&Constants[0], Constants.size(),
1096 if (const ConstantDataSequential *CDS =
1097 dyn_cast<ConstantDataSequential>(C)) {
1098 SmallVector<SDValue, 4> Ops;
1099 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1100 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1101 // Add each leaf value from the operand to the Constants list
1102 // to form a flattened list of all the values.
1103 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1104 Ops.push_back(SDValue(Val, i));
1107 if (isa<ArrayType>(CDS->getType()))
1108 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc());
1109 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1110 VT, &Ops[0], Ops.size());
1113 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1114 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1115 "Unknown struct or array constant!");
1117 SmallVector<EVT, 4> ValueVTs;
1118 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1119 unsigned NumElts = ValueVTs.size();
1121 return SDValue(); // empty struct
1122 SmallVector<SDValue, 4> Constants(NumElts);
1123 for (unsigned i = 0; i != NumElts; ++i) {
1124 EVT EltVT = ValueVTs[i];
1125 if (isa<UndefValue>(C))
1126 Constants[i] = DAG.getUNDEF(EltVT);
1127 else if (EltVT.isFloatingPoint())
1128 Constants[i] = DAG.getConstantFP(0, EltVT);
1130 Constants[i] = DAG.getConstant(0, EltVT);
1133 return DAG.getMergeValues(&Constants[0], NumElts,
1137 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1138 return DAG.getBlockAddress(BA, VT);
1140 VectorType *VecTy = cast<VectorType>(V->getType());
1141 unsigned NumElements = VecTy->getNumElements();
1143 // Now that we know the number and type of the elements, get that number of
1144 // elements into the Ops array based on what kind of constant it is.
1145 SmallVector<SDValue, 16> Ops;
1146 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1147 for (unsigned i = 0; i != NumElements; ++i)
1148 Ops.push_back(getValue(CV->getOperand(i)));
1150 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1151 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1154 if (EltVT.isFloatingPoint())
1155 Op = DAG.getConstantFP(0, EltVT);
1157 Op = DAG.getConstant(0, EltVT);
1158 Ops.assign(NumElements, Op);
1161 // Create a BUILD_VECTOR node.
1162 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1163 VT, &Ops[0], Ops.size());
1166 // If this is a static alloca, generate it as the frameindex instead of
1168 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1169 DenseMap<const AllocaInst*, int>::iterator SI =
1170 FuncInfo.StaticAllocaMap.find(AI);
1171 if (SI != FuncInfo.StaticAllocaMap.end())
1172 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1175 // If this is an instruction which fast-isel has deferred, select it now.
1176 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1177 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1178 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1179 SDValue Chain = DAG.getEntryNode();
1180 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V);
1183 llvm_unreachable("Can't get register for value!");
1186 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1187 SDValue Chain = getControlRoot();
1188 SmallVector<ISD::OutputArg, 8> Outs;
1189 SmallVector<SDValue, 8> OutVals;
1191 if (!FuncInfo.CanLowerReturn) {
1192 unsigned DemoteReg = FuncInfo.DemoteRegister;
1193 const Function *F = I.getParent()->getParent();
1195 // Emit a store of the return value through the virtual register.
1196 // Leave Outs empty so that LowerReturn won't try to load return
1197 // registers the usual way.
1198 SmallVector<EVT, 1> PtrValueVTs;
1199 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1202 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1203 SDValue RetOp = getValue(I.getOperand(0));
1205 SmallVector<EVT, 4> ValueVTs;
1206 SmallVector<uint64_t, 4> Offsets;
1207 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1208 unsigned NumValues = ValueVTs.size();
1210 SmallVector<SDValue, 4> Chains(NumValues);
1211 for (unsigned i = 0; i != NumValues; ++i) {
1212 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1213 RetPtr.getValueType(), RetPtr,
1214 DAG.getIntPtrConstant(Offsets[i]));
1216 DAG.getStore(Chain, getCurDebugLoc(),
1217 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1218 // FIXME: better loc info would be nice.
1219 Add, MachinePointerInfo(), false, false, 0);
1222 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1223 MVT::Other, &Chains[0], NumValues);
1224 } else if (I.getNumOperands() != 0) {
1225 SmallVector<EVT, 4> ValueVTs;
1226 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1227 unsigned NumValues = ValueVTs.size();
1229 SDValue RetOp = getValue(I.getOperand(0));
1230 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1231 EVT VT = ValueVTs[j];
1233 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1235 const Function *F = I.getParent()->getParent();
1236 if (F->getRetAttributes().hasAttribute(Attribute::SExt))
1237 ExtendKind = ISD::SIGN_EXTEND;
1238 else if (F->getRetAttributes().hasAttribute(Attribute::ZExt))
1239 ExtendKind = ISD::ZERO_EXTEND;
1241 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1242 VT = TLI.getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1244 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1245 MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1246 SmallVector<SDValue, 4> Parts(NumParts);
1247 getCopyToParts(DAG, getCurDebugLoc(),
1248 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1249 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1251 // 'inreg' on function refers to return value
1252 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1253 if (F->getRetAttributes().hasAttribute(Attribute::InReg))
1256 // Propagate extension type if any
1257 if (ExtendKind == ISD::SIGN_EXTEND)
1259 else if (ExtendKind == ISD::ZERO_EXTEND)
1262 for (unsigned i = 0; i < NumParts; ++i) {
1263 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1264 /*isfixed=*/true, 0, 0));
1265 OutVals.push_back(Parts[i]);
1271 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1272 CallingConv::ID CallConv =
1273 DAG.getMachineFunction().getFunction()->getCallingConv();
1274 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1275 Outs, OutVals, getCurDebugLoc(), DAG);
1277 // Verify that the target's LowerReturn behaved as expected.
1278 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1279 "LowerReturn didn't return a valid chain!");
1281 // Update the DAG with the new chain value resulting from return lowering.
1285 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1286 /// created for it, emit nodes to copy the value into the virtual
1288 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1290 if (V->getType()->isEmptyTy())
1293 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1294 if (VMI != FuncInfo.ValueMap.end()) {
1295 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1296 CopyValueToVirtualRegister(V, VMI->second);
1300 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1301 /// the current basic block, add it to ValueMap now so that we'll get a
1303 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1304 // No need to export constants.
1305 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1307 // Already exported?
1308 if (FuncInfo.isExportedInst(V)) return;
1310 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1311 CopyValueToVirtualRegister(V, Reg);
1314 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1315 const BasicBlock *FromBB) {
1316 // The operands of the setcc have to be in this block. We don't know
1317 // how to export them from some other block.
1318 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1319 // Can export from current BB.
1320 if (VI->getParent() == FromBB)
1323 // Is already exported, noop.
1324 return FuncInfo.isExportedInst(V);
1327 // If this is an argument, we can export it if the BB is the entry block or
1328 // if it is already exported.
1329 if (isa<Argument>(V)) {
1330 if (FromBB == &FromBB->getParent()->getEntryBlock())
1333 // Otherwise, can only export this if it is already exported.
1334 return FuncInfo.isExportedInst(V);
1337 // Otherwise, constants can always be exported.
1341 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1342 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1343 const MachineBasicBlock *Dst) const {
1344 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1347 const BasicBlock *SrcBB = Src->getBasicBlock();
1348 const BasicBlock *DstBB = Dst->getBasicBlock();
1349 return BPI->getEdgeWeight(SrcBB, DstBB);
1352 void SelectionDAGBuilder::
1353 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1354 uint32_t Weight /* = 0 */) {
1356 Weight = getEdgeWeight(Src, Dst);
1357 Src->addSuccessor(Dst, Weight);
1361 static bool InBlock(const Value *V, const BasicBlock *BB) {
1362 if (const Instruction *I = dyn_cast<Instruction>(V))
1363 return I->getParent() == BB;
1367 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1368 /// This function emits a branch and is used at the leaves of an OR or an
1369 /// AND operator tree.
1372 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1373 MachineBasicBlock *TBB,
1374 MachineBasicBlock *FBB,
1375 MachineBasicBlock *CurBB,
1376 MachineBasicBlock *SwitchBB) {
1377 const BasicBlock *BB = CurBB->getBasicBlock();
1379 // If the leaf of the tree is a comparison, merge the condition into
1381 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1382 // The operands of the cmp have to be in this block. We don't know
1383 // how to export them from some other block. If this is the first block
1384 // of the sequence, no exporting is needed.
1385 if (CurBB == SwitchBB ||
1386 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1387 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1388 ISD::CondCode Condition;
1389 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1390 Condition = getICmpCondCode(IC->getPredicate());
1391 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1392 Condition = getFCmpCondCode(FC->getPredicate());
1393 if (TM.Options.NoNaNsFPMath)
1394 Condition = getFCmpCodeWithoutNaN(Condition);
1396 Condition = ISD::SETEQ; // silence warning.
1397 llvm_unreachable("Unknown compare instruction");
1400 CaseBlock CB(Condition, BOp->getOperand(0),
1401 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1402 SwitchCases.push_back(CB);
1407 // Create a CaseBlock record representing this branch.
1408 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1409 NULL, TBB, FBB, CurBB);
1410 SwitchCases.push_back(CB);
1413 /// FindMergedConditions - If Cond is an expression like
1414 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1415 MachineBasicBlock *TBB,
1416 MachineBasicBlock *FBB,
1417 MachineBasicBlock *CurBB,
1418 MachineBasicBlock *SwitchBB,
1420 // If this node is not part of the or/and tree, emit it as a branch.
1421 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1422 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1423 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1424 BOp->getParent() != CurBB->getBasicBlock() ||
1425 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1426 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1427 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1431 // Create TmpBB after CurBB.
1432 MachineFunction::iterator BBI = CurBB;
1433 MachineFunction &MF = DAG.getMachineFunction();
1434 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1435 CurBB->getParent()->insert(++BBI, TmpBB);
1437 if (Opc == Instruction::Or) {
1438 // Codegen X | Y as:
1446 // Emit the LHS condition.
1447 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1449 // Emit the RHS condition into TmpBB.
1450 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1452 assert(Opc == Instruction::And && "Unknown merge op!");
1453 // Codegen X & Y as:
1460 // This requires creation of TmpBB after CurBB.
1462 // Emit the LHS condition.
1463 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1465 // Emit the RHS condition into TmpBB.
1466 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1470 /// If the set of cases should be emitted as a series of branches, return true.
1471 /// If we should emit this as a bunch of and/or'd together conditions, return
1474 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1475 if (Cases.size() != 2) return true;
1477 // If this is two comparisons of the same values or'd or and'd together, they
1478 // will get folded into a single comparison, so don't emit two blocks.
1479 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1480 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1481 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1482 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1486 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1487 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1488 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1489 Cases[0].CC == Cases[1].CC &&
1490 isa<Constant>(Cases[0].CmpRHS) &&
1491 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1492 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1494 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1501 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1502 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1504 // Update machine-CFG edges.
1505 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1507 // Figure out which block is immediately after the current one.
1508 MachineBasicBlock *NextBlock = 0;
1509 MachineFunction::iterator BBI = BrMBB;
1510 if (++BBI != FuncInfo.MF->end())
1513 if (I.isUnconditional()) {
1514 // Update machine-CFG edges.
1515 BrMBB->addSuccessor(Succ0MBB);
1517 // If this is not a fall-through branch, emit the branch.
1518 if (Succ0MBB != NextBlock)
1519 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1520 MVT::Other, getControlRoot(),
1521 DAG.getBasicBlock(Succ0MBB)));
1526 // If this condition is one of the special cases we handle, do special stuff
1528 const Value *CondVal = I.getCondition();
1529 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1531 // If this is a series of conditions that are or'd or and'd together, emit
1532 // this as a sequence of branches instead of setcc's with and/or operations.
1533 // As long as jumps are not expensive, this should improve performance.
1534 // For example, instead of something like:
1547 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1548 if (!TLI.isJumpExpensive() &&
1550 (BOp->getOpcode() == Instruction::And ||
1551 BOp->getOpcode() == Instruction::Or)) {
1552 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1554 // If the compares in later blocks need to use values not currently
1555 // exported from this block, export them now. This block should always
1556 // be the first entry.
1557 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1559 // Allow some cases to be rejected.
1560 if (ShouldEmitAsBranches(SwitchCases)) {
1561 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1562 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1563 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1566 // Emit the branch for this block.
1567 visitSwitchCase(SwitchCases[0], BrMBB);
1568 SwitchCases.erase(SwitchCases.begin());
1572 // Okay, we decided not to do this, remove any inserted MBB's and clear
1574 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1575 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1577 SwitchCases.clear();
1581 // Create a CaseBlock record representing this branch.
1582 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1583 NULL, Succ0MBB, Succ1MBB, BrMBB);
1585 // Use visitSwitchCase to actually insert the fast branch sequence for this
1587 visitSwitchCase(CB, BrMBB);
1590 /// visitSwitchCase - Emits the necessary code to represent a single node in
1591 /// the binary search tree resulting from lowering a switch instruction.
1592 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1593 MachineBasicBlock *SwitchBB) {
1595 SDValue CondLHS = getValue(CB.CmpLHS);
1596 DebugLoc dl = getCurDebugLoc();
1598 // Build the setcc now.
1599 if (CB.CmpMHS == NULL) {
1600 // Fold "(X == true)" to X and "(X == false)" to !X to
1601 // handle common cases produced by branch lowering.
1602 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1603 CB.CC == ISD::SETEQ)
1605 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1606 CB.CC == ISD::SETEQ) {
1607 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1608 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1610 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1612 assert(CB.CC == ISD::SETCC_INVALID &&
1613 "Condition is undefined for to-the-range belonging check.");
1615 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1616 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1618 SDValue CmpOp = getValue(CB.CmpMHS);
1619 EVT VT = CmpOp.getValueType();
1621 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) {
1622 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1625 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1626 VT, CmpOp, DAG.getConstant(Low, VT));
1627 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1628 DAG.getConstant(High-Low, VT), ISD::SETULE);
1632 // Update successor info
1633 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1634 // TrueBB and FalseBB are always different unless the incoming IR is
1635 // degenerate. This only happens when running llc on weird IR.
1636 if (CB.TrueBB != CB.FalseBB)
1637 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1639 // Set NextBlock to be the MBB immediately after the current one, if any.
1640 // This is used to avoid emitting unnecessary branches to the next block.
1641 MachineBasicBlock *NextBlock = 0;
1642 MachineFunction::iterator BBI = SwitchBB;
1643 if (++BBI != FuncInfo.MF->end())
1646 // If the lhs block is the next block, invert the condition so that we can
1647 // fall through to the lhs instead of the rhs block.
1648 if (CB.TrueBB == NextBlock) {
1649 std::swap(CB.TrueBB, CB.FalseBB);
1650 SDValue True = DAG.getConstant(1, Cond.getValueType());
1651 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1654 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1655 MVT::Other, getControlRoot(), Cond,
1656 DAG.getBasicBlock(CB.TrueBB));
1658 // Insert the false branch. Do this even if it's a fall through branch,
1659 // this makes it easier to do DAG optimizations which require inverting
1660 // the branch condition.
1661 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1662 DAG.getBasicBlock(CB.FalseBB));
1664 DAG.setRoot(BrCond);
1667 /// visitJumpTable - Emit JumpTable node in the current MBB
1668 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1669 // Emit the code for the jump table
1670 assert(JT.Reg != -1U && "Should lower JT Header first!");
1671 EVT PTy = TLI.getPointerTy();
1672 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1674 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1675 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1676 MVT::Other, Index.getValue(1),
1678 DAG.setRoot(BrJumpTable);
1681 /// visitJumpTableHeader - This function emits necessary code to produce index
1682 /// in the JumpTable from switch case.
1683 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1684 JumpTableHeader &JTH,
1685 MachineBasicBlock *SwitchBB) {
1686 // Subtract the lowest switch case value from the value being switched on and
1687 // conditional branch to default mbb if the result is greater than the
1688 // difference between smallest and largest cases.
1689 SDValue SwitchOp = getValue(JTH.SValue);
1690 EVT VT = SwitchOp.getValueType();
1691 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1692 DAG.getConstant(JTH.First, VT));
1694 // The SDNode we just created, which holds the value being switched on minus
1695 // the smallest case value, needs to be copied to a virtual register so it
1696 // can be used as an index into the jump table in a subsequent basic block.
1697 // This value may be smaller or larger than the target's pointer type, and
1698 // therefore require extension or truncating.
1699 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1701 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1702 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1703 JumpTableReg, SwitchOp);
1704 JT.Reg = JumpTableReg;
1706 // Emit the range check for the jump table, and branch to the default block
1707 // for the switch statement if the value being switched on exceeds the largest
1708 // case in the switch.
1709 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1710 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1711 DAG.getConstant(JTH.Last-JTH.First,VT),
1714 // Set NextBlock to be the MBB immediately after the current one, if any.
1715 // This is used to avoid emitting unnecessary branches to the next block.
1716 MachineBasicBlock *NextBlock = 0;
1717 MachineFunction::iterator BBI = SwitchBB;
1719 if (++BBI != FuncInfo.MF->end())
1722 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1723 MVT::Other, CopyTo, CMP,
1724 DAG.getBasicBlock(JT.Default));
1726 if (JT.MBB != NextBlock)
1727 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1728 DAG.getBasicBlock(JT.MBB));
1730 DAG.setRoot(BrCond);
1733 /// visitBitTestHeader - This function emits necessary code to produce value
1734 /// suitable for "bit tests"
1735 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1736 MachineBasicBlock *SwitchBB) {
1737 // Subtract the minimum value
1738 SDValue SwitchOp = getValue(B.SValue);
1739 EVT VT = SwitchOp.getValueType();
1740 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1741 DAG.getConstant(B.First, VT));
1744 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1745 TLI.getSetCCResultType(Sub.getValueType()),
1746 Sub, DAG.getConstant(B.Range, VT),
1749 // Determine the type of the test operands.
1750 bool UsePtrType = false;
1751 if (!TLI.isTypeLegal(VT))
1754 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1755 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1756 // Switch table case range are encoded into series of masks.
1757 // Just use pointer type, it's guaranteed to fit.
1763 VT = TLI.getPointerTy();
1764 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1767 B.RegVT = VT.getSimpleVT();
1768 B.Reg = FuncInfo.CreateReg(B.RegVT);
1769 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1772 // Set NextBlock to be the MBB immediately after the current one, if any.
1773 // This is used to avoid emitting unnecessary branches to the next block.
1774 MachineBasicBlock *NextBlock = 0;
1775 MachineFunction::iterator BBI = SwitchBB;
1776 if (++BBI != FuncInfo.MF->end())
1779 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1781 addSuccessorWithWeight(SwitchBB, B.Default);
1782 addSuccessorWithWeight(SwitchBB, MBB);
1784 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1785 MVT::Other, CopyTo, RangeCmp,
1786 DAG.getBasicBlock(B.Default));
1788 if (MBB != NextBlock)
1789 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1790 DAG.getBasicBlock(MBB));
1792 DAG.setRoot(BrRange);
1795 /// visitBitTestCase - this function produces one "bit test"
1796 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1797 MachineBasicBlock* NextMBB,
1798 uint32_t BranchWeightToNext,
1801 MachineBasicBlock *SwitchBB) {
1803 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1806 unsigned PopCount = CountPopulation_64(B.Mask);
1807 if (PopCount == 1) {
1808 // Testing for a single bit; just compare the shift count with what it
1809 // would need to be to shift a 1 bit in that position.
1810 Cmp = DAG.getSetCC(getCurDebugLoc(),
1811 TLI.getSetCCResultType(VT),
1813 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1815 } else if (PopCount == BB.Range) {
1816 // There is only one zero bit in the range, test for it directly.
1817 Cmp = DAG.getSetCC(getCurDebugLoc(),
1818 TLI.getSetCCResultType(VT),
1820 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1823 // Make desired shift
1824 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1825 DAG.getConstant(1, VT), ShiftOp);
1827 // Emit bit tests and jumps
1828 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1829 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1830 Cmp = DAG.getSetCC(getCurDebugLoc(),
1831 TLI.getSetCCResultType(VT),
1832 AndOp, DAG.getConstant(0, VT),
1836 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1837 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1838 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1839 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1841 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1842 MVT::Other, getControlRoot(),
1843 Cmp, DAG.getBasicBlock(B.TargetBB));
1845 // Set NextBlock to be the MBB immediately after the current one, if any.
1846 // This is used to avoid emitting unnecessary branches to the next block.
1847 MachineBasicBlock *NextBlock = 0;
1848 MachineFunction::iterator BBI = SwitchBB;
1849 if (++BBI != FuncInfo.MF->end())
1852 if (NextMBB != NextBlock)
1853 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1854 DAG.getBasicBlock(NextMBB));
1859 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1860 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1862 // Retrieve successors.
1863 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1864 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1866 const Value *Callee(I.getCalledValue());
1867 const Function *Fn = dyn_cast<Function>(Callee);
1868 if (isa<InlineAsm>(Callee))
1870 else if (Fn && Fn->isIntrinsic()) {
1871 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
1872 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1874 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1876 // If the value of the invoke is used outside of its defining block, make it
1877 // available as a virtual register.
1878 CopyToExportRegsIfNeeded(&I);
1880 // Update successor info
1881 addSuccessorWithWeight(InvokeMBB, Return);
1882 addSuccessorWithWeight(InvokeMBB, LandingPad);
1884 // Drop into normal successor.
1885 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1886 MVT::Other, getControlRoot(),
1887 DAG.getBasicBlock(Return)));
1890 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1891 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1894 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1895 assert(FuncInfo.MBB->isLandingPad() &&
1896 "Call to landingpad not in landing pad!");
1898 MachineBasicBlock *MBB = FuncInfo.MBB;
1899 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1900 AddLandingPadInfo(LP, MMI, MBB);
1902 // If there aren't registers to copy the values into (e.g., during SjLj
1903 // exceptions), then don't bother to create these DAG nodes.
1904 if (TLI.getExceptionPointerRegister() == 0 &&
1905 TLI.getExceptionSelectorRegister() == 0)
1908 SmallVector<EVT, 2> ValueVTs;
1909 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1911 // Insert the EXCEPTIONADDR instruction.
1912 assert(FuncInfo.MBB->isLandingPad() &&
1913 "Call to eh.exception not in landing pad!");
1914 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1916 Ops[0] = DAG.getRoot();
1917 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
1918 SDValue Chain = Op1.getValue(1);
1920 // Insert the EHSELECTION instruction.
1921 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1924 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
1925 Chain = Op2.getValue(1);
1926 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
1930 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
1931 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1934 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1935 setValue(&LP, RetPair.first);
1936 DAG.setRoot(RetPair.second);
1939 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1940 /// small case ranges).
1941 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1942 CaseRecVector& WorkList,
1944 MachineBasicBlock *Default,
1945 MachineBasicBlock *SwitchBB) {
1946 // Size is the number of Cases represented by this range.
1947 size_t Size = CR.Range.second - CR.Range.first;
1951 // Get the MachineFunction which holds the current MBB. This is used when
1952 // inserting any additional MBBs necessary to represent the switch.
1953 MachineFunction *CurMF = FuncInfo.MF;
1955 // Figure out which block is immediately after the current one.
1956 MachineBasicBlock *NextBlock = 0;
1957 MachineFunction::iterator BBI = CR.CaseBB;
1959 if (++BBI != FuncInfo.MF->end())
1962 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1963 // If any two of the cases has the same destination, and if one value
1964 // is the same as the other, but has one bit unset that the other has set,
1965 // use bit manipulation to do two compares at once. For example:
1966 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1967 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1968 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1969 if (Size == 2 && CR.CaseBB == SwitchBB) {
1970 Case &Small = *CR.Range.first;
1971 Case &Big = *(CR.Range.second-1);
1973 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1974 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1975 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1977 // Check that there is only one bit different.
1978 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1979 (SmallValue | BigValue) == BigValue) {
1980 // Isolate the common bit.
1981 APInt CommonBit = BigValue & ~SmallValue;
1982 assert((SmallValue | CommonBit) == BigValue &&
1983 CommonBit.countPopulation() == 1 && "Not a common bit?");
1985 SDValue CondLHS = getValue(SV);
1986 EVT VT = CondLHS.getValueType();
1987 DebugLoc DL = getCurDebugLoc();
1989 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1990 DAG.getConstant(CommonBit, VT));
1991 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1992 Or, DAG.getConstant(BigValue, VT),
1995 // Update successor info.
1996 // Both Small and Big will jump to Small.BB, so we sum up the weights.
1997 addSuccessorWithWeight(SwitchBB, Small.BB,
1998 Small.ExtraWeight + Big.ExtraWeight);
1999 addSuccessorWithWeight(SwitchBB, Default,
2000 // The default destination is the first successor in IR.
2001 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2003 // Insert the true branch.
2004 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2005 getControlRoot(), Cond,
2006 DAG.getBasicBlock(Small.BB));
2008 // Insert the false branch.
2009 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2010 DAG.getBasicBlock(Default));
2012 DAG.setRoot(BrCond);
2018 // Order cases by weight so the most likely case will be checked first.
2019 uint32_t UnhandledWeights = 0;
2021 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2022 uint32_t IWeight = I->ExtraWeight;
2023 UnhandledWeights += IWeight;
2024 for (CaseItr J = CR.Range.first; J < I; ++J) {
2025 uint32_t JWeight = J->ExtraWeight;
2026 if (IWeight > JWeight)
2031 // Rearrange the case blocks so that the last one falls through if possible.
2032 Case &BackCase = *(CR.Range.second-1);
2034 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2035 // The last case block won't fall through into 'NextBlock' if we emit the
2036 // branches in this order. See if rearranging a case value would help.
2037 // We start at the bottom as it's the case with the least weight.
2038 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){
2039 if (I->BB == NextBlock) {
2040 std::swap(*I, BackCase);
2046 // Create a CaseBlock record representing a conditional branch to
2047 // the Case's target mbb if the value being switched on SV is equal
2049 MachineBasicBlock *CurBlock = CR.CaseBB;
2050 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2051 MachineBasicBlock *FallThrough;
2053 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2054 CurMF->insert(BBI, FallThrough);
2056 // Put SV in a virtual register to make it available from the new blocks.
2057 ExportFromCurrentBlock(SV);
2059 // If the last case doesn't match, go to the default block.
2060 FallThrough = Default;
2063 const Value *RHS, *LHS, *MHS;
2065 if (I->High == I->Low) {
2066 // This is just small small case range :) containing exactly 1 case
2068 LHS = SV; RHS = I->High; MHS = NULL;
2070 CC = ISD::SETCC_INVALID;
2071 LHS = I->Low; MHS = SV; RHS = I->High;
2074 // The false weight should be sum of all un-handled cases.
2075 UnhandledWeights -= I->ExtraWeight;
2076 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2078 /* trueweight */ I->ExtraWeight,
2079 /* falseweight */ UnhandledWeights);
2081 // If emitting the first comparison, just call visitSwitchCase to emit the
2082 // code into the current block. Otherwise, push the CaseBlock onto the
2083 // vector to be later processed by SDISel, and insert the node's MBB
2084 // before the next MBB.
2085 if (CurBlock == SwitchBB)
2086 visitSwitchCase(CB, SwitchBB);
2088 SwitchCases.push_back(CB);
2090 CurBlock = FallThrough;
2096 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2097 return TLI.supportJumpTables() &&
2098 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2099 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2102 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2103 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2104 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth);
2105 return (LastExt - FirstExt + 1ULL);
2108 /// handleJTSwitchCase - Emit jumptable for current switch case range
2109 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2110 CaseRecVector &WorkList,
2112 MachineBasicBlock *Default,
2113 MachineBasicBlock *SwitchBB) {
2114 Case& FrontCase = *CR.Range.first;
2115 Case& BackCase = *(CR.Range.second-1);
2117 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2118 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2120 APInt TSize(First.getBitWidth(), 0);
2121 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2124 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2127 APInt Range = ComputeRange(First, Last);
2128 // The density is TSize / Range. Require at least 40%.
2129 // It should not be possible for IntTSize to saturate for sane code, but make
2130 // sure we handle Range saturation correctly.
2131 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2132 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2133 if (IntTSize * 10 < IntRange * 4)
2136 DEBUG(dbgs() << "Lowering jump table\n"
2137 << "First entry: " << First << ". Last entry: " << Last << '\n'
2138 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2140 // Get the MachineFunction which holds the current MBB. This is used when
2141 // inserting any additional MBBs necessary to represent the switch.
2142 MachineFunction *CurMF = FuncInfo.MF;
2144 // Figure out which block is immediately after the current one.
2145 MachineFunction::iterator BBI = CR.CaseBB;
2148 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2150 // Create a new basic block to hold the code for loading the address
2151 // of the jump table, and jumping to it. Update successor information;
2152 // we will either branch to the default case for the switch, or the jump
2154 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2155 CurMF->insert(BBI, JumpTableBB);
2157 addSuccessorWithWeight(CR.CaseBB, Default);
2158 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2160 // Build a vector of destination BBs, corresponding to each target
2161 // of the jump table. If the value of the jump table slot corresponds to
2162 // a case statement, push the case's BB onto the vector, otherwise, push
2164 std::vector<MachineBasicBlock*> DestBBs;
2166 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2167 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2168 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2170 if (Low.ule(TEI) && TEI.ule(High)) {
2171 DestBBs.push_back(I->BB);
2175 DestBBs.push_back(Default);
2179 // Calculate weight for each unique destination in CR.
2180 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2182 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2183 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2184 DestWeights.find(I->BB);
2185 if (Itr != DestWeights.end())
2186 Itr->second += I->ExtraWeight;
2188 DestWeights[I->BB] = I->ExtraWeight;
2191 // Update successor info. Add one edge to each unique successor.
2192 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2193 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2194 E = DestBBs.end(); I != E; ++I) {
2195 if (!SuccsHandled[(*I)->getNumber()]) {
2196 SuccsHandled[(*I)->getNumber()] = true;
2197 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2198 DestWeights.find(*I);
2199 addSuccessorWithWeight(JumpTableBB, *I,
2200 Itr != DestWeights.end() ? Itr->second : 0);
2204 // Create a jump table index for this jump table.
2205 unsigned JTEncoding = TLI.getJumpTableEncoding();
2206 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2207 ->createJumpTableIndex(DestBBs);
2209 // Set the jump table information so that we can codegen it as a second
2210 // MachineBasicBlock
2211 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2212 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2213 if (CR.CaseBB == SwitchBB)
2214 visitJumpTableHeader(JT, JTH, SwitchBB);
2216 JTCases.push_back(JumpTableBlock(JTH, JT));
2220 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2222 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2223 CaseRecVector& WorkList,
2225 MachineBasicBlock *Default,
2226 MachineBasicBlock *SwitchBB) {
2227 // Get the MachineFunction which holds the current MBB. This is used when
2228 // inserting any additional MBBs necessary to represent the switch.
2229 MachineFunction *CurMF = FuncInfo.MF;
2231 // Figure out which block is immediately after the current one.
2232 MachineFunction::iterator BBI = CR.CaseBB;
2235 Case& FrontCase = *CR.Range.first;
2236 Case& BackCase = *(CR.Range.second-1);
2237 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2239 // Size is the number of Cases represented by this range.
2240 unsigned Size = CR.Range.second - CR.Range.first;
2242 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2243 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2245 CaseItr Pivot = CR.Range.first + Size/2;
2247 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2248 // (heuristically) allow us to emit JumpTable's later.
2249 APInt TSize(First.getBitWidth(), 0);
2250 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2254 APInt LSize = FrontCase.size();
2255 APInt RSize = TSize-LSize;
2256 DEBUG(dbgs() << "Selecting best pivot: \n"
2257 << "First: " << First << ", Last: " << Last <<'\n'
2258 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2259 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2261 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2262 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2263 APInt Range = ComputeRange(LEnd, RBegin);
2264 assert((Range - 2ULL).isNonNegative() &&
2265 "Invalid case distance");
2266 // Use volatile double here to avoid excess precision issues on some hosts,
2267 // e.g. that use 80-bit X87 registers.
2268 volatile double LDensity =
2269 (double)LSize.roundToDouble() /
2270 (LEnd - First + 1ULL).roundToDouble();
2271 volatile double RDensity =
2272 (double)RSize.roundToDouble() /
2273 (Last - RBegin + 1ULL).roundToDouble();
2274 double Metric = Range.logBase2()*(LDensity+RDensity);
2275 // Should always split in some non-trivial place
2276 DEBUG(dbgs() <<"=>Step\n"
2277 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2278 << "LDensity: " << LDensity
2279 << ", RDensity: " << RDensity << '\n'
2280 << "Metric: " << Metric << '\n');
2281 if (FMetric < Metric) {
2284 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2290 if (areJTsAllowed(TLI)) {
2291 // If our case is dense we *really* should handle it earlier!
2292 assert((FMetric > 0) && "Should handle dense range earlier!");
2294 Pivot = CR.Range.first + Size/2;
2297 CaseRange LHSR(CR.Range.first, Pivot);
2298 CaseRange RHSR(Pivot, CR.Range.second);
2299 const Constant *C = Pivot->Low;
2300 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2302 // We know that we branch to the LHS if the Value being switched on is
2303 // less than the Pivot value, C. We use this to optimize our binary
2304 // tree a bit, by recognizing that if SV is greater than or equal to the
2305 // LHS's Case Value, and that Case Value is exactly one less than the
2306 // Pivot's Value, then we can branch directly to the LHS's Target,
2307 // rather than creating a leaf node for it.
2308 if ((LHSR.second - LHSR.first) == 1 &&
2309 LHSR.first->High == CR.GE &&
2310 cast<ConstantInt>(C)->getValue() ==
2311 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2312 TrueBB = LHSR.first->BB;
2314 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2315 CurMF->insert(BBI, TrueBB);
2316 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2318 // Put SV in a virtual register to make it available from the new blocks.
2319 ExportFromCurrentBlock(SV);
2322 // Similar to the optimization above, if the Value being switched on is
2323 // known to be less than the Constant CR.LT, and the current Case Value
2324 // is CR.LT - 1, then we can branch directly to the target block for
2325 // the current Case Value, rather than emitting a RHS leaf node for it.
2326 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2327 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2328 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2329 FalseBB = RHSR.first->BB;
2331 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2332 CurMF->insert(BBI, FalseBB);
2333 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2335 // Put SV in a virtual register to make it available from the new blocks.
2336 ExportFromCurrentBlock(SV);
2339 // Create a CaseBlock record representing a conditional branch to
2340 // the LHS node if the value being switched on SV is less than C.
2341 // Otherwise, branch to LHS.
2342 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2344 if (CR.CaseBB == SwitchBB)
2345 visitSwitchCase(CB, SwitchBB);
2347 SwitchCases.push_back(CB);
2352 /// handleBitTestsSwitchCase - if current case range has few destination and
2353 /// range span less, than machine word bitwidth, encode case range into series
2354 /// of masks and emit bit tests with these masks.
2355 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2356 CaseRecVector& WorkList,
2358 MachineBasicBlock* Default,
2359 MachineBasicBlock *SwitchBB){
2360 EVT PTy = TLI.getPointerTy();
2361 unsigned IntPtrBits = PTy.getSizeInBits();
2363 Case& FrontCase = *CR.Range.first;
2364 Case& BackCase = *(CR.Range.second-1);
2366 // Get the MachineFunction which holds the current MBB. This is used when
2367 // inserting any additional MBBs necessary to represent the switch.
2368 MachineFunction *CurMF = FuncInfo.MF;
2370 // If target does not have legal shift left, do not emit bit tests at all.
2371 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2375 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2377 // Single case counts one, case range - two.
2378 numCmps += (I->Low == I->High ? 1 : 2);
2381 // Count unique destinations
2382 SmallSet<MachineBasicBlock*, 4> Dests;
2383 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2384 Dests.insert(I->BB);
2385 if (Dests.size() > 3)
2386 // Don't bother the code below, if there are too much unique destinations
2389 DEBUG(dbgs() << "Total number of unique destinations: "
2390 << Dests.size() << '\n'
2391 << "Total number of comparisons: " << numCmps << '\n');
2393 // Compute span of values.
2394 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2395 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2396 APInt cmpRange = maxValue - minValue;
2398 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2399 << "Low bound: " << minValue << '\n'
2400 << "High bound: " << maxValue << '\n');
2402 if (cmpRange.uge(IntPtrBits) ||
2403 (!(Dests.size() == 1 && numCmps >= 3) &&
2404 !(Dests.size() == 2 && numCmps >= 5) &&
2405 !(Dests.size() >= 3 && numCmps >= 6)))
2408 DEBUG(dbgs() << "Emitting bit tests\n");
2409 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2411 // Optimize the case where all the case values fit in a
2412 // word without having to subtract minValue. In this case,
2413 // we can optimize away the subtraction.
2414 if (maxValue.ult(IntPtrBits)) {
2415 cmpRange = maxValue;
2417 lowBound = minValue;
2420 CaseBitsVector CasesBits;
2421 unsigned i, count = 0;
2423 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2424 MachineBasicBlock* Dest = I->BB;
2425 for (i = 0; i < count; ++i)
2426 if (Dest == CasesBits[i].BB)
2430 assert((count < 3) && "Too much destinations to test!");
2431 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2435 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2436 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2438 uint64_t lo = (lowValue - lowBound).getZExtValue();
2439 uint64_t hi = (highValue - lowBound).getZExtValue();
2440 CasesBits[i].ExtraWeight += I->ExtraWeight;
2442 for (uint64_t j = lo; j <= hi; j++) {
2443 CasesBits[i].Mask |= 1ULL << j;
2444 CasesBits[i].Bits++;
2448 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2452 // Figure out which block is immediately after the current one.
2453 MachineFunction::iterator BBI = CR.CaseBB;
2456 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2458 DEBUG(dbgs() << "Cases:\n");
2459 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2460 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2461 << ", Bits: " << CasesBits[i].Bits
2462 << ", BB: " << CasesBits[i].BB << '\n');
2464 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2465 CurMF->insert(BBI, CaseBB);
2466 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2468 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2470 // Put SV in a virtual register to make it available from the new blocks.
2471 ExportFromCurrentBlock(SV);
2474 BitTestBlock BTB(lowBound, cmpRange, SV,
2475 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2476 CR.CaseBB, Default, BTC);
2478 if (CR.CaseBB == SwitchBB)
2479 visitBitTestHeader(BTB, SwitchBB);
2481 BitTestCases.push_back(BTB);
2486 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2487 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2488 const SwitchInst& SI) {
2490 /// Use a shorter form of declaration, and also
2491 /// show the we want to use CRSBuilder as Clusterifier.
2492 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier;
2494 Clusterifier TheClusterifier;
2496 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2497 // Start with "simple" cases
2498 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2500 const BasicBlock *SuccBB = i.getCaseSuccessor();
2501 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2503 TheClusterifier.add(i.getCaseValueEx(), SMBB,
2504 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0);
2507 TheClusterifier.optimize();
2510 for (Clusterifier::RangeIterator i = TheClusterifier.begin(),
2511 e = TheClusterifier.end(); i != e; ++i, ++numCmps) {
2512 Clusterifier::Cluster &C = *i;
2513 // Update edge weight for the cluster.
2514 unsigned W = C.first.Weight;
2516 // FIXME: Currently work with ConstantInt based numbers.
2517 // Changing it to APInt based is a pretty heavy for this commit.
2518 Cases.push_back(Case(C.first.getLow().toConstantInt(),
2519 C.first.getHigh().toConstantInt(), C.second, W));
2521 if (C.first.getLow() != C.first.getHigh())
2522 // A range counts double, since it requires two compares.
2529 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2530 MachineBasicBlock *Last) {
2532 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2533 if (JTCases[i].first.HeaderBB == First)
2534 JTCases[i].first.HeaderBB = Last;
2536 // Update BitTestCases.
2537 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2538 if (BitTestCases[i].Parent == First)
2539 BitTestCases[i].Parent = Last;
2542 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2543 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2545 // Figure out which block is immediately after the current one.
2546 MachineBasicBlock *NextBlock = 0;
2547 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2549 // If there is only the default destination, branch to it if it is not the
2550 // next basic block. Otherwise, just fall through.
2551 if (!SI.getNumCases()) {
2552 // Update machine-CFG edges.
2554 // If this is not a fall-through branch, emit the branch.
2555 SwitchMBB->addSuccessor(Default);
2556 if (Default != NextBlock)
2557 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2558 MVT::Other, getControlRoot(),
2559 DAG.getBasicBlock(Default)));
2564 // If there are any non-default case statements, create a vector of Cases
2565 // representing each one, and sort the vector so that we can efficiently
2566 // create a binary search tree from them.
2568 size_t numCmps = Clusterify(Cases, SI);
2569 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2570 << ". Total compares: " << numCmps << '\n');
2573 // Get the Value to be switched on and default basic blocks, which will be
2574 // inserted into CaseBlock records, representing basic blocks in the binary
2576 const Value *SV = SI.getCondition();
2578 // Push the initial CaseRec onto the worklist
2579 CaseRecVector WorkList;
2580 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2581 CaseRange(Cases.begin(),Cases.end())));
2583 while (!WorkList.empty()) {
2584 // Grab a record representing a case range to process off the worklist
2585 CaseRec CR = WorkList.back();
2586 WorkList.pop_back();
2588 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2591 // If the range has few cases (two or less) emit a series of specific
2593 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2596 // If the switch has more than N blocks, and is at least 40% dense, and the
2597 // target supports indirect branches, then emit a jump table rather than
2598 // lowering the switch to a binary tree of conditional branches.
2599 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2600 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2603 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2604 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2605 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2609 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2610 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2612 // Update machine-CFG edges with unique successors.
2613 SmallSet<BasicBlock*, 32> Done;
2614 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2615 BasicBlock *BB = I.getSuccessor(i);
2616 bool Inserted = Done.insert(BB);
2620 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2621 addSuccessorWithWeight(IndirectBrMBB, Succ);
2624 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2625 MVT::Other, getControlRoot(),
2626 getValue(I.getAddress())));
2629 void SelectionDAGBuilder::visitFSub(const User &I) {
2630 // -0.0 - X --> fneg
2631 Type *Ty = I.getType();
2632 if (isa<Constant>(I.getOperand(0)) &&
2633 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2634 SDValue Op2 = getValue(I.getOperand(1));
2635 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2636 Op2.getValueType(), Op2));
2640 visitBinary(I, ISD::FSUB);
2643 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2644 SDValue Op1 = getValue(I.getOperand(0));
2645 SDValue Op2 = getValue(I.getOperand(1));
2646 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2647 Op1.getValueType(), Op1, Op2));
2650 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2651 SDValue Op1 = getValue(I.getOperand(0));
2652 SDValue Op2 = getValue(I.getOperand(1));
2654 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2656 // Coerce the shift amount to the right type if we can.
2657 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2658 unsigned ShiftSize = ShiftTy.getSizeInBits();
2659 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2660 DebugLoc DL = getCurDebugLoc();
2662 // If the operand is smaller than the shift count type, promote it.
2663 if (ShiftSize > Op2Size)
2664 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2666 // If the operand is larger than the shift count type but the shift
2667 // count type has enough bits to represent any shift value, truncate
2668 // it now. This is a common case and it exposes the truncate to
2669 // optimization early.
2670 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2671 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2672 // Otherwise we'll need to temporarily settle for some other convenient
2673 // type. Type legalization will make adjustments once the shiftee is split.
2675 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2678 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2679 Op1.getValueType(), Op1, Op2));
2682 void SelectionDAGBuilder::visitSDiv(const User &I) {
2683 SDValue Op1 = getValue(I.getOperand(0));
2684 SDValue Op2 = getValue(I.getOperand(1));
2686 // Turn exact SDivs into multiplications.
2687 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2689 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2690 !isa<ConstantSDNode>(Op1) &&
2691 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2692 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2694 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2698 void SelectionDAGBuilder::visitICmp(const User &I) {
2699 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2700 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2701 predicate = IC->getPredicate();
2702 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2703 predicate = ICmpInst::Predicate(IC->getPredicate());
2704 SDValue Op1 = getValue(I.getOperand(0));
2705 SDValue Op2 = getValue(I.getOperand(1));
2706 ISD::CondCode Opcode = getICmpCondCode(predicate);
2708 EVT DestVT = TLI.getValueType(I.getType());
2709 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2712 void SelectionDAGBuilder::visitFCmp(const User &I) {
2713 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2714 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2715 predicate = FC->getPredicate();
2716 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2717 predicate = FCmpInst::Predicate(FC->getPredicate());
2718 SDValue Op1 = getValue(I.getOperand(0));
2719 SDValue Op2 = getValue(I.getOperand(1));
2720 ISD::CondCode Condition = getFCmpCondCode(predicate);
2721 if (TM.Options.NoNaNsFPMath)
2722 Condition = getFCmpCodeWithoutNaN(Condition);
2723 EVT DestVT = TLI.getValueType(I.getType());
2724 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2727 void SelectionDAGBuilder::visitSelect(const User &I) {
2728 SmallVector<EVT, 4> ValueVTs;
2729 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2730 unsigned NumValues = ValueVTs.size();
2731 if (NumValues == 0) return;
2733 SmallVector<SDValue, 4> Values(NumValues);
2734 SDValue Cond = getValue(I.getOperand(0));
2735 SDValue TrueVal = getValue(I.getOperand(1));
2736 SDValue FalseVal = getValue(I.getOperand(2));
2737 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2738 ISD::VSELECT : ISD::SELECT;
2740 for (unsigned i = 0; i != NumValues; ++i)
2741 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
2742 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2744 SDValue(TrueVal.getNode(),
2745 TrueVal.getResNo() + i),
2746 SDValue(FalseVal.getNode(),
2747 FalseVal.getResNo() + i));
2749 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2750 DAG.getVTList(&ValueVTs[0], NumValues),
2751 &Values[0], NumValues));
2754 void SelectionDAGBuilder::visitTrunc(const User &I) {
2755 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2756 SDValue N = getValue(I.getOperand(0));
2757 EVT DestVT = TLI.getValueType(I.getType());
2758 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2761 void SelectionDAGBuilder::visitZExt(const User &I) {
2762 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2763 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2764 SDValue N = getValue(I.getOperand(0));
2765 EVT DestVT = TLI.getValueType(I.getType());
2766 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2769 void SelectionDAGBuilder::visitSExt(const User &I) {
2770 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2771 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2772 SDValue N = getValue(I.getOperand(0));
2773 EVT DestVT = TLI.getValueType(I.getType());
2774 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2777 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2778 // FPTrunc is never a no-op cast, no need to check
2779 SDValue N = getValue(I.getOperand(0));
2780 EVT DestVT = TLI.getValueType(I.getType());
2781 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2783 DAG.getTargetConstant(0, TLI.getPointerTy())));
2786 void SelectionDAGBuilder::visitFPExt(const User &I){
2787 // FPExt is never a no-op cast, no need to check
2788 SDValue N = getValue(I.getOperand(0));
2789 EVT DestVT = TLI.getValueType(I.getType());
2790 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2793 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2794 // FPToUI is never a no-op cast, no need to check
2795 SDValue N = getValue(I.getOperand(0));
2796 EVT DestVT = TLI.getValueType(I.getType());
2797 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2800 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2801 // FPToSI is never a no-op cast, no need to check
2802 SDValue N = getValue(I.getOperand(0));
2803 EVT DestVT = TLI.getValueType(I.getType());
2804 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2807 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2808 // UIToFP is never a no-op cast, no need to check
2809 SDValue N = getValue(I.getOperand(0));
2810 EVT DestVT = TLI.getValueType(I.getType());
2811 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2814 void SelectionDAGBuilder::visitSIToFP(const User &I){
2815 // SIToFP is never a no-op cast, no need to check
2816 SDValue N = getValue(I.getOperand(0));
2817 EVT DestVT = TLI.getValueType(I.getType());
2818 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2821 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2822 // What to do depends on the size of the integer and the size of the pointer.
2823 // We can either truncate, zero extend, or no-op, accordingly.
2824 SDValue N = getValue(I.getOperand(0));
2825 EVT DestVT = TLI.getValueType(I.getType());
2826 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2829 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2830 // What to do depends on the size of the integer and the size of the pointer.
2831 // We can either truncate, zero extend, or no-op, accordingly.
2832 SDValue N = getValue(I.getOperand(0));
2833 EVT DestVT = TLI.getValueType(I.getType());
2834 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2837 void SelectionDAGBuilder::visitBitCast(const User &I) {
2838 SDValue N = getValue(I.getOperand(0));
2839 EVT DestVT = TLI.getValueType(I.getType());
2841 // BitCast assures us that source and destination are the same size so this is
2842 // either a BITCAST or a no-op.
2843 if (DestVT != N.getValueType())
2844 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2845 DestVT, N)); // convert types.
2847 setValue(&I, N); // noop cast.
2850 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2851 SDValue InVec = getValue(I.getOperand(0));
2852 SDValue InVal = getValue(I.getOperand(1));
2853 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2855 getValue(I.getOperand(2)));
2856 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2857 TLI.getValueType(I.getType()),
2858 InVec, InVal, InIdx));
2861 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2862 SDValue InVec = getValue(I.getOperand(0));
2863 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2865 getValue(I.getOperand(1)));
2866 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2867 TLI.getValueType(I.getType()), InVec, InIdx));
2870 // Utility for visitShuffleVector - Return true if every element in Mask,
2871 // beginning from position Pos and ending in Pos+Size, falls within the
2872 // specified sequential range [L, L+Pos). or is undef.
2873 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2874 unsigned Pos, unsigned Size, int Low) {
2875 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2876 if (Mask[i] >= 0 && Mask[i] != Low)
2881 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2882 SDValue Src1 = getValue(I.getOperand(0));
2883 SDValue Src2 = getValue(I.getOperand(1));
2885 SmallVector<int, 8> Mask;
2886 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2887 unsigned MaskNumElts = Mask.size();
2889 EVT VT = TLI.getValueType(I.getType());
2890 EVT SrcVT = Src1.getValueType();
2891 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2893 if (SrcNumElts == MaskNumElts) {
2894 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2899 // Normalize the shuffle vector since mask and vector length don't match.
2900 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2901 // Mask is longer than the source vectors and is a multiple of the source
2902 // vectors. We can use concatenate vector to make the mask and vectors
2904 if (SrcNumElts*2 == MaskNumElts) {
2905 // First check for Src1 in low and Src2 in high
2906 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2907 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2908 // The shuffle is concatenating two vectors together.
2909 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2913 // Then check for Src2 in low and Src1 in high
2914 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2915 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2916 // The shuffle is concatenating two vectors together.
2917 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2923 // Pad both vectors with undefs to make them the same length as the mask.
2924 unsigned NumConcat = MaskNumElts / SrcNumElts;
2925 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2926 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2927 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2929 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2930 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2934 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2935 getCurDebugLoc(), VT,
2936 &MOps1[0], NumConcat);
2937 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2938 getCurDebugLoc(), VT,
2939 &MOps2[0], NumConcat);
2941 // Readjust mask for new input vector length.
2942 SmallVector<int, 8> MappedOps;
2943 for (unsigned i = 0; i != MaskNumElts; ++i) {
2945 if (Idx >= (int)SrcNumElts)
2946 Idx -= SrcNumElts - MaskNumElts;
2947 MappedOps.push_back(Idx);
2950 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2955 if (SrcNumElts > MaskNumElts) {
2956 // Analyze the access pattern of the vector to see if we can extract
2957 // two subvectors and do the shuffle. The analysis is done by calculating
2958 // the range of elements the mask access on both vectors.
2959 int MinRange[2] = { static_cast<int>(SrcNumElts),
2960 static_cast<int>(SrcNumElts)};
2961 int MaxRange[2] = {-1, -1};
2963 for (unsigned i = 0; i != MaskNumElts; ++i) {
2969 if (Idx >= (int)SrcNumElts) {
2973 if (Idx > MaxRange[Input])
2974 MaxRange[Input] = Idx;
2975 if (Idx < MinRange[Input])
2976 MinRange[Input] = Idx;
2979 // Check if the access is smaller than the vector size and can we find
2980 // a reasonable extract index.
2981 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2983 int StartIdx[2]; // StartIdx to extract from
2984 for (unsigned Input = 0; Input < 2; ++Input) {
2985 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2986 RangeUse[Input] = 0; // Unused
2987 StartIdx[Input] = 0;
2991 // Find a good start index that is a multiple of the mask length. Then
2992 // see if the rest of the elements are in range.
2993 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2994 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2995 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2996 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2999 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3000 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3003 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3004 // Extract appropriate subvector and generate a vector shuffle
3005 for (unsigned Input = 0; Input < 2; ++Input) {
3006 SDValue &Src = Input == 0 ? Src1 : Src2;
3007 if (RangeUse[Input] == 0)
3008 Src = DAG.getUNDEF(VT);
3010 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
3011 Src, DAG.getIntPtrConstant(StartIdx[Input]));
3014 // Calculate new mask.
3015 SmallVector<int, 8> MappedOps;
3016 for (unsigned i = 0; i != MaskNumElts; ++i) {
3019 if (Idx < (int)SrcNumElts)
3022 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3024 MappedOps.push_back(Idx);
3027 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
3033 // We can't use either concat vectors or extract subvectors so fall back to
3034 // replacing the shuffle with extract and build vector.
3035 // to insert and build vector.
3036 EVT EltVT = VT.getVectorElementType();
3037 EVT PtrVT = TLI.getPointerTy();
3038 SmallVector<SDValue,8> Ops;
3039 for (unsigned i = 0; i != MaskNumElts; ++i) {
3044 Res = DAG.getUNDEF(EltVT);
3046 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3047 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3049 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
3050 EltVT, Src, DAG.getConstant(Idx, PtrVT));
3056 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
3057 VT, &Ops[0], Ops.size()));
3060 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3061 const Value *Op0 = I.getOperand(0);
3062 const Value *Op1 = I.getOperand(1);
3063 Type *AggTy = I.getType();
3064 Type *ValTy = Op1->getType();
3065 bool IntoUndef = isa<UndefValue>(Op0);
3066 bool FromUndef = isa<UndefValue>(Op1);
3068 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3070 SmallVector<EVT, 4> AggValueVTs;
3071 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3072 SmallVector<EVT, 4> ValValueVTs;
3073 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3075 unsigned NumAggValues = AggValueVTs.size();
3076 unsigned NumValValues = ValValueVTs.size();
3077 SmallVector<SDValue, 4> Values(NumAggValues);
3079 SDValue Agg = getValue(Op0);
3081 // Copy the beginning value(s) from the original aggregate.
3082 for (; i != LinearIndex; ++i)
3083 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3084 SDValue(Agg.getNode(), Agg.getResNo() + i);
3085 // Copy values from the inserted value(s).
3087 SDValue Val = getValue(Op1);
3088 for (; i != LinearIndex + NumValValues; ++i)
3089 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3090 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3092 // Copy remaining value(s) from the original aggregate.
3093 for (; i != NumAggValues; ++i)
3094 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3095 SDValue(Agg.getNode(), Agg.getResNo() + i);
3097 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3098 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3099 &Values[0], NumAggValues));
3102 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3103 const Value *Op0 = I.getOperand(0);
3104 Type *AggTy = Op0->getType();
3105 Type *ValTy = I.getType();
3106 bool OutOfUndef = isa<UndefValue>(Op0);
3108 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3110 SmallVector<EVT, 4> ValValueVTs;
3111 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3113 unsigned NumValValues = ValValueVTs.size();
3115 // Ignore a extractvalue that produces an empty object
3116 if (!NumValValues) {
3117 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3121 SmallVector<SDValue, 4> Values(NumValValues);
3123 SDValue Agg = getValue(Op0);
3124 // Copy out the selected value(s).
3125 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3126 Values[i - LinearIndex] =
3128 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3129 SDValue(Agg.getNode(), Agg.getResNo() + i);
3131 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3132 DAG.getVTList(&ValValueVTs[0], NumValValues),
3133 &Values[0], NumValValues));
3136 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3137 SDValue N = getValue(I.getOperand(0));
3138 // Note that the pointer operand may be a vector of pointers. Take the scalar
3139 // element which holds a pointer.
3140 Type *Ty = I.getOperand(0)->getType()->getScalarType();
3142 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3144 const Value *Idx = *OI;
3145 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3146 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3149 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3150 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3151 DAG.getConstant(Offset, N.getValueType()));
3154 Ty = StTy->getElementType(Field);
3156 Ty = cast<SequentialType>(Ty)->getElementType();
3158 // If this is a constant subscript, handle it quickly.
3159 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3160 if (CI->isZero()) continue;
3162 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3164 EVT PTy = TLI.getPointerTy();
3165 unsigned PtrBits = PTy.getSizeInBits();
3167 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3169 DAG.getConstant(Offs, MVT::i64));
3171 OffsVal = DAG.getIntPtrConstant(Offs);
3173 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3178 // N = N + Idx * ElementSize;
3179 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3180 TD->getTypeAllocSize(Ty));
3181 SDValue IdxN = getValue(Idx);
3183 // If the index is smaller or larger than intptr_t, truncate or extend
3185 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3187 // If this is a multiply by a power of two, turn it into a shl
3188 // immediately. This is a very common case.
3189 if (ElementSize != 1) {
3190 if (ElementSize.isPowerOf2()) {
3191 unsigned Amt = ElementSize.logBase2();
3192 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3193 N.getValueType(), IdxN,
3194 DAG.getConstant(Amt, IdxN.getValueType()));
3196 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3197 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3198 N.getValueType(), IdxN, Scale);
3202 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3203 N.getValueType(), N, IdxN);
3210 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3211 // If this is a fixed sized alloca in the entry block of the function,
3212 // allocate it statically on the stack.
3213 if (FuncInfo.StaticAllocaMap.count(&I))
3214 return; // getValue will auto-populate this.
3216 Type *Ty = I.getAllocatedType();
3217 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3219 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3222 SDValue AllocSize = getValue(I.getArraySize());
3224 EVT IntPtr = TLI.getPointerTy();
3225 if (AllocSize.getValueType() != IntPtr)
3226 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3228 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3230 DAG.getConstant(TySize, IntPtr));
3232 // Handle alignment. If the requested alignment is less than or equal to
3233 // the stack alignment, ignore it. If the size is greater than or equal to
3234 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3235 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3236 if (Align <= StackAlign)
3239 // Round the size of the allocation up to the stack alignment size
3240 // by add SA-1 to the size.
3241 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3242 AllocSize.getValueType(), AllocSize,
3243 DAG.getIntPtrConstant(StackAlign-1));
3245 // Mask out the low bits for alignment purposes.
3246 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3247 AllocSize.getValueType(), AllocSize,
3248 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3250 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3251 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3252 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3255 DAG.setRoot(DSA.getValue(1));
3257 // Inform the Frame Information that we have just allocated a variable-sized
3259 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3262 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3264 return visitAtomicLoad(I);
3266 const Value *SV = I.getOperand(0);
3267 SDValue Ptr = getValue(SV);
3269 Type *Ty = I.getType();
3271 bool isVolatile = I.isVolatile();
3272 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3273 bool isInvariant = I.getMetadata("invariant.load") != 0;
3274 unsigned Alignment = I.getAlignment();
3275 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3276 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3278 SmallVector<EVT, 4> ValueVTs;
3279 SmallVector<uint64_t, 4> Offsets;
3280 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3281 unsigned NumValues = ValueVTs.size();
3286 bool ConstantMemory = false;
3287 if (I.isVolatile() || NumValues > MaxParallelChains)
3288 // Serialize volatile loads with other side effects.
3290 else if (AA->pointsToConstantMemory(
3291 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3292 // Do not serialize (non-volatile) loads of constant memory with anything.
3293 Root = DAG.getEntryNode();
3294 ConstantMemory = true;
3296 // Do not serialize non-volatile loads against each other.
3297 Root = DAG.getRoot();
3300 SmallVector<SDValue, 4> Values(NumValues);
3301 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3303 EVT PtrVT = Ptr.getValueType();
3304 unsigned ChainI = 0;
3305 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3306 // Serializing loads here may result in excessive register pressure, and
3307 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3308 // could recover a bit by hoisting nodes upward in the chain by recognizing
3309 // they are side-effect free or do not alias. The optimizer should really
3310 // avoid this case by converting large object/array copies to llvm.memcpy
3311 // (MaxParallelChains should always remain as failsafe).
3312 if (ChainI == MaxParallelChains) {
3313 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3314 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3315 MVT::Other, &Chains[0], ChainI);
3319 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3321 DAG.getConstant(Offsets[i], PtrVT));
3322 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3323 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3324 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3328 Chains[ChainI] = L.getValue(1);
3331 if (!ConstantMemory) {
3332 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3333 MVT::Other, &Chains[0], ChainI);
3337 PendingLoads.push_back(Chain);
3340 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3341 DAG.getVTList(&ValueVTs[0], NumValues),
3342 &Values[0], NumValues));
3345 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3347 return visitAtomicStore(I);
3349 const Value *SrcV = I.getOperand(0);
3350 const Value *PtrV = I.getOperand(1);
3352 SmallVector<EVT, 4> ValueVTs;
3353 SmallVector<uint64_t, 4> Offsets;
3354 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3355 unsigned NumValues = ValueVTs.size();
3359 // Get the lowered operands. Note that we do this after
3360 // checking if NumResults is zero, because with zero results
3361 // the operands won't have values in the map.
3362 SDValue Src = getValue(SrcV);
3363 SDValue Ptr = getValue(PtrV);
3365 SDValue Root = getRoot();
3366 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3368 EVT PtrVT = Ptr.getValueType();
3369 bool isVolatile = I.isVolatile();
3370 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3371 unsigned Alignment = I.getAlignment();
3372 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3374 unsigned ChainI = 0;
3375 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3376 // See visitLoad comments.
3377 if (ChainI == MaxParallelChains) {
3378 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3379 MVT::Other, &Chains[0], ChainI);
3383 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3384 DAG.getConstant(Offsets[i], PtrVT));
3385 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3386 SDValue(Src.getNode(), Src.getResNo() + i),
3387 Add, MachinePointerInfo(PtrV, Offsets[i]),
3388 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3389 Chains[ChainI] = St;
3392 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3393 MVT::Other, &Chains[0], ChainI);
3395 AssignOrderingToNode(StoreNode.getNode());
3396 DAG.setRoot(StoreNode);
3399 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3400 SynchronizationScope Scope,
3401 bool Before, DebugLoc dl,
3403 const TargetLowering &TLI) {
3404 // Fence, if necessary
3406 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3408 else if (Order == Acquire || Order == Monotonic)
3411 if (Order == AcquireRelease)
3413 else if (Order == Release || Order == Monotonic)
3418 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3419 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3420 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3423 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3424 DebugLoc dl = getCurDebugLoc();
3425 AtomicOrdering Order = I.getOrdering();
3426 SynchronizationScope Scope = I.getSynchScope();
3428 SDValue InChain = getRoot();
3430 if (TLI.getInsertFencesForAtomic())
3431 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3435 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3436 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3438 getValue(I.getPointerOperand()),
3439 getValue(I.getCompareOperand()),
3440 getValue(I.getNewValOperand()),
3441 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3442 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3445 SDValue OutChain = L.getValue(1);
3447 if (TLI.getInsertFencesForAtomic())
3448 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3452 DAG.setRoot(OutChain);
3455 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3456 DebugLoc dl = getCurDebugLoc();
3458 switch (I.getOperation()) {
3459 default: llvm_unreachable("Unknown atomicrmw operation");
3460 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3461 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3462 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3463 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3464 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3465 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3466 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3467 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3468 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3469 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3470 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3472 AtomicOrdering Order = I.getOrdering();
3473 SynchronizationScope Scope = I.getSynchScope();
3475 SDValue InChain = getRoot();
3477 if (TLI.getInsertFencesForAtomic())
3478 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3482 DAG.getAtomic(NT, dl,
3483 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3485 getValue(I.getPointerOperand()),
3486 getValue(I.getValOperand()),
3487 I.getPointerOperand(), 0 /* Alignment */,
3488 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3491 SDValue OutChain = L.getValue(1);
3493 if (TLI.getInsertFencesForAtomic())
3494 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3498 DAG.setRoot(OutChain);
3501 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3502 DebugLoc dl = getCurDebugLoc();
3505 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3506 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3507 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3510 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3511 DebugLoc dl = getCurDebugLoc();
3512 AtomicOrdering Order = I.getOrdering();
3513 SynchronizationScope Scope = I.getSynchScope();
3515 SDValue InChain = getRoot();
3517 EVT VT = TLI.getValueType(I.getType());
3519 if (I.getAlignment() * 8 < VT.getSizeInBits())
3520 report_fatal_error("Cannot generate unaligned atomic load");
3523 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3524 getValue(I.getPointerOperand()),
3525 I.getPointerOperand(), I.getAlignment(),
3526 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3529 SDValue OutChain = L.getValue(1);
3531 if (TLI.getInsertFencesForAtomic())
3532 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3536 DAG.setRoot(OutChain);
3539 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3540 DebugLoc dl = getCurDebugLoc();
3542 AtomicOrdering Order = I.getOrdering();
3543 SynchronizationScope Scope = I.getSynchScope();
3545 SDValue InChain = getRoot();
3547 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3549 if (I.getAlignment() * 8 < VT.getSizeInBits())
3550 report_fatal_error("Cannot generate unaligned atomic store");
3552 if (TLI.getInsertFencesForAtomic())
3553 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3557 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3559 getValue(I.getPointerOperand()),
3560 getValue(I.getValueOperand()),
3561 I.getPointerOperand(), I.getAlignment(),
3562 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3565 if (TLI.getInsertFencesForAtomic())
3566 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3569 DAG.setRoot(OutChain);
3572 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3574 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3575 unsigned Intrinsic) {
3576 bool HasChain = !I.doesNotAccessMemory();
3577 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3579 // Build the operand list.
3580 SmallVector<SDValue, 8> Ops;
3581 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3583 // We don't need to serialize loads against other loads.
3584 Ops.push_back(DAG.getRoot());
3586 Ops.push_back(getRoot());
3590 // Info is set by getTgtMemInstrinsic
3591 TargetLowering::IntrinsicInfo Info;
3592 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3594 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3595 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3596 Info.opc == ISD::INTRINSIC_W_CHAIN)
3597 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3599 // Add all operands of the call to the operand list.
3600 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3601 SDValue Op = getValue(I.getArgOperand(i));
3605 SmallVector<EVT, 4> ValueVTs;
3606 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3609 ValueVTs.push_back(MVT::Other);
3611 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3615 if (IsTgtIntrinsic) {
3616 // This is target intrinsic that touches memory
3617 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3618 VTs, &Ops[0], Ops.size(),
3620 MachinePointerInfo(Info.ptrVal, Info.offset),
3621 Info.align, Info.vol,
3622 Info.readMem, Info.writeMem);
3623 } else if (!HasChain) {
3624 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3625 VTs, &Ops[0], Ops.size());
3626 } else if (!I.getType()->isVoidTy()) {
3627 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3628 VTs, &Ops[0], Ops.size());
3630 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3631 VTs, &Ops[0], Ops.size());
3635 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3637 PendingLoads.push_back(Chain);
3642 if (!I.getType()->isVoidTy()) {
3643 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3644 EVT VT = TLI.getValueType(PTy);
3645 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3648 setValue(&I, Result);
3650 // Assign order to result here. If the intrinsic does not produce a result,
3651 // it won't be mapped to a SDNode and visit() will not assign it an order
3654 AssignOrderingToNode(Result.getNode());
3658 /// GetSignificand - Get the significand and build it into a floating-point
3659 /// number with exponent of 1:
3661 /// Op = (Op & 0x007fffff) | 0x3f800000;
3663 /// where Op is the hexidecimal representation of floating point value.
3665 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3666 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3667 DAG.getConstant(0x007fffff, MVT::i32));
3668 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3669 DAG.getConstant(0x3f800000, MVT::i32));
3670 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3673 /// GetExponent - Get the exponent:
3675 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3677 /// where Op is the hexidecimal representation of floating point value.
3679 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3681 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3682 DAG.getConstant(0x7f800000, MVT::i32));
3683 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3684 DAG.getConstant(23, TLI.getPointerTy()));
3685 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3686 DAG.getConstant(127, MVT::i32));
3687 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3690 /// getF32Constant - Get 32-bit floating point constant.
3692 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3693 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3696 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3697 /// limited-precision mode.
3698 static SDValue expandExp(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3699 const TargetLowering &TLI) {
3700 if (Op.getValueType() == MVT::f32 &&
3701 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3703 // Put the exponent in the right bit position for later addition to the
3706 // #define LOG2OFe 1.4426950f
3707 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3708 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3709 getF32Constant(DAG, 0x3fb8aa3b));
3710 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3712 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3713 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3714 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3716 // IntegerPartOfX <<= 23;
3717 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3718 DAG.getConstant(23, TLI.getPointerTy()));
3720 SDValue TwoToFracPartOfX;
3721 if (LimitFloatPrecision <= 6) {
3722 // For floating-point precision of 6:
3724 // TwoToFractionalPartOfX =
3726 // (0.735607626f + 0.252464424f * x) * x;
3728 // error 0.0144103317, which is 6 bits
3729 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3730 getF32Constant(DAG, 0x3e814304));
3731 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3732 getF32Constant(DAG, 0x3f3c50c8));
3733 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3734 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3735 getF32Constant(DAG, 0x3f7f5e7e));
3736 } else if (LimitFloatPrecision <= 12) {
3737 // For floating-point precision of 12:
3739 // TwoToFractionalPartOfX =
3742 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3744 // 0.000107046256 error, which is 13 to 14 bits
3745 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3746 getF32Constant(DAG, 0x3da235e3));
3747 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3748 getF32Constant(DAG, 0x3e65b8f3));
3749 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3750 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3751 getF32Constant(DAG, 0x3f324b07));
3752 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3753 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3754 getF32Constant(DAG, 0x3f7ff8fd));
3755 } else { // LimitFloatPrecision <= 18
3756 // For floating-point precision of 18:
3758 // TwoToFractionalPartOfX =
3762 // (0.554906021e-1f +
3763 // (0.961591928e-2f +
3764 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3766 // error 2.47208000*10^(-7), which is better than 18 bits
3767 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3768 getF32Constant(DAG, 0x3924b03e));
3769 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3770 getF32Constant(DAG, 0x3ab24b87));
3771 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3772 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3773 getF32Constant(DAG, 0x3c1d8c17));
3774 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3775 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3776 getF32Constant(DAG, 0x3d634a1d));
3777 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3778 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3779 getF32Constant(DAG, 0x3e75fe14));
3780 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3781 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3782 getF32Constant(DAG, 0x3f317234));
3783 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3784 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3785 getF32Constant(DAG, 0x3f800000));
3788 // Add the exponent into the result in integer domain.
3789 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3790 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3791 DAG.getNode(ISD::ADD, dl, MVT::i32,
3792 t13, IntegerPartOfX));
3795 // No special expansion.
3796 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3799 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3800 /// limited-precision mode.
3801 static SDValue expandLog(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3802 const TargetLowering &TLI) {
3803 if (Op.getValueType() == MVT::f32 &&
3804 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3805 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3807 // Scale the exponent by log(2) [0.69314718f].
3808 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3809 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3810 getF32Constant(DAG, 0x3f317218));
3812 // Get the significand and build it into a floating-point number with
3814 SDValue X = GetSignificand(DAG, Op1, dl);
3816 SDValue LogOfMantissa;
3817 if (LimitFloatPrecision <= 6) {
3818 // For floating-point precision of 6:
3822 // (1.4034025f - 0.23903021f * x) * x;
3824 // error 0.0034276066, which is better than 8 bits
3825 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3826 getF32Constant(DAG, 0xbe74c456));
3827 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3828 getF32Constant(DAG, 0x3fb3a2b1));
3829 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3830 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3831 getF32Constant(DAG, 0x3f949a29));
3832 } else if (LimitFloatPrecision <= 12) {
3833 // For floating-point precision of 12:
3839 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3841 // error 0.000061011436, which is 14 bits
3842 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3843 getF32Constant(DAG, 0xbd67b6d6));
3844 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3845 getF32Constant(DAG, 0x3ee4f4b8));
3846 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3847 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3848 getF32Constant(DAG, 0x3fbc278b));
3849 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3850 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3851 getF32Constant(DAG, 0x40348e95));
3852 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3853 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3854 getF32Constant(DAG, 0x3fdef31a));
3855 } else { // LimitFloatPrecision <= 18
3856 // For floating-point precision of 18:
3864 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3866 // error 0.0000023660568, which is better than 18 bits
3867 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3868 getF32Constant(DAG, 0xbc91e5ac));
3869 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3870 getF32Constant(DAG, 0x3e4350aa));
3871 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3872 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3873 getF32Constant(DAG, 0x3f60d3e3));
3874 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3875 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3876 getF32Constant(DAG, 0x4011cdf0));
3877 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3878 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3879 getF32Constant(DAG, 0x406cfd1c));
3880 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3881 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3882 getF32Constant(DAG, 0x408797cb));
3883 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3884 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3885 getF32Constant(DAG, 0x4006dcab));
3888 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3891 // No special expansion.
3892 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3895 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3896 /// limited-precision mode.
3897 static SDValue expandLog2(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3898 const TargetLowering &TLI) {
3899 if (Op.getValueType() == MVT::f32 &&
3900 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3901 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3903 // Get the exponent.
3904 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3906 // Get the significand and build it into a floating-point number with
3908 SDValue X = GetSignificand(DAG, Op1, dl);
3910 // Different possible minimax approximations of significand in
3911 // floating-point for various degrees of accuracy over [1,2].
3912 SDValue Log2ofMantissa;
3913 if (LimitFloatPrecision <= 6) {
3914 // For floating-point precision of 6:
3916 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3918 // error 0.0049451742, which is more than 7 bits
3919 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3920 getF32Constant(DAG, 0xbeb08fe0));
3921 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3922 getF32Constant(DAG, 0x40019463));
3923 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3924 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3925 getF32Constant(DAG, 0x3fd6633d));
3926 } else if (LimitFloatPrecision <= 12) {
3927 // For floating-point precision of 12:
3933 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3935 // error 0.0000876136000, which is better than 13 bits
3936 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3937 getF32Constant(DAG, 0xbda7262e));
3938 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3939 getF32Constant(DAG, 0x3f25280b));
3940 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3941 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3942 getF32Constant(DAG, 0x4007b923));
3943 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3944 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3945 getF32Constant(DAG, 0x40823e2f));
3946 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3947 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3948 getF32Constant(DAG, 0x4020d29c));
3949 } else { // LimitFloatPrecision <= 18
3950 // For floating-point precision of 18:
3959 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3961 // error 0.0000018516, which is better than 18 bits
3962 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3963 getF32Constant(DAG, 0xbcd2769e));
3964 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3965 getF32Constant(DAG, 0x3e8ce0b9));
3966 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3967 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3968 getF32Constant(DAG, 0x3fa22ae7));
3969 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3970 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3971 getF32Constant(DAG, 0x40525723));
3972 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3973 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3974 getF32Constant(DAG, 0x40aaf200));
3975 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3976 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3977 getF32Constant(DAG, 0x40c39dad));
3978 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3979 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3980 getF32Constant(DAG, 0x4042902c));
3983 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3986 // No special expansion.
3987 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3990 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3991 /// limited-precision mode.
3992 static SDValue expandLog10(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3993 const TargetLowering &TLI) {
3994 if (Op.getValueType() == MVT::f32 &&
3995 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3996 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3998 // Scale the exponent by log10(2) [0.30102999f].
3999 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4000 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4001 getF32Constant(DAG, 0x3e9a209a));
4003 // Get the significand and build it into a floating-point number with
4005 SDValue X = GetSignificand(DAG, Op1, dl);
4007 SDValue Log10ofMantissa;
4008 if (LimitFloatPrecision <= 6) {
4009 // For floating-point precision of 6:
4011 // Log10ofMantissa =
4013 // (0.60948995f - 0.10380950f * x) * x;
4015 // error 0.0014886165, which is 6 bits
4016 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4017 getF32Constant(DAG, 0xbdd49a13));
4018 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4019 getF32Constant(DAG, 0x3f1c0789));
4020 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4021 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4022 getF32Constant(DAG, 0x3f011300));
4023 } else if (LimitFloatPrecision <= 12) {
4024 // For floating-point precision of 12:
4026 // Log10ofMantissa =
4029 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4031 // error 0.00019228036, which is better than 12 bits
4032 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4033 getF32Constant(DAG, 0x3d431f31));
4034 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4035 getF32Constant(DAG, 0x3ea21fb2));
4036 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4037 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4038 getF32Constant(DAG, 0x3f6ae232));
4039 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4040 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4041 getF32Constant(DAG, 0x3f25f7c3));
4042 } else { // LimitFloatPrecision <= 18
4043 // For floating-point precision of 18:
4045 // Log10ofMantissa =
4050 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4052 // error 0.0000037995730, which is better than 18 bits
4053 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4054 getF32Constant(DAG, 0x3c5d51ce));
4055 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4056 getF32Constant(DAG, 0x3e00685a));
4057 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4058 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4059 getF32Constant(DAG, 0x3efb6798));
4060 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4061 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4062 getF32Constant(DAG, 0x3f88d192));
4063 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4064 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4065 getF32Constant(DAG, 0x3fc4316c));
4066 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4067 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4068 getF32Constant(DAG, 0x3f57ce70));
4071 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4074 // No special expansion.
4075 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4078 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4079 /// limited-precision mode.
4080 static SDValue expandExp2(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
4081 const TargetLowering &TLI) {
4082 if (Op.getValueType() == MVT::f32 &&
4083 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4084 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4086 // FractionalPartOfX = x - (float)IntegerPartOfX;
4087 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4088 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4090 // IntegerPartOfX <<= 23;
4091 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4092 DAG.getConstant(23, TLI.getPointerTy()));
4094 SDValue TwoToFractionalPartOfX;
4095 if (LimitFloatPrecision <= 6) {
4096 // For floating-point precision of 6:
4098 // TwoToFractionalPartOfX =
4100 // (0.735607626f + 0.252464424f * x) * x;
4102 // error 0.0144103317, which is 6 bits
4103 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4104 getF32Constant(DAG, 0x3e814304));
4105 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4106 getF32Constant(DAG, 0x3f3c50c8));
4107 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4108 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4109 getF32Constant(DAG, 0x3f7f5e7e));
4110 } else if (LimitFloatPrecision <= 12) {
4111 // For floating-point precision of 12:
4113 // TwoToFractionalPartOfX =
4116 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4118 // error 0.000107046256, which is 13 to 14 bits
4119 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4120 getF32Constant(DAG, 0x3da235e3));
4121 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4122 getF32Constant(DAG, 0x3e65b8f3));
4123 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4124 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4125 getF32Constant(DAG, 0x3f324b07));
4126 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4127 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4128 getF32Constant(DAG, 0x3f7ff8fd));
4129 } else { // LimitFloatPrecision <= 18
4130 // For floating-point precision of 18:
4132 // TwoToFractionalPartOfX =
4136 // (0.554906021e-1f +
4137 // (0.961591928e-2f +
4138 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4139 // error 2.47208000*10^(-7), which is better than 18 bits
4140 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4141 getF32Constant(DAG, 0x3924b03e));
4142 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4143 getF32Constant(DAG, 0x3ab24b87));
4144 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4145 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4146 getF32Constant(DAG, 0x3c1d8c17));
4147 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4148 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4149 getF32Constant(DAG, 0x3d634a1d));
4150 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4151 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4152 getF32Constant(DAG, 0x3e75fe14));
4153 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4154 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4155 getF32Constant(DAG, 0x3f317234));
4156 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4157 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4158 getF32Constant(DAG, 0x3f800000));
4161 // Add the exponent into the result in integer domain.
4162 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4163 TwoToFractionalPartOfX);
4164 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4165 DAG.getNode(ISD::ADD, dl, MVT::i32,
4166 t13, IntegerPartOfX));
4169 // No special expansion.
4170 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4173 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4174 /// limited-precision mode with x == 10.0f.
4175 static SDValue expandPow(DebugLoc dl, SDValue LHS, SDValue RHS,
4176 SelectionDAG &DAG, const TargetLowering &TLI) {
4177 bool IsExp10 = false;
4178 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 &&
4179 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4180 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4182 IsExp10 = LHSC->isExactlyValue(Ten);
4187 // Put the exponent in the right bit position for later addition to the
4190 // #define LOG2OF10 3.3219281f
4191 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4192 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4193 getF32Constant(DAG, 0x40549a78));
4194 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4196 // FractionalPartOfX = x - (float)IntegerPartOfX;
4197 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4198 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4200 // IntegerPartOfX <<= 23;
4201 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4202 DAG.getConstant(23, TLI.getPointerTy()));
4204 SDValue TwoToFractionalPartOfX;
4205 if (LimitFloatPrecision <= 6) {
4206 // For floating-point precision of 6:
4208 // twoToFractionalPartOfX =
4210 // (0.735607626f + 0.252464424f * x) * x;
4212 // error 0.0144103317, which is 6 bits
4213 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4214 getF32Constant(DAG, 0x3e814304));
4215 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4216 getF32Constant(DAG, 0x3f3c50c8));
4217 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4218 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4219 getF32Constant(DAG, 0x3f7f5e7e));
4220 } else if (LimitFloatPrecision <= 12) {
4221 // For floating-point precision of 12:
4223 // TwoToFractionalPartOfX =
4226 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4228 // error 0.000107046256, which is 13 to 14 bits
4229 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4230 getF32Constant(DAG, 0x3da235e3));
4231 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4232 getF32Constant(DAG, 0x3e65b8f3));
4233 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4234 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4235 getF32Constant(DAG, 0x3f324b07));
4236 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4237 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4238 getF32Constant(DAG, 0x3f7ff8fd));
4239 } else { // LimitFloatPrecision <= 18
4240 // For floating-point precision of 18:
4242 // TwoToFractionalPartOfX =
4246 // (0.554906021e-1f +
4247 // (0.961591928e-2f +
4248 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4249 // error 2.47208000*10^(-7), which is better than 18 bits
4250 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4251 getF32Constant(DAG, 0x3924b03e));
4252 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4253 getF32Constant(DAG, 0x3ab24b87));
4254 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4255 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4256 getF32Constant(DAG, 0x3c1d8c17));
4257 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4258 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4259 getF32Constant(DAG, 0x3d634a1d));
4260 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4261 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4262 getF32Constant(DAG, 0x3e75fe14));
4263 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4264 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4265 getF32Constant(DAG, 0x3f317234));
4266 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4267 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4268 getF32Constant(DAG, 0x3f800000));
4271 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4272 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4273 DAG.getNode(ISD::ADD, dl, MVT::i32,
4274 t13, IntegerPartOfX));
4277 // No special expansion.
4278 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4282 /// ExpandPowI - Expand a llvm.powi intrinsic.
4283 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4284 SelectionDAG &DAG) {
4285 // If RHS is a constant, we can expand this out to a multiplication tree,
4286 // otherwise we end up lowering to a call to __powidf2 (for example). When
4287 // optimizing for size, we only want to do this if the expansion would produce
4288 // a small number of multiplies, otherwise we do the full expansion.
4289 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4290 // Get the exponent as a positive value.
4291 unsigned Val = RHSC->getSExtValue();
4292 if ((int)Val < 0) Val = -Val;
4294 // powi(x, 0) -> 1.0
4296 return DAG.getConstantFP(1.0, LHS.getValueType());
4298 const Function *F = DAG.getMachineFunction().getFunction();
4299 if (!F->getFnAttributes().hasAttribute(Attribute::OptimizeForSize) ||
4300 // If optimizing for size, don't insert too many multiplies. This
4301 // inserts up to 5 multiplies.
4302 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4303 // We use the simple binary decomposition method to generate the multiply
4304 // sequence. There are more optimal ways to do this (for example,
4305 // powi(x,15) generates one more multiply than it should), but this has
4306 // the benefit of being both really simple and much better than a libcall.
4307 SDValue Res; // Logically starts equal to 1.0
4308 SDValue CurSquare = LHS;
4312 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4314 Res = CurSquare; // 1.0*CurSquare.
4317 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4318 CurSquare, CurSquare);
4322 // If the original was negative, invert the result, producing 1/(x*x*x).
4323 if (RHSC->getSExtValue() < 0)
4324 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4325 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4330 // Otherwise, expand to a libcall.
4331 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4334 // getTruncatedArgReg - Find underlying register used for an truncated
4336 static unsigned getTruncatedArgReg(const SDValue &N) {
4337 if (N.getOpcode() != ISD::TRUNCATE)
4340 const SDValue &Ext = N.getOperand(0);
4341 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4342 const SDValue &CFR = Ext.getOperand(0);
4343 if (CFR.getOpcode() == ISD::CopyFromReg)
4344 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4345 if (CFR.getOpcode() == ISD::TRUNCATE)
4346 return getTruncatedArgReg(CFR);
4351 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4352 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4353 /// At the end of instruction selection, they will be inserted to the entry BB.
4355 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4358 const Argument *Arg = dyn_cast<Argument>(V);
4362 MachineFunction &MF = DAG.getMachineFunction();
4363 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4364 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4366 // Ignore inlined function arguments here.
4367 DIVariable DV(Variable);
4368 if (DV.isInlinedFnArgument(MF.getFunction()))
4372 // Some arguments' frame index is recorded during argument lowering.
4373 Offset = FuncInfo.getArgumentFrameIndex(Arg);
4375 Reg = TRI->getFrameRegister(MF);
4377 if (!Reg && N.getNode()) {
4378 if (N.getOpcode() == ISD::CopyFromReg)
4379 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4381 Reg = getTruncatedArgReg(N);
4382 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4383 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4384 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4391 // Check if ValueMap has reg number.
4392 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4393 if (VMI != FuncInfo.ValueMap.end())
4397 if (!Reg && N.getNode()) {
4398 // Check if frame index is available.
4399 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4400 if (FrameIndexSDNode *FINode =
4401 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4402 Reg = TRI->getFrameRegister(MF);
4403 Offset = FINode->getIndex();
4410 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4411 TII->get(TargetOpcode::DBG_VALUE))
4412 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4413 FuncInfo.ArgDbgValues.push_back(&*MIB);
4417 // VisualStudio defines setjmp as _setjmp
4418 #if defined(_MSC_VER) && defined(setjmp) && \
4419 !defined(setjmp_undefined_for_msvc)
4420 # pragma push_macro("setjmp")
4422 # define setjmp_undefined_for_msvc
4425 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4426 /// we want to emit this as a call to a named external function, return the name
4427 /// otherwise lower it and return null.
4429 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4430 DebugLoc dl = getCurDebugLoc();
4433 switch (Intrinsic) {
4435 // By default, turn this into a target intrinsic node.
4436 visitTargetIntrinsic(I, Intrinsic);
4438 case Intrinsic::vastart: visitVAStart(I); return 0;
4439 case Intrinsic::vaend: visitVAEnd(I); return 0;
4440 case Intrinsic::vacopy: visitVACopy(I); return 0;
4441 case Intrinsic::returnaddress:
4442 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4443 getValue(I.getArgOperand(0))));
4445 case Intrinsic::frameaddress:
4446 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4447 getValue(I.getArgOperand(0))));
4449 case Intrinsic::setjmp:
4450 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4451 case Intrinsic::longjmp:
4452 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4453 case Intrinsic::memcpy: {
4454 // Assert for address < 256 since we support only user defined address
4456 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4458 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4460 "Unknown address space");
4461 SDValue Op1 = getValue(I.getArgOperand(0));
4462 SDValue Op2 = getValue(I.getArgOperand(1));
4463 SDValue Op3 = getValue(I.getArgOperand(2));
4464 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4465 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4466 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4467 MachinePointerInfo(I.getArgOperand(0)),
4468 MachinePointerInfo(I.getArgOperand(1))));
4471 case Intrinsic::memset: {
4472 // Assert for address < 256 since we support only user defined address
4474 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4476 "Unknown address space");
4477 SDValue Op1 = getValue(I.getArgOperand(0));
4478 SDValue Op2 = getValue(I.getArgOperand(1));
4479 SDValue Op3 = getValue(I.getArgOperand(2));
4480 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4481 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4482 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4483 MachinePointerInfo(I.getArgOperand(0))));
4486 case Intrinsic::memmove: {
4487 // Assert for address < 256 since we support only user defined address
4489 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4491 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4493 "Unknown address space");
4494 SDValue Op1 = getValue(I.getArgOperand(0));
4495 SDValue Op2 = getValue(I.getArgOperand(1));
4496 SDValue Op3 = getValue(I.getArgOperand(2));
4497 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4498 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4499 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4500 MachinePointerInfo(I.getArgOperand(0)),
4501 MachinePointerInfo(I.getArgOperand(1))));
4504 case Intrinsic::dbg_declare: {
4505 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4506 MDNode *Variable = DI.getVariable();
4507 const Value *Address = DI.getAddress();
4508 if (!Address || !DIVariable(Variable).Verify()) {
4509 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4513 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4514 // but do not always have a corresponding SDNode built. The SDNodeOrder
4515 // absolute, but not relative, values are different depending on whether
4516 // debug info exists.
4519 // Check if address has undef value.
4520 if (isa<UndefValue>(Address) ||
4521 (Address->use_empty() && !isa<Argument>(Address))) {
4522 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4526 SDValue &N = NodeMap[Address];
4527 if (!N.getNode() && isa<Argument>(Address))
4528 // Check unused arguments map.
4529 N = UnusedArgNodeMap[Address];
4532 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4533 Address = BCI->getOperand(0);
4534 // Parameters are handled specially.
4536 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4537 isa<Argument>(Address));
4539 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4541 if (isParameter && !AI) {
4542 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4544 // Byval parameter. We have a frame index at this point.
4545 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4546 0, dl, SDNodeOrder);
4548 // Address is an argument, so try to emit its dbg value using
4549 // virtual register info from the FuncInfo.ValueMap.
4550 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4554 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4555 0, dl, SDNodeOrder);
4557 // Can't do anything with other non-AI cases yet.
4558 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4559 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4560 DEBUG(Address->dump());
4563 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4565 // If Address is an argument then try to emit its dbg value using
4566 // virtual register info from the FuncInfo.ValueMap.
4567 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4568 // If variable is pinned by a alloca in dominating bb then
4569 // use StaticAllocaMap.
4570 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4571 if (AI->getParent() != DI.getParent()) {
4572 DenseMap<const AllocaInst*, int>::iterator SI =
4573 FuncInfo.StaticAllocaMap.find(AI);
4574 if (SI != FuncInfo.StaticAllocaMap.end()) {
4575 SDV = DAG.getDbgValue(Variable, SI->second,
4576 0, dl, SDNodeOrder);
4577 DAG.AddDbgValue(SDV, 0, false);
4582 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4587 case Intrinsic::dbg_value: {
4588 const DbgValueInst &DI = cast<DbgValueInst>(I);
4589 if (!DIVariable(DI.getVariable()).Verify())
4592 MDNode *Variable = DI.getVariable();
4593 uint64_t Offset = DI.getOffset();
4594 const Value *V = DI.getValue();
4598 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4599 // but do not always have a corresponding SDNode built. The SDNodeOrder
4600 // absolute, but not relative, values are different depending on whether
4601 // debug info exists.
4604 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4605 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4606 DAG.AddDbgValue(SDV, 0, false);
4608 // Do not use getValue() in here; we don't want to generate code at
4609 // this point if it hasn't been done yet.
4610 SDValue N = NodeMap[V];
4611 if (!N.getNode() && isa<Argument>(V))
4612 // Check unused arguments map.
4613 N = UnusedArgNodeMap[V];
4615 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4616 SDV = DAG.getDbgValue(Variable, N.getNode(),
4617 N.getResNo(), Offset, dl, SDNodeOrder);
4618 DAG.AddDbgValue(SDV, N.getNode(), false);
4620 } else if (!V->use_empty() ) {
4621 // Do not call getValue(V) yet, as we don't want to generate code.
4622 // Remember it for later.
4623 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4624 DanglingDebugInfoMap[V] = DDI;
4626 // We may expand this to cover more cases. One case where we have no
4627 // data available is an unreferenced parameter.
4628 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4632 // Build a debug info table entry.
4633 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4634 V = BCI->getOperand(0);
4635 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4636 // Don't handle byval struct arguments or VLAs, for example.
4638 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4639 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4642 DenseMap<const AllocaInst*, int>::iterator SI =
4643 FuncInfo.StaticAllocaMap.find(AI);
4644 if (SI == FuncInfo.StaticAllocaMap.end())
4646 int FI = SI->second;
4648 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4649 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4650 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4654 case Intrinsic::eh_typeid_for: {
4655 // Find the type id for the given typeinfo.
4656 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4657 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4658 Res = DAG.getConstant(TypeID, MVT::i32);
4663 case Intrinsic::eh_return_i32:
4664 case Intrinsic::eh_return_i64:
4665 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4666 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4669 getValue(I.getArgOperand(0)),
4670 getValue(I.getArgOperand(1))));
4672 case Intrinsic::eh_unwind_init:
4673 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4675 case Intrinsic::eh_dwarf_cfa: {
4676 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4677 TLI.getPointerTy());
4678 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4680 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4681 TLI.getPointerTy()),
4683 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4685 DAG.getConstant(0, TLI.getPointerTy()));
4686 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4690 case Intrinsic::eh_sjlj_callsite: {
4691 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4692 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4693 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4694 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4696 MMI.setCurrentCallSite(CI->getZExtValue());
4699 case Intrinsic::eh_sjlj_functioncontext: {
4700 // Get and store the index of the function context.
4701 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4703 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4704 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4705 MFI->setFunctionContextIndex(FI);
4708 case Intrinsic::eh_sjlj_setjmp: {
4711 Ops[1] = getValue(I.getArgOperand(0));
4712 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
4713 DAG.getVTList(MVT::i32, MVT::Other),
4715 setValue(&I, Op.getValue(0));
4716 DAG.setRoot(Op.getValue(1));
4719 case Intrinsic::eh_sjlj_longjmp: {
4720 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4721 getRoot(), getValue(I.getArgOperand(0))));
4725 case Intrinsic::x86_mmx_pslli_w:
4726 case Intrinsic::x86_mmx_pslli_d:
4727 case Intrinsic::x86_mmx_pslli_q:
4728 case Intrinsic::x86_mmx_psrli_w:
4729 case Intrinsic::x86_mmx_psrli_d:
4730 case Intrinsic::x86_mmx_psrli_q:
4731 case Intrinsic::x86_mmx_psrai_w:
4732 case Intrinsic::x86_mmx_psrai_d: {
4733 SDValue ShAmt = getValue(I.getArgOperand(1));
4734 if (isa<ConstantSDNode>(ShAmt)) {
4735 visitTargetIntrinsic(I, Intrinsic);
4738 unsigned NewIntrinsic = 0;
4739 EVT ShAmtVT = MVT::v2i32;
4740 switch (Intrinsic) {
4741 case Intrinsic::x86_mmx_pslli_w:
4742 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4744 case Intrinsic::x86_mmx_pslli_d:
4745 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4747 case Intrinsic::x86_mmx_pslli_q:
4748 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4750 case Intrinsic::x86_mmx_psrli_w:
4751 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4753 case Intrinsic::x86_mmx_psrli_d:
4754 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4756 case Intrinsic::x86_mmx_psrli_q:
4757 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4759 case Intrinsic::x86_mmx_psrai_w:
4760 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4762 case Intrinsic::x86_mmx_psrai_d:
4763 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4765 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4768 // The vector shift intrinsics with scalars uses 32b shift amounts but
4769 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4771 // We must do this early because v2i32 is not a legal type.
4774 ShOps[1] = DAG.getConstant(0, MVT::i32);
4775 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4776 EVT DestVT = TLI.getValueType(I.getType());
4777 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4778 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4779 DAG.getConstant(NewIntrinsic, MVT::i32),
4780 getValue(I.getArgOperand(0)), ShAmt);
4784 case Intrinsic::x86_avx_vinsertf128_pd_256:
4785 case Intrinsic::x86_avx_vinsertf128_ps_256:
4786 case Intrinsic::x86_avx_vinsertf128_si_256:
4787 case Intrinsic::x86_avx2_vinserti128: {
4788 EVT DestVT = TLI.getValueType(I.getType());
4789 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
4790 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4791 ElVT.getVectorNumElements();
4792 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT,
4793 getValue(I.getArgOperand(0)),
4794 getValue(I.getArgOperand(1)),
4795 DAG.getIntPtrConstant(Idx));
4799 case Intrinsic::x86_avx_vextractf128_pd_256:
4800 case Intrinsic::x86_avx_vextractf128_ps_256:
4801 case Intrinsic::x86_avx_vextractf128_si_256:
4802 case Intrinsic::x86_avx2_vextracti128: {
4803 EVT DestVT = TLI.getValueType(I.getType());
4804 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
4805 DestVT.getVectorNumElements();
4806 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4807 getValue(I.getArgOperand(0)),
4808 DAG.getIntPtrConstant(Idx));
4812 case Intrinsic::convertff:
4813 case Intrinsic::convertfsi:
4814 case Intrinsic::convertfui:
4815 case Intrinsic::convertsif:
4816 case Intrinsic::convertuif:
4817 case Intrinsic::convertss:
4818 case Intrinsic::convertsu:
4819 case Intrinsic::convertus:
4820 case Intrinsic::convertuu: {
4821 ISD::CvtCode Code = ISD::CVT_INVALID;
4822 switch (Intrinsic) {
4823 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4824 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4825 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4826 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4827 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4828 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4829 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4830 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4831 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4832 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4834 EVT DestVT = TLI.getValueType(I.getType());
4835 const Value *Op1 = I.getArgOperand(0);
4836 Res = DAG.getConvertRndSat(DestVT, dl, getValue(Op1),
4837 DAG.getValueType(DestVT),
4838 DAG.getValueType(getValue(Op1).getValueType()),
4839 getValue(I.getArgOperand(1)),
4840 getValue(I.getArgOperand(2)),
4845 case Intrinsic::powi:
4846 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4847 getValue(I.getArgOperand(1)), DAG));
4849 case Intrinsic::log:
4850 setValue(&I, expandLog(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4852 case Intrinsic::log2:
4853 setValue(&I, expandLog2(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4855 case Intrinsic::log10:
4856 setValue(&I, expandLog10(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4858 case Intrinsic::exp:
4859 setValue(&I, expandExp(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4861 case Intrinsic::exp2:
4862 setValue(&I, expandExp2(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4864 case Intrinsic::pow:
4865 setValue(&I, expandPow(dl, getValue(I.getArgOperand(0)),
4866 getValue(I.getArgOperand(1)), DAG, TLI));
4868 case Intrinsic::sqrt:
4869 case Intrinsic::fabs:
4870 case Intrinsic::sin:
4871 case Intrinsic::cos:
4872 case Intrinsic::floor:
4873 case Intrinsic::ceil:
4874 case Intrinsic::trunc:
4875 case Intrinsic::rint:
4876 case Intrinsic::nearbyint: {
4878 switch (Intrinsic) {
4879 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4880 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4881 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4882 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4883 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4884 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4885 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4886 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4887 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4888 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4891 setValue(&I, DAG.getNode(Opcode, dl,
4892 getValue(I.getArgOperand(0)).getValueType(),
4893 getValue(I.getArgOperand(0))));
4896 case Intrinsic::fma:
4897 setValue(&I, DAG.getNode(ISD::FMA, dl,
4898 getValue(I.getArgOperand(0)).getValueType(),
4899 getValue(I.getArgOperand(0)),
4900 getValue(I.getArgOperand(1)),
4901 getValue(I.getArgOperand(2))));
4903 case Intrinsic::fmuladd: {
4904 EVT VT = TLI.getValueType(I.getType());
4905 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4906 TLI.isOperationLegalOrCustom(ISD::FMA, VT) &&
4907 TLI.isFMAFasterThanMulAndAdd(VT)){
4908 setValue(&I, DAG.getNode(ISD::FMA, dl,
4909 getValue(I.getArgOperand(0)).getValueType(),
4910 getValue(I.getArgOperand(0)),
4911 getValue(I.getArgOperand(1)),
4912 getValue(I.getArgOperand(2))));
4914 SDValue Mul = DAG.getNode(ISD::FMUL, dl,
4915 getValue(I.getArgOperand(0)).getValueType(),
4916 getValue(I.getArgOperand(0)),
4917 getValue(I.getArgOperand(1)));
4918 SDValue Add = DAG.getNode(ISD::FADD, dl,
4919 getValue(I.getArgOperand(0)).getValueType(),
4921 getValue(I.getArgOperand(2)));
4926 case Intrinsic::convert_to_fp16:
4927 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4928 MVT::i16, getValue(I.getArgOperand(0))));
4930 case Intrinsic::convert_from_fp16:
4931 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4932 MVT::f32, getValue(I.getArgOperand(0))));
4934 case Intrinsic::pcmarker: {
4935 SDValue Tmp = getValue(I.getArgOperand(0));
4936 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4939 case Intrinsic::readcyclecounter: {
4940 SDValue Op = getRoot();
4941 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4942 DAG.getVTList(MVT::i64, MVT::Other),
4945 DAG.setRoot(Res.getValue(1));
4948 case Intrinsic::bswap:
4949 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4950 getValue(I.getArgOperand(0)).getValueType(),
4951 getValue(I.getArgOperand(0))));
4953 case Intrinsic::cttz: {
4954 SDValue Arg = getValue(I.getArgOperand(0));
4955 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4956 EVT Ty = Arg.getValueType();
4957 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4961 case Intrinsic::ctlz: {
4962 SDValue Arg = getValue(I.getArgOperand(0));
4963 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4964 EVT Ty = Arg.getValueType();
4965 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4969 case Intrinsic::ctpop: {
4970 SDValue Arg = getValue(I.getArgOperand(0));
4971 EVT Ty = Arg.getValueType();
4972 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4975 case Intrinsic::stacksave: {
4976 SDValue Op = getRoot();
4977 Res = DAG.getNode(ISD::STACKSAVE, dl,
4978 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4980 DAG.setRoot(Res.getValue(1));
4983 case Intrinsic::stackrestore: {
4984 Res = getValue(I.getArgOperand(0));
4985 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4988 case Intrinsic::stackprotector: {
4989 // Emit code into the DAG to store the stack guard onto the stack.
4990 MachineFunction &MF = DAG.getMachineFunction();
4991 MachineFrameInfo *MFI = MF.getFrameInfo();
4992 EVT PtrTy = TLI.getPointerTy();
4994 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4995 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4997 int FI = FuncInfo.StaticAllocaMap[Slot];
4998 MFI->setStackProtectorIndex(FI);
5000 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5002 // Store the stack protector onto the stack.
5003 Res = DAG.getStore(getRoot(), dl, Src, FIN,
5004 MachinePointerInfo::getFixedStack(FI),
5010 case Intrinsic::objectsize: {
5011 // If we don't know by now, we're never going to know.
5012 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5014 assert(CI && "Non-constant type in __builtin_object_size?");
5016 SDValue Arg = getValue(I.getCalledValue());
5017 EVT Ty = Arg.getValueType();
5020 Res = DAG.getConstant(-1ULL, Ty);
5022 Res = DAG.getConstant(0, Ty);
5027 case Intrinsic::var_annotation:
5028 // Discard annotate attributes
5031 case Intrinsic::init_trampoline: {
5032 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5036 Ops[1] = getValue(I.getArgOperand(0));
5037 Ops[2] = getValue(I.getArgOperand(1));
5038 Ops[3] = getValue(I.getArgOperand(2));
5039 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5040 Ops[5] = DAG.getSrcValue(F);
5042 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
5047 case Intrinsic::adjust_trampoline: {
5048 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
5050 getValue(I.getArgOperand(0))));
5053 case Intrinsic::gcroot:
5055 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5056 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5058 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5059 GFI->addStackRoot(FI->getIndex(), TypeMap);
5062 case Intrinsic::gcread:
5063 case Intrinsic::gcwrite:
5064 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5065 case Intrinsic::flt_rounds:
5066 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
5069 case Intrinsic::expect: {
5070 // Just replace __builtin_expect(exp, c) with EXP.
5071 setValue(&I, getValue(I.getArgOperand(0)));
5075 case Intrinsic::debugtrap:
5076 case Intrinsic::trap: {
5077 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5078 if (TrapFuncName.empty()) {
5079 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5080 ISD::TRAP : ISD::DEBUGTRAP;
5081 DAG.setRoot(DAG.getNode(Op, dl,MVT::Other, getRoot()));
5084 TargetLowering::ArgListTy Args;
5086 CallLoweringInfo CLI(getRoot(), I.getType(),
5087 false, false, false, false, 0, CallingConv::C,
5088 /*isTailCall=*/false,
5089 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5090 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5092 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5093 DAG.setRoot(Result.second);
5097 case Intrinsic::uadd_with_overflow:
5098 case Intrinsic::sadd_with_overflow:
5099 case Intrinsic::usub_with_overflow:
5100 case Intrinsic::ssub_with_overflow:
5101 case Intrinsic::umul_with_overflow:
5102 case Intrinsic::smul_with_overflow: {
5104 switch (Intrinsic) {
5105 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5106 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5107 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5108 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5109 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5110 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5111 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5113 SDValue Op1 = getValue(I.getArgOperand(0));
5114 SDValue Op2 = getValue(I.getArgOperand(1));
5116 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5117 setValue(&I, DAG.getNode(Op, dl, VTs, Op1, Op2));
5120 case Intrinsic::prefetch: {
5122 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5124 Ops[1] = getValue(I.getArgOperand(0));
5125 Ops[2] = getValue(I.getArgOperand(1));
5126 Ops[3] = getValue(I.getArgOperand(2));
5127 Ops[4] = getValue(I.getArgOperand(3));
5128 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
5129 DAG.getVTList(MVT::Other),
5131 EVT::getIntegerVT(*Context, 8),
5132 MachinePointerInfo(I.getArgOperand(0)),
5134 false, /* volatile */
5136 rw==1)); /* write */
5139 case Intrinsic::lifetime_start:
5140 case Intrinsic::lifetime_end: {
5141 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5142 // Stack coloring is not enabled in O0, discard region information.
5143 if (TM.getOptLevel() == CodeGenOpt::None)
5146 SmallVector<Value *, 4> Allocas;
5147 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD);
5149 for (SmallVector<Value*, 4>::iterator Object = Allocas.begin(),
5150 E = Allocas.end(); Object != E; ++Object) {
5151 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5153 // Could not find an Alloca.
5154 if (!LifetimeObject)
5157 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5161 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5162 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5164 Res = DAG.getNode(Opcode, dl, MVT::Other, Ops, 2);
5168 case Intrinsic::invariant_start:
5169 // Discard region information.
5170 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5172 case Intrinsic::invariant_end:
5173 // Discard region information.
5175 case Intrinsic::donothing:
5181 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5183 MachineBasicBlock *LandingPad) {
5184 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5185 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5186 Type *RetTy = FTy->getReturnType();
5187 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5188 MCSymbol *BeginLabel = 0;
5190 TargetLowering::ArgListTy Args;
5191 TargetLowering::ArgListEntry Entry;
5192 Args.reserve(CS.arg_size());
5194 // Check whether the function can return without sret-demotion.
5195 SmallVector<ISD::OutputArg, 4> Outs;
5196 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
5199 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5200 DAG.getMachineFunction(),
5201 FTy->isVarArg(), Outs,
5204 SDValue DemoteStackSlot;
5205 int DemoteStackIdx = -100;
5207 if (!CanLowerReturn) {
5208 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(
5209 FTy->getReturnType());
5210 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(
5211 FTy->getReturnType());
5212 MachineFunction &MF = DAG.getMachineFunction();
5213 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5214 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5216 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5217 Entry.Node = DemoteStackSlot;
5218 Entry.Ty = StackSlotPtrType;
5219 Entry.isSExt = false;
5220 Entry.isZExt = false;
5221 Entry.isInReg = false;
5222 Entry.isSRet = true;
5223 Entry.isNest = false;
5224 Entry.isByVal = false;
5225 Entry.Alignment = Align;
5226 Args.push_back(Entry);
5227 RetTy = Type::getVoidTy(FTy->getContext());
5230 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5232 const Value *V = *i;
5235 if (V->getType()->isEmptyTy())
5238 SDValue ArgNode = getValue(V);
5239 Entry.Node = ArgNode; Entry.Ty = V->getType();
5241 unsigned attrInd = i - CS.arg_begin() + 1;
5242 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5243 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5244 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5245 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5246 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5247 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5248 Entry.Alignment = CS.getParamAlignment(attrInd);
5249 Args.push_back(Entry);
5253 // Insert a label before the invoke call to mark the try range. This can be
5254 // used to detect deletion of the invoke via the MachineModuleInfo.
5255 BeginLabel = MMI.getContext().CreateTempSymbol();
5257 // For SjLj, keep track of which landing pads go with which invokes
5258 // so as to maintain the ordering of pads in the LSDA.
5259 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5260 if (CallSiteIndex) {
5261 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5262 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5264 // Now that the call site is handled, stop tracking it.
5265 MMI.setCurrentCallSite(0);
5268 // Both PendingLoads and PendingExports must be flushed here;
5269 // this call might not return.
5271 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5274 // Check if target-independent constraints permit a tail call here.
5275 // Target-dependent constraints are checked within TLI.LowerCallTo.
5277 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
5281 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5282 getCurDebugLoc(), CS);
5283 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI);
5284 assert((isTailCall || Result.second.getNode()) &&
5285 "Non-null chain expected with non-tail call!");
5286 assert((Result.second.getNode() || !Result.first.getNode()) &&
5287 "Null value expected with tail call!");
5288 if (Result.first.getNode()) {
5289 setValue(CS.getInstruction(), Result.first);
5290 } else if (!CanLowerReturn && Result.second.getNode()) {
5291 // The instruction result is the result of loading from the
5292 // hidden sret parameter.
5293 SmallVector<EVT, 1> PVTs;
5294 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5296 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5297 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5298 EVT PtrVT = PVTs[0];
5300 SmallVector<EVT, 4> RetTys;
5301 SmallVector<uint64_t, 4> Offsets;
5302 RetTy = FTy->getReturnType();
5303 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets);
5305 unsigned NumValues = RetTys.size();
5306 SmallVector<SDValue, 4> Values(NumValues);
5307 SmallVector<SDValue, 4> Chains(NumValues);
5309 for (unsigned i = 0; i < NumValues; ++i) {
5310 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5312 DAG.getConstant(Offsets[i], PtrVT));
5313 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add,
5314 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5315 false, false, false, 1);
5317 Chains[i] = L.getValue(1);
5320 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5321 MVT::Other, &Chains[0], NumValues);
5322 PendingLoads.push_back(Chain);
5324 setValue(CS.getInstruction(),
5325 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5326 DAG.getVTList(&RetTys[0], RetTys.size()),
5327 &Values[0], Values.size()));
5330 // Assign order to nodes here. If the call does not produce a result, it won't
5331 // be mapped to a SDNode and visit() will not assign it an order number.
5332 if (!Result.second.getNode()) {
5333 // As a special case, a null chain means that a tail call has been emitted and
5334 // the DAG root is already updated.
5337 AssignOrderingToNode(DAG.getRoot().getNode());
5339 DAG.setRoot(Result.second);
5341 AssignOrderingToNode(Result.second.getNode());
5345 // Insert a label at the end of the invoke call to mark the try range. This
5346 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5347 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5348 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5350 // Inform MachineModuleInfo of range.
5351 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5355 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5356 /// value is equal or not-equal to zero.
5357 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5358 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5360 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5361 if (IC->isEquality())
5362 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5363 if (C->isNullValue())
5365 // Unknown instruction.
5371 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5373 SelectionDAGBuilder &Builder) {
5375 // Check to see if this load can be trivially constant folded, e.g. if the
5376 // input is from a string literal.
5377 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5378 // Cast pointer to the type we really want to load.
5379 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5380 PointerType::getUnqual(LoadTy));
5382 if (const Constant *LoadCst =
5383 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5385 return Builder.getValue(LoadCst);
5388 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5389 // still constant memory, the input chain can be the entry node.
5391 bool ConstantMemory = false;
5393 // Do not serialize (non-volatile) loads of constant memory with anything.
5394 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5395 Root = Builder.DAG.getEntryNode();
5396 ConstantMemory = true;
5398 // Do not serialize non-volatile loads against each other.
5399 Root = Builder.DAG.getRoot();
5402 SDValue Ptr = Builder.getValue(PtrVal);
5403 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5404 Ptr, MachinePointerInfo(PtrVal),
5406 false /*nontemporal*/,
5407 false /*isinvariant*/, 1 /* align=1 */);
5409 if (!ConstantMemory)
5410 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5415 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5416 /// If so, return true and lower it, otherwise return false and it will be
5417 /// lowered like a normal call.
5418 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5419 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5420 if (I.getNumArgOperands() != 3)
5423 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5424 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5425 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5426 !I.getType()->isIntegerTy())
5429 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5431 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5432 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5433 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5434 bool ActuallyDoIt = true;
5437 switch (Size->getZExtValue()) {
5439 LoadVT = MVT::Other;
5441 ActuallyDoIt = false;
5445 LoadTy = Type::getInt16Ty(Size->getContext());
5449 LoadTy = Type::getInt32Ty(Size->getContext());
5453 LoadTy = Type::getInt64Ty(Size->getContext());
5457 LoadVT = MVT::v4i32;
5458 LoadTy = Type::getInt32Ty(Size->getContext());
5459 LoadTy = VectorType::get(LoadTy, 4);
5464 // This turns into unaligned loads. We only do this if the target natively
5465 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5466 // we'll only produce a small number of byte loads.
5468 // Require that we can find a legal MVT, and only do this if the target
5469 // supports unaligned loads of that type. Expanding into byte loads would
5471 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5472 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5473 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5474 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5475 ActuallyDoIt = false;
5479 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5480 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5482 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5484 EVT CallVT = TLI.getValueType(I.getType(), true);
5485 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5494 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5495 /// operation (as expected), translate it to an SDNode with the specified opcode
5496 /// and return true.
5497 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5499 // Sanity check that it really is a unary floating-point call.
5500 if (I.getNumArgOperands() != 1 ||
5501 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5502 I.getType() != I.getArgOperand(0)->getType() ||
5503 !I.onlyReadsMemory())
5506 SDValue Tmp = getValue(I.getArgOperand(0));
5507 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Tmp.getValueType(), Tmp));
5511 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5512 // Handle inline assembly differently.
5513 if (isa<InlineAsm>(I.getCalledValue())) {
5518 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5519 ComputeUsesVAFloatArgument(I, &MMI);
5521 const char *RenameFn = 0;
5522 if (Function *F = I.getCalledFunction()) {
5523 if (F->isDeclaration()) {
5524 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5525 if (unsigned IID = II->getIntrinsicID(F)) {
5526 RenameFn = visitIntrinsicCall(I, IID);
5531 if (unsigned IID = F->getIntrinsicID()) {
5532 RenameFn = visitIntrinsicCall(I, IID);
5538 // Check for well-known libc/libm calls. If the function is internal, it
5539 // can't be a library call.
5541 if (!F->hasLocalLinkage() && F->hasName() &&
5542 LibInfo->getLibFunc(F->getName(), Func) &&
5543 LibInfo->hasOptimizedCodeGen(Func)) {
5546 case LibFunc::copysign:
5547 case LibFunc::copysignf:
5548 case LibFunc::copysignl:
5549 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5550 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5551 I.getType() == I.getArgOperand(0)->getType() &&
5552 I.getType() == I.getArgOperand(1)->getType() &&
5553 I.onlyReadsMemory()) {
5554 SDValue LHS = getValue(I.getArgOperand(0));
5555 SDValue RHS = getValue(I.getArgOperand(1));
5556 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5557 LHS.getValueType(), LHS, RHS));
5562 case LibFunc::fabsf:
5563 case LibFunc::fabsl:
5564 if (visitUnaryFloatCall(I, ISD::FABS))
5570 if (visitUnaryFloatCall(I, ISD::FSIN))
5576 if (visitUnaryFloatCall(I, ISD::FCOS))
5580 case LibFunc::sqrtf:
5581 case LibFunc::sqrtl:
5582 if (visitUnaryFloatCall(I, ISD::FSQRT))
5585 case LibFunc::floor:
5586 case LibFunc::floorf:
5587 case LibFunc::floorl:
5588 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5591 case LibFunc::nearbyint:
5592 case LibFunc::nearbyintf:
5593 case LibFunc::nearbyintl:
5594 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5598 case LibFunc::ceilf:
5599 case LibFunc::ceill:
5600 if (visitUnaryFloatCall(I, ISD::FCEIL))
5604 case LibFunc::rintf:
5605 case LibFunc::rintl:
5606 if (visitUnaryFloatCall(I, ISD::FRINT))
5609 case LibFunc::trunc:
5610 case LibFunc::truncf:
5611 case LibFunc::truncl:
5612 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5616 case LibFunc::log2f:
5617 case LibFunc::log2l:
5618 if (visitUnaryFloatCall(I, ISD::FLOG2))
5622 case LibFunc::exp2f:
5623 case LibFunc::exp2l:
5624 if (visitUnaryFloatCall(I, ISD::FEXP2))
5627 case LibFunc::memcmp:
5628 if (visitMemCmpCall(I))
5637 Callee = getValue(I.getCalledValue());
5639 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5641 // Check if we can potentially perform a tail call. More detailed checking is
5642 // be done within LowerCallTo, after more information about the call is known.
5643 LowerCallTo(&I, Callee, I.isTailCall());
5648 /// AsmOperandInfo - This contains information for each constraint that we are
5650 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5652 /// CallOperand - If this is the result output operand or a clobber
5653 /// this is null, otherwise it is the incoming operand to the CallInst.
5654 /// This gets modified as the asm is processed.
5655 SDValue CallOperand;
5657 /// AssignedRegs - If this is a register or register class operand, this
5658 /// contains the set of register corresponding to the operand.
5659 RegsForValue AssignedRegs;
5661 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5662 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5665 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5666 /// corresponds to. If there is no Value* for this operand, it returns
5668 EVT getCallOperandValEVT(LLVMContext &Context,
5669 const TargetLowering &TLI,
5670 const DataLayout *TD) const {
5671 if (CallOperandVal == 0) return MVT::Other;
5673 if (isa<BasicBlock>(CallOperandVal))
5674 return TLI.getPointerTy();
5676 llvm::Type *OpTy = CallOperandVal->getType();
5678 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5679 // If this is an indirect operand, the operand is a pointer to the
5682 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5684 report_fatal_error("Indirect operand for inline asm not a pointer!");
5685 OpTy = PtrTy->getElementType();
5688 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5689 if (StructType *STy = dyn_cast<StructType>(OpTy))
5690 if (STy->getNumElements() == 1)
5691 OpTy = STy->getElementType(0);
5693 // If OpTy is not a single value, it may be a struct/union that we
5694 // can tile with integers.
5695 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5696 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5705 OpTy = IntegerType::get(Context, BitSize);
5710 return TLI.getValueType(OpTy, true);
5714 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5716 } // end anonymous namespace
5718 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5719 /// specified operand. We prefer to assign virtual registers, to allow the
5720 /// register allocator to handle the assignment process. However, if the asm
5721 /// uses features that we can't model on machineinstrs, we have SDISel do the
5722 /// allocation. This produces generally horrible, but correct, code.
5724 /// OpInfo describes the operand.
5726 static void GetRegistersForValue(SelectionDAG &DAG,
5727 const TargetLowering &TLI,
5729 SDISelAsmOperandInfo &OpInfo) {
5730 LLVMContext &Context = *DAG.getContext();
5732 MachineFunction &MF = DAG.getMachineFunction();
5733 SmallVector<unsigned, 4> Regs;
5735 // If this is a constraint for a single physreg, or a constraint for a
5736 // register class, find it.
5737 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5738 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5739 OpInfo.ConstraintVT);
5741 unsigned NumRegs = 1;
5742 if (OpInfo.ConstraintVT != MVT::Other) {
5743 // If this is a FP input in an integer register (or visa versa) insert a bit
5744 // cast of the input value. More generally, handle any case where the input
5745 // value disagrees with the register class we plan to stick this in.
5746 if (OpInfo.Type == InlineAsm::isInput &&
5747 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5748 // Try to convert to the first EVT that the reg class contains. If the
5749 // types are identical size, use a bitcast to convert (e.g. two differing
5751 MVT RegVT = *PhysReg.second->vt_begin();
5752 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5753 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5754 RegVT, OpInfo.CallOperand);
5755 OpInfo.ConstraintVT = RegVT;
5756 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5757 // If the input is a FP value and we want it in FP registers, do a
5758 // bitcast to the corresponding integer type. This turns an f64 value
5759 // into i64, which can be passed with two i32 values on a 32-bit
5761 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5762 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5763 RegVT, OpInfo.CallOperand);
5764 OpInfo.ConstraintVT = RegVT;
5768 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5772 EVT ValueVT = OpInfo.ConstraintVT;
5774 // If this is a constraint for a specific physical register, like {r17},
5776 if (unsigned AssignedReg = PhysReg.first) {
5777 const TargetRegisterClass *RC = PhysReg.second;
5778 if (OpInfo.ConstraintVT == MVT::Other)
5779 ValueVT = *RC->vt_begin();
5781 // Get the actual register value type. This is important, because the user
5782 // may have asked for (e.g.) the AX register in i32 type. We need to
5783 // remember that AX is actually i16 to get the right extension.
5784 RegVT = *RC->vt_begin();
5786 // This is a explicit reference to a physical register.
5787 Regs.push_back(AssignedReg);
5789 // If this is an expanded reference, add the rest of the regs to Regs.
5791 TargetRegisterClass::iterator I = RC->begin();
5792 for (; *I != AssignedReg; ++I)
5793 assert(I != RC->end() && "Didn't find reg!");
5795 // Already added the first reg.
5797 for (; NumRegs; --NumRegs, ++I) {
5798 assert(I != RC->end() && "Ran out of registers to allocate!");
5803 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5807 // Otherwise, if this was a reference to an LLVM register class, create vregs
5808 // for this reference.
5809 if (const TargetRegisterClass *RC = PhysReg.second) {
5810 RegVT = *RC->vt_begin();
5811 if (OpInfo.ConstraintVT == MVT::Other)
5814 // Create the appropriate number of virtual registers.
5815 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5816 for (; NumRegs; --NumRegs)
5817 Regs.push_back(RegInfo.createVirtualRegister(RC));
5819 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5823 // Otherwise, we couldn't allocate enough registers for this.
5826 /// visitInlineAsm - Handle a call to an InlineAsm object.
5828 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5829 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5831 /// ConstraintOperands - Information about all of the constraints.
5832 SDISelAsmOperandInfoVector ConstraintOperands;
5834 TargetLowering::AsmOperandInfoVector
5835 TargetConstraints = TLI.ParseConstraints(CS);
5837 bool hasMemory = false;
5839 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5840 unsigned ResNo = 0; // ResNo - The result number of the next output.
5841 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5842 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5843 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5845 MVT OpVT = MVT::Other;
5847 // Compute the value type for each operand.
5848 switch (OpInfo.Type) {
5849 case InlineAsm::isOutput:
5850 // Indirect outputs just consume an argument.
5851 if (OpInfo.isIndirect) {
5852 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5856 // The return value of the call is this value. As such, there is no
5857 // corresponding argument.
5858 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5859 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5860 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
5862 assert(ResNo == 0 && "Asm only has one result!");
5863 OpVT = TLI.getSimpleValueType(CS.getType());
5867 case InlineAsm::isInput:
5868 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5870 case InlineAsm::isClobber:
5875 // If this is an input or an indirect output, process the call argument.
5876 // BasicBlocks are labels, currently appearing only in asm's.
5877 if (OpInfo.CallOperandVal) {
5878 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5879 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5881 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5884 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD).
5888 OpInfo.ConstraintVT = OpVT;
5890 // Indirect operand accesses access memory.
5891 if (OpInfo.isIndirect)
5894 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5895 TargetLowering::ConstraintType
5896 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5897 if (CType == TargetLowering::C_Memory) {
5905 SDValue Chain, Flag;
5907 // We won't need to flush pending loads if this asm doesn't touch
5908 // memory and is nonvolatile.
5909 if (hasMemory || IA->hasSideEffects())
5912 Chain = DAG.getRoot();
5914 // Second pass over the constraints: compute which constraint option to use
5915 // and assign registers to constraints that want a specific physreg.
5916 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5917 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5919 // If this is an output operand with a matching input operand, look up the
5920 // matching input. If their types mismatch, e.g. one is an integer, the
5921 // other is floating point, or their sizes are different, flag it as an
5923 if (OpInfo.hasMatchingInput()) {
5924 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5926 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5927 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5928 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5929 OpInfo.ConstraintVT);
5930 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5931 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
5932 Input.ConstraintVT);
5933 if ((OpInfo.ConstraintVT.isInteger() !=
5934 Input.ConstraintVT.isInteger()) ||
5935 (MatchRC.second != InputRC.second)) {
5936 report_fatal_error("Unsupported asm: input constraint"
5937 " with a matching output constraint of"
5938 " incompatible type!");
5940 Input.ConstraintVT = OpInfo.ConstraintVT;
5944 // Compute the constraint code and ConstraintType to use.
5945 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5947 // If this is a memory input, and if the operand is not indirect, do what we
5948 // need to to provide an address for the memory input.
5949 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5950 !OpInfo.isIndirect) {
5951 assert((OpInfo.isMultipleAlternative ||
5952 (OpInfo.Type == InlineAsm::isInput)) &&
5953 "Can only indirectify direct input operands!");
5955 // Memory operands really want the address of the value. If we don't have
5956 // an indirect input, put it in the constpool if we can, otherwise spill
5957 // it to a stack slot.
5958 // TODO: This isn't quite right. We need to handle these according to
5959 // the addressing mode that the constraint wants. Also, this may take
5960 // an additional register for the computation and we don't want that
5963 // If the operand is a float, integer, or vector constant, spill to a
5964 // constant pool entry to get its address.
5965 const Value *OpVal = OpInfo.CallOperandVal;
5966 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5967 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5968 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5969 TLI.getPointerTy());
5971 // Otherwise, create a stack slot and emit a store to it before the
5973 Type *Ty = OpVal->getType();
5974 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5975 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5976 MachineFunction &MF = DAG.getMachineFunction();
5977 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5978 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5979 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5980 OpInfo.CallOperand, StackSlot,
5981 MachinePointerInfo::getFixedStack(SSFI),
5983 OpInfo.CallOperand = StackSlot;
5986 // There is no longer a Value* corresponding to this operand.
5987 OpInfo.CallOperandVal = 0;
5989 // It is now an indirect operand.
5990 OpInfo.isIndirect = true;
5993 // If this constraint is for a specific register, allocate it before
5995 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5996 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
5999 // Second pass - Loop over all of the operands, assigning virtual or physregs
6000 // to register class operands.
6001 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6002 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6004 // C_Register operands have already been allocated, Other/Memory don't need
6006 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6007 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6010 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6011 std::vector<SDValue> AsmNodeOperands;
6012 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6013 AsmNodeOperands.push_back(
6014 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6015 TLI.getPointerTy()));
6017 // If we have a !srcloc metadata node associated with it, we want to attach
6018 // this to the ultimately generated inline asm machineinstr. To do this, we
6019 // pass in the third operand as this (potentially null) inline asm MDNode.
6020 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6021 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6023 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6024 // bits as operand 3.
6025 unsigned ExtraInfo = 0;
6026 if (IA->hasSideEffects())
6027 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6028 if (IA->isAlignStack())
6029 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6030 // Set the asm dialect.
6031 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6033 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6034 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6035 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6037 // Compute the constraint code and ConstraintType to use.
6038 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6040 // Ideally, we would only check against memory constraints. However, the
6041 // meaning of an other constraint can be target-specific and we can't easily
6042 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6043 // for other constriants as well.
6044 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6045 OpInfo.ConstraintType == TargetLowering::C_Other) {
6046 if (OpInfo.Type == InlineAsm::isInput)
6047 ExtraInfo |= InlineAsm::Extra_MayLoad;
6048 else if (OpInfo.Type == InlineAsm::isOutput)
6049 ExtraInfo |= InlineAsm::Extra_MayStore;
6053 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6054 TLI.getPointerTy()));
6056 // Loop over all of the inputs, copying the operand values into the
6057 // appropriate registers and processing the output regs.
6058 RegsForValue RetValRegs;
6060 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6061 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6063 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6064 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6066 switch (OpInfo.Type) {
6067 case InlineAsm::isOutput: {
6068 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6069 OpInfo.ConstraintType != TargetLowering::C_Register) {
6070 // Memory output, or 'other' output (e.g. 'X' constraint).
6071 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6073 // Add information to the INLINEASM node to know about this output.
6074 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6075 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6076 TLI.getPointerTy()));
6077 AsmNodeOperands.push_back(OpInfo.CallOperand);
6081 // Otherwise, this is a register or register class output.
6083 // Copy the output from the appropriate register. Find a register that
6085 if (OpInfo.AssignedRegs.Regs.empty()) {
6086 LLVMContext &Ctx = *DAG.getContext();
6087 Ctx.emitError(CS.getInstruction(),
6088 "couldn't allocate output register for constraint '" +
6089 Twine(OpInfo.ConstraintCode) + "'");
6093 // If this is an indirect operand, store through the pointer after the
6095 if (OpInfo.isIndirect) {
6096 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6097 OpInfo.CallOperandVal));
6099 // This is the result value of the call.
6100 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6101 // Concatenate this output onto the outputs list.
6102 RetValRegs.append(OpInfo.AssignedRegs);
6105 // Add information to the INLINEASM node to know that this register is
6107 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6108 InlineAsm::Kind_RegDefEarlyClobber :
6109 InlineAsm::Kind_RegDef,
6116 case InlineAsm::isInput: {
6117 SDValue InOperandVal = OpInfo.CallOperand;
6119 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6120 // If this is required to match an output register we have already set,
6121 // just use its register.
6122 unsigned OperandNo = OpInfo.getMatchedOperand();
6124 // Scan until we find the definition we already emitted of this operand.
6125 // When we find it, create a RegsForValue operand.
6126 unsigned CurOp = InlineAsm::Op_FirstOperand;
6127 for (; OperandNo; --OperandNo) {
6128 // Advance to the next operand.
6130 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6131 assert((InlineAsm::isRegDefKind(OpFlag) ||
6132 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6133 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6134 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6138 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6139 if (InlineAsm::isRegDefKind(OpFlag) ||
6140 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6141 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6142 if (OpInfo.isIndirect) {
6143 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6144 LLVMContext &Ctx = *DAG.getContext();
6145 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6146 " don't know how to handle tied "
6147 "indirect register inputs");
6150 RegsForValue MatchedRegs;
6151 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6152 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6153 MatchedRegs.RegVTs.push_back(RegVT);
6154 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6155 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6157 MatchedRegs.Regs.push_back
6158 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
6160 // Use the produced MatchedRegs object to
6161 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6162 Chain, &Flag, CS.getInstruction());
6163 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6164 true, OpInfo.getMatchedOperand(),
6165 DAG, AsmNodeOperands);
6169 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6170 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6171 "Unexpected number of operands");
6172 // Add information to the INLINEASM node to know about this input.
6173 // See InlineAsm.h isUseOperandTiedToDef.
6174 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6175 OpInfo.getMatchedOperand());
6176 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6177 TLI.getPointerTy()));
6178 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6182 // Treat indirect 'X' constraint as memory.
6183 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6185 OpInfo.ConstraintType = TargetLowering::C_Memory;
6187 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6188 std::vector<SDValue> Ops;
6189 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6192 LLVMContext &Ctx = *DAG.getContext();
6193 Ctx.emitError(CS.getInstruction(),
6194 "invalid operand for inline asm constraint '" +
6195 Twine(OpInfo.ConstraintCode) + "'");
6199 // Add information to the INLINEASM node to know about this input.
6200 unsigned ResOpType =
6201 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6202 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6203 TLI.getPointerTy()));
6204 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6208 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6209 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6210 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6211 "Memory operands expect pointer values");
6213 // Add information to the INLINEASM node to know about this input.
6214 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6215 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6216 TLI.getPointerTy()));
6217 AsmNodeOperands.push_back(InOperandVal);
6221 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6222 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6223 "Unknown constraint type!");
6225 // TODO: Support this.
6226 if (OpInfo.isIndirect) {
6227 LLVMContext &Ctx = *DAG.getContext();
6228 Ctx.emitError(CS.getInstruction(),
6229 "Don't know how to handle indirect register inputs yet "
6230 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'");
6234 // Copy the input into the appropriate registers.
6235 if (OpInfo.AssignedRegs.Regs.empty()) {
6236 LLVMContext &Ctx = *DAG.getContext();
6237 Ctx.emitError(CS.getInstruction(),
6238 "couldn't allocate input reg for constraint '" +
6239 Twine(OpInfo.ConstraintCode) + "'");
6243 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6244 Chain, &Flag, CS.getInstruction());
6246 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6247 DAG, AsmNodeOperands);
6250 case InlineAsm::isClobber: {
6251 // Add the clobbered value to the operand list, so that the register
6252 // allocator is aware that the physreg got clobbered.
6253 if (!OpInfo.AssignedRegs.Regs.empty())
6254 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6262 // Finish up input operands. Set the input chain and add the flag last.
6263 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6264 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6266 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6267 DAG.getVTList(MVT::Other, MVT::Glue),
6268 &AsmNodeOperands[0], AsmNodeOperands.size());
6269 Flag = Chain.getValue(1);
6271 // If this asm returns a register value, copy the result from that register
6272 // and set it as the value of the call.
6273 if (!RetValRegs.Regs.empty()) {
6274 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6275 Chain, &Flag, CS.getInstruction());
6277 // FIXME: Why don't we do this for inline asms with MRVs?
6278 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6279 EVT ResultType = TLI.getValueType(CS.getType());
6281 // If any of the results of the inline asm is a vector, it may have the
6282 // wrong width/num elts. This can happen for register classes that can
6283 // contain multiple different value types. The preg or vreg allocated may
6284 // not have the same VT as was expected. Convert it to the right type
6285 // with bit_convert.
6286 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6287 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6290 } else if (ResultType != Val.getValueType() &&
6291 ResultType.isInteger() && Val.getValueType().isInteger()) {
6292 // If a result value was tied to an input value, the computed result may
6293 // have a wider width than the expected result. Extract the relevant
6295 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6298 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6301 setValue(CS.getInstruction(), Val);
6302 // Don't need to use this as a chain in this case.
6303 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6307 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6309 // Process indirect outputs, first output all of the flagged copies out of
6311 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6312 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6313 const Value *Ptr = IndirectStoresToEmit[i].second;
6314 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6316 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6319 // Emit the non-flagged stores from the physregs.
6320 SmallVector<SDValue, 8> OutChains;
6321 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6322 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6323 StoresToEmit[i].first,
6324 getValue(StoresToEmit[i].second),
6325 MachinePointerInfo(StoresToEmit[i].second),
6327 OutChains.push_back(Val);
6330 if (!OutChains.empty())
6331 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6332 &OutChains[0], OutChains.size());
6337 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6338 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6339 MVT::Other, getRoot(),
6340 getValue(I.getArgOperand(0)),
6341 DAG.getSrcValue(I.getArgOperand(0))));
6344 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6345 const DataLayout &TD = *TLI.getDataLayout();
6346 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6347 getRoot(), getValue(I.getOperand(0)),
6348 DAG.getSrcValue(I.getOperand(0)),
6349 TD.getABITypeAlignment(I.getType()));
6351 DAG.setRoot(V.getValue(1));
6354 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6355 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6356 MVT::Other, getRoot(),
6357 getValue(I.getArgOperand(0)),
6358 DAG.getSrcValue(I.getArgOperand(0))));
6361 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6362 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6363 MVT::Other, getRoot(),
6364 getValue(I.getArgOperand(0)),
6365 getValue(I.getArgOperand(1)),
6366 DAG.getSrcValue(I.getArgOperand(0)),
6367 DAG.getSrcValue(I.getArgOperand(1))));
6370 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6371 /// implementation, which just calls LowerCall.
6372 /// FIXME: When all targets are
6373 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6374 std::pair<SDValue, SDValue>
6375 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6376 // Handle all of the outgoing arguments.
6378 CLI.OutVals.clear();
6379 ArgListTy &Args = CLI.Args;
6380 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6381 SmallVector<EVT, 4> ValueVTs;
6382 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6383 for (unsigned Value = 0, NumValues = ValueVTs.size();
6384 Value != NumValues; ++Value) {
6385 EVT VT = ValueVTs[Value];
6386 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6387 SDValue Op = SDValue(Args[i].Node.getNode(),
6388 Args[i].Node.getResNo() + Value);
6389 ISD::ArgFlagsTy Flags;
6390 unsigned OriginalAlignment =
6391 getDataLayout()->getABITypeAlignment(ArgTy);
6397 if (Args[i].isInReg)
6401 if (Args[i].isByVal) {
6403 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6404 Type *ElementTy = Ty->getElementType();
6405 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6406 // For ByVal, alignment should come from FE. BE will guess if this
6407 // info is not there but there are cases it cannot get right.
6408 unsigned FrameAlign;
6409 if (Args[i].Alignment)
6410 FrameAlign = Args[i].Alignment;
6412 FrameAlign = getByValTypeAlignment(ElementTy);
6413 Flags.setByValAlign(FrameAlign);
6417 Flags.setOrigAlign(OriginalAlignment);
6419 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6420 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6421 SmallVector<SDValue, 4> Parts(NumParts);
6422 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6425 ExtendKind = ISD::SIGN_EXTEND;
6426 else if (Args[i].isZExt)
6427 ExtendKind = ISD::ZERO_EXTEND;
6429 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
6430 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind);
6432 for (unsigned j = 0; j != NumParts; ++j) {
6433 // if it isn't first piece, alignment must be 1
6434 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6435 i < CLI.NumFixedArgs,
6436 i, j*Parts[j].getValueType().getStoreSize());
6437 if (NumParts > 1 && j == 0)
6438 MyFlags.Flags.setSplit();
6440 MyFlags.Flags.setOrigAlign(1);
6442 CLI.Outs.push_back(MyFlags);
6443 CLI.OutVals.push_back(Parts[j]);
6448 // Handle the incoming return values from the call.
6450 SmallVector<EVT, 4> RetTys;
6451 ComputeValueVTs(*this, CLI.RetTy, RetTys);
6452 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6454 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6455 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6456 for (unsigned i = 0; i != NumRegs; ++i) {
6457 ISD::InputArg MyFlags;
6458 MyFlags.VT = RegisterVT;
6459 MyFlags.Used = CLI.IsReturnValueUsed;
6461 MyFlags.Flags.setSExt();
6463 MyFlags.Flags.setZExt();
6465 MyFlags.Flags.setInReg();
6466 CLI.Ins.push_back(MyFlags);
6470 SmallVector<SDValue, 4> InVals;
6471 CLI.Chain = LowerCall(CLI, InVals);
6473 // Verify that the target's LowerCall behaved as expected.
6474 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6475 "LowerCall didn't return a valid chain!");
6476 assert((!CLI.IsTailCall || InVals.empty()) &&
6477 "LowerCall emitted a return value for a tail call!");
6478 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6479 "LowerCall didn't emit the correct number of values!");
6481 // For a tail call, the return value is merely live-out and there aren't
6482 // any nodes in the DAG representing it. Return a special value to
6483 // indicate that a tail call has been emitted and no more Instructions
6484 // should be processed in the current block.
6485 if (CLI.IsTailCall) {
6486 CLI.DAG.setRoot(CLI.Chain);
6487 return std::make_pair(SDValue(), SDValue());
6490 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6491 assert(InVals[i].getNode() &&
6492 "LowerCall emitted a null value!");
6493 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6494 "LowerCall emitted a value with the wrong type!");
6497 // Collect the legal value parts into potentially illegal values
6498 // that correspond to the original function's return values.
6499 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6501 AssertOp = ISD::AssertSext;
6502 else if (CLI.RetZExt)
6503 AssertOp = ISD::AssertZext;
6504 SmallVector<SDValue, 4> ReturnValues;
6505 unsigned CurReg = 0;
6506 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6508 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6509 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6511 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6512 NumRegs, RegisterVT, VT, NULL,
6517 // For a function returning void, there is no return value. We can't create
6518 // such a node, so we just return a null return value in that case. In
6519 // that case, nothing will actually look at the value.
6520 if (ReturnValues.empty())
6521 return std::make_pair(SDValue(), CLI.Chain);
6523 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6524 CLI.DAG.getVTList(&RetTys[0], RetTys.size()),
6525 &ReturnValues[0], ReturnValues.size());
6526 return std::make_pair(Res, CLI.Chain);
6529 void TargetLowering::LowerOperationWrapper(SDNode *N,
6530 SmallVectorImpl<SDValue> &Results,
6531 SelectionDAG &DAG) const {
6532 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6534 Results.push_back(Res);
6537 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6538 llvm_unreachable("LowerOperation not implemented for this target!");
6542 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6543 SDValue Op = getNonRegisterValue(V);
6544 assert((Op.getOpcode() != ISD::CopyFromReg ||
6545 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6546 "Copy from a reg to the same reg!");
6547 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6549 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6550 SDValue Chain = DAG.getEntryNode();
6551 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0, V);
6552 PendingExports.push_back(Chain);
6555 #include "llvm/CodeGen/SelectionDAGISel.h"
6557 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6558 /// entry block, return true. This includes arguments used by switches, since
6559 /// the switch may expand into multiple basic blocks.
6560 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6561 // With FastISel active, we may be splitting blocks, so force creation
6562 // of virtual registers for all non-dead arguments.
6564 return A->use_empty();
6566 const BasicBlock *Entry = A->getParent()->begin();
6567 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6569 const User *U = *UI;
6570 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6571 return false; // Use not in entry block.
6576 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6577 // If this is the entry block, emit arguments.
6578 const Function &F = *LLVMBB->getParent();
6579 SelectionDAG &DAG = SDB->DAG;
6580 DebugLoc dl = SDB->getCurDebugLoc();
6581 const DataLayout *TD = TLI.getDataLayout();
6582 SmallVector<ISD::InputArg, 16> Ins;
6584 // Check whether the function can return without sret-demotion.
6585 SmallVector<ISD::OutputArg, 4> Outs;
6586 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6589 if (!FuncInfo->CanLowerReturn) {
6590 // Put in an sret pointer parameter before all the other parameters.
6591 SmallVector<EVT, 1> ValueVTs;
6592 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6594 // NOTE: Assuming that a pointer will never break down to more than one VT
6596 ISD::ArgFlagsTy Flags;
6598 MVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6599 ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0);
6600 Ins.push_back(RetArg);
6603 // Set up the incoming argument description vector.
6605 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6606 I != E; ++I, ++Idx) {
6607 SmallVector<EVT, 4> ValueVTs;
6608 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6609 bool isArgValueUsed = !I->use_empty();
6610 for (unsigned Value = 0, NumValues = ValueVTs.size();
6611 Value != NumValues; ++Value) {
6612 EVT VT = ValueVTs[Value];
6613 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6614 ISD::ArgFlagsTy Flags;
6615 unsigned OriginalAlignment =
6616 TD->getABITypeAlignment(ArgTy);
6618 if (F.getParamAttributes(Idx).hasAttribute(Attribute::ZExt))
6620 if (F.getParamAttributes(Idx).hasAttribute(Attribute::SExt))
6622 if (F.getParamAttributes(Idx).hasAttribute(Attribute::InReg))
6624 if (F.getParamAttributes(Idx).hasAttribute(Attribute::StructRet))
6626 if (F.getParamAttributes(Idx).hasAttribute(Attribute::ByVal)) {
6628 PointerType *Ty = cast<PointerType>(I->getType());
6629 Type *ElementTy = Ty->getElementType();
6630 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6631 // For ByVal, alignment should be passed from FE. BE will guess if
6632 // this info is not there but there are cases it cannot get right.
6633 unsigned FrameAlign;
6634 if (F.getParamAlignment(Idx))
6635 FrameAlign = F.getParamAlignment(Idx);
6637 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6638 Flags.setByValAlign(FrameAlign);
6640 if (F.getParamAttributes(Idx).hasAttribute(Attribute::Nest))
6642 Flags.setOrigAlign(OriginalAlignment);
6644 MVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6645 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6646 for (unsigned i = 0; i != NumRegs; ++i) {
6647 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed,
6648 Idx-1, i*RegisterVT.getStoreSize());
6649 if (NumRegs > 1 && i == 0)
6650 MyFlags.Flags.setSplit();
6651 // if it isn't first piece, alignment must be 1
6653 MyFlags.Flags.setOrigAlign(1);
6654 Ins.push_back(MyFlags);
6659 // Call the target to set up the argument values.
6660 SmallVector<SDValue, 8> InVals;
6661 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6665 // Verify that the target's LowerFormalArguments behaved as expected.
6666 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6667 "LowerFormalArguments didn't return a valid chain!");
6668 assert(InVals.size() == Ins.size() &&
6669 "LowerFormalArguments didn't emit the correct number of values!");
6671 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6672 assert(InVals[i].getNode() &&
6673 "LowerFormalArguments emitted a null value!");
6674 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6675 "LowerFormalArguments emitted a value with the wrong type!");
6679 // Update the DAG with the new chain value resulting from argument lowering.
6680 DAG.setRoot(NewRoot);
6682 // Set up the argument values.
6685 if (!FuncInfo->CanLowerReturn) {
6686 // Create a virtual register for the sret pointer, and put in a copy
6687 // from the sret argument into it.
6688 SmallVector<EVT, 1> ValueVTs;
6689 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6690 MVT VT = ValueVTs[0].getSimpleVT();
6691 MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6692 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6693 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6694 RegVT, VT, NULL, AssertOp);
6696 MachineFunction& MF = SDB->DAG.getMachineFunction();
6697 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6698 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6699 FuncInfo->DemoteRegister = SRetReg;
6700 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6702 DAG.setRoot(NewRoot);
6704 // i indexes lowered arguments. Bump it past the hidden sret argument.
6705 // Idx indexes LLVM arguments. Don't touch it.
6709 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6711 SmallVector<SDValue, 4> ArgValues;
6712 SmallVector<EVT, 4> ValueVTs;
6713 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6714 unsigned NumValues = ValueVTs.size();
6716 // If this argument is unused then remember its value. It is used to generate
6717 // debugging information.
6718 if (I->use_empty() && NumValues)
6719 SDB->setUnusedArgValue(I, InVals[i]);
6721 for (unsigned Val = 0; Val != NumValues; ++Val) {
6722 EVT VT = ValueVTs[Val];
6723 MVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6724 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6726 if (!I->use_empty()) {
6727 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6728 if (F.getParamAttributes(Idx).hasAttribute(Attribute::SExt))
6729 AssertOp = ISD::AssertSext;
6730 else if (F.getParamAttributes(Idx).hasAttribute(Attribute::ZExt))
6731 AssertOp = ISD::AssertZext;
6733 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6734 NumParts, PartVT, VT,
6741 // We don't need to do anything else for unused arguments.
6742 if (ArgValues.empty())
6745 // Note down frame index.
6746 if (FrameIndexSDNode *FI =
6747 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6748 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6750 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6751 SDB->getCurDebugLoc());
6753 SDB->setValue(I, Res);
6754 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6755 if (LoadSDNode *LNode =
6756 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6757 if (FrameIndexSDNode *FI =
6758 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6759 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6762 // If this argument is live outside of the entry block, insert a copy from
6763 // wherever we got it to the vreg that other BB's will reference it as.
6764 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6765 // If we can, though, try to skip creating an unnecessary vreg.
6766 // FIXME: This isn't very clean... it would be nice to make this more
6767 // general. It's also subtly incompatible with the hacks FastISel
6769 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6770 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6771 FuncInfo->ValueMap[I] = Reg;
6775 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6776 FuncInfo->InitializeRegForValue(I);
6777 SDB->CopyToExportRegsIfNeeded(I);
6781 assert(i == InVals.size() && "Argument register count mismatch!");
6783 // Finally, if the target has anything special to do, allow it to do so.
6784 // FIXME: this should insert code into the DAG!
6785 EmitFunctionEntryCode();
6788 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6789 /// ensure constants are generated when needed. Remember the virtual registers
6790 /// that need to be added to the Machine PHI nodes as input. We cannot just
6791 /// directly add them, because expansion might result in multiple MBB's for one
6792 /// BB. As such, the start of the BB might correspond to a different MBB than
6796 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6797 const TerminatorInst *TI = LLVMBB->getTerminator();
6799 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6801 // Check successor nodes' PHI nodes that expect a constant to be available
6803 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6804 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6805 if (!isa<PHINode>(SuccBB->begin())) continue;
6806 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6808 // If this terminator has multiple identical successors (common for
6809 // switches), only handle each succ once.
6810 if (!SuccsHandled.insert(SuccMBB)) continue;
6812 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6814 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6815 // nodes and Machine PHI nodes, but the incoming operands have not been
6817 for (BasicBlock::const_iterator I = SuccBB->begin();
6818 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6819 // Ignore dead phi's.
6820 if (PN->use_empty()) continue;
6823 if (PN->getType()->isEmptyTy())
6827 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6829 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6830 unsigned &RegOut = ConstantsOut[C];
6832 RegOut = FuncInfo.CreateRegs(C->getType());
6833 CopyValueToVirtualRegister(C, RegOut);
6837 DenseMap<const Value *, unsigned>::iterator I =
6838 FuncInfo.ValueMap.find(PHIOp);
6839 if (I != FuncInfo.ValueMap.end())
6842 assert(isa<AllocaInst>(PHIOp) &&
6843 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6844 "Didn't codegen value into a register!??");
6845 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6846 CopyValueToVirtualRegister(PHIOp, Reg);
6850 // Remember that this register needs to added to the machine PHI node as
6851 // the input for this MBB.
6852 SmallVector<EVT, 4> ValueVTs;
6853 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6854 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6855 EVT VT = ValueVTs[vti];
6856 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6857 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6858 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6859 Reg += NumRegisters;
6863 ConstantsOut.clear();