1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
73 // Limit the width of DAG chains. This is important in general to prevent
74 // prevent DAG-based analysis from blowing up. For example, alias analysis and
75 // load clustering may not complete in reasonable time. It is difficult to
76 // recognize and avoid this situation within each individual analysis, and
77 // future analyses are likely to have the same behavior. Limiting DAG width is
78 // the safe approach, and will be especially important with global DAGs.
80 // MaxParallelChains default is arbitrarily high to avoid affecting
81 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
82 // sequence over this should have been converted to llvm.memcpy by the
83 // frontend. It easy to induce this behavior with .ll code such as:
84 // %buffer = alloca [4096 x i8]
85 // %data = load [4096 x i8]* %argPtr
86 // store [4096 x i8] %data, [4096 x i8]* %buffer
87 static cl::opt<unsigned>
88 MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"),
89 cl::init(64), cl::Hidden);
91 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
92 const SDValue *Parts, unsigned NumParts,
93 EVT PartVT, EVT ValueVT);
95 /// getCopyFromParts - Create a value that contains the specified legal parts
96 /// combined into the value they represent. If the parts combine to a type
97 /// larger then ValueVT then AssertOp can be used to specify whether the extra
98 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
99 /// (ISD::AssertSext).
100 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
101 const SDValue *Parts,
102 unsigned NumParts, EVT PartVT, EVT ValueVT,
103 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
104 if (ValueVT.isVector())
105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
107 assert(NumParts > 0 && "No parts to assemble!");
108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
109 SDValue Val = Parts[0];
112 // Assemble the value from multiple parts.
113 if (ValueVT.isInteger()) {
114 unsigned PartBits = PartVT.getSizeInBits();
115 unsigned ValueBits = ValueVT.getSizeInBits();
117 // Assemble the power of 2 part.
118 unsigned RoundParts = NumParts & (NumParts - 1) ?
119 1 << Log2_32(NumParts) : NumParts;
120 unsigned RoundBits = PartBits * RoundParts;
121 EVT RoundVT = RoundBits == ValueBits ?
122 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
125 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
127 if (RoundParts > 2) {
128 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
130 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
131 RoundParts / 2, PartVT, HalfVT);
133 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
134 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
137 if (TLI.isBigEndian())
140 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
142 if (RoundParts < NumParts) {
143 // Assemble the trailing non-power-of-2 part.
144 unsigned OddParts = NumParts - RoundParts;
145 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
146 Hi = getCopyFromParts(DAG, DL,
147 Parts + RoundParts, OddParts, PartVT, OddVT);
149 // Combine the round and odd parts.
151 if (TLI.isBigEndian())
153 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
154 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
155 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
156 DAG.getConstant(Lo.getValueType().getSizeInBits(),
157 TLI.getPointerTy()));
158 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
159 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
161 } else if (PartVT.isFloatingPoint()) {
162 // FP split into multiple FP parts (for ppcf128)
163 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
166 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
167 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
168 if (TLI.isBigEndian())
170 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
172 // FP split into integer parts (soft fp)
173 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
174 !PartVT.isVector() && "Unexpected split");
175 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
176 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
180 // There is now one part, held in Val. Correct it to match ValueVT.
181 PartVT = Val.getValueType();
183 if (PartVT == ValueVT)
186 if (PartVT.isInteger() && ValueVT.isInteger()) {
187 if (ValueVT.bitsLT(PartVT)) {
188 // For a truncate, see if we have any information to
189 // indicate whether the truncated bits will always be
190 // zero or sign-extension.
191 if (AssertOp != ISD::DELETED_NODE)
192 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
193 DAG.getValueType(ValueVT));
194 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
196 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
199 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
200 // FP_ROUND's are always exact here.
201 if (ValueVT.bitsLT(Val.getValueType()))
202 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
203 DAG.getIntPtrConstant(1));
205 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
208 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
209 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
211 llvm_unreachable("Unknown mismatch!");
215 /// getCopyFromParts - Create a value that contains the specified legal parts
216 /// combined into the value they represent. If the parts combine to a type
217 /// larger then ValueVT then AssertOp can be used to specify whether the extra
218 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
219 /// (ISD::AssertSext).
220 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
221 const SDValue *Parts, unsigned NumParts,
222 EVT PartVT, EVT ValueVT) {
223 assert(ValueVT.isVector() && "Not a vector value");
224 assert(NumParts > 0 && "No parts to assemble!");
225 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
226 SDValue Val = Parts[0];
228 // Handle a multi-element vector.
230 EVT IntermediateVT, RegisterVT;
231 unsigned NumIntermediates;
233 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
234 NumIntermediates, RegisterVT);
235 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
236 NumParts = NumRegs; // Silence a compiler warning.
237 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
238 assert(RegisterVT == Parts[0].getValueType() &&
239 "Part type doesn't match part!");
241 // Assemble the parts into intermediate operands.
242 SmallVector<SDValue, 8> Ops(NumIntermediates);
243 if (NumIntermediates == NumParts) {
244 // If the register was not expanded, truncate or copy the value,
246 for (unsigned i = 0; i != NumParts; ++i)
247 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
248 PartVT, IntermediateVT);
249 } else if (NumParts > 0) {
250 // If the intermediate type was expanded, build the intermediate
251 // operands from the parts.
252 assert(NumParts % NumIntermediates == 0 &&
253 "Must expand into a divisible number of parts!");
254 unsigned Factor = NumParts / NumIntermediates;
255 for (unsigned i = 0; i != NumIntermediates; ++i)
256 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
257 PartVT, IntermediateVT);
260 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
261 // intermediate operands.
262 Val = DAG.getNode(IntermediateVT.isVector() ?
263 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
264 ValueVT, &Ops[0], NumIntermediates);
267 // There is now one part, held in Val. Correct it to match ValueVT.
268 PartVT = Val.getValueType();
270 if (PartVT == ValueVT)
273 if (PartVT.isVector()) {
274 // If the element type of the source/dest vectors are the same, but the
275 // parts vector has more elements than the value vector, then we have a
276 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
278 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
279 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
280 "Cannot narrow, it would be a lossy transformation");
281 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
282 DAG.getIntPtrConstant(0));
285 // Vector/Vector bitcast.
286 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
289 assert(ValueVT.getVectorElementType() == PartVT &&
290 ValueVT.getVectorNumElements() == 1 &&
291 "Only trivial scalar-to-vector conversions should get here!");
292 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
298 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
299 SDValue Val, SDValue *Parts, unsigned NumParts,
302 /// getCopyToParts - Create a series of nodes that contain the specified value
303 /// split into legal parts. If the parts contain more bits than Val, then, for
304 /// integers, ExtendKind can be used to specify how to generate the extra bits.
305 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
306 SDValue Val, SDValue *Parts, unsigned NumParts,
308 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
309 EVT ValueVT = Val.getValueType();
311 // Handle the vector case separately.
312 if (ValueVT.isVector())
313 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
315 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
316 unsigned PartBits = PartVT.getSizeInBits();
317 unsigned OrigNumParts = NumParts;
318 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
323 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
324 if (PartVT == ValueVT) {
325 assert(NumParts == 1 && "No-op copy with multiple parts!");
330 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
331 // If the parts cover more bits than the value has, promote the value.
332 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
333 assert(NumParts == 1 && "Do not know what to promote to!");
334 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
336 assert(PartVT.isInteger() && ValueVT.isInteger() &&
337 "Unknown mismatch!");
338 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
339 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
341 } else if (PartBits == ValueVT.getSizeInBits()) {
342 // Different types of the same size.
343 assert(NumParts == 1 && PartVT != ValueVT);
344 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
345 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
346 // If the parts cover less bits than value has, truncate the value.
347 assert(PartVT.isInteger() && ValueVT.isInteger() &&
348 "Unknown mismatch!");
349 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
350 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
353 // The value may have changed - recompute ValueVT.
354 ValueVT = Val.getValueType();
355 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
356 "Failed to tile the value with PartVT!");
359 assert(PartVT == ValueVT && "Type conversion failed!");
364 // Expand the value into multiple parts.
365 if (NumParts & (NumParts - 1)) {
366 // The number of parts is not a power of 2. Split off and copy the tail.
367 assert(PartVT.isInteger() && ValueVT.isInteger() &&
368 "Do not know what to expand to!");
369 unsigned RoundParts = 1 << Log2_32(NumParts);
370 unsigned RoundBits = RoundParts * PartBits;
371 unsigned OddParts = NumParts - RoundParts;
372 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
373 DAG.getIntPtrConstant(RoundBits));
374 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
376 if (TLI.isBigEndian())
377 // The odd parts were reversed by getCopyToParts - unreverse them.
378 std::reverse(Parts + RoundParts, Parts + NumParts);
380 NumParts = RoundParts;
381 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
382 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
385 // The number of parts is a power of 2. Repeatedly bisect the value using
387 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
388 EVT::getIntegerVT(*DAG.getContext(),
389 ValueVT.getSizeInBits()),
392 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
393 for (unsigned i = 0; i < NumParts; i += StepSize) {
394 unsigned ThisBits = StepSize * PartBits / 2;
395 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
396 SDValue &Part0 = Parts[i];
397 SDValue &Part1 = Parts[i+StepSize/2];
399 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
400 ThisVT, Part0, DAG.getIntPtrConstant(1));
401 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
402 ThisVT, Part0, DAG.getIntPtrConstant(0));
404 if (ThisBits == PartBits && ThisVT != PartVT) {
405 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
406 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
411 if (TLI.isBigEndian())
412 std::reverse(Parts, Parts + OrigNumParts);
416 /// getCopyToPartsVector - Create a series of nodes that contain the specified
417 /// value split into legal parts.
418 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
419 SDValue Val, SDValue *Parts, unsigned NumParts,
421 EVT ValueVT = Val.getValueType();
422 assert(ValueVT.isVector() && "Not a vector");
423 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
426 if (PartVT == ValueVT) {
428 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
429 // Bitconvert vector->vector case.
430 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
431 } else if (PartVT.isVector() &&
432 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
433 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
434 EVT ElementVT = PartVT.getVectorElementType();
435 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
437 SmallVector<SDValue, 16> Ops;
438 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
439 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
440 ElementVT, Val, DAG.getIntPtrConstant(i)));
442 for (unsigned i = ValueVT.getVectorNumElements(),
443 e = PartVT.getVectorNumElements(); i != e; ++i)
444 Ops.push_back(DAG.getUNDEF(ElementVT));
446 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
448 // FIXME: Use CONCAT for 2x -> 4x.
450 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
451 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
453 // Vector -> scalar conversion.
454 assert(ValueVT.getVectorElementType() == PartVT &&
455 ValueVT.getVectorNumElements() == 1 &&
456 "Only trivial vector-to-scalar conversions should get here!");
457 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
458 PartVT, Val, DAG.getIntPtrConstant(0));
465 // Handle a multi-element vector.
466 EVT IntermediateVT, RegisterVT;
467 unsigned NumIntermediates;
468 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
470 NumIntermediates, RegisterVT);
471 unsigned NumElements = ValueVT.getVectorNumElements();
473 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
474 NumParts = NumRegs; // Silence a compiler warning.
475 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
477 // Split the vector into intermediate operands.
478 SmallVector<SDValue, 8> Ops(NumIntermediates);
479 for (unsigned i = 0; i != NumIntermediates; ++i) {
480 if (IntermediateVT.isVector())
481 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
483 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
485 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
486 IntermediateVT, Val, DAG.getIntPtrConstant(i));
489 // Split the intermediate operands into legal parts.
490 if (NumParts == NumIntermediates) {
491 // If the register was not expanded, promote or copy the value,
493 for (unsigned i = 0; i != NumParts; ++i)
494 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
495 } else if (NumParts > 0) {
496 // If the intermediate type was expanded, split each the value into
498 assert(NumParts % NumIntermediates == 0 &&
499 "Must expand into a divisible number of parts!");
500 unsigned Factor = NumParts / NumIntermediates;
501 for (unsigned i = 0; i != NumIntermediates; ++i)
502 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
510 /// RegsForValue - This struct represents the registers (physical or virtual)
511 /// that a particular set of values is assigned, and the type information
512 /// about the value. The most common situation is to represent one value at a
513 /// time, but struct or array values are handled element-wise as multiple
514 /// values. The splitting of aggregates is performed recursively, so that we
515 /// never have aggregate-typed registers. The values at this point do not
516 /// necessarily have legal types, so each value may require one or more
517 /// registers of some legal type.
519 struct RegsForValue {
520 /// ValueVTs - The value types of the values, which may not be legal, and
521 /// may need be promoted or synthesized from one or more registers.
523 SmallVector<EVT, 4> ValueVTs;
525 /// RegVTs - The value types of the registers. This is the same size as
526 /// ValueVTs and it records, for each value, what the type of the assigned
527 /// register or registers are. (Individual values are never synthesized
528 /// from more than one type of register.)
530 /// With virtual registers, the contents of RegVTs is redundant with TLI's
531 /// getRegisterType member function, however when with physical registers
532 /// it is necessary to have a separate record of the types.
534 SmallVector<EVT, 4> RegVTs;
536 /// Regs - This list holds the registers assigned to the values.
537 /// Each legal or promoted value requires one register, and each
538 /// expanded value requires multiple registers.
540 SmallVector<unsigned, 4> Regs;
544 RegsForValue(const SmallVector<unsigned, 4> ®s,
545 EVT regvt, EVT valuevt)
546 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
548 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
549 unsigned Reg, const Type *Ty) {
550 ComputeValueVTs(tli, Ty, ValueVTs);
552 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
553 EVT ValueVT = ValueVTs[Value];
554 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
555 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
556 for (unsigned i = 0; i != NumRegs; ++i)
557 Regs.push_back(Reg + i);
558 RegVTs.push_back(RegisterVT);
563 /// areValueTypesLegal - Return true if types of all the values are legal.
564 bool areValueTypesLegal(const TargetLowering &TLI) {
565 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
566 EVT RegisterVT = RegVTs[Value];
567 if (!TLI.isTypeLegal(RegisterVT))
573 /// append - Add the specified values to this one.
574 void append(const RegsForValue &RHS) {
575 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
576 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
577 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
580 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
581 /// this value and returns the result as a ValueVTs value. This uses
582 /// Chain/Flag as the input and updates them for the output Chain/Flag.
583 /// If the Flag pointer is NULL, no flag is used.
584 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
586 SDValue &Chain, SDValue *Flag) const;
588 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
589 /// specified value into the registers specified by this object. This uses
590 /// Chain/Flag as the input and updates them for the output Chain/Flag.
591 /// If the Flag pointer is NULL, no flag is used.
592 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
593 SDValue &Chain, SDValue *Flag) const;
595 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
596 /// operand list. This adds the code marker, matching input operand index
597 /// (if applicable), and includes the number of values added into it.
598 void AddInlineAsmOperands(unsigned Kind,
599 bool HasMatching, unsigned MatchingIdx,
601 std::vector<SDValue> &Ops) const;
605 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
606 /// this value and returns the result as a ValueVT value. This uses
607 /// Chain/Flag as the input and updates them for the output Chain/Flag.
608 /// If the Flag pointer is NULL, no flag is used.
609 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
610 FunctionLoweringInfo &FuncInfo,
612 SDValue &Chain, SDValue *Flag) const {
613 // A Value with type {} or [0 x %t] needs no registers.
614 if (ValueVTs.empty())
617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
619 // Assemble the legal parts into the final values.
620 SmallVector<SDValue, 4> Values(ValueVTs.size());
621 SmallVector<SDValue, 8> Parts;
622 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
623 // Copy the legal parts from the registers.
624 EVT ValueVT = ValueVTs[Value];
625 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
626 EVT RegisterVT = RegVTs[Value];
628 Parts.resize(NumRegs);
629 for (unsigned i = 0; i != NumRegs; ++i) {
632 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
634 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
635 *Flag = P.getValue(2);
638 Chain = P.getValue(1);
641 // If the source register was virtual and if we know something about it,
642 // add an assert node.
643 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
644 !RegisterVT.isInteger() || RegisterVT.isVector() ||
645 !FuncInfo.LiveOutRegInfo.inBounds(Regs[Part+i]))
648 const FunctionLoweringInfo::LiveOutInfo &LOI =
649 FuncInfo.LiveOutRegInfo[Regs[Part+i]];
651 unsigned RegSize = RegisterVT.getSizeInBits();
652 unsigned NumSignBits = LOI.NumSignBits;
653 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
655 // FIXME: We capture more information than the dag can represent. For
656 // now, just use the tightest assertzext/assertsext possible.
658 EVT FromVT(MVT::Other);
659 if (NumSignBits == RegSize)
660 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
661 else if (NumZeroBits >= RegSize-1)
662 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
663 else if (NumSignBits > RegSize-8)
664 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
665 else if (NumZeroBits >= RegSize-8)
666 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
667 else if (NumSignBits > RegSize-16)
668 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
669 else if (NumZeroBits >= RegSize-16)
670 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
671 else if (NumSignBits > RegSize-32)
672 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
673 else if (NumZeroBits >= RegSize-32)
674 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
678 // Add an assertion node.
679 assert(FromVT != MVT::Other);
680 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
681 RegisterVT, P, DAG.getValueType(FromVT));
684 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
685 NumRegs, RegisterVT, ValueVT);
690 return DAG.getNode(ISD::MERGE_VALUES, dl,
691 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
692 &Values[0], ValueVTs.size());
695 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
696 /// specified value into the registers specified by this object. This uses
697 /// Chain/Flag as the input and updates them for the output Chain/Flag.
698 /// If the Flag pointer is NULL, no flag is used.
699 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
700 SDValue &Chain, SDValue *Flag) const {
701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
703 // Get the list of the values's legal parts.
704 unsigned NumRegs = Regs.size();
705 SmallVector<SDValue, 8> Parts(NumRegs);
706 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
707 EVT ValueVT = ValueVTs[Value];
708 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
709 EVT RegisterVT = RegVTs[Value];
711 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
712 &Parts[Part], NumParts, RegisterVT);
716 // Copy the parts into the registers.
717 SmallVector<SDValue, 8> Chains(NumRegs);
718 for (unsigned i = 0; i != NumRegs; ++i) {
721 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
723 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
724 *Flag = Part.getValue(1);
727 Chains[i] = Part.getValue(0);
730 if (NumRegs == 1 || Flag)
731 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
732 // flagged to it. That is the CopyToReg nodes and the user are considered
733 // a single scheduling unit. If we create a TokenFactor and return it as
734 // chain, then the TokenFactor is both a predecessor (operand) of the
735 // user as well as a successor (the TF operands are flagged to the user).
736 // c1, f1 = CopyToReg
737 // c2, f2 = CopyToReg
738 // c3 = TokenFactor c1, c2
741 Chain = Chains[NumRegs-1];
743 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
746 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
747 /// operand list. This adds the code marker and includes the number of
748 /// values added into it.
749 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
750 unsigned MatchingIdx,
752 std::vector<SDValue> &Ops) const {
753 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
755 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
757 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
758 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
761 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
762 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
763 EVT RegisterVT = RegVTs[Value];
764 for (unsigned i = 0; i != NumRegs; ++i) {
765 assert(Reg < Regs.size() && "Mismatch in # registers expected");
766 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
771 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
774 TD = DAG.getTarget().getTargetData();
777 /// clear - Clear out the current SelectionDAG and the associated
778 /// state and prepare this SelectionDAGBuilder object to be used
779 /// for a new block. This doesn't clear out information about
780 /// additional blocks that are needed to complete switch lowering
781 /// or PHI node updating; that information is cleared out as it is
783 void SelectionDAGBuilder::clear() {
785 UnusedArgNodeMap.clear();
786 PendingLoads.clear();
787 PendingExports.clear();
788 DanglingDebugInfoMap.clear();
789 CurDebugLoc = DebugLoc();
793 /// getRoot - Return the current virtual root of the Selection DAG,
794 /// flushing any PendingLoad items. This must be done before emitting
795 /// a store or any other node that may need to be ordered after any
796 /// prior load instructions.
798 SDValue SelectionDAGBuilder::getRoot() {
799 if (PendingLoads.empty())
800 return DAG.getRoot();
802 if (PendingLoads.size() == 1) {
803 SDValue Root = PendingLoads[0];
805 PendingLoads.clear();
809 // Otherwise, we have to make a token factor node.
810 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
811 &PendingLoads[0], PendingLoads.size());
812 PendingLoads.clear();
817 /// getControlRoot - Similar to getRoot, but instead of flushing all the
818 /// PendingLoad items, flush all the PendingExports items. It is necessary
819 /// to do this before emitting a terminator instruction.
821 SDValue SelectionDAGBuilder::getControlRoot() {
822 SDValue Root = DAG.getRoot();
824 if (PendingExports.empty())
827 // Turn all of the CopyToReg chains into one factored node.
828 if (Root.getOpcode() != ISD::EntryToken) {
829 unsigned i = 0, e = PendingExports.size();
830 for (; i != e; ++i) {
831 assert(PendingExports[i].getNode()->getNumOperands() > 1);
832 if (PendingExports[i].getNode()->getOperand(0) == Root)
833 break; // Don't add the root if we already indirectly depend on it.
837 PendingExports.push_back(Root);
840 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
842 PendingExports.size());
843 PendingExports.clear();
848 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
849 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
850 DAG.AssignOrdering(Node, SDNodeOrder);
852 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
853 AssignOrderingToNode(Node->getOperand(I).getNode());
856 void SelectionDAGBuilder::visit(const Instruction &I) {
857 // Set up outgoing PHI node register values before emitting the terminator.
858 if (isa<TerminatorInst>(&I))
859 HandlePHINodesInSuccessorBlocks(I.getParent());
861 CurDebugLoc = I.getDebugLoc();
863 visit(I.getOpcode(), I);
865 if (!isa<TerminatorInst>(&I) && !HasTailCall)
866 CopyToExportRegsIfNeeded(&I);
868 CurDebugLoc = DebugLoc();
871 void SelectionDAGBuilder::visitPHI(const PHINode &) {
872 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
875 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
876 // Note: this doesn't use InstVisitor, because it has to work with
877 // ConstantExpr's in addition to instructions.
879 default: llvm_unreachable("Unknown instruction type encountered!");
880 // Build the switch statement using the Instruction.def file.
881 #define HANDLE_INST(NUM, OPCODE, CLASS) \
882 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
883 #include "llvm/Instruction.def"
886 // Assign the ordering to the freshly created DAG nodes.
887 if (NodeMap.count(&I)) {
889 AssignOrderingToNode(getValue(&I).getNode());
893 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
894 // generate the debug data structures now that we've seen its definition.
895 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
897 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
899 const DbgValueInst *DI = DDI.getDI();
900 DebugLoc dl = DDI.getdl();
901 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
902 MDNode *Variable = DI->getVariable();
903 uint64_t Offset = DI->getOffset();
906 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
907 SDV = DAG.getDbgValue(Variable, Val.getNode(),
908 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
909 DAG.AddDbgValue(SDV, Val.getNode(), false);
912 DEBUG(dbgs() << "Dropping debug info for " << DI);
913 DanglingDebugInfoMap[V] = DanglingDebugInfo();
917 // getValue - Return an SDValue for the given Value.
918 SDValue SelectionDAGBuilder::getValue(const Value *V) {
919 // If we already have an SDValue for this value, use it. It's important
920 // to do this first, so that we don't create a CopyFromReg if we already
921 // have a regular SDValue.
922 SDValue &N = NodeMap[V];
923 if (N.getNode()) return N;
925 // If there's a virtual register allocated and initialized for this
927 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
928 if (It != FuncInfo.ValueMap.end()) {
929 unsigned InReg = It->second;
930 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
931 SDValue Chain = DAG.getEntryNode();
932 return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
935 // Otherwise create a new SDValue and remember it.
936 SDValue Val = getValueImpl(V);
938 resolveDanglingDebugInfo(V, Val);
942 /// getNonRegisterValue - Return an SDValue for the given Value, but
943 /// don't look in FuncInfo.ValueMap for a virtual register.
944 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
945 // If we already have an SDValue for this value, use it.
946 SDValue &N = NodeMap[V];
947 if (N.getNode()) return N;
949 // Otherwise create a new SDValue and remember it.
950 SDValue Val = getValueImpl(V);
952 resolveDanglingDebugInfo(V, Val);
956 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
957 /// Create an SDValue for the given value.
958 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
959 if (const Constant *C = dyn_cast<Constant>(V)) {
960 EVT VT = TLI.getValueType(V->getType(), true);
962 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
963 return DAG.getConstant(*CI, VT);
965 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
966 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
968 if (isa<ConstantPointerNull>(C))
969 return DAG.getConstant(0, TLI.getPointerTy());
971 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
972 return DAG.getConstantFP(*CFP, VT);
974 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
975 return DAG.getUNDEF(VT);
977 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
978 visit(CE->getOpcode(), *CE);
979 SDValue N1 = NodeMap[V];
980 assert(N1.getNode() && "visit didn't populate the NodeMap!");
984 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
985 SmallVector<SDValue, 4> Constants;
986 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
988 SDNode *Val = getValue(*OI).getNode();
989 // If the operand is an empty aggregate, there are no values.
991 // Add each leaf value from the operand to the Constants list
992 // to form a flattened list of all the values.
993 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
994 Constants.push_back(SDValue(Val, i));
997 return DAG.getMergeValues(&Constants[0], Constants.size(),
1001 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1002 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1003 "Unknown struct or array constant!");
1005 SmallVector<EVT, 4> ValueVTs;
1006 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1007 unsigned NumElts = ValueVTs.size();
1009 return SDValue(); // empty struct
1010 SmallVector<SDValue, 4> Constants(NumElts);
1011 for (unsigned i = 0; i != NumElts; ++i) {
1012 EVT EltVT = ValueVTs[i];
1013 if (isa<UndefValue>(C))
1014 Constants[i] = DAG.getUNDEF(EltVT);
1015 else if (EltVT.isFloatingPoint())
1016 Constants[i] = DAG.getConstantFP(0, EltVT);
1018 Constants[i] = DAG.getConstant(0, EltVT);
1021 return DAG.getMergeValues(&Constants[0], NumElts,
1025 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1026 return DAG.getBlockAddress(BA, VT);
1028 const VectorType *VecTy = cast<VectorType>(V->getType());
1029 unsigned NumElements = VecTy->getNumElements();
1031 // Now that we know the number and type of the elements, get that number of
1032 // elements into the Ops array based on what kind of constant it is.
1033 SmallVector<SDValue, 16> Ops;
1034 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1035 for (unsigned i = 0; i != NumElements; ++i)
1036 Ops.push_back(getValue(CP->getOperand(i)));
1038 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1039 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1042 if (EltVT.isFloatingPoint())
1043 Op = DAG.getConstantFP(0, EltVT);
1045 Op = DAG.getConstant(0, EltVT);
1046 Ops.assign(NumElements, Op);
1049 // Create a BUILD_VECTOR node.
1050 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1051 VT, &Ops[0], Ops.size());
1054 // If this is a static alloca, generate it as the frameindex instead of
1056 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1057 DenseMap<const AllocaInst*, int>::iterator SI =
1058 FuncInfo.StaticAllocaMap.find(AI);
1059 if (SI != FuncInfo.StaticAllocaMap.end())
1060 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1063 // If this is an instruction which fast-isel has deferred, select it now.
1064 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1065 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1066 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1067 SDValue Chain = DAG.getEntryNode();
1068 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1071 llvm_unreachable("Can't get register for value!");
1075 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1076 SDValue Chain = getControlRoot();
1077 SmallVector<ISD::OutputArg, 8> Outs;
1078 SmallVector<SDValue, 8> OutVals;
1080 if (!FuncInfo.CanLowerReturn) {
1081 unsigned DemoteReg = FuncInfo.DemoteRegister;
1082 const Function *F = I.getParent()->getParent();
1084 // Emit a store of the return value through the virtual register.
1085 // Leave Outs empty so that LowerReturn won't try to load return
1086 // registers the usual way.
1087 SmallVector<EVT, 1> PtrValueVTs;
1088 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1091 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1092 SDValue RetOp = getValue(I.getOperand(0));
1094 SmallVector<EVT, 4> ValueVTs;
1095 SmallVector<uint64_t, 4> Offsets;
1096 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1097 unsigned NumValues = ValueVTs.size();
1099 SmallVector<SDValue, 4> Chains(NumValues);
1100 for (unsigned i = 0; i != NumValues; ++i) {
1101 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1102 RetPtr.getValueType(), RetPtr,
1103 DAG.getIntPtrConstant(Offsets[i]));
1105 DAG.getStore(Chain, getCurDebugLoc(),
1106 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1107 // FIXME: better loc info would be nice.
1108 Add, MachinePointerInfo(), false, false, 0);
1111 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1112 MVT::Other, &Chains[0], NumValues);
1113 } else if (I.getNumOperands() != 0) {
1114 SmallVector<EVT, 4> ValueVTs;
1115 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1116 unsigned NumValues = ValueVTs.size();
1118 SDValue RetOp = getValue(I.getOperand(0));
1119 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1120 EVT VT = ValueVTs[j];
1122 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1124 const Function *F = I.getParent()->getParent();
1125 if (F->paramHasAttr(0, Attribute::SExt))
1126 ExtendKind = ISD::SIGN_EXTEND;
1127 else if (F->paramHasAttr(0, Attribute::ZExt))
1128 ExtendKind = ISD::ZERO_EXTEND;
1130 // FIXME: C calling convention requires the return type to be promoted
1131 // to at least 32-bit. But this is not necessary for non-C calling
1132 // conventions. The frontend should mark functions whose return values
1133 // require promoting with signext or zeroext attributes.
1134 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1135 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
1136 if (VT.bitsLT(MinVT))
1140 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1141 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1142 SmallVector<SDValue, 4> Parts(NumParts);
1143 getCopyToParts(DAG, getCurDebugLoc(),
1144 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1145 &Parts[0], NumParts, PartVT, ExtendKind);
1147 // 'inreg' on function refers to return value
1148 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1149 if (F->paramHasAttr(0, Attribute::InReg))
1152 // Propagate extension type if any
1153 if (F->paramHasAttr(0, Attribute::SExt))
1155 else if (F->paramHasAttr(0, Attribute::ZExt))
1158 for (unsigned i = 0; i < NumParts; ++i) {
1159 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1161 OutVals.push_back(Parts[i]);
1167 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1168 CallingConv::ID CallConv =
1169 DAG.getMachineFunction().getFunction()->getCallingConv();
1170 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1171 Outs, OutVals, getCurDebugLoc(), DAG);
1173 // Verify that the target's LowerReturn behaved as expected.
1174 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1175 "LowerReturn didn't return a valid chain!");
1177 // Update the DAG with the new chain value resulting from return lowering.
1181 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1182 /// created for it, emit nodes to copy the value into the virtual
1184 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1185 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1186 if (VMI != FuncInfo.ValueMap.end()) {
1187 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1188 CopyValueToVirtualRegister(V, VMI->second);
1192 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1193 /// the current basic block, add it to ValueMap now so that we'll get a
1195 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1196 // No need to export constants.
1197 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1199 // Already exported?
1200 if (FuncInfo.isExportedInst(V)) return;
1202 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1203 CopyValueToVirtualRegister(V, Reg);
1206 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1207 const BasicBlock *FromBB) {
1208 // The operands of the setcc have to be in this block. We don't know
1209 // how to export them from some other block.
1210 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1211 // Can export from current BB.
1212 if (VI->getParent() == FromBB)
1215 // Is already exported, noop.
1216 return FuncInfo.isExportedInst(V);
1219 // If this is an argument, we can export it if the BB is the entry block or
1220 // if it is already exported.
1221 if (isa<Argument>(V)) {
1222 if (FromBB == &FromBB->getParent()->getEntryBlock())
1225 // Otherwise, can only export this if it is already exported.
1226 return FuncInfo.isExportedInst(V);
1229 // Otherwise, constants can always be exported.
1233 static bool InBlock(const Value *V, const BasicBlock *BB) {
1234 if (const Instruction *I = dyn_cast<Instruction>(V))
1235 return I->getParent() == BB;
1239 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1240 /// This function emits a branch and is used at the leaves of an OR or an
1241 /// AND operator tree.
1244 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1245 MachineBasicBlock *TBB,
1246 MachineBasicBlock *FBB,
1247 MachineBasicBlock *CurBB,
1248 MachineBasicBlock *SwitchBB) {
1249 const BasicBlock *BB = CurBB->getBasicBlock();
1251 // If the leaf of the tree is a comparison, merge the condition into
1253 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1254 // The operands of the cmp have to be in this block. We don't know
1255 // how to export them from some other block. If this is the first block
1256 // of the sequence, no exporting is needed.
1257 if (CurBB == SwitchBB ||
1258 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1259 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1260 ISD::CondCode Condition;
1261 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1262 Condition = getICmpCondCode(IC->getPredicate());
1263 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1264 Condition = getFCmpCondCode(FC->getPredicate());
1266 Condition = ISD::SETEQ; // silence warning.
1267 llvm_unreachable("Unknown compare instruction");
1270 CaseBlock CB(Condition, BOp->getOperand(0),
1271 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1272 SwitchCases.push_back(CB);
1277 // Create a CaseBlock record representing this branch.
1278 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1279 NULL, TBB, FBB, CurBB);
1280 SwitchCases.push_back(CB);
1283 /// FindMergedConditions - If Cond is an expression like
1284 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1285 MachineBasicBlock *TBB,
1286 MachineBasicBlock *FBB,
1287 MachineBasicBlock *CurBB,
1288 MachineBasicBlock *SwitchBB,
1290 // If this node is not part of the or/and tree, emit it as a branch.
1291 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1292 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1293 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1294 BOp->getParent() != CurBB->getBasicBlock() ||
1295 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1296 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1297 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1301 // Create TmpBB after CurBB.
1302 MachineFunction::iterator BBI = CurBB;
1303 MachineFunction &MF = DAG.getMachineFunction();
1304 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1305 CurBB->getParent()->insert(++BBI, TmpBB);
1307 if (Opc == Instruction::Or) {
1308 // Codegen X | Y as:
1316 // Emit the LHS condition.
1317 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1319 // Emit the RHS condition into TmpBB.
1320 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1322 assert(Opc == Instruction::And && "Unknown merge op!");
1323 // Codegen X & Y as:
1330 // This requires creation of TmpBB after CurBB.
1332 // Emit the LHS condition.
1333 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1335 // Emit the RHS condition into TmpBB.
1336 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1340 /// If the set of cases should be emitted as a series of branches, return true.
1341 /// If we should emit this as a bunch of and/or'd together conditions, return
1344 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1345 if (Cases.size() != 2) return true;
1347 // If this is two comparisons of the same values or'd or and'd together, they
1348 // will get folded into a single comparison, so don't emit two blocks.
1349 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1350 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1351 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1352 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1356 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1357 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1358 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1359 Cases[0].CC == Cases[1].CC &&
1360 isa<Constant>(Cases[0].CmpRHS) &&
1361 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1362 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1364 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1371 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1372 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1374 // Update machine-CFG edges.
1375 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1377 // Figure out which block is immediately after the current one.
1378 MachineBasicBlock *NextBlock = 0;
1379 MachineFunction::iterator BBI = BrMBB;
1380 if (++BBI != FuncInfo.MF->end())
1383 if (I.isUnconditional()) {
1384 // Update machine-CFG edges.
1385 BrMBB->addSuccessor(Succ0MBB);
1387 // If this is not a fall-through branch, emit the branch.
1388 if (Succ0MBB != NextBlock)
1389 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1390 MVT::Other, getControlRoot(),
1391 DAG.getBasicBlock(Succ0MBB)));
1396 // If this condition is one of the special cases we handle, do special stuff
1398 const Value *CondVal = I.getCondition();
1399 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1401 // If this is a series of conditions that are or'd or and'd together, emit
1402 // this as a sequence of branches instead of setcc's with and/or operations.
1403 // As long as jumps are not expensive, this should improve performance.
1404 // For example, instead of something like:
1417 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1418 if (!TLI.isJumpExpensive() &&
1420 (BOp->getOpcode() == Instruction::And ||
1421 BOp->getOpcode() == Instruction::Or)) {
1422 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1424 // If the compares in later blocks need to use values not currently
1425 // exported from this block, export them now. This block should always
1426 // be the first entry.
1427 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1429 // Allow some cases to be rejected.
1430 if (ShouldEmitAsBranches(SwitchCases)) {
1431 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1432 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1433 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1436 // Emit the branch for this block.
1437 visitSwitchCase(SwitchCases[0], BrMBB);
1438 SwitchCases.erase(SwitchCases.begin());
1442 // Okay, we decided not to do this, remove any inserted MBB's and clear
1444 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1445 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1447 SwitchCases.clear();
1451 // Create a CaseBlock record representing this branch.
1452 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1453 NULL, Succ0MBB, Succ1MBB, BrMBB);
1455 // Use visitSwitchCase to actually insert the fast branch sequence for this
1457 visitSwitchCase(CB, BrMBB);
1460 /// visitSwitchCase - Emits the necessary code to represent a single node in
1461 /// the binary search tree resulting from lowering a switch instruction.
1462 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1463 MachineBasicBlock *SwitchBB) {
1465 SDValue CondLHS = getValue(CB.CmpLHS);
1466 DebugLoc dl = getCurDebugLoc();
1468 // Build the setcc now.
1469 if (CB.CmpMHS == NULL) {
1470 // Fold "(X == true)" to X and "(X == false)" to !X to
1471 // handle common cases produced by branch lowering.
1472 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1473 CB.CC == ISD::SETEQ)
1475 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1476 CB.CC == ISD::SETEQ) {
1477 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1478 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1480 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1482 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1484 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1485 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1487 SDValue CmpOp = getValue(CB.CmpMHS);
1488 EVT VT = CmpOp.getValueType();
1490 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1491 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1494 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1495 VT, CmpOp, DAG.getConstant(Low, VT));
1496 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1497 DAG.getConstant(High-Low, VT), ISD::SETULE);
1501 // Update successor info
1502 SwitchBB->addSuccessor(CB.TrueBB);
1503 SwitchBB->addSuccessor(CB.FalseBB);
1505 // Set NextBlock to be the MBB immediately after the current one, if any.
1506 // This is used to avoid emitting unnecessary branches to the next block.
1507 MachineBasicBlock *NextBlock = 0;
1508 MachineFunction::iterator BBI = SwitchBB;
1509 if (++BBI != FuncInfo.MF->end())
1512 // If the lhs block is the next block, invert the condition so that we can
1513 // fall through to the lhs instead of the rhs block.
1514 if (CB.TrueBB == NextBlock) {
1515 std::swap(CB.TrueBB, CB.FalseBB);
1516 SDValue True = DAG.getConstant(1, Cond.getValueType());
1517 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1520 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1521 MVT::Other, getControlRoot(), Cond,
1522 DAG.getBasicBlock(CB.TrueBB));
1524 // Insert the false branch. Do this even if it's a fall through branch,
1525 // this makes it easier to do DAG optimizations which require inverting
1526 // the branch condition.
1527 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1528 DAG.getBasicBlock(CB.FalseBB));
1530 DAG.setRoot(BrCond);
1533 /// visitJumpTable - Emit JumpTable node in the current MBB
1534 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1535 // Emit the code for the jump table
1536 assert(JT.Reg != -1U && "Should lower JT Header first!");
1537 EVT PTy = TLI.getPointerTy();
1538 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1540 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1541 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1542 MVT::Other, Index.getValue(1),
1544 DAG.setRoot(BrJumpTable);
1547 /// visitJumpTableHeader - This function emits necessary code to produce index
1548 /// in the JumpTable from switch case.
1549 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1550 JumpTableHeader &JTH,
1551 MachineBasicBlock *SwitchBB) {
1552 // Subtract the lowest switch case value from the value being switched on and
1553 // conditional branch to default mbb if the result is greater than the
1554 // difference between smallest and largest cases.
1555 SDValue SwitchOp = getValue(JTH.SValue);
1556 EVT VT = SwitchOp.getValueType();
1557 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1558 DAG.getConstant(JTH.First, VT));
1560 // The SDNode we just created, which holds the value being switched on minus
1561 // the smallest case value, needs to be copied to a virtual register so it
1562 // can be used as an index into the jump table in a subsequent basic block.
1563 // This value may be smaller or larger than the target's pointer type, and
1564 // therefore require extension or truncating.
1565 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1567 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1568 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1569 JumpTableReg, SwitchOp);
1570 JT.Reg = JumpTableReg;
1572 // Emit the range check for the jump table, and branch to the default block
1573 // for the switch statement if the value being switched on exceeds the largest
1574 // case in the switch.
1575 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1576 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1577 DAG.getConstant(JTH.Last-JTH.First,VT),
1580 // Set NextBlock to be the MBB immediately after the current one, if any.
1581 // This is used to avoid emitting unnecessary branches to the next block.
1582 MachineBasicBlock *NextBlock = 0;
1583 MachineFunction::iterator BBI = SwitchBB;
1585 if (++BBI != FuncInfo.MF->end())
1588 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1589 MVT::Other, CopyTo, CMP,
1590 DAG.getBasicBlock(JT.Default));
1592 if (JT.MBB != NextBlock)
1593 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1594 DAG.getBasicBlock(JT.MBB));
1596 DAG.setRoot(BrCond);
1599 /// visitBitTestHeader - This function emits necessary code to produce value
1600 /// suitable for "bit tests"
1601 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1602 MachineBasicBlock *SwitchBB) {
1603 // Subtract the minimum value
1604 SDValue SwitchOp = getValue(B.SValue);
1605 EVT VT = SwitchOp.getValueType();
1606 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1607 DAG.getConstant(B.First, VT));
1610 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1611 TLI.getSetCCResultType(Sub.getValueType()),
1612 Sub, DAG.getConstant(B.Range, VT),
1615 // Determine the type of the test operands.
1616 bool UsePtrType = false;
1617 if (!TLI.isTypeLegal(VT))
1620 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1621 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) {
1622 // Switch table case range are encoded into series of masks.
1623 // Just use pointer type, it's guaranteed to fit.
1629 VT = TLI.getPointerTy();
1630 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1634 B.Reg = FuncInfo.CreateReg(VT);
1635 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1638 // Set NextBlock to be the MBB immediately after the current one, if any.
1639 // This is used to avoid emitting unnecessary branches to the next block.
1640 MachineBasicBlock *NextBlock = 0;
1641 MachineFunction::iterator BBI = SwitchBB;
1642 if (++BBI != FuncInfo.MF->end())
1645 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1647 SwitchBB->addSuccessor(B.Default);
1648 SwitchBB->addSuccessor(MBB);
1650 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1651 MVT::Other, CopyTo, RangeCmp,
1652 DAG.getBasicBlock(B.Default));
1654 if (MBB != NextBlock)
1655 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1656 DAG.getBasicBlock(MBB));
1658 DAG.setRoot(BrRange);
1661 /// visitBitTestCase - this function produces one "bit test"
1662 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1663 MachineBasicBlock* NextMBB,
1666 MachineBasicBlock *SwitchBB) {
1668 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1671 if (CountPopulation_64(B.Mask) == 1) {
1672 // Testing for a single bit; just compare the shift count with what it
1673 // would need to be to shift a 1 bit in that position.
1674 Cmp = DAG.getSetCC(getCurDebugLoc(),
1675 TLI.getSetCCResultType(VT),
1677 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1680 // Make desired shift
1681 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1682 DAG.getConstant(1, VT), ShiftOp);
1684 // Emit bit tests and jumps
1685 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1686 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1687 Cmp = DAG.getSetCC(getCurDebugLoc(),
1688 TLI.getSetCCResultType(VT),
1689 AndOp, DAG.getConstant(0, VT),
1693 SwitchBB->addSuccessor(B.TargetBB);
1694 SwitchBB->addSuccessor(NextMBB);
1696 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1697 MVT::Other, getControlRoot(),
1698 Cmp, DAG.getBasicBlock(B.TargetBB));
1700 // Set NextBlock to be the MBB immediately after the current one, if any.
1701 // This is used to avoid emitting unnecessary branches to the next block.
1702 MachineBasicBlock *NextBlock = 0;
1703 MachineFunction::iterator BBI = SwitchBB;
1704 if (++BBI != FuncInfo.MF->end())
1707 if (NextMBB != NextBlock)
1708 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1709 DAG.getBasicBlock(NextMBB));
1714 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1715 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1717 // Retrieve successors.
1718 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1719 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1721 const Value *Callee(I.getCalledValue());
1722 if (isa<InlineAsm>(Callee))
1725 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1727 // If the value of the invoke is used outside of its defining block, make it
1728 // available as a virtual register.
1729 CopyToExportRegsIfNeeded(&I);
1731 // Update successor info
1732 InvokeMBB->addSuccessor(Return);
1733 InvokeMBB->addSuccessor(LandingPad);
1735 // Drop into normal successor.
1736 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1737 MVT::Other, getControlRoot(),
1738 DAG.getBasicBlock(Return)));
1741 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1744 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1745 /// small case ranges).
1746 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1747 CaseRecVector& WorkList,
1749 MachineBasicBlock *Default,
1750 MachineBasicBlock *SwitchBB) {
1751 Case& BackCase = *(CR.Range.second-1);
1753 // Size is the number of Cases represented by this range.
1754 size_t Size = CR.Range.second - CR.Range.first;
1758 // Get the MachineFunction which holds the current MBB. This is used when
1759 // inserting any additional MBBs necessary to represent the switch.
1760 MachineFunction *CurMF = FuncInfo.MF;
1762 // Figure out which block is immediately after the current one.
1763 MachineBasicBlock *NextBlock = 0;
1764 MachineFunction::iterator BBI = CR.CaseBB;
1766 if (++BBI != FuncInfo.MF->end())
1769 // If any two of the cases has the same destination, and if one value
1770 // is the same as the other, but has one bit unset that the other has set,
1771 // use bit manipulation to do two compares at once. For example:
1772 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1773 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1774 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1775 if (Size == 2 && CR.CaseBB == SwitchBB) {
1776 Case &Small = *CR.Range.first;
1777 Case &Big = *(CR.Range.second-1);
1779 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1780 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1781 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1783 // Check that there is only one bit different.
1784 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1785 (SmallValue | BigValue) == BigValue) {
1786 // Isolate the common bit.
1787 APInt CommonBit = BigValue & ~SmallValue;
1788 assert((SmallValue | CommonBit) == BigValue &&
1789 CommonBit.countPopulation() == 1 && "Not a common bit?");
1791 SDValue CondLHS = getValue(SV);
1792 EVT VT = CondLHS.getValueType();
1793 DebugLoc DL = getCurDebugLoc();
1795 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1796 DAG.getConstant(CommonBit, VT));
1797 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1798 Or, DAG.getConstant(BigValue, VT),
1801 // Update successor info.
1802 SwitchBB->addSuccessor(Small.BB);
1803 SwitchBB->addSuccessor(Default);
1805 // Insert the true branch.
1806 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1807 getControlRoot(), Cond,
1808 DAG.getBasicBlock(Small.BB));
1810 // Insert the false branch.
1811 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1812 DAG.getBasicBlock(Default));
1814 DAG.setRoot(BrCond);
1820 // Rearrange the case blocks so that the last one falls through if possible.
1821 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1822 // The last case block won't fall through into 'NextBlock' if we emit the
1823 // branches in this order. See if rearranging a case value would help.
1824 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1825 if (I->BB == NextBlock) {
1826 std::swap(*I, BackCase);
1832 // Create a CaseBlock record representing a conditional branch to
1833 // the Case's target mbb if the value being switched on SV is equal
1835 MachineBasicBlock *CurBlock = CR.CaseBB;
1836 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1837 MachineBasicBlock *FallThrough;
1839 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1840 CurMF->insert(BBI, FallThrough);
1842 // Put SV in a virtual register to make it available from the new blocks.
1843 ExportFromCurrentBlock(SV);
1845 // If the last case doesn't match, go to the default block.
1846 FallThrough = Default;
1849 const Value *RHS, *LHS, *MHS;
1851 if (I->High == I->Low) {
1852 // This is just small small case range :) containing exactly 1 case
1854 LHS = SV; RHS = I->High; MHS = NULL;
1857 LHS = I->Low; MHS = SV; RHS = I->High;
1859 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1861 // If emitting the first comparison, just call visitSwitchCase to emit the
1862 // code into the current block. Otherwise, push the CaseBlock onto the
1863 // vector to be later processed by SDISel, and insert the node's MBB
1864 // before the next MBB.
1865 if (CurBlock == SwitchBB)
1866 visitSwitchCase(CB, SwitchBB);
1868 SwitchCases.push_back(CB);
1870 CurBlock = FallThrough;
1876 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1877 return !DisableJumpTables &&
1878 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1879 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1882 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1883 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1884 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
1885 return (LastExt - FirstExt + 1ULL);
1888 /// handleJTSwitchCase - Emit jumptable for current switch case range
1889 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1890 CaseRecVector& WorkList,
1892 MachineBasicBlock* Default,
1893 MachineBasicBlock *SwitchBB) {
1894 Case& FrontCase = *CR.Range.first;
1895 Case& BackCase = *(CR.Range.second-1);
1897 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1898 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1900 APInt TSize(First.getBitWidth(), 0);
1901 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1905 if (!areJTsAllowed(TLI) || TSize.ult(4))
1908 APInt Range = ComputeRange(First, Last);
1909 double Density = TSize.roundToDouble() / Range.roundToDouble();
1913 DEBUG(dbgs() << "Lowering jump table\n"
1914 << "First entry: " << First << ". Last entry: " << Last << '\n'
1915 << "Range: " << Range
1916 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1918 // Get the MachineFunction which holds the current MBB. This is used when
1919 // inserting any additional MBBs necessary to represent the switch.
1920 MachineFunction *CurMF = FuncInfo.MF;
1922 // Figure out which block is immediately after the current one.
1923 MachineFunction::iterator BBI = CR.CaseBB;
1926 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1928 // Create a new basic block to hold the code for loading the address
1929 // of the jump table, and jumping to it. Update successor information;
1930 // we will either branch to the default case for the switch, or the jump
1932 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1933 CurMF->insert(BBI, JumpTableBB);
1934 CR.CaseBB->addSuccessor(Default);
1935 CR.CaseBB->addSuccessor(JumpTableBB);
1937 // Build a vector of destination BBs, corresponding to each target
1938 // of the jump table. If the value of the jump table slot corresponds to
1939 // a case statement, push the case's BB onto the vector, otherwise, push
1941 std::vector<MachineBasicBlock*> DestBBs;
1943 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1944 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1945 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1947 if (Low.sle(TEI) && TEI.sle(High)) {
1948 DestBBs.push_back(I->BB);
1952 DestBBs.push_back(Default);
1956 // Update successor info. Add one edge to each unique successor.
1957 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1958 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1959 E = DestBBs.end(); I != E; ++I) {
1960 if (!SuccsHandled[(*I)->getNumber()]) {
1961 SuccsHandled[(*I)->getNumber()] = true;
1962 JumpTableBB->addSuccessor(*I);
1966 // Create a jump table index for this jump table.
1967 unsigned JTEncoding = TLI.getJumpTableEncoding();
1968 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1969 ->createJumpTableIndex(DestBBs);
1971 // Set the jump table information so that we can codegen it as a second
1972 // MachineBasicBlock
1973 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1974 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1975 if (CR.CaseBB == SwitchBB)
1976 visitJumpTableHeader(JT, JTH, SwitchBB);
1978 JTCases.push_back(JumpTableBlock(JTH, JT));
1983 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1985 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1986 CaseRecVector& WorkList,
1988 MachineBasicBlock *Default,
1989 MachineBasicBlock *SwitchBB) {
1990 // Get the MachineFunction which holds the current MBB. This is used when
1991 // inserting any additional MBBs necessary to represent the switch.
1992 MachineFunction *CurMF = FuncInfo.MF;
1994 // Figure out which block is immediately after the current one.
1995 MachineFunction::iterator BBI = CR.CaseBB;
1998 Case& FrontCase = *CR.Range.first;
1999 Case& BackCase = *(CR.Range.second-1);
2000 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2002 // Size is the number of Cases represented by this range.
2003 unsigned Size = CR.Range.second - CR.Range.first;
2005 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2006 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2008 CaseItr Pivot = CR.Range.first + Size/2;
2010 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2011 // (heuristically) allow us to emit JumpTable's later.
2012 APInt TSize(First.getBitWidth(), 0);
2013 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2017 APInt LSize = FrontCase.size();
2018 APInt RSize = TSize-LSize;
2019 DEBUG(dbgs() << "Selecting best pivot: \n"
2020 << "First: " << First << ", Last: " << Last <<'\n'
2021 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2022 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2024 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2025 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2026 APInt Range = ComputeRange(LEnd, RBegin);
2027 assert((Range - 2ULL).isNonNegative() &&
2028 "Invalid case distance");
2029 double LDensity = (double)LSize.roundToDouble() /
2030 (LEnd - First + 1ULL).roundToDouble();
2031 double RDensity = (double)RSize.roundToDouble() /
2032 (Last - RBegin + 1ULL).roundToDouble();
2033 double Metric = Range.logBase2()*(LDensity+RDensity);
2034 // Should always split in some non-trivial place
2035 DEBUG(dbgs() <<"=>Step\n"
2036 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2037 << "LDensity: " << LDensity
2038 << ", RDensity: " << RDensity << '\n'
2039 << "Metric: " << Metric << '\n');
2040 if (FMetric < Metric) {
2043 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2049 if (areJTsAllowed(TLI)) {
2050 // If our case is dense we *really* should handle it earlier!
2051 assert((FMetric > 0) && "Should handle dense range earlier!");
2053 Pivot = CR.Range.first + Size/2;
2056 CaseRange LHSR(CR.Range.first, Pivot);
2057 CaseRange RHSR(Pivot, CR.Range.second);
2058 Constant *C = Pivot->Low;
2059 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2061 // We know that we branch to the LHS if the Value being switched on is
2062 // less than the Pivot value, C. We use this to optimize our binary
2063 // tree a bit, by recognizing that if SV is greater than or equal to the
2064 // LHS's Case Value, and that Case Value is exactly one less than the
2065 // Pivot's Value, then we can branch directly to the LHS's Target,
2066 // rather than creating a leaf node for it.
2067 if ((LHSR.second - LHSR.first) == 1 &&
2068 LHSR.first->High == CR.GE &&
2069 cast<ConstantInt>(C)->getValue() ==
2070 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2071 TrueBB = LHSR.first->BB;
2073 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2074 CurMF->insert(BBI, TrueBB);
2075 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2077 // Put SV in a virtual register to make it available from the new blocks.
2078 ExportFromCurrentBlock(SV);
2081 // Similar to the optimization above, if the Value being switched on is
2082 // known to be less than the Constant CR.LT, and the current Case Value
2083 // is CR.LT - 1, then we can branch directly to the target block for
2084 // the current Case Value, rather than emitting a RHS leaf node for it.
2085 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2086 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2087 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2088 FalseBB = RHSR.first->BB;
2090 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2091 CurMF->insert(BBI, FalseBB);
2092 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2094 // Put SV in a virtual register to make it available from the new blocks.
2095 ExportFromCurrentBlock(SV);
2098 // Create a CaseBlock record representing a conditional branch to
2099 // the LHS node if the value being switched on SV is less than C.
2100 // Otherwise, branch to LHS.
2101 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2103 if (CR.CaseBB == SwitchBB)
2104 visitSwitchCase(CB, SwitchBB);
2106 SwitchCases.push_back(CB);
2111 /// handleBitTestsSwitchCase - if current case range has few destination and
2112 /// range span less, than machine word bitwidth, encode case range into series
2113 /// of masks and emit bit tests with these masks.
2114 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2115 CaseRecVector& WorkList,
2117 MachineBasicBlock* Default,
2118 MachineBasicBlock *SwitchBB){
2119 EVT PTy = TLI.getPointerTy();
2120 unsigned IntPtrBits = PTy.getSizeInBits();
2122 Case& FrontCase = *CR.Range.first;
2123 Case& BackCase = *(CR.Range.second-1);
2125 // Get the MachineFunction which holds the current MBB. This is used when
2126 // inserting any additional MBBs necessary to represent the switch.
2127 MachineFunction *CurMF = FuncInfo.MF;
2129 // If target does not have legal shift left, do not emit bit tests at all.
2130 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2134 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2136 // Single case counts one, case range - two.
2137 numCmps += (I->Low == I->High ? 1 : 2);
2140 // Count unique destinations
2141 SmallSet<MachineBasicBlock*, 4> Dests;
2142 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2143 Dests.insert(I->BB);
2144 if (Dests.size() > 3)
2145 // Don't bother the code below, if there are too much unique destinations
2148 DEBUG(dbgs() << "Total number of unique destinations: "
2149 << Dests.size() << '\n'
2150 << "Total number of comparisons: " << numCmps << '\n');
2152 // Compute span of values.
2153 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2154 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2155 APInt cmpRange = maxValue - minValue;
2157 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2158 << "Low bound: " << minValue << '\n'
2159 << "High bound: " << maxValue << '\n');
2161 if (cmpRange.uge(IntPtrBits) ||
2162 (!(Dests.size() == 1 && numCmps >= 3) &&
2163 !(Dests.size() == 2 && numCmps >= 5) &&
2164 !(Dests.size() >= 3 && numCmps >= 6)))
2167 DEBUG(dbgs() << "Emitting bit tests\n");
2168 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2170 // Optimize the case where all the case values fit in a
2171 // word without having to subtract minValue. In this case,
2172 // we can optimize away the subtraction.
2173 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2174 cmpRange = maxValue;
2176 lowBound = minValue;
2179 CaseBitsVector CasesBits;
2180 unsigned i, count = 0;
2182 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2183 MachineBasicBlock* Dest = I->BB;
2184 for (i = 0; i < count; ++i)
2185 if (Dest == CasesBits[i].BB)
2189 assert((count < 3) && "Too much destinations to test!");
2190 CasesBits.push_back(CaseBits(0, Dest, 0));
2194 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2195 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2197 uint64_t lo = (lowValue - lowBound).getZExtValue();
2198 uint64_t hi = (highValue - lowBound).getZExtValue();
2200 for (uint64_t j = lo; j <= hi; j++) {
2201 CasesBits[i].Mask |= 1ULL << j;
2202 CasesBits[i].Bits++;
2206 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2210 // Figure out which block is immediately after the current one.
2211 MachineFunction::iterator BBI = CR.CaseBB;
2214 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2216 DEBUG(dbgs() << "Cases:\n");
2217 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2218 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2219 << ", Bits: " << CasesBits[i].Bits
2220 << ", BB: " << CasesBits[i].BB << '\n');
2222 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2223 CurMF->insert(BBI, CaseBB);
2224 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2228 // Put SV in a virtual register to make it available from the new blocks.
2229 ExportFromCurrentBlock(SV);
2232 BitTestBlock BTB(lowBound, cmpRange, SV,
2233 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2234 CR.CaseBB, Default, BTC);
2236 if (CR.CaseBB == SwitchBB)
2237 visitBitTestHeader(BTB, SwitchBB);
2239 BitTestCases.push_back(BTB);
2244 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2245 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2246 const SwitchInst& SI) {
2249 // Start with "simple" cases
2250 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2251 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2252 Cases.push_back(Case(SI.getSuccessorValue(i),
2253 SI.getSuccessorValue(i),
2256 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2258 // Merge case into clusters
2259 if (Cases.size() >= 2)
2260 // Must recompute end() each iteration because it may be
2261 // invalidated by erase if we hold on to it
2262 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2263 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2264 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2265 MachineBasicBlock* nextBB = J->BB;
2266 MachineBasicBlock* currentBB = I->BB;
2268 // If the two neighboring cases go to the same destination, merge them
2269 // into a single case.
2270 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2278 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2279 if (I->Low != I->High)
2280 // A range counts double, since it requires two compares.
2287 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2288 MachineBasicBlock *Last) {
2290 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2291 if (JTCases[i].first.HeaderBB == First)
2292 JTCases[i].first.HeaderBB = Last;
2294 // Update BitTestCases.
2295 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2296 if (BitTestCases[i].Parent == First)
2297 BitTestCases[i].Parent = Last;
2300 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2301 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2303 // Figure out which block is immediately after the current one.
2304 MachineBasicBlock *NextBlock = 0;
2305 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2307 // If there is only the default destination, branch to it if it is not the
2308 // next basic block. Otherwise, just fall through.
2309 if (SI.getNumOperands() == 2) {
2310 // Update machine-CFG edges.
2312 // If this is not a fall-through branch, emit the branch.
2313 SwitchMBB->addSuccessor(Default);
2314 if (Default != NextBlock)
2315 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2316 MVT::Other, getControlRoot(),
2317 DAG.getBasicBlock(Default)));
2322 // If there are any non-default case statements, create a vector of Cases
2323 // representing each one, and sort the vector so that we can efficiently
2324 // create a binary search tree from them.
2326 size_t numCmps = Clusterify(Cases, SI);
2327 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2328 << ". Total compares: " << numCmps << '\n');
2331 // Get the Value to be switched on and default basic blocks, which will be
2332 // inserted into CaseBlock records, representing basic blocks in the binary
2334 const Value *SV = SI.getOperand(0);
2336 // Push the initial CaseRec onto the worklist
2337 CaseRecVector WorkList;
2338 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2339 CaseRange(Cases.begin(),Cases.end())));
2341 while (!WorkList.empty()) {
2342 // Grab a record representing a case range to process off the worklist
2343 CaseRec CR = WorkList.back();
2344 WorkList.pop_back();
2346 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2349 // If the range has few cases (two or less) emit a series of specific
2351 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2354 // If the switch has more than 5 blocks, and at least 40% dense, and the
2355 // target supports indirect branches, then emit a jump table rather than
2356 // lowering the switch to a binary tree of conditional branches.
2357 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2360 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2361 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2362 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2366 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2367 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2369 // Update machine-CFG edges with unique successors.
2370 SmallVector<BasicBlock*, 32> succs;
2371 succs.reserve(I.getNumSuccessors());
2372 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2373 succs.push_back(I.getSuccessor(i));
2374 array_pod_sort(succs.begin(), succs.end());
2375 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2376 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2377 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2379 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2380 MVT::Other, getControlRoot(),
2381 getValue(I.getAddress())));
2384 void SelectionDAGBuilder::visitFSub(const User &I) {
2385 // -0.0 - X --> fneg
2386 const Type *Ty = I.getType();
2387 if (Ty->isVectorTy()) {
2388 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2389 const VectorType *DestTy = cast<VectorType>(I.getType());
2390 const Type *ElTy = DestTy->getElementType();
2391 unsigned VL = DestTy->getNumElements();
2392 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2393 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2395 SDValue Op2 = getValue(I.getOperand(1));
2396 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2397 Op2.getValueType(), Op2));
2403 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2404 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2405 SDValue Op2 = getValue(I.getOperand(1));
2406 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2407 Op2.getValueType(), Op2));
2411 visitBinary(I, ISD::FSUB);
2414 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2415 SDValue Op1 = getValue(I.getOperand(0));
2416 SDValue Op2 = getValue(I.getOperand(1));
2417 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2418 Op1.getValueType(), Op1, Op2));
2421 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2422 SDValue Op1 = getValue(I.getOperand(0));
2423 SDValue Op2 = getValue(I.getOperand(1));
2424 if (!I.getType()->isVectorTy() &&
2425 Op2.getValueType() != TLI.getShiftAmountTy()) {
2426 // If the operand is smaller than the shift count type, promote it.
2427 EVT PTy = TLI.getPointerTy();
2428 EVT STy = TLI.getShiftAmountTy();
2429 if (STy.bitsGT(Op2.getValueType()))
2430 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2431 TLI.getShiftAmountTy(), Op2);
2432 // If the operand is larger than the shift count type but the shift
2433 // count type has enough bits to represent any shift value, truncate
2434 // it now. This is a common case and it exposes the truncate to
2435 // optimization early.
2436 else if (STy.getSizeInBits() >=
2437 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2438 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2439 TLI.getShiftAmountTy(), Op2);
2440 // Otherwise we'll need to temporarily settle for some other
2441 // convenient type; type legalization will make adjustments as
2443 else if (PTy.bitsLT(Op2.getValueType()))
2444 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2445 TLI.getPointerTy(), Op2);
2446 else if (PTy.bitsGT(Op2.getValueType()))
2447 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2448 TLI.getPointerTy(), Op2);
2451 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2452 Op1.getValueType(), Op1, Op2));
2455 void SelectionDAGBuilder::visitICmp(const User &I) {
2456 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2457 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2458 predicate = IC->getPredicate();
2459 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2460 predicate = ICmpInst::Predicate(IC->getPredicate());
2461 SDValue Op1 = getValue(I.getOperand(0));
2462 SDValue Op2 = getValue(I.getOperand(1));
2463 ISD::CondCode Opcode = getICmpCondCode(predicate);
2465 EVT DestVT = TLI.getValueType(I.getType());
2466 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2469 void SelectionDAGBuilder::visitFCmp(const User &I) {
2470 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2471 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2472 predicate = FC->getPredicate();
2473 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2474 predicate = FCmpInst::Predicate(FC->getPredicate());
2475 SDValue Op1 = getValue(I.getOperand(0));
2476 SDValue Op2 = getValue(I.getOperand(1));
2477 ISD::CondCode Condition = getFCmpCondCode(predicate);
2478 EVT DestVT = TLI.getValueType(I.getType());
2479 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2482 void SelectionDAGBuilder::visitSelect(const User &I) {
2483 SmallVector<EVT, 4> ValueVTs;
2484 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2485 unsigned NumValues = ValueVTs.size();
2486 if (NumValues == 0) return;
2488 SmallVector<SDValue, 4> Values(NumValues);
2489 SDValue Cond = getValue(I.getOperand(0));
2490 SDValue TrueVal = getValue(I.getOperand(1));
2491 SDValue FalseVal = getValue(I.getOperand(2));
2493 for (unsigned i = 0; i != NumValues; ++i)
2494 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2495 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2497 SDValue(TrueVal.getNode(),
2498 TrueVal.getResNo() + i),
2499 SDValue(FalseVal.getNode(),
2500 FalseVal.getResNo() + i));
2502 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2503 DAG.getVTList(&ValueVTs[0], NumValues),
2504 &Values[0], NumValues));
2507 void SelectionDAGBuilder::visitTrunc(const User &I) {
2508 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2509 SDValue N = getValue(I.getOperand(0));
2510 EVT DestVT = TLI.getValueType(I.getType());
2511 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2514 void SelectionDAGBuilder::visitZExt(const User &I) {
2515 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2516 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2517 SDValue N = getValue(I.getOperand(0));
2518 EVT DestVT = TLI.getValueType(I.getType());
2519 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2522 void SelectionDAGBuilder::visitSExt(const User &I) {
2523 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2524 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2525 SDValue N = getValue(I.getOperand(0));
2526 EVT DestVT = TLI.getValueType(I.getType());
2527 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2530 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2531 // FPTrunc is never a no-op cast, no need to check
2532 SDValue N = getValue(I.getOperand(0));
2533 EVT DestVT = TLI.getValueType(I.getType());
2534 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2535 DestVT, N, DAG.getIntPtrConstant(0)));
2538 void SelectionDAGBuilder::visitFPExt(const User &I){
2539 // FPTrunc is never a no-op cast, no need to check
2540 SDValue N = getValue(I.getOperand(0));
2541 EVT DestVT = TLI.getValueType(I.getType());
2542 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2545 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2546 // FPToUI is never a no-op cast, no need to check
2547 SDValue N = getValue(I.getOperand(0));
2548 EVT DestVT = TLI.getValueType(I.getType());
2549 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2552 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2553 // FPToSI is never a no-op cast, no need to check
2554 SDValue N = getValue(I.getOperand(0));
2555 EVT DestVT = TLI.getValueType(I.getType());
2556 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2559 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2560 // UIToFP is never a no-op cast, no need to check
2561 SDValue N = getValue(I.getOperand(0));
2562 EVT DestVT = TLI.getValueType(I.getType());
2563 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2566 void SelectionDAGBuilder::visitSIToFP(const User &I){
2567 // SIToFP is never a no-op cast, no need to check
2568 SDValue N = getValue(I.getOperand(0));
2569 EVT DestVT = TLI.getValueType(I.getType());
2570 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2573 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2574 // What to do depends on the size of the integer and the size of the pointer.
2575 // We can either truncate, zero extend, or no-op, accordingly.
2576 SDValue N = getValue(I.getOperand(0));
2577 EVT DestVT = TLI.getValueType(I.getType());
2578 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2581 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2582 // What to do depends on the size of the integer and the size of the pointer.
2583 // We can either truncate, zero extend, or no-op, accordingly.
2584 SDValue N = getValue(I.getOperand(0));
2585 EVT DestVT = TLI.getValueType(I.getType());
2586 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2589 void SelectionDAGBuilder::visitBitCast(const User &I) {
2590 SDValue N = getValue(I.getOperand(0));
2591 EVT DestVT = TLI.getValueType(I.getType());
2593 // BitCast assures us that source and destination are the same size so this is
2594 // either a BITCAST or a no-op.
2595 if (DestVT != N.getValueType())
2596 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2597 DestVT, N)); // convert types.
2599 setValue(&I, N); // noop cast.
2602 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2603 SDValue InVec = getValue(I.getOperand(0));
2604 SDValue InVal = getValue(I.getOperand(1));
2605 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2607 getValue(I.getOperand(2)));
2608 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2609 TLI.getValueType(I.getType()),
2610 InVec, InVal, InIdx));
2613 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2614 SDValue InVec = getValue(I.getOperand(0));
2615 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2617 getValue(I.getOperand(1)));
2618 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2619 TLI.getValueType(I.getType()), InVec, InIdx));
2622 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2623 // from SIndx and increasing to the element length (undefs are allowed).
2624 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2625 unsigned MaskNumElts = Mask.size();
2626 for (unsigned i = 0; i != MaskNumElts; ++i)
2627 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2632 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2633 SmallVector<int, 8> Mask;
2634 SDValue Src1 = getValue(I.getOperand(0));
2635 SDValue Src2 = getValue(I.getOperand(1));
2637 // Convert the ConstantVector mask operand into an array of ints, with -1
2638 // representing undef values.
2639 SmallVector<Constant*, 8> MaskElts;
2640 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2641 unsigned MaskNumElts = MaskElts.size();
2642 for (unsigned i = 0; i != MaskNumElts; ++i) {
2643 if (isa<UndefValue>(MaskElts[i]))
2646 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2649 EVT VT = TLI.getValueType(I.getType());
2650 EVT SrcVT = Src1.getValueType();
2651 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2653 if (SrcNumElts == MaskNumElts) {
2654 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2659 // Normalize the shuffle vector since mask and vector length don't match.
2660 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2661 // Mask is longer than the source vectors and is a multiple of the source
2662 // vectors. We can use concatenate vector to make the mask and vectors
2664 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2665 // The shuffle is concatenating two vectors together.
2666 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2671 // Pad both vectors with undefs to make them the same length as the mask.
2672 unsigned NumConcat = MaskNumElts / SrcNumElts;
2673 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2674 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2675 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2677 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2678 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2682 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2683 getCurDebugLoc(), VT,
2684 &MOps1[0], NumConcat);
2685 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2686 getCurDebugLoc(), VT,
2687 &MOps2[0], NumConcat);
2689 // Readjust mask for new input vector length.
2690 SmallVector<int, 8> MappedOps;
2691 for (unsigned i = 0; i != MaskNumElts; ++i) {
2693 if (Idx < (int)SrcNumElts)
2694 MappedOps.push_back(Idx);
2696 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2699 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2704 if (SrcNumElts > MaskNumElts) {
2705 // Analyze the access pattern of the vector to see if we can extract
2706 // two subvectors and do the shuffle. The analysis is done by calculating
2707 // the range of elements the mask access on both vectors.
2708 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2709 int MaxRange[2] = {-1, -1};
2711 for (unsigned i = 0; i != MaskNumElts; ++i) {
2717 if (Idx >= (int)SrcNumElts) {
2721 if (Idx > MaxRange[Input])
2722 MaxRange[Input] = Idx;
2723 if (Idx < MinRange[Input])
2724 MinRange[Input] = Idx;
2727 // Check if the access is smaller than the vector size and can we find
2728 // a reasonable extract index.
2729 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2731 int StartIdx[2]; // StartIdx to extract from
2732 for (int Input=0; Input < 2; ++Input) {
2733 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2734 RangeUse[Input] = 0; // Unused
2735 StartIdx[Input] = 0;
2736 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2737 // Fits within range but we should see if we can find a good
2738 // start index that is a multiple of the mask length.
2739 if (MaxRange[Input] < (int)MaskNumElts) {
2740 RangeUse[Input] = 1; // Extract from beginning of the vector
2741 StartIdx[Input] = 0;
2743 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2744 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2745 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2746 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2751 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2752 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2755 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2756 // Extract appropriate subvector and generate a vector shuffle
2757 for (int Input=0; Input < 2; ++Input) {
2758 SDValue &Src = Input == 0 ? Src1 : Src2;
2759 if (RangeUse[Input] == 0)
2760 Src = DAG.getUNDEF(VT);
2762 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2763 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2766 // Calculate new mask.
2767 SmallVector<int, 8> MappedOps;
2768 for (unsigned i = 0; i != MaskNumElts; ++i) {
2771 MappedOps.push_back(Idx);
2772 else if (Idx < (int)SrcNumElts)
2773 MappedOps.push_back(Idx - StartIdx[0]);
2775 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2778 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2784 // We can't use either concat vectors or extract subvectors so fall back to
2785 // replacing the shuffle with extract and build vector.
2786 // to insert and build vector.
2787 EVT EltVT = VT.getVectorElementType();
2788 EVT PtrVT = TLI.getPointerTy();
2789 SmallVector<SDValue,8> Ops;
2790 for (unsigned i = 0; i != MaskNumElts; ++i) {
2792 Ops.push_back(DAG.getUNDEF(EltVT));
2797 if (Idx < (int)SrcNumElts)
2798 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2799 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2801 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2803 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2809 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2810 VT, &Ops[0], Ops.size()));
2813 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2814 const Value *Op0 = I.getOperand(0);
2815 const Value *Op1 = I.getOperand(1);
2816 const Type *AggTy = I.getType();
2817 const Type *ValTy = Op1->getType();
2818 bool IntoUndef = isa<UndefValue>(Op0);
2819 bool FromUndef = isa<UndefValue>(Op1);
2821 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2823 SmallVector<EVT, 4> AggValueVTs;
2824 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2825 SmallVector<EVT, 4> ValValueVTs;
2826 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2828 unsigned NumAggValues = AggValueVTs.size();
2829 unsigned NumValValues = ValValueVTs.size();
2830 SmallVector<SDValue, 4> Values(NumAggValues);
2832 SDValue Agg = getValue(Op0);
2833 SDValue Val = getValue(Op1);
2835 // Copy the beginning value(s) from the original aggregate.
2836 for (; i != LinearIndex; ++i)
2837 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2838 SDValue(Agg.getNode(), Agg.getResNo() + i);
2839 // Copy values from the inserted value(s).
2840 for (; i != LinearIndex + NumValValues; ++i)
2841 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2842 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2843 // Copy remaining value(s) from the original aggregate.
2844 for (; i != NumAggValues; ++i)
2845 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2846 SDValue(Agg.getNode(), Agg.getResNo() + i);
2848 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2849 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2850 &Values[0], NumAggValues));
2853 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2854 const Value *Op0 = I.getOperand(0);
2855 const Type *AggTy = Op0->getType();
2856 const Type *ValTy = I.getType();
2857 bool OutOfUndef = isa<UndefValue>(Op0);
2859 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2861 SmallVector<EVT, 4> ValValueVTs;
2862 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2864 unsigned NumValValues = ValValueVTs.size();
2865 SmallVector<SDValue, 4> Values(NumValValues);
2867 SDValue Agg = getValue(Op0);
2868 // Copy out the selected value(s).
2869 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2870 Values[i - LinearIndex] =
2872 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2873 SDValue(Agg.getNode(), Agg.getResNo() + i);
2875 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2876 DAG.getVTList(&ValValueVTs[0], NumValValues),
2877 &Values[0], NumValValues));
2880 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2881 SDValue N = getValue(I.getOperand(0));
2882 const Type *Ty = I.getOperand(0)->getType();
2884 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2886 const Value *Idx = *OI;
2887 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2888 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2891 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2892 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2893 DAG.getIntPtrConstant(Offset));
2896 Ty = StTy->getElementType(Field);
2898 Ty = cast<SequentialType>(Ty)->getElementType();
2900 // If this is a constant subscript, handle it quickly.
2901 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2902 if (CI->isZero()) continue;
2904 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2906 EVT PTy = TLI.getPointerTy();
2907 unsigned PtrBits = PTy.getSizeInBits();
2909 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2911 DAG.getConstant(Offs, MVT::i64));
2913 OffsVal = DAG.getIntPtrConstant(Offs);
2915 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2920 // N = N + Idx * ElementSize;
2921 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2922 TD->getTypeAllocSize(Ty));
2923 SDValue IdxN = getValue(Idx);
2925 // If the index is smaller or larger than intptr_t, truncate or extend
2927 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2929 // If this is a multiply by a power of two, turn it into a shl
2930 // immediately. This is a very common case.
2931 if (ElementSize != 1) {
2932 if (ElementSize.isPowerOf2()) {
2933 unsigned Amt = ElementSize.logBase2();
2934 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2935 N.getValueType(), IdxN,
2936 DAG.getConstant(Amt, TLI.getPointerTy()));
2938 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2939 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2940 N.getValueType(), IdxN, Scale);
2944 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2945 N.getValueType(), N, IdxN);
2952 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2953 // If this is a fixed sized alloca in the entry block of the function,
2954 // allocate it statically on the stack.
2955 if (FuncInfo.StaticAllocaMap.count(&I))
2956 return; // getValue will auto-populate this.
2958 const Type *Ty = I.getAllocatedType();
2959 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2961 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2964 SDValue AllocSize = getValue(I.getArraySize());
2966 EVT IntPtr = TLI.getPointerTy();
2967 if (AllocSize.getValueType() != IntPtr)
2968 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2970 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2972 DAG.getConstant(TySize, IntPtr));
2974 // Handle alignment. If the requested alignment is less than or equal to
2975 // the stack alignment, ignore it. If the size is greater than or equal to
2976 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2977 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
2978 if (Align <= StackAlign)
2981 // Round the size of the allocation up to the stack alignment size
2982 // by add SA-1 to the size.
2983 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2984 AllocSize.getValueType(), AllocSize,
2985 DAG.getIntPtrConstant(StackAlign-1));
2987 // Mask out the low bits for alignment purposes.
2988 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2989 AllocSize.getValueType(), AllocSize,
2990 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2992 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2993 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2994 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2997 DAG.setRoot(DSA.getValue(1));
2999 // Inform the Frame Information that we have just allocated a variable-sized
3001 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3004 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3005 const Value *SV = I.getOperand(0);
3006 SDValue Ptr = getValue(SV);
3008 const Type *Ty = I.getType();
3010 bool isVolatile = I.isVolatile();
3011 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3012 unsigned Alignment = I.getAlignment();
3013 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3015 SmallVector<EVT, 4> ValueVTs;
3016 SmallVector<uint64_t, 4> Offsets;
3017 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3018 unsigned NumValues = ValueVTs.size();
3023 bool ConstantMemory = false;
3024 if (I.isVolatile() || NumValues > MaxParallelChains)
3025 // Serialize volatile loads with other side effects.
3027 else if (AA->pointsToConstantMemory(
3028 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3029 // Do not serialize (non-volatile) loads of constant memory with anything.
3030 Root = DAG.getEntryNode();
3031 ConstantMemory = true;
3033 // Do not serialize non-volatile loads against each other.
3034 Root = DAG.getRoot();
3037 SmallVector<SDValue, 4> Values(NumValues);
3038 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3040 EVT PtrVT = Ptr.getValueType();
3041 unsigned ChainI = 0;
3042 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3043 // Serializing loads here may result in excessive register pressure, and
3044 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3045 // could recover a bit by hoisting nodes upward in the chain by recognizing
3046 // they are side-effect free or do not alias. The optimizer should really
3047 // avoid this case by converting large object/array copies to llvm.memcpy
3048 // (MaxParallelChains should always remain as failsafe).
3049 if (ChainI == MaxParallelChains) {
3050 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3051 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3052 MVT::Other, &Chains[0], ChainI);
3056 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3058 DAG.getConstant(Offsets[i], PtrVT));
3059 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3060 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3061 isNonTemporal, Alignment, TBAAInfo);
3064 Chains[ChainI] = L.getValue(1);
3067 if (!ConstantMemory) {
3068 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3069 MVT::Other, &Chains[0], ChainI);
3073 PendingLoads.push_back(Chain);
3076 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3077 DAG.getVTList(&ValueVTs[0], NumValues),
3078 &Values[0], NumValues));
3081 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3082 const Value *SrcV = I.getOperand(0);
3083 const Value *PtrV = I.getOperand(1);
3085 SmallVector<EVT, 4> ValueVTs;
3086 SmallVector<uint64_t, 4> Offsets;
3087 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3088 unsigned NumValues = ValueVTs.size();
3092 // Get the lowered operands. Note that we do this after
3093 // checking if NumResults is zero, because with zero results
3094 // the operands won't have values in the map.
3095 SDValue Src = getValue(SrcV);
3096 SDValue Ptr = getValue(PtrV);
3098 SDValue Root = getRoot();
3099 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3101 EVT PtrVT = Ptr.getValueType();
3102 bool isVolatile = I.isVolatile();
3103 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3104 unsigned Alignment = I.getAlignment();
3105 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3107 unsigned ChainI = 0;
3108 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3109 // See visitLoad comments.
3110 if (ChainI == MaxParallelChains) {
3111 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3112 MVT::Other, &Chains[0], ChainI);
3116 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3117 DAG.getConstant(Offsets[i], PtrVT));
3118 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3119 SDValue(Src.getNode(), Src.getResNo() + i),
3120 Add, MachinePointerInfo(PtrV, Offsets[i]),
3121 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3122 Chains[ChainI] = St;
3125 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3126 MVT::Other, &Chains[0], ChainI);
3128 AssignOrderingToNode(StoreNode.getNode());
3129 DAG.setRoot(StoreNode);
3132 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3134 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3135 unsigned Intrinsic) {
3136 bool HasChain = !I.doesNotAccessMemory();
3137 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3139 // Build the operand list.
3140 SmallVector<SDValue, 8> Ops;
3141 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3143 // We don't need to serialize loads against other loads.
3144 Ops.push_back(DAG.getRoot());
3146 Ops.push_back(getRoot());
3150 // Info is set by getTgtMemInstrinsic
3151 TargetLowering::IntrinsicInfo Info;
3152 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3154 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3155 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3156 Info.opc == ISD::INTRINSIC_W_CHAIN)
3157 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3159 // Add all operands of the call to the operand list.
3160 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3161 SDValue Op = getValue(I.getArgOperand(i));
3162 assert(TLI.isTypeLegal(Op.getValueType()) &&
3163 "Intrinsic uses a non-legal type?");
3167 SmallVector<EVT, 4> ValueVTs;
3168 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3170 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3171 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3172 "Intrinsic uses a non-legal type?");
3177 ValueVTs.push_back(MVT::Other);
3179 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3183 if (IsTgtIntrinsic) {
3184 // This is target intrinsic that touches memory
3185 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3186 VTs, &Ops[0], Ops.size(),
3188 MachinePointerInfo(Info.ptrVal, Info.offset),
3189 Info.align, Info.vol,
3190 Info.readMem, Info.writeMem);
3191 } else if (!HasChain) {
3192 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3193 VTs, &Ops[0], Ops.size());
3194 } else if (!I.getType()->isVoidTy()) {
3195 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3196 VTs, &Ops[0], Ops.size());
3198 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3199 VTs, &Ops[0], Ops.size());
3203 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3205 PendingLoads.push_back(Chain);
3210 if (!I.getType()->isVoidTy()) {
3211 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3212 EVT VT = TLI.getValueType(PTy);
3213 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3216 setValue(&I, Result);
3220 /// GetSignificand - Get the significand and build it into a floating-point
3221 /// number with exponent of 1:
3223 /// Op = (Op & 0x007fffff) | 0x3f800000;
3225 /// where Op is the hexidecimal representation of floating point value.
3227 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3228 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3229 DAG.getConstant(0x007fffff, MVT::i32));
3230 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3231 DAG.getConstant(0x3f800000, MVT::i32));
3232 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3235 /// GetExponent - Get the exponent:
3237 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3239 /// where Op is the hexidecimal representation of floating point value.
3241 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3243 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3244 DAG.getConstant(0x7f800000, MVT::i32));
3245 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3246 DAG.getConstant(23, TLI.getPointerTy()));
3247 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3248 DAG.getConstant(127, MVT::i32));
3249 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3252 /// getF32Constant - Get 32-bit floating point constant.
3254 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3255 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3258 /// Inlined utility function to implement binary input atomic intrinsics for
3259 /// visitIntrinsicCall: I is a call instruction
3260 /// Op is the associated NodeType for I
3262 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3264 SDValue Root = getRoot();
3266 DAG.getAtomic(Op, getCurDebugLoc(),
3267 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3269 getValue(I.getArgOperand(0)),
3270 getValue(I.getArgOperand(1)),
3271 I.getArgOperand(0));
3273 DAG.setRoot(L.getValue(1));
3277 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3279 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3280 SDValue Op1 = getValue(I.getArgOperand(0));
3281 SDValue Op2 = getValue(I.getArgOperand(1));
3283 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3284 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3288 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3289 /// limited-precision mode.
3291 SelectionDAGBuilder::visitExp(const CallInst &I) {
3293 DebugLoc dl = getCurDebugLoc();
3295 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3296 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3297 SDValue Op = getValue(I.getArgOperand(0));
3299 // Put the exponent in the right bit position for later addition to the
3302 // #define LOG2OFe 1.4426950f
3303 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3304 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3305 getF32Constant(DAG, 0x3fb8aa3b));
3306 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3308 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3309 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3310 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3312 // IntegerPartOfX <<= 23;
3313 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3314 DAG.getConstant(23, TLI.getPointerTy()));
3316 if (LimitFloatPrecision <= 6) {
3317 // For floating-point precision of 6:
3319 // TwoToFractionalPartOfX =
3321 // (0.735607626f + 0.252464424f * x) * x;
3323 // error 0.0144103317, which is 6 bits
3324 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3325 getF32Constant(DAG, 0x3e814304));
3326 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3327 getF32Constant(DAG, 0x3f3c50c8));
3328 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3329 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3330 getF32Constant(DAG, 0x3f7f5e7e));
3331 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3333 // Add the exponent into the result in integer domain.
3334 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3335 TwoToFracPartOfX, IntegerPartOfX);
3337 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3338 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3339 // For floating-point precision of 12:
3341 // TwoToFractionalPartOfX =
3344 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3346 // 0.000107046256 error, which is 13 to 14 bits
3347 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3348 getF32Constant(DAG, 0x3da235e3));
3349 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3350 getF32Constant(DAG, 0x3e65b8f3));
3351 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3352 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3353 getF32Constant(DAG, 0x3f324b07));
3354 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3355 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3356 getF32Constant(DAG, 0x3f7ff8fd));
3357 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3359 // Add the exponent into the result in integer domain.
3360 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3361 TwoToFracPartOfX, IntegerPartOfX);
3363 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3364 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3365 // For floating-point precision of 18:
3367 // TwoToFractionalPartOfX =
3371 // (0.554906021e-1f +
3372 // (0.961591928e-2f +
3373 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3375 // error 2.47208000*10^(-7), which is better than 18 bits
3376 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3377 getF32Constant(DAG, 0x3924b03e));
3378 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3379 getF32Constant(DAG, 0x3ab24b87));
3380 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3381 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3382 getF32Constant(DAG, 0x3c1d8c17));
3383 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3384 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3385 getF32Constant(DAG, 0x3d634a1d));
3386 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3387 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3388 getF32Constant(DAG, 0x3e75fe14));
3389 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3390 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3391 getF32Constant(DAG, 0x3f317234));
3392 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3393 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3394 getF32Constant(DAG, 0x3f800000));
3395 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3398 // Add the exponent into the result in integer domain.
3399 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3400 TwoToFracPartOfX, IntegerPartOfX);
3402 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3405 // No special expansion.
3406 result = DAG.getNode(ISD::FEXP, dl,
3407 getValue(I.getArgOperand(0)).getValueType(),
3408 getValue(I.getArgOperand(0)));
3411 setValue(&I, result);
3414 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3415 /// limited-precision mode.
3417 SelectionDAGBuilder::visitLog(const CallInst &I) {
3419 DebugLoc dl = getCurDebugLoc();
3421 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3422 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3423 SDValue Op = getValue(I.getArgOperand(0));
3424 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3426 // Scale the exponent by log(2) [0.69314718f].
3427 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3428 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3429 getF32Constant(DAG, 0x3f317218));
3431 // Get the significand and build it into a floating-point number with
3433 SDValue X = GetSignificand(DAG, Op1, dl);
3435 if (LimitFloatPrecision <= 6) {
3436 // For floating-point precision of 6:
3440 // (1.4034025f - 0.23903021f * x) * x;
3442 // error 0.0034276066, which is better than 8 bits
3443 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3444 getF32Constant(DAG, 0xbe74c456));
3445 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3446 getF32Constant(DAG, 0x3fb3a2b1));
3447 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3448 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3449 getF32Constant(DAG, 0x3f949a29));
3451 result = DAG.getNode(ISD::FADD, dl,
3452 MVT::f32, LogOfExponent, LogOfMantissa);
3453 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3454 // For floating-point precision of 12:
3460 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3462 // error 0.000061011436, which is 14 bits
3463 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3464 getF32Constant(DAG, 0xbd67b6d6));
3465 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3466 getF32Constant(DAG, 0x3ee4f4b8));
3467 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3468 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3469 getF32Constant(DAG, 0x3fbc278b));
3470 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3471 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3472 getF32Constant(DAG, 0x40348e95));
3473 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3474 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3475 getF32Constant(DAG, 0x3fdef31a));
3477 result = DAG.getNode(ISD::FADD, dl,
3478 MVT::f32, LogOfExponent, LogOfMantissa);
3479 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3480 // For floating-point precision of 18:
3488 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3490 // error 0.0000023660568, which is better than 18 bits
3491 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3492 getF32Constant(DAG, 0xbc91e5ac));
3493 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3494 getF32Constant(DAG, 0x3e4350aa));
3495 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3496 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3497 getF32Constant(DAG, 0x3f60d3e3));
3498 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3499 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3500 getF32Constant(DAG, 0x4011cdf0));
3501 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3502 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3503 getF32Constant(DAG, 0x406cfd1c));
3504 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3505 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3506 getF32Constant(DAG, 0x408797cb));
3507 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3508 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3509 getF32Constant(DAG, 0x4006dcab));
3511 result = DAG.getNode(ISD::FADD, dl,
3512 MVT::f32, LogOfExponent, LogOfMantissa);
3515 // No special expansion.
3516 result = DAG.getNode(ISD::FLOG, dl,
3517 getValue(I.getArgOperand(0)).getValueType(),
3518 getValue(I.getArgOperand(0)));
3521 setValue(&I, result);
3524 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3525 /// limited-precision mode.
3527 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3529 DebugLoc dl = getCurDebugLoc();
3531 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3532 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3533 SDValue Op = getValue(I.getArgOperand(0));
3534 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3536 // Get the exponent.
3537 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3539 // Get the significand and build it into a floating-point number with
3541 SDValue X = GetSignificand(DAG, Op1, dl);
3543 // Different possible minimax approximations of significand in
3544 // floating-point for various degrees of accuracy over [1,2].
3545 if (LimitFloatPrecision <= 6) {
3546 // For floating-point precision of 6:
3548 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3550 // error 0.0049451742, which is more than 7 bits
3551 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3552 getF32Constant(DAG, 0xbeb08fe0));
3553 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3554 getF32Constant(DAG, 0x40019463));
3555 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3556 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3557 getF32Constant(DAG, 0x3fd6633d));
3559 result = DAG.getNode(ISD::FADD, dl,
3560 MVT::f32, LogOfExponent, Log2ofMantissa);
3561 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3562 // For floating-point precision of 12:
3568 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3570 // error 0.0000876136000, which is better than 13 bits
3571 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3572 getF32Constant(DAG, 0xbda7262e));
3573 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3574 getF32Constant(DAG, 0x3f25280b));
3575 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3576 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3577 getF32Constant(DAG, 0x4007b923));
3578 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3579 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3580 getF32Constant(DAG, 0x40823e2f));
3581 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3582 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3583 getF32Constant(DAG, 0x4020d29c));
3585 result = DAG.getNode(ISD::FADD, dl,
3586 MVT::f32, LogOfExponent, Log2ofMantissa);
3587 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3588 // For floating-point precision of 18:
3597 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3599 // error 0.0000018516, which is better than 18 bits
3600 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3601 getF32Constant(DAG, 0xbcd2769e));
3602 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3603 getF32Constant(DAG, 0x3e8ce0b9));
3604 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3605 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3606 getF32Constant(DAG, 0x3fa22ae7));
3607 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3608 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3609 getF32Constant(DAG, 0x40525723));
3610 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3611 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3612 getF32Constant(DAG, 0x40aaf200));
3613 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3614 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3615 getF32Constant(DAG, 0x40c39dad));
3616 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3617 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3618 getF32Constant(DAG, 0x4042902c));
3620 result = DAG.getNode(ISD::FADD, dl,
3621 MVT::f32, LogOfExponent, Log2ofMantissa);
3624 // No special expansion.
3625 result = DAG.getNode(ISD::FLOG2, dl,
3626 getValue(I.getArgOperand(0)).getValueType(),
3627 getValue(I.getArgOperand(0)));
3630 setValue(&I, result);
3633 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3634 /// limited-precision mode.
3636 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3638 DebugLoc dl = getCurDebugLoc();
3640 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3641 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3642 SDValue Op = getValue(I.getArgOperand(0));
3643 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3645 // Scale the exponent by log10(2) [0.30102999f].
3646 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3647 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3648 getF32Constant(DAG, 0x3e9a209a));
3650 // Get the significand and build it into a floating-point number with
3652 SDValue X = GetSignificand(DAG, Op1, dl);
3654 if (LimitFloatPrecision <= 6) {
3655 // For floating-point precision of 6:
3657 // Log10ofMantissa =
3659 // (0.60948995f - 0.10380950f * x) * x;
3661 // error 0.0014886165, which is 6 bits
3662 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3663 getF32Constant(DAG, 0xbdd49a13));
3664 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3665 getF32Constant(DAG, 0x3f1c0789));
3666 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3667 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3668 getF32Constant(DAG, 0x3f011300));
3670 result = DAG.getNode(ISD::FADD, dl,
3671 MVT::f32, LogOfExponent, Log10ofMantissa);
3672 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3673 // For floating-point precision of 12:
3675 // Log10ofMantissa =
3678 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3680 // error 0.00019228036, which is better than 12 bits
3681 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3682 getF32Constant(DAG, 0x3d431f31));
3683 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3684 getF32Constant(DAG, 0x3ea21fb2));
3685 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3686 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3687 getF32Constant(DAG, 0x3f6ae232));
3688 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3689 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3690 getF32Constant(DAG, 0x3f25f7c3));
3692 result = DAG.getNode(ISD::FADD, dl,
3693 MVT::f32, LogOfExponent, Log10ofMantissa);
3694 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3695 // For floating-point precision of 18:
3697 // Log10ofMantissa =
3702 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3704 // error 0.0000037995730, which is better than 18 bits
3705 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3706 getF32Constant(DAG, 0x3c5d51ce));
3707 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3708 getF32Constant(DAG, 0x3e00685a));
3709 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3710 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3711 getF32Constant(DAG, 0x3efb6798));
3712 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3713 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3714 getF32Constant(DAG, 0x3f88d192));
3715 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3716 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3717 getF32Constant(DAG, 0x3fc4316c));
3718 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3719 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3720 getF32Constant(DAG, 0x3f57ce70));
3722 result = DAG.getNode(ISD::FADD, dl,
3723 MVT::f32, LogOfExponent, Log10ofMantissa);
3726 // No special expansion.
3727 result = DAG.getNode(ISD::FLOG10, dl,
3728 getValue(I.getArgOperand(0)).getValueType(),
3729 getValue(I.getArgOperand(0)));
3732 setValue(&I, result);
3735 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3736 /// limited-precision mode.
3738 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3740 DebugLoc dl = getCurDebugLoc();
3742 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3743 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3744 SDValue Op = getValue(I.getArgOperand(0));
3746 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3748 // FractionalPartOfX = x - (float)IntegerPartOfX;
3749 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3750 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3752 // IntegerPartOfX <<= 23;
3753 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3754 DAG.getConstant(23, TLI.getPointerTy()));
3756 if (LimitFloatPrecision <= 6) {
3757 // For floating-point precision of 6:
3759 // TwoToFractionalPartOfX =
3761 // (0.735607626f + 0.252464424f * x) * x;
3763 // error 0.0144103317, which is 6 bits
3764 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3765 getF32Constant(DAG, 0x3e814304));
3766 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3767 getF32Constant(DAG, 0x3f3c50c8));
3768 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3769 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3770 getF32Constant(DAG, 0x3f7f5e7e));
3771 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3772 SDValue TwoToFractionalPartOfX =
3773 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3775 result = DAG.getNode(ISD::BITCAST, dl,
3776 MVT::f32, TwoToFractionalPartOfX);
3777 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3778 // For floating-point precision of 12:
3780 // TwoToFractionalPartOfX =
3783 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3785 // error 0.000107046256, which is 13 to 14 bits
3786 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3787 getF32Constant(DAG, 0x3da235e3));
3788 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3789 getF32Constant(DAG, 0x3e65b8f3));
3790 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3791 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3792 getF32Constant(DAG, 0x3f324b07));
3793 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3794 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3795 getF32Constant(DAG, 0x3f7ff8fd));
3796 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3797 SDValue TwoToFractionalPartOfX =
3798 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3800 result = DAG.getNode(ISD::BITCAST, dl,
3801 MVT::f32, TwoToFractionalPartOfX);
3802 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3803 // For floating-point precision of 18:
3805 // TwoToFractionalPartOfX =
3809 // (0.554906021e-1f +
3810 // (0.961591928e-2f +
3811 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3812 // error 2.47208000*10^(-7), which is better than 18 bits
3813 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3814 getF32Constant(DAG, 0x3924b03e));
3815 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3816 getF32Constant(DAG, 0x3ab24b87));
3817 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3818 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3819 getF32Constant(DAG, 0x3c1d8c17));
3820 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3821 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3822 getF32Constant(DAG, 0x3d634a1d));
3823 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3824 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3825 getF32Constant(DAG, 0x3e75fe14));
3826 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3827 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3828 getF32Constant(DAG, 0x3f317234));
3829 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3830 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3831 getF32Constant(DAG, 0x3f800000));
3832 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3833 SDValue TwoToFractionalPartOfX =
3834 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3836 result = DAG.getNode(ISD::BITCAST, dl,
3837 MVT::f32, TwoToFractionalPartOfX);
3840 // No special expansion.
3841 result = DAG.getNode(ISD::FEXP2, dl,
3842 getValue(I.getArgOperand(0)).getValueType(),
3843 getValue(I.getArgOperand(0)));
3846 setValue(&I, result);
3849 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3850 /// limited-precision mode with x == 10.0f.
3852 SelectionDAGBuilder::visitPow(const CallInst &I) {
3854 const Value *Val = I.getArgOperand(0);
3855 DebugLoc dl = getCurDebugLoc();
3856 bool IsExp10 = false;
3858 if (getValue(Val).getValueType() == MVT::f32 &&
3859 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3860 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3861 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3862 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3864 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3869 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3870 SDValue Op = getValue(I.getArgOperand(1));
3872 // Put the exponent in the right bit position for later addition to the
3875 // #define LOG2OF10 3.3219281f
3876 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3877 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3878 getF32Constant(DAG, 0x40549a78));
3879 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3881 // FractionalPartOfX = x - (float)IntegerPartOfX;
3882 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3883 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3885 // IntegerPartOfX <<= 23;
3886 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3887 DAG.getConstant(23, TLI.getPointerTy()));
3889 if (LimitFloatPrecision <= 6) {
3890 // For floating-point precision of 6:
3892 // twoToFractionalPartOfX =
3894 // (0.735607626f + 0.252464424f * x) * x;
3896 // error 0.0144103317, which is 6 bits
3897 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3898 getF32Constant(DAG, 0x3e814304));
3899 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3900 getF32Constant(DAG, 0x3f3c50c8));
3901 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3902 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3903 getF32Constant(DAG, 0x3f7f5e7e));
3904 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3905 SDValue TwoToFractionalPartOfX =
3906 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3908 result = DAG.getNode(ISD::BITCAST, dl,
3909 MVT::f32, TwoToFractionalPartOfX);
3910 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3911 // For floating-point precision of 12:
3913 // TwoToFractionalPartOfX =
3916 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3918 // error 0.000107046256, which is 13 to 14 bits
3919 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3920 getF32Constant(DAG, 0x3da235e3));
3921 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3922 getF32Constant(DAG, 0x3e65b8f3));
3923 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3924 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3925 getF32Constant(DAG, 0x3f324b07));
3926 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3927 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3928 getF32Constant(DAG, 0x3f7ff8fd));
3929 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3930 SDValue TwoToFractionalPartOfX =
3931 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3933 result = DAG.getNode(ISD::BITCAST, dl,
3934 MVT::f32, TwoToFractionalPartOfX);
3935 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3936 // For floating-point precision of 18:
3938 // TwoToFractionalPartOfX =
3942 // (0.554906021e-1f +
3943 // (0.961591928e-2f +
3944 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3945 // error 2.47208000*10^(-7), which is better than 18 bits
3946 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3947 getF32Constant(DAG, 0x3924b03e));
3948 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3949 getF32Constant(DAG, 0x3ab24b87));
3950 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3951 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3952 getF32Constant(DAG, 0x3c1d8c17));
3953 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3954 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3955 getF32Constant(DAG, 0x3d634a1d));
3956 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3957 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3958 getF32Constant(DAG, 0x3e75fe14));
3959 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3960 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3961 getF32Constant(DAG, 0x3f317234));
3962 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3963 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3964 getF32Constant(DAG, 0x3f800000));
3965 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3966 SDValue TwoToFractionalPartOfX =
3967 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3969 result = DAG.getNode(ISD::BITCAST, dl,
3970 MVT::f32, TwoToFractionalPartOfX);
3973 // No special expansion.
3974 result = DAG.getNode(ISD::FPOW, dl,
3975 getValue(I.getArgOperand(0)).getValueType(),
3976 getValue(I.getArgOperand(0)),
3977 getValue(I.getArgOperand(1)));
3980 setValue(&I, result);
3984 /// ExpandPowI - Expand a llvm.powi intrinsic.
3985 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3986 SelectionDAG &DAG) {
3987 // If RHS is a constant, we can expand this out to a multiplication tree,
3988 // otherwise we end up lowering to a call to __powidf2 (for example). When
3989 // optimizing for size, we only want to do this if the expansion would produce
3990 // a small number of multiplies, otherwise we do the full expansion.
3991 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3992 // Get the exponent as a positive value.
3993 unsigned Val = RHSC->getSExtValue();
3994 if ((int)Val < 0) Val = -Val;
3996 // powi(x, 0) -> 1.0
3998 return DAG.getConstantFP(1.0, LHS.getValueType());
4000 const Function *F = DAG.getMachineFunction().getFunction();
4001 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4002 // If optimizing for size, don't insert too many multiplies. This
4003 // inserts up to 5 multiplies.
4004 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4005 // We use the simple binary decomposition method to generate the multiply
4006 // sequence. There are more optimal ways to do this (for example,
4007 // powi(x,15) generates one more multiply than it should), but this has
4008 // the benefit of being both really simple and much better than a libcall.
4009 SDValue Res; // Logically starts equal to 1.0
4010 SDValue CurSquare = LHS;
4014 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4016 Res = CurSquare; // 1.0*CurSquare.
4019 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4020 CurSquare, CurSquare);
4024 // If the original was negative, invert the result, producing 1/(x*x*x).
4025 if (RHSC->getSExtValue() < 0)
4026 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4027 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4032 // Otherwise, expand to a libcall.
4033 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4036 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4037 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4038 /// At the end of instruction selection, they will be inserted to the entry BB.
4040 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4043 const Argument *Arg = dyn_cast<Argument>(V);
4047 MachineFunction &MF = DAG.getMachineFunction();
4048 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4049 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4051 // Ignore inlined function arguments here.
4052 DIVariable DV(Variable);
4053 if (DV.isInlinedFnArgument(MF.getFunction()))
4056 MachineBasicBlock *MBB = FuncInfo.MBB;
4057 if (MBB != &MF.front())
4061 if (Arg->hasByValAttr()) {
4062 // Byval arguments' frame index is recorded during argument lowering.
4063 // Use this info directly.
4064 Reg = TRI->getFrameRegister(MF);
4065 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4066 // If byval argument ofset is not recorded then ignore this.
4071 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) {
4072 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4073 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4074 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4075 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4082 // Check if ValueMap has reg number.
4083 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4084 if (VMI != FuncInfo.ValueMap.end())
4088 if (!Reg && N.getNode()) {
4089 // Check if frame index is available.
4090 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4091 if (FrameIndexSDNode *FINode =
4092 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4093 Reg = TRI->getFrameRegister(MF);
4094 Offset = FINode->getIndex();
4101 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4102 TII->get(TargetOpcode::DBG_VALUE))
4103 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4104 FuncInfo.ArgDbgValues.push_back(&*MIB);
4108 // VisualStudio defines setjmp as _setjmp
4109 #if defined(_MSC_VER) && defined(setjmp) && \
4110 !defined(setjmp_undefined_for_msvc)
4111 # pragma push_macro("setjmp")
4113 # define setjmp_undefined_for_msvc
4116 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4117 /// we want to emit this as a call to a named external function, return the name
4118 /// otherwise lower it and return null.
4120 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4121 DebugLoc dl = getCurDebugLoc();
4124 switch (Intrinsic) {
4126 // By default, turn this into a target intrinsic node.
4127 visitTargetIntrinsic(I, Intrinsic);
4129 case Intrinsic::vastart: visitVAStart(I); return 0;
4130 case Intrinsic::vaend: visitVAEnd(I); return 0;
4131 case Intrinsic::vacopy: visitVACopy(I); return 0;
4132 case Intrinsic::returnaddress:
4133 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4134 getValue(I.getArgOperand(0))));
4136 case Intrinsic::frameaddress:
4137 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4138 getValue(I.getArgOperand(0))));
4140 case Intrinsic::setjmp:
4141 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4142 case Intrinsic::longjmp:
4143 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4144 case Intrinsic::memcpy: {
4145 // Assert for address < 256 since we support only user defined address
4147 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4149 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4151 "Unknown address space");
4152 SDValue Op1 = getValue(I.getArgOperand(0));
4153 SDValue Op2 = getValue(I.getArgOperand(1));
4154 SDValue Op3 = getValue(I.getArgOperand(2));
4155 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4156 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4157 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4158 MachinePointerInfo(I.getArgOperand(0)),
4159 MachinePointerInfo(I.getArgOperand(1))));
4162 case Intrinsic::memset: {
4163 // Assert for address < 256 since we support only user defined address
4165 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4167 "Unknown address space");
4168 SDValue Op1 = getValue(I.getArgOperand(0));
4169 SDValue Op2 = getValue(I.getArgOperand(1));
4170 SDValue Op3 = getValue(I.getArgOperand(2));
4171 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4172 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4173 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4174 MachinePointerInfo(I.getArgOperand(0))));
4177 case Intrinsic::memmove: {
4178 // Assert for address < 256 since we support only user defined address
4180 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4182 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4184 "Unknown address space");
4185 SDValue Op1 = getValue(I.getArgOperand(0));
4186 SDValue Op2 = getValue(I.getArgOperand(1));
4187 SDValue Op3 = getValue(I.getArgOperand(2));
4188 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4189 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4190 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4191 MachinePointerInfo(I.getArgOperand(0)),
4192 MachinePointerInfo(I.getArgOperand(1))));
4195 case Intrinsic::dbg_declare: {
4196 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4197 MDNode *Variable = DI.getVariable();
4198 const Value *Address = DI.getAddress();
4199 if (!Address || !DIVariable(DI.getVariable()).Verify())
4202 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4203 // but do not always have a corresponding SDNode built. The SDNodeOrder
4204 // absolute, but not relative, values are different depending on whether
4205 // debug info exists.
4208 // Check if address has undef value.
4209 if (isa<UndefValue>(Address) ||
4210 (Address->use_empty() && !isa<Argument>(Address))) {
4211 DEBUG(dbgs() << "Dropping debug info for " << DI);
4215 SDValue &N = NodeMap[Address];
4216 if (!N.getNode() && isa<Argument>(Address))
4217 // Check unused arguments map.
4218 N = UnusedArgNodeMap[Address];
4221 // Parameters are handled specially.
4223 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4224 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4225 Address = BCI->getOperand(0);
4226 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4228 if (isParameter && !AI) {
4229 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4231 // Byval parameter. We have a frame index at this point.
4232 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4233 0, dl, SDNodeOrder);
4235 // Can't do anything with other non-AI cases yet. This might be a
4236 // parameter of a callee function that got inlined, for example.
4237 DEBUG(dbgs() << "Dropping debug info for " << DI);
4241 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4242 0, dl, SDNodeOrder);
4244 // Can't do anything with other non-AI cases yet.
4245 DEBUG(dbgs() << "Dropping debug info for " << DI);
4248 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4250 // If Address is an argument then try to emit its dbg value using
4251 // virtual register info from the FuncInfo.ValueMap.
4252 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4253 // If variable is pinned by a alloca in dominating bb then
4254 // use StaticAllocaMap.
4255 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4256 if (AI->getParent() != DI.getParent()) {
4257 DenseMap<const AllocaInst*, int>::iterator SI =
4258 FuncInfo.StaticAllocaMap.find(AI);
4259 if (SI != FuncInfo.StaticAllocaMap.end()) {
4260 SDV = DAG.getDbgValue(Variable, SI->second,
4261 0, dl, SDNodeOrder);
4262 DAG.AddDbgValue(SDV, 0, false);
4267 DEBUG(dbgs() << "Dropping debug info for " << DI);
4272 case Intrinsic::dbg_value: {
4273 const DbgValueInst &DI = cast<DbgValueInst>(I);
4274 if (!DIVariable(DI.getVariable()).Verify())
4277 MDNode *Variable = DI.getVariable();
4278 uint64_t Offset = DI.getOffset();
4279 const Value *V = DI.getValue();
4283 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4284 // but do not always have a corresponding SDNode built. The SDNodeOrder
4285 // absolute, but not relative, values are different depending on whether
4286 // debug info exists.
4289 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4290 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4291 DAG.AddDbgValue(SDV, 0, false);
4293 // Do not use getValue() in here; we don't want to generate code at
4294 // this point if it hasn't been done yet.
4295 SDValue N = NodeMap[V];
4296 if (!N.getNode() && isa<Argument>(V))
4297 // Check unused arguments map.
4298 N = UnusedArgNodeMap[V];
4300 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4301 SDV = DAG.getDbgValue(Variable, N.getNode(),
4302 N.getResNo(), Offset, dl, SDNodeOrder);
4303 DAG.AddDbgValue(SDV, N.getNode(), false);
4305 } else if (isa<PHINode>(V) && !V->use_empty() ) {
4306 // Do not call getValue(V) yet, as we don't want to generate code.
4307 // Remember it for later.
4308 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4309 DanglingDebugInfoMap[V] = DDI;
4311 // We may expand this to cover more cases. One case where we have no
4312 // data available is an unreferenced parameter.
4313 DEBUG(dbgs() << "Dropping debug info for " << DI);
4317 // Build a debug info table entry.
4318 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4319 V = BCI->getOperand(0);
4320 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4321 // Don't handle byval struct arguments or VLAs, for example.
4324 DenseMap<const AllocaInst*, int>::iterator SI =
4325 FuncInfo.StaticAllocaMap.find(AI);
4326 if (SI == FuncInfo.StaticAllocaMap.end())
4328 int FI = SI->second;
4330 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4331 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4332 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4335 case Intrinsic::eh_exception: {
4336 // Insert the EXCEPTIONADDR instruction.
4337 assert(FuncInfo.MBB->isLandingPad() &&
4338 "Call to eh.exception not in landing pad!");
4339 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4341 Ops[0] = DAG.getRoot();
4342 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4344 DAG.setRoot(Op.getValue(1));
4348 case Intrinsic::eh_selector: {
4349 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4350 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4351 if (CallMBB->isLandingPad())
4352 AddCatchInfo(I, &MMI, CallMBB);
4355 FuncInfo.CatchInfoLost.insert(&I);
4357 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4358 unsigned Reg = TLI.getExceptionSelectorRegister();
4359 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4362 // Insert the EHSELECTION instruction.
4363 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4365 Ops[0] = getValue(I.getArgOperand(0));
4367 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4368 DAG.setRoot(Op.getValue(1));
4369 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4373 case Intrinsic::eh_typeid_for: {
4374 // Find the type id for the given typeinfo.
4375 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4376 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4377 Res = DAG.getConstant(TypeID, MVT::i32);
4382 case Intrinsic::eh_return_i32:
4383 case Intrinsic::eh_return_i64:
4384 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4385 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4388 getValue(I.getArgOperand(0)),
4389 getValue(I.getArgOperand(1))));
4391 case Intrinsic::eh_unwind_init:
4392 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4394 case Intrinsic::eh_dwarf_cfa: {
4395 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4396 TLI.getPointerTy());
4397 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4399 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4400 TLI.getPointerTy()),
4402 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4404 DAG.getConstant(0, TLI.getPointerTy()));
4405 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4409 case Intrinsic::eh_sjlj_callsite: {
4410 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4411 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4412 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4413 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4415 MMI.setCurrentCallSite(CI->getZExtValue());
4418 case Intrinsic::eh_sjlj_setjmp: {
4419 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4420 getValue(I.getArgOperand(0))));
4423 case Intrinsic::eh_sjlj_longjmp: {
4424 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4425 getRoot(), getValue(I.getArgOperand(0))));
4428 case Intrinsic::eh_sjlj_dispatch_setup: {
4429 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4430 getRoot(), getValue(I.getArgOperand(0))));
4434 case Intrinsic::x86_mmx_pslli_w:
4435 case Intrinsic::x86_mmx_pslli_d:
4436 case Intrinsic::x86_mmx_pslli_q:
4437 case Intrinsic::x86_mmx_psrli_w:
4438 case Intrinsic::x86_mmx_psrli_d:
4439 case Intrinsic::x86_mmx_psrli_q:
4440 case Intrinsic::x86_mmx_psrai_w:
4441 case Intrinsic::x86_mmx_psrai_d: {
4442 SDValue ShAmt = getValue(I.getArgOperand(1));
4443 if (isa<ConstantSDNode>(ShAmt)) {
4444 visitTargetIntrinsic(I, Intrinsic);
4447 unsigned NewIntrinsic = 0;
4448 EVT ShAmtVT = MVT::v2i32;
4449 switch (Intrinsic) {
4450 case Intrinsic::x86_mmx_pslli_w:
4451 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4453 case Intrinsic::x86_mmx_pslli_d:
4454 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4456 case Intrinsic::x86_mmx_pslli_q:
4457 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4459 case Intrinsic::x86_mmx_psrli_w:
4460 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4462 case Intrinsic::x86_mmx_psrli_d:
4463 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4465 case Intrinsic::x86_mmx_psrli_q:
4466 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4468 case Intrinsic::x86_mmx_psrai_w:
4469 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4471 case Intrinsic::x86_mmx_psrai_d:
4472 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4474 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4477 // The vector shift intrinsics with scalars uses 32b shift amounts but
4478 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4480 // We must do this early because v2i32 is not a legal type.
4481 DebugLoc dl = getCurDebugLoc();
4484 ShOps[1] = DAG.getConstant(0, MVT::i32);
4485 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4486 EVT DestVT = TLI.getValueType(I.getType());
4487 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4488 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4489 DAG.getConstant(NewIntrinsic, MVT::i32),
4490 getValue(I.getArgOperand(0)), ShAmt);
4494 case Intrinsic::convertff:
4495 case Intrinsic::convertfsi:
4496 case Intrinsic::convertfui:
4497 case Intrinsic::convertsif:
4498 case Intrinsic::convertuif:
4499 case Intrinsic::convertss:
4500 case Intrinsic::convertsu:
4501 case Intrinsic::convertus:
4502 case Intrinsic::convertuu: {
4503 ISD::CvtCode Code = ISD::CVT_INVALID;
4504 switch (Intrinsic) {
4505 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4506 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4507 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4508 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4509 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4510 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4511 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4512 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4513 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4515 EVT DestVT = TLI.getValueType(I.getType());
4516 const Value *Op1 = I.getArgOperand(0);
4517 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4518 DAG.getValueType(DestVT),
4519 DAG.getValueType(getValue(Op1).getValueType()),
4520 getValue(I.getArgOperand(1)),
4521 getValue(I.getArgOperand(2)),
4526 case Intrinsic::sqrt:
4527 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4528 getValue(I.getArgOperand(0)).getValueType(),
4529 getValue(I.getArgOperand(0))));
4531 case Intrinsic::powi:
4532 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4533 getValue(I.getArgOperand(1)), DAG));
4535 case Intrinsic::sin:
4536 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4537 getValue(I.getArgOperand(0)).getValueType(),
4538 getValue(I.getArgOperand(0))));
4540 case Intrinsic::cos:
4541 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4542 getValue(I.getArgOperand(0)).getValueType(),
4543 getValue(I.getArgOperand(0))));
4545 case Intrinsic::log:
4548 case Intrinsic::log2:
4551 case Intrinsic::log10:
4554 case Intrinsic::exp:
4557 case Intrinsic::exp2:
4560 case Intrinsic::pow:
4563 case Intrinsic::convert_to_fp16:
4564 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4565 MVT::i16, getValue(I.getArgOperand(0))));
4567 case Intrinsic::convert_from_fp16:
4568 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4569 MVT::f32, getValue(I.getArgOperand(0))));
4571 case Intrinsic::pcmarker: {
4572 SDValue Tmp = getValue(I.getArgOperand(0));
4573 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4576 case Intrinsic::readcyclecounter: {
4577 SDValue Op = getRoot();
4578 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4579 DAG.getVTList(MVT::i64, MVT::Other),
4582 DAG.setRoot(Res.getValue(1));
4585 case Intrinsic::bswap:
4586 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4587 getValue(I.getArgOperand(0)).getValueType(),
4588 getValue(I.getArgOperand(0))));
4590 case Intrinsic::cttz: {
4591 SDValue Arg = getValue(I.getArgOperand(0));
4592 EVT Ty = Arg.getValueType();
4593 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4596 case Intrinsic::ctlz: {
4597 SDValue Arg = getValue(I.getArgOperand(0));
4598 EVT Ty = Arg.getValueType();
4599 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4602 case Intrinsic::ctpop: {
4603 SDValue Arg = getValue(I.getArgOperand(0));
4604 EVT Ty = Arg.getValueType();
4605 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4608 case Intrinsic::stacksave: {
4609 SDValue Op = getRoot();
4610 Res = DAG.getNode(ISD::STACKSAVE, dl,
4611 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4613 DAG.setRoot(Res.getValue(1));
4616 case Intrinsic::stackrestore: {
4617 Res = getValue(I.getArgOperand(0));
4618 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4621 case Intrinsic::stackprotector: {
4622 // Emit code into the DAG to store the stack guard onto the stack.
4623 MachineFunction &MF = DAG.getMachineFunction();
4624 MachineFrameInfo *MFI = MF.getFrameInfo();
4625 EVT PtrTy = TLI.getPointerTy();
4627 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4628 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4630 int FI = FuncInfo.StaticAllocaMap[Slot];
4631 MFI->setStackProtectorIndex(FI);
4633 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4635 // Store the stack protector onto the stack.
4636 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4637 MachinePointerInfo::getFixedStack(FI),
4643 case Intrinsic::objectsize: {
4644 // If we don't know by now, we're never going to know.
4645 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4647 assert(CI && "Non-constant type in __builtin_object_size?");
4649 SDValue Arg = getValue(I.getCalledValue());
4650 EVT Ty = Arg.getValueType();
4653 Res = DAG.getConstant(-1ULL, Ty);
4655 Res = DAG.getConstant(0, Ty);
4660 case Intrinsic::var_annotation:
4661 // Discard annotate attributes
4664 case Intrinsic::init_trampoline: {
4665 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4669 Ops[1] = getValue(I.getArgOperand(0));
4670 Ops[2] = getValue(I.getArgOperand(1));
4671 Ops[3] = getValue(I.getArgOperand(2));
4672 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4673 Ops[5] = DAG.getSrcValue(F);
4675 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4676 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4680 DAG.setRoot(Res.getValue(1));
4683 case Intrinsic::gcroot:
4685 const Value *Alloca = I.getArgOperand(0);
4686 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4688 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4689 GFI->addStackRoot(FI->getIndex(), TypeMap);
4692 case Intrinsic::gcread:
4693 case Intrinsic::gcwrite:
4694 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4696 case Intrinsic::flt_rounds:
4697 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4699 case Intrinsic::trap:
4700 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4702 case Intrinsic::uadd_with_overflow:
4703 return implVisitAluOverflow(I, ISD::UADDO);
4704 case Intrinsic::sadd_with_overflow:
4705 return implVisitAluOverflow(I, ISD::SADDO);
4706 case Intrinsic::usub_with_overflow:
4707 return implVisitAluOverflow(I, ISD::USUBO);
4708 case Intrinsic::ssub_with_overflow:
4709 return implVisitAluOverflow(I, ISD::SSUBO);
4710 case Intrinsic::umul_with_overflow:
4711 return implVisitAluOverflow(I, ISD::UMULO);
4712 case Intrinsic::smul_with_overflow:
4713 return implVisitAluOverflow(I, ISD::SMULO);
4715 case Intrinsic::prefetch: {
4717 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4719 Ops[1] = getValue(I.getArgOperand(0));
4720 Ops[2] = getValue(I.getArgOperand(1));
4721 Ops[3] = getValue(I.getArgOperand(2));
4722 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4723 DAG.getVTList(MVT::Other),
4725 EVT::getIntegerVT(*Context, 8),
4726 MachinePointerInfo(I.getArgOperand(0)),
4728 false, /* volatile */
4730 rw==1)); /* write */
4733 case Intrinsic::memory_barrier: {
4736 for (int x = 1; x < 6; ++x)
4737 Ops[x] = getValue(I.getArgOperand(x - 1));
4739 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4742 case Intrinsic::atomic_cmp_swap: {
4743 SDValue Root = getRoot();
4745 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4746 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4748 getValue(I.getArgOperand(0)),
4749 getValue(I.getArgOperand(1)),
4750 getValue(I.getArgOperand(2)),
4751 MachinePointerInfo(I.getArgOperand(0)));
4753 DAG.setRoot(L.getValue(1));
4756 case Intrinsic::atomic_load_add:
4757 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4758 case Intrinsic::atomic_load_sub:
4759 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4760 case Intrinsic::atomic_load_or:
4761 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4762 case Intrinsic::atomic_load_xor:
4763 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4764 case Intrinsic::atomic_load_and:
4765 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4766 case Intrinsic::atomic_load_nand:
4767 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4768 case Intrinsic::atomic_load_max:
4769 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4770 case Intrinsic::atomic_load_min:
4771 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4772 case Intrinsic::atomic_load_umin:
4773 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4774 case Intrinsic::atomic_load_umax:
4775 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4776 case Intrinsic::atomic_swap:
4777 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4779 case Intrinsic::invariant_start:
4780 case Intrinsic::lifetime_start:
4781 // Discard region information.
4782 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4784 case Intrinsic::invariant_end:
4785 case Intrinsic::lifetime_end:
4786 // Discard region information.
4791 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4793 MachineBasicBlock *LandingPad) {
4794 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4795 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4796 const Type *RetTy = FTy->getReturnType();
4797 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4798 MCSymbol *BeginLabel = 0;
4800 TargetLowering::ArgListTy Args;
4801 TargetLowering::ArgListEntry Entry;
4802 Args.reserve(CS.arg_size());
4804 // Check whether the function can return without sret-demotion.
4805 SmallVector<ISD::OutputArg, 4> Outs;
4806 SmallVector<uint64_t, 4> Offsets;
4807 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4808 Outs, TLI, &Offsets);
4810 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4811 FTy->isVarArg(), Outs, FTy->getContext());
4813 SDValue DemoteStackSlot;
4814 int DemoteStackIdx = -100;
4816 if (!CanLowerReturn) {
4817 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4818 FTy->getReturnType());
4819 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4820 FTy->getReturnType());
4821 MachineFunction &MF = DAG.getMachineFunction();
4822 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4823 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4825 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4826 Entry.Node = DemoteStackSlot;
4827 Entry.Ty = StackSlotPtrType;
4828 Entry.isSExt = false;
4829 Entry.isZExt = false;
4830 Entry.isInReg = false;
4831 Entry.isSRet = true;
4832 Entry.isNest = false;
4833 Entry.isByVal = false;
4834 Entry.Alignment = Align;
4835 Args.push_back(Entry);
4836 RetTy = Type::getVoidTy(FTy->getContext());
4839 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4841 SDValue ArgNode = getValue(*i);
4842 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4844 unsigned attrInd = i - CS.arg_begin() + 1;
4845 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4846 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4847 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4848 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4849 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4850 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4851 Entry.Alignment = CS.getParamAlignment(attrInd);
4852 Args.push_back(Entry);
4856 // Insert a label before the invoke call to mark the try range. This can be
4857 // used to detect deletion of the invoke via the MachineModuleInfo.
4858 BeginLabel = MMI.getContext().CreateTempSymbol();
4860 // For SjLj, keep track of which landing pads go with which invokes
4861 // so as to maintain the ordering of pads in the LSDA.
4862 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4863 if (CallSiteIndex) {
4864 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4865 // Now that the call site is handled, stop tracking it.
4866 MMI.setCurrentCallSite(0);
4869 // Both PendingLoads and PendingExports must be flushed here;
4870 // this call might not return.
4872 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4875 // Check if target-independent constraints permit a tail call here.
4876 // Target-dependent constraints are checked within TLI.LowerCallTo.
4878 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4881 // If there's a possibility that fast-isel has already selected some amount
4882 // of the current basic block, don't emit a tail call.
4883 if (isTailCall && EnableFastISel)
4886 std::pair<SDValue,SDValue> Result =
4887 TLI.LowerCallTo(getRoot(), RetTy,
4888 CS.paramHasAttr(0, Attribute::SExt),
4889 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4890 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4891 CS.getCallingConv(),
4893 !CS.getInstruction()->use_empty(),
4894 Callee, Args, DAG, getCurDebugLoc());
4895 assert((isTailCall || Result.second.getNode()) &&
4896 "Non-null chain expected with non-tail call!");
4897 assert((Result.second.getNode() || !Result.first.getNode()) &&
4898 "Null value expected with tail call!");
4899 if (Result.first.getNode()) {
4900 setValue(CS.getInstruction(), Result.first);
4901 } else if (!CanLowerReturn && Result.second.getNode()) {
4902 // The instruction result is the result of loading from the
4903 // hidden sret parameter.
4904 SmallVector<EVT, 1> PVTs;
4905 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4907 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4908 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4909 EVT PtrVT = PVTs[0];
4910 unsigned NumValues = Outs.size();
4911 SmallVector<SDValue, 4> Values(NumValues);
4912 SmallVector<SDValue, 4> Chains(NumValues);
4914 for (unsigned i = 0; i < NumValues; ++i) {
4915 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4917 DAG.getConstant(Offsets[i], PtrVT));
4918 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4920 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
4923 Chains[i] = L.getValue(1);
4926 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4927 MVT::Other, &Chains[0], NumValues);
4928 PendingLoads.push_back(Chain);
4930 // Collect the legal value parts into potentially illegal values
4931 // that correspond to the original function's return values.
4932 SmallVector<EVT, 4> RetTys;
4933 RetTy = FTy->getReturnType();
4934 ComputeValueVTs(TLI, RetTy, RetTys);
4935 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4936 SmallVector<SDValue, 4> ReturnValues;
4937 unsigned CurReg = 0;
4938 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4940 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4941 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4943 SDValue ReturnValue =
4944 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4945 RegisterVT, VT, AssertOp);
4946 ReturnValues.push_back(ReturnValue);
4950 setValue(CS.getInstruction(),
4951 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4952 DAG.getVTList(&RetTys[0], RetTys.size()),
4953 &ReturnValues[0], ReturnValues.size()));
4957 // As a special case, a null chain means that a tail call has been emitted and
4958 // the DAG root is already updated.
4959 if (Result.second.getNode())
4960 DAG.setRoot(Result.second);
4965 // Insert a label at the end of the invoke call to mark the try range. This
4966 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4967 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4968 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4970 // Inform MachineModuleInfo of range.
4971 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4975 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4976 /// value is equal or not-equal to zero.
4977 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4978 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4980 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4981 if (IC->isEquality())
4982 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4983 if (C->isNullValue())
4985 // Unknown instruction.
4991 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4993 SelectionDAGBuilder &Builder) {
4995 // Check to see if this load can be trivially constant folded, e.g. if the
4996 // input is from a string literal.
4997 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4998 // Cast pointer to the type we really want to load.
4999 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5000 PointerType::getUnqual(LoadTy));
5002 if (const Constant *LoadCst =
5003 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5005 return Builder.getValue(LoadCst);
5008 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5009 // still constant memory, the input chain can be the entry node.
5011 bool ConstantMemory = false;
5013 // Do not serialize (non-volatile) loads of constant memory with anything.
5014 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5015 Root = Builder.DAG.getEntryNode();
5016 ConstantMemory = true;
5018 // Do not serialize non-volatile loads against each other.
5019 Root = Builder.DAG.getRoot();
5022 SDValue Ptr = Builder.getValue(PtrVal);
5023 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5024 Ptr, MachinePointerInfo(PtrVal),
5026 false /*nontemporal*/, 1 /* align=1 */);
5028 if (!ConstantMemory)
5029 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5034 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5035 /// If so, return true and lower it, otherwise return false and it will be
5036 /// lowered like a normal call.
5037 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5038 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5039 if (I.getNumArgOperands() != 3)
5042 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5043 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5044 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5045 !I.getType()->isIntegerTy())
5048 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5050 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5051 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5052 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5053 bool ActuallyDoIt = true;
5056 switch (Size->getZExtValue()) {
5058 LoadVT = MVT::Other;
5060 ActuallyDoIt = false;
5064 LoadTy = Type::getInt16Ty(Size->getContext());
5068 LoadTy = Type::getInt32Ty(Size->getContext());
5072 LoadTy = Type::getInt64Ty(Size->getContext());
5076 LoadVT = MVT::v4i32;
5077 LoadTy = Type::getInt32Ty(Size->getContext());
5078 LoadTy = VectorType::get(LoadTy, 4);
5083 // This turns into unaligned loads. We only do this if the target natively
5084 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5085 // we'll only produce a small number of byte loads.
5087 // Require that we can find a legal MVT, and only do this if the target
5088 // supports unaligned loads of that type. Expanding into byte loads would
5090 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5091 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5092 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5093 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5094 ActuallyDoIt = false;
5098 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5099 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5101 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5103 EVT CallVT = TLI.getValueType(I.getType(), true);
5104 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5114 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5115 // Handle inline assembly differently.
5116 if (isa<InlineAsm>(I.getCalledValue())) {
5121 // See if any floating point values are being passed to this function. This is
5122 // used to emit an undefined reference to fltused on Windows.
5123 const FunctionType *FT =
5124 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5125 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5126 if (FT->isVarArg() &&
5127 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5128 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5129 const Type* T = I.getArgOperand(i)->getType();
5130 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T);
5132 if (!i->isFloatingPointTy()) continue;
5133 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5139 const char *RenameFn = 0;
5140 if (Function *F = I.getCalledFunction()) {
5141 if (F->isDeclaration()) {
5142 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5143 if (unsigned IID = II->getIntrinsicID(F)) {
5144 RenameFn = visitIntrinsicCall(I, IID);
5149 if (unsigned IID = F->getIntrinsicID()) {
5150 RenameFn = visitIntrinsicCall(I, IID);
5156 // Check for well-known libc/libm calls. If the function is internal, it
5157 // can't be a library call.
5158 if (!F->hasLocalLinkage() && F->hasName()) {
5159 StringRef Name = F->getName();
5160 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5161 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5162 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5163 I.getType() == I.getArgOperand(0)->getType() &&
5164 I.getType() == I.getArgOperand(1)->getType()) {
5165 SDValue LHS = getValue(I.getArgOperand(0));
5166 SDValue RHS = getValue(I.getArgOperand(1));
5167 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5168 LHS.getValueType(), LHS, RHS));
5171 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5172 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5173 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5174 I.getType() == I.getArgOperand(0)->getType()) {
5175 SDValue Tmp = getValue(I.getArgOperand(0));
5176 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5177 Tmp.getValueType(), Tmp));
5180 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5181 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5182 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5183 I.getType() == I.getArgOperand(0)->getType() &&
5184 I.onlyReadsMemory()) {
5185 SDValue Tmp = getValue(I.getArgOperand(0));
5186 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5187 Tmp.getValueType(), Tmp));
5190 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5191 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5192 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5193 I.getType() == I.getArgOperand(0)->getType() &&
5194 I.onlyReadsMemory()) {
5195 SDValue Tmp = getValue(I.getArgOperand(0));
5196 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5197 Tmp.getValueType(), Tmp));
5200 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5201 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5202 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5203 I.getType() == I.getArgOperand(0)->getType() &&
5204 I.onlyReadsMemory()) {
5205 SDValue Tmp = getValue(I.getArgOperand(0));
5206 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5207 Tmp.getValueType(), Tmp));
5210 } else if (Name == "memcmp") {
5211 if (visitMemCmpCall(I))
5219 Callee = getValue(I.getCalledValue());
5221 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5223 // Check if we can potentially perform a tail call. More detailed checking is
5224 // be done within LowerCallTo, after more information about the call is known.
5225 LowerCallTo(&I, Callee, I.isTailCall());
5230 /// AsmOperandInfo - This contains information for each constraint that we are
5232 class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo :
5233 public TargetLowering::AsmOperandInfo {
5235 /// CallOperand - If this is the result output operand or a clobber
5236 /// this is null, otherwise it is the incoming operand to the CallInst.
5237 /// This gets modified as the asm is processed.
5238 SDValue CallOperand;
5240 /// AssignedRegs - If this is a register or register class operand, this
5241 /// contains the set of register corresponding to the operand.
5242 RegsForValue AssignedRegs;
5244 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5245 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5248 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5249 /// busy in OutputRegs/InputRegs.
5250 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5251 std::set<unsigned> &OutputRegs,
5252 std::set<unsigned> &InputRegs,
5253 const TargetRegisterInfo &TRI) const {
5255 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5256 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5259 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5260 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5264 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5265 /// corresponds to. If there is no Value* for this operand, it returns
5267 EVT getCallOperandValEVT(LLVMContext &Context,
5268 const TargetLowering &TLI,
5269 const TargetData *TD) const {
5270 if (CallOperandVal == 0) return MVT::Other;
5272 if (isa<BasicBlock>(CallOperandVal))
5273 return TLI.getPointerTy();
5275 const llvm::Type *OpTy = CallOperandVal->getType();
5277 // If this is an indirect operand, the operand is a pointer to the
5280 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5282 report_fatal_error("Indirect operand for inline asm not a pointer!");
5283 OpTy = PtrTy->getElementType();
5286 // If OpTy is not a single value, it may be a struct/union that we
5287 // can tile with integers.
5288 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5289 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5298 OpTy = IntegerType::get(Context, BitSize);
5303 return TLI.getValueType(OpTy, true);
5307 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5309 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5310 const TargetRegisterInfo &TRI) {
5311 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5313 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5314 for (; *Aliases; ++Aliases)
5315 Regs.insert(*Aliases);
5319 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5321 } // end llvm namespace.
5323 /// isAllocatableRegister - If the specified register is safe to allocate,
5324 /// i.e. it isn't a stack pointer or some other special register, return the
5325 /// register class for the register. Otherwise, return null.
5326 static const TargetRegisterClass *
5327 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5328 const TargetLowering &TLI,
5329 const TargetRegisterInfo *TRI) {
5330 EVT FoundVT = MVT::Other;
5331 const TargetRegisterClass *FoundRC = 0;
5332 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5333 E = TRI->regclass_end(); RCI != E; ++RCI) {
5334 EVT ThisVT = MVT::Other;
5336 const TargetRegisterClass *RC = *RCI;
5337 // If none of the value types for this register class are valid, we
5338 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5339 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5341 if (TLI.isTypeLegal(*I)) {
5342 // If we have already found this register in a different register class,
5343 // choose the one with the largest VT specified. For example, on
5344 // PowerPC, we favor f64 register classes over f32.
5345 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5352 if (ThisVT == MVT::Other) continue;
5354 // NOTE: This isn't ideal. In particular, this might allocate the
5355 // frame pointer in functions that need it (due to them not being taken
5356 // out of allocation, because a variable sized allocation hasn't been seen
5357 // yet). This is a slight code pessimization, but should still work.
5358 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5359 E = RC->allocation_order_end(MF); I != E; ++I)
5361 // We found a matching register class. Keep looking at others in case
5362 // we find one with larger registers that this physreg is also in.
5371 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5372 /// specified operand. We prefer to assign virtual registers, to allow the
5373 /// register allocator to handle the assignment process. However, if the asm
5374 /// uses features that we can't model on machineinstrs, we have SDISel do the
5375 /// allocation. This produces generally horrible, but correct, code.
5377 /// OpInfo describes the operand.
5378 /// Input and OutputRegs are the set of already allocated physical registers.
5380 void SelectionDAGBuilder::
5381 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5382 std::set<unsigned> &OutputRegs,
5383 std::set<unsigned> &InputRegs) {
5384 LLVMContext &Context = FuncInfo.Fn->getContext();
5386 // Compute whether this value requires an input register, an output register,
5388 bool isOutReg = false;
5389 bool isInReg = false;
5390 switch (OpInfo.Type) {
5391 case InlineAsm::isOutput:
5394 // If there is an input constraint that matches this, we need to reserve
5395 // the input register so no other inputs allocate to it.
5396 isInReg = OpInfo.hasMatchingInput();
5398 case InlineAsm::isInput:
5402 case InlineAsm::isClobber:
5409 MachineFunction &MF = DAG.getMachineFunction();
5410 SmallVector<unsigned, 4> Regs;
5412 // If this is a constraint for a single physreg, or a constraint for a
5413 // register class, find it.
5414 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5415 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5416 OpInfo.ConstraintVT);
5418 unsigned NumRegs = 1;
5419 if (OpInfo.ConstraintVT != MVT::Other) {
5420 // If this is a FP input in an integer register (or visa versa) insert a bit
5421 // cast of the input value. More generally, handle any case where the input
5422 // value disagrees with the register class we plan to stick this in.
5423 if (OpInfo.Type == InlineAsm::isInput &&
5424 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5425 // Try to convert to the first EVT that the reg class contains. If the
5426 // types are identical size, use a bitcast to convert (e.g. two differing
5428 EVT RegVT = *PhysReg.second->vt_begin();
5429 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5430 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5431 RegVT, OpInfo.CallOperand);
5432 OpInfo.ConstraintVT = RegVT;
5433 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5434 // If the input is a FP value and we want it in FP registers, do a
5435 // bitcast to the corresponding integer type. This turns an f64 value
5436 // into i64, which can be passed with two i32 values on a 32-bit
5438 RegVT = EVT::getIntegerVT(Context,
5439 OpInfo.ConstraintVT.getSizeInBits());
5440 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5441 RegVT, OpInfo.CallOperand);
5442 OpInfo.ConstraintVT = RegVT;
5446 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5450 EVT ValueVT = OpInfo.ConstraintVT;
5452 // If this is a constraint for a specific physical register, like {r17},
5454 if (unsigned AssignedReg = PhysReg.first) {
5455 const TargetRegisterClass *RC = PhysReg.second;
5456 if (OpInfo.ConstraintVT == MVT::Other)
5457 ValueVT = *RC->vt_begin();
5459 // Get the actual register value type. This is important, because the user
5460 // may have asked for (e.g.) the AX register in i32 type. We need to
5461 // remember that AX is actually i16 to get the right extension.
5462 RegVT = *RC->vt_begin();
5464 // This is a explicit reference to a physical register.
5465 Regs.push_back(AssignedReg);
5467 // If this is an expanded reference, add the rest of the regs to Regs.
5469 TargetRegisterClass::iterator I = RC->begin();
5470 for (; *I != AssignedReg; ++I)
5471 assert(I != RC->end() && "Didn't find reg!");
5473 // Already added the first reg.
5475 for (; NumRegs; --NumRegs, ++I) {
5476 assert(I != RC->end() && "Ran out of registers to allocate!");
5481 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5482 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5483 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5487 // Otherwise, if this was a reference to an LLVM register class, create vregs
5488 // for this reference.
5489 if (const TargetRegisterClass *RC = PhysReg.second) {
5490 RegVT = *RC->vt_begin();
5491 if (OpInfo.ConstraintVT == MVT::Other)
5494 // Create the appropriate number of virtual registers.
5495 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5496 for (; NumRegs; --NumRegs)
5497 Regs.push_back(RegInfo.createVirtualRegister(RC));
5499 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5503 // This is a reference to a register class that doesn't directly correspond
5504 // to an LLVM register class. Allocate NumRegs consecutive, available,
5505 // registers from the class.
5506 std::vector<unsigned> RegClassRegs
5507 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5508 OpInfo.ConstraintVT);
5510 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5511 unsigned NumAllocated = 0;
5512 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5513 unsigned Reg = RegClassRegs[i];
5514 // See if this register is available.
5515 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5516 (isInReg && InputRegs.count(Reg))) { // Already used.
5517 // Make sure we find consecutive registers.
5522 // Check to see if this register is allocatable (i.e. don't give out the
5524 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5525 if (!RC) { // Couldn't allocate this register.
5526 // Reset NumAllocated to make sure we return consecutive registers.
5531 // Okay, this register is good, we can use it.
5534 // If we allocated enough consecutive registers, succeed.
5535 if (NumAllocated == NumRegs) {
5536 unsigned RegStart = (i-NumAllocated)+1;
5537 unsigned RegEnd = i+1;
5538 // Mark all of the allocated registers used.
5539 for (unsigned i = RegStart; i != RegEnd; ++i)
5540 Regs.push_back(RegClassRegs[i]);
5542 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5543 OpInfo.ConstraintVT);
5544 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5549 // Otherwise, we couldn't allocate enough registers for this.
5552 /// visitInlineAsm - Handle a call to an InlineAsm object.
5554 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5555 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5557 /// ConstraintOperands - Information about all of the constraints.
5558 SDISelAsmOperandInfoVector ConstraintOperands;
5560 std::set<unsigned> OutputRegs, InputRegs;
5562 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS);
5563 bool hasMemory = false;
5565 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5566 unsigned ResNo = 0; // ResNo - The result number of the next output.
5567 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5568 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5569 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5571 EVT OpVT = MVT::Other;
5573 // Compute the value type for each operand.
5574 switch (OpInfo.Type) {
5575 case InlineAsm::isOutput:
5576 // Indirect outputs just consume an argument.
5577 if (OpInfo.isIndirect) {
5578 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5582 // The return value of the call is this value. As such, there is no
5583 // corresponding argument.
5584 assert(!CS.getType()->isVoidTy() &&
5586 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5587 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5589 assert(ResNo == 0 && "Asm only has one result!");
5590 OpVT = TLI.getValueType(CS.getType());
5594 case InlineAsm::isInput:
5595 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5597 case InlineAsm::isClobber:
5602 // If this is an input or an indirect output, process the call argument.
5603 // BasicBlocks are labels, currently appearing only in asm's.
5604 if (OpInfo.CallOperandVal) {
5605 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5606 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5608 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5611 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5614 OpInfo.ConstraintVT = OpVT;
5616 // Indirect operand accesses access memory.
5617 if (OpInfo.isIndirect)
5620 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5621 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]);
5622 if (CType == TargetLowering::C_Memory) {
5630 SDValue Chain, Flag;
5632 // We won't need to flush pending loads if this asm doesn't touch
5633 // memory and is nonvolatile.
5634 if (hasMemory || IA->hasSideEffects())
5637 Chain = DAG.getRoot();
5639 // Second pass over the constraints: compute which constraint option to use
5640 // and assign registers to constraints that want a specific physreg.
5641 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5642 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5644 // If this is an output operand with a matching input operand, look up the
5645 // matching input. If their types mismatch, e.g. one is an integer, the
5646 // other is floating point, or their sizes are different, flag it as an
5648 if (OpInfo.hasMatchingInput()) {
5649 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5651 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5652 if ((OpInfo.ConstraintVT.isInteger() !=
5653 Input.ConstraintVT.isInteger()) ||
5654 (OpInfo.ConstraintVT.getSizeInBits() !=
5655 Input.ConstraintVT.getSizeInBits())) {
5656 report_fatal_error("Unsupported asm: input constraint"
5657 " with a matching output constraint of"
5658 " incompatible type!");
5660 Input.ConstraintVT = OpInfo.ConstraintVT;
5664 // Compute the constraint code and ConstraintType to use.
5665 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5667 // If this is a memory input, and if the operand is not indirect, do what we
5668 // need to to provide an address for the memory input.
5669 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5670 !OpInfo.isIndirect) {
5671 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) &&
5672 "Can only indirectify direct input operands!");
5674 // Memory operands really want the address of the value. If we don't have
5675 // an indirect input, put it in the constpool if we can, otherwise spill
5676 // it to a stack slot.
5678 // If the operand is a float, integer, or vector constant, spill to a
5679 // constant pool entry to get its address.
5680 const Value *OpVal = OpInfo.CallOperandVal;
5681 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5682 isa<ConstantVector>(OpVal)) {
5683 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5684 TLI.getPointerTy());
5686 // Otherwise, create a stack slot and emit a store to it before the
5688 const Type *Ty = OpVal->getType();
5689 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5690 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5691 MachineFunction &MF = DAG.getMachineFunction();
5692 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5693 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5694 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5695 OpInfo.CallOperand, StackSlot,
5696 MachinePointerInfo::getFixedStack(SSFI),
5698 OpInfo.CallOperand = StackSlot;
5701 // There is no longer a Value* corresponding to this operand.
5702 OpInfo.CallOperandVal = 0;
5704 // It is now an indirect operand.
5705 OpInfo.isIndirect = true;
5708 // If this constraint is for a specific register, allocate it before
5710 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5711 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5714 // Second pass - Loop over all of the operands, assigning virtual or physregs
5715 // to register class operands.
5716 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5717 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5719 // C_Register operands have already been allocated, Other/Memory don't need
5721 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5722 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5725 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5726 std::vector<SDValue> AsmNodeOperands;
5727 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5728 AsmNodeOperands.push_back(
5729 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5730 TLI.getPointerTy()));
5732 // If we have a !srcloc metadata node associated with it, we want to attach
5733 // this to the ultimately generated inline asm machineinstr. To do this, we
5734 // pass in the third operand as this (potentially null) inline asm MDNode.
5735 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5736 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5738 // Remember the HasSideEffect and AlignStack bits as operand 3.
5739 unsigned ExtraInfo = 0;
5740 if (IA->hasSideEffects())
5741 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5742 if (IA->isAlignStack())
5743 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5744 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
5745 TLI.getPointerTy()));
5747 // Loop over all of the inputs, copying the operand values into the
5748 // appropriate registers and processing the output regs.
5749 RegsForValue RetValRegs;
5751 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5752 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5754 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5755 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5757 switch (OpInfo.Type) {
5758 case InlineAsm::isOutput: {
5759 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5760 OpInfo.ConstraintType != TargetLowering::C_Register) {
5761 // Memory output, or 'other' output (e.g. 'X' constraint).
5762 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5764 // Add information to the INLINEASM node to know about this output.
5765 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5766 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5767 TLI.getPointerTy()));
5768 AsmNodeOperands.push_back(OpInfo.CallOperand);
5772 // Otherwise, this is a register or register class output.
5774 // Copy the output from the appropriate register. Find a register that
5776 if (OpInfo.AssignedRegs.Regs.empty())
5777 report_fatal_error("Couldn't allocate output reg for constraint '" +
5778 Twine(OpInfo.ConstraintCode) + "'!");
5780 // If this is an indirect operand, store through the pointer after the
5782 if (OpInfo.isIndirect) {
5783 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5784 OpInfo.CallOperandVal));
5786 // This is the result value of the call.
5787 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5788 // Concatenate this output onto the outputs list.
5789 RetValRegs.append(OpInfo.AssignedRegs);
5792 // Add information to the INLINEASM node to know that this register is
5794 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5795 InlineAsm::Kind_RegDefEarlyClobber :
5796 InlineAsm::Kind_RegDef,
5803 case InlineAsm::isInput: {
5804 SDValue InOperandVal = OpInfo.CallOperand;
5806 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5807 // If this is required to match an output register we have already set,
5808 // just use its register.
5809 unsigned OperandNo = OpInfo.getMatchedOperand();
5811 // Scan until we find the definition we already emitted of this operand.
5812 // When we find it, create a RegsForValue operand.
5813 unsigned CurOp = InlineAsm::Op_FirstOperand;
5814 for (; OperandNo; --OperandNo) {
5815 // Advance to the next operand.
5817 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5818 assert((InlineAsm::isRegDefKind(OpFlag) ||
5819 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5820 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5821 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5825 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5826 if (InlineAsm::isRegDefKind(OpFlag) ||
5827 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5828 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5829 if (OpInfo.isIndirect) {
5830 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5831 LLVMContext &Ctx = *DAG.getContext();
5832 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5833 " don't know how to handle tied "
5834 "indirect register inputs");
5837 RegsForValue MatchedRegs;
5838 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5839 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5840 MatchedRegs.RegVTs.push_back(RegVT);
5841 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5842 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5844 MatchedRegs.Regs.push_back
5845 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5847 // Use the produced MatchedRegs object to
5848 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5850 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5851 true, OpInfo.getMatchedOperand(),
5852 DAG, AsmNodeOperands);
5856 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5857 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5858 "Unexpected number of operands");
5859 // Add information to the INLINEASM node to know about this input.
5860 // See InlineAsm.h isUseOperandTiedToDef.
5861 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5862 OpInfo.getMatchedOperand());
5863 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5864 TLI.getPointerTy()));
5865 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5869 // Treat indirect 'X' constraint as memory.
5870 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5872 OpInfo.ConstraintType = TargetLowering::C_Memory;
5874 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5875 std::vector<SDValue> Ops;
5876 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5879 report_fatal_error("Invalid operand for inline asm constraint '" +
5880 Twine(OpInfo.ConstraintCode) + "'!");
5882 // Add information to the INLINEASM node to know about this input.
5883 unsigned ResOpType =
5884 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5885 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5886 TLI.getPointerTy()));
5887 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5891 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5892 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5893 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5894 "Memory operands expect pointer values");
5896 // Add information to the INLINEASM node to know about this input.
5897 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5898 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5899 TLI.getPointerTy()));
5900 AsmNodeOperands.push_back(InOperandVal);
5904 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5905 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5906 "Unknown constraint type!");
5907 assert(!OpInfo.isIndirect &&
5908 "Don't know how to handle indirect register inputs yet!");
5910 // Copy the input into the appropriate registers.
5911 if (OpInfo.AssignedRegs.Regs.empty() ||
5912 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5913 report_fatal_error("Couldn't allocate input reg for constraint '" +
5914 Twine(OpInfo.ConstraintCode) + "'!");
5916 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5919 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5920 DAG, AsmNodeOperands);
5923 case InlineAsm::isClobber: {
5924 // Add the clobbered value to the operand list, so that the register
5925 // allocator is aware that the physreg got clobbered.
5926 if (!OpInfo.AssignedRegs.Regs.empty())
5927 OpInfo.AssignedRegs.AddInlineAsmOperands(
5928 InlineAsm::Kind_RegDefEarlyClobber,
5936 // Finish up input operands. Set the input chain and add the flag last.
5937 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
5938 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5940 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5941 DAG.getVTList(MVT::Other, MVT::Glue),
5942 &AsmNodeOperands[0], AsmNodeOperands.size());
5943 Flag = Chain.getValue(1);
5945 // If this asm returns a register value, copy the result from that register
5946 // and set it as the value of the call.
5947 if (!RetValRegs.Regs.empty()) {
5948 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5951 // FIXME: Why don't we do this for inline asms with MRVs?
5952 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5953 EVT ResultType = TLI.getValueType(CS.getType());
5955 // If any of the results of the inline asm is a vector, it may have the
5956 // wrong width/num elts. This can happen for register classes that can
5957 // contain multiple different value types. The preg or vreg allocated may
5958 // not have the same VT as was expected. Convert it to the right type
5959 // with bit_convert.
5960 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5961 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5964 } else if (ResultType != Val.getValueType() &&
5965 ResultType.isInteger() && Val.getValueType().isInteger()) {
5966 // If a result value was tied to an input value, the computed result may
5967 // have a wider width than the expected result. Extract the relevant
5969 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5972 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5975 setValue(CS.getInstruction(), Val);
5976 // Don't need to use this as a chain in this case.
5977 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5981 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5983 // Process indirect outputs, first output all of the flagged copies out of
5985 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5986 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5987 const Value *Ptr = IndirectStoresToEmit[i].second;
5988 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5990 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5993 // Emit the non-flagged stores from the physregs.
5994 SmallVector<SDValue, 8> OutChains;
5995 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5996 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5997 StoresToEmit[i].first,
5998 getValue(StoresToEmit[i].second),
5999 MachinePointerInfo(StoresToEmit[i].second),
6001 OutChains.push_back(Val);
6004 if (!OutChains.empty())
6005 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6006 &OutChains[0], OutChains.size());
6011 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6012 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6013 MVT::Other, getRoot(),
6014 getValue(I.getArgOperand(0)),
6015 DAG.getSrcValue(I.getArgOperand(0))));
6018 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6019 const TargetData &TD = *TLI.getTargetData();
6020 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6021 getRoot(), getValue(I.getOperand(0)),
6022 DAG.getSrcValue(I.getOperand(0)),
6023 TD.getABITypeAlignment(I.getType()));
6025 DAG.setRoot(V.getValue(1));
6028 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6029 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6030 MVT::Other, getRoot(),
6031 getValue(I.getArgOperand(0)),
6032 DAG.getSrcValue(I.getArgOperand(0))));
6035 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6036 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6037 MVT::Other, getRoot(),
6038 getValue(I.getArgOperand(0)),
6039 getValue(I.getArgOperand(1)),
6040 DAG.getSrcValue(I.getArgOperand(0)),
6041 DAG.getSrcValue(I.getArgOperand(1))));
6044 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6045 /// implementation, which just calls LowerCall.
6046 /// FIXME: When all targets are
6047 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6048 std::pair<SDValue, SDValue>
6049 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
6050 bool RetSExt, bool RetZExt, bool isVarArg,
6051 bool isInreg, unsigned NumFixedArgs,
6052 CallingConv::ID CallConv, bool isTailCall,
6053 bool isReturnValueUsed,
6055 ArgListTy &Args, SelectionDAG &DAG,
6056 DebugLoc dl) const {
6057 // Handle all of the outgoing arguments.
6058 SmallVector<ISD::OutputArg, 32> Outs;
6059 SmallVector<SDValue, 32> OutVals;
6060 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6061 SmallVector<EVT, 4> ValueVTs;
6062 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6063 for (unsigned Value = 0, NumValues = ValueVTs.size();
6064 Value != NumValues; ++Value) {
6065 EVT VT = ValueVTs[Value];
6066 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6067 SDValue Op = SDValue(Args[i].Node.getNode(),
6068 Args[i].Node.getResNo() + Value);
6069 ISD::ArgFlagsTy Flags;
6070 unsigned OriginalAlignment =
6071 getTargetData()->getABITypeAlignment(ArgTy);
6077 if (Args[i].isInReg)
6081 if (Args[i].isByVal) {
6083 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
6084 const Type *ElementTy = Ty->getElementType();
6085 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
6086 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
6087 // For ByVal, alignment should come from FE. BE will guess if this
6088 // info is not there but there are cases it cannot get right.
6089 if (Args[i].Alignment)
6090 FrameAlign = Args[i].Alignment;
6091 Flags.setByValAlign(FrameAlign);
6092 Flags.setByValSize(FrameSize);
6096 Flags.setOrigAlign(OriginalAlignment);
6098 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6099 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6100 SmallVector<SDValue, 4> Parts(NumParts);
6101 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6104 ExtendKind = ISD::SIGN_EXTEND;
6105 else if (Args[i].isZExt)
6106 ExtendKind = ISD::ZERO_EXTEND;
6108 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6109 PartVT, ExtendKind);
6111 for (unsigned j = 0; j != NumParts; ++j) {
6112 // if it isn't first piece, alignment must be 1
6113 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6115 if (NumParts > 1 && j == 0)
6116 MyFlags.Flags.setSplit();
6118 MyFlags.Flags.setOrigAlign(1);
6120 Outs.push_back(MyFlags);
6121 OutVals.push_back(Parts[j]);
6126 // Handle the incoming return values from the call.
6127 SmallVector<ISD::InputArg, 32> Ins;
6128 SmallVector<EVT, 4> RetTys;
6129 ComputeValueVTs(*this, RetTy, RetTys);
6130 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6132 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6133 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6134 for (unsigned i = 0; i != NumRegs; ++i) {
6135 ISD::InputArg MyFlags;
6136 MyFlags.VT = RegisterVT.getSimpleVT();
6137 MyFlags.Used = isReturnValueUsed;
6139 MyFlags.Flags.setSExt();
6141 MyFlags.Flags.setZExt();
6143 MyFlags.Flags.setInReg();
6144 Ins.push_back(MyFlags);
6148 SmallVector<SDValue, 4> InVals;
6149 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6150 Outs, OutVals, Ins, dl, DAG, InVals);
6152 // Verify that the target's LowerCall behaved as expected.
6153 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6154 "LowerCall didn't return a valid chain!");
6155 assert((!isTailCall || InVals.empty()) &&
6156 "LowerCall emitted a return value for a tail call!");
6157 assert((isTailCall || InVals.size() == Ins.size()) &&
6158 "LowerCall didn't emit the correct number of values!");
6160 // For a tail call, the return value is merely live-out and there aren't
6161 // any nodes in the DAG representing it. Return a special value to
6162 // indicate that a tail call has been emitted and no more Instructions
6163 // should be processed in the current block.
6166 return std::make_pair(SDValue(), SDValue());
6169 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6170 assert(InVals[i].getNode() &&
6171 "LowerCall emitted a null value!");
6172 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6173 "LowerCall emitted a value with the wrong type!");
6176 // Collect the legal value parts into potentially illegal values
6177 // that correspond to the original function's return values.
6178 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6180 AssertOp = ISD::AssertSext;
6182 AssertOp = ISD::AssertZext;
6183 SmallVector<SDValue, 4> ReturnValues;
6184 unsigned CurReg = 0;
6185 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6187 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6188 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6190 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6191 NumRegs, RegisterVT, VT,
6196 // For a function returning void, there is no return value. We can't create
6197 // such a node, so we just return a null return value in that case. In
6198 // that case, nothing will actualy look at the value.
6199 if (ReturnValues.empty())
6200 return std::make_pair(SDValue(), Chain);
6202 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6203 DAG.getVTList(&RetTys[0], RetTys.size()),
6204 &ReturnValues[0], ReturnValues.size());
6205 return std::make_pair(Res, Chain);
6208 void TargetLowering::LowerOperationWrapper(SDNode *N,
6209 SmallVectorImpl<SDValue> &Results,
6210 SelectionDAG &DAG) const {
6211 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6213 Results.push_back(Res);
6216 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6217 llvm_unreachable("LowerOperation not implemented for this target!");
6222 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6223 SDValue Op = getNonRegisterValue(V);
6224 assert((Op.getOpcode() != ISD::CopyFromReg ||
6225 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6226 "Copy from a reg to the same reg!");
6227 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6229 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6230 SDValue Chain = DAG.getEntryNode();
6231 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6232 PendingExports.push_back(Chain);
6235 #include "llvm/CodeGen/SelectionDAGISel.h"
6237 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6238 // If this is the entry block, emit arguments.
6239 const Function &F = *LLVMBB->getParent();
6240 SelectionDAG &DAG = SDB->DAG;
6241 DebugLoc dl = SDB->getCurDebugLoc();
6242 const TargetData *TD = TLI.getTargetData();
6243 SmallVector<ISD::InputArg, 16> Ins;
6245 // Check whether the function can return without sret-demotion.
6246 SmallVector<ISD::OutputArg, 4> Outs;
6247 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6250 if (!FuncInfo->CanLowerReturn) {
6251 // Put in an sret pointer parameter before all the other parameters.
6252 SmallVector<EVT, 1> ValueVTs;
6253 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6255 // NOTE: Assuming that a pointer will never break down to more than one VT
6257 ISD::ArgFlagsTy Flags;
6259 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6260 ISD::InputArg RetArg(Flags, RegisterVT, true);
6261 Ins.push_back(RetArg);
6264 // Set up the incoming argument description vector.
6266 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6267 I != E; ++I, ++Idx) {
6268 SmallVector<EVT, 4> ValueVTs;
6269 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6270 bool isArgValueUsed = !I->use_empty();
6271 for (unsigned Value = 0, NumValues = ValueVTs.size();
6272 Value != NumValues; ++Value) {
6273 EVT VT = ValueVTs[Value];
6274 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6275 ISD::ArgFlagsTy Flags;
6276 unsigned OriginalAlignment =
6277 TD->getABITypeAlignment(ArgTy);
6279 if (F.paramHasAttr(Idx, Attribute::ZExt))
6281 if (F.paramHasAttr(Idx, Attribute::SExt))
6283 if (F.paramHasAttr(Idx, Attribute::InReg))
6285 if (F.paramHasAttr(Idx, Attribute::StructRet))
6287 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6289 const PointerType *Ty = cast<PointerType>(I->getType());
6290 const Type *ElementTy = Ty->getElementType();
6291 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6292 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6293 // For ByVal, alignment should be passed from FE. BE will guess if
6294 // this info is not there but there are cases it cannot get right.
6295 if (F.getParamAlignment(Idx))
6296 FrameAlign = F.getParamAlignment(Idx);
6297 Flags.setByValAlign(FrameAlign);
6298 Flags.setByValSize(FrameSize);
6300 if (F.paramHasAttr(Idx, Attribute::Nest))
6302 Flags.setOrigAlign(OriginalAlignment);
6304 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6305 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6306 for (unsigned i = 0; i != NumRegs; ++i) {
6307 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6308 if (NumRegs > 1 && i == 0)
6309 MyFlags.Flags.setSplit();
6310 // if it isn't first piece, alignment must be 1
6312 MyFlags.Flags.setOrigAlign(1);
6313 Ins.push_back(MyFlags);
6318 // Call the target to set up the argument values.
6319 SmallVector<SDValue, 8> InVals;
6320 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6324 // Verify that the target's LowerFormalArguments behaved as expected.
6325 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6326 "LowerFormalArguments didn't return a valid chain!");
6327 assert(InVals.size() == Ins.size() &&
6328 "LowerFormalArguments didn't emit the correct number of values!");
6330 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6331 assert(InVals[i].getNode() &&
6332 "LowerFormalArguments emitted a null value!");
6333 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6334 "LowerFormalArguments emitted a value with the wrong type!");
6338 // Update the DAG with the new chain value resulting from argument lowering.
6339 DAG.setRoot(NewRoot);
6341 // Set up the argument values.
6344 if (!FuncInfo->CanLowerReturn) {
6345 // Create a virtual register for the sret pointer, and put in a copy
6346 // from the sret argument into it.
6347 SmallVector<EVT, 1> ValueVTs;
6348 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6349 EVT VT = ValueVTs[0];
6350 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6351 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6352 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6353 RegVT, VT, AssertOp);
6355 MachineFunction& MF = SDB->DAG.getMachineFunction();
6356 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6357 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6358 FuncInfo->DemoteRegister = SRetReg;
6359 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6361 DAG.setRoot(NewRoot);
6363 // i indexes lowered arguments. Bump it past the hidden sret argument.
6364 // Idx indexes LLVM arguments. Don't touch it.
6368 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6370 SmallVector<SDValue, 4> ArgValues;
6371 SmallVector<EVT, 4> ValueVTs;
6372 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6373 unsigned NumValues = ValueVTs.size();
6375 // If this argument is unused then remember its value. It is used to generate
6376 // debugging information.
6377 if (I->use_empty() && NumValues)
6378 SDB->setUnusedArgValue(I, InVals[i]);
6380 for (unsigned Value = 0; Value != NumValues; ++Value) {
6381 EVT VT = ValueVTs[Value];
6382 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6383 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6385 if (!I->use_empty()) {
6386 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6387 if (F.paramHasAttr(Idx, Attribute::SExt))
6388 AssertOp = ISD::AssertSext;
6389 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6390 AssertOp = ISD::AssertZext;
6392 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6393 NumParts, PartVT, VT,
6400 // Note down frame index for byval arguments.
6401 if (I->hasByValAttr() && !ArgValues.empty())
6402 if (FrameIndexSDNode *FI =
6403 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6404 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6406 if (!I->use_empty()) {
6408 if (!ArgValues.empty())
6409 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6410 SDB->getCurDebugLoc());
6411 SDB->setValue(I, Res);
6413 // If this argument is live outside of the entry block, insert a copy from
6414 // whereever we got it to the vreg that other BB's will reference it as.
6415 SDB->CopyToExportRegsIfNeeded(I);
6419 assert(i == InVals.size() && "Argument register count mismatch!");
6421 // Finally, if the target has anything special to do, allow it to do so.
6422 // FIXME: this should insert code into the DAG!
6423 EmitFunctionEntryCode();
6426 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6427 /// ensure constants are generated when needed. Remember the virtual registers
6428 /// that need to be added to the Machine PHI nodes as input. We cannot just
6429 /// directly add them, because expansion might result in multiple MBB's for one
6430 /// BB. As such, the start of the BB might correspond to a different MBB than
6434 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6435 const TerminatorInst *TI = LLVMBB->getTerminator();
6437 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6439 // Check successor nodes' PHI nodes that expect a constant to be available
6441 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6442 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6443 if (!isa<PHINode>(SuccBB->begin())) continue;
6444 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6446 // If this terminator has multiple identical successors (common for
6447 // switches), only handle each succ once.
6448 if (!SuccsHandled.insert(SuccMBB)) continue;
6450 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6452 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6453 // nodes and Machine PHI nodes, but the incoming operands have not been
6455 for (BasicBlock::const_iterator I = SuccBB->begin();
6456 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6457 // Ignore dead phi's.
6458 if (PN->use_empty()) continue;
6461 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6463 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6464 unsigned &RegOut = ConstantsOut[C];
6466 RegOut = FuncInfo.CreateRegs(C->getType());
6467 CopyValueToVirtualRegister(C, RegOut);
6471 DenseMap<const Value *, unsigned>::iterator I =
6472 FuncInfo.ValueMap.find(PHIOp);
6473 if (I != FuncInfo.ValueMap.end())
6476 assert(isa<AllocaInst>(PHIOp) &&
6477 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6478 "Didn't codegen value into a register!??");
6479 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6480 CopyValueToVirtualRegister(PHIOp, Reg);
6484 // Remember that this register needs to added to the machine PHI node as
6485 // the input for this MBB.
6486 SmallVector<EVT, 4> ValueVTs;
6487 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6488 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6489 EVT VT = ValueVTs[vti];
6490 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6491 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6492 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6493 Reg += NumRegisters;
6497 ConstantsOut.clear();