1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/InlineAsm.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/IntrinsicInst.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/IR/LLVMContext.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/IntegersSubsetMapping.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
63 /// LimitFloatPrecision - Generate low-precision inline sequences for
64 /// some float libcalls (6, 8 or 12 bits).
65 static unsigned LimitFloatPrecision;
67 static cl::opt<unsigned, true>
68 LimitFPPrecision("limit-float-precision",
69 cl::desc("Generate low-precision inline sequences "
70 "for some float libcalls"),
71 cl::location(LimitFloatPrecision),
74 // Limit the width of DAG chains. This is important in general to prevent
75 // prevent DAG-based analysis from blowing up. For example, alias analysis and
76 // load clustering may not complete in reasonable time. It is difficult to
77 // recognize and avoid this situation within each individual analysis, and
78 // future analyses are likely to have the same behavior. Limiting DAG width is
79 // the safe approach, and will be especially important with global DAGs.
81 // MaxParallelChains default is arbitrarily high to avoid affecting
82 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
83 // sequence over this should have been converted to llvm.memcpy by the
84 // frontend. It easy to induce this behavior with .ll code such as:
85 // %buffer = alloca [4096 x i8]
86 // %data = load [4096 x i8]* %argPtr
87 // store [4096 x i8] %data, [4096 x i8]* %buffer
88 static const unsigned MaxParallelChains = 64;
90 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
91 const SDValue *Parts, unsigned NumParts,
92 MVT PartVT, EVT ValueVT, const Value *V);
94 /// getCopyFromParts - Create a value that contains the specified legal parts
95 /// combined into the value they represent. If the parts combine to a type
96 /// larger then ValueVT then AssertOp can be used to specify whether the extra
97 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
98 /// (ISD::AssertSext).
99 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
100 const SDValue *Parts,
101 unsigned NumParts, MVT PartVT, EVT ValueVT,
103 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
104 if (ValueVT.isVector())
105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
108 assert(NumParts > 0 && "No parts to assemble!");
109 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
110 SDValue Val = Parts[0];
113 // Assemble the value from multiple parts.
114 if (ValueVT.isInteger()) {
115 unsigned PartBits = PartVT.getSizeInBits();
116 unsigned ValueBits = ValueVT.getSizeInBits();
118 // Assemble the power of 2 part.
119 unsigned RoundParts = NumParts & (NumParts - 1) ?
120 1 << Log2_32(NumParts) : NumParts;
121 unsigned RoundBits = PartBits * RoundParts;
122 EVT RoundVT = RoundBits == ValueBits ?
123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
128 if (RoundParts > 2) {
129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
131 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
132 RoundParts / 2, PartVT, HalfVT, V);
134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
138 if (TLI.isBigEndian())
141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
143 if (RoundParts < NumParts) {
144 // Assemble the trailing non-power-of-2 part.
145 unsigned OddParts = NumParts - RoundParts;
146 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
147 Hi = getCopyFromParts(DAG, DL,
148 Parts + RoundParts, OddParts, PartVT, OddVT, V);
150 // Combine the round and odd parts.
152 if (TLI.isBigEndian())
154 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
157 DAG.getConstant(Lo.getValueType().getSizeInBits(),
158 TLI.getPointerTy()));
159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
160 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
162 } else if (PartVT.isFloatingPoint()) {
163 // FP split into multiple FP parts (for ppcf128)
164 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
167 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
168 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
169 if (TLI.isBigEndian())
171 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
173 // FP split into integer parts (soft fp)
174 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
175 !PartVT.isVector() && "Unexpected split");
176 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
177 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
181 // There is now one part, held in Val. Correct it to match ValueVT.
182 EVT PartEVT = Val.getValueType();
184 if (PartEVT == ValueVT)
187 if (PartEVT.isInteger() && ValueVT.isInteger()) {
188 if (ValueVT.bitsLT(PartEVT)) {
189 // For a truncate, see if we have any information to
190 // indicate whether the truncated bits will always be
191 // zero or sign-extension.
192 if (AssertOp != ISD::DELETED_NODE)
193 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
194 DAG.getValueType(ValueVT));
195 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
197 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
200 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
201 // FP_ROUND's are always exact here.
202 if (ValueVT.bitsLT(Val.getValueType()))
203 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
204 DAG.getTargetConstant(1, TLI.getPointerTy()));
206 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
209 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
210 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
212 llvm_unreachable("Unknown mismatch!");
215 /// getCopyFromPartsVector - Create a value that contains the specified legal
216 /// parts combined into the value they represent. If the parts combine to a
217 /// type larger then ValueVT then AssertOp can be used to specify whether the
218 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
219 /// ValueVT (ISD::AssertSext).
220 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
221 const SDValue *Parts, unsigned NumParts,
222 MVT PartVT, EVT ValueVT, const Value *V) {
223 assert(ValueVT.isVector() && "Not a vector value");
224 assert(NumParts > 0 && "No parts to assemble!");
225 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
226 SDValue Val = Parts[0];
228 // Handle a multi-element vector.
232 unsigned NumIntermediates;
234 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
235 NumIntermediates, RegisterVT);
236 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
237 NumParts = NumRegs; // Silence a compiler warning.
238 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
239 assert(RegisterVT == Parts[0].getSimpleValueType() &&
240 "Part type doesn't match part!");
242 // Assemble the parts into intermediate operands.
243 SmallVector<SDValue, 8> Ops(NumIntermediates);
244 if (NumIntermediates == NumParts) {
245 // If the register was not expanded, truncate or copy the value,
247 for (unsigned i = 0; i != NumParts; ++i)
248 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
249 PartVT, IntermediateVT, V);
250 } else if (NumParts > 0) {
251 // If the intermediate type was expanded, build the intermediate
252 // operands from the parts.
253 assert(NumParts % NumIntermediates == 0 &&
254 "Must expand into a divisible number of parts!");
255 unsigned Factor = NumParts / NumIntermediates;
256 for (unsigned i = 0; i != NumIntermediates; ++i)
257 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
258 PartVT, IntermediateVT, V);
261 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
262 // intermediate operands.
263 Val = DAG.getNode(IntermediateVT.isVector() ?
264 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
265 ValueVT, &Ops[0], NumIntermediates);
268 // There is now one part, held in Val. Correct it to match ValueVT.
269 EVT PartEVT = Val.getValueType();
271 if (PartEVT == ValueVT)
274 if (PartEVT.isVector()) {
275 // If the element type of the source/dest vectors are the same, but the
276 // parts vector has more elements than the value vector, then we have a
277 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
279 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
280 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
281 "Cannot narrow, it would be a lossy transformation");
282 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
283 DAG.getIntPtrConstant(0));
286 // Vector/Vector bitcast.
287 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
288 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
290 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
291 "Cannot handle this kind of promotion");
292 // Promoted vector extract
293 bool Smaller = ValueVT.bitsLE(PartEVT);
294 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
299 // Trivial bitcast if the types are the same size and the destination
300 // vector type is legal.
301 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
302 TLI.isTypeLegal(ValueVT))
303 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
305 // Handle cases such as i8 -> <1 x i1>
306 if (ValueVT.getVectorNumElements() != 1) {
307 LLVMContext &Ctx = *DAG.getContext();
308 Twine ErrMsg("non-trivial scalar-to-vector conversion");
309 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
310 if (const CallInst *CI = dyn_cast<CallInst>(I))
311 if (isa<InlineAsm>(CI->getCalledValue()))
312 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
313 Ctx.emitError(I, ErrMsg);
315 Ctx.emitError(ErrMsg);
317 return DAG.getUNDEF(ValueVT);
320 if (ValueVT.getVectorNumElements() == 1 &&
321 ValueVT.getVectorElementType() != PartEVT) {
322 bool Smaller = ValueVT.bitsLE(PartEVT);
323 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
324 DL, ValueVT.getScalarType(), Val);
327 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
330 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
331 SDValue Val, SDValue *Parts, unsigned NumParts,
332 MVT PartVT, const Value *V);
334 /// getCopyToParts - Create a series of nodes that contain the specified value
335 /// split into legal parts. If the parts contain more bits than Val, then, for
336 /// integers, ExtendKind can be used to specify how to generate the extra bits.
337 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
338 SDValue Val, SDValue *Parts, unsigned NumParts,
339 MVT PartVT, const Value *V,
340 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
341 EVT ValueVT = Val.getValueType();
343 // Handle the vector case separately.
344 if (ValueVT.isVector())
345 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
348 unsigned PartBits = PartVT.getSizeInBits();
349 unsigned OrigNumParts = NumParts;
350 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
355 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
356 EVT PartEVT = PartVT;
357 if (PartEVT == ValueVT) {
358 assert(NumParts == 1 && "No-op copy with multiple parts!");
363 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
364 // If the parts cover more bits than the value has, promote the value.
365 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
366 assert(NumParts == 1 && "Do not know what to promote to!");
367 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
369 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
370 ValueVT.isInteger() &&
371 "Unknown mismatch!");
372 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
373 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
374 if (PartVT == MVT::x86mmx)
375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
377 } else if (PartBits == ValueVT.getSizeInBits()) {
378 // Different types of the same size.
379 assert(NumParts == 1 && PartEVT != ValueVT);
380 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
381 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
382 // If the parts cover less bits than value has, truncate the value.
383 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
384 ValueVT.isInteger() &&
385 "Unknown mismatch!");
386 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
387 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
388 if (PartVT == MVT::x86mmx)
389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
392 // The value may have changed - recompute ValueVT.
393 ValueVT = Val.getValueType();
394 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
395 "Failed to tile the value with PartVT!");
398 if (PartEVT != ValueVT) {
399 LLVMContext &Ctx = *DAG.getContext();
400 Twine ErrMsg("scalar-to-vector conversion failed");
401 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
402 if (const CallInst *CI = dyn_cast<CallInst>(I))
403 if (isa<InlineAsm>(CI->getCalledValue()))
404 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
405 Ctx.emitError(I, ErrMsg);
407 Ctx.emitError(ErrMsg);
415 // Expand the value into multiple parts.
416 if (NumParts & (NumParts - 1)) {
417 // The number of parts is not a power of 2. Split off and copy the tail.
418 assert(PartVT.isInteger() && ValueVT.isInteger() &&
419 "Do not know what to expand to!");
420 unsigned RoundParts = 1 << Log2_32(NumParts);
421 unsigned RoundBits = RoundParts * PartBits;
422 unsigned OddParts = NumParts - RoundParts;
423 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
424 DAG.getIntPtrConstant(RoundBits));
425 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
427 if (TLI.isBigEndian())
428 // The odd parts were reversed by getCopyToParts - unreverse them.
429 std::reverse(Parts + RoundParts, Parts + NumParts);
431 NumParts = RoundParts;
432 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
433 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
436 // The number of parts is a power of 2. Repeatedly bisect the value using
438 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
439 EVT::getIntegerVT(*DAG.getContext(),
440 ValueVT.getSizeInBits()),
443 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
444 for (unsigned i = 0; i < NumParts; i += StepSize) {
445 unsigned ThisBits = StepSize * PartBits / 2;
446 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
447 SDValue &Part0 = Parts[i];
448 SDValue &Part1 = Parts[i+StepSize/2];
450 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
451 ThisVT, Part0, DAG.getIntPtrConstant(1));
452 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
453 ThisVT, Part0, DAG.getIntPtrConstant(0));
455 if (ThisBits == PartBits && ThisVT != PartVT) {
456 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
457 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
462 if (TLI.isBigEndian())
463 std::reverse(Parts, Parts + OrigNumParts);
467 /// getCopyToPartsVector - Create a series of nodes that contain the specified
468 /// value split into legal parts.
469 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
470 SDValue Val, SDValue *Parts, unsigned NumParts,
471 MVT PartVT, const Value *V) {
472 EVT ValueVT = Val.getValueType();
473 assert(ValueVT.isVector() && "Not a vector");
474 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
477 EVT PartEVT = PartVT;
478 if (PartEVT == ValueVT) {
480 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
481 // Bitconvert vector->vector case.
482 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
483 } else if (PartVT.isVector() &&
484 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
485 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
486 EVT ElementVT = PartVT.getVectorElementType();
487 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
489 SmallVector<SDValue, 16> Ops;
490 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
491 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
492 ElementVT, Val, DAG.getIntPtrConstant(i)));
494 for (unsigned i = ValueVT.getVectorNumElements(),
495 e = PartVT.getVectorNumElements(); i != e; ++i)
496 Ops.push_back(DAG.getUNDEF(ElementVT));
498 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
500 // FIXME: Use CONCAT for 2x -> 4x.
502 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
503 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
504 } else if (PartVT.isVector() &&
505 PartEVT.getVectorElementType().bitsGE(
506 ValueVT.getVectorElementType()) &&
507 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
509 // Promoted vector extract
510 bool Smaller = PartEVT.bitsLE(ValueVT);
511 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
514 // Vector -> scalar conversion.
515 assert(ValueVT.getVectorNumElements() == 1 &&
516 "Only trivial vector-to-scalar conversions should get here!");
517 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
518 PartVT, Val, DAG.getIntPtrConstant(0));
520 bool Smaller = ValueVT.bitsLE(PartVT);
521 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
529 // Handle a multi-element vector.
532 unsigned NumIntermediates;
533 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
535 NumIntermediates, RegisterVT);
536 unsigned NumElements = ValueVT.getVectorNumElements();
538 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
539 NumParts = NumRegs; // Silence a compiler warning.
540 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
542 // Split the vector into intermediate operands.
543 SmallVector<SDValue, 8> Ops(NumIntermediates);
544 for (unsigned i = 0; i != NumIntermediates; ++i) {
545 if (IntermediateVT.isVector())
546 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
548 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
550 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
551 IntermediateVT, Val, DAG.getIntPtrConstant(i));
554 // Split the intermediate operands into legal parts.
555 if (NumParts == NumIntermediates) {
556 // If the register was not expanded, promote or copy the value,
558 for (unsigned i = 0; i != NumParts; ++i)
559 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
560 } else if (NumParts > 0) {
561 // If the intermediate type was expanded, split each the value into
563 assert(NumParts % NumIntermediates == 0 &&
564 "Must expand into a divisible number of parts!");
565 unsigned Factor = NumParts / NumIntermediates;
566 for (unsigned i = 0; i != NumIntermediates; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
572 /// RegsForValue - This struct represents the registers (physical or virtual)
573 /// that a particular set of values is assigned, and the type information
574 /// about the value. The most common situation is to represent one value at a
575 /// time, but struct or array values are handled element-wise as multiple
576 /// values. The splitting of aggregates is performed recursively, so that we
577 /// never have aggregate-typed registers. The values at this point do not
578 /// necessarily have legal types, so each value may require one or more
579 /// registers of some legal type.
581 struct RegsForValue {
582 /// ValueVTs - The value types of the values, which may not be legal, and
583 /// may need be promoted or synthesized from one or more registers.
585 SmallVector<EVT, 4> ValueVTs;
587 /// RegVTs - The value types of the registers. This is the same size as
588 /// ValueVTs and it records, for each value, what the type of the assigned
589 /// register or registers are. (Individual values are never synthesized
590 /// from more than one type of register.)
592 /// With virtual registers, the contents of RegVTs is redundant with TLI's
593 /// getRegisterType member function, however when with physical registers
594 /// it is necessary to have a separate record of the types.
596 SmallVector<MVT, 4> RegVTs;
598 /// Regs - This list holds the registers assigned to the values.
599 /// Each legal or promoted value requires one register, and each
600 /// expanded value requires multiple registers.
602 SmallVector<unsigned, 4> Regs;
606 RegsForValue(const SmallVector<unsigned, 4> ®s,
607 MVT regvt, EVT valuevt)
608 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
610 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
611 unsigned Reg, Type *Ty) {
612 ComputeValueVTs(tli, Ty, ValueVTs);
614 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
615 EVT ValueVT = ValueVTs[Value];
616 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
617 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
618 for (unsigned i = 0; i != NumRegs; ++i)
619 Regs.push_back(Reg + i);
620 RegVTs.push_back(RegisterVT);
625 /// areValueTypesLegal - Return true if types of all the values are legal.
626 bool areValueTypesLegal(const TargetLowering &TLI) {
627 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
628 MVT RegisterVT = RegVTs[Value];
629 if (!TLI.isTypeLegal(RegisterVT))
635 /// append - Add the specified values to this one.
636 void append(const RegsForValue &RHS) {
637 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
638 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
639 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
642 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
643 /// this value and returns the result as a ValueVTs value. This uses
644 /// Chain/Flag as the input and updates them for the output Chain/Flag.
645 /// If the Flag pointer is NULL, no flag is used.
646 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
648 SDValue &Chain, SDValue *Flag,
649 const Value *V = 0) const;
651 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
652 /// specified value into the registers specified by this object. This uses
653 /// Chain/Flag as the input and updates them for the output Chain/Flag.
654 /// If the Flag pointer is NULL, no flag is used.
655 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
656 SDValue &Chain, SDValue *Flag, const Value *V) const;
658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
659 /// operand list. This adds the code marker, matching input operand index
660 /// (if applicable), and includes the number of values added into it.
661 void AddInlineAsmOperands(unsigned Kind,
662 bool HasMatching, unsigned MatchingIdx,
664 std::vector<SDValue> &Ops) const;
668 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
669 /// this value and returns the result as a ValueVT value. This uses
670 /// Chain/Flag as the input and updates them for the output Chain/Flag.
671 /// If the Flag pointer is NULL, no flag is used.
672 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
673 FunctionLoweringInfo &FuncInfo,
675 SDValue &Chain, SDValue *Flag,
676 const Value *V) const {
677 // A Value with type {} or [0 x %t] needs no registers.
678 if (ValueVTs.empty())
681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
683 // Assemble the legal parts into the final values.
684 SmallVector<SDValue, 4> Values(ValueVTs.size());
685 SmallVector<SDValue, 8> Parts;
686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
687 // Copy the legal parts from the registers.
688 EVT ValueVT = ValueVTs[Value];
689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
690 MVT RegisterVT = RegVTs[Value];
692 Parts.resize(NumRegs);
693 for (unsigned i = 0; i != NumRegs; ++i) {
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
699 *Flag = P.getValue(2);
702 Chain = P.getValue(1);
705 // If the source register was virtual and if we know something about it,
706 // add an assert node.
707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
708 !RegisterVT.isInteger() || RegisterVT.isVector())
711 const FunctionLoweringInfo::LiveOutInfo *LOI =
712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
716 unsigned RegSize = RegisterVT.getSizeInBits();
717 unsigned NumSignBits = LOI->NumSignBits;
718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
720 // FIXME: We capture more information than the dag can represent. For
721 // now, just use the tightest assertzext/assertsext possible.
723 EVT FromVT(MVT::Other);
724 if (NumSignBits == RegSize)
725 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
726 else if (NumZeroBits >= RegSize-1)
727 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
728 else if (NumSignBits > RegSize-8)
729 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
730 else if (NumZeroBits >= RegSize-8)
731 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
732 else if (NumSignBits > RegSize-16)
733 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
734 else if (NumZeroBits >= RegSize-16)
735 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
736 else if (NumSignBits > RegSize-32)
737 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
738 else if (NumZeroBits >= RegSize-32)
739 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
743 // Add an assertion node.
744 assert(FromVT != MVT::Other);
745 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
746 RegisterVT, P, DAG.getValueType(FromVT));
749 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
750 NumRegs, RegisterVT, ValueVT, V);
755 return DAG.getNode(ISD::MERGE_VALUES, dl,
756 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
757 &Values[0], ValueVTs.size());
760 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
761 /// specified value into the registers specified by this object. This uses
762 /// Chain/Flag as the input and updates them for the output Chain/Flag.
763 /// If the Flag pointer is NULL, no flag is used.
764 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
765 SDValue &Chain, SDValue *Flag,
766 const Value *V) const {
767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
769 // Get the list of the values's legal parts.
770 unsigned NumRegs = Regs.size();
771 SmallVector<SDValue, 8> Parts(NumRegs);
772 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
773 EVT ValueVT = ValueVTs[Value];
774 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
775 MVT RegisterVT = RegVTs[Value];
776 ISD::NodeType ExtendKind =
777 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
779 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
780 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
784 // Copy the parts into the registers.
785 SmallVector<SDValue, 8> Chains(NumRegs);
786 for (unsigned i = 0; i != NumRegs; ++i) {
789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
791 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
792 *Flag = Part.getValue(1);
795 Chains[i] = Part.getValue(0);
798 if (NumRegs == 1 || Flag)
799 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
800 // flagged to it. That is the CopyToReg nodes and the user are considered
801 // a single scheduling unit. If we create a TokenFactor and return it as
802 // chain, then the TokenFactor is both a predecessor (operand) of the
803 // user as well as a successor (the TF operands are flagged to the user).
804 // c1, f1 = CopyToReg
805 // c2, f2 = CopyToReg
806 // c3 = TokenFactor c1, c2
809 Chain = Chains[NumRegs-1];
811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
814 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
815 /// operand list. This adds the code marker and includes the number of
816 /// values added into it.
817 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
818 unsigned MatchingIdx,
820 std::vector<SDValue> &Ops) const {
821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
823 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
825 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
826 else if (!Regs.empty() &&
827 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
828 // Put the register class of the virtual registers in the flag word. That
829 // way, later passes can recompute register class constraints for inline
830 // assembly as well as normal instructions.
831 // Don't do this for tied operands that can use the regclass information
833 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
834 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
835 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
838 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
841 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
842 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
843 MVT RegisterVT = RegVTs[Value];
844 for (unsigned i = 0; i != NumRegs; ++i) {
845 assert(Reg < Regs.size() && "Mismatch in # registers expected");
846 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
851 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
852 const TargetLibraryInfo *li) {
856 TD = DAG.getTarget().getDataLayout();
857 Context = DAG.getContext();
858 LPadToCallSiteMap.clear();
861 /// clear - Clear out the current SelectionDAG and the associated
862 /// state and prepare this SelectionDAGBuilder object to be used
863 /// for a new block. This doesn't clear out information about
864 /// additional blocks that are needed to complete switch lowering
865 /// or PHI node updating; that information is cleared out as it is
867 void SelectionDAGBuilder::clear() {
869 UnusedArgNodeMap.clear();
870 PendingLoads.clear();
871 PendingExports.clear();
876 /// clearDanglingDebugInfo - Clear the dangling debug information
877 /// map. This function is separated from the clear so that debug
878 /// information that is dangling in a basic block can be properly
879 /// resolved in a different basic block. This allows the
880 /// SelectionDAG to resolve dangling debug information attached
882 void SelectionDAGBuilder::clearDanglingDebugInfo() {
883 DanglingDebugInfoMap.clear();
886 /// getRoot - Return the current virtual root of the Selection DAG,
887 /// flushing any PendingLoad items. This must be done before emitting
888 /// a store or any other node that may need to be ordered after any
889 /// prior load instructions.
891 SDValue SelectionDAGBuilder::getRoot() {
892 if (PendingLoads.empty())
893 return DAG.getRoot();
895 if (PendingLoads.size() == 1) {
896 SDValue Root = PendingLoads[0];
898 PendingLoads.clear();
902 // Otherwise, we have to make a token factor node.
903 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
904 &PendingLoads[0], PendingLoads.size());
905 PendingLoads.clear();
910 /// getControlRoot - Similar to getRoot, but instead of flushing all the
911 /// PendingLoad items, flush all the PendingExports items. It is necessary
912 /// to do this before emitting a terminator instruction.
914 SDValue SelectionDAGBuilder::getControlRoot() {
915 SDValue Root = DAG.getRoot();
917 if (PendingExports.empty())
920 // Turn all of the CopyToReg chains into one factored node.
921 if (Root.getOpcode() != ISD::EntryToken) {
922 unsigned i = 0, e = PendingExports.size();
923 for (; i != e; ++i) {
924 assert(PendingExports[i].getNode()->getNumOperands() > 1);
925 if (PendingExports[i].getNode()->getOperand(0) == Root)
926 break; // Don't add the root if we already indirectly depend on it.
930 PendingExports.push_back(Root);
933 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
935 PendingExports.size());
936 PendingExports.clear();
941 void SelectionDAGBuilder::visit(const Instruction &I) {
942 // Set up outgoing PHI node register values before emitting the terminator.
943 if (isa<TerminatorInst>(&I))
944 HandlePHINodesInSuccessorBlocks(I.getParent());
950 visit(I.getOpcode(), I);
952 if (!isa<TerminatorInst>(&I) && !HasTailCall)
953 CopyToExportRegsIfNeeded(&I);
958 void SelectionDAGBuilder::visitPHI(const PHINode &) {
959 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
962 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
963 // Note: this doesn't use InstVisitor, because it has to work with
964 // ConstantExpr's in addition to instructions.
966 default: llvm_unreachable("Unknown instruction type encountered!");
967 // Build the switch statement using the Instruction.def file.
968 #define HANDLE_INST(NUM, OPCODE, CLASS) \
969 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
970 #include "llvm/IR/Instruction.def"
974 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
975 // generate the debug data structures now that we've seen its definition.
976 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
978 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
980 const DbgValueInst *DI = DDI.getDI();
981 DebugLoc dl = DDI.getdl();
982 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
983 MDNode *Variable = DI->getVariable();
984 uint64_t Offset = DI->getOffset();
987 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
988 SDV = DAG.getDbgValue(Variable, Val.getNode(),
989 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
990 DAG.AddDbgValue(SDV, Val.getNode(), false);
993 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
994 DanglingDebugInfoMap[V] = DanglingDebugInfo();
998 /// getValue - Return an SDValue for the given Value.
999 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1000 // If we already have an SDValue for this value, use it. It's important
1001 // to do this first, so that we don't create a CopyFromReg if we already
1002 // have a regular SDValue.
1003 SDValue &N = NodeMap[V];
1004 if (N.getNode()) return N;
1006 // If there's a virtual register allocated and initialized for this
1008 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1009 if (It != FuncInfo.ValueMap.end()) {
1010 unsigned InReg = It->second;
1011 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
1012 SDValue Chain = DAG.getEntryNode();
1013 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
1014 resolveDanglingDebugInfo(V, N);
1018 // Otherwise create a new SDValue and remember it.
1019 SDValue Val = getValueImpl(V);
1021 resolveDanglingDebugInfo(V, Val);
1025 /// getNonRegisterValue - Return an SDValue for the given Value, but
1026 /// don't look in FuncInfo.ValueMap for a virtual register.
1027 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1028 // If we already have an SDValue for this value, use it.
1029 SDValue &N = NodeMap[V];
1030 if (N.getNode()) return N;
1032 // Otherwise create a new SDValue and remember it.
1033 SDValue Val = getValueImpl(V);
1035 resolveDanglingDebugInfo(V, Val);
1039 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1040 /// Create an SDValue for the given value.
1041 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1042 if (const Constant *C = dyn_cast<Constant>(V)) {
1043 EVT VT = TLI.getValueType(V->getType(), true);
1045 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1046 return DAG.getConstant(*CI, VT);
1048 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1049 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1051 if (isa<ConstantPointerNull>(C))
1052 return DAG.getConstant(0, TLI.getPointerTy());
1054 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1055 return DAG.getConstantFP(*CFP, VT);
1057 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1058 return DAG.getUNDEF(VT);
1060 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1061 visit(CE->getOpcode(), *CE);
1062 SDValue N1 = NodeMap[V];
1063 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1067 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1068 SmallVector<SDValue, 4> Constants;
1069 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1071 SDNode *Val = getValue(*OI).getNode();
1072 // If the operand is an empty aggregate, there are no values.
1074 // Add each leaf value from the operand to the Constants list
1075 // to form a flattened list of all the values.
1076 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1077 Constants.push_back(SDValue(Val, i));
1080 return DAG.getMergeValues(&Constants[0], Constants.size(),
1084 if (const ConstantDataSequential *CDS =
1085 dyn_cast<ConstantDataSequential>(C)) {
1086 SmallVector<SDValue, 4> Ops;
1087 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1088 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1089 // Add each leaf value from the operand to the Constants list
1090 // to form a flattened list of all the values.
1091 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1092 Ops.push_back(SDValue(Val, i));
1095 if (isa<ArrayType>(CDS->getType()))
1096 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
1097 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1098 VT, &Ops[0], Ops.size());
1101 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1102 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1103 "Unknown struct or array constant!");
1105 SmallVector<EVT, 4> ValueVTs;
1106 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1107 unsigned NumElts = ValueVTs.size();
1109 return SDValue(); // empty struct
1110 SmallVector<SDValue, 4> Constants(NumElts);
1111 for (unsigned i = 0; i != NumElts; ++i) {
1112 EVT EltVT = ValueVTs[i];
1113 if (isa<UndefValue>(C))
1114 Constants[i] = DAG.getUNDEF(EltVT);
1115 else if (EltVT.isFloatingPoint())
1116 Constants[i] = DAG.getConstantFP(0, EltVT);
1118 Constants[i] = DAG.getConstant(0, EltVT);
1121 return DAG.getMergeValues(&Constants[0], NumElts,
1125 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1126 return DAG.getBlockAddress(BA, VT);
1128 VectorType *VecTy = cast<VectorType>(V->getType());
1129 unsigned NumElements = VecTy->getNumElements();
1131 // Now that we know the number and type of the elements, get that number of
1132 // elements into the Ops array based on what kind of constant it is.
1133 SmallVector<SDValue, 16> Ops;
1134 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1135 for (unsigned i = 0; i != NumElements; ++i)
1136 Ops.push_back(getValue(CV->getOperand(i)));
1138 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1139 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1142 if (EltVT.isFloatingPoint())
1143 Op = DAG.getConstantFP(0, EltVT);
1145 Op = DAG.getConstant(0, EltVT);
1146 Ops.assign(NumElements, Op);
1149 // Create a BUILD_VECTOR node.
1150 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1151 VT, &Ops[0], Ops.size());
1154 // If this is a static alloca, generate it as the frameindex instead of
1156 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1157 DenseMap<const AllocaInst*, int>::iterator SI =
1158 FuncInfo.StaticAllocaMap.find(AI);
1159 if (SI != FuncInfo.StaticAllocaMap.end())
1160 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1163 // If this is an instruction which fast-isel has deferred, select it now.
1164 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1165 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1166 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1167 SDValue Chain = DAG.getEntryNode();
1168 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
1171 llvm_unreachable("Can't get register for value!");
1174 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1175 SDValue Chain = getControlRoot();
1176 SmallVector<ISD::OutputArg, 8> Outs;
1177 SmallVector<SDValue, 8> OutVals;
1179 if (!FuncInfo.CanLowerReturn) {
1180 unsigned DemoteReg = FuncInfo.DemoteRegister;
1181 const Function *F = I.getParent()->getParent();
1183 // Emit a store of the return value through the virtual register.
1184 // Leave Outs empty so that LowerReturn won't try to load return
1185 // registers the usual way.
1186 SmallVector<EVT, 1> PtrValueVTs;
1187 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1190 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1191 SDValue RetOp = getValue(I.getOperand(0));
1193 SmallVector<EVT, 4> ValueVTs;
1194 SmallVector<uint64_t, 4> Offsets;
1195 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1196 unsigned NumValues = ValueVTs.size();
1198 SmallVector<SDValue, 4> Chains(NumValues);
1199 for (unsigned i = 0; i != NumValues; ++i) {
1200 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1201 RetPtr.getValueType(), RetPtr,
1202 DAG.getIntPtrConstant(Offsets[i]));
1204 DAG.getStore(Chain, getCurSDLoc(),
1205 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1206 // FIXME: better loc info would be nice.
1207 Add, MachinePointerInfo(), false, false, 0);
1210 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1211 MVT::Other, &Chains[0], NumValues);
1212 } else if (I.getNumOperands() != 0) {
1213 SmallVector<EVT, 4> ValueVTs;
1214 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1215 unsigned NumValues = ValueVTs.size();
1217 SDValue RetOp = getValue(I.getOperand(0));
1218 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1219 EVT VT = ValueVTs[j];
1221 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1223 const Function *F = I.getParent()->getParent();
1224 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1226 ExtendKind = ISD::SIGN_EXTEND;
1227 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1229 ExtendKind = ISD::ZERO_EXTEND;
1231 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1232 VT = TLI.getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1234 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1235 MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1236 SmallVector<SDValue, 4> Parts(NumParts);
1237 getCopyToParts(DAG, getCurSDLoc(),
1238 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1239 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1241 // 'inreg' on function refers to return value
1242 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1243 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1247 // Propagate extension type if any
1248 if (ExtendKind == ISD::SIGN_EXTEND)
1250 else if (ExtendKind == ISD::ZERO_EXTEND)
1253 for (unsigned i = 0; i < NumParts; ++i) {
1254 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1255 /*isfixed=*/true, 0, 0));
1256 OutVals.push_back(Parts[i]);
1262 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1263 CallingConv::ID CallConv =
1264 DAG.getMachineFunction().getFunction()->getCallingConv();
1265 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1266 Outs, OutVals, getCurSDLoc(), DAG);
1268 // Verify that the target's LowerReturn behaved as expected.
1269 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1270 "LowerReturn didn't return a valid chain!");
1272 // Update the DAG with the new chain value resulting from return lowering.
1276 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1277 /// created for it, emit nodes to copy the value into the virtual
1279 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1281 if (V->getType()->isEmptyTy())
1284 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1285 if (VMI != FuncInfo.ValueMap.end()) {
1286 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1287 CopyValueToVirtualRegister(V, VMI->second);
1291 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1292 /// the current basic block, add it to ValueMap now so that we'll get a
1294 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1295 // No need to export constants.
1296 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1298 // Already exported?
1299 if (FuncInfo.isExportedInst(V)) return;
1301 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1302 CopyValueToVirtualRegister(V, Reg);
1305 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1306 const BasicBlock *FromBB) {
1307 // The operands of the setcc have to be in this block. We don't know
1308 // how to export them from some other block.
1309 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1310 // Can export from current BB.
1311 if (VI->getParent() == FromBB)
1314 // Is already exported, noop.
1315 return FuncInfo.isExportedInst(V);
1318 // If this is an argument, we can export it if the BB is the entry block or
1319 // if it is already exported.
1320 if (isa<Argument>(V)) {
1321 if (FromBB == &FromBB->getParent()->getEntryBlock())
1324 // Otherwise, can only export this if it is already exported.
1325 return FuncInfo.isExportedInst(V);
1328 // Otherwise, constants can always be exported.
1332 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1333 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1334 const MachineBasicBlock *Dst) const {
1335 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1338 const BasicBlock *SrcBB = Src->getBasicBlock();
1339 const BasicBlock *DstBB = Dst->getBasicBlock();
1340 return BPI->getEdgeWeight(SrcBB, DstBB);
1343 void SelectionDAGBuilder::
1344 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1345 uint32_t Weight /* = 0 */) {
1347 Weight = getEdgeWeight(Src, Dst);
1348 Src->addSuccessor(Dst, Weight);
1352 static bool InBlock(const Value *V, const BasicBlock *BB) {
1353 if (const Instruction *I = dyn_cast<Instruction>(V))
1354 return I->getParent() == BB;
1358 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1359 /// This function emits a branch and is used at the leaves of an OR or an
1360 /// AND operator tree.
1363 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1364 MachineBasicBlock *TBB,
1365 MachineBasicBlock *FBB,
1366 MachineBasicBlock *CurBB,
1367 MachineBasicBlock *SwitchBB) {
1368 const BasicBlock *BB = CurBB->getBasicBlock();
1370 // If the leaf of the tree is a comparison, merge the condition into
1372 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1373 // The operands of the cmp have to be in this block. We don't know
1374 // how to export them from some other block. If this is the first block
1375 // of the sequence, no exporting is needed.
1376 if (CurBB == SwitchBB ||
1377 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1378 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1379 ISD::CondCode Condition;
1380 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1381 Condition = getICmpCondCode(IC->getPredicate());
1382 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1383 Condition = getFCmpCondCode(FC->getPredicate());
1384 if (TM.Options.NoNaNsFPMath)
1385 Condition = getFCmpCodeWithoutNaN(Condition);
1387 Condition = ISD::SETEQ; // silence warning.
1388 llvm_unreachable("Unknown compare instruction");
1391 CaseBlock CB(Condition, BOp->getOperand(0),
1392 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1393 SwitchCases.push_back(CB);
1398 // Create a CaseBlock record representing this branch.
1399 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1400 NULL, TBB, FBB, CurBB);
1401 SwitchCases.push_back(CB);
1404 /// FindMergedConditions - If Cond is an expression like
1405 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1406 MachineBasicBlock *TBB,
1407 MachineBasicBlock *FBB,
1408 MachineBasicBlock *CurBB,
1409 MachineBasicBlock *SwitchBB,
1411 // If this node is not part of the or/and tree, emit it as a branch.
1412 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1413 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1414 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1415 BOp->getParent() != CurBB->getBasicBlock() ||
1416 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1417 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1418 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1422 // Create TmpBB after CurBB.
1423 MachineFunction::iterator BBI = CurBB;
1424 MachineFunction &MF = DAG.getMachineFunction();
1425 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1426 CurBB->getParent()->insert(++BBI, TmpBB);
1428 if (Opc == Instruction::Or) {
1429 // Codegen X | Y as:
1437 // Emit the LHS condition.
1438 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1440 // Emit the RHS condition into TmpBB.
1441 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1443 assert(Opc == Instruction::And && "Unknown merge op!");
1444 // Codegen X & Y as:
1451 // This requires creation of TmpBB after CurBB.
1453 // Emit the LHS condition.
1454 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1456 // Emit the RHS condition into TmpBB.
1457 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1461 /// If the set of cases should be emitted as a series of branches, return true.
1462 /// If we should emit this as a bunch of and/or'd together conditions, return
1465 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1466 if (Cases.size() != 2) return true;
1468 // If this is two comparisons of the same values or'd or and'd together, they
1469 // will get folded into a single comparison, so don't emit two blocks.
1470 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1471 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1472 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1473 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1477 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1478 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1479 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1480 Cases[0].CC == Cases[1].CC &&
1481 isa<Constant>(Cases[0].CmpRHS) &&
1482 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1483 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1485 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1492 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1493 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1495 // Update machine-CFG edges.
1496 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1498 // Figure out which block is immediately after the current one.
1499 MachineBasicBlock *NextBlock = 0;
1500 MachineFunction::iterator BBI = BrMBB;
1501 if (++BBI != FuncInfo.MF->end())
1504 if (I.isUnconditional()) {
1505 // Update machine-CFG edges.
1506 BrMBB->addSuccessor(Succ0MBB);
1508 // If this is not a fall-through branch, emit the branch.
1509 if (Succ0MBB != NextBlock)
1510 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1511 MVT::Other, getControlRoot(),
1512 DAG.getBasicBlock(Succ0MBB)));
1517 // If this condition is one of the special cases we handle, do special stuff
1519 const Value *CondVal = I.getCondition();
1520 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1522 // If this is a series of conditions that are or'd or and'd together, emit
1523 // this as a sequence of branches instead of setcc's with and/or operations.
1524 // As long as jumps are not expensive, this should improve performance.
1525 // For example, instead of something like:
1538 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1539 if (!TLI.isJumpExpensive() &&
1541 (BOp->getOpcode() == Instruction::And ||
1542 BOp->getOpcode() == Instruction::Or)) {
1543 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1545 // If the compares in later blocks need to use values not currently
1546 // exported from this block, export them now. This block should always
1547 // be the first entry.
1548 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1550 // Allow some cases to be rejected.
1551 if (ShouldEmitAsBranches(SwitchCases)) {
1552 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1553 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1554 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1557 // Emit the branch for this block.
1558 visitSwitchCase(SwitchCases[0], BrMBB);
1559 SwitchCases.erase(SwitchCases.begin());
1563 // Okay, we decided not to do this, remove any inserted MBB's and clear
1565 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1566 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1568 SwitchCases.clear();
1572 // Create a CaseBlock record representing this branch.
1573 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1574 NULL, Succ0MBB, Succ1MBB, BrMBB);
1576 // Use visitSwitchCase to actually insert the fast branch sequence for this
1578 visitSwitchCase(CB, BrMBB);
1581 /// visitSwitchCase - Emits the necessary code to represent a single node in
1582 /// the binary search tree resulting from lowering a switch instruction.
1583 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1584 MachineBasicBlock *SwitchBB) {
1586 SDValue CondLHS = getValue(CB.CmpLHS);
1587 SDLoc dl = getCurSDLoc();
1589 // Build the setcc now.
1590 if (CB.CmpMHS == NULL) {
1591 // Fold "(X == true)" to X and "(X == false)" to !X to
1592 // handle common cases produced by branch lowering.
1593 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1594 CB.CC == ISD::SETEQ)
1596 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1597 CB.CC == ISD::SETEQ) {
1598 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1599 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1601 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1603 assert(CB.CC == ISD::SETCC_INVALID &&
1604 "Condition is undefined for to-the-range belonging check.");
1606 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1607 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1609 SDValue CmpOp = getValue(CB.CmpMHS);
1610 EVT VT = CmpOp.getValueType();
1612 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) {
1613 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1616 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1617 VT, CmpOp, DAG.getConstant(Low, VT));
1618 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1619 DAG.getConstant(High-Low, VT), ISD::SETULE);
1623 // Update successor info
1624 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1625 // TrueBB and FalseBB are always different unless the incoming IR is
1626 // degenerate. This only happens when running llc on weird IR.
1627 if (CB.TrueBB != CB.FalseBB)
1628 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1630 // Set NextBlock to be the MBB immediately after the current one, if any.
1631 // This is used to avoid emitting unnecessary branches to the next block.
1632 MachineBasicBlock *NextBlock = 0;
1633 MachineFunction::iterator BBI = SwitchBB;
1634 if (++BBI != FuncInfo.MF->end())
1637 // If the lhs block is the next block, invert the condition so that we can
1638 // fall through to the lhs instead of the rhs block.
1639 if (CB.TrueBB == NextBlock) {
1640 std::swap(CB.TrueBB, CB.FalseBB);
1641 SDValue True = DAG.getConstant(1, Cond.getValueType());
1642 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1645 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1646 MVT::Other, getControlRoot(), Cond,
1647 DAG.getBasicBlock(CB.TrueBB));
1649 // Insert the false branch. Do this even if it's a fall through branch,
1650 // this makes it easier to do DAG optimizations which require inverting
1651 // the branch condition.
1652 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1653 DAG.getBasicBlock(CB.FalseBB));
1655 DAG.setRoot(BrCond);
1658 /// visitJumpTable - Emit JumpTable node in the current MBB
1659 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1660 // Emit the code for the jump table
1661 assert(JT.Reg != -1U && "Should lower JT Header first!");
1662 EVT PTy = TLI.getPointerTy();
1663 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1665 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1666 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1667 MVT::Other, Index.getValue(1),
1669 DAG.setRoot(BrJumpTable);
1672 /// visitJumpTableHeader - This function emits necessary code to produce index
1673 /// in the JumpTable from switch case.
1674 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1675 JumpTableHeader &JTH,
1676 MachineBasicBlock *SwitchBB) {
1677 // Subtract the lowest switch case value from the value being switched on and
1678 // conditional branch to default mbb if the result is greater than the
1679 // difference between smallest and largest cases.
1680 SDValue SwitchOp = getValue(JTH.SValue);
1681 EVT VT = SwitchOp.getValueType();
1682 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1683 DAG.getConstant(JTH.First, VT));
1685 // The SDNode we just created, which holds the value being switched on minus
1686 // the smallest case value, needs to be copied to a virtual register so it
1687 // can be used as an index into the jump table in a subsequent basic block.
1688 // This value may be smaller or larger than the target's pointer type, and
1689 // therefore require extension or truncating.
1690 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1692 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1693 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1694 JumpTableReg, SwitchOp);
1695 JT.Reg = JumpTableReg;
1697 // Emit the range check for the jump table, and branch to the default block
1698 // for the switch statement if the value being switched on exceeds the largest
1699 // case in the switch.
1700 SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1701 TLI.getSetCCResultType(*DAG.getContext(),
1702 Sub.getValueType()),
1704 DAG.getConstant(JTH.Last - JTH.First,VT),
1707 // Set NextBlock to be the MBB immediately after the current one, if any.
1708 // This is used to avoid emitting unnecessary branches to the next block.
1709 MachineBasicBlock *NextBlock = 0;
1710 MachineFunction::iterator BBI = SwitchBB;
1712 if (++BBI != FuncInfo.MF->end())
1715 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1716 MVT::Other, CopyTo, CMP,
1717 DAG.getBasicBlock(JT.Default));
1719 if (JT.MBB != NextBlock)
1720 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1721 DAG.getBasicBlock(JT.MBB));
1723 DAG.setRoot(BrCond);
1726 /// visitBitTestHeader - This function emits necessary code to produce value
1727 /// suitable for "bit tests"
1728 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1729 MachineBasicBlock *SwitchBB) {
1730 // Subtract the minimum value
1731 SDValue SwitchOp = getValue(B.SValue);
1732 EVT VT = SwitchOp.getValueType();
1733 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1734 DAG.getConstant(B.First, VT));
1737 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1738 TLI.getSetCCResultType(*DAG.getContext(),
1739 Sub.getValueType()),
1740 Sub, DAG.getConstant(B.Range, VT),
1743 // Determine the type of the test operands.
1744 bool UsePtrType = false;
1745 if (!TLI.isTypeLegal(VT))
1748 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1749 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1750 // Switch table case range are encoded into series of masks.
1751 // Just use pointer type, it's guaranteed to fit.
1757 VT = TLI.getPointerTy();
1758 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1761 B.RegVT = VT.getSimpleVT();
1762 B.Reg = FuncInfo.CreateReg(B.RegVT);
1763 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1766 // Set NextBlock to be the MBB immediately after the current one, if any.
1767 // This is used to avoid emitting unnecessary branches to the next block.
1768 MachineBasicBlock *NextBlock = 0;
1769 MachineFunction::iterator BBI = SwitchBB;
1770 if (++BBI != FuncInfo.MF->end())
1773 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1775 addSuccessorWithWeight(SwitchBB, B.Default);
1776 addSuccessorWithWeight(SwitchBB, MBB);
1778 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1779 MVT::Other, CopyTo, RangeCmp,
1780 DAG.getBasicBlock(B.Default));
1782 if (MBB != NextBlock)
1783 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1784 DAG.getBasicBlock(MBB));
1786 DAG.setRoot(BrRange);
1789 /// visitBitTestCase - this function produces one "bit test"
1790 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1791 MachineBasicBlock* NextMBB,
1792 uint32_t BranchWeightToNext,
1795 MachineBasicBlock *SwitchBB) {
1797 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1800 unsigned PopCount = CountPopulation_64(B.Mask);
1801 if (PopCount == 1) {
1802 // Testing for a single bit; just compare the shift count with what it
1803 // would need to be to shift a 1 bit in that position.
1804 Cmp = DAG.getSetCC(getCurSDLoc(),
1805 TLI.getSetCCResultType(*DAG.getContext(), VT),
1807 DAG.getConstant(countTrailingZeros(B.Mask), VT),
1809 } else if (PopCount == BB.Range) {
1810 // There is only one zero bit in the range, test for it directly.
1811 Cmp = DAG.getSetCC(getCurSDLoc(),
1812 TLI.getSetCCResultType(*DAG.getContext(), VT),
1814 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1817 // Make desired shift
1818 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1819 DAG.getConstant(1, VT), ShiftOp);
1821 // Emit bit tests and jumps
1822 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1823 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1824 Cmp = DAG.getSetCC(getCurSDLoc(),
1825 TLI.getSetCCResultType(*DAG.getContext(), VT),
1826 AndOp, DAG.getConstant(0, VT),
1830 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1831 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1832 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1833 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1835 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1836 MVT::Other, getControlRoot(),
1837 Cmp, DAG.getBasicBlock(B.TargetBB));
1839 // Set NextBlock to be the MBB immediately after the current one, if any.
1840 // This is used to avoid emitting unnecessary branches to the next block.
1841 MachineBasicBlock *NextBlock = 0;
1842 MachineFunction::iterator BBI = SwitchBB;
1843 if (++BBI != FuncInfo.MF->end())
1846 if (NextMBB != NextBlock)
1847 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1848 DAG.getBasicBlock(NextMBB));
1853 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1854 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1856 // Retrieve successors.
1857 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1858 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1860 const Value *Callee(I.getCalledValue());
1861 const Function *Fn = dyn_cast<Function>(Callee);
1862 if (isa<InlineAsm>(Callee))
1864 else if (Fn && Fn->isIntrinsic()) {
1865 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
1866 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1868 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1870 // If the value of the invoke is used outside of its defining block, make it
1871 // available as a virtual register.
1872 CopyToExportRegsIfNeeded(&I);
1874 // Update successor info
1875 addSuccessorWithWeight(InvokeMBB, Return);
1876 addSuccessorWithWeight(InvokeMBB, LandingPad);
1878 // Drop into normal successor.
1879 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1880 MVT::Other, getControlRoot(),
1881 DAG.getBasicBlock(Return)));
1884 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1885 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1888 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1889 assert(FuncInfo.MBB->isLandingPad() &&
1890 "Call to landingpad not in landing pad!");
1892 MachineBasicBlock *MBB = FuncInfo.MBB;
1893 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1894 AddLandingPadInfo(LP, MMI, MBB);
1896 // If there aren't registers to copy the values into (e.g., during SjLj
1897 // exceptions), then don't bother to create these DAG nodes.
1898 if (TLI.getExceptionPointerRegister() == 0 &&
1899 TLI.getExceptionSelectorRegister() == 0)
1902 SmallVector<EVT, 2> ValueVTs;
1903 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1905 // Insert the EXCEPTIONADDR instruction.
1906 assert(FuncInfo.MBB->isLandingPad() &&
1907 "Call to eh.exception not in landing pad!");
1908 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1910 Ops[0] = DAG.getRoot();
1911 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurSDLoc(), VTs, Ops, 1);
1912 SDValue Chain = Op1.getValue(1);
1914 // Insert the EHSELECTION instruction.
1915 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1918 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurSDLoc(), VTs, Ops, 2);
1919 Chain = Op2.getValue(1);
1920 Op2 = DAG.getSExtOrTrunc(Op2, getCurSDLoc(), MVT::i32);
1924 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
1925 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1928 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1929 setValue(&LP, RetPair.first);
1930 DAG.setRoot(RetPair.second);
1933 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1934 /// small case ranges).
1935 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1936 CaseRecVector& WorkList,
1938 MachineBasicBlock *Default,
1939 MachineBasicBlock *SwitchBB) {
1940 // Size is the number of Cases represented by this range.
1941 size_t Size = CR.Range.second - CR.Range.first;
1945 // Get the MachineFunction which holds the current MBB. This is used when
1946 // inserting any additional MBBs necessary to represent the switch.
1947 MachineFunction *CurMF = FuncInfo.MF;
1949 // Figure out which block is immediately after the current one.
1950 MachineBasicBlock *NextBlock = 0;
1951 MachineFunction::iterator BBI = CR.CaseBB;
1953 if (++BBI != FuncInfo.MF->end())
1956 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1957 // If any two of the cases has the same destination, and if one value
1958 // is the same as the other, but has one bit unset that the other has set,
1959 // use bit manipulation to do two compares at once. For example:
1960 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1961 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1962 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1963 if (Size == 2 && CR.CaseBB == SwitchBB) {
1964 Case &Small = *CR.Range.first;
1965 Case &Big = *(CR.Range.second-1);
1967 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1968 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1969 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1971 // Check that there is only one bit different.
1972 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1973 (SmallValue | BigValue) == BigValue) {
1974 // Isolate the common bit.
1975 APInt CommonBit = BigValue & ~SmallValue;
1976 assert((SmallValue | CommonBit) == BigValue &&
1977 CommonBit.countPopulation() == 1 && "Not a common bit?");
1979 SDValue CondLHS = getValue(SV);
1980 EVT VT = CondLHS.getValueType();
1981 SDLoc DL = getCurSDLoc();
1983 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1984 DAG.getConstant(CommonBit, VT));
1985 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1986 Or, DAG.getConstant(BigValue, VT),
1989 // Update successor info.
1990 // Both Small and Big will jump to Small.BB, so we sum up the weights.
1991 addSuccessorWithWeight(SwitchBB, Small.BB,
1992 Small.ExtraWeight + Big.ExtraWeight);
1993 addSuccessorWithWeight(SwitchBB, Default,
1994 // The default destination is the first successor in IR.
1995 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
1997 // Insert the true branch.
1998 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1999 getControlRoot(), Cond,
2000 DAG.getBasicBlock(Small.BB));
2002 // Insert the false branch.
2003 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2004 DAG.getBasicBlock(Default));
2006 DAG.setRoot(BrCond);
2012 // Order cases by weight so the most likely case will be checked first.
2013 uint32_t UnhandledWeights = 0;
2015 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2016 uint32_t IWeight = I->ExtraWeight;
2017 UnhandledWeights += IWeight;
2018 for (CaseItr J = CR.Range.first; J < I; ++J) {
2019 uint32_t JWeight = J->ExtraWeight;
2020 if (IWeight > JWeight)
2025 // Rearrange the case blocks so that the last one falls through if possible.
2026 Case &BackCase = *(CR.Range.second-1);
2028 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2029 // The last case block won't fall through into 'NextBlock' if we emit the
2030 // branches in this order. See if rearranging a case value would help.
2031 // We start at the bottom as it's the case with the least weight.
2032 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){
2033 if (I->BB == NextBlock) {
2034 std::swap(*I, BackCase);
2040 // Create a CaseBlock record representing a conditional branch to
2041 // the Case's target mbb if the value being switched on SV is equal
2043 MachineBasicBlock *CurBlock = CR.CaseBB;
2044 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2045 MachineBasicBlock *FallThrough;
2047 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2048 CurMF->insert(BBI, FallThrough);
2050 // Put SV in a virtual register to make it available from the new blocks.
2051 ExportFromCurrentBlock(SV);
2053 // If the last case doesn't match, go to the default block.
2054 FallThrough = Default;
2057 const Value *RHS, *LHS, *MHS;
2059 if (I->High == I->Low) {
2060 // This is just small small case range :) containing exactly 1 case
2062 LHS = SV; RHS = I->High; MHS = NULL;
2064 CC = ISD::SETCC_INVALID;
2065 LHS = I->Low; MHS = SV; RHS = I->High;
2068 // The false weight should be sum of all un-handled cases.
2069 UnhandledWeights -= I->ExtraWeight;
2070 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2072 /* trueweight */ I->ExtraWeight,
2073 /* falseweight */ UnhandledWeights);
2075 // If emitting the first comparison, just call visitSwitchCase to emit the
2076 // code into the current block. Otherwise, push the CaseBlock onto the
2077 // vector to be later processed by SDISel, and insert the node's MBB
2078 // before the next MBB.
2079 if (CurBlock == SwitchBB)
2080 visitSwitchCase(CB, SwitchBB);
2082 SwitchCases.push_back(CB);
2084 CurBlock = FallThrough;
2090 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2091 return TLI.supportJumpTables() &&
2092 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2093 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2096 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2097 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2098 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth);
2099 return (LastExt - FirstExt + 1ULL);
2102 /// handleJTSwitchCase - Emit jumptable for current switch case range
2103 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2104 CaseRecVector &WorkList,
2106 MachineBasicBlock *Default,
2107 MachineBasicBlock *SwitchBB) {
2108 Case& FrontCase = *CR.Range.first;
2109 Case& BackCase = *(CR.Range.second-1);
2111 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2112 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2114 APInt TSize(First.getBitWidth(), 0);
2115 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2118 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2121 APInt Range = ComputeRange(First, Last);
2122 // The density is TSize / Range. Require at least 40%.
2123 // It should not be possible for IntTSize to saturate for sane code, but make
2124 // sure we handle Range saturation correctly.
2125 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2126 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2127 if (IntTSize * 10 < IntRange * 4)
2130 DEBUG(dbgs() << "Lowering jump table\n"
2131 << "First entry: " << First << ". Last entry: " << Last << '\n'
2132 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2134 // Get the MachineFunction which holds the current MBB. This is used when
2135 // inserting any additional MBBs necessary to represent the switch.
2136 MachineFunction *CurMF = FuncInfo.MF;
2138 // Figure out which block is immediately after the current one.
2139 MachineFunction::iterator BBI = CR.CaseBB;
2142 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2144 // Create a new basic block to hold the code for loading the address
2145 // of the jump table, and jumping to it. Update successor information;
2146 // we will either branch to the default case for the switch, or the jump
2148 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2149 CurMF->insert(BBI, JumpTableBB);
2151 addSuccessorWithWeight(CR.CaseBB, Default);
2152 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2154 // Build a vector of destination BBs, corresponding to each target
2155 // of the jump table. If the value of the jump table slot corresponds to
2156 // a case statement, push the case's BB onto the vector, otherwise, push
2158 std::vector<MachineBasicBlock*> DestBBs;
2160 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2161 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2162 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2164 if (Low.ule(TEI) && TEI.ule(High)) {
2165 DestBBs.push_back(I->BB);
2169 DestBBs.push_back(Default);
2173 // Calculate weight for each unique destination in CR.
2174 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2176 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2177 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2178 DestWeights.find(I->BB);
2179 if (Itr != DestWeights.end())
2180 Itr->second += I->ExtraWeight;
2182 DestWeights[I->BB] = I->ExtraWeight;
2185 // Update successor info. Add one edge to each unique successor.
2186 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2187 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2188 E = DestBBs.end(); I != E; ++I) {
2189 if (!SuccsHandled[(*I)->getNumber()]) {
2190 SuccsHandled[(*I)->getNumber()] = true;
2191 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2192 DestWeights.find(*I);
2193 addSuccessorWithWeight(JumpTableBB, *I,
2194 Itr != DestWeights.end() ? Itr->second : 0);
2198 // Create a jump table index for this jump table.
2199 unsigned JTEncoding = TLI.getJumpTableEncoding();
2200 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2201 ->createJumpTableIndex(DestBBs);
2203 // Set the jump table information so that we can codegen it as a second
2204 // MachineBasicBlock
2205 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2206 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2207 if (CR.CaseBB == SwitchBB)
2208 visitJumpTableHeader(JT, JTH, SwitchBB);
2210 JTCases.push_back(JumpTableBlock(JTH, JT));
2214 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2216 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2217 CaseRecVector& WorkList,
2219 MachineBasicBlock *Default,
2220 MachineBasicBlock *SwitchBB) {
2221 // Get the MachineFunction which holds the current MBB. This is used when
2222 // inserting any additional MBBs necessary to represent the switch.
2223 MachineFunction *CurMF = FuncInfo.MF;
2225 // Figure out which block is immediately after the current one.
2226 MachineFunction::iterator BBI = CR.CaseBB;
2229 Case& FrontCase = *CR.Range.first;
2230 Case& BackCase = *(CR.Range.second-1);
2231 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2233 // Size is the number of Cases represented by this range.
2234 unsigned Size = CR.Range.second - CR.Range.first;
2236 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2237 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2239 CaseItr Pivot = CR.Range.first + Size/2;
2241 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2242 // (heuristically) allow us to emit JumpTable's later.
2243 APInt TSize(First.getBitWidth(), 0);
2244 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2248 APInt LSize = FrontCase.size();
2249 APInt RSize = TSize-LSize;
2250 DEBUG(dbgs() << "Selecting best pivot: \n"
2251 << "First: " << First << ", Last: " << Last <<'\n'
2252 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2253 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2255 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2256 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2257 APInt Range = ComputeRange(LEnd, RBegin);
2258 assert((Range - 2ULL).isNonNegative() &&
2259 "Invalid case distance");
2260 // Use volatile double here to avoid excess precision issues on some hosts,
2261 // e.g. that use 80-bit X87 registers.
2262 volatile double LDensity =
2263 (double)LSize.roundToDouble() /
2264 (LEnd - First + 1ULL).roundToDouble();
2265 volatile double RDensity =
2266 (double)RSize.roundToDouble() /
2267 (Last - RBegin + 1ULL).roundToDouble();
2268 double Metric = Range.logBase2()*(LDensity+RDensity);
2269 // Should always split in some non-trivial place
2270 DEBUG(dbgs() <<"=>Step\n"
2271 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2272 << "LDensity: " << LDensity
2273 << ", RDensity: " << RDensity << '\n'
2274 << "Metric: " << Metric << '\n');
2275 if (FMetric < Metric) {
2278 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2284 if (areJTsAllowed(TLI)) {
2285 // If our case is dense we *really* should handle it earlier!
2286 assert((FMetric > 0) && "Should handle dense range earlier!");
2288 Pivot = CR.Range.first + Size/2;
2291 CaseRange LHSR(CR.Range.first, Pivot);
2292 CaseRange RHSR(Pivot, CR.Range.second);
2293 const Constant *C = Pivot->Low;
2294 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2296 // We know that we branch to the LHS if the Value being switched on is
2297 // less than the Pivot value, C. We use this to optimize our binary
2298 // tree a bit, by recognizing that if SV is greater than or equal to the
2299 // LHS's Case Value, and that Case Value is exactly one less than the
2300 // Pivot's Value, then we can branch directly to the LHS's Target,
2301 // rather than creating a leaf node for it.
2302 if ((LHSR.second - LHSR.first) == 1 &&
2303 LHSR.first->High == CR.GE &&
2304 cast<ConstantInt>(C)->getValue() ==
2305 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2306 TrueBB = LHSR.first->BB;
2308 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2309 CurMF->insert(BBI, TrueBB);
2310 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2312 // Put SV in a virtual register to make it available from the new blocks.
2313 ExportFromCurrentBlock(SV);
2316 // Similar to the optimization above, if the Value being switched on is
2317 // known to be less than the Constant CR.LT, and the current Case Value
2318 // is CR.LT - 1, then we can branch directly to the target block for
2319 // the current Case Value, rather than emitting a RHS leaf node for it.
2320 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2321 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2322 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2323 FalseBB = RHSR.first->BB;
2325 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2326 CurMF->insert(BBI, FalseBB);
2327 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2329 // Put SV in a virtual register to make it available from the new blocks.
2330 ExportFromCurrentBlock(SV);
2333 // Create a CaseBlock record representing a conditional branch to
2334 // the LHS node if the value being switched on SV is less than C.
2335 // Otherwise, branch to LHS.
2336 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2338 if (CR.CaseBB == SwitchBB)
2339 visitSwitchCase(CB, SwitchBB);
2341 SwitchCases.push_back(CB);
2346 /// handleBitTestsSwitchCase - if current case range has few destination and
2347 /// range span less, than machine word bitwidth, encode case range into series
2348 /// of masks and emit bit tests with these masks.
2349 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2350 CaseRecVector& WorkList,
2352 MachineBasicBlock* Default,
2353 MachineBasicBlock *SwitchBB){
2354 EVT PTy = TLI.getPointerTy();
2355 unsigned IntPtrBits = PTy.getSizeInBits();
2357 Case& FrontCase = *CR.Range.first;
2358 Case& BackCase = *(CR.Range.second-1);
2360 // Get the MachineFunction which holds the current MBB. This is used when
2361 // inserting any additional MBBs necessary to represent the switch.
2362 MachineFunction *CurMF = FuncInfo.MF;
2364 // If target does not have legal shift left, do not emit bit tests at all.
2365 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2369 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2371 // Single case counts one, case range - two.
2372 numCmps += (I->Low == I->High ? 1 : 2);
2375 // Count unique destinations
2376 SmallSet<MachineBasicBlock*, 4> Dests;
2377 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2378 Dests.insert(I->BB);
2379 if (Dests.size() > 3)
2380 // Don't bother the code below, if there are too much unique destinations
2383 DEBUG(dbgs() << "Total number of unique destinations: "
2384 << Dests.size() << '\n'
2385 << "Total number of comparisons: " << numCmps << '\n');
2387 // Compute span of values.
2388 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2389 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2390 APInt cmpRange = maxValue - minValue;
2392 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2393 << "Low bound: " << minValue << '\n'
2394 << "High bound: " << maxValue << '\n');
2396 if (cmpRange.uge(IntPtrBits) ||
2397 (!(Dests.size() == 1 && numCmps >= 3) &&
2398 !(Dests.size() == 2 && numCmps >= 5) &&
2399 !(Dests.size() >= 3 && numCmps >= 6)))
2402 DEBUG(dbgs() << "Emitting bit tests\n");
2403 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2405 // Optimize the case where all the case values fit in a
2406 // word without having to subtract minValue. In this case,
2407 // we can optimize away the subtraction.
2408 if (maxValue.ult(IntPtrBits)) {
2409 cmpRange = maxValue;
2411 lowBound = minValue;
2414 CaseBitsVector CasesBits;
2415 unsigned i, count = 0;
2417 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2418 MachineBasicBlock* Dest = I->BB;
2419 for (i = 0; i < count; ++i)
2420 if (Dest == CasesBits[i].BB)
2424 assert((count < 3) && "Too much destinations to test!");
2425 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2429 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2430 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2432 uint64_t lo = (lowValue - lowBound).getZExtValue();
2433 uint64_t hi = (highValue - lowBound).getZExtValue();
2434 CasesBits[i].ExtraWeight += I->ExtraWeight;
2436 for (uint64_t j = lo; j <= hi; j++) {
2437 CasesBits[i].Mask |= 1ULL << j;
2438 CasesBits[i].Bits++;
2442 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2446 // Figure out which block is immediately after the current one.
2447 MachineFunction::iterator BBI = CR.CaseBB;
2450 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2452 DEBUG(dbgs() << "Cases:\n");
2453 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2454 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2455 << ", Bits: " << CasesBits[i].Bits
2456 << ", BB: " << CasesBits[i].BB << '\n');
2458 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2459 CurMF->insert(BBI, CaseBB);
2460 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2462 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2464 // Put SV in a virtual register to make it available from the new blocks.
2465 ExportFromCurrentBlock(SV);
2468 BitTestBlock BTB(lowBound, cmpRange, SV,
2469 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2470 CR.CaseBB, Default, BTC);
2472 if (CR.CaseBB == SwitchBB)
2473 visitBitTestHeader(BTB, SwitchBB);
2475 BitTestCases.push_back(BTB);
2480 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2481 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2482 const SwitchInst& SI) {
2484 /// Use a shorter form of declaration, and also
2485 /// show the we want to use CRSBuilder as Clusterifier.
2486 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier;
2488 Clusterifier TheClusterifier;
2490 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2491 // Start with "simple" cases
2492 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2494 const BasicBlock *SuccBB = i.getCaseSuccessor();
2495 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2497 TheClusterifier.add(i.getCaseValueEx(), SMBB,
2498 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0);
2501 TheClusterifier.optimize();
2504 for (Clusterifier::RangeIterator i = TheClusterifier.begin(),
2505 e = TheClusterifier.end(); i != e; ++i, ++numCmps) {
2506 Clusterifier::Cluster &C = *i;
2507 // Update edge weight for the cluster.
2508 unsigned W = C.first.Weight;
2510 // FIXME: Currently work with ConstantInt based numbers.
2511 // Changing it to APInt based is a pretty heavy for this commit.
2512 Cases.push_back(Case(C.first.getLow().toConstantInt(),
2513 C.first.getHigh().toConstantInt(), C.second, W));
2515 if (C.first.getLow() != C.first.getHigh())
2516 // A range counts double, since it requires two compares.
2523 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2524 MachineBasicBlock *Last) {
2526 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2527 if (JTCases[i].first.HeaderBB == First)
2528 JTCases[i].first.HeaderBB = Last;
2530 // Update BitTestCases.
2531 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2532 if (BitTestCases[i].Parent == First)
2533 BitTestCases[i].Parent = Last;
2536 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2537 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2539 // Figure out which block is immediately after the current one.
2540 MachineBasicBlock *NextBlock = 0;
2541 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2543 // If there is only the default destination, branch to it if it is not the
2544 // next basic block. Otherwise, just fall through.
2545 if (!SI.getNumCases()) {
2546 // Update machine-CFG edges.
2548 // If this is not a fall-through branch, emit the branch.
2549 SwitchMBB->addSuccessor(Default);
2550 if (Default != NextBlock)
2551 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2552 MVT::Other, getControlRoot(),
2553 DAG.getBasicBlock(Default)));
2558 // If there are any non-default case statements, create a vector of Cases
2559 // representing each one, and sort the vector so that we can efficiently
2560 // create a binary search tree from them.
2562 size_t numCmps = Clusterify(Cases, SI);
2563 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2564 << ". Total compares: " << numCmps << '\n');
2567 // Get the Value to be switched on and default basic blocks, which will be
2568 // inserted into CaseBlock records, representing basic blocks in the binary
2570 const Value *SV = SI.getCondition();
2572 // Push the initial CaseRec onto the worklist
2573 CaseRecVector WorkList;
2574 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2575 CaseRange(Cases.begin(),Cases.end())));
2577 while (!WorkList.empty()) {
2578 // Grab a record representing a case range to process off the worklist
2579 CaseRec CR = WorkList.back();
2580 WorkList.pop_back();
2582 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2585 // If the range has few cases (two or less) emit a series of specific
2587 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2590 // If the switch has more than N blocks, and is at least 40% dense, and the
2591 // target supports indirect branches, then emit a jump table rather than
2592 // lowering the switch to a binary tree of conditional branches.
2593 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2594 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2597 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2598 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2599 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2603 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2604 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2606 // Update machine-CFG edges with unique successors.
2607 SmallSet<BasicBlock*, 32> Done;
2608 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2609 BasicBlock *BB = I.getSuccessor(i);
2610 bool Inserted = Done.insert(BB);
2614 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2615 addSuccessorWithWeight(IndirectBrMBB, Succ);
2618 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2619 MVT::Other, getControlRoot(),
2620 getValue(I.getAddress())));
2623 void SelectionDAGBuilder::visitFSub(const User &I) {
2624 // -0.0 - X --> fneg
2625 Type *Ty = I.getType();
2626 if (isa<Constant>(I.getOperand(0)) &&
2627 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2628 SDValue Op2 = getValue(I.getOperand(1));
2629 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2630 Op2.getValueType(), Op2));
2634 visitBinary(I, ISD::FSUB);
2637 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2638 SDValue Op1 = getValue(I.getOperand(0));
2639 SDValue Op2 = getValue(I.getOperand(1));
2640 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(),
2641 Op1.getValueType(), Op1, Op2));
2644 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2645 SDValue Op1 = getValue(I.getOperand(0));
2646 SDValue Op2 = getValue(I.getOperand(1));
2648 EVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2650 // Coerce the shift amount to the right type if we can.
2651 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2652 unsigned ShiftSize = ShiftTy.getSizeInBits();
2653 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2654 SDLoc DL = getCurSDLoc();
2656 // If the operand is smaller than the shift count type, promote it.
2657 if (ShiftSize > Op2Size)
2658 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2660 // If the operand is larger than the shift count type but the shift
2661 // count type has enough bits to represent any shift value, truncate
2662 // it now. This is a common case and it exposes the truncate to
2663 // optimization early.
2664 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2665 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2666 // Otherwise we'll need to temporarily settle for some other convenient
2667 // type. Type legalization will make adjustments once the shiftee is split.
2669 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2672 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(),
2673 Op1.getValueType(), Op1, Op2));
2676 void SelectionDAGBuilder::visitSDiv(const User &I) {
2677 SDValue Op1 = getValue(I.getOperand(0));
2678 SDValue Op2 = getValue(I.getOperand(1));
2680 // Turn exact SDivs into multiplications.
2681 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2683 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2684 !isa<ConstantSDNode>(Op1) &&
2685 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2686 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2688 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2692 void SelectionDAGBuilder::visitICmp(const User &I) {
2693 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2694 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2695 predicate = IC->getPredicate();
2696 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2697 predicate = ICmpInst::Predicate(IC->getPredicate());
2698 SDValue Op1 = getValue(I.getOperand(0));
2699 SDValue Op2 = getValue(I.getOperand(1));
2700 ISD::CondCode Opcode = getICmpCondCode(predicate);
2702 EVT DestVT = TLI.getValueType(I.getType());
2703 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2706 void SelectionDAGBuilder::visitFCmp(const User &I) {
2707 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2708 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2709 predicate = FC->getPredicate();
2710 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2711 predicate = FCmpInst::Predicate(FC->getPredicate());
2712 SDValue Op1 = getValue(I.getOperand(0));
2713 SDValue Op2 = getValue(I.getOperand(1));
2714 ISD::CondCode Condition = getFCmpCondCode(predicate);
2715 if (TM.Options.NoNaNsFPMath)
2716 Condition = getFCmpCodeWithoutNaN(Condition);
2717 EVT DestVT = TLI.getValueType(I.getType());
2718 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2721 void SelectionDAGBuilder::visitSelect(const User &I) {
2722 SmallVector<EVT, 4> ValueVTs;
2723 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2724 unsigned NumValues = ValueVTs.size();
2725 if (NumValues == 0) return;
2727 SmallVector<SDValue, 4> Values(NumValues);
2728 SDValue Cond = getValue(I.getOperand(0));
2729 SDValue TrueVal = getValue(I.getOperand(1));
2730 SDValue FalseVal = getValue(I.getOperand(2));
2731 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2732 ISD::VSELECT : ISD::SELECT;
2734 for (unsigned i = 0; i != NumValues; ++i)
2735 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2736 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2738 SDValue(TrueVal.getNode(),
2739 TrueVal.getResNo() + i),
2740 SDValue(FalseVal.getNode(),
2741 FalseVal.getResNo() + i));
2743 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2744 DAG.getVTList(&ValueVTs[0], NumValues),
2745 &Values[0], NumValues));
2748 void SelectionDAGBuilder::visitTrunc(const User &I) {
2749 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2750 SDValue N = getValue(I.getOperand(0));
2751 EVT DestVT = TLI.getValueType(I.getType());
2752 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2755 void SelectionDAGBuilder::visitZExt(const User &I) {
2756 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2757 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2758 SDValue N = getValue(I.getOperand(0));
2759 EVT DestVT = TLI.getValueType(I.getType());
2760 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2763 void SelectionDAGBuilder::visitSExt(const User &I) {
2764 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2765 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2766 SDValue N = getValue(I.getOperand(0));
2767 EVT DestVT = TLI.getValueType(I.getType());
2768 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2771 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2772 // FPTrunc is never a no-op cast, no need to check
2773 SDValue N = getValue(I.getOperand(0));
2774 EVT DestVT = TLI.getValueType(I.getType());
2775 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2777 DAG.getTargetConstant(0, TLI.getPointerTy())));
2780 void SelectionDAGBuilder::visitFPExt(const User &I){
2781 // FPExt is never a no-op cast, no need to check
2782 SDValue N = getValue(I.getOperand(0));
2783 EVT DestVT = TLI.getValueType(I.getType());
2784 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2787 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2788 // FPToUI is never a no-op cast, no need to check
2789 SDValue N = getValue(I.getOperand(0));
2790 EVT DestVT = TLI.getValueType(I.getType());
2791 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2794 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2795 // FPToSI is never a no-op cast, no need to check
2796 SDValue N = getValue(I.getOperand(0));
2797 EVT DestVT = TLI.getValueType(I.getType());
2798 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2801 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2802 // UIToFP is never a no-op cast, no need to check
2803 SDValue N = getValue(I.getOperand(0));
2804 EVT DestVT = TLI.getValueType(I.getType());
2805 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2808 void SelectionDAGBuilder::visitSIToFP(const User &I){
2809 // SIToFP is never a no-op cast, no need to check
2810 SDValue N = getValue(I.getOperand(0));
2811 EVT DestVT = TLI.getValueType(I.getType());
2812 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2815 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2816 // What to do depends on the size of the integer and the size of the pointer.
2817 // We can either truncate, zero extend, or no-op, accordingly.
2818 SDValue N = getValue(I.getOperand(0));
2819 EVT DestVT = TLI.getValueType(I.getType());
2820 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2823 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2824 // What to do depends on the size of the integer and the size of the pointer.
2825 // We can either truncate, zero extend, or no-op, accordingly.
2826 SDValue N = getValue(I.getOperand(0));
2827 EVT DestVT = TLI.getValueType(I.getType());
2828 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2831 void SelectionDAGBuilder::visitBitCast(const User &I) {
2832 SDValue N = getValue(I.getOperand(0));
2833 EVT DestVT = TLI.getValueType(I.getType());
2835 // BitCast assures us that source and destination are the same size so this is
2836 // either a BITCAST or a no-op.
2837 if (DestVT != N.getValueType())
2838 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
2839 DestVT, N)); // convert types.
2841 setValue(&I, N); // noop cast.
2844 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2845 SDValue InVec = getValue(I.getOperand(0));
2846 SDValue InVal = getValue(I.getOperand(1));
2847 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(),
2849 getValue(I.getOperand(2)));
2850 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2851 TLI.getValueType(I.getType()),
2852 InVec, InVal, InIdx));
2855 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2856 SDValue InVec = getValue(I.getOperand(0));
2857 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(),
2859 getValue(I.getOperand(1)));
2860 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2861 TLI.getValueType(I.getType()), InVec, InIdx));
2864 // Utility for visitShuffleVector - Return true if every element in Mask,
2865 // beginning from position Pos and ending in Pos+Size, falls within the
2866 // specified sequential range [L, L+Pos). or is undef.
2867 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2868 unsigned Pos, unsigned Size, int Low) {
2869 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2870 if (Mask[i] >= 0 && Mask[i] != Low)
2875 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2876 SDValue Src1 = getValue(I.getOperand(0));
2877 SDValue Src2 = getValue(I.getOperand(1));
2879 SmallVector<int, 8> Mask;
2880 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2881 unsigned MaskNumElts = Mask.size();
2883 EVT VT = TLI.getValueType(I.getType());
2884 EVT SrcVT = Src1.getValueType();
2885 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2887 if (SrcNumElts == MaskNumElts) {
2888 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2893 // Normalize the shuffle vector since mask and vector length don't match.
2894 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2895 // Mask is longer than the source vectors and is a multiple of the source
2896 // vectors. We can use concatenate vector to make the mask and vectors
2898 if (SrcNumElts*2 == MaskNumElts) {
2899 // First check for Src1 in low and Src2 in high
2900 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2901 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2902 // The shuffle is concatenating two vectors together.
2903 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2907 // Then check for Src2 in low and Src1 in high
2908 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2909 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2910 // The shuffle is concatenating two vectors together.
2911 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2917 // Pad both vectors with undefs to make them the same length as the mask.
2918 unsigned NumConcat = MaskNumElts / SrcNumElts;
2919 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2920 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2921 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2923 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2924 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2928 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2930 &MOps1[0], NumConcat);
2931 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2933 &MOps2[0], NumConcat);
2935 // Readjust mask for new input vector length.
2936 SmallVector<int, 8> MappedOps;
2937 for (unsigned i = 0; i != MaskNumElts; ++i) {
2939 if (Idx >= (int)SrcNumElts)
2940 Idx -= SrcNumElts - MaskNumElts;
2941 MappedOps.push_back(Idx);
2944 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2949 if (SrcNumElts > MaskNumElts) {
2950 // Analyze the access pattern of the vector to see if we can extract
2951 // two subvectors and do the shuffle. The analysis is done by calculating
2952 // the range of elements the mask access on both vectors.
2953 int MinRange[2] = { static_cast<int>(SrcNumElts),
2954 static_cast<int>(SrcNumElts)};
2955 int MaxRange[2] = {-1, -1};
2957 for (unsigned i = 0; i != MaskNumElts; ++i) {
2963 if (Idx >= (int)SrcNumElts) {
2967 if (Idx > MaxRange[Input])
2968 MaxRange[Input] = Idx;
2969 if (Idx < MinRange[Input])
2970 MinRange[Input] = Idx;
2973 // Check if the access is smaller than the vector size and can we find
2974 // a reasonable extract index.
2975 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2977 int StartIdx[2]; // StartIdx to extract from
2978 for (unsigned Input = 0; Input < 2; ++Input) {
2979 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2980 RangeUse[Input] = 0; // Unused
2981 StartIdx[Input] = 0;
2985 // Find a good start index that is a multiple of the mask length. Then
2986 // see if the rest of the elements are in range.
2987 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2988 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2989 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2990 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2993 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2994 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2997 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2998 // Extract appropriate subvector and generate a vector shuffle
2999 for (unsigned Input = 0; Input < 2; ++Input) {
3000 SDValue &Src = Input == 0 ? Src1 : Src2;
3001 if (RangeUse[Input] == 0)
3002 Src = DAG.getUNDEF(VT);
3004 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3005 Src, DAG.getIntPtrConstant(StartIdx[Input]));
3008 // Calculate new mask.
3009 SmallVector<int, 8> MappedOps;
3010 for (unsigned i = 0; i != MaskNumElts; ++i) {
3013 if (Idx < (int)SrcNumElts)
3016 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3018 MappedOps.push_back(Idx);
3021 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3027 // We can't use either concat vectors or extract subvectors so fall back to
3028 // replacing the shuffle with extract and build vector.
3029 // to insert and build vector.
3030 EVT EltVT = VT.getVectorElementType();
3031 EVT PtrVT = TLI.getPointerTy();
3032 SmallVector<SDValue,8> Ops;
3033 for (unsigned i = 0; i != MaskNumElts; ++i) {
3038 Res = DAG.getUNDEF(EltVT);
3040 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3041 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3043 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3044 EltVT, Src, DAG.getConstant(Idx, PtrVT));
3050 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
3051 VT, &Ops[0], Ops.size()));
3054 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3055 const Value *Op0 = I.getOperand(0);
3056 const Value *Op1 = I.getOperand(1);
3057 Type *AggTy = I.getType();
3058 Type *ValTy = Op1->getType();
3059 bool IntoUndef = isa<UndefValue>(Op0);
3060 bool FromUndef = isa<UndefValue>(Op1);
3062 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3064 SmallVector<EVT, 4> AggValueVTs;
3065 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3066 SmallVector<EVT, 4> ValValueVTs;
3067 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3069 unsigned NumAggValues = AggValueVTs.size();
3070 unsigned NumValValues = ValValueVTs.size();
3071 SmallVector<SDValue, 4> Values(NumAggValues);
3073 SDValue Agg = getValue(Op0);
3075 // Copy the beginning value(s) from the original aggregate.
3076 for (; i != LinearIndex; ++i)
3077 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3078 SDValue(Agg.getNode(), Agg.getResNo() + i);
3079 // Copy values from the inserted value(s).
3081 SDValue Val = getValue(Op1);
3082 for (; i != LinearIndex + NumValValues; ++i)
3083 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3084 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3086 // Copy remaining value(s) from the original aggregate.
3087 for (; i != NumAggValues; ++i)
3088 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3089 SDValue(Agg.getNode(), Agg.getResNo() + i);
3091 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3092 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3093 &Values[0], NumAggValues));
3096 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3097 const Value *Op0 = I.getOperand(0);
3098 Type *AggTy = Op0->getType();
3099 Type *ValTy = I.getType();
3100 bool OutOfUndef = isa<UndefValue>(Op0);
3102 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3104 SmallVector<EVT, 4> ValValueVTs;
3105 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3107 unsigned NumValValues = ValValueVTs.size();
3109 // Ignore a extractvalue that produces an empty object
3110 if (!NumValValues) {
3111 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3115 SmallVector<SDValue, 4> Values(NumValValues);
3117 SDValue Agg = getValue(Op0);
3118 // Copy out the selected value(s).
3119 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3120 Values[i - LinearIndex] =
3122 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3123 SDValue(Agg.getNode(), Agg.getResNo() + i);
3125 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3126 DAG.getVTList(&ValValueVTs[0], NumValValues),
3127 &Values[0], NumValValues));
3130 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3131 SDValue N = getValue(I.getOperand(0));
3132 // Note that the pointer operand may be a vector of pointers. Take the scalar
3133 // element which holds a pointer.
3134 Type *Ty = I.getOperand(0)->getType()->getScalarType();
3136 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3138 const Value *Idx = *OI;
3139 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3140 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3143 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3144 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3145 DAG.getConstant(Offset, N.getValueType()));
3148 Ty = StTy->getElementType(Field);
3150 Ty = cast<SequentialType>(Ty)->getElementType();
3152 // If this is a constant subscript, handle it quickly.
3153 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3154 if (CI->isZero()) continue;
3156 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3158 EVT PTy = TLI.getPointerTy();
3159 unsigned PtrBits = PTy.getSizeInBits();
3161 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(),
3163 DAG.getConstant(Offs, MVT::i64));
3165 OffsVal = DAG.getIntPtrConstant(Offs);
3167 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3172 // N = N + Idx * ElementSize;
3173 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3174 TD->getTypeAllocSize(Ty));
3175 SDValue IdxN = getValue(Idx);
3177 // If the index is smaller or larger than intptr_t, truncate or extend
3179 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3181 // If this is a multiply by a power of two, turn it into a shl
3182 // immediately. This is a very common case.
3183 if (ElementSize != 1) {
3184 if (ElementSize.isPowerOf2()) {
3185 unsigned Amt = ElementSize.logBase2();
3186 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3187 N.getValueType(), IdxN,
3188 DAG.getConstant(Amt, IdxN.getValueType()));
3190 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3191 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3192 N.getValueType(), IdxN, Scale);
3196 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3197 N.getValueType(), N, IdxN);
3204 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3205 // If this is a fixed sized alloca in the entry block of the function,
3206 // allocate it statically on the stack.
3207 if (FuncInfo.StaticAllocaMap.count(&I))
3208 return; // getValue will auto-populate this.
3210 Type *Ty = I.getAllocatedType();
3211 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3213 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3216 SDValue AllocSize = getValue(I.getArraySize());
3218 EVT IntPtr = TLI.getPointerTy();
3219 if (AllocSize.getValueType() != IntPtr)
3220 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3222 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3224 DAG.getConstant(TySize, IntPtr));
3226 // Handle alignment. If the requested alignment is less than or equal to
3227 // the stack alignment, ignore it. If the size is greater than or equal to
3228 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3229 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3230 if (Align <= StackAlign)
3233 // Round the size of the allocation up to the stack alignment size
3234 // by add SA-1 to the size.
3235 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3236 AllocSize.getValueType(), AllocSize,
3237 DAG.getIntPtrConstant(StackAlign-1));
3239 // Mask out the low bits for alignment purposes.
3240 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3241 AllocSize.getValueType(), AllocSize,
3242 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3244 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3245 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3246 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(),
3249 DAG.setRoot(DSA.getValue(1));
3251 // Inform the Frame Information that we have just allocated a variable-sized
3253 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3256 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3258 return visitAtomicLoad(I);
3260 const Value *SV = I.getOperand(0);
3261 SDValue Ptr = getValue(SV);
3263 Type *Ty = I.getType();
3265 bool isVolatile = I.isVolatile();
3266 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3267 bool isInvariant = I.getMetadata("invariant.load") != 0;
3268 unsigned Alignment = I.getAlignment();
3269 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3270 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3272 SmallVector<EVT, 4> ValueVTs;
3273 SmallVector<uint64_t, 4> Offsets;
3274 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3275 unsigned NumValues = ValueVTs.size();
3280 bool ConstantMemory = false;
3281 if (I.isVolatile() || NumValues > MaxParallelChains)
3282 // Serialize volatile loads with other side effects.
3284 else if (AA->pointsToConstantMemory(
3285 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3286 // Do not serialize (non-volatile) loads of constant memory with anything.
3287 Root = DAG.getEntryNode();
3288 ConstantMemory = true;
3290 // Do not serialize non-volatile loads against each other.
3291 Root = DAG.getRoot();
3294 SmallVector<SDValue, 4> Values(NumValues);
3295 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3297 EVT PtrVT = Ptr.getValueType();
3298 unsigned ChainI = 0;
3299 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3300 // Serializing loads here may result in excessive register pressure, and
3301 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3302 // could recover a bit by hoisting nodes upward in the chain by recognizing
3303 // they are side-effect free or do not alias. The optimizer should really
3304 // avoid this case by converting large object/array copies to llvm.memcpy
3305 // (MaxParallelChains should always remain as failsafe).
3306 if (ChainI == MaxParallelChains) {
3307 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3308 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3309 MVT::Other, &Chains[0], ChainI);
3313 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3315 DAG.getConstant(Offsets[i], PtrVT));
3316 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3317 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3318 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3322 Chains[ChainI] = L.getValue(1);
3325 if (!ConstantMemory) {
3326 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3327 MVT::Other, &Chains[0], ChainI);
3331 PendingLoads.push_back(Chain);
3334 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3335 DAG.getVTList(&ValueVTs[0], NumValues),
3336 &Values[0], NumValues));
3339 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3341 return visitAtomicStore(I);
3343 const Value *SrcV = I.getOperand(0);
3344 const Value *PtrV = I.getOperand(1);
3346 SmallVector<EVT, 4> ValueVTs;
3347 SmallVector<uint64_t, 4> Offsets;
3348 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3349 unsigned NumValues = ValueVTs.size();
3353 // Get the lowered operands. Note that we do this after
3354 // checking if NumResults is zero, because with zero results
3355 // the operands won't have values in the map.
3356 SDValue Src = getValue(SrcV);
3357 SDValue Ptr = getValue(PtrV);
3359 SDValue Root = getRoot();
3360 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3362 EVT PtrVT = Ptr.getValueType();
3363 bool isVolatile = I.isVolatile();
3364 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3365 unsigned Alignment = I.getAlignment();
3366 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3368 unsigned ChainI = 0;
3369 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3370 // See visitLoad comments.
3371 if (ChainI == MaxParallelChains) {
3372 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3373 MVT::Other, &Chains[0], ChainI);
3377 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3378 DAG.getConstant(Offsets[i], PtrVT));
3379 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3380 SDValue(Src.getNode(), Src.getResNo() + i),
3381 Add, MachinePointerInfo(PtrV, Offsets[i]),
3382 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3383 Chains[ChainI] = St;
3386 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3387 MVT::Other, &Chains[0], ChainI);
3388 DAG.setRoot(StoreNode);
3391 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3392 SynchronizationScope Scope,
3393 bool Before, SDLoc dl,
3395 const TargetLowering &TLI) {
3396 // Fence, if necessary
3398 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3400 else if (Order == Acquire || Order == Monotonic)
3403 if (Order == AcquireRelease)
3405 else if (Order == Release || Order == Monotonic)
3410 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3411 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3412 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3415 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3416 SDLoc dl = getCurSDLoc();
3417 AtomicOrdering Order = I.getOrdering();
3418 SynchronizationScope Scope = I.getSynchScope();
3420 SDValue InChain = getRoot();
3422 if (TLI.getInsertFencesForAtomic())
3423 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3427 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3428 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3430 getValue(I.getPointerOperand()),
3431 getValue(I.getCompareOperand()),
3432 getValue(I.getNewValOperand()),
3433 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3434 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3437 SDValue OutChain = L.getValue(1);
3439 if (TLI.getInsertFencesForAtomic())
3440 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3444 DAG.setRoot(OutChain);
3447 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3448 SDLoc dl = getCurSDLoc();
3450 switch (I.getOperation()) {
3451 default: llvm_unreachable("Unknown atomicrmw operation");
3452 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3453 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3454 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3455 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3456 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3457 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3458 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3459 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3460 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3461 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3462 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3464 AtomicOrdering Order = I.getOrdering();
3465 SynchronizationScope Scope = I.getSynchScope();
3467 SDValue InChain = getRoot();
3469 if (TLI.getInsertFencesForAtomic())
3470 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3474 DAG.getAtomic(NT, dl,
3475 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3477 getValue(I.getPointerOperand()),
3478 getValue(I.getValOperand()),
3479 I.getPointerOperand(), 0 /* Alignment */,
3480 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3483 SDValue OutChain = L.getValue(1);
3485 if (TLI.getInsertFencesForAtomic())
3486 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3490 DAG.setRoot(OutChain);
3493 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3494 SDLoc dl = getCurSDLoc();
3497 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3498 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3499 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3502 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3503 SDLoc dl = getCurSDLoc();
3504 AtomicOrdering Order = I.getOrdering();
3505 SynchronizationScope Scope = I.getSynchScope();
3507 SDValue InChain = getRoot();
3509 EVT VT = TLI.getValueType(I.getType());
3511 if (I.getAlignment() < VT.getSizeInBits() / 8)
3512 report_fatal_error("Cannot generate unaligned atomic load");
3515 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3516 getValue(I.getPointerOperand()),
3517 I.getPointerOperand(), I.getAlignment(),
3518 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3521 SDValue OutChain = L.getValue(1);
3523 if (TLI.getInsertFencesForAtomic())
3524 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3528 DAG.setRoot(OutChain);
3531 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3532 SDLoc dl = getCurSDLoc();
3534 AtomicOrdering Order = I.getOrdering();
3535 SynchronizationScope Scope = I.getSynchScope();
3537 SDValue InChain = getRoot();
3539 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3541 if (I.getAlignment() < VT.getSizeInBits() / 8)
3542 report_fatal_error("Cannot generate unaligned atomic store");
3544 if (TLI.getInsertFencesForAtomic())
3545 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3549 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3551 getValue(I.getPointerOperand()),
3552 getValue(I.getValueOperand()),
3553 I.getPointerOperand(), I.getAlignment(),
3554 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3557 if (TLI.getInsertFencesForAtomic())
3558 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3561 DAG.setRoot(OutChain);
3564 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3566 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3567 unsigned Intrinsic) {
3568 bool HasChain = !I.doesNotAccessMemory();
3569 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3571 // Build the operand list.
3572 SmallVector<SDValue, 8> Ops;
3573 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3575 // We don't need to serialize loads against other loads.
3576 Ops.push_back(DAG.getRoot());
3578 Ops.push_back(getRoot());
3582 // Info is set by getTgtMemInstrinsic
3583 TargetLowering::IntrinsicInfo Info;
3584 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3586 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3587 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3588 Info.opc == ISD::INTRINSIC_W_CHAIN)
3589 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3591 // Add all operands of the call to the operand list.
3592 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3593 SDValue Op = getValue(I.getArgOperand(i));
3597 SmallVector<EVT, 4> ValueVTs;
3598 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3601 ValueVTs.push_back(MVT::Other);
3603 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3607 if (IsTgtIntrinsic) {
3608 // This is target intrinsic that touches memory
3609 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3610 VTs, &Ops[0], Ops.size(),
3612 MachinePointerInfo(Info.ptrVal, Info.offset),
3613 Info.align, Info.vol,
3614 Info.readMem, Info.writeMem);
3615 } else if (!HasChain) {
3616 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(),
3617 VTs, &Ops[0], Ops.size());
3618 } else if (!I.getType()->isVoidTy()) {
3619 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(),
3620 VTs, &Ops[0], Ops.size());
3622 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(),
3623 VTs, &Ops[0], Ops.size());
3627 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3629 PendingLoads.push_back(Chain);
3634 if (!I.getType()->isVoidTy()) {
3635 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3636 EVT VT = TLI.getValueType(PTy);
3637 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3640 setValue(&I, Result);
3644 /// GetSignificand - Get the significand and build it into a floating-point
3645 /// number with exponent of 1:
3647 /// Op = (Op & 0x007fffff) | 0x3f800000;
3649 /// where Op is the hexadecimal representation of floating point value.
3651 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3652 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3653 DAG.getConstant(0x007fffff, MVT::i32));
3654 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3655 DAG.getConstant(0x3f800000, MVT::i32));
3656 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3659 /// GetExponent - Get the exponent:
3661 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3663 /// where Op is the hexadecimal representation of floating point value.
3665 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3667 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3668 DAG.getConstant(0x7f800000, MVT::i32));
3669 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3670 DAG.getConstant(23, TLI.getPointerTy()));
3671 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3672 DAG.getConstant(127, MVT::i32));
3673 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3676 /// getF32Constant - Get 32-bit floating point constant.
3678 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3679 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3683 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3684 /// limited-precision mode.
3685 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3686 const TargetLowering &TLI) {
3687 if (Op.getValueType() == MVT::f32 &&
3688 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3690 // Put the exponent in the right bit position for later addition to the
3693 // #define LOG2OFe 1.4426950f
3694 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3695 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3696 getF32Constant(DAG, 0x3fb8aa3b));
3697 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3699 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3700 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3701 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3703 // IntegerPartOfX <<= 23;
3704 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3705 DAG.getConstant(23, TLI.getPointerTy()));
3707 SDValue TwoToFracPartOfX;
3708 if (LimitFloatPrecision <= 6) {
3709 // For floating-point precision of 6:
3711 // TwoToFractionalPartOfX =
3713 // (0.735607626f + 0.252464424f * x) * x;
3715 // error 0.0144103317, which is 6 bits
3716 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3717 getF32Constant(DAG, 0x3e814304));
3718 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3719 getF32Constant(DAG, 0x3f3c50c8));
3720 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3721 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3722 getF32Constant(DAG, 0x3f7f5e7e));
3723 } else if (LimitFloatPrecision <= 12) {
3724 // For floating-point precision of 12:
3726 // TwoToFractionalPartOfX =
3729 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3731 // 0.000107046256 error, which is 13 to 14 bits
3732 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3733 getF32Constant(DAG, 0x3da235e3));
3734 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3735 getF32Constant(DAG, 0x3e65b8f3));
3736 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3737 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3738 getF32Constant(DAG, 0x3f324b07));
3739 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3740 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3741 getF32Constant(DAG, 0x3f7ff8fd));
3742 } else { // LimitFloatPrecision <= 18
3743 // For floating-point precision of 18:
3745 // TwoToFractionalPartOfX =
3749 // (0.554906021e-1f +
3750 // (0.961591928e-2f +
3751 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3753 // error 2.47208000*10^(-7), which is better than 18 bits
3754 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3755 getF32Constant(DAG, 0x3924b03e));
3756 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3757 getF32Constant(DAG, 0x3ab24b87));
3758 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3759 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3760 getF32Constant(DAG, 0x3c1d8c17));
3761 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3762 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3763 getF32Constant(DAG, 0x3d634a1d));
3764 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3765 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3766 getF32Constant(DAG, 0x3e75fe14));
3767 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3768 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3769 getF32Constant(DAG, 0x3f317234));
3770 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3771 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3772 getF32Constant(DAG, 0x3f800000));
3775 // Add the exponent into the result in integer domain.
3776 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3777 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3778 DAG.getNode(ISD::ADD, dl, MVT::i32,
3779 t13, IntegerPartOfX));
3782 // No special expansion.
3783 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3786 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3787 /// limited-precision mode.
3788 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3789 const TargetLowering &TLI) {
3790 if (Op.getValueType() == MVT::f32 &&
3791 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3792 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3794 // Scale the exponent by log(2) [0.69314718f].
3795 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3796 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3797 getF32Constant(DAG, 0x3f317218));
3799 // Get the significand and build it into a floating-point number with
3801 SDValue X = GetSignificand(DAG, Op1, dl);
3803 SDValue LogOfMantissa;
3804 if (LimitFloatPrecision <= 6) {
3805 // For floating-point precision of 6:
3809 // (1.4034025f - 0.23903021f * x) * x;
3811 // error 0.0034276066, which is better than 8 bits
3812 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3813 getF32Constant(DAG, 0xbe74c456));
3814 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3815 getF32Constant(DAG, 0x3fb3a2b1));
3816 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3817 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3818 getF32Constant(DAG, 0x3f949a29));
3819 } else if (LimitFloatPrecision <= 12) {
3820 // For floating-point precision of 12:
3826 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3828 // error 0.000061011436, which is 14 bits
3829 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3830 getF32Constant(DAG, 0xbd67b6d6));
3831 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3832 getF32Constant(DAG, 0x3ee4f4b8));
3833 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3834 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3835 getF32Constant(DAG, 0x3fbc278b));
3836 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3837 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3838 getF32Constant(DAG, 0x40348e95));
3839 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3840 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3841 getF32Constant(DAG, 0x3fdef31a));
3842 } else { // LimitFloatPrecision <= 18
3843 // For floating-point precision of 18:
3851 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3853 // error 0.0000023660568, which is better than 18 bits
3854 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3855 getF32Constant(DAG, 0xbc91e5ac));
3856 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3857 getF32Constant(DAG, 0x3e4350aa));
3858 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3859 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3860 getF32Constant(DAG, 0x3f60d3e3));
3861 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3862 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3863 getF32Constant(DAG, 0x4011cdf0));
3864 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3865 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3866 getF32Constant(DAG, 0x406cfd1c));
3867 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3868 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3869 getF32Constant(DAG, 0x408797cb));
3870 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3871 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3872 getF32Constant(DAG, 0x4006dcab));
3875 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3878 // No special expansion.
3879 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3882 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3883 /// limited-precision mode.
3884 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3885 const TargetLowering &TLI) {
3886 if (Op.getValueType() == MVT::f32 &&
3887 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3888 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3890 // Get the exponent.
3891 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3893 // Get the significand and build it into a floating-point number with
3895 SDValue X = GetSignificand(DAG, Op1, dl);
3897 // Different possible minimax approximations of significand in
3898 // floating-point for various degrees of accuracy over [1,2].
3899 SDValue Log2ofMantissa;
3900 if (LimitFloatPrecision <= 6) {
3901 // For floating-point precision of 6:
3903 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3905 // error 0.0049451742, which is more than 7 bits
3906 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3907 getF32Constant(DAG, 0xbeb08fe0));
3908 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3909 getF32Constant(DAG, 0x40019463));
3910 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3911 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3912 getF32Constant(DAG, 0x3fd6633d));
3913 } else if (LimitFloatPrecision <= 12) {
3914 // For floating-point precision of 12:
3920 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3922 // error 0.0000876136000, which is better than 13 bits
3923 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3924 getF32Constant(DAG, 0xbda7262e));
3925 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3926 getF32Constant(DAG, 0x3f25280b));
3927 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3928 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3929 getF32Constant(DAG, 0x4007b923));
3930 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3931 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3932 getF32Constant(DAG, 0x40823e2f));
3933 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3934 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3935 getF32Constant(DAG, 0x4020d29c));
3936 } else { // LimitFloatPrecision <= 18
3937 // For floating-point precision of 18:
3946 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3948 // error 0.0000018516, which is better than 18 bits
3949 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3950 getF32Constant(DAG, 0xbcd2769e));
3951 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3952 getF32Constant(DAG, 0x3e8ce0b9));
3953 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3954 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3955 getF32Constant(DAG, 0x3fa22ae7));
3956 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3957 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3958 getF32Constant(DAG, 0x40525723));
3959 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3960 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3961 getF32Constant(DAG, 0x40aaf200));
3962 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3963 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3964 getF32Constant(DAG, 0x40c39dad));
3965 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3966 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3967 getF32Constant(DAG, 0x4042902c));
3970 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3973 // No special expansion.
3974 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3977 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3978 /// limited-precision mode.
3979 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3980 const TargetLowering &TLI) {
3981 if (Op.getValueType() == MVT::f32 &&
3982 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3983 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3985 // Scale the exponent by log10(2) [0.30102999f].
3986 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3987 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3988 getF32Constant(DAG, 0x3e9a209a));
3990 // Get the significand and build it into a floating-point number with
3992 SDValue X = GetSignificand(DAG, Op1, dl);
3994 SDValue Log10ofMantissa;
3995 if (LimitFloatPrecision <= 6) {
3996 // For floating-point precision of 6:
3998 // Log10ofMantissa =
4000 // (0.60948995f - 0.10380950f * x) * x;
4002 // error 0.0014886165, which is 6 bits
4003 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4004 getF32Constant(DAG, 0xbdd49a13));
4005 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4006 getF32Constant(DAG, 0x3f1c0789));
4007 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4008 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4009 getF32Constant(DAG, 0x3f011300));
4010 } else if (LimitFloatPrecision <= 12) {
4011 // For floating-point precision of 12:
4013 // Log10ofMantissa =
4016 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4018 // error 0.00019228036, which is better than 12 bits
4019 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4020 getF32Constant(DAG, 0x3d431f31));
4021 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4022 getF32Constant(DAG, 0x3ea21fb2));
4023 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4024 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4025 getF32Constant(DAG, 0x3f6ae232));
4026 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4027 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4028 getF32Constant(DAG, 0x3f25f7c3));
4029 } else { // LimitFloatPrecision <= 18
4030 // For floating-point precision of 18:
4032 // Log10ofMantissa =
4037 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4039 // error 0.0000037995730, which is better than 18 bits
4040 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4041 getF32Constant(DAG, 0x3c5d51ce));
4042 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4043 getF32Constant(DAG, 0x3e00685a));
4044 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4045 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4046 getF32Constant(DAG, 0x3efb6798));
4047 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4048 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4049 getF32Constant(DAG, 0x3f88d192));
4050 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4051 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4052 getF32Constant(DAG, 0x3fc4316c));
4053 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4054 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4055 getF32Constant(DAG, 0x3f57ce70));
4058 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4061 // No special expansion.
4062 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4065 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4066 /// limited-precision mode.
4067 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4068 const TargetLowering &TLI) {
4069 if (Op.getValueType() == MVT::f32 &&
4070 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4071 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4073 // FractionalPartOfX = x - (float)IntegerPartOfX;
4074 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4075 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4077 // IntegerPartOfX <<= 23;
4078 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4079 DAG.getConstant(23, TLI.getPointerTy()));
4081 SDValue TwoToFractionalPartOfX;
4082 if (LimitFloatPrecision <= 6) {
4083 // For floating-point precision of 6:
4085 // TwoToFractionalPartOfX =
4087 // (0.735607626f + 0.252464424f * x) * x;
4089 // error 0.0144103317, which is 6 bits
4090 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4091 getF32Constant(DAG, 0x3e814304));
4092 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4093 getF32Constant(DAG, 0x3f3c50c8));
4094 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4095 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4096 getF32Constant(DAG, 0x3f7f5e7e));
4097 } else if (LimitFloatPrecision <= 12) {
4098 // For floating-point precision of 12:
4100 // TwoToFractionalPartOfX =
4103 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4105 // error 0.000107046256, which is 13 to 14 bits
4106 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4107 getF32Constant(DAG, 0x3da235e3));
4108 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4109 getF32Constant(DAG, 0x3e65b8f3));
4110 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4111 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4112 getF32Constant(DAG, 0x3f324b07));
4113 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4114 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4115 getF32Constant(DAG, 0x3f7ff8fd));
4116 } else { // LimitFloatPrecision <= 18
4117 // For floating-point precision of 18:
4119 // TwoToFractionalPartOfX =
4123 // (0.554906021e-1f +
4124 // (0.961591928e-2f +
4125 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4126 // error 2.47208000*10^(-7), which is better than 18 bits
4127 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4128 getF32Constant(DAG, 0x3924b03e));
4129 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4130 getF32Constant(DAG, 0x3ab24b87));
4131 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4132 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4133 getF32Constant(DAG, 0x3c1d8c17));
4134 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4135 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4136 getF32Constant(DAG, 0x3d634a1d));
4137 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4138 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4139 getF32Constant(DAG, 0x3e75fe14));
4140 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4141 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4142 getF32Constant(DAG, 0x3f317234));
4143 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4144 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4145 getF32Constant(DAG, 0x3f800000));
4148 // Add the exponent into the result in integer domain.
4149 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4150 TwoToFractionalPartOfX);
4151 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4152 DAG.getNode(ISD::ADD, dl, MVT::i32,
4153 t13, IntegerPartOfX));
4156 // No special expansion.
4157 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4160 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4161 /// limited-precision mode with x == 10.0f.
4162 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4163 SelectionDAG &DAG, const TargetLowering &TLI) {
4164 bool IsExp10 = false;
4165 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 &&
4166 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4167 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4169 IsExp10 = LHSC->isExactlyValue(Ten);
4174 // Put the exponent in the right bit position for later addition to the
4177 // #define LOG2OF10 3.3219281f
4178 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4179 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4180 getF32Constant(DAG, 0x40549a78));
4181 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4183 // FractionalPartOfX = x - (float)IntegerPartOfX;
4184 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4185 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4187 // IntegerPartOfX <<= 23;
4188 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4189 DAG.getConstant(23, TLI.getPointerTy()));
4191 SDValue TwoToFractionalPartOfX;
4192 if (LimitFloatPrecision <= 6) {
4193 // For floating-point precision of 6:
4195 // twoToFractionalPartOfX =
4197 // (0.735607626f + 0.252464424f * x) * x;
4199 // error 0.0144103317, which is 6 bits
4200 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4201 getF32Constant(DAG, 0x3e814304));
4202 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4203 getF32Constant(DAG, 0x3f3c50c8));
4204 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4205 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4206 getF32Constant(DAG, 0x3f7f5e7e));
4207 } else if (LimitFloatPrecision <= 12) {
4208 // For floating-point precision of 12:
4210 // TwoToFractionalPartOfX =
4213 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4215 // error 0.000107046256, which is 13 to 14 bits
4216 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4217 getF32Constant(DAG, 0x3da235e3));
4218 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4219 getF32Constant(DAG, 0x3e65b8f3));
4220 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4221 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4222 getF32Constant(DAG, 0x3f324b07));
4223 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4224 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4225 getF32Constant(DAG, 0x3f7ff8fd));
4226 } else { // LimitFloatPrecision <= 18
4227 // For floating-point precision of 18:
4229 // TwoToFractionalPartOfX =
4233 // (0.554906021e-1f +
4234 // (0.961591928e-2f +
4235 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4236 // error 2.47208000*10^(-7), which is better than 18 bits
4237 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4238 getF32Constant(DAG, 0x3924b03e));
4239 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4240 getF32Constant(DAG, 0x3ab24b87));
4241 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4242 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4243 getF32Constant(DAG, 0x3c1d8c17));
4244 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4245 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4246 getF32Constant(DAG, 0x3d634a1d));
4247 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4248 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4249 getF32Constant(DAG, 0x3e75fe14));
4250 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4251 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4252 getF32Constant(DAG, 0x3f317234));
4253 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4254 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4255 getF32Constant(DAG, 0x3f800000));
4258 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4259 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4260 DAG.getNode(ISD::ADD, dl, MVT::i32,
4261 t13, IntegerPartOfX));
4264 // No special expansion.
4265 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4269 /// ExpandPowI - Expand a llvm.powi intrinsic.
4270 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4271 SelectionDAG &DAG) {
4272 // If RHS is a constant, we can expand this out to a multiplication tree,
4273 // otherwise we end up lowering to a call to __powidf2 (for example). When
4274 // optimizing for size, we only want to do this if the expansion would produce
4275 // a small number of multiplies, otherwise we do the full expansion.
4276 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4277 // Get the exponent as a positive value.
4278 unsigned Val = RHSC->getSExtValue();
4279 if ((int)Val < 0) Val = -Val;
4281 // powi(x, 0) -> 1.0
4283 return DAG.getConstantFP(1.0, LHS.getValueType());
4285 const Function *F = DAG.getMachineFunction().getFunction();
4286 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4287 Attribute::OptimizeForSize) ||
4288 // If optimizing for size, don't insert too many multiplies. This
4289 // inserts up to 5 multiplies.
4290 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4291 // We use the simple binary decomposition method to generate the multiply
4292 // sequence. There are more optimal ways to do this (for example,
4293 // powi(x,15) generates one more multiply than it should), but this has
4294 // the benefit of being both really simple and much better than a libcall.
4295 SDValue Res; // Logically starts equal to 1.0
4296 SDValue CurSquare = LHS;
4300 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4302 Res = CurSquare; // 1.0*CurSquare.
4305 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4306 CurSquare, CurSquare);
4310 // If the original was negative, invert the result, producing 1/(x*x*x).
4311 if (RHSC->getSExtValue() < 0)
4312 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4313 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4318 // Otherwise, expand to a libcall.
4319 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4322 // getTruncatedArgReg - Find underlying register used for an truncated
4324 static unsigned getTruncatedArgReg(const SDValue &N) {
4325 if (N.getOpcode() != ISD::TRUNCATE)
4328 const SDValue &Ext = N.getOperand(0);
4329 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4330 const SDValue &CFR = Ext.getOperand(0);
4331 if (CFR.getOpcode() == ISD::CopyFromReg)
4332 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4333 if (CFR.getOpcode() == ISD::TRUNCATE)
4334 return getTruncatedArgReg(CFR);
4339 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4340 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4341 /// At the end of instruction selection, they will be inserted to the entry BB.
4343 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4346 const Argument *Arg = dyn_cast<Argument>(V);
4350 MachineFunction &MF = DAG.getMachineFunction();
4351 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4352 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4354 // Ignore inlined function arguments here.
4355 DIVariable DV(Variable);
4356 if (DV.isInlinedFnArgument(MF.getFunction()))
4360 // Some arguments' frame index is recorded during argument lowering.
4361 Offset = FuncInfo.getArgumentFrameIndex(Arg);
4363 Reg = TRI->getFrameRegister(MF);
4365 if (!Reg && N.getNode()) {
4366 if (N.getOpcode() == ISD::CopyFromReg)
4367 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4369 Reg = getTruncatedArgReg(N);
4370 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4371 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4372 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4379 // Check if ValueMap has reg number.
4380 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4381 if (VMI != FuncInfo.ValueMap.end())
4385 if (!Reg && N.getNode()) {
4386 // Check if frame index is available.
4387 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4388 if (FrameIndexSDNode *FINode =
4389 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4390 Reg = TRI->getFrameRegister(MF);
4391 Offset = FINode->getIndex();
4398 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4399 TII->get(TargetOpcode::DBG_VALUE))
4400 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4401 FuncInfo.ArgDbgValues.push_back(&*MIB);
4405 // VisualStudio defines setjmp as _setjmp
4406 #if defined(_MSC_VER) && defined(setjmp) && \
4407 !defined(setjmp_undefined_for_msvc)
4408 # pragma push_macro("setjmp")
4410 # define setjmp_undefined_for_msvc
4413 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4414 /// we want to emit this as a call to a named external function, return the name
4415 /// otherwise lower it and return null.
4417 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4418 SDLoc sdl = getCurSDLoc();
4419 DebugLoc dl = getCurDebugLoc();
4422 switch (Intrinsic) {
4424 // By default, turn this into a target intrinsic node.
4425 visitTargetIntrinsic(I, Intrinsic);
4427 case Intrinsic::vastart: visitVAStart(I); return 0;
4428 case Intrinsic::vaend: visitVAEnd(I); return 0;
4429 case Intrinsic::vacopy: visitVACopy(I); return 0;
4430 case Intrinsic::returnaddress:
4431 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4432 getValue(I.getArgOperand(0))));
4434 case Intrinsic::frameaddress:
4435 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4436 getValue(I.getArgOperand(0))));
4438 case Intrinsic::setjmp:
4439 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4440 case Intrinsic::longjmp:
4441 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4442 case Intrinsic::memcpy: {
4443 // Assert for address < 256 since we support only user defined address
4445 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4447 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4449 "Unknown address space");
4450 SDValue Op1 = getValue(I.getArgOperand(0));
4451 SDValue Op2 = getValue(I.getArgOperand(1));
4452 SDValue Op3 = getValue(I.getArgOperand(2));
4453 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4455 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4456 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4457 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4458 MachinePointerInfo(I.getArgOperand(0)),
4459 MachinePointerInfo(I.getArgOperand(1))));
4462 case Intrinsic::memset: {
4463 // Assert for address < 256 since we support only user defined address
4465 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4467 "Unknown address space");
4468 SDValue Op1 = getValue(I.getArgOperand(0));
4469 SDValue Op2 = getValue(I.getArgOperand(1));
4470 SDValue Op3 = getValue(I.getArgOperand(2));
4471 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4473 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4474 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4475 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4476 MachinePointerInfo(I.getArgOperand(0))));
4479 case Intrinsic::memmove: {
4480 // Assert for address < 256 since we support only user defined address
4482 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4484 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4486 "Unknown address space");
4487 SDValue Op1 = getValue(I.getArgOperand(0));
4488 SDValue Op2 = getValue(I.getArgOperand(1));
4489 SDValue Op3 = getValue(I.getArgOperand(2));
4490 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4492 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4493 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4494 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4495 MachinePointerInfo(I.getArgOperand(0)),
4496 MachinePointerInfo(I.getArgOperand(1))));
4499 case Intrinsic::dbg_declare: {
4500 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4501 MDNode *Variable = DI.getVariable();
4502 const Value *Address = DI.getAddress();
4503 if (!Address || !DIVariable(Variable).Verify()) {
4504 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4508 // Check if address has undef value.
4509 if (isa<UndefValue>(Address) ||
4510 (Address->use_empty() && !isa<Argument>(Address))) {
4511 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4515 SDValue &N = NodeMap[Address];
4516 if (!N.getNode() && isa<Argument>(Address))
4517 // Check unused arguments map.
4518 N = UnusedArgNodeMap[Address];
4521 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4522 Address = BCI->getOperand(0);
4523 // Parameters are handled specially.
4525 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4526 isa<Argument>(Address));
4528 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4530 if (isParameter && !AI) {
4531 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4533 // Byval parameter. We have a frame index at this point.
4534 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4535 0, dl, SDNodeOrder);
4537 // Address is an argument, so try to emit its dbg value using
4538 // virtual register info from the FuncInfo.ValueMap.
4539 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4543 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4544 0, dl, SDNodeOrder);
4546 // Can't do anything with other non-AI cases yet.
4547 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4548 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4549 DEBUG(Address->dump());
4552 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4554 // If Address is an argument then try to emit its dbg value using
4555 // virtual register info from the FuncInfo.ValueMap.
4556 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4557 // If variable is pinned by a alloca in dominating bb then
4558 // use StaticAllocaMap.
4559 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4560 if (AI->getParent() != DI.getParent()) {
4561 DenseMap<const AllocaInst*, int>::iterator SI =
4562 FuncInfo.StaticAllocaMap.find(AI);
4563 if (SI != FuncInfo.StaticAllocaMap.end()) {
4564 SDV = DAG.getDbgValue(Variable, SI->second,
4565 0, dl, SDNodeOrder);
4566 DAG.AddDbgValue(SDV, 0, false);
4571 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4576 case Intrinsic::dbg_value: {
4577 const DbgValueInst &DI = cast<DbgValueInst>(I);
4578 if (!DIVariable(DI.getVariable()).Verify())
4581 MDNode *Variable = DI.getVariable();
4582 uint64_t Offset = DI.getOffset();
4583 const Value *V = DI.getValue();
4588 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4589 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4590 DAG.AddDbgValue(SDV, 0, false);
4592 // Do not use getValue() in here; we don't want to generate code at
4593 // this point if it hasn't been done yet.
4594 SDValue N = NodeMap[V];
4595 if (!N.getNode() && isa<Argument>(V))
4596 // Check unused arguments map.
4597 N = UnusedArgNodeMap[V];
4599 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4600 SDV = DAG.getDbgValue(Variable, N.getNode(),
4601 N.getResNo(), Offset, dl, SDNodeOrder);
4602 DAG.AddDbgValue(SDV, N.getNode(), false);
4604 } else if (!V->use_empty() ) {
4605 // Do not call getValue(V) yet, as we don't want to generate code.
4606 // Remember it for later.
4607 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4608 DanglingDebugInfoMap[V] = DDI;
4610 // We may expand this to cover more cases. One case where we have no
4611 // data available is an unreferenced parameter.
4612 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4616 // Build a debug info table entry.
4617 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4618 V = BCI->getOperand(0);
4619 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4620 // Don't handle byval struct arguments or VLAs, for example.
4622 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4623 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4626 DenseMap<const AllocaInst*, int>::iterator SI =
4627 FuncInfo.StaticAllocaMap.find(AI);
4628 if (SI == FuncInfo.StaticAllocaMap.end())
4630 int FI = SI->second;
4632 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4633 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4634 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4638 case Intrinsic::eh_typeid_for: {
4639 // Find the type id for the given typeinfo.
4640 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4641 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4642 Res = DAG.getConstant(TypeID, MVT::i32);
4647 case Intrinsic::eh_return_i32:
4648 case Intrinsic::eh_return_i64:
4649 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4650 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4653 getValue(I.getArgOperand(0)),
4654 getValue(I.getArgOperand(1))));
4656 case Intrinsic::eh_unwind_init:
4657 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4659 case Intrinsic::eh_dwarf_cfa: {
4660 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4661 TLI.getPointerTy());
4662 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4664 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4665 TLI.getPointerTy()),
4667 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
4669 DAG.getConstant(0, TLI.getPointerTy()));
4670 setValue(&I, DAG.getNode(ISD::ADD, sdl, TLI.getPointerTy(),
4674 case Intrinsic::eh_sjlj_callsite: {
4675 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4676 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4677 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4678 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4680 MMI.setCurrentCallSite(CI->getZExtValue());
4683 case Intrinsic::eh_sjlj_functioncontext: {
4684 // Get and store the index of the function context.
4685 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4687 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4688 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4689 MFI->setFunctionContextIndex(FI);
4692 case Intrinsic::eh_sjlj_setjmp: {
4695 Ops[1] = getValue(I.getArgOperand(0));
4696 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4697 DAG.getVTList(MVT::i32, MVT::Other),
4699 setValue(&I, Op.getValue(0));
4700 DAG.setRoot(Op.getValue(1));
4703 case Intrinsic::eh_sjlj_longjmp: {
4704 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4705 getRoot(), getValue(I.getArgOperand(0))));
4709 case Intrinsic::x86_mmx_pslli_w:
4710 case Intrinsic::x86_mmx_pslli_d:
4711 case Intrinsic::x86_mmx_pslli_q:
4712 case Intrinsic::x86_mmx_psrli_w:
4713 case Intrinsic::x86_mmx_psrli_d:
4714 case Intrinsic::x86_mmx_psrli_q:
4715 case Intrinsic::x86_mmx_psrai_w:
4716 case Intrinsic::x86_mmx_psrai_d: {
4717 SDValue ShAmt = getValue(I.getArgOperand(1));
4718 if (isa<ConstantSDNode>(ShAmt)) {
4719 visitTargetIntrinsic(I, Intrinsic);
4722 unsigned NewIntrinsic = 0;
4723 EVT ShAmtVT = MVT::v2i32;
4724 switch (Intrinsic) {
4725 case Intrinsic::x86_mmx_pslli_w:
4726 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4728 case Intrinsic::x86_mmx_pslli_d:
4729 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4731 case Intrinsic::x86_mmx_pslli_q:
4732 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4734 case Intrinsic::x86_mmx_psrli_w:
4735 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4737 case Intrinsic::x86_mmx_psrli_d:
4738 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4740 case Intrinsic::x86_mmx_psrli_q:
4741 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4743 case Intrinsic::x86_mmx_psrai_w:
4744 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4746 case Intrinsic::x86_mmx_psrai_d:
4747 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4749 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4752 // The vector shift intrinsics with scalars uses 32b shift amounts but
4753 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4755 // We must do this early because v2i32 is not a legal type.
4758 ShOps[1] = DAG.getConstant(0, MVT::i32);
4759 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2);
4760 EVT DestVT = TLI.getValueType(I.getType());
4761 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4762 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4763 DAG.getConstant(NewIntrinsic, MVT::i32),
4764 getValue(I.getArgOperand(0)), ShAmt);
4768 case Intrinsic::x86_avx_vinsertf128_pd_256:
4769 case Intrinsic::x86_avx_vinsertf128_ps_256:
4770 case Intrinsic::x86_avx_vinsertf128_si_256:
4771 case Intrinsic::x86_avx2_vinserti128: {
4772 EVT DestVT = TLI.getValueType(I.getType());
4773 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
4774 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4775 ElVT.getVectorNumElements();
4776 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
4777 getValue(I.getArgOperand(0)),
4778 getValue(I.getArgOperand(1)),
4779 DAG.getIntPtrConstant(Idx));
4783 case Intrinsic::x86_avx_vextractf128_pd_256:
4784 case Intrinsic::x86_avx_vextractf128_ps_256:
4785 case Intrinsic::x86_avx_vextractf128_si_256:
4786 case Intrinsic::x86_avx2_vextracti128: {
4787 EVT DestVT = TLI.getValueType(I.getType());
4788 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
4789 DestVT.getVectorNumElements();
4790 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
4791 getValue(I.getArgOperand(0)),
4792 DAG.getIntPtrConstant(Idx));
4796 case Intrinsic::convertff:
4797 case Intrinsic::convertfsi:
4798 case Intrinsic::convertfui:
4799 case Intrinsic::convertsif:
4800 case Intrinsic::convertuif:
4801 case Intrinsic::convertss:
4802 case Intrinsic::convertsu:
4803 case Intrinsic::convertus:
4804 case Intrinsic::convertuu: {
4805 ISD::CvtCode Code = ISD::CVT_INVALID;
4806 switch (Intrinsic) {
4807 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4808 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4809 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4810 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4811 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4812 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4813 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4814 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4815 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4816 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4818 EVT DestVT = TLI.getValueType(I.getType());
4819 const Value *Op1 = I.getArgOperand(0);
4820 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4821 DAG.getValueType(DestVT),
4822 DAG.getValueType(getValue(Op1).getValueType()),
4823 getValue(I.getArgOperand(1)),
4824 getValue(I.getArgOperand(2)),
4829 case Intrinsic::powi:
4830 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4831 getValue(I.getArgOperand(1)), DAG));
4833 case Intrinsic::log:
4834 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4836 case Intrinsic::log2:
4837 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4839 case Intrinsic::log10:
4840 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4842 case Intrinsic::exp:
4843 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4845 case Intrinsic::exp2:
4846 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4848 case Intrinsic::pow:
4849 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4850 getValue(I.getArgOperand(1)), DAG, TLI));
4852 case Intrinsic::sqrt:
4853 case Intrinsic::fabs:
4854 case Intrinsic::sin:
4855 case Intrinsic::cos:
4856 case Intrinsic::floor:
4857 case Intrinsic::ceil:
4858 case Intrinsic::trunc:
4859 case Intrinsic::rint:
4860 case Intrinsic::nearbyint: {
4862 switch (Intrinsic) {
4863 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4864 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4865 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4866 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4867 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4868 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4869 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4870 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4871 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4872 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4875 setValue(&I, DAG.getNode(Opcode, sdl,
4876 getValue(I.getArgOperand(0)).getValueType(),
4877 getValue(I.getArgOperand(0))));
4880 case Intrinsic::fma:
4881 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4882 getValue(I.getArgOperand(0)).getValueType(),
4883 getValue(I.getArgOperand(0)),
4884 getValue(I.getArgOperand(1)),
4885 getValue(I.getArgOperand(2))));
4887 case Intrinsic::fmuladd: {
4888 EVT VT = TLI.getValueType(I.getType());
4889 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4890 TLI.isFMAFasterThanMulAndAdd(VT)){
4891 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4892 getValue(I.getArgOperand(0)).getValueType(),
4893 getValue(I.getArgOperand(0)),
4894 getValue(I.getArgOperand(1)),
4895 getValue(I.getArgOperand(2))));
4897 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4898 getValue(I.getArgOperand(0)).getValueType(),
4899 getValue(I.getArgOperand(0)),
4900 getValue(I.getArgOperand(1)));
4901 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4902 getValue(I.getArgOperand(0)).getValueType(),
4904 getValue(I.getArgOperand(2)));
4909 case Intrinsic::convert_to_fp16:
4910 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl,
4911 MVT::i16, getValue(I.getArgOperand(0))));
4913 case Intrinsic::convert_from_fp16:
4914 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl,
4915 MVT::f32, getValue(I.getArgOperand(0))));
4917 case Intrinsic::pcmarker: {
4918 SDValue Tmp = getValue(I.getArgOperand(0));
4919 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4922 case Intrinsic::readcyclecounter: {
4923 SDValue Op = getRoot();
4924 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4925 DAG.getVTList(MVT::i64, MVT::Other),
4928 DAG.setRoot(Res.getValue(1));
4931 case Intrinsic::bswap:
4932 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4933 getValue(I.getArgOperand(0)).getValueType(),
4934 getValue(I.getArgOperand(0))));
4936 case Intrinsic::cttz: {
4937 SDValue Arg = getValue(I.getArgOperand(0));
4938 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4939 EVT Ty = Arg.getValueType();
4940 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4944 case Intrinsic::ctlz: {
4945 SDValue Arg = getValue(I.getArgOperand(0));
4946 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4947 EVT Ty = Arg.getValueType();
4948 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4952 case Intrinsic::ctpop: {
4953 SDValue Arg = getValue(I.getArgOperand(0));
4954 EVT Ty = Arg.getValueType();
4955 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4958 case Intrinsic::stacksave: {
4959 SDValue Op = getRoot();
4960 Res = DAG.getNode(ISD::STACKSAVE, sdl,
4961 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4963 DAG.setRoot(Res.getValue(1));
4966 case Intrinsic::stackrestore: {
4967 Res = getValue(I.getArgOperand(0));
4968 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4971 case Intrinsic::stackprotector: {
4972 // Emit code into the DAG to store the stack guard onto the stack.
4973 MachineFunction &MF = DAG.getMachineFunction();
4974 MachineFrameInfo *MFI = MF.getFrameInfo();
4975 EVT PtrTy = TLI.getPointerTy();
4977 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4978 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4980 int FI = FuncInfo.StaticAllocaMap[Slot];
4981 MFI->setStackProtectorIndex(FI);
4983 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4985 // Store the stack protector onto the stack.
4986 Res = DAG.getStore(getRoot(), sdl, Src, FIN,
4987 MachinePointerInfo::getFixedStack(FI),
4993 case Intrinsic::objectsize: {
4994 // If we don't know by now, we're never going to know.
4995 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4997 assert(CI && "Non-constant type in __builtin_object_size?");
4999 SDValue Arg = getValue(I.getCalledValue());
5000 EVT Ty = Arg.getValueType();
5003 Res = DAG.getConstant(-1ULL, Ty);
5005 Res = DAG.getConstant(0, Ty);
5010 case Intrinsic::annotation:
5011 case Intrinsic::ptr_annotation:
5012 // Drop the intrinsic, but forward the value
5013 setValue(&I, getValue(I.getOperand(0)));
5015 case Intrinsic::var_annotation:
5016 // Discard annotate attributes
5019 case Intrinsic::init_trampoline: {
5020 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5024 Ops[1] = getValue(I.getArgOperand(0));
5025 Ops[2] = getValue(I.getArgOperand(1));
5026 Ops[3] = getValue(I.getArgOperand(2));
5027 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5028 Ops[5] = DAG.getSrcValue(F);
5030 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6);
5035 case Intrinsic::adjust_trampoline: {
5036 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5038 getValue(I.getArgOperand(0))));
5041 case Intrinsic::gcroot:
5043 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5044 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5046 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5047 GFI->addStackRoot(FI->getIndex(), TypeMap);
5050 case Intrinsic::gcread:
5051 case Intrinsic::gcwrite:
5052 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5053 case Intrinsic::flt_rounds:
5054 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5057 case Intrinsic::expect: {
5058 // Just replace __builtin_expect(exp, c) with EXP.
5059 setValue(&I, getValue(I.getArgOperand(0)));
5063 case Intrinsic::debugtrap:
5064 case Intrinsic::trap: {
5065 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5066 if (TrapFuncName.empty()) {
5067 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5068 ISD::TRAP : ISD::DEBUGTRAP;
5069 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5072 TargetLowering::ArgListTy Args;
5074 CallLoweringInfo CLI(getRoot(), I.getType(),
5075 false, false, false, false, 0, CallingConv::C,
5076 /*isTailCall=*/false,
5077 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5078 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5080 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5081 DAG.setRoot(Result.second);
5085 case Intrinsic::uadd_with_overflow:
5086 case Intrinsic::sadd_with_overflow:
5087 case Intrinsic::usub_with_overflow:
5088 case Intrinsic::ssub_with_overflow:
5089 case Intrinsic::umul_with_overflow:
5090 case Intrinsic::smul_with_overflow: {
5092 switch (Intrinsic) {
5093 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5094 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5095 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5096 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5097 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5098 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5099 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5101 SDValue Op1 = getValue(I.getArgOperand(0));
5102 SDValue Op2 = getValue(I.getArgOperand(1));
5104 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5105 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5108 case Intrinsic::prefetch: {
5110 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5112 Ops[1] = getValue(I.getArgOperand(0));
5113 Ops[2] = getValue(I.getArgOperand(1));
5114 Ops[3] = getValue(I.getArgOperand(2));
5115 Ops[4] = getValue(I.getArgOperand(3));
5116 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5117 DAG.getVTList(MVT::Other),
5119 EVT::getIntegerVT(*Context, 8),
5120 MachinePointerInfo(I.getArgOperand(0)),
5122 false, /* volatile */
5124 rw==1)); /* write */
5127 case Intrinsic::lifetime_start:
5128 case Intrinsic::lifetime_end: {
5129 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5130 // Stack coloring is not enabled in O0, discard region information.
5131 if (TM.getOptLevel() == CodeGenOpt::None)
5134 SmallVector<Value *, 4> Allocas;
5135 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD);
5137 for (SmallVector<Value*, 4>::iterator Object = Allocas.begin(),
5138 E = Allocas.end(); Object != E; ++Object) {
5139 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5141 // Could not find an Alloca.
5142 if (!LifetimeObject)
5145 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5149 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5150 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5152 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2);
5157 case Intrinsic::invariant_start:
5158 // Discard region information.
5159 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5161 case Intrinsic::invariant_end:
5162 // Discard region information.
5164 case Intrinsic::donothing:
5170 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5172 MachineBasicBlock *LandingPad) {
5173 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5174 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5175 Type *RetTy = FTy->getReturnType();
5176 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5177 MCSymbol *BeginLabel = 0;
5179 TargetLowering::ArgListTy Args;
5180 TargetLowering::ArgListEntry Entry;
5181 Args.reserve(CS.arg_size());
5183 // Check whether the function can return without sret-demotion.
5184 SmallVector<ISD::OutputArg, 4> Outs;
5185 GetReturnInfo(RetTy, CS.getAttributes(), Outs, TLI);
5187 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5188 DAG.getMachineFunction(),
5189 FTy->isVarArg(), Outs,
5192 SDValue DemoteStackSlot;
5193 int DemoteStackIdx = -100;
5195 if (!CanLowerReturn) {
5196 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(
5197 FTy->getReturnType());
5198 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(
5199 FTy->getReturnType());
5200 MachineFunction &MF = DAG.getMachineFunction();
5201 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5202 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5204 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5205 Entry.Node = DemoteStackSlot;
5206 Entry.Ty = StackSlotPtrType;
5207 Entry.isSExt = false;
5208 Entry.isZExt = false;
5209 Entry.isInReg = false;
5210 Entry.isSRet = true;
5211 Entry.isNest = false;
5212 Entry.isByVal = false;
5213 Entry.isReturned = false;
5214 Entry.Alignment = Align;
5215 Args.push_back(Entry);
5216 RetTy = Type::getVoidTy(FTy->getContext());
5219 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5221 const Value *V = *i;
5224 if (V->getType()->isEmptyTy())
5227 SDValue ArgNode = getValue(V);
5228 Entry.Node = ArgNode; Entry.Ty = V->getType();
5230 unsigned attrInd = i - CS.arg_begin() + 1;
5231 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5232 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5233 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5234 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5235 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5236 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5237 Entry.isReturned = CS.paramHasAttr(attrInd, Attribute::Returned);
5238 Entry.Alignment = CS.getParamAlignment(attrInd);
5239 Args.push_back(Entry);
5243 // Insert a label before the invoke call to mark the try range. This can be
5244 // used to detect deletion of the invoke via the MachineModuleInfo.
5245 BeginLabel = MMI.getContext().CreateTempSymbol();
5247 // For SjLj, keep track of which landing pads go with which invokes
5248 // so as to maintain the ordering of pads in the LSDA.
5249 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5250 if (CallSiteIndex) {
5251 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5252 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5254 // Now that the call site is handled, stop tracking it.
5255 MMI.setCurrentCallSite(0);
5258 // Both PendingLoads and PendingExports must be flushed here;
5259 // this call might not return.
5261 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5264 // Check if target-independent constraints permit a tail call here.
5265 // Target-dependent constraints are checked within TLI.LowerCallTo.
5266 if (isTailCall && !isInTailCallPosition(CS, TLI))
5270 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5272 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI);
5273 assert((isTailCall || Result.second.getNode()) &&
5274 "Non-null chain expected with non-tail call!");
5275 assert((Result.second.getNode() || !Result.first.getNode()) &&
5276 "Null value expected with tail call!");
5277 if (Result.first.getNode()) {
5278 setValue(CS.getInstruction(), Result.first);
5279 } else if (!CanLowerReturn && Result.second.getNode()) {
5280 // The instruction result is the result of loading from the
5281 // hidden sret parameter.
5282 SmallVector<EVT, 1> PVTs;
5283 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5285 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5286 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5287 EVT PtrVT = PVTs[0];
5289 SmallVector<EVT, 4> RetTys;
5290 SmallVector<uint64_t, 4> Offsets;
5291 RetTy = FTy->getReturnType();
5292 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets);
5294 unsigned NumValues = RetTys.size();
5295 SmallVector<SDValue, 4> Values(NumValues);
5296 SmallVector<SDValue, 4> Chains(NumValues);
5298 for (unsigned i = 0; i < NumValues; ++i) {
5299 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT,
5301 DAG.getConstant(Offsets[i], PtrVT));
5302 SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add,
5303 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5304 false, false, false, 1);
5306 Chains[i] = L.getValue(1);
5309 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
5310 MVT::Other, &Chains[0], NumValues);
5311 PendingLoads.push_back(Chain);
5313 setValue(CS.getInstruction(),
5314 DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
5315 DAG.getVTList(&RetTys[0], RetTys.size()),
5316 &Values[0], Values.size()));
5319 if (!Result.second.getNode()) {
5320 // As a special case, a null chain means that a tail call has been emitted and
5321 // the DAG root is already updated.
5324 DAG.setRoot(Result.second);
5328 // Insert a label at the end of the invoke call to mark the try range. This
5329 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5330 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5331 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5333 // Inform MachineModuleInfo of range.
5334 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5338 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5339 /// value is equal or not-equal to zero.
5340 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5341 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5343 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5344 if (IC->isEquality())
5345 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5346 if (C->isNullValue())
5348 // Unknown instruction.
5354 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5356 SelectionDAGBuilder &Builder) {
5358 // Check to see if this load can be trivially constant folded, e.g. if the
5359 // input is from a string literal.
5360 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5361 // Cast pointer to the type we really want to load.
5362 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5363 PointerType::getUnqual(LoadTy));
5365 if (const Constant *LoadCst =
5366 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5368 return Builder.getValue(LoadCst);
5371 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5372 // still constant memory, the input chain can be the entry node.
5374 bool ConstantMemory = false;
5376 // Do not serialize (non-volatile) loads of constant memory with anything.
5377 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5378 Root = Builder.DAG.getEntryNode();
5379 ConstantMemory = true;
5381 // Do not serialize non-volatile loads against each other.
5382 Root = Builder.DAG.getRoot();
5385 SDValue Ptr = Builder.getValue(PtrVal);
5386 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5387 Ptr, MachinePointerInfo(PtrVal),
5389 false /*nontemporal*/,
5390 false /*isinvariant*/, 1 /* align=1 */);
5392 if (!ConstantMemory)
5393 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5398 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5399 /// If so, return true and lower it, otherwise return false and it will be
5400 /// lowered like a normal call.
5401 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5402 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5403 if (I.getNumArgOperands() != 3)
5406 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5407 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5408 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5409 !I.getType()->isIntegerTy())
5412 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5414 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5415 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5416 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5417 bool ActuallyDoIt = true;
5420 switch (Size->getZExtValue()) {
5422 LoadVT = MVT::Other;
5424 ActuallyDoIt = false;
5428 LoadTy = Type::getInt16Ty(Size->getContext());
5432 LoadTy = Type::getInt32Ty(Size->getContext());
5436 LoadTy = Type::getInt64Ty(Size->getContext());
5440 LoadVT = MVT::v4i32;
5441 LoadTy = Type::getInt32Ty(Size->getContext());
5442 LoadTy = VectorType::get(LoadTy, 4);
5447 // This turns into unaligned loads. We only do this if the target natively
5448 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5449 // we'll only produce a small number of byte loads.
5451 // Require that we can find a legal MVT, and only do this if the target
5452 // supports unaligned loads of that type. Expanding into byte loads would
5454 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5455 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5456 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5457 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5458 ActuallyDoIt = false;
5462 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5463 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5465 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5467 EVT CallVT = TLI.getValueType(I.getType(), true);
5468 setValue(&I, DAG.getZExtOrTrunc(Res, getCurSDLoc(), CallVT));
5477 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5478 /// operation (as expected), translate it to an SDNode with the specified opcode
5479 /// and return true.
5480 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5482 // Sanity check that it really is a unary floating-point call.
5483 if (I.getNumArgOperands() != 1 ||
5484 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5485 I.getType() != I.getArgOperand(0)->getType() ||
5486 !I.onlyReadsMemory())
5489 SDValue Tmp = getValue(I.getArgOperand(0));
5490 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5494 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5495 // Handle inline assembly differently.
5496 if (isa<InlineAsm>(I.getCalledValue())) {
5501 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5502 ComputeUsesVAFloatArgument(I, &MMI);
5504 const char *RenameFn = 0;
5505 if (Function *F = I.getCalledFunction()) {
5506 if (F->isDeclaration()) {
5507 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5508 if (unsigned IID = II->getIntrinsicID(F)) {
5509 RenameFn = visitIntrinsicCall(I, IID);
5514 if (unsigned IID = F->getIntrinsicID()) {
5515 RenameFn = visitIntrinsicCall(I, IID);
5521 // Check for well-known libc/libm calls. If the function is internal, it
5522 // can't be a library call.
5524 if (!F->hasLocalLinkage() && F->hasName() &&
5525 LibInfo->getLibFunc(F->getName(), Func) &&
5526 LibInfo->hasOptimizedCodeGen(Func)) {
5529 case LibFunc::copysign:
5530 case LibFunc::copysignf:
5531 case LibFunc::copysignl:
5532 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5533 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5534 I.getType() == I.getArgOperand(0)->getType() &&
5535 I.getType() == I.getArgOperand(1)->getType() &&
5536 I.onlyReadsMemory()) {
5537 SDValue LHS = getValue(I.getArgOperand(0));
5538 SDValue RHS = getValue(I.getArgOperand(1));
5539 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5540 LHS.getValueType(), LHS, RHS));
5545 case LibFunc::fabsf:
5546 case LibFunc::fabsl:
5547 if (visitUnaryFloatCall(I, ISD::FABS))
5553 if (visitUnaryFloatCall(I, ISD::FSIN))
5559 if (visitUnaryFloatCall(I, ISD::FCOS))
5563 case LibFunc::sqrtf:
5564 case LibFunc::sqrtl:
5565 if (visitUnaryFloatCall(I, ISD::FSQRT))
5568 case LibFunc::floor:
5569 case LibFunc::floorf:
5570 case LibFunc::floorl:
5571 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5574 case LibFunc::nearbyint:
5575 case LibFunc::nearbyintf:
5576 case LibFunc::nearbyintl:
5577 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5581 case LibFunc::ceilf:
5582 case LibFunc::ceill:
5583 if (visitUnaryFloatCall(I, ISD::FCEIL))
5587 case LibFunc::rintf:
5588 case LibFunc::rintl:
5589 if (visitUnaryFloatCall(I, ISD::FRINT))
5592 case LibFunc::trunc:
5593 case LibFunc::truncf:
5594 case LibFunc::truncl:
5595 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5599 case LibFunc::log2f:
5600 case LibFunc::log2l:
5601 if (visitUnaryFloatCall(I, ISD::FLOG2))
5605 case LibFunc::exp2f:
5606 case LibFunc::exp2l:
5607 if (visitUnaryFloatCall(I, ISD::FEXP2))
5610 case LibFunc::memcmp:
5611 if (visitMemCmpCall(I))
5620 Callee = getValue(I.getCalledValue());
5622 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5624 // Check if we can potentially perform a tail call. More detailed checking is
5625 // be done within LowerCallTo, after more information about the call is known.
5626 LowerCallTo(&I, Callee, I.isTailCall());
5631 /// AsmOperandInfo - This contains information for each constraint that we are
5633 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5635 /// CallOperand - If this is the result output operand or a clobber
5636 /// this is null, otherwise it is the incoming operand to the CallInst.
5637 /// This gets modified as the asm is processed.
5638 SDValue CallOperand;
5640 /// AssignedRegs - If this is a register or register class operand, this
5641 /// contains the set of register corresponding to the operand.
5642 RegsForValue AssignedRegs;
5644 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5645 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5648 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5649 /// corresponds to. If there is no Value* for this operand, it returns
5651 EVT getCallOperandValEVT(LLVMContext &Context,
5652 const TargetLowering &TLI,
5653 const DataLayout *TD) const {
5654 if (CallOperandVal == 0) return MVT::Other;
5656 if (isa<BasicBlock>(CallOperandVal))
5657 return TLI.getPointerTy();
5659 llvm::Type *OpTy = CallOperandVal->getType();
5661 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5662 // If this is an indirect operand, the operand is a pointer to the
5665 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5667 report_fatal_error("Indirect operand for inline asm not a pointer!");
5668 OpTy = PtrTy->getElementType();
5671 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5672 if (StructType *STy = dyn_cast<StructType>(OpTy))
5673 if (STy->getNumElements() == 1)
5674 OpTy = STy->getElementType(0);
5676 // If OpTy is not a single value, it may be a struct/union that we
5677 // can tile with integers.
5678 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5679 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5688 OpTy = IntegerType::get(Context, BitSize);
5693 return TLI.getValueType(OpTy, true);
5697 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5699 } // end anonymous namespace
5701 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5702 /// specified operand. We prefer to assign virtual registers, to allow the
5703 /// register allocator to handle the assignment process. However, if the asm
5704 /// uses features that we can't model on machineinstrs, we have SDISel do the
5705 /// allocation. This produces generally horrible, but correct, code.
5707 /// OpInfo describes the operand.
5709 static void GetRegistersForValue(SelectionDAG &DAG,
5710 const TargetLowering &TLI,
5712 SDISelAsmOperandInfo &OpInfo) {
5713 LLVMContext &Context = *DAG.getContext();
5715 MachineFunction &MF = DAG.getMachineFunction();
5716 SmallVector<unsigned, 4> Regs;
5718 // If this is a constraint for a single physreg, or a constraint for a
5719 // register class, find it.
5720 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5721 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5722 OpInfo.ConstraintVT);
5724 unsigned NumRegs = 1;
5725 if (OpInfo.ConstraintVT != MVT::Other) {
5726 // If this is a FP input in an integer register (or visa versa) insert a bit
5727 // cast of the input value. More generally, handle any case where the input
5728 // value disagrees with the register class we plan to stick this in.
5729 if (OpInfo.Type == InlineAsm::isInput &&
5730 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5731 // Try to convert to the first EVT that the reg class contains. If the
5732 // types are identical size, use a bitcast to convert (e.g. two differing
5734 MVT RegVT = *PhysReg.second->vt_begin();
5735 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5736 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5737 RegVT, OpInfo.CallOperand);
5738 OpInfo.ConstraintVT = RegVT;
5739 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5740 // If the input is a FP value and we want it in FP registers, do a
5741 // bitcast to the corresponding integer type. This turns an f64 value
5742 // into i64, which can be passed with two i32 values on a 32-bit
5744 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5745 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5746 RegVT, OpInfo.CallOperand);
5747 OpInfo.ConstraintVT = RegVT;
5751 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5755 EVT ValueVT = OpInfo.ConstraintVT;
5757 // If this is a constraint for a specific physical register, like {r17},
5759 if (unsigned AssignedReg = PhysReg.first) {
5760 const TargetRegisterClass *RC = PhysReg.second;
5761 if (OpInfo.ConstraintVT == MVT::Other)
5762 ValueVT = *RC->vt_begin();
5764 // Get the actual register value type. This is important, because the user
5765 // may have asked for (e.g.) the AX register in i32 type. We need to
5766 // remember that AX is actually i16 to get the right extension.
5767 RegVT = *RC->vt_begin();
5769 // This is a explicit reference to a physical register.
5770 Regs.push_back(AssignedReg);
5772 // If this is an expanded reference, add the rest of the regs to Regs.
5774 TargetRegisterClass::iterator I = RC->begin();
5775 for (; *I != AssignedReg; ++I)
5776 assert(I != RC->end() && "Didn't find reg!");
5778 // Already added the first reg.
5780 for (; NumRegs; --NumRegs, ++I) {
5781 assert(I != RC->end() && "Ran out of registers to allocate!");
5786 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5790 // Otherwise, if this was a reference to an LLVM register class, create vregs
5791 // for this reference.
5792 if (const TargetRegisterClass *RC = PhysReg.second) {
5793 RegVT = *RC->vt_begin();
5794 if (OpInfo.ConstraintVT == MVT::Other)
5797 // Create the appropriate number of virtual registers.
5798 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5799 for (; NumRegs; --NumRegs)
5800 Regs.push_back(RegInfo.createVirtualRegister(RC));
5802 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5806 // Otherwise, we couldn't allocate enough registers for this.
5809 /// visitInlineAsm - Handle a call to an InlineAsm object.
5811 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5812 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5814 /// ConstraintOperands - Information about all of the constraints.
5815 SDISelAsmOperandInfoVector ConstraintOperands;
5817 TargetLowering::AsmOperandInfoVector
5818 TargetConstraints = TLI.ParseConstraints(CS);
5820 bool hasMemory = false;
5822 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5823 unsigned ResNo = 0; // ResNo - The result number of the next output.
5824 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5825 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5826 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5828 MVT OpVT = MVT::Other;
5830 // Compute the value type for each operand.
5831 switch (OpInfo.Type) {
5832 case InlineAsm::isOutput:
5833 // Indirect outputs just consume an argument.
5834 if (OpInfo.isIndirect) {
5835 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5839 // The return value of the call is this value. As such, there is no
5840 // corresponding argument.
5841 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5842 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5843 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
5845 assert(ResNo == 0 && "Asm only has one result!");
5846 OpVT = TLI.getSimpleValueType(CS.getType());
5850 case InlineAsm::isInput:
5851 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5853 case InlineAsm::isClobber:
5858 // If this is an input or an indirect output, process the call argument.
5859 // BasicBlocks are labels, currently appearing only in asm's.
5860 if (OpInfo.CallOperandVal) {
5861 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5862 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5864 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5867 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD).
5871 OpInfo.ConstraintVT = OpVT;
5873 // Indirect operand accesses access memory.
5874 if (OpInfo.isIndirect)
5877 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5878 TargetLowering::ConstraintType
5879 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5880 if (CType == TargetLowering::C_Memory) {
5888 SDValue Chain, Flag;
5890 // We won't need to flush pending loads if this asm doesn't touch
5891 // memory and is nonvolatile.
5892 if (hasMemory || IA->hasSideEffects())
5895 Chain = DAG.getRoot();
5897 // Second pass over the constraints: compute which constraint option to use
5898 // and assign registers to constraints that want a specific physreg.
5899 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5900 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5902 // If this is an output operand with a matching input operand, look up the
5903 // matching input. If their types mismatch, e.g. one is an integer, the
5904 // other is floating point, or their sizes are different, flag it as an
5906 if (OpInfo.hasMatchingInput()) {
5907 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5909 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5910 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5911 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5912 OpInfo.ConstraintVT);
5913 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5914 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
5915 Input.ConstraintVT);
5916 if ((OpInfo.ConstraintVT.isInteger() !=
5917 Input.ConstraintVT.isInteger()) ||
5918 (MatchRC.second != InputRC.second)) {
5919 report_fatal_error("Unsupported asm: input constraint"
5920 " with a matching output constraint of"
5921 " incompatible type!");
5923 Input.ConstraintVT = OpInfo.ConstraintVT;
5927 // Compute the constraint code and ConstraintType to use.
5928 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5930 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5931 OpInfo.Type == InlineAsm::isClobber)
5934 // If this is a memory input, and if the operand is not indirect, do what we
5935 // need to to provide an address for the memory input.
5936 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5937 !OpInfo.isIndirect) {
5938 assert((OpInfo.isMultipleAlternative ||
5939 (OpInfo.Type == InlineAsm::isInput)) &&
5940 "Can only indirectify direct input operands!");
5942 // Memory operands really want the address of the value. If we don't have
5943 // an indirect input, put it in the constpool if we can, otherwise spill
5944 // it to a stack slot.
5945 // TODO: This isn't quite right. We need to handle these according to
5946 // the addressing mode that the constraint wants. Also, this may take
5947 // an additional register for the computation and we don't want that
5950 // If the operand is a float, integer, or vector constant, spill to a
5951 // constant pool entry to get its address.
5952 const Value *OpVal = OpInfo.CallOperandVal;
5953 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5954 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5955 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5956 TLI.getPointerTy());
5958 // Otherwise, create a stack slot and emit a store to it before the
5960 Type *Ty = OpVal->getType();
5961 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5962 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5963 MachineFunction &MF = DAG.getMachineFunction();
5964 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5965 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5966 Chain = DAG.getStore(Chain, getCurSDLoc(),
5967 OpInfo.CallOperand, StackSlot,
5968 MachinePointerInfo::getFixedStack(SSFI),
5970 OpInfo.CallOperand = StackSlot;
5973 // There is no longer a Value* corresponding to this operand.
5974 OpInfo.CallOperandVal = 0;
5976 // It is now an indirect operand.
5977 OpInfo.isIndirect = true;
5980 // If this constraint is for a specific register, allocate it before
5982 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5983 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
5986 // Second pass - Loop over all of the operands, assigning virtual or physregs
5987 // to register class operands.
5988 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5989 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5991 // C_Register operands have already been allocated, Other/Memory don't need
5993 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5994 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
5997 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5998 std::vector<SDValue> AsmNodeOperands;
5999 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6000 AsmNodeOperands.push_back(
6001 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6002 TLI.getPointerTy()));
6004 // If we have a !srcloc metadata node associated with it, we want to attach
6005 // this to the ultimately generated inline asm machineinstr. To do this, we
6006 // pass in the third operand as this (potentially null) inline asm MDNode.
6007 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6008 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6010 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6011 // bits as operand 3.
6012 unsigned ExtraInfo = 0;
6013 if (IA->hasSideEffects())
6014 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6015 if (IA->isAlignStack())
6016 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6017 // Set the asm dialect.
6018 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6020 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6021 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6022 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6024 // Compute the constraint code and ConstraintType to use.
6025 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6027 // Ideally, we would only check against memory constraints. However, the
6028 // meaning of an other constraint can be target-specific and we can't easily
6029 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6030 // for other constriants as well.
6031 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6032 OpInfo.ConstraintType == TargetLowering::C_Other) {
6033 if (OpInfo.Type == InlineAsm::isInput)
6034 ExtraInfo |= InlineAsm::Extra_MayLoad;
6035 else if (OpInfo.Type == InlineAsm::isOutput)
6036 ExtraInfo |= InlineAsm::Extra_MayStore;
6037 else if (OpInfo.Type == InlineAsm::isClobber)
6038 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6042 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6043 TLI.getPointerTy()));
6045 // Loop over all of the inputs, copying the operand values into the
6046 // appropriate registers and processing the output regs.
6047 RegsForValue RetValRegs;
6049 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6050 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6052 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6053 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6055 switch (OpInfo.Type) {
6056 case InlineAsm::isOutput: {
6057 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6058 OpInfo.ConstraintType != TargetLowering::C_Register) {
6059 // Memory output, or 'other' output (e.g. 'X' constraint).
6060 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6062 // Add information to the INLINEASM node to know about this output.
6063 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6064 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6065 TLI.getPointerTy()));
6066 AsmNodeOperands.push_back(OpInfo.CallOperand);
6070 // Otherwise, this is a register or register class output.
6072 // Copy the output from the appropriate register. Find a register that
6074 if (OpInfo.AssignedRegs.Regs.empty()) {
6075 LLVMContext &Ctx = *DAG.getContext();
6076 Ctx.emitError(CS.getInstruction(),
6077 "couldn't allocate output register for constraint '" +
6078 Twine(OpInfo.ConstraintCode) + "'");
6082 // If this is an indirect operand, store through the pointer after the
6084 if (OpInfo.isIndirect) {
6085 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6086 OpInfo.CallOperandVal));
6088 // This is the result value of the call.
6089 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6090 // Concatenate this output onto the outputs list.
6091 RetValRegs.append(OpInfo.AssignedRegs);
6094 // Add information to the INLINEASM node to know that this register is
6096 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6097 InlineAsm::Kind_RegDefEarlyClobber :
6098 InlineAsm::Kind_RegDef,
6105 case InlineAsm::isInput: {
6106 SDValue InOperandVal = OpInfo.CallOperand;
6108 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6109 // If this is required to match an output register we have already set,
6110 // just use its register.
6111 unsigned OperandNo = OpInfo.getMatchedOperand();
6113 // Scan until we find the definition we already emitted of this operand.
6114 // When we find it, create a RegsForValue operand.
6115 unsigned CurOp = InlineAsm::Op_FirstOperand;
6116 for (; OperandNo; --OperandNo) {
6117 // Advance to the next operand.
6119 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6120 assert((InlineAsm::isRegDefKind(OpFlag) ||
6121 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6122 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6123 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6127 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6128 if (InlineAsm::isRegDefKind(OpFlag) ||
6129 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6130 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6131 if (OpInfo.isIndirect) {
6132 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6133 LLVMContext &Ctx = *DAG.getContext();
6134 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6135 " don't know how to handle tied "
6136 "indirect register inputs");
6137 report_fatal_error("Cannot handle indirect register inputs!");
6140 RegsForValue MatchedRegs;
6141 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6142 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6143 MatchedRegs.RegVTs.push_back(RegVT);
6144 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6145 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6147 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6148 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6150 LLVMContext &Ctx = *DAG.getContext();
6151 Ctx.emitError(CS.getInstruction(), "inline asm error: This value"
6152 " type register class is not natively supported!");
6153 report_fatal_error("inline asm error: This value type register "
6154 "class is not natively supported!");
6157 // Use the produced MatchedRegs object to
6158 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6159 Chain, &Flag, CS.getInstruction());
6160 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6161 true, OpInfo.getMatchedOperand(),
6162 DAG, AsmNodeOperands);
6166 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6167 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6168 "Unexpected number of operands");
6169 // Add information to the INLINEASM node to know about this input.
6170 // See InlineAsm.h isUseOperandTiedToDef.
6171 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6172 OpInfo.getMatchedOperand());
6173 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6174 TLI.getPointerTy()));
6175 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6179 // Treat indirect 'X' constraint as memory.
6180 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6182 OpInfo.ConstraintType = TargetLowering::C_Memory;
6184 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6185 std::vector<SDValue> Ops;
6186 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6189 LLVMContext &Ctx = *DAG.getContext();
6190 Ctx.emitError(CS.getInstruction(),
6191 "invalid operand for inline asm constraint '" +
6192 Twine(OpInfo.ConstraintCode) + "'");
6196 // Add information to the INLINEASM node to know about this input.
6197 unsigned ResOpType =
6198 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6199 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6200 TLI.getPointerTy()));
6201 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6205 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6206 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6207 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6208 "Memory operands expect pointer values");
6210 // Add information to the INLINEASM node to know about this input.
6211 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6212 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6213 TLI.getPointerTy()));
6214 AsmNodeOperands.push_back(InOperandVal);
6218 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6219 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6220 "Unknown constraint type!");
6222 // TODO: Support this.
6223 if (OpInfo.isIndirect) {
6224 LLVMContext &Ctx = *DAG.getContext();
6225 Ctx.emitError(CS.getInstruction(),
6226 "Don't know how to handle indirect register inputs yet "
6227 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'");
6231 // Copy the input into the appropriate registers.
6232 if (OpInfo.AssignedRegs.Regs.empty()) {
6233 LLVMContext &Ctx = *DAG.getContext();
6234 Ctx.emitError(CS.getInstruction(),
6235 "couldn't allocate input reg for constraint '" +
6236 Twine(OpInfo.ConstraintCode) + "'");
6240 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6241 Chain, &Flag, CS.getInstruction());
6243 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6244 DAG, AsmNodeOperands);
6247 case InlineAsm::isClobber: {
6248 // Add the clobbered value to the operand list, so that the register
6249 // allocator is aware that the physreg got clobbered.
6250 if (!OpInfo.AssignedRegs.Regs.empty())
6251 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6259 // Finish up input operands. Set the input chain and add the flag last.
6260 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6261 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6263 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6264 DAG.getVTList(MVT::Other, MVT::Glue),
6265 &AsmNodeOperands[0], AsmNodeOperands.size());
6266 Flag = Chain.getValue(1);
6268 // If this asm returns a register value, copy the result from that register
6269 // and set it as the value of the call.
6270 if (!RetValRegs.Regs.empty()) {
6271 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6272 Chain, &Flag, CS.getInstruction());
6274 // FIXME: Why don't we do this for inline asms with MRVs?
6275 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6276 EVT ResultType = TLI.getValueType(CS.getType());
6278 // If any of the results of the inline asm is a vector, it may have the
6279 // wrong width/num elts. This can happen for register classes that can
6280 // contain multiple different value types. The preg or vreg allocated may
6281 // not have the same VT as was expected. Convert it to the right type
6282 // with bit_convert.
6283 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6284 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6287 } else if (ResultType != Val.getValueType() &&
6288 ResultType.isInteger() && Val.getValueType().isInteger()) {
6289 // If a result value was tied to an input value, the computed result may
6290 // have a wider width than the expected result. Extract the relevant
6292 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6295 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6298 setValue(CS.getInstruction(), Val);
6299 // Don't need to use this as a chain in this case.
6300 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6304 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6306 // Process indirect outputs, first output all of the flagged copies out of
6308 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6309 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6310 const Value *Ptr = IndirectStoresToEmit[i].second;
6311 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6313 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6316 // Emit the non-flagged stores from the physregs.
6317 SmallVector<SDValue, 8> OutChains;
6318 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6319 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6320 StoresToEmit[i].first,
6321 getValue(StoresToEmit[i].second),
6322 MachinePointerInfo(StoresToEmit[i].second),
6324 OutChains.push_back(Val);
6327 if (!OutChains.empty())
6328 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
6329 &OutChains[0], OutChains.size());
6334 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6335 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6336 MVT::Other, getRoot(),
6337 getValue(I.getArgOperand(0)),
6338 DAG.getSrcValue(I.getArgOperand(0))));
6341 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6342 const DataLayout &TD = *TLI.getDataLayout();
6343 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6344 getRoot(), getValue(I.getOperand(0)),
6345 DAG.getSrcValue(I.getOperand(0)),
6346 TD.getABITypeAlignment(I.getType()));
6348 DAG.setRoot(V.getValue(1));
6351 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6352 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6353 MVT::Other, getRoot(),
6354 getValue(I.getArgOperand(0)),
6355 DAG.getSrcValue(I.getArgOperand(0))));
6358 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6359 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6360 MVT::Other, getRoot(),
6361 getValue(I.getArgOperand(0)),
6362 getValue(I.getArgOperand(1)),
6363 DAG.getSrcValue(I.getArgOperand(0)),
6364 DAG.getSrcValue(I.getArgOperand(1))));
6367 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6368 /// implementation, which just calls LowerCall.
6369 /// FIXME: When all targets are
6370 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6371 std::pair<SDValue, SDValue>
6372 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6373 // Handle the incoming return values from the call.
6375 SmallVector<EVT, 4> RetTys;
6376 ComputeValueVTs(*this, CLI.RetTy, RetTys);
6377 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6379 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6380 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6381 for (unsigned i = 0; i != NumRegs; ++i) {
6382 ISD::InputArg MyFlags;
6383 MyFlags.VT = RegisterVT;
6384 MyFlags.Used = CLI.IsReturnValueUsed;
6386 MyFlags.Flags.setSExt();
6388 MyFlags.Flags.setZExt();
6390 MyFlags.Flags.setInReg();
6391 CLI.Ins.push_back(MyFlags);
6395 // Handle all of the outgoing arguments.
6397 CLI.OutVals.clear();
6398 ArgListTy &Args = CLI.Args;
6399 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6400 SmallVector<EVT, 4> ValueVTs;
6401 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6402 for (unsigned Value = 0, NumValues = ValueVTs.size();
6403 Value != NumValues; ++Value) {
6404 EVT VT = ValueVTs[Value];
6405 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6406 SDValue Op = SDValue(Args[i].Node.getNode(),
6407 Args[i].Node.getResNo() + Value);
6408 ISD::ArgFlagsTy Flags;
6409 unsigned OriginalAlignment =
6410 getDataLayout()->getABITypeAlignment(ArgTy);
6416 if (Args[i].isInReg)
6420 if (Args[i].isByVal) {
6422 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6423 Type *ElementTy = Ty->getElementType();
6424 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6425 // For ByVal, alignment should come from FE. BE will guess if this
6426 // info is not there but there are cases it cannot get right.
6427 unsigned FrameAlign;
6428 if (Args[i].Alignment)
6429 FrameAlign = Args[i].Alignment;
6431 FrameAlign = getByValTypeAlignment(ElementTy);
6432 Flags.setByValAlign(FrameAlign);
6436 Flags.setOrigAlign(OriginalAlignment);
6438 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6439 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6440 SmallVector<SDValue, 4> Parts(NumParts);
6441 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6444 ExtendKind = ISD::SIGN_EXTEND;
6445 else if (Args[i].isZExt)
6446 ExtendKind = ISD::ZERO_EXTEND;
6448 // Conservatively only handle 'returned' on non-vectors for now
6449 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6450 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6451 "unexpected use of 'returned'");
6452 // Before passing 'returned' to the target lowering code, ensure that
6453 // either the register MVT and the actual EVT are the same size or that
6454 // the return value and argument are extended in the same way; in these
6455 // cases it's safe to pass the argument register value unchanged as the
6456 // return register value (although it's at the target's option whether
6458 // TODO: allow code generation to take advantage of partially preserved
6459 // registers rather than clobbering the entire register when the
6460 // parameter extension method is not compatible with the return
6462 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6463 (ExtendKind != ISD::ANY_EXTEND &&
6464 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6465 Flags.setReturned();
6468 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
6469 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind);
6471 for (unsigned j = 0; j != NumParts; ++j) {
6472 // if it isn't first piece, alignment must be 1
6473 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6474 i < CLI.NumFixedArgs,
6475 i, j*Parts[j].getValueType().getStoreSize());
6476 if (NumParts > 1 && j == 0)
6477 MyFlags.Flags.setSplit();
6479 MyFlags.Flags.setOrigAlign(1);
6481 CLI.Outs.push_back(MyFlags);
6482 CLI.OutVals.push_back(Parts[j]);
6487 SmallVector<SDValue, 4> InVals;
6488 CLI.Chain = LowerCall(CLI, InVals);
6490 // Verify that the target's LowerCall behaved as expected.
6491 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6492 "LowerCall didn't return a valid chain!");
6493 assert((!CLI.IsTailCall || InVals.empty()) &&
6494 "LowerCall emitted a return value for a tail call!");
6495 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6496 "LowerCall didn't emit the correct number of values!");
6498 // For a tail call, the return value is merely live-out and there aren't
6499 // any nodes in the DAG representing it. Return a special value to
6500 // indicate that a tail call has been emitted and no more Instructions
6501 // should be processed in the current block.
6502 if (CLI.IsTailCall) {
6503 CLI.DAG.setRoot(CLI.Chain);
6504 return std::make_pair(SDValue(), SDValue());
6507 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6508 assert(InVals[i].getNode() &&
6509 "LowerCall emitted a null value!");
6510 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6511 "LowerCall emitted a value with the wrong type!");
6514 // Collect the legal value parts into potentially illegal values
6515 // that correspond to the original function's return values.
6516 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6518 AssertOp = ISD::AssertSext;
6519 else if (CLI.RetZExt)
6520 AssertOp = ISD::AssertZext;
6521 SmallVector<SDValue, 4> ReturnValues;
6522 unsigned CurReg = 0;
6523 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6525 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6526 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6528 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6529 NumRegs, RegisterVT, VT, NULL,
6534 // For a function returning void, there is no return value. We can't create
6535 // such a node, so we just return a null return value in that case. In
6536 // that case, nothing will actually look at the value.
6537 if (ReturnValues.empty())
6538 return std::make_pair(SDValue(), CLI.Chain);
6540 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6541 CLI.DAG.getVTList(&RetTys[0], RetTys.size()),
6542 &ReturnValues[0], ReturnValues.size());
6543 return std::make_pair(Res, CLI.Chain);
6546 void TargetLowering::LowerOperationWrapper(SDNode *N,
6547 SmallVectorImpl<SDValue> &Results,
6548 SelectionDAG &DAG) const {
6549 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6551 Results.push_back(Res);
6554 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6555 llvm_unreachable("LowerOperation not implemented for this target!");
6559 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6560 SDValue Op = getNonRegisterValue(V);
6561 assert((Op.getOpcode() != ISD::CopyFromReg ||
6562 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6563 "Copy from a reg to the same reg!");
6564 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6566 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6567 SDValue Chain = DAG.getEntryNode();
6568 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, 0, V);
6569 PendingExports.push_back(Chain);
6572 #include "llvm/CodeGen/SelectionDAGISel.h"
6574 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6575 /// entry block, return true. This includes arguments used by switches, since
6576 /// the switch may expand into multiple basic blocks.
6577 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6578 // With FastISel active, we may be splitting blocks, so force creation
6579 // of virtual registers for all non-dead arguments.
6581 return A->use_empty();
6583 const BasicBlock *Entry = A->getParent()->begin();
6584 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6586 const User *U = *UI;
6587 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6588 return false; // Use not in entry block.
6593 void SelectionDAGISel::LowerArguments(const Function &F) {
6594 SelectionDAG &DAG = SDB->DAG;
6595 SDLoc dl = SDB->getCurSDLoc();
6596 const DataLayout *TD = TLI.getDataLayout();
6597 SmallVector<ISD::InputArg, 16> Ins;
6599 if (!FuncInfo->CanLowerReturn) {
6600 // Put in an sret pointer parameter before all the other parameters.
6601 SmallVector<EVT, 1> ValueVTs;
6602 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6604 // NOTE: Assuming that a pointer will never break down to more than one VT
6606 ISD::ArgFlagsTy Flags;
6608 MVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6609 ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0);
6610 Ins.push_back(RetArg);
6613 // Set up the incoming argument description vector.
6615 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6616 I != E; ++I, ++Idx) {
6617 SmallVector<EVT, 4> ValueVTs;
6618 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6619 bool isArgValueUsed = !I->use_empty();
6620 for (unsigned Value = 0, NumValues = ValueVTs.size();
6621 Value != NumValues; ++Value) {
6622 EVT VT = ValueVTs[Value];
6623 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6624 ISD::ArgFlagsTy Flags;
6625 unsigned OriginalAlignment =
6626 TD->getABITypeAlignment(ArgTy);
6628 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
6630 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
6632 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
6634 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
6636 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal)) {
6638 PointerType *Ty = cast<PointerType>(I->getType());
6639 Type *ElementTy = Ty->getElementType();
6640 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6641 // For ByVal, alignment should be passed from FE. BE will guess if
6642 // this info is not there but there are cases it cannot get right.
6643 unsigned FrameAlign;
6644 if (F.getParamAlignment(Idx))
6645 FrameAlign = F.getParamAlignment(Idx);
6647 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6648 Flags.setByValAlign(FrameAlign);
6650 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
6652 Flags.setOrigAlign(OriginalAlignment);
6654 MVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6655 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6656 for (unsigned i = 0; i != NumRegs; ++i) {
6657 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed,
6658 Idx-1, i*RegisterVT.getStoreSize());
6659 if (NumRegs > 1 && i == 0)
6660 MyFlags.Flags.setSplit();
6661 // if it isn't first piece, alignment must be 1
6663 MyFlags.Flags.setOrigAlign(1);
6664 Ins.push_back(MyFlags);
6669 // Call the target to set up the argument values.
6670 SmallVector<SDValue, 8> InVals;
6671 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6675 // Verify that the target's LowerFormalArguments behaved as expected.
6676 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6677 "LowerFormalArguments didn't return a valid chain!");
6678 assert(InVals.size() == Ins.size() &&
6679 "LowerFormalArguments didn't emit the correct number of values!");
6681 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6682 assert(InVals[i].getNode() &&
6683 "LowerFormalArguments emitted a null value!");
6684 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6685 "LowerFormalArguments emitted a value with the wrong type!");
6689 // Update the DAG with the new chain value resulting from argument lowering.
6690 DAG.setRoot(NewRoot);
6692 // Set up the argument values.
6695 if (!FuncInfo->CanLowerReturn) {
6696 // Create a virtual register for the sret pointer, and put in a copy
6697 // from the sret argument into it.
6698 SmallVector<EVT, 1> ValueVTs;
6699 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6700 MVT VT = ValueVTs[0].getSimpleVT();
6701 MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6702 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6703 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6704 RegVT, VT, NULL, AssertOp);
6706 MachineFunction& MF = SDB->DAG.getMachineFunction();
6707 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6708 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6709 FuncInfo->DemoteRegister = SRetReg;
6710 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
6712 DAG.setRoot(NewRoot);
6714 // i indexes lowered arguments. Bump it past the hidden sret argument.
6715 // Idx indexes LLVM arguments. Don't touch it.
6719 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6721 SmallVector<SDValue, 4> ArgValues;
6722 SmallVector<EVT, 4> ValueVTs;
6723 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6724 unsigned NumValues = ValueVTs.size();
6726 // If this argument is unused then remember its value. It is used to generate
6727 // debugging information.
6728 if (I->use_empty() && NumValues) {
6729 SDB->setUnusedArgValue(I, InVals[i]);
6731 // Also remember any frame index for use in FastISel.
6732 if (FrameIndexSDNode *FI =
6733 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
6734 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6737 for (unsigned Val = 0; Val != NumValues; ++Val) {
6738 EVT VT = ValueVTs[Val];
6739 MVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6740 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6742 if (!I->use_empty()) {
6743 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6744 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
6745 AssertOp = ISD::AssertSext;
6746 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
6747 AssertOp = ISD::AssertZext;
6749 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6750 NumParts, PartVT, VT,
6757 // We don't need to do anything else for unused arguments.
6758 if (ArgValues.empty())
6761 // Note down frame index.
6762 if (FrameIndexSDNode *FI =
6763 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6764 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6766 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6767 SDB->getCurSDLoc());
6769 SDB->setValue(I, Res);
6770 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6771 if (LoadSDNode *LNode =
6772 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6773 if (FrameIndexSDNode *FI =
6774 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6775 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6778 // If this argument is live outside of the entry block, insert a copy from
6779 // wherever we got it to the vreg that other BB's will reference it as.
6780 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6781 // If we can, though, try to skip creating an unnecessary vreg.
6782 // FIXME: This isn't very clean... it would be nice to make this more
6783 // general. It's also subtly incompatible with the hacks FastISel
6785 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6786 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6787 FuncInfo->ValueMap[I] = Reg;
6791 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6792 FuncInfo->InitializeRegForValue(I);
6793 SDB->CopyToExportRegsIfNeeded(I);
6797 assert(i == InVals.size() && "Argument register count mismatch!");
6799 // Finally, if the target has anything special to do, allow it to do so.
6800 // FIXME: this should insert code into the DAG!
6801 EmitFunctionEntryCode();
6804 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6805 /// ensure constants are generated when needed. Remember the virtual registers
6806 /// that need to be added to the Machine PHI nodes as input. We cannot just
6807 /// directly add them, because expansion might result in multiple MBB's for one
6808 /// BB. As such, the start of the BB might correspond to a different MBB than
6812 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6813 const TerminatorInst *TI = LLVMBB->getTerminator();
6815 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6817 // Check successor nodes' PHI nodes that expect a constant to be available
6819 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6820 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6821 if (!isa<PHINode>(SuccBB->begin())) continue;
6822 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6824 // If this terminator has multiple identical successors (common for
6825 // switches), only handle each succ once.
6826 if (!SuccsHandled.insert(SuccMBB)) continue;
6828 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6830 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6831 // nodes and Machine PHI nodes, but the incoming operands have not been
6833 for (BasicBlock::const_iterator I = SuccBB->begin();
6834 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6835 // Ignore dead phi's.
6836 if (PN->use_empty()) continue;
6839 if (PN->getType()->isEmptyTy())
6843 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6845 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6846 unsigned &RegOut = ConstantsOut[C];
6848 RegOut = FuncInfo.CreateRegs(C->getType());
6849 CopyValueToVirtualRegister(C, RegOut);
6853 DenseMap<const Value *, unsigned>::iterator I =
6854 FuncInfo.ValueMap.find(PHIOp);
6855 if (I != FuncInfo.ValueMap.end())
6858 assert(isa<AllocaInst>(PHIOp) &&
6859 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6860 "Didn't codegen value into a register!??");
6861 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6862 CopyValueToVirtualRegister(PHIOp, Reg);
6866 // Remember that this register needs to added to the machine PHI node as
6867 // the input for this MBB.
6868 SmallVector<EVT, 4> ValueVTs;
6869 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6870 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6871 EVT VT = ValueVTs[vti];
6872 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6873 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6874 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6875 Reg += NumRegisters;
6879 ConstantsOut.clear();