1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/FastISel.h"
34 #include "llvm/CodeGen/GCStrategy.h"
35 #include "llvm/CodeGen/GCMetadata.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineInstrBuilder.h"
39 #include "llvm/CodeGen/MachineJumpTableInfo.h"
40 #include "llvm/CodeGen/MachineModuleInfo.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/PseudoSourceValue.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/Analysis/DebugInfo.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLowering.h"
51 #include "llvm/Target/TargetOptions.h"
52 #include "llvm/Support/Compiler.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
61 /// LimitFloatPrecision - Generate low-precision inline sequences for
62 /// some float libcalls (6, 8 or 12 bits).
63 static unsigned LimitFloatPrecision;
65 static cl::opt<unsigned, true>
66 LimitFPPrecision("limit-float-precision",
67 cl::desc("Generate low-precision inline sequences "
68 "for some float libcalls"),
69 cl::location(LimitFloatPrecision),
73 /// RegsForValue - This struct represents the registers (physical or virtual)
74 /// that a particular set of values is assigned, and the type information
75 /// about the value. The most common situation is to represent one value at a
76 /// time, but struct or array values are handled element-wise as multiple
77 /// values. The splitting of aggregates is performed recursively, so that we
78 /// never have aggregate-typed registers. The values at this point do not
79 /// necessarily have legal types, so each value may require one or more
80 /// registers of some legal type.
83 /// TLI - The TargetLowering object.
85 const TargetLowering *TLI;
87 /// ValueVTs - The value types of the values, which may not be legal, and
88 /// may need be promoted or synthesized from one or more registers.
90 SmallVector<EVT, 4> ValueVTs;
92 /// RegVTs - The value types of the registers. This is the same size as
93 /// ValueVTs and it records, for each value, what the type of the assigned
94 /// register or registers are. (Individual values are never synthesized
95 /// from more than one type of register.)
97 /// With virtual registers, the contents of RegVTs is redundant with TLI's
98 /// getRegisterType member function, however when with physical registers
99 /// it is necessary to have a separate record of the types.
101 SmallVector<EVT, 4> RegVTs;
103 /// Regs - This list holds the registers assigned to the values.
104 /// Each legal or promoted value requires one register, and each
105 /// expanded value requires multiple registers.
107 SmallVector<unsigned, 4> Regs;
109 RegsForValue() : TLI(0) {}
111 RegsForValue(const TargetLowering &tli,
112 const SmallVector<unsigned, 4> ®s,
113 EVT regvt, EVT valuevt)
114 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
115 RegsForValue(const TargetLowering &tli,
116 const SmallVector<unsigned, 4> ®s,
117 const SmallVector<EVT, 4> ®vts,
118 const SmallVector<EVT, 4> &valuevts)
119 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
120 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
121 unsigned Reg, const Type *Ty) : TLI(&tli) {
122 ComputeValueVTs(tli, Ty, ValueVTs);
124 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
125 EVT ValueVT = ValueVTs[Value];
126 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT);
127 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT);
128 for (unsigned i = 0; i != NumRegs; ++i)
129 Regs.push_back(Reg + i);
130 RegVTs.push_back(RegisterVT);
135 /// areValueTypesLegal - Return true if types of all the values are legal.
136 bool areValueTypesLegal() {
137 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
138 EVT RegisterVT = RegVTs[Value];
139 if (!TLI->isTypeLegal(RegisterVT))
146 /// append - Add the specified values to this one.
147 void append(const RegsForValue &RHS) {
149 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
150 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
151 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
155 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
156 /// this value and returns the result as a ValueVTs value. This uses
157 /// Chain/Flag as the input and updates them for the output Chain/Flag.
158 /// If the Flag pointer is NULL, no flag is used.
159 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
160 SDValue &Chain, SDValue *Flag) const;
162 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
163 /// specified value into the registers specified by this object. This uses
164 /// Chain/Flag as the input and updates them for the output Chain/Flag.
165 /// If the Flag pointer is NULL, no flag is used.
166 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
167 SDValue &Chain, SDValue *Flag) const;
169 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
170 /// operand list. This adds the code marker, matching input operand index
171 /// (if applicable), and includes the number of values added into it.
172 void AddInlineAsmOperands(unsigned Kind,
173 bool HasMatching, unsigned MatchingIdx,
175 std::vector<SDValue> &Ops) const;
179 /// getCopyFromParts - Create a value that contains the specified legal parts
180 /// combined into the value they represent. If the parts combine to a type
181 /// larger then ValueVT then AssertOp can be used to specify whether the extra
182 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
183 /// (ISD::AssertSext).
184 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
185 const SDValue *Parts,
186 unsigned NumParts, EVT PartVT, EVT ValueVT,
187 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
188 assert(NumParts > 0 && "No parts to assemble!");
189 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
190 SDValue Val = Parts[0];
193 // Assemble the value from multiple parts.
194 if (!ValueVT.isVector() && ValueVT.isInteger()) {
195 unsigned PartBits = PartVT.getSizeInBits();
196 unsigned ValueBits = ValueVT.getSizeInBits();
198 // Assemble the power of 2 part.
199 unsigned RoundParts = NumParts & (NumParts - 1) ?
200 1 << Log2_32(NumParts) : NumParts;
201 unsigned RoundBits = PartBits * RoundParts;
202 EVT RoundVT = RoundBits == ValueBits ?
203 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
206 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
208 if (RoundParts > 2) {
209 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts / 2,
211 Hi = getCopyFromParts(DAG, dl, Parts + RoundParts / 2,
212 RoundParts / 2, PartVT, HalfVT);
214 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
215 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
218 if (TLI.isBigEndian())
221 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
223 if (RoundParts < NumParts) {
224 // Assemble the trailing non-power-of-2 part.
225 unsigned OddParts = NumParts - RoundParts;
226 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
227 Hi = getCopyFromParts(DAG, dl,
228 Parts + RoundParts, OddParts, PartVT, OddVT);
230 // Combine the round and odd parts.
232 if (TLI.isBigEndian())
234 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
235 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
236 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
237 DAG.getConstant(Lo.getValueType().getSizeInBits(),
238 TLI.getPointerTy()));
239 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
240 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
242 } else if (ValueVT.isVector()) {
243 // Handle a multi-element vector.
244 EVT IntermediateVT, RegisterVT;
245 unsigned NumIntermediates;
247 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
248 NumIntermediates, RegisterVT);
249 assert(NumRegs == NumParts
250 && "Part count doesn't match vector breakdown!");
251 NumParts = NumRegs; // Silence a compiler warning.
252 assert(RegisterVT == PartVT
253 && "Part type doesn't match vector breakdown!");
254 assert(RegisterVT == Parts[0].getValueType() &&
255 "Part type doesn't match part!");
257 // Assemble the parts into intermediate operands.
258 SmallVector<SDValue, 8> Ops(NumIntermediates);
259 if (NumIntermediates == NumParts) {
260 // If the register was not expanded, truncate or copy the value,
262 for (unsigned i = 0; i != NumParts; ++i)
263 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
264 PartVT, IntermediateVT);
265 } else if (NumParts > 0) {
266 // If the intermediate type was expanded, build the intermediate
267 // operands from the parts.
268 assert(NumParts % NumIntermediates == 0 &&
269 "Must expand into a divisible number of parts!");
270 unsigned Factor = NumParts / NumIntermediates;
271 for (unsigned i = 0; i != NumIntermediates; ++i)
272 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
273 PartVT, IntermediateVT);
276 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
277 // intermediate operands.
278 Val = DAG.getNode(IntermediateVT.isVector() ?
279 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
280 ValueVT, &Ops[0], NumIntermediates);
281 } else if (PartVT.isFloatingPoint()) {
282 // FP split into multiple FP parts (for ppcf128)
283 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
286 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
287 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
288 if (TLI.isBigEndian())
290 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
292 // FP split into integer parts (soft fp)
293 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
294 !PartVT.isVector() && "Unexpected split");
295 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
296 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
300 // There is now one part, held in Val. Correct it to match ValueVT.
301 PartVT = Val.getValueType();
303 if (PartVT == ValueVT)
306 if (PartVT.isVector()) {
307 assert(ValueVT.isVector() && "Unknown vector conversion!");
308 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
311 if (ValueVT.isVector()) {
312 assert(ValueVT.getVectorElementType() == PartVT &&
313 ValueVT.getVectorNumElements() == 1 &&
314 "Only trivial scalar-to-vector conversions should get here!");
315 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
318 if (PartVT.isInteger() &&
319 ValueVT.isInteger()) {
320 if (ValueVT.bitsLT(PartVT)) {
321 // For a truncate, see if we have any information to
322 // indicate whether the truncated bits will always be
323 // zero or sign-extension.
324 if (AssertOp != ISD::DELETED_NODE)
325 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
326 DAG.getValueType(ValueVT));
327 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
329 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
333 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
334 if (ValueVT.bitsLT(Val.getValueType())) {
335 // FP_ROUND's are always exact here.
336 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
337 DAG.getIntPtrConstant(1));
340 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
343 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
344 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
346 llvm_unreachable("Unknown mismatch!");
350 /// getCopyToParts - Create a series of nodes that contain the specified value
351 /// split into legal parts. If the parts contain more bits than Val, then, for
352 /// integers, ExtendKind can be used to specify how to generate the extra bits.
353 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl,
354 SDValue Val, SDValue *Parts, unsigned NumParts,
356 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
357 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
358 EVT PtrVT = TLI.getPointerTy();
359 EVT ValueVT = Val.getValueType();
360 unsigned PartBits = PartVT.getSizeInBits();
361 unsigned OrigNumParts = NumParts;
362 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
367 if (!ValueVT.isVector()) {
368 if (PartVT == ValueVT) {
369 assert(NumParts == 1 && "No-op copy with multiple parts!");
374 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
375 // If the parts cover more bits than the value has, promote the value.
376 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
377 assert(NumParts == 1 && "Do not know what to promote to!");
378 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
379 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
380 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
381 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
383 llvm_unreachable("Unknown mismatch!");
385 } else if (PartBits == ValueVT.getSizeInBits()) {
386 // Different types of the same size.
387 assert(NumParts == 1 && PartVT != ValueVT);
388 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
389 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
390 // If the parts cover less bits than value has, truncate the value.
391 if (PartVT.isInteger() && ValueVT.isInteger()) {
392 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
393 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
395 llvm_unreachable("Unknown mismatch!");
399 // The value may have changed - recompute ValueVT.
400 ValueVT = Val.getValueType();
401 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
402 "Failed to tile the value with PartVT!");
405 assert(PartVT == ValueVT && "Type conversion failed!");
410 // Expand the value into multiple parts.
411 if (NumParts & (NumParts - 1)) {
412 // The number of parts is not a power of 2. Split off and copy the tail.
413 assert(PartVT.isInteger() && ValueVT.isInteger() &&
414 "Do not know what to expand to!");
415 unsigned RoundParts = 1 << Log2_32(NumParts);
416 unsigned RoundBits = RoundParts * PartBits;
417 unsigned OddParts = NumParts - RoundParts;
418 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
419 DAG.getConstant(RoundBits,
420 TLI.getPointerTy()));
421 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts,
424 if (TLI.isBigEndian())
425 // The odd parts were reversed by getCopyToParts - unreverse them.
426 std::reverse(Parts + RoundParts, Parts + NumParts);
428 NumParts = RoundParts;
429 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
430 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
433 // The number of parts is a power of 2. Repeatedly bisect the value using
435 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
436 EVT::getIntegerVT(*DAG.getContext(),
437 ValueVT.getSizeInBits()),
440 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
441 for (unsigned i = 0; i < NumParts; i += StepSize) {
442 unsigned ThisBits = StepSize * PartBits / 2;
443 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
444 SDValue &Part0 = Parts[i];
445 SDValue &Part1 = Parts[i+StepSize/2];
447 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
449 DAG.getConstant(1, PtrVT));
450 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
452 DAG.getConstant(0, PtrVT));
454 if (ThisBits == PartBits && ThisVT != PartVT) {
455 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
457 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
463 if (TLI.isBigEndian())
464 std::reverse(Parts, Parts + OrigNumParts);
471 if (PartVT != ValueVT) {
472 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
473 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
475 assert(ValueVT.getVectorElementType() == PartVT &&
476 ValueVT.getVectorNumElements() == 1 &&
477 "Only trivial vector-to-scalar conversions should get here!");
478 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
480 DAG.getConstant(0, PtrVT));
488 // Handle a multi-element vector.
489 EVT IntermediateVT, RegisterVT;
490 unsigned NumIntermediates;
491 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
492 IntermediateVT, NumIntermediates, RegisterVT);
493 unsigned NumElements = ValueVT.getVectorNumElements();
495 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
496 NumParts = NumRegs; // Silence a compiler warning.
497 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
499 // Split the vector into intermediate operands.
500 SmallVector<SDValue, 8> Ops(NumIntermediates);
501 for (unsigned i = 0; i != NumIntermediates; ++i) {
502 if (IntermediateVT.isVector())
503 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
505 DAG.getConstant(i * (NumElements / NumIntermediates),
508 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
510 DAG.getConstant(i, PtrVT));
513 // Split the intermediate operands into legal parts.
514 if (NumParts == NumIntermediates) {
515 // If the register was not expanded, promote or copy the value,
517 for (unsigned i = 0; i != NumParts; ++i)
518 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
519 } else if (NumParts > 0) {
520 // If the intermediate type was expanded, split each the value into
522 assert(NumParts % NumIntermediates == 0 &&
523 "Must expand into a divisible number of parts!");
524 unsigned Factor = NumParts / NumIntermediates;
525 for (unsigned i = 0; i != NumIntermediates; ++i)
526 getCopyToParts(DAG, dl, Ops[i], &Parts[i*Factor], Factor, PartVT);
531 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
534 TD = DAG.getTarget().getTargetData();
537 /// clear - Clear out the curret SelectionDAG and the associated
538 /// state and prepare this SelectionDAGBuilder object to be used
539 /// for a new block. This doesn't clear out information about
540 /// additional blocks that are needed to complete switch lowering
541 /// or PHI node updating; that information is cleared out as it is
543 void SelectionDAGBuilder::clear() {
545 PendingLoads.clear();
546 PendingExports.clear();
549 CurDebugLoc = DebugLoc();
553 /// getRoot - Return the current virtual root of the Selection DAG,
554 /// flushing any PendingLoad items. This must be done before emitting
555 /// a store or any other node that may need to be ordered after any
556 /// prior load instructions.
558 SDValue SelectionDAGBuilder::getRoot() {
559 if (PendingLoads.empty())
560 return DAG.getRoot();
562 if (PendingLoads.size() == 1) {
563 SDValue Root = PendingLoads[0];
565 PendingLoads.clear();
569 // Otherwise, we have to make a token factor node.
570 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
571 &PendingLoads[0], PendingLoads.size());
572 PendingLoads.clear();
577 /// getControlRoot - Similar to getRoot, but instead of flushing all the
578 /// PendingLoad items, flush all the PendingExports items. It is necessary
579 /// to do this before emitting a terminator instruction.
581 SDValue SelectionDAGBuilder::getControlRoot() {
582 SDValue Root = DAG.getRoot();
584 if (PendingExports.empty())
587 // Turn all of the CopyToReg chains into one factored node.
588 if (Root.getOpcode() != ISD::EntryToken) {
589 unsigned i = 0, e = PendingExports.size();
590 for (; i != e; ++i) {
591 assert(PendingExports[i].getNode()->getNumOperands() > 1);
592 if (PendingExports[i].getNode()->getOperand(0) == Root)
593 break; // Don't add the root if we already indirectly depend on it.
597 PendingExports.push_back(Root);
600 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
602 PendingExports.size());
603 PendingExports.clear();
608 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
609 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
610 DAG.AssignOrdering(Node, SDNodeOrder);
612 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
613 AssignOrderingToNode(Node->getOperand(I).getNode());
616 void SelectionDAGBuilder::visit(Instruction &I) {
617 visit(I.getOpcode(), I);
620 void SelectionDAGBuilder::visit(unsigned Opcode, User &I) {
621 // Note: this doesn't use InstVisitor, because it has to work with
622 // ConstantExpr's in addition to instructions.
624 default: llvm_unreachable("Unknown instruction type encountered!");
625 // Build the switch statement using the Instruction.def file.
626 #define HANDLE_INST(NUM, OPCODE, CLASS) \
627 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
628 #include "llvm/Instruction.def"
631 // Assign the ordering to the freshly created DAG nodes.
632 if (NodeMap.count(&I)) {
634 AssignOrderingToNode(getValue(&I).getNode());
638 SDValue SelectionDAGBuilder::getValue(const Value *V) {
639 SDValue &N = NodeMap[V];
640 if (N.getNode()) return N;
642 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
643 EVT VT = TLI.getValueType(V->getType(), true);
645 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
646 return N = DAG.getConstant(*CI, VT);
648 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
649 return N = DAG.getGlobalAddress(GV, VT);
651 if (isa<ConstantPointerNull>(C))
652 return N = DAG.getConstant(0, TLI.getPointerTy());
654 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
655 return N = DAG.getConstantFP(*CFP, VT);
657 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
658 return N = DAG.getUNDEF(VT);
660 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
661 visit(CE->getOpcode(), *CE);
662 SDValue N1 = NodeMap[V];
663 assert(N1.getNode() && "visit didn't populate the ValueMap!");
667 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
668 SmallVector<SDValue, 4> Constants;
669 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
671 SDNode *Val = getValue(*OI).getNode();
672 // If the operand is an empty aggregate, there are no values.
674 // Add each leaf value from the operand to the Constants list
675 // to form a flattened list of all the values.
676 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
677 Constants.push_back(SDValue(Val, i));
680 return DAG.getMergeValues(&Constants[0], Constants.size(),
684 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
685 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
686 "Unknown struct or array constant!");
688 SmallVector<EVT, 4> ValueVTs;
689 ComputeValueVTs(TLI, C->getType(), ValueVTs);
690 unsigned NumElts = ValueVTs.size();
692 return SDValue(); // empty struct
693 SmallVector<SDValue, 4> Constants(NumElts);
694 for (unsigned i = 0; i != NumElts; ++i) {
695 EVT EltVT = ValueVTs[i];
696 if (isa<UndefValue>(C))
697 Constants[i] = DAG.getUNDEF(EltVT);
698 else if (EltVT.isFloatingPoint())
699 Constants[i] = DAG.getConstantFP(0, EltVT);
701 Constants[i] = DAG.getConstant(0, EltVT);
704 return DAG.getMergeValues(&Constants[0], NumElts,
708 if (BlockAddress *BA = dyn_cast<BlockAddress>(C))
709 return DAG.getBlockAddress(BA, VT);
711 const VectorType *VecTy = cast<VectorType>(V->getType());
712 unsigned NumElements = VecTy->getNumElements();
714 // Now that we know the number and type of the elements, get that number of
715 // elements into the Ops array based on what kind of constant it is.
716 SmallVector<SDValue, 16> Ops;
717 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
718 for (unsigned i = 0; i != NumElements; ++i)
719 Ops.push_back(getValue(CP->getOperand(i)));
721 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
722 EVT EltVT = TLI.getValueType(VecTy->getElementType());
725 if (EltVT.isFloatingPoint())
726 Op = DAG.getConstantFP(0, EltVT);
728 Op = DAG.getConstant(0, EltVT);
729 Ops.assign(NumElements, Op);
732 // Create a BUILD_VECTOR node.
733 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
734 VT, &Ops[0], Ops.size());
737 // If this is a static alloca, generate it as the frameindex instead of
739 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
740 DenseMap<const AllocaInst*, int>::iterator SI =
741 FuncInfo.StaticAllocaMap.find(AI);
742 if (SI != FuncInfo.StaticAllocaMap.end())
743 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
746 unsigned InReg = FuncInfo.ValueMap[V];
747 assert(InReg && "Value not in map!");
749 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
750 SDValue Chain = DAG.getEntryNode();
751 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
754 /// Get the EVTs and ArgFlags collections that represent the legalized return
755 /// type of the given function. This does not require a DAG or a return value,
756 /// and is suitable for use before any DAGs for the function are constructed.
757 static void getReturnInfo(const Type* ReturnType,
758 Attributes attr, SmallVectorImpl<EVT> &OutVTs,
759 SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
761 SmallVectorImpl<uint64_t> *Offsets = 0) {
762 SmallVector<EVT, 4> ValueVTs;
763 ComputeValueVTs(TLI, ReturnType, ValueVTs);
764 unsigned NumValues = ValueVTs.size();
765 if (NumValues == 0) return;
768 for (unsigned j = 0, f = NumValues; j != f; ++j) {
769 EVT VT = ValueVTs[j];
770 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
772 if (attr & Attribute::SExt)
773 ExtendKind = ISD::SIGN_EXTEND;
774 else if (attr & Attribute::ZExt)
775 ExtendKind = ISD::ZERO_EXTEND;
777 // FIXME: C calling convention requires the return type to be promoted to
778 // at least 32-bit. But this is not necessary for non-C calling
779 // conventions. The frontend should mark functions whose return values
780 // require promoting with signext or zeroext attributes.
781 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
782 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
783 if (VT.bitsLT(MinVT))
787 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
788 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
789 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
790 PartVT.getTypeForEVT(ReturnType->getContext()));
792 // 'inreg' on function refers to return value
793 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
794 if (attr & Attribute::InReg)
797 // Propagate extension type if any
798 if (attr & Attribute::SExt)
800 else if (attr & Attribute::ZExt)
803 for (unsigned i = 0; i < NumParts; ++i) {
804 OutVTs.push_back(PartVT);
805 OutFlags.push_back(Flags);
808 Offsets->push_back(Offset);
815 void SelectionDAGBuilder::visitRet(ReturnInst &I) {
816 SDValue Chain = getControlRoot();
817 SmallVector<ISD::OutputArg, 8> Outs;
818 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
820 if (!FLI.CanLowerReturn) {
821 unsigned DemoteReg = FLI.DemoteRegister;
822 const Function *F = I.getParent()->getParent();
824 // Emit a store of the return value through the virtual register.
825 // Leave Outs empty so that LowerReturn won't try to load return
826 // registers the usual way.
827 SmallVector<EVT, 1> PtrValueVTs;
828 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
831 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
832 SDValue RetOp = getValue(I.getOperand(0));
834 SmallVector<EVT, 4> ValueVTs;
835 SmallVector<uint64_t, 4> Offsets;
836 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
837 unsigned NumValues = ValueVTs.size();
839 SmallVector<SDValue, 4> Chains(NumValues);
840 EVT PtrVT = PtrValueVTs[0];
841 for (unsigned i = 0; i != NumValues; ++i) {
842 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, RetPtr,
843 DAG.getConstant(Offsets[i], PtrVT));
845 DAG.getStore(Chain, getCurDebugLoc(),
846 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
847 Add, NULL, Offsets[i], false, false, 0);
850 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
851 MVT::Other, &Chains[0], NumValues);
852 } else if (I.getNumOperands() != 0) {
853 SmallVector<EVT, 4> ValueVTs;
854 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
855 unsigned NumValues = ValueVTs.size();
857 SDValue RetOp = getValue(I.getOperand(0));
858 for (unsigned j = 0, f = NumValues; j != f; ++j) {
859 EVT VT = ValueVTs[j];
861 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
863 const Function *F = I.getParent()->getParent();
864 if (F->paramHasAttr(0, Attribute::SExt))
865 ExtendKind = ISD::SIGN_EXTEND;
866 else if (F->paramHasAttr(0, Attribute::ZExt))
867 ExtendKind = ISD::ZERO_EXTEND;
869 // FIXME: C calling convention requires the return type to be promoted
870 // to at least 32-bit. But this is not necessary for non-C calling
871 // conventions. The frontend should mark functions whose return values
872 // require promoting with signext or zeroext attributes.
873 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
874 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
875 if (VT.bitsLT(MinVT))
879 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
880 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
881 SmallVector<SDValue, 4> Parts(NumParts);
882 getCopyToParts(DAG, getCurDebugLoc(),
883 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
884 &Parts[0], NumParts, PartVT, ExtendKind);
886 // 'inreg' on function refers to return value
887 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
888 if (F->paramHasAttr(0, Attribute::InReg))
891 // Propagate extension type if any
892 if (F->paramHasAttr(0, Attribute::SExt))
894 else if (F->paramHasAttr(0, Attribute::ZExt))
897 for (unsigned i = 0; i < NumParts; ++i)
898 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
903 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
904 CallingConv::ID CallConv =
905 DAG.getMachineFunction().getFunction()->getCallingConv();
906 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
907 Outs, getCurDebugLoc(), DAG);
909 // Verify that the target's LowerReturn behaved as expected.
910 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
911 "LowerReturn didn't return a valid chain!");
913 // Update the DAG with the new chain value resulting from return lowering.
917 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
918 /// created for it, emit nodes to copy the value into the virtual
920 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(Value *V) {
921 if (!V->use_empty()) {
922 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
923 if (VMI != FuncInfo.ValueMap.end())
924 CopyValueToVirtualRegister(V, VMI->second);
928 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
929 /// the current basic block, add it to ValueMap now so that we'll get a
931 void SelectionDAGBuilder::ExportFromCurrentBlock(Value *V) {
932 // No need to export constants.
933 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
936 if (FuncInfo.isExportedInst(V)) return;
938 unsigned Reg = FuncInfo.InitializeRegForValue(V);
939 CopyValueToVirtualRegister(V, Reg);
942 bool SelectionDAGBuilder::isExportableFromCurrentBlock(Value *V,
943 const BasicBlock *FromBB) {
944 // The operands of the setcc have to be in this block. We don't know
945 // how to export them from some other block.
946 if (Instruction *VI = dyn_cast<Instruction>(V)) {
947 // Can export from current BB.
948 if (VI->getParent() == FromBB)
951 // Is already exported, noop.
952 return FuncInfo.isExportedInst(V);
955 // If this is an argument, we can export it if the BB is the entry block or
956 // if it is already exported.
957 if (isa<Argument>(V)) {
958 if (FromBB == &FromBB->getParent()->getEntryBlock())
961 // Otherwise, can only export this if it is already exported.
962 return FuncInfo.isExportedInst(V);
965 // Otherwise, constants can always be exported.
969 static bool InBlock(const Value *V, const BasicBlock *BB) {
970 if (const Instruction *I = dyn_cast<Instruction>(V))
971 return I->getParent() == BB;
975 /// getFCmpCondCode - Return the ISD condition code corresponding to
976 /// the given LLVM IR floating-point condition code. This includes
977 /// consideration of global floating-point math flags.
979 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
980 ISD::CondCode FPC, FOC;
982 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
983 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
984 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
985 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
986 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
987 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
988 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
989 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
990 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
991 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
992 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
993 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
994 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
995 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
996 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
997 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
999 llvm_unreachable("Invalid FCmp predicate opcode!");
1000 FOC = FPC = ISD::SETFALSE;
1003 if (FiniteOnlyFPMath())
1009 /// getICmpCondCode - Return the ISD condition code corresponding to
1010 /// the given LLVM IR integer condition code.
1012 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1014 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1015 case ICmpInst::ICMP_NE: return ISD::SETNE;
1016 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1017 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1018 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1019 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1020 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1021 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1022 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1023 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1025 llvm_unreachable("Invalid ICmp predicate opcode!");
1030 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1031 /// This function emits a branch and is used at the leaves of an OR or an
1032 /// AND operator tree.
1035 SelectionDAGBuilder::EmitBranchForMergedCondition(Value *Cond,
1036 MachineBasicBlock *TBB,
1037 MachineBasicBlock *FBB,
1038 MachineBasicBlock *CurBB) {
1039 const BasicBlock *BB = CurBB->getBasicBlock();
1041 // If the leaf of the tree is a comparison, merge the condition into
1043 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1044 // The operands of the cmp have to be in this block. We don't know
1045 // how to export them from some other block. If this is the first block
1046 // of the sequence, no exporting is needed.
1047 if (CurBB == CurMBB ||
1048 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1049 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1050 ISD::CondCode Condition;
1051 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1052 Condition = getICmpCondCode(IC->getPredicate());
1053 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1054 Condition = getFCmpCondCode(FC->getPredicate());
1056 Condition = ISD::SETEQ; // silence warning.
1057 llvm_unreachable("Unknown compare instruction");
1060 CaseBlock CB(Condition, BOp->getOperand(0),
1061 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1062 SwitchCases.push_back(CB);
1067 // Create a CaseBlock record representing this branch.
1068 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1069 NULL, TBB, FBB, CurBB);
1070 SwitchCases.push_back(CB);
1073 /// FindMergedConditions - If Cond is an expression like
1074 void SelectionDAGBuilder::FindMergedConditions(Value *Cond,
1075 MachineBasicBlock *TBB,
1076 MachineBasicBlock *FBB,
1077 MachineBasicBlock *CurBB,
1079 // If this node is not part of the or/and tree, emit it as a branch.
1080 Instruction *BOp = dyn_cast<Instruction>(Cond);
1081 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1082 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1083 BOp->getParent() != CurBB->getBasicBlock() ||
1084 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1085 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1086 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1090 // Create TmpBB after CurBB.
1091 MachineFunction::iterator BBI = CurBB;
1092 MachineFunction &MF = DAG.getMachineFunction();
1093 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1094 CurBB->getParent()->insert(++BBI, TmpBB);
1096 if (Opc == Instruction::Or) {
1097 // Codegen X | Y as:
1105 // Emit the LHS condition.
1106 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1108 // Emit the RHS condition into TmpBB.
1109 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1111 assert(Opc == Instruction::And && "Unknown merge op!");
1112 // Codegen X & Y as:
1119 // This requires creation of TmpBB after CurBB.
1121 // Emit the LHS condition.
1122 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1124 // Emit the RHS condition into TmpBB.
1125 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1129 /// If the set of cases should be emitted as a series of branches, return true.
1130 /// If we should emit this as a bunch of and/or'd together conditions, return
1133 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1134 if (Cases.size() != 2) return true;
1136 // If this is two comparisons of the same values or'd or and'd together, they
1137 // will get folded into a single comparison, so don't emit two blocks.
1138 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1139 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1140 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1141 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1145 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1146 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1147 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1148 Cases[0].CC == Cases[1].CC &&
1149 isa<Constant>(Cases[0].CmpRHS) &&
1150 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1151 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1153 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1160 void SelectionDAGBuilder::visitBr(BranchInst &I) {
1161 // Update machine-CFG edges.
1162 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1164 // Figure out which block is immediately after the current one.
1165 MachineBasicBlock *NextBlock = 0;
1166 MachineFunction::iterator BBI = CurMBB;
1167 if (++BBI != FuncInfo.MF->end())
1170 if (I.isUnconditional()) {
1171 // Update machine-CFG edges.
1172 CurMBB->addSuccessor(Succ0MBB);
1174 // If this is not a fall-through branch, emit the branch.
1175 if (Succ0MBB != NextBlock)
1176 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1177 MVT::Other, getControlRoot(),
1178 DAG.getBasicBlock(Succ0MBB)));
1183 // If this condition is one of the special cases we handle, do special stuff
1185 Value *CondVal = I.getCondition();
1186 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1188 // If this is a series of conditions that are or'd or and'd together, emit
1189 // this as a sequence of branches instead of setcc's with and/or operations.
1190 // For example, instead of something like:
1203 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1204 if (BOp->hasOneUse() &&
1205 (BOp->getOpcode() == Instruction::And ||
1206 BOp->getOpcode() == Instruction::Or)) {
1207 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1208 // If the compares in later blocks need to use values not currently
1209 // exported from this block, export them now. This block should always
1210 // be the first entry.
1211 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1213 // Allow some cases to be rejected.
1214 if (ShouldEmitAsBranches(SwitchCases)) {
1215 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1216 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1217 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1220 // Emit the branch for this block.
1221 visitSwitchCase(SwitchCases[0]);
1222 SwitchCases.erase(SwitchCases.begin());
1226 // Okay, we decided not to do this, remove any inserted MBB's and clear
1228 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1229 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1231 SwitchCases.clear();
1235 // Create a CaseBlock record representing this branch.
1236 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1237 NULL, Succ0MBB, Succ1MBB, CurMBB);
1239 // Use visitSwitchCase to actually insert the fast branch sequence for this
1241 visitSwitchCase(CB);
1244 /// visitSwitchCase - Emits the necessary code to represent a single node in
1245 /// the binary search tree resulting from lowering a switch instruction.
1246 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
1248 SDValue CondLHS = getValue(CB.CmpLHS);
1249 DebugLoc dl = getCurDebugLoc();
1251 // Build the setcc now.
1252 if (CB.CmpMHS == NULL) {
1253 // Fold "(X == true)" to X and "(X == false)" to !X to
1254 // handle common cases produced by branch lowering.
1255 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1256 CB.CC == ISD::SETEQ)
1258 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1259 CB.CC == ISD::SETEQ) {
1260 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1261 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1263 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1265 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1267 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1268 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1270 SDValue CmpOp = getValue(CB.CmpMHS);
1271 EVT VT = CmpOp.getValueType();
1273 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1274 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1277 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1278 VT, CmpOp, DAG.getConstant(Low, VT));
1279 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1280 DAG.getConstant(High-Low, VT), ISD::SETULE);
1284 // Update successor info
1285 CurMBB->addSuccessor(CB.TrueBB);
1286 CurMBB->addSuccessor(CB.FalseBB);
1288 // Set NextBlock to be the MBB immediately after the current one, if any.
1289 // This is used to avoid emitting unnecessary branches to the next block.
1290 MachineBasicBlock *NextBlock = 0;
1291 MachineFunction::iterator BBI = CurMBB;
1292 if (++BBI != FuncInfo.MF->end())
1295 // If the lhs block is the next block, invert the condition so that we can
1296 // fall through to the lhs instead of the rhs block.
1297 if (CB.TrueBB == NextBlock) {
1298 std::swap(CB.TrueBB, CB.FalseBB);
1299 SDValue True = DAG.getConstant(1, Cond.getValueType());
1300 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1303 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1304 MVT::Other, getControlRoot(), Cond,
1305 DAG.getBasicBlock(CB.TrueBB));
1307 // If the branch was constant folded, fix up the CFG.
1308 if (BrCond.getOpcode() == ISD::BR) {
1309 CurMBB->removeSuccessor(CB.FalseBB);
1311 // Otherwise, go ahead and insert the false branch.
1312 if (BrCond == getControlRoot())
1313 CurMBB->removeSuccessor(CB.TrueBB);
1315 if (CB.FalseBB != NextBlock)
1316 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1317 DAG.getBasicBlock(CB.FalseBB));
1320 DAG.setRoot(BrCond);
1323 /// visitJumpTable - Emit JumpTable node in the current MBB
1324 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1325 // Emit the code for the jump table
1326 assert(JT.Reg != -1U && "Should lower JT Header first!");
1327 EVT PTy = TLI.getPointerTy();
1328 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1330 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1331 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1332 MVT::Other, Index.getValue(1),
1334 DAG.setRoot(BrJumpTable);
1337 /// visitJumpTableHeader - This function emits necessary code to produce index
1338 /// in the JumpTable from switch case.
1339 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1340 JumpTableHeader &JTH) {
1341 // Subtract the lowest switch case value from the value being switched on and
1342 // conditional branch to default mbb if the result is greater than the
1343 // difference between smallest and largest cases.
1344 SDValue SwitchOp = getValue(JTH.SValue);
1345 EVT VT = SwitchOp.getValueType();
1346 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1347 DAG.getConstant(JTH.First, VT));
1349 // The SDNode we just created, which holds the value being switched on minus
1350 // the smallest case value, needs to be copied to a virtual register so it
1351 // can be used as an index into the jump table in a subsequent basic block.
1352 // This value may be smaller or larger than the target's pointer type, and
1353 // therefore require extension or truncating.
1354 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1356 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1357 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1358 JumpTableReg, SwitchOp);
1359 JT.Reg = JumpTableReg;
1361 // Emit the range check for the jump table, and branch to the default block
1362 // for the switch statement if the value being switched on exceeds the largest
1363 // case in the switch.
1364 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1365 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1366 DAG.getConstant(JTH.Last-JTH.First,VT),
1369 // Set NextBlock to be the MBB immediately after the current one, if any.
1370 // This is used to avoid emitting unnecessary branches to the next block.
1371 MachineBasicBlock *NextBlock = 0;
1372 MachineFunction::iterator BBI = CurMBB;
1374 if (++BBI != FuncInfo.MF->end())
1377 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1378 MVT::Other, CopyTo, CMP,
1379 DAG.getBasicBlock(JT.Default));
1381 if (JT.MBB != NextBlock)
1382 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1383 DAG.getBasicBlock(JT.MBB));
1385 DAG.setRoot(BrCond);
1388 /// visitBitTestHeader - This function emits necessary code to produce value
1389 /// suitable for "bit tests"
1390 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
1391 // Subtract the minimum value
1392 SDValue SwitchOp = getValue(B.SValue);
1393 EVT VT = SwitchOp.getValueType();
1394 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1395 DAG.getConstant(B.First, VT));
1398 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1399 TLI.getSetCCResultType(Sub.getValueType()),
1400 Sub, DAG.getConstant(B.Range, VT),
1403 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
1404 TLI.getPointerTy());
1406 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1407 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1410 // Set NextBlock to be the MBB immediately after the current one, if any.
1411 // This is used to avoid emitting unnecessary branches to the next block.
1412 MachineBasicBlock *NextBlock = 0;
1413 MachineFunction::iterator BBI = CurMBB;
1414 if (++BBI != FuncInfo.MF->end())
1417 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1419 CurMBB->addSuccessor(B.Default);
1420 CurMBB->addSuccessor(MBB);
1422 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1423 MVT::Other, CopyTo, RangeCmp,
1424 DAG.getBasicBlock(B.Default));
1426 if (MBB != NextBlock)
1427 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1428 DAG.getBasicBlock(MBB));
1430 DAG.setRoot(BrRange);
1433 /// visitBitTestCase - this function produces one "bit test"
1434 void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
1437 // Make desired shift
1438 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1439 TLI.getPointerTy());
1440 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1442 DAG.getConstant(1, TLI.getPointerTy()),
1445 // Emit bit tests and jumps
1446 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1447 TLI.getPointerTy(), SwitchVal,
1448 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1449 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1450 TLI.getSetCCResultType(AndOp.getValueType()),
1451 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1454 CurMBB->addSuccessor(B.TargetBB);
1455 CurMBB->addSuccessor(NextMBB);
1457 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1458 MVT::Other, getControlRoot(),
1459 AndCmp, DAG.getBasicBlock(B.TargetBB));
1461 // Set NextBlock to be the MBB immediately after the current one, if any.
1462 // This is used to avoid emitting unnecessary branches to the next block.
1463 MachineBasicBlock *NextBlock = 0;
1464 MachineFunction::iterator BBI = CurMBB;
1465 if (++BBI != FuncInfo.MF->end())
1468 if (NextMBB != NextBlock)
1469 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1470 DAG.getBasicBlock(NextMBB));
1475 void SelectionDAGBuilder::visitInvoke(InvokeInst &I) {
1476 // Retrieve successors.
1477 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1478 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1480 const Value *Callee(I.getCalledValue());
1481 if (isa<InlineAsm>(Callee))
1484 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1486 // If the value of the invoke is used outside of its defining block, make it
1487 // available as a virtual register.
1488 CopyToExportRegsIfNeeded(&I);
1490 // Update successor info
1491 CurMBB->addSuccessor(Return);
1492 CurMBB->addSuccessor(LandingPad);
1494 // Drop into normal successor.
1495 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1496 MVT::Other, getControlRoot(),
1497 DAG.getBasicBlock(Return)));
1500 void SelectionDAGBuilder::visitUnwind(UnwindInst &I) {
1503 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1504 /// small case ranges).
1505 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1506 CaseRecVector& WorkList,
1508 MachineBasicBlock* Default) {
1509 Case& BackCase = *(CR.Range.second-1);
1511 // Size is the number of Cases represented by this range.
1512 size_t Size = CR.Range.second - CR.Range.first;
1516 // Get the MachineFunction which holds the current MBB. This is used when
1517 // inserting any additional MBBs necessary to represent the switch.
1518 MachineFunction *CurMF = FuncInfo.MF;
1520 // Figure out which block is immediately after the current one.
1521 MachineBasicBlock *NextBlock = 0;
1522 MachineFunction::iterator BBI = CR.CaseBB;
1524 if (++BBI != FuncInfo.MF->end())
1527 // TODO: If any two of the cases has the same destination, and if one value
1528 // is the same as the other, but has one bit unset that the other has set,
1529 // use bit manipulation to do two compares at once. For example:
1530 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1532 // Rearrange the case blocks so that the last one falls through if possible.
1533 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1534 // The last case block won't fall through into 'NextBlock' if we emit the
1535 // branches in this order. See if rearranging a case value would help.
1536 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1537 if (I->BB == NextBlock) {
1538 std::swap(*I, BackCase);
1544 // Create a CaseBlock record representing a conditional branch to
1545 // the Case's target mbb if the value being switched on SV is equal
1547 MachineBasicBlock *CurBlock = CR.CaseBB;
1548 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1549 MachineBasicBlock *FallThrough;
1551 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1552 CurMF->insert(BBI, FallThrough);
1554 // Put SV in a virtual register to make it available from the new blocks.
1555 ExportFromCurrentBlock(SV);
1557 // If the last case doesn't match, go to the default block.
1558 FallThrough = Default;
1561 Value *RHS, *LHS, *MHS;
1563 if (I->High == I->Low) {
1564 // This is just small small case range :) containing exactly 1 case
1566 LHS = SV; RHS = I->High; MHS = NULL;
1569 LHS = I->Low; MHS = SV; RHS = I->High;
1571 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1573 // If emitting the first comparison, just call visitSwitchCase to emit the
1574 // code into the current block. Otherwise, push the CaseBlock onto the
1575 // vector to be later processed by SDISel, and insert the node's MBB
1576 // before the next MBB.
1577 if (CurBlock == CurMBB)
1578 visitSwitchCase(CB);
1580 SwitchCases.push_back(CB);
1582 CurBlock = FallThrough;
1588 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1589 return !DisableJumpTables &&
1590 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1591 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1594 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1595 APInt LastExt(Last), FirstExt(First);
1596 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1597 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1598 return (LastExt - FirstExt + 1ULL);
1601 /// handleJTSwitchCase - Emit jumptable for current switch case range
1602 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1603 CaseRecVector& WorkList,
1605 MachineBasicBlock* Default) {
1606 Case& FrontCase = *CR.Range.first;
1607 Case& BackCase = *(CR.Range.second-1);
1609 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1610 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1612 APInt TSize(First.getBitWidth(), 0);
1613 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1617 if (!areJTsAllowed(TLI) || TSize.ult(4))
1620 APInt Range = ComputeRange(First, Last);
1621 double Density = TSize.roundToDouble() / Range.roundToDouble();
1625 DEBUG(dbgs() << "Lowering jump table\n"
1626 << "First entry: " << First << ". Last entry: " << Last << '\n'
1627 << "Range: " << Range
1628 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1630 // Get the MachineFunction which holds the current MBB. This is used when
1631 // inserting any additional MBBs necessary to represent the switch.
1632 MachineFunction *CurMF = FuncInfo.MF;
1634 // Figure out which block is immediately after the current one.
1635 MachineFunction::iterator BBI = CR.CaseBB;
1638 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1640 // Create a new basic block to hold the code for loading the address
1641 // of the jump table, and jumping to it. Update successor information;
1642 // we will either branch to the default case for the switch, or the jump
1644 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1645 CurMF->insert(BBI, JumpTableBB);
1646 CR.CaseBB->addSuccessor(Default);
1647 CR.CaseBB->addSuccessor(JumpTableBB);
1649 // Build a vector of destination BBs, corresponding to each target
1650 // of the jump table. If the value of the jump table slot corresponds to
1651 // a case statement, push the case's BB onto the vector, otherwise, push
1653 std::vector<MachineBasicBlock*> DestBBs;
1655 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1656 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1657 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1659 if (Low.sle(TEI) && TEI.sle(High)) {
1660 DestBBs.push_back(I->BB);
1664 DestBBs.push_back(Default);
1668 // Update successor info. Add one edge to each unique successor.
1669 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1670 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1671 E = DestBBs.end(); I != E; ++I) {
1672 if (!SuccsHandled[(*I)->getNumber()]) {
1673 SuccsHandled[(*I)->getNumber()] = true;
1674 JumpTableBB->addSuccessor(*I);
1678 // Create a jump table index for this jump table.
1679 unsigned JTEncoding = TLI.getJumpTableEncoding();
1680 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1681 ->createJumpTableIndex(DestBBs);
1683 // Set the jump table information so that we can codegen it as a second
1684 // MachineBasicBlock
1685 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1686 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1687 if (CR.CaseBB == CurMBB)
1688 visitJumpTableHeader(JT, JTH);
1690 JTCases.push_back(JumpTableBlock(JTH, JT));
1695 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1697 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1698 CaseRecVector& WorkList,
1700 MachineBasicBlock* Default) {
1701 // Get the MachineFunction which holds the current MBB. This is used when
1702 // inserting any additional MBBs necessary to represent the switch.
1703 MachineFunction *CurMF = FuncInfo.MF;
1705 // Figure out which block is immediately after the current one.
1706 MachineFunction::iterator BBI = CR.CaseBB;
1709 Case& FrontCase = *CR.Range.first;
1710 Case& BackCase = *(CR.Range.second-1);
1711 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1713 // Size is the number of Cases represented by this range.
1714 unsigned Size = CR.Range.second - CR.Range.first;
1716 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1717 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1719 CaseItr Pivot = CR.Range.first + Size/2;
1721 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1722 // (heuristically) allow us to emit JumpTable's later.
1723 APInt TSize(First.getBitWidth(), 0);
1724 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1728 APInt LSize = FrontCase.size();
1729 APInt RSize = TSize-LSize;
1730 DEBUG(dbgs() << "Selecting best pivot: \n"
1731 << "First: " << First << ", Last: " << Last <<'\n'
1732 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1733 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1735 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
1736 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
1737 APInt Range = ComputeRange(LEnd, RBegin);
1738 assert((Range - 2ULL).isNonNegative() &&
1739 "Invalid case distance");
1740 double LDensity = (double)LSize.roundToDouble() /
1741 (LEnd - First + 1ULL).roundToDouble();
1742 double RDensity = (double)RSize.roundToDouble() /
1743 (Last - RBegin + 1ULL).roundToDouble();
1744 double Metric = Range.logBase2()*(LDensity+RDensity);
1745 // Should always split in some non-trivial place
1746 DEBUG(dbgs() <<"=>Step\n"
1747 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1748 << "LDensity: " << LDensity
1749 << ", RDensity: " << RDensity << '\n'
1750 << "Metric: " << Metric << '\n');
1751 if (FMetric < Metric) {
1754 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
1760 if (areJTsAllowed(TLI)) {
1761 // If our case is dense we *really* should handle it earlier!
1762 assert((FMetric > 0) && "Should handle dense range earlier!");
1764 Pivot = CR.Range.first + Size/2;
1767 CaseRange LHSR(CR.Range.first, Pivot);
1768 CaseRange RHSR(Pivot, CR.Range.second);
1769 Constant *C = Pivot->Low;
1770 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1772 // We know that we branch to the LHS if the Value being switched on is
1773 // less than the Pivot value, C. We use this to optimize our binary
1774 // tree a bit, by recognizing that if SV is greater than or equal to the
1775 // LHS's Case Value, and that Case Value is exactly one less than the
1776 // Pivot's Value, then we can branch directly to the LHS's Target,
1777 // rather than creating a leaf node for it.
1778 if ((LHSR.second - LHSR.first) == 1 &&
1779 LHSR.first->High == CR.GE &&
1780 cast<ConstantInt>(C)->getValue() ==
1781 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1782 TrueBB = LHSR.first->BB;
1784 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1785 CurMF->insert(BBI, TrueBB);
1786 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1788 // Put SV in a virtual register to make it available from the new blocks.
1789 ExportFromCurrentBlock(SV);
1792 // Similar to the optimization above, if the Value being switched on is
1793 // known to be less than the Constant CR.LT, and the current Case Value
1794 // is CR.LT - 1, then we can branch directly to the target block for
1795 // the current Case Value, rather than emitting a RHS leaf node for it.
1796 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1797 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1798 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1799 FalseBB = RHSR.first->BB;
1801 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1802 CurMF->insert(BBI, FalseBB);
1803 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1805 // Put SV in a virtual register to make it available from the new blocks.
1806 ExportFromCurrentBlock(SV);
1809 // Create a CaseBlock record representing a conditional branch to
1810 // the LHS node if the value being switched on SV is less than C.
1811 // Otherwise, branch to LHS.
1812 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1814 if (CR.CaseBB == CurMBB)
1815 visitSwitchCase(CB);
1817 SwitchCases.push_back(CB);
1822 /// handleBitTestsSwitchCase - if current case range has few destination and
1823 /// range span less, than machine word bitwidth, encode case range into series
1824 /// of masks and emit bit tests with these masks.
1825 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
1826 CaseRecVector& WorkList,
1828 MachineBasicBlock* Default){
1829 EVT PTy = TLI.getPointerTy();
1830 unsigned IntPtrBits = PTy.getSizeInBits();
1832 Case& FrontCase = *CR.Range.first;
1833 Case& BackCase = *(CR.Range.second-1);
1835 // Get the MachineFunction which holds the current MBB. This is used when
1836 // inserting any additional MBBs necessary to represent the switch.
1837 MachineFunction *CurMF = FuncInfo.MF;
1839 // If target does not have legal shift left, do not emit bit tests at all.
1840 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1844 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1846 // Single case counts one, case range - two.
1847 numCmps += (I->Low == I->High ? 1 : 2);
1850 // Count unique destinations
1851 SmallSet<MachineBasicBlock*, 4> Dests;
1852 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1853 Dests.insert(I->BB);
1854 if (Dests.size() > 3)
1855 // Don't bother the code below, if there are too much unique destinations
1858 DEBUG(dbgs() << "Total number of unique destinations: "
1859 << Dests.size() << '\n'
1860 << "Total number of comparisons: " << numCmps << '\n');
1862 // Compute span of values.
1863 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1864 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1865 APInt cmpRange = maxValue - minValue;
1867 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
1868 << "Low bound: " << minValue << '\n'
1869 << "High bound: " << maxValue << '\n');
1871 if (cmpRange.uge(IntPtrBits) ||
1872 (!(Dests.size() == 1 && numCmps >= 3) &&
1873 !(Dests.size() == 2 && numCmps >= 5) &&
1874 !(Dests.size() >= 3 && numCmps >= 6)))
1877 DEBUG(dbgs() << "Emitting bit tests\n");
1878 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1880 // Optimize the case where all the case values fit in a
1881 // word without having to subtract minValue. In this case,
1882 // we can optimize away the subtraction.
1883 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
1884 cmpRange = maxValue;
1886 lowBound = minValue;
1889 CaseBitsVector CasesBits;
1890 unsigned i, count = 0;
1892 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1893 MachineBasicBlock* Dest = I->BB;
1894 for (i = 0; i < count; ++i)
1895 if (Dest == CasesBits[i].BB)
1899 assert((count < 3) && "Too much destinations to test!");
1900 CasesBits.push_back(CaseBits(0, Dest, 0));
1904 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1905 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1907 uint64_t lo = (lowValue - lowBound).getZExtValue();
1908 uint64_t hi = (highValue - lowBound).getZExtValue();
1910 for (uint64_t j = lo; j <= hi; j++) {
1911 CasesBits[i].Mask |= 1ULL << j;
1912 CasesBits[i].Bits++;
1916 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1920 // Figure out which block is immediately after the current one.
1921 MachineFunction::iterator BBI = CR.CaseBB;
1924 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1926 DEBUG(dbgs() << "Cases:\n");
1927 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1928 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
1929 << ", Bits: " << CasesBits[i].Bits
1930 << ", BB: " << CasesBits[i].BB << '\n');
1932 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1933 CurMF->insert(BBI, CaseBB);
1934 BTC.push_back(BitTestCase(CasesBits[i].Mask,
1938 // Put SV in a virtual register to make it available from the new blocks.
1939 ExportFromCurrentBlock(SV);
1942 BitTestBlock BTB(lowBound, cmpRange, SV,
1943 -1U, (CR.CaseBB == CurMBB),
1944 CR.CaseBB, Default, BTC);
1946 if (CR.CaseBB == CurMBB)
1947 visitBitTestHeader(BTB);
1949 BitTestCases.push_back(BTB);
1954 /// Clusterify - Transform simple list of Cases into list of CaseRange's
1955 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
1956 const SwitchInst& SI) {
1959 // Start with "simple" cases
1960 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
1961 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1962 Cases.push_back(Case(SI.getSuccessorValue(i),
1963 SI.getSuccessorValue(i),
1966 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1968 // Merge case into clusters
1969 if (Cases.size() >= 2)
1970 // Must recompute end() each iteration because it may be
1971 // invalidated by erase if we hold on to it
1972 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
1973 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
1974 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
1975 MachineBasicBlock* nextBB = J->BB;
1976 MachineBasicBlock* currentBB = I->BB;
1978 // If the two neighboring cases go to the same destination, merge them
1979 // into a single case.
1980 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
1988 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1989 if (I->Low != I->High)
1990 // A range counts double, since it requires two compares.
1997 void SelectionDAGBuilder::visitSwitch(SwitchInst &SI) {
1998 // Figure out which block is immediately after the current one.
1999 MachineBasicBlock *NextBlock = 0;
2000 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2002 // If there is only the default destination, branch to it if it is not the
2003 // next basic block. Otherwise, just fall through.
2004 if (SI.getNumOperands() == 2) {
2005 // Update machine-CFG edges.
2007 // If this is not a fall-through branch, emit the branch.
2008 CurMBB->addSuccessor(Default);
2009 if (Default != NextBlock)
2010 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2011 MVT::Other, getControlRoot(),
2012 DAG.getBasicBlock(Default)));
2017 // If there are any non-default case statements, create a vector of Cases
2018 // representing each one, and sort the vector so that we can efficiently
2019 // create a binary search tree from them.
2021 size_t numCmps = Clusterify(Cases, SI);
2022 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2023 << ". Total compares: " << numCmps << '\n');
2026 // Get the Value to be switched on and default basic blocks, which will be
2027 // inserted into CaseBlock records, representing basic blocks in the binary
2029 Value *SV = SI.getOperand(0);
2031 // Push the initial CaseRec onto the worklist
2032 CaseRecVector WorkList;
2033 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2035 while (!WorkList.empty()) {
2036 // Grab a record representing a case range to process off the worklist
2037 CaseRec CR = WorkList.back();
2038 WorkList.pop_back();
2040 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2043 // If the range has few cases (two or less) emit a series of specific
2045 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2048 // If the switch has more than 5 blocks, and at least 40% dense, and the
2049 // target supports indirect branches, then emit a jump table rather than
2050 // lowering the switch to a binary tree of conditional branches.
2051 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2054 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2055 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2056 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2060 void SelectionDAGBuilder::visitIndirectBr(IndirectBrInst &I) {
2061 // Update machine-CFG edges with unique successors.
2062 SmallVector<BasicBlock*, 32> succs;
2063 succs.reserve(I.getNumSuccessors());
2064 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2065 succs.push_back(I.getSuccessor(i));
2066 array_pod_sort(succs.begin(), succs.end());
2067 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2068 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2069 CurMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2071 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2072 MVT::Other, getControlRoot(),
2073 getValue(I.getAddress())));
2076 void SelectionDAGBuilder::visitFSub(User &I) {
2077 // -0.0 - X --> fneg
2078 const Type *Ty = I.getType();
2079 if (Ty->isVectorTy()) {
2080 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2081 const VectorType *DestTy = cast<VectorType>(I.getType());
2082 const Type *ElTy = DestTy->getElementType();
2083 unsigned VL = DestTy->getNumElements();
2084 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2085 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2087 SDValue Op2 = getValue(I.getOperand(1));
2088 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2089 Op2.getValueType(), Op2));
2095 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2096 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2097 SDValue Op2 = getValue(I.getOperand(1));
2098 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2099 Op2.getValueType(), Op2));
2103 visitBinary(I, ISD::FSUB);
2106 void SelectionDAGBuilder::visitBinary(User &I, unsigned OpCode) {
2107 SDValue Op1 = getValue(I.getOperand(0));
2108 SDValue Op2 = getValue(I.getOperand(1));
2109 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2110 Op1.getValueType(), Op1, Op2));
2113 void SelectionDAGBuilder::visitShift(User &I, unsigned Opcode) {
2114 SDValue Op1 = getValue(I.getOperand(0));
2115 SDValue Op2 = getValue(I.getOperand(1));
2116 if (!I.getType()->isVectorTy() &&
2117 Op2.getValueType() != TLI.getShiftAmountTy()) {
2118 // If the operand is smaller than the shift count type, promote it.
2119 EVT PTy = TLI.getPointerTy();
2120 EVT STy = TLI.getShiftAmountTy();
2121 if (STy.bitsGT(Op2.getValueType()))
2122 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2123 TLI.getShiftAmountTy(), Op2);
2124 // If the operand is larger than the shift count type but the shift
2125 // count type has enough bits to represent any shift value, truncate
2126 // it now. This is a common case and it exposes the truncate to
2127 // optimization early.
2128 else if (STy.getSizeInBits() >=
2129 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2130 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2131 TLI.getShiftAmountTy(), Op2);
2132 // Otherwise we'll need to temporarily settle for some other
2133 // convenient type; type legalization will make adjustments as
2135 else if (PTy.bitsLT(Op2.getValueType()))
2136 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2137 TLI.getPointerTy(), Op2);
2138 else if (PTy.bitsGT(Op2.getValueType()))
2139 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2140 TLI.getPointerTy(), Op2);
2143 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2144 Op1.getValueType(), Op1, Op2));
2147 void SelectionDAGBuilder::visitICmp(User &I) {
2148 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2149 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2150 predicate = IC->getPredicate();
2151 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2152 predicate = ICmpInst::Predicate(IC->getPredicate());
2153 SDValue Op1 = getValue(I.getOperand(0));
2154 SDValue Op2 = getValue(I.getOperand(1));
2155 ISD::CondCode Opcode = getICmpCondCode(predicate);
2157 EVT DestVT = TLI.getValueType(I.getType());
2158 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2161 void SelectionDAGBuilder::visitFCmp(User &I) {
2162 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2163 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2164 predicate = FC->getPredicate();
2165 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2166 predicate = FCmpInst::Predicate(FC->getPredicate());
2167 SDValue Op1 = getValue(I.getOperand(0));
2168 SDValue Op2 = getValue(I.getOperand(1));
2169 ISD::CondCode Condition = getFCmpCondCode(predicate);
2170 EVT DestVT = TLI.getValueType(I.getType());
2171 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2174 void SelectionDAGBuilder::visitSelect(User &I) {
2175 SmallVector<EVT, 4> ValueVTs;
2176 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2177 unsigned NumValues = ValueVTs.size();
2178 if (NumValues == 0) return;
2180 SmallVector<SDValue, 4> Values(NumValues);
2181 SDValue Cond = getValue(I.getOperand(0));
2182 SDValue TrueVal = getValue(I.getOperand(1));
2183 SDValue FalseVal = getValue(I.getOperand(2));
2185 for (unsigned i = 0; i != NumValues; ++i)
2186 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2187 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2189 SDValue(TrueVal.getNode(),
2190 TrueVal.getResNo() + i),
2191 SDValue(FalseVal.getNode(),
2192 FalseVal.getResNo() + i));
2194 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2195 DAG.getVTList(&ValueVTs[0], NumValues),
2196 &Values[0], NumValues));
2199 void SelectionDAGBuilder::visitTrunc(User &I) {
2200 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2201 SDValue N = getValue(I.getOperand(0));
2202 EVT DestVT = TLI.getValueType(I.getType());
2203 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2206 void SelectionDAGBuilder::visitZExt(User &I) {
2207 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2208 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2209 SDValue N = getValue(I.getOperand(0));
2210 EVT DestVT = TLI.getValueType(I.getType());
2211 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2214 void SelectionDAGBuilder::visitSExt(User &I) {
2215 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2216 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2217 SDValue N = getValue(I.getOperand(0));
2218 EVT DestVT = TLI.getValueType(I.getType());
2219 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2222 void SelectionDAGBuilder::visitFPTrunc(User &I) {
2223 // FPTrunc is never a no-op cast, no need to check
2224 SDValue N = getValue(I.getOperand(0));
2225 EVT DestVT = TLI.getValueType(I.getType());
2226 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2227 DestVT, N, DAG.getIntPtrConstant(0)));
2230 void SelectionDAGBuilder::visitFPExt(User &I){
2231 // FPTrunc is never a no-op cast, no need to check
2232 SDValue N = getValue(I.getOperand(0));
2233 EVT DestVT = TLI.getValueType(I.getType());
2234 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2237 void SelectionDAGBuilder::visitFPToUI(User &I) {
2238 // FPToUI is never a no-op cast, no need to check
2239 SDValue N = getValue(I.getOperand(0));
2240 EVT DestVT = TLI.getValueType(I.getType());
2241 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2244 void SelectionDAGBuilder::visitFPToSI(User &I) {
2245 // FPToSI is never a no-op cast, no need to check
2246 SDValue N = getValue(I.getOperand(0));
2247 EVT DestVT = TLI.getValueType(I.getType());
2248 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2251 void SelectionDAGBuilder::visitUIToFP(User &I) {
2252 // UIToFP is never a no-op cast, no need to check
2253 SDValue N = getValue(I.getOperand(0));
2254 EVT DestVT = TLI.getValueType(I.getType());
2255 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2258 void SelectionDAGBuilder::visitSIToFP(User &I){
2259 // SIToFP is never a no-op cast, no need to check
2260 SDValue N = getValue(I.getOperand(0));
2261 EVT DestVT = TLI.getValueType(I.getType());
2262 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2265 void SelectionDAGBuilder::visitPtrToInt(User &I) {
2266 // What to do depends on the size of the integer and the size of the pointer.
2267 // We can either truncate, zero extend, or no-op, accordingly.
2268 SDValue N = getValue(I.getOperand(0));
2269 EVT SrcVT = N.getValueType();
2270 EVT DestVT = TLI.getValueType(I.getType());
2271 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2274 void SelectionDAGBuilder::visitIntToPtr(User &I) {
2275 // What to do depends on the size of the integer and the size of the pointer.
2276 // We can either truncate, zero extend, or no-op, accordingly.
2277 SDValue N = getValue(I.getOperand(0));
2278 EVT SrcVT = N.getValueType();
2279 EVT DestVT = TLI.getValueType(I.getType());
2280 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2283 void SelectionDAGBuilder::visitBitCast(User &I) {
2284 SDValue N = getValue(I.getOperand(0));
2285 EVT DestVT = TLI.getValueType(I.getType());
2287 // BitCast assures us that source and destination are the same size so this is
2288 // either a BIT_CONVERT or a no-op.
2289 if (DestVT != N.getValueType())
2290 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2291 DestVT, N)); // convert types.
2293 setValue(&I, N); // noop cast.
2296 void SelectionDAGBuilder::visitInsertElement(User &I) {
2297 SDValue InVec = getValue(I.getOperand(0));
2298 SDValue InVal = getValue(I.getOperand(1));
2299 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2301 getValue(I.getOperand(2)));
2302 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2303 TLI.getValueType(I.getType()),
2304 InVec, InVal, InIdx));
2307 void SelectionDAGBuilder::visitExtractElement(User &I) {
2308 SDValue InVec = getValue(I.getOperand(0));
2309 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2311 getValue(I.getOperand(1)));
2312 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2313 TLI.getValueType(I.getType()), InVec, InIdx));
2316 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2317 // from SIndx and increasing to the element length (undefs are allowed).
2318 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2319 unsigned MaskNumElts = Mask.size();
2320 for (unsigned i = 0; i != MaskNumElts; ++i)
2321 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2326 void SelectionDAGBuilder::visitShuffleVector(User &I) {
2327 SmallVector<int, 8> Mask;
2328 SDValue Src1 = getValue(I.getOperand(0));
2329 SDValue Src2 = getValue(I.getOperand(1));
2331 // Convert the ConstantVector mask operand into an array of ints, with -1
2332 // representing undef values.
2333 SmallVector<Constant*, 8> MaskElts;
2334 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2335 unsigned MaskNumElts = MaskElts.size();
2336 for (unsigned i = 0; i != MaskNumElts; ++i) {
2337 if (isa<UndefValue>(MaskElts[i]))
2340 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2343 EVT VT = TLI.getValueType(I.getType());
2344 EVT SrcVT = Src1.getValueType();
2345 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2347 if (SrcNumElts == MaskNumElts) {
2348 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2353 // Normalize the shuffle vector since mask and vector length don't match.
2354 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2355 // Mask is longer than the source vectors and is a multiple of the source
2356 // vectors. We can use concatenate vector to make the mask and vectors
2358 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2359 // The shuffle is concatenating two vectors together.
2360 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2365 // Pad both vectors with undefs to make them the same length as the mask.
2366 unsigned NumConcat = MaskNumElts / SrcNumElts;
2367 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2368 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2369 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2371 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2372 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2376 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2377 getCurDebugLoc(), VT,
2378 &MOps1[0], NumConcat);
2379 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2380 getCurDebugLoc(), VT,
2381 &MOps2[0], NumConcat);
2383 // Readjust mask for new input vector length.
2384 SmallVector<int, 8> MappedOps;
2385 for (unsigned i = 0; i != MaskNumElts; ++i) {
2387 if (Idx < (int)SrcNumElts)
2388 MappedOps.push_back(Idx);
2390 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2393 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2398 if (SrcNumElts > MaskNumElts) {
2399 // Analyze the access pattern of the vector to see if we can extract
2400 // two subvectors and do the shuffle. The analysis is done by calculating
2401 // the range of elements the mask access on both vectors.
2402 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2403 int MaxRange[2] = {-1, -1};
2405 for (unsigned i = 0; i != MaskNumElts; ++i) {
2411 if (Idx >= (int)SrcNumElts) {
2415 if (Idx > MaxRange[Input])
2416 MaxRange[Input] = Idx;
2417 if (Idx < MinRange[Input])
2418 MinRange[Input] = Idx;
2421 // Check if the access is smaller than the vector size and can we find
2422 // a reasonable extract index.
2423 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2425 int StartIdx[2]; // StartIdx to extract from
2426 for (int Input=0; Input < 2; ++Input) {
2427 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2428 RangeUse[Input] = 0; // Unused
2429 StartIdx[Input] = 0;
2430 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2431 // Fits within range but we should see if we can find a good
2432 // start index that is a multiple of the mask length.
2433 if (MaxRange[Input] < (int)MaskNumElts) {
2434 RangeUse[Input] = 1; // Extract from beginning of the vector
2435 StartIdx[Input] = 0;
2437 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2438 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2439 StartIdx[Input] + MaskNumElts < SrcNumElts)
2440 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2445 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2446 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2449 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2450 // Extract appropriate subvector and generate a vector shuffle
2451 for (int Input=0; Input < 2; ++Input) {
2452 SDValue &Src = Input == 0 ? Src1 : Src2;
2453 if (RangeUse[Input] == 0)
2454 Src = DAG.getUNDEF(VT);
2456 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2457 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2460 // Calculate new mask.
2461 SmallVector<int, 8> MappedOps;
2462 for (unsigned i = 0; i != MaskNumElts; ++i) {
2465 MappedOps.push_back(Idx);
2466 else if (Idx < (int)SrcNumElts)
2467 MappedOps.push_back(Idx - StartIdx[0]);
2469 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2472 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2478 // We can't use either concat vectors or extract subvectors so fall back to
2479 // replacing the shuffle with extract and build vector.
2480 // to insert and build vector.
2481 EVT EltVT = VT.getVectorElementType();
2482 EVT PtrVT = TLI.getPointerTy();
2483 SmallVector<SDValue,8> Ops;
2484 for (unsigned i = 0; i != MaskNumElts; ++i) {
2486 Ops.push_back(DAG.getUNDEF(EltVT));
2491 if (Idx < (int)SrcNumElts)
2492 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2493 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2495 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2497 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2503 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2504 VT, &Ops[0], Ops.size()));
2507 void SelectionDAGBuilder::visitInsertValue(InsertValueInst &I) {
2508 const Value *Op0 = I.getOperand(0);
2509 const Value *Op1 = I.getOperand(1);
2510 const Type *AggTy = I.getType();
2511 const Type *ValTy = Op1->getType();
2512 bool IntoUndef = isa<UndefValue>(Op0);
2513 bool FromUndef = isa<UndefValue>(Op1);
2515 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2516 I.idx_begin(), I.idx_end());
2518 SmallVector<EVT, 4> AggValueVTs;
2519 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2520 SmallVector<EVT, 4> ValValueVTs;
2521 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2523 unsigned NumAggValues = AggValueVTs.size();
2524 unsigned NumValValues = ValValueVTs.size();
2525 SmallVector<SDValue, 4> Values(NumAggValues);
2527 SDValue Agg = getValue(Op0);
2528 SDValue Val = getValue(Op1);
2530 // Copy the beginning value(s) from the original aggregate.
2531 for (; i != LinearIndex; ++i)
2532 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2533 SDValue(Agg.getNode(), Agg.getResNo() + i);
2534 // Copy values from the inserted value(s).
2535 for (; i != LinearIndex + NumValValues; ++i)
2536 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2537 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2538 // Copy remaining value(s) from the original aggregate.
2539 for (; i != NumAggValues; ++i)
2540 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2541 SDValue(Agg.getNode(), Agg.getResNo() + i);
2543 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2544 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2545 &Values[0], NumAggValues));
2548 void SelectionDAGBuilder::visitExtractValue(ExtractValueInst &I) {
2549 const Value *Op0 = I.getOperand(0);
2550 const Type *AggTy = Op0->getType();
2551 const Type *ValTy = I.getType();
2552 bool OutOfUndef = isa<UndefValue>(Op0);
2554 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2555 I.idx_begin(), I.idx_end());
2557 SmallVector<EVT, 4> ValValueVTs;
2558 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2560 unsigned NumValValues = ValValueVTs.size();
2561 SmallVector<SDValue, 4> Values(NumValValues);
2563 SDValue Agg = getValue(Op0);
2564 // Copy out the selected value(s).
2565 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2566 Values[i - LinearIndex] =
2568 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2569 SDValue(Agg.getNode(), Agg.getResNo() + i);
2571 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2572 DAG.getVTList(&ValValueVTs[0], NumValValues),
2573 &Values[0], NumValValues));
2576 void SelectionDAGBuilder::visitGetElementPtr(User &I) {
2577 SDValue N = getValue(I.getOperand(0));
2578 const Type *Ty = I.getOperand(0)->getType();
2580 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2583 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2584 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2587 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2588 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2589 DAG.getIntPtrConstant(Offset));
2592 Ty = StTy->getElementType(Field);
2593 } else if (const UnionType *UnTy = dyn_cast<UnionType>(Ty)) {
2594 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2596 // Offset canonically 0 for unions, but type changes
2597 Ty = UnTy->getElementType(Field);
2599 Ty = cast<SequentialType>(Ty)->getElementType();
2601 // If this is a constant subscript, handle it quickly.
2602 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2603 if (CI->getZExtValue() == 0) continue;
2605 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2607 EVT PTy = TLI.getPointerTy();
2608 unsigned PtrBits = PTy.getSizeInBits();
2610 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2612 DAG.getConstant(Offs, MVT::i64));
2614 OffsVal = DAG.getIntPtrConstant(Offs);
2616 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2621 // N = N + Idx * ElementSize;
2622 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2623 TD->getTypeAllocSize(Ty));
2624 SDValue IdxN = getValue(Idx);
2626 // If the index is smaller or larger than intptr_t, truncate or extend
2628 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2630 // If this is a multiply by a power of two, turn it into a shl
2631 // immediately. This is a very common case.
2632 if (ElementSize != 1) {
2633 if (ElementSize.isPowerOf2()) {
2634 unsigned Amt = ElementSize.logBase2();
2635 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2636 N.getValueType(), IdxN,
2637 DAG.getConstant(Amt, TLI.getPointerTy()));
2639 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2640 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2641 N.getValueType(), IdxN, Scale);
2645 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2646 N.getValueType(), N, IdxN);
2653 void SelectionDAGBuilder::visitAlloca(AllocaInst &I) {
2654 // If this is a fixed sized alloca in the entry block of the function,
2655 // allocate it statically on the stack.
2656 if (FuncInfo.StaticAllocaMap.count(&I))
2657 return; // getValue will auto-populate this.
2659 const Type *Ty = I.getAllocatedType();
2660 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2662 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2665 SDValue AllocSize = getValue(I.getArraySize());
2667 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2669 DAG.getConstant(TySize, AllocSize.getValueType()));
2671 EVT IntPtr = TLI.getPointerTy();
2672 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2674 // Handle alignment. If the requested alignment is less than or equal to
2675 // the stack alignment, ignore it. If the size is greater than or equal to
2676 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2677 unsigned StackAlign =
2678 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2679 if (Align <= StackAlign)
2682 // Round the size of the allocation up to the stack alignment size
2683 // by add SA-1 to the size.
2684 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2685 AllocSize.getValueType(), AllocSize,
2686 DAG.getIntPtrConstant(StackAlign-1));
2688 // Mask out the low bits for alignment purposes.
2689 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2690 AllocSize.getValueType(), AllocSize,
2691 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2693 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2694 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2695 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2698 DAG.setRoot(DSA.getValue(1));
2700 // Inform the Frame Information that we have just allocated a variable-sized
2702 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
2705 void SelectionDAGBuilder::visitLoad(LoadInst &I) {
2706 const Value *SV = I.getOperand(0);
2707 SDValue Ptr = getValue(SV);
2709 const Type *Ty = I.getType();
2711 bool isVolatile = I.isVolatile();
2712 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2713 unsigned Alignment = I.getAlignment();
2715 SmallVector<EVT, 4> ValueVTs;
2716 SmallVector<uint64_t, 4> Offsets;
2717 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2718 unsigned NumValues = ValueVTs.size();
2723 bool ConstantMemory = false;
2725 // Serialize volatile loads with other side effects.
2727 else if (AA->pointsToConstantMemory(SV)) {
2728 // Do not serialize (non-volatile) loads of constant memory with anything.
2729 Root = DAG.getEntryNode();
2730 ConstantMemory = true;
2732 // Do not serialize non-volatile loads against each other.
2733 Root = DAG.getRoot();
2736 SmallVector<SDValue, 4> Values(NumValues);
2737 SmallVector<SDValue, 4> Chains(NumValues);
2738 EVT PtrVT = Ptr.getValueType();
2739 for (unsigned i = 0; i != NumValues; ++i) {
2740 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2742 DAG.getConstant(Offsets[i], PtrVT));
2743 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2744 A, SV, Offsets[i], isVolatile,
2745 isNonTemporal, Alignment);
2748 Chains[i] = L.getValue(1);
2751 if (!ConstantMemory) {
2752 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2753 MVT::Other, &Chains[0], NumValues);
2757 PendingLoads.push_back(Chain);
2760 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2761 DAG.getVTList(&ValueVTs[0], NumValues),
2762 &Values[0], NumValues));
2765 void SelectionDAGBuilder::visitStore(StoreInst &I) {
2766 Value *SrcV = I.getOperand(0);
2767 Value *PtrV = I.getOperand(1);
2769 SmallVector<EVT, 4> ValueVTs;
2770 SmallVector<uint64_t, 4> Offsets;
2771 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2772 unsigned NumValues = ValueVTs.size();
2776 // Get the lowered operands. Note that we do this after
2777 // checking if NumResults is zero, because with zero results
2778 // the operands won't have values in the map.
2779 SDValue Src = getValue(SrcV);
2780 SDValue Ptr = getValue(PtrV);
2782 SDValue Root = getRoot();
2783 SmallVector<SDValue, 4> Chains(NumValues);
2784 EVT PtrVT = Ptr.getValueType();
2785 bool isVolatile = I.isVolatile();
2786 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2787 unsigned Alignment = I.getAlignment();
2789 for (unsigned i = 0; i != NumValues; ++i) {
2790 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
2791 DAG.getConstant(Offsets[i], PtrVT));
2792 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2793 SDValue(Src.getNode(), Src.getResNo() + i),
2794 Add, PtrV, Offsets[i], isVolatile,
2795 isNonTemporal, Alignment);
2798 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2799 MVT::Other, &Chains[0], NumValues));
2802 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2804 void SelectionDAGBuilder::visitTargetIntrinsic(CallInst &I,
2805 unsigned Intrinsic) {
2806 bool HasChain = !I.doesNotAccessMemory();
2807 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2809 // Build the operand list.
2810 SmallVector<SDValue, 8> Ops;
2811 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2813 // We don't need to serialize loads against other loads.
2814 Ops.push_back(DAG.getRoot());
2816 Ops.push_back(getRoot());
2820 // Info is set by getTgtMemInstrinsic
2821 TargetLowering::IntrinsicInfo Info;
2822 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2824 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2825 if (!IsTgtIntrinsic)
2826 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2828 // Add all operands of the call to the operand list.
2829 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2830 SDValue Op = getValue(I.getOperand(i));
2831 assert(TLI.isTypeLegal(Op.getValueType()) &&
2832 "Intrinsic uses a non-legal type?");
2836 SmallVector<EVT, 4> ValueVTs;
2837 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2839 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
2840 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
2841 "Intrinsic uses a non-legal type?");
2846 ValueVTs.push_back(MVT::Other);
2848 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
2852 if (IsTgtIntrinsic) {
2853 // This is target intrinsic that touches memory
2854 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2855 VTs, &Ops[0], Ops.size(),
2856 Info.memVT, Info.ptrVal, Info.offset,
2857 Info.align, Info.vol,
2858 Info.readMem, Info.writeMem);
2859 } else if (!HasChain) {
2860 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2861 VTs, &Ops[0], Ops.size());
2862 } else if (!I.getType()->isVoidTy()) {
2863 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2864 VTs, &Ops[0], Ops.size());
2866 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2867 VTs, &Ops[0], Ops.size());
2871 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2873 PendingLoads.push_back(Chain);
2878 if (!I.getType()->isVoidTy()) {
2879 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2880 EVT VT = TLI.getValueType(PTy);
2881 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2884 setValue(&I, Result);
2888 /// GetSignificand - Get the significand and build it into a floating-point
2889 /// number with exponent of 1:
2891 /// Op = (Op & 0x007fffff) | 0x3f800000;
2893 /// where Op is the hexidecimal representation of floating point value.
2895 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
2896 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
2897 DAG.getConstant(0x007fffff, MVT::i32));
2898 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
2899 DAG.getConstant(0x3f800000, MVT::i32));
2900 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
2903 /// GetExponent - Get the exponent:
2905 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
2907 /// where Op is the hexidecimal representation of floating point value.
2909 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
2911 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
2912 DAG.getConstant(0x7f800000, MVT::i32));
2913 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
2914 DAG.getConstant(23, TLI.getPointerTy()));
2915 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
2916 DAG.getConstant(127, MVT::i32));
2917 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
2920 /// getF32Constant - Get 32-bit floating point constant.
2922 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
2923 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
2926 /// Inlined utility function to implement binary input atomic intrinsics for
2927 /// visitIntrinsicCall: I is a call instruction
2928 /// Op is the associated NodeType for I
2930 SelectionDAGBuilder::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
2931 SDValue Root = getRoot();
2933 DAG.getAtomic(Op, getCurDebugLoc(),
2934 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
2936 getValue(I.getOperand(1)),
2937 getValue(I.getOperand(2)),
2940 DAG.setRoot(L.getValue(1));
2944 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
2946 SelectionDAGBuilder::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
2947 SDValue Op1 = getValue(I.getOperand(1));
2948 SDValue Op2 = getValue(I.getOperand(2));
2950 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
2951 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
2955 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
2956 /// limited-precision mode.
2958 SelectionDAGBuilder::visitExp(CallInst &I) {
2960 DebugLoc dl = getCurDebugLoc();
2962 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2963 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2964 SDValue Op = getValue(I.getOperand(1));
2966 // Put the exponent in the right bit position for later addition to the
2969 // #define LOG2OFe 1.4426950f
2970 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
2971 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
2972 getF32Constant(DAG, 0x3fb8aa3b));
2973 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
2975 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
2976 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
2977 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
2979 // IntegerPartOfX <<= 23;
2980 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
2981 DAG.getConstant(23, TLI.getPointerTy()));
2983 if (LimitFloatPrecision <= 6) {
2984 // For floating-point precision of 6:
2986 // TwoToFractionalPartOfX =
2988 // (0.735607626f + 0.252464424f * x) * x;
2990 // error 0.0144103317, which is 6 bits
2991 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
2992 getF32Constant(DAG, 0x3e814304));
2993 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
2994 getF32Constant(DAG, 0x3f3c50c8));
2995 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
2996 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
2997 getF32Constant(DAG, 0x3f7f5e7e));
2998 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3000 // Add the exponent into the result in integer domain.
3001 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3002 TwoToFracPartOfX, IntegerPartOfX);
3004 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3005 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3006 // For floating-point precision of 12:
3008 // TwoToFractionalPartOfX =
3011 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3013 // 0.000107046256 error, which is 13 to 14 bits
3014 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3015 getF32Constant(DAG, 0x3da235e3));
3016 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3017 getF32Constant(DAG, 0x3e65b8f3));
3018 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3019 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3020 getF32Constant(DAG, 0x3f324b07));
3021 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3022 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3023 getF32Constant(DAG, 0x3f7ff8fd));
3024 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3026 // Add the exponent into the result in integer domain.
3027 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3028 TwoToFracPartOfX, IntegerPartOfX);
3030 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3031 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3032 // For floating-point precision of 18:
3034 // TwoToFractionalPartOfX =
3038 // (0.554906021e-1f +
3039 // (0.961591928e-2f +
3040 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3042 // error 2.47208000*10^(-7), which is better than 18 bits
3043 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3044 getF32Constant(DAG, 0x3924b03e));
3045 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3046 getF32Constant(DAG, 0x3ab24b87));
3047 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3048 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3049 getF32Constant(DAG, 0x3c1d8c17));
3050 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3051 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3052 getF32Constant(DAG, 0x3d634a1d));
3053 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3054 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3055 getF32Constant(DAG, 0x3e75fe14));
3056 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3057 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3058 getF32Constant(DAG, 0x3f317234));
3059 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3060 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3061 getF32Constant(DAG, 0x3f800000));
3062 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3065 // Add the exponent into the result in integer domain.
3066 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3067 TwoToFracPartOfX, IntegerPartOfX);
3069 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3072 // No special expansion.
3073 result = DAG.getNode(ISD::FEXP, dl,
3074 getValue(I.getOperand(1)).getValueType(),
3075 getValue(I.getOperand(1)));
3078 setValue(&I, result);
3081 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3082 /// limited-precision mode.
3084 SelectionDAGBuilder::visitLog(CallInst &I) {
3086 DebugLoc dl = getCurDebugLoc();
3088 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3089 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3090 SDValue Op = getValue(I.getOperand(1));
3091 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3093 // Scale the exponent by log(2) [0.69314718f].
3094 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3095 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3096 getF32Constant(DAG, 0x3f317218));
3098 // Get the significand and build it into a floating-point number with
3100 SDValue X = GetSignificand(DAG, Op1, dl);
3102 if (LimitFloatPrecision <= 6) {
3103 // For floating-point precision of 6:
3107 // (1.4034025f - 0.23903021f * x) * x;
3109 // error 0.0034276066, which is better than 8 bits
3110 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3111 getF32Constant(DAG, 0xbe74c456));
3112 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3113 getF32Constant(DAG, 0x3fb3a2b1));
3114 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3115 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3116 getF32Constant(DAG, 0x3f949a29));
3118 result = DAG.getNode(ISD::FADD, dl,
3119 MVT::f32, LogOfExponent, LogOfMantissa);
3120 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3121 // For floating-point precision of 12:
3127 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3129 // error 0.000061011436, which is 14 bits
3130 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3131 getF32Constant(DAG, 0xbd67b6d6));
3132 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3133 getF32Constant(DAG, 0x3ee4f4b8));
3134 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3135 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3136 getF32Constant(DAG, 0x3fbc278b));
3137 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3138 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3139 getF32Constant(DAG, 0x40348e95));
3140 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3141 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3142 getF32Constant(DAG, 0x3fdef31a));
3144 result = DAG.getNode(ISD::FADD, dl,
3145 MVT::f32, LogOfExponent, LogOfMantissa);
3146 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3147 // For floating-point precision of 18:
3155 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3157 // error 0.0000023660568, which is better than 18 bits
3158 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3159 getF32Constant(DAG, 0xbc91e5ac));
3160 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3161 getF32Constant(DAG, 0x3e4350aa));
3162 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3163 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3164 getF32Constant(DAG, 0x3f60d3e3));
3165 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3166 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3167 getF32Constant(DAG, 0x4011cdf0));
3168 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3169 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3170 getF32Constant(DAG, 0x406cfd1c));
3171 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3172 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3173 getF32Constant(DAG, 0x408797cb));
3174 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3175 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3176 getF32Constant(DAG, 0x4006dcab));
3178 result = DAG.getNode(ISD::FADD, dl,
3179 MVT::f32, LogOfExponent, LogOfMantissa);
3182 // No special expansion.
3183 result = DAG.getNode(ISD::FLOG, dl,
3184 getValue(I.getOperand(1)).getValueType(),
3185 getValue(I.getOperand(1)));
3188 setValue(&I, result);
3191 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3192 /// limited-precision mode.
3194 SelectionDAGBuilder::visitLog2(CallInst &I) {
3196 DebugLoc dl = getCurDebugLoc();
3198 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3199 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3200 SDValue Op = getValue(I.getOperand(1));
3201 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3203 // Get the exponent.
3204 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3206 // Get the significand and build it into a floating-point number with
3208 SDValue X = GetSignificand(DAG, Op1, dl);
3210 // Different possible minimax approximations of significand in
3211 // floating-point for various degrees of accuracy over [1,2].
3212 if (LimitFloatPrecision <= 6) {
3213 // For floating-point precision of 6:
3215 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3217 // error 0.0049451742, which is more than 7 bits
3218 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3219 getF32Constant(DAG, 0xbeb08fe0));
3220 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3221 getF32Constant(DAG, 0x40019463));
3222 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3223 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3224 getF32Constant(DAG, 0x3fd6633d));
3226 result = DAG.getNode(ISD::FADD, dl,
3227 MVT::f32, LogOfExponent, Log2ofMantissa);
3228 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3229 // For floating-point precision of 12:
3235 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3237 // error 0.0000876136000, which is better than 13 bits
3238 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3239 getF32Constant(DAG, 0xbda7262e));
3240 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3241 getF32Constant(DAG, 0x3f25280b));
3242 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3243 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3244 getF32Constant(DAG, 0x4007b923));
3245 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3246 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3247 getF32Constant(DAG, 0x40823e2f));
3248 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3249 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3250 getF32Constant(DAG, 0x4020d29c));
3252 result = DAG.getNode(ISD::FADD, dl,
3253 MVT::f32, LogOfExponent, Log2ofMantissa);
3254 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3255 // For floating-point precision of 18:
3264 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3266 // error 0.0000018516, which is better than 18 bits
3267 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3268 getF32Constant(DAG, 0xbcd2769e));
3269 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3270 getF32Constant(DAG, 0x3e8ce0b9));
3271 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3272 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3273 getF32Constant(DAG, 0x3fa22ae7));
3274 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3275 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3276 getF32Constant(DAG, 0x40525723));
3277 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3278 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3279 getF32Constant(DAG, 0x40aaf200));
3280 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3281 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3282 getF32Constant(DAG, 0x40c39dad));
3283 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3284 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3285 getF32Constant(DAG, 0x4042902c));
3287 result = DAG.getNode(ISD::FADD, dl,
3288 MVT::f32, LogOfExponent, Log2ofMantissa);
3291 // No special expansion.
3292 result = DAG.getNode(ISD::FLOG2, dl,
3293 getValue(I.getOperand(1)).getValueType(),
3294 getValue(I.getOperand(1)));
3297 setValue(&I, result);
3300 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3301 /// limited-precision mode.
3303 SelectionDAGBuilder::visitLog10(CallInst &I) {
3305 DebugLoc dl = getCurDebugLoc();
3307 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3308 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3309 SDValue Op = getValue(I.getOperand(1));
3310 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3312 // Scale the exponent by log10(2) [0.30102999f].
3313 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3314 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3315 getF32Constant(DAG, 0x3e9a209a));
3317 // Get the significand and build it into a floating-point number with
3319 SDValue X = GetSignificand(DAG, Op1, dl);
3321 if (LimitFloatPrecision <= 6) {
3322 // For floating-point precision of 6:
3324 // Log10ofMantissa =
3326 // (0.60948995f - 0.10380950f * x) * x;
3328 // error 0.0014886165, which is 6 bits
3329 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3330 getF32Constant(DAG, 0xbdd49a13));
3331 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3332 getF32Constant(DAG, 0x3f1c0789));
3333 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3334 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3335 getF32Constant(DAG, 0x3f011300));
3337 result = DAG.getNode(ISD::FADD, dl,
3338 MVT::f32, LogOfExponent, Log10ofMantissa);
3339 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3340 // For floating-point precision of 12:
3342 // Log10ofMantissa =
3345 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3347 // error 0.00019228036, which is better than 12 bits
3348 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3349 getF32Constant(DAG, 0x3d431f31));
3350 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3351 getF32Constant(DAG, 0x3ea21fb2));
3352 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3353 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3354 getF32Constant(DAG, 0x3f6ae232));
3355 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3356 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3357 getF32Constant(DAG, 0x3f25f7c3));
3359 result = DAG.getNode(ISD::FADD, dl,
3360 MVT::f32, LogOfExponent, Log10ofMantissa);
3361 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3362 // For floating-point precision of 18:
3364 // Log10ofMantissa =
3369 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3371 // error 0.0000037995730, which is better than 18 bits
3372 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3373 getF32Constant(DAG, 0x3c5d51ce));
3374 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3375 getF32Constant(DAG, 0x3e00685a));
3376 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3377 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3378 getF32Constant(DAG, 0x3efb6798));
3379 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3380 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3381 getF32Constant(DAG, 0x3f88d192));
3382 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3383 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3384 getF32Constant(DAG, 0x3fc4316c));
3385 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3386 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3387 getF32Constant(DAG, 0x3f57ce70));
3389 result = DAG.getNode(ISD::FADD, dl,
3390 MVT::f32, LogOfExponent, Log10ofMantissa);
3393 // No special expansion.
3394 result = DAG.getNode(ISD::FLOG10, dl,
3395 getValue(I.getOperand(1)).getValueType(),
3396 getValue(I.getOperand(1)));
3399 setValue(&I, result);
3402 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3403 /// limited-precision mode.
3405 SelectionDAGBuilder::visitExp2(CallInst &I) {
3407 DebugLoc dl = getCurDebugLoc();
3409 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3410 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3411 SDValue Op = getValue(I.getOperand(1));
3413 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3415 // FractionalPartOfX = x - (float)IntegerPartOfX;
3416 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3417 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3419 // IntegerPartOfX <<= 23;
3420 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3421 DAG.getConstant(23, TLI.getPointerTy()));
3423 if (LimitFloatPrecision <= 6) {
3424 // For floating-point precision of 6:
3426 // TwoToFractionalPartOfX =
3428 // (0.735607626f + 0.252464424f * x) * x;
3430 // error 0.0144103317, which is 6 bits
3431 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3432 getF32Constant(DAG, 0x3e814304));
3433 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3434 getF32Constant(DAG, 0x3f3c50c8));
3435 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3436 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3437 getF32Constant(DAG, 0x3f7f5e7e));
3438 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3439 SDValue TwoToFractionalPartOfX =
3440 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3442 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3443 MVT::f32, TwoToFractionalPartOfX);
3444 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3445 // For floating-point precision of 12:
3447 // TwoToFractionalPartOfX =
3450 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3452 // error 0.000107046256, which is 13 to 14 bits
3453 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3454 getF32Constant(DAG, 0x3da235e3));
3455 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3456 getF32Constant(DAG, 0x3e65b8f3));
3457 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3458 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3459 getF32Constant(DAG, 0x3f324b07));
3460 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3461 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3462 getF32Constant(DAG, 0x3f7ff8fd));
3463 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3464 SDValue TwoToFractionalPartOfX =
3465 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3467 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3468 MVT::f32, TwoToFractionalPartOfX);
3469 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3470 // For floating-point precision of 18:
3472 // TwoToFractionalPartOfX =
3476 // (0.554906021e-1f +
3477 // (0.961591928e-2f +
3478 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3479 // error 2.47208000*10^(-7), which is better than 18 bits
3480 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3481 getF32Constant(DAG, 0x3924b03e));
3482 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3483 getF32Constant(DAG, 0x3ab24b87));
3484 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3485 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3486 getF32Constant(DAG, 0x3c1d8c17));
3487 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3488 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3489 getF32Constant(DAG, 0x3d634a1d));
3490 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3491 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3492 getF32Constant(DAG, 0x3e75fe14));
3493 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3494 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3495 getF32Constant(DAG, 0x3f317234));
3496 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3497 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3498 getF32Constant(DAG, 0x3f800000));
3499 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3500 SDValue TwoToFractionalPartOfX =
3501 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3503 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3504 MVT::f32, TwoToFractionalPartOfX);
3507 // No special expansion.
3508 result = DAG.getNode(ISD::FEXP2, dl,
3509 getValue(I.getOperand(1)).getValueType(),
3510 getValue(I.getOperand(1)));
3513 setValue(&I, result);
3516 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3517 /// limited-precision mode with x == 10.0f.
3519 SelectionDAGBuilder::visitPow(CallInst &I) {
3521 Value *Val = I.getOperand(1);
3522 DebugLoc dl = getCurDebugLoc();
3523 bool IsExp10 = false;
3525 if (getValue(Val).getValueType() == MVT::f32 &&
3526 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3527 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3528 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3529 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3531 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3536 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3537 SDValue Op = getValue(I.getOperand(2));
3539 // Put the exponent in the right bit position for later addition to the
3542 // #define LOG2OF10 3.3219281f
3543 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3544 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3545 getF32Constant(DAG, 0x40549a78));
3546 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3548 // FractionalPartOfX = x - (float)IntegerPartOfX;
3549 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3550 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3552 // IntegerPartOfX <<= 23;
3553 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3554 DAG.getConstant(23, TLI.getPointerTy()));
3556 if (LimitFloatPrecision <= 6) {
3557 // For floating-point precision of 6:
3559 // twoToFractionalPartOfX =
3561 // (0.735607626f + 0.252464424f * x) * x;
3563 // error 0.0144103317, which is 6 bits
3564 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3565 getF32Constant(DAG, 0x3e814304));
3566 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3567 getF32Constant(DAG, 0x3f3c50c8));
3568 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3569 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3570 getF32Constant(DAG, 0x3f7f5e7e));
3571 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3572 SDValue TwoToFractionalPartOfX =
3573 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3575 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3576 MVT::f32, TwoToFractionalPartOfX);
3577 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3578 // For floating-point precision of 12:
3580 // TwoToFractionalPartOfX =
3583 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3585 // error 0.000107046256, which is 13 to 14 bits
3586 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3587 getF32Constant(DAG, 0x3da235e3));
3588 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3589 getF32Constant(DAG, 0x3e65b8f3));
3590 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3591 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3592 getF32Constant(DAG, 0x3f324b07));
3593 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3594 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3595 getF32Constant(DAG, 0x3f7ff8fd));
3596 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3597 SDValue TwoToFractionalPartOfX =
3598 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3600 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3601 MVT::f32, TwoToFractionalPartOfX);
3602 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3603 // For floating-point precision of 18:
3605 // TwoToFractionalPartOfX =
3609 // (0.554906021e-1f +
3610 // (0.961591928e-2f +
3611 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3612 // error 2.47208000*10^(-7), which is better than 18 bits
3613 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3614 getF32Constant(DAG, 0x3924b03e));
3615 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3616 getF32Constant(DAG, 0x3ab24b87));
3617 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3618 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3619 getF32Constant(DAG, 0x3c1d8c17));
3620 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3621 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3622 getF32Constant(DAG, 0x3d634a1d));
3623 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3624 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3625 getF32Constant(DAG, 0x3e75fe14));
3626 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3627 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3628 getF32Constant(DAG, 0x3f317234));
3629 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3630 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3631 getF32Constant(DAG, 0x3f800000));
3632 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3633 SDValue TwoToFractionalPartOfX =
3634 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3636 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3637 MVT::f32, TwoToFractionalPartOfX);
3640 // No special expansion.
3641 result = DAG.getNode(ISD::FPOW, dl,
3642 getValue(I.getOperand(1)).getValueType(),
3643 getValue(I.getOperand(1)),
3644 getValue(I.getOperand(2)));
3647 setValue(&I, result);
3651 /// ExpandPowI - Expand a llvm.powi intrinsic.
3652 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3653 SelectionDAG &DAG) {
3654 // If RHS is a constant, we can expand this out to a multiplication tree,
3655 // otherwise we end up lowering to a call to __powidf2 (for example). When
3656 // optimizing for size, we only want to do this if the expansion would produce
3657 // a small number of multiplies, otherwise we do the full expansion.
3658 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3659 // Get the exponent as a positive value.
3660 unsigned Val = RHSC->getSExtValue();
3661 if ((int)Val < 0) Val = -Val;
3663 // powi(x, 0) -> 1.0
3665 return DAG.getConstantFP(1.0, LHS.getValueType());
3667 Function *F = DAG.getMachineFunction().getFunction();
3668 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3669 // If optimizing for size, don't insert too many multiplies. This
3670 // inserts up to 5 multiplies.
3671 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3672 // We use the simple binary decomposition method to generate the multiply
3673 // sequence. There are more optimal ways to do this (for example,
3674 // powi(x,15) generates one more multiply than it should), but this has
3675 // the benefit of being both really simple and much better than a libcall.
3676 SDValue Res; // Logically starts equal to 1.0
3677 SDValue CurSquare = LHS;
3681 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3683 Res = CurSquare; // 1.0*CurSquare.
3686 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3687 CurSquare, CurSquare);
3691 // If the original was negative, invert the result, producing 1/(x*x*x).
3692 if (RHSC->getSExtValue() < 0)
3693 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3694 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3699 // Otherwise, expand to a libcall.
3700 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3704 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3705 /// we want to emit this as a call to a named external function, return the name
3706 /// otherwise lower it and return null.
3708 SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3709 DebugLoc dl = getCurDebugLoc();
3712 switch (Intrinsic) {
3714 // By default, turn this into a target intrinsic node.
3715 visitTargetIntrinsic(I, Intrinsic);
3717 case Intrinsic::vastart: visitVAStart(I); return 0;
3718 case Intrinsic::vaend: visitVAEnd(I); return 0;
3719 case Intrinsic::vacopy: visitVACopy(I); return 0;
3720 case Intrinsic::returnaddress:
3721 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3722 getValue(I.getOperand(1))));
3724 case Intrinsic::frameaddress:
3725 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3726 getValue(I.getOperand(1))));
3728 case Intrinsic::setjmp:
3729 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3730 case Intrinsic::longjmp:
3731 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3732 case Intrinsic::memcpy: {
3733 // Assert for address < 256 since we support only user defined address
3735 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace()
3737 cast<PointerType>(I.getOperand(2)->getType())->getAddressSpace()
3739 "Unknown address space");
3740 SDValue Op1 = getValue(I.getOperand(1));
3741 SDValue Op2 = getValue(I.getOperand(2));
3742 SDValue Op3 = getValue(I.getOperand(3));
3743 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3744 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue();
3745 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
3746 I.getOperand(1), 0, I.getOperand(2), 0));
3749 case Intrinsic::memset: {
3750 // Assert for address < 256 since we support only user defined address
3752 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace()
3754 "Unknown address space");
3755 SDValue Op1 = getValue(I.getOperand(1));
3756 SDValue Op2 = getValue(I.getOperand(2));
3757 SDValue Op3 = getValue(I.getOperand(3));
3758 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3759 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue();
3760 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
3761 I.getOperand(1), 0));
3764 case Intrinsic::memmove: {
3765 // Assert for address < 256 since we support only user defined address
3767 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace()
3769 cast<PointerType>(I.getOperand(2)->getType())->getAddressSpace()
3771 "Unknown address space");
3772 SDValue Op1 = getValue(I.getOperand(1));
3773 SDValue Op2 = getValue(I.getOperand(2));
3774 SDValue Op3 = getValue(I.getOperand(3));
3775 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3776 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue();
3778 // If the source and destination are known to not be aliases, we can
3779 // lower memmove as memcpy.
3780 uint64_t Size = -1ULL;
3781 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3782 Size = C->getZExtValue();
3783 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3784 AliasAnalysis::NoAlias) {
3785 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
3786 false, I.getOperand(1), 0, I.getOperand(2), 0));
3790 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
3791 I.getOperand(1), 0, I.getOperand(2), 0));
3794 case Intrinsic::dbg_declare: {
3795 // FIXME: currently, we get here only if OptLevel != CodeGenOpt::None.
3796 // The real handling of this intrinsic is in FastISel.
3797 if (OptLevel != CodeGenOpt::None)
3798 // FIXME: Variable debug info is not supported here.
3800 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3801 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None))
3804 MDNode *Variable = DI.getVariable();
3805 Value *Address = DI.getAddress();
3808 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
3809 Address = BCI->getOperand(0);
3810 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
3811 // Don't handle byval struct arguments or VLAs, for example.
3814 DenseMap<const AllocaInst*, int>::iterator SI =
3815 FuncInfo.StaticAllocaMap.find(AI);
3816 if (SI == FuncInfo.StaticAllocaMap.end())
3818 int FI = SI->second;
3820 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3821 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
3822 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
3825 case Intrinsic::dbg_value: {
3826 DbgValueInst &DI = cast<DbgValueInst>(I);
3827 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None))
3830 MDNode *Variable = DI.getVariable();
3831 uint64_t Offset = DI.getOffset();
3832 Value *V = DI.getValue();
3836 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
3837 // but do not always have a corresponding SDNode built. The SDNodeOrder
3838 // absolute, but not relative, values are different depending on whether
3839 // debug info exists.
3841 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
3842 DAG.AddDbgValue(DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder));
3844 SDValue &N = NodeMap[V];
3846 DAG.AddDbgValue(DAG.getDbgValue(Variable, N.getNode(),
3847 N.getResNo(), Offset, dl, SDNodeOrder),
3850 // We may expand this to cover more cases. One case where we have no
3851 // data available is an unreferenced parameter; we need this fallback.
3852 DAG.AddDbgValue(DAG.getDbgValue(Variable,
3853 UndefValue::get(V->getType()),
3854 Offset, dl, SDNodeOrder));
3857 // Build a debug info table entry.
3858 if (BitCastInst *BCI = dyn_cast<BitCastInst>(V))
3859 V = BCI->getOperand(0);
3860 AllocaInst *AI = dyn_cast<AllocaInst>(V);
3861 // Don't handle byval struct arguments or VLAs, for example.
3864 DenseMap<const AllocaInst*, int>::iterator SI =
3865 FuncInfo.StaticAllocaMap.find(AI);
3866 if (SI == FuncInfo.StaticAllocaMap.end())
3868 int FI = SI->second;
3870 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3871 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
3872 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
3875 case Intrinsic::eh_exception: {
3876 // Insert the EXCEPTIONADDR instruction.
3877 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
3878 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3880 Ops[0] = DAG.getRoot();
3881 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3883 DAG.setRoot(Op.getValue(1));
3887 case Intrinsic::eh_selector: {
3888 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3889 if (CurMBB->isLandingPad())
3890 AddCatchInfo(I, &MMI, CurMBB);
3893 FuncInfo.CatchInfoLost.insert(&I);
3895 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3896 unsigned Reg = TLI.getExceptionSelectorRegister();
3897 if (Reg) CurMBB->addLiveIn(Reg);
3900 // Insert the EHSELECTION instruction.
3901 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3903 Ops[0] = getValue(I.getOperand(1));
3905 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
3906 DAG.setRoot(Op.getValue(1));
3907 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
3911 case Intrinsic::eh_typeid_for: {
3912 // Find the type id for the given typeinfo.
3913 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3914 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
3915 Res = DAG.getConstant(TypeID, MVT::i32);
3920 case Intrinsic::eh_return_i32:
3921 case Intrinsic::eh_return_i64:
3922 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
3923 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
3926 getValue(I.getOperand(1)),
3927 getValue(I.getOperand(2))));
3929 case Intrinsic::eh_unwind_init:
3930 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
3932 case Intrinsic::eh_dwarf_cfa: {
3933 EVT VT = getValue(I.getOperand(1)).getValueType();
3934 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl,
3935 TLI.getPointerTy());
3936 SDValue Offset = DAG.getNode(ISD::ADD, dl,
3938 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
3939 TLI.getPointerTy()),
3941 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
3943 DAG.getConstant(0, TLI.getPointerTy()));
3944 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
3948 case Intrinsic::eh_sjlj_callsite: {
3949 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3950 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1));
3951 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
3952 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
3954 MMI.setCurrentCallSite(CI->getZExtValue());
3958 case Intrinsic::convertff:
3959 case Intrinsic::convertfsi:
3960 case Intrinsic::convertfui:
3961 case Intrinsic::convertsif:
3962 case Intrinsic::convertuif:
3963 case Intrinsic::convertss:
3964 case Intrinsic::convertsu:
3965 case Intrinsic::convertus:
3966 case Intrinsic::convertuu: {
3967 ISD::CvtCode Code = ISD::CVT_INVALID;
3968 switch (Intrinsic) {
3969 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
3970 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
3971 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
3972 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
3973 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
3974 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
3975 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
3976 case Intrinsic::convertus: Code = ISD::CVT_US; break;
3977 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
3979 EVT DestVT = TLI.getValueType(I.getType());
3980 Value *Op1 = I.getOperand(1);
3981 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
3982 DAG.getValueType(DestVT),
3983 DAG.getValueType(getValue(Op1).getValueType()),
3984 getValue(I.getOperand(2)),
3985 getValue(I.getOperand(3)),
3990 case Intrinsic::sqrt:
3991 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
3992 getValue(I.getOperand(1)).getValueType(),
3993 getValue(I.getOperand(1))));
3995 case Intrinsic::powi:
3996 setValue(&I, ExpandPowI(dl, getValue(I.getOperand(1)),
3997 getValue(I.getOperand(2)), DAG));
3999 case Intrinsic::sin:
4000 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4001 getValue(I.getOperand(1)).getValueType(),
4002 getValue(I.getOperand(1))));
4004 case Intrinsic::cos:
4005 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4006 getValue(I.getOperand(1)).getValueType(),
4007 getValue(I.getOperand(1))));
4009 case Intrinsic::log:
4012 case Intrinsic::log2:
4015 case Intrinsic::log10:
4018 case Intrinsic::exp:
4021 case Intrinsic::exp2:
4024 case Intrinsic::pow:
4027 case Intrinsic::convert_to_fp16:
4028 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4029 MVT::i16, getValue(I.getOperand(1))));
4031 case Intrinsic::convert_from_fp16:
4032 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4033 MVT::f32, getValue(I.getOperand(1))));
4035 case Intrinsic::pcmarker: {
4036 SDValue Tmp = getValue(I.getOperand(1));
4037 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4040 case Intrinsic::readcyclecounter: {
4041 SDValue Op = getRoot();
4042 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4043 DAG.getVTList(MVT::i64, MVT::Other),
4046 DAG.setRoot(Res.getValue(1));
4049 case Intrinsic::bswap:
4050 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4051 getValue(I.getOperand(1)).getValueType(),
4052 getValue(I.getOperand(1))));
4054 case Intrinsic::cttz: {
4055 SDValue Arg = getValue(I.getOperand(1));
4056 EVT Ty = Arg.getValueType();
4057 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4060 case Intrinsic::ctlz: {
4061 SDValue Arg = getValue(I.getOperand(1));
4062 EVT Ty = Arg.getValueType();
4063 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4066 case Intrinsic::ctpop: {
4067 SDValue Arg = getValue(I.getOperand(1));
4068 EVT Ty = Arg.getValueType();
4069 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4072 case Intrinsic::stacksave: {
4073 SDValue Op = getRoot();
4074 Res = DAG.getNode(ISD::STACKSAVE, dl,
4075 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4077 DAG.setRoot(Res.getValue(1));
4080 case Intrinsic::stackrestore: {
4081 Res = getValue(I.getOperand(1));
4082 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4085 case Intrinsic::stackprotector: {
4086 // Emit code into the DAG to store the stack guard onto the stack.
4087 MachineFunction &MF = DAG.getMachineFunction();
4088 MachineFrameInfo *MFI = MF.getFrameInfo();
4089 EVT PtrTy = TLI.getPointerTy();
4091 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4092 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4094 int FI = FuncInfo.StaticAllocaMap[Slot];
4095 MFI->setStackProtectorIndex(FI);
4097 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4099 // Store the stack protector onto the stack.
4100 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4101 PseudoSourceValue::getFixedStack(FI),
4107 case Intrinsic::objectsize: {
4108 // If we don't know by now, we're never going to know.
4109 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2));
4111 assert(CI && "Non-constant type in __builtin_object_size?");
4113 SDValue Arg = getValue(I.getOperand(0));
4114 EVT Ty = Arg.getValueType();
4116 if (CI->getZExtValue() == 0)
4117 Res = DAG.getConstant(-1ULL, Ty);
4119 Res = DAG.getConstant(0, Ty);
4124 case Intrinsic::var_annotation:
4125 // Discard annotate attributes
4128 case Intrinsic::init_trampoline: {
4129 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4133 Ops[1] = getValue(I.getOperand(1));
4134 Ops[2] = getValue(I.getOperand(2));
4135 Ops[3] = getValue(I.getOperand(3));
4136 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4137 Ops[5] = DAG.getSrcValue(F);
4139 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4140 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4144 DAG.setRoot(Res.getValue(1));
4147 case Intrinsic::gcroot:
4149 Value *Alloca = I.getOperand(1);
4150 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4152 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4153 GFI->addStackRoot(FI->getIndex(), TypeMap);
4156 case Intrinsic::gcread:
4157 case Intrinsic::gcwrite:
4158 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4160 case Intrinsic::flt_rounds:
4161 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4163 case Intrinsic::trap:
4164 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4166 case Intrinsic::uadd_with_overflow:
4167 return implVisitAluOverflow(I, ISD::UADDO);
4168 case Intrinsic::sadd_with_overflow:
4169 return implVisitAluOverflow(I, ISD::SADDO);
4170 case Intrinsic::usub_with_overflow:
4171 return implVisitAluOverflow(I, ISD::USUBO);
4172 case Intrinsic::ssub_with_overflow:
4173 return implVisitAluOverflow(I, ISD::SSUBO);
4174 case Intrinsic::umul_with_overflow:
4175 return implVisitAluOverflow(I, ISD::UMULO);
4176 case Intrinsic::smul_with_overflow:
4177 return implVisitAluOverflow(I, ISD::SMULO);
4179 case Intrinsic::prefetch: {
4182 Ops[1] = getValue(I.getOperand(1));
4183 Ops[2] = getValue(I.getOperand(2));
4184 Ops[3] = getValue(I.getOperand(3));
4185 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4189 case Intrinsic::memory_barrier: {
4192 for (int x = 1; x < 6; ++x)
4193 Ops[x] = getValue(I.getOperand(x));
4195 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4198 case Intrinsic::atomic_cmp_swap: {
4199 SDValue Root = getRoot();
4201 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4202 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4204 getValue(I.getOperand(1)),
4205 getValue(I.getOperand(2)),
4206 getValue(I.getOperand(3)),
4209 DAG.setRoot(L.getValue(1));
4212 case Intrinsic::atomic_load_add:
4213 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4214 case Intrinsic::atomic_load_sub:
4215 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4216 case Intrinsic::atomic_load_or:
4217 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4218 case Intrinsic::atomic_load_xor:
4219 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4220 case Intrinsic::atomic_load_and:
4221 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4222 case Intrinsic::atomic_load_nand:
4223 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4224 case Intrinsic::atomic_load_max:
4225 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4226 case Intrinsic::atomic_load_min:
4227 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4228 case Intrinsic::atomic_load_umin:
4229 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4230 case Intrinsic::atomic_load_umax:
4231 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4232 case Intrinsic::atomic_swap:
4233 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4235 case Intrinsic::invariant_start:
4236 case Intrinsic::lifetime_start:
4237 // Discard region information.
4238 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4240 case Intrinsic::invariant_end:
4241 case Intrinsic::lifetime_end:
4242 // Discard region information.
4247 /// Test if the given instruction is in a position to be optimized
4248 /// with a tail-call. This roughly means that it's in a block with
4249 /// a return and there's nothing that needs to be scheduled
4250 /// between it and the return.
4252 /// This function only tests target-independent requirements.
4254 isInTailCallPosition(CallSite CS, Attributes CalleeRetAttr,
4255 const TargetLowering &TLI) {
4256 const Instruction *I = CS.getInstruction();
4257 const BasicBlock *ExitBB = I->getParent();
4258 const TerminatorInst *Term = ExitBB->getTerminator();
4259 const ReturnInst *Ret = dyn_cast<ReturnInst>(Term);
4260 const Function *F = ExitBB->getParent();
4262 // The block must end in a return statement or unreachable.
4264 // FIXME: Decline tailcall if it's not guaranteed and if the block ends in
4265 // an unreachable, for now. The way tailcall optimization is currently
4266 // implemented means it will add an epilogue followed by a jump. That is
4267 // not profitable. Also, if the callee is a special function (e.g.
4268 // longjmp on x86), it can end up causing miscompilation that has not
4269 // been fully understood.
4271 (!GuaranteedTailCallOpt || !isa<UnreachableInst>(Term))) return false;
4273 // If I will have a chain, make sure no other instruction that will have a
4274 // chain interposes between I and the return.
4275 if (I->mayHaveSideEffects() || I->mayReadFromMemory() ||
4276 !I->isSafeToSpeculativelyExecute())
4277 for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ;
4281 // Debug info intrinsics do not get in the way of tail call optimization.
4282 if (isa<DbgInfoIntrinsic>(BBI))
4284 if (BBI->mayHaveSideEffects() || BBI->mayReadFromMemory() ||
4285 !BBI->isSafeToSpeculativelyExecute())
4289 // If the block ends with a void return or unreachable, it doesn't matter
4290 // what the call's return type is.
4291 if (!Ret || Ret->getNumOperands() == 0) return true;
4293 // If the return value is undef, it doesn't matter what the call's
4295 if (isa<UndefValue>(Ret->getOperand(0))) return true;
4297 // Conservatively require the attributes of the call to match those of
4298 // the return. Ignore noalias because it doesn't affect the call sequence.
4299 unsigned CallerRetAttr = F->getAttributes().getRetAttributes();
4300 if ((CalleeRetAttr ^ CallerRetAttr) & ~Attribute::NoAlias)
4303 // It's not safe to eliminate the sign / zero extension of the return value.
4304 if ((CallerRetAttr & Attribute::ZExt) || (CallerRetAttr & Attribute::SExt))
4307 // Otherwise, make sure the unmodified return value of I is the return value.
4308 for (const Instruction *U = dyn_cast<Instruction>(Ret->getOperand(0)); ;
4309 U = dyn_cast<Instruction>(U->getOperand(0))) {
4312 if (!U->hasOneUse())
4316 // Check for a truly no-op truncate.
4317 if (isa<TruncInst>(U) &&
4318 TLI.isTruncateFree(U->getOperand(0)->getType(), U->getType()))
4320 // Check for a truly no-op bitcast.
4321 if (isa<BitCastInst>(U) &&
4322 (U->getOperand(0)->getType() == U->getType() ||
4323 (U->getOperand(0)->getType()->isPointerTy() &&
4324 U->getType()->isPointerTy())))
4326 // Otherwise it's not a true no-op.
4333 void SelectionDAGBuilder::LowerCallTo(CallSite CS, SDValue Callee,
4335 MachineBasicBlock *LandingPad) {
4336 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4337 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4338 const Type *RetTy = FTy->getReturnType();
4339 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4340 MCSymbol *BeginLabel = 0;
4342 TargetLowering::ArgListTy Args;
4343 TargetLowering::ArgListEntry Entry;
4344 Args.reserve(CS.arg_size());
4346 // Check whether the function can return without sret-demotion.
4347 SmallVector<EVT, 4> OutVTs;
4348 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
4349 SmallVector<uint64_t, 4> Offsets;
4350 getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4351 OutVTs, OutsFlags, TLI, &Offsets);
4353 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4354 FTy->isVarArg(), OutVTs, OutsFlags, DAG);
4356 SDValue DemoteStackSlot;
4358 if (!CanLowerReturn) {
4359 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4360 FTy->getReturnType());
4361 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4362 FTy->getReturnType());
4363 MachineFunction &MF = DAG.getMachineFunction();
4364 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4365 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4367 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4368 Entry.Node = DemoteStackSlot;
4369 Entry.Ty = StackSlotPtrType;
4370 Entry.isSExt = false;
4371 Entry.isZExt = false;
4372 Entry.isInReg = false;
4373 Entry.isSRet = true;
4374 Entry.isNest = false;
4375 Entry.isByVal = false;
4376 Entry.Alignment = Align;
4377 Args.push_back(Entry);
4378 RetTy = Type::getVoidTy(FTy->getContext());
4381 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4383 SDValue ArgNode = getValue(*i);
4384 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4386 unsigned attrInd = i - CS.arg_begin() + 1;
4387 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4388 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4389 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4390 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4391 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4392 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4393 Entry.Alignment = CS.getParamAlignment(attrInd);
4394 Args.push_back(Entry);
4398 // Insert a label before the invoke call to mark the try range. This can be
4399 // used to detect deletion of the invoke via the MachineModuleInfo.
4400 BeginLabel = MMI.getContext().CreateTempSymbol();
4402 // For SjLj, keep track of which landing pads go with which invokes
4403 // so as to maintain the ordering of pads in the LSDA.
4404 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4405 if (CallSiteIndex) {
4406 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4407 // Now that the call site is handled, stop tracking it.
4408 MMI.setCurrentCallSite(0);
4411 // Both PendingLoads and PendingExports must be flushed here;
4412 // this call might not return.
4414 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4417 // Check if target-independent constraints permit a tail call here.
4418 // Target-dependent constraints are checked within TLI.LowerCallTo.
4420 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4423 std::pair<SDValue,SDValue> Result =
4424 TLI.LowerCallTo(getRoot(), RetTy,
4425 CS.paramHasAttr(0, Attribute::SExt),
4426 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4427 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4428 CS.getCallingConv(),
4430 !CS.getInstruction()->use_empty(),
4431 Callee, Args, DAG, getCurDebugLoc());
4432 assert((isTailCall || Result.second.getNode()) &&
4433 "Non-null chain expected with non-tail call!");
4434 assert((Result.second.getNode() || !Result.first.getNode()) &&
4435 "Null value expected with tail call!");
4436 if (Result.first.getNode()) {
4437 setValue(CS.getInstruction(), Result.first);
4438 } else if (!CanLowerReturn && Result.second.getNode()) {
4439 // The instruction result is the result of loading from the
4440 // hidden sret parameter.
4441 SmallVector<EVT, 1> PVTs;
4442 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4444 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4445 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4446 EVT PtrVT = PVTs[0];
4447 unsigned NumValues = OutVTs.size();
4448 SmallVector<SDValue, 4> Values(NumValues);
4449 SmallVector<SDValue, 4> Chains(NumValues);
4451 for (unsigned i = 0; i < NumValues; ++i) {
4452 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4454 DAG.getConstant(Offsets[i], PtrVT));
4455 SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second,
4456 Add, NULL, Offsets[i], false, false, 1);
4458 Chains[i] = L.getValue(1);
4461 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4462 MVT::Other, &Chains[0], NumValues);
4463 PendingLoads.push_back(Chain);
4465 // Collect the legal value parts into potentially illegal values
4466 // that correspond to the original function's return values.
4467 SmallVector<EVT, 4> RetTys;
4468 RetTy = FTy->getReturnType();
4469 ComputeValueVTs(TLI, RetTy, RetTys);
4470 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4471 SmallVector<SDValue, 4> ReturnValues;
4472 unsigned CurReg = 0;
4473 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4475 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4476 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4478 SDValue ReturnValue =
4479 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4480 RegisterVT, VT, AssertOp);
4481 ReturnValues.push_back(ReturnValue);
4485 setValue(CS.getInstruction(),
4486 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4487 DAG.getVTList(&RetTys[0], RetTys.size()),
4488 &ReturnValues[0], ReturnValues.size()));
4492 // As a special case, a null chain means that a tail call has been emitted and
4493 // the DAG root is already updated.
4494 if (Result.second.getNode())
4495 DAG.setRoot(Result.second);
4500 // Insert a label at the end of the invoke call to mark the try range. This
4501 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4502 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4503 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4505 // Inform MachineModuleInfo of range.
4506 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4510 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4511 /// value is equal or not-equal to zero.
4512 static bool IsOnlyUsedInZeroEqualityComparison(Value *V) {
4513 for (Value::use_iterator UI = V->use_begin(), E = V->use_end();
4515 if (ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4516 if (IC->isEquality())
4517 if (Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4518 if (C->isNullValue())
4520 // Unknown instruction.
4526 static SDValue getMemCmpLoad(Value *PtrVal, MVT LoadVT, const Type *LoadTy,
4527 SelectionDAGBuilder &Builder) {
4529 // Check to see if this load can be trivially constant folded, e.g. if the
4530 // input is from a string literal.
4531 if (Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4532 // Cast pointer to the type we really want to load.
4533 LoadInput = ConstantExpr::getBitCast(LoadInput,
4534 PointerType::getUnqual(LoadTy));
4536 if (Constant *LoadCst = ConstantFoldLoadFromConstPtr(LoadInput, Builder.TD))
4537 return Builder.getValue(LoadCst);
4540 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4541 // still constant memory, the input chain can be the entry node.
4543 bool ConstantMemory = false;
4545 // Do not serialize (non-volatile) loads of constant memory with anything.
4546 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4547 Root = Builder.DAG.getEntryNode();
4548 ConstantMemory = true;
4550 // Do not serialize non-volatile loads against each other.
4551 Root = Builder.DAG.getRoot();
4554 SDValue Ptr = Builder.getValue(PtrVal);
4555 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
4556 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/,
4558 false /*nontemporal*/, 1 /* align=1 */);
4560 if (!ConstantMemory)
4561 Builder.PendingLoads.push_back(LoadVal.getValue(1));
4566 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
4567 /// If so, return true and lower it, otherwise return false and it will be
4568 /// lowered like a normal call.
4569 bool SelectionDAGBuilder::visitMemCmpCall(CallInst &I) {
4570 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
4571 if (I.getNumOperands() != 4)
4574 Value *LHS = I.getOperand(1), *RHS = I.getOperand(2);
4575 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
4576 !I.getOperand(3)->getType()->isIntegerTy() ||
4577 !I.getType()->isIntegerTy())
4580 ConstantInt *Size = dyn_cast<ConstantInt>(I.getOperand(3));
4582 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
4583 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
4584 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
4585 bool ActuallyDoIt = true;
4588 switch (Size->getZExtValue()) {
4590 LoadVT = MVT::Other;
4592 ActuallyDoIt = false;
4596 LoadTy = Type::getInt16Ty(Size->getContext());
4600 LoadTy = Type::getInt32Ty(Size->getContext());
4604 LoadTy = Type::getInt64Ty(Size->getContext());
4608 LoadVT = MVT::v4i32;
4609 LoadTy = Type::getInt32Ty(Size->getContext());
4610 LoadTy = VectorType::get(LoadTy, 4);
4615 // This turns into unaligned loads. We only do this if the target natively
4616 // supports the MVT we'll be loading or if it is small enough (<= 4) that
4617 // we'll only produce a small number of byte loads.
4619 // Require that we can find a legal MVT, and only do this if the target
4620 // supports unaligned loads of that type. Expanding into byte loads would
4622 if (ActuallyDoIt && Size->getZExtValue() > 4) {
4623 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
4624 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
4625 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
4626 ActuallyDoIt = false;
4630 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
4631 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
4633 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
4635 EVT CallVT = TLI.getValueType(I.getType(), true);
4636 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
4646 void SelectionDAGBuilder::visitCall(CallInst &I) {
4647 const char *RenameFn = 0;
4648 if (Function *F = I.getCalledFunction()) {
4649 if (F->isDeclaration()) {
4650 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4652 if (unsigned IID = II->getIntrinsicID(F)) {
4653 RenameFn = visitIntrinsicCall(I, IID);
4658 if (unsigned IID = F->getIntrinsicID()) {
4659 RenameFn = visitIntrinsicCall(I, IID);
4665 // Check for well-known libc/libm calls. If the function is internal, it
4666 // can't be a library call.
4667 if (!F->hasLocalLinkage() && F->hasName()) {
4668 StringRef Name = F->getName();
4669 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
4670 if (I.getNumOperands() == 3 && // Basic sanity checks.
4671 I.getOperand(1)->getType()->isFloatingPointTy() &&
4672 I.getType() == I.getOperand(1)->getType() &&
4673 I.getType() == I.getOperand(2)->getType()) {
4674 SDValue LHS = getValue(I.getOperand(1));
4675 SDValue RHS = getValue(I.getOperand(2));
4676 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4677 LHS.getValueType(), LHS, RHS));
4680 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4681 if (I.getNumOperands() == 2 && // Basic sanity checks.
4682 I.getOperand(1)->getType()->isFloatingPointTy() &&
4683 I.getType() == I.getOperand(1)->getType()) {
4684 SDValue Tmp = getValue(I.getOperand(1));
4685 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4686 Tmp.getValueType(), Tmp));
4689 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4690 if (I.getNumOperands() == 2 && // Basic sanity checks.
4691 I.getOperand(1)->getType()->isFloatingPointTy() &&
4692 I.getType() == I.getOperand(1)->getType() &&
4693 I.onlyReadsMemory()) {
4694 SDValue Tmp = getValue(I.getOperand(1));
4695 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4696 Tmp.getValueType(), Tmp));
4699 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4700 if (I.getNumOperands() == 2 && // Basic sanity checks.
4701 I.getOperand(1)->getType()->isFloatingPointTy() &&
4702 I.getType() == I.getOperand(1)->getType() &&
4703 I.onlyReadsMemory()) {
4704 SDValue Tmp = getValue(I.getOperand(1));
4705 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4706 Tmp.getValueType(), Tmp));
4709 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
4710 if (I.getNumOperands() == 2 && // Basic sanity checks.
4711 I.getOperand(1)->getType()->isFloatingPointTy() &&
4712 I.getType() == I.getOperand(1)->getType() &&
4713 I.onlyReadsMemory()) {
4714 SDValue Tmp = getValue(I.getOperand(1));
4715 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
4716 Tmp.getValueType(), Tmp));
4719 } else if (Name == "memcmp") {
4720 if (visitMemCmpCall(I))
4724 } else if (isa<InlineAsm>(I.getOperand(0))) {
4731 Callee = getValue(I.getOperand(0));
4733 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4735 // Check if we can potentially perform a tail call. More detailed checking is
4736 // be done within LowerCallTo, after more information about the call is known.
4737 LowerCallTo(&I, Callee, I.isTailCall());
4740 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4741 /// this value and returns the result as a ValueVT value. This uses
4742 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4743 /// If the Flag pointer is NULL, no flag is used.
4744 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4745 SDValue &Chain, SDValue *Flag) const {
4746 // Assemble the legal parts into the final values.
4747 SmallVector<SDValue, 4> Values(ValueVTs.size());
4748 SmallVector<SDValue, 8> Parts;
4749 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4750 // Copy the legal parts from the registers.
4751 EVT ValueVT = ValueVTs[Value];
4752 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4753 EVT RegisterVT = RegVTs[Value];
4755 Parts.resize(NumRegs);
4756 for (unsigned i = 0; i != NumRegs; ++i) {
4759 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4761 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4762 *Flag = P.getValue(2);
4765 Chain = P.getValue(1);
4767 // If the source register was virtual and if we know something about it,
4768 // add an assert node.
4769 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4770 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4771 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4772 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4773 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4774 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4776 unsigned RegSize = RegisterVT.getSizeInBits();
4777 unsigned NumSignBits = LOI.NumSignBits;
4778 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4780 // FIXME: We capture more information than the dag can represent. For
4781 // now, just use the tightest assertzext/assertsext possible.
4783 EVT FromVT(MVT::Other);
4784 if (NumSignBits == RegSize)
4785 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4786 else if (NumZeroBits >= RegSize-1)
4787 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4788 else if (NumSignBits > RegSize-8)
4789 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4790 else if (NumZeroBits >= RegSize-8)
4791 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4792 else if (NumSignBits > RegSize-16)
4793 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4794 else if (NumZeroBits >= RegSize-16)
4795 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4796 else if (NumSignBits > RegSize-32)
4797 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4798 else if (NumZeroBits >= RegSize-32)
4799 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4801 if (FromVT != MVT::Other)
4802 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4803 RegisterVT, P, DAG.getValueType(FromVT));
4810 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4811 NumRegs, RegisterVT, ValueVT);
4816 return DAG.getNode(ISD::MERGE_VALUES, dl,
4817 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4818 &Values[0], ValueVTs.size());
4821 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4822 /// specified value into the registers specified by this object. This uses
4823 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4824 /// If the Flag pointer is NULL, no flag is used.
4825 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4826 SDValue &Chain, SDValue *Flag) const {
4827 // Get the list of the values's legal parts.
4828 unsigned NumRegs = Regs.size();
4829 SmallVector<SDValue, 8> Parts(NumRegs);
4830 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4831 EVT ValueVT = ValueVTs[Value];
4832 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4833 EVT RegisterVT = RegVTs[Value];
4835 getCopyToParts(DAG, dl,
4836 Val.getValue(Val.getResNo() + Value),
4837 &Parts[Part], NumParts, RegisterVT);
4841 // Copy the parts into the registers.
4842 SmallVector<SDValue, 8> Chains(NumRegs);
4843 for (unsigned i = 0; i != NumRegs; ++i) {
4846 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4848 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4849 *Flag = Part.getValue(1);
4852 Chains[i] = Part.getValue(0);
4855 if (NumRegs == 1 || Flag)
4856 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4857 // flagged to it. That is the CopyToReg nodes and the user are considered
4858 // a single scheduling unit. If we create a TokenFactor and return it as
4859 // chain, then the TokenFactor is both a predecessor (operand) of the
4860 // user as well as a successor (the TF operands are flagged to the user).
4861 // c1, f1 = CopyToReg
4862 // c2, f2 = CopyToReg
4863 // c3 = TokenFactor c1, c2
4866 Chain = Chains[NumRegs-1];
4868 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4871 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4872 /// operand list. This adds the code marker and includes the number of
4873 /// values added into it.
4874 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
4875 unsigned MatchingIdx,
4877 std::vector<SDValue> &Ops) const {
4878 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
4880 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
4881 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
4884 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4885 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
4886 EVT RegisterVT = RegVTs[Value];
4887 for (unsigned i = 0; i != NumRegs; ++i) {
4888 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4889 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4894 /// isAllocatableRegister - If the specified register is safe to allocate,
4895 /// i.e. it isn't a stack pointer or some other special register, return the
4896 /// register class for the register. Otherwise, return null.
4897 static const TargetRegisterClass *
4898 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4899 const TargetLowering &TLI,
4900 const TargetRegisterInfo *TRI) {
4901 EVT FoundVT = MVT::Other;
4902 const TargetRegisterClass *FoundRC = 0;
4903 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4904 E = TRI->regclass_end(); RCI != E; ++RCI) {
4905 EVT ThisVT = MVT::Other;
4907 const TargetRegisterClass *RC = *RCI;
4908 // If none of the value types for this register class are valid, we
4909 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4910 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4912 if (TLI.isTypeLegal(*I)) {
4913 // If we have already found this register in a different register class,
4914 // choose the one with the largest VT specified. For example, on
4915 // PowerPC, we favor f64 register classes over f32.
4916 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4923 if (ThisVT == MVT::Other) continue;
4925 // NOTE: This isn't ideal. In particular, this might allocate the
4926 // frame pointer in functions that need it (due to them not being taken
4927 // out of allocation, because a variable sized allocation hasn't been seen
4928 // yet). This is a slight code pessimization, but should still work.
4929 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4930 E = RC->allocation_order_end(MF); I != E; ++I)
4932 // We found a matching register class. Keep looking at others in case
4933 // we find one with larger registers that this physreg is also in.
4944 /// AsmOperandInfo - This contains information for each constraint that we are
4946 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4947 public TargetLowering::AsmOperandInfo {
4949 /// CallOperand - If this is the result output operand or a clobber
4950 /// this is null, otherwise it is the incoming operand to the CallInst.
4951 /// This gets modified as the asm is processed.
4952 SDValue CallOperand;
4954 /// AssignedRegs - If this is a register or register class operand, this
4955 /// contains the set of register corresponding to the operand.
4956 RegsForValue AssignedRegs;
4958 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4959 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4962 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4963 /// busy in OutputRegs/InputRegs.
4964 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4965 std::set<unsigned> &OutputRegs,
4966 std::set<unsigned> &InputRegs,
4967 const TargetRegisterInfo &TRI) const {
4969 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4970 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4973 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4974 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4978 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
4979 /// corresponds to. If there is no Value* for this operand, it returns
4981 EVT getCallOperandValEVT(LLVMContext &Context,
4982 const TargetLowering &TLI,
4983 const TargetData *TD) const {
4984 if (CallOperandVal == 0) return MVT::Other;
4986 if (isa<BasicBlock>(CallOperandVal))
4987 return TLI.getPointerTy();
4989 const llvm::Type *OpTy = CallOperandVal->getType();
4991 // If this is an indirect operand, the operand is a pointer to the
4994 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
4996 report_fatal_error("Indirect operand for inline asm not a pointer!");
4997 OpTy = PtrTy->getElementType();
5000 // If OpTy is not a single value, it may be a struct/union that we
5001 // can tile with integers.
5002 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5003 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5012 OpTy = IntegerType::get(Context, BitSize);
5017 return TLI.getValueType(OpTy, true);
5021 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5023 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5024 const TargetRegisterInfo &TRI) {
5025 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5027 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5028 for (; *Aliases; ++Aliases)
5029 Regs.insert(*Aliases);
5032 } // end llvm namespace.
5035 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5036 /// specified operand. We prefer to assign virtual registers, to allow the
5037 /// register allocator to handle the assignment process. However, if the asm
5038 /// uses features that we can't model on machineinstrs, we have SDISel do the
5039 /// allocation. This produces generally horrible, but correct, code.
5041 /// OpInfo describes the operand.
5042 /// Input and OutputRegs are the set of already allocated physical registers.
5044 void SelectionDAGBuilder::
5045 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5046 std::set<unsigned> &OutputRegs,
5047 std::set<unsigned> &InputRegs) {
5048 LLVMContext &Context = FuncInfo.Fn->getContext();
5050 // Compute whether this value requires an input register, an output register,
5052 bool isOutReg = false;
5053 bool isInReg = false;
5054 switch (OpInfo.Type) {
5055 case InlineAsm::isOutput:
5058 // If there is an input constraint that matches this, we need to reserve
5059 // the input register so no other inputs allocate to it.
5060 isInReg = OpInfo.hasMatchingInput();
5062 case InlineAsm::isInput:
5066 case InlineAsm::isClobber:
5073 MachineFunction &MF = DAG.getMachineFunction();
5074 SmallVector<unsigned, 4> Regs;
5076 // If this is a constraint for a single physreg, or a constraint for a
5077 // register class, find it.
5078 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5079 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5080 OpInfo.ConstraintVT);
5082 unsigned NumRegs = 1;
5083 if (OpInfo.ConstraintVT != MVT::Other) {
5084 // If this is a FP input in an integer register (or visa versa) insert a bit
5085 // cast of the input value. More generally, handle any case where the input
5086 // value disagrees with the register class we plan to stick this in.
5087 if (OpInfo.Type == InlineAsm::isInput &&
5088 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5089 // Try to convert to the first EVT that the reg class contains. If the
5090 // types are identical size, use a bitcast to convert (e.g. two differing
5092 EVT RegVT = *PhysReg.second->vt_begin();
5093 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5094 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5095 RegVT, OpInfo.CallOperand);
5096 OpInfo.ConstraintVT = RegVT;
5097 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5098 // If the input is a FP value and we want it in FP registers, do a
5099 // bitcast to the corresponding integer type. This turns an f64 value
5100 // into i64, which can be passed with two i32 values on a 32-bit
5102 RegVT = EVT::getIntegerVT(Context,
5103 OpInfo.ConstraintVT.getSizeInBits());
5104 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5105 RegVT, OpInfo.CallOperand);
5106 OpInfo.ConstraintVT = RegVT;
5110 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5114 EVT ValueVT = OpInfo.ConstraintVT;
5116 // If this is a constraint for a specific physical register, like {r17},
5118 if (unsigned AssignedReg = PhysReg.first) {
5119 const TargetRegisterClass *RC = PhysReg.second;
5120 if (OpInfo.ConstraintVT == MVT::Other)
5121 ValueVT = *RC->vt_begin();
5123 // Get the actual register value type. This is important, because the user
5124 // may have asked for (e.g.) the AX register in i32 type. We need to
5125 // remember that AX is actually i16 to get the right extension.
5126 RegVT = *RC->vt_begin();
5128 // This is a explicit reference to a physical register.
5129 Regs.push_back(AssignedReg);
5131 // If this is an expanded reference, add the rest of the regs to Regs.
5133 TargetRegisterClass::iterator I = RC->begin();
5134 for (; *I != AssignedReg; ++I)
5135 assert(I != RC->end() && "Didn't find reg!");
5137 // Already added the first reg.
5139 for (; NumRegs; --NumRegs, ++I) {
5140 assert(I != RC->end() && "Ran out of registers to allocate!");
5145 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5146 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5147 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5151 // Otherwise, if this was a reference to an LLVM register class, create vregs
5152 // for this reference.
5153 if (const TargetRegisterClass *RC = PhysReg.second) {
5154 RegVT = *RC->vt_begin();
5155 if (OpInfo.ConstraintVT == MVT::Other)
5158 // Create the appropriate number of virtual registers.
5159 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5160 for (; NumRegs; --NumRegs)
5161 Regs.push_back(RegInfo.createVirtualRegister(RC));
5163 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5167 // This is a reference to a register class that doesn't directly correspond
5168 // to an LLVM register class. Allocate NumRegs consecutive, available,
5169 // registers from the class.
5170 std::vector<unsigned> RegClassRegs
5171 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5172 OpInfo.ConstraintVT);
5174 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5175 unsigned NumAllocated = 0;
5176 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5177 unsigned Reg = RegClassRegs[i];
5178 // See if this register is available.
5179 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5180 (isInReg && InputRegs.count(Reg))) { // Already used.
5181 // Make sure we find consecutive registers.
5186 // Check to see if this register is allocatable (i.e. don't give out the
5188 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5189 if (!RC) { // Couldn't allocate this register.
5190 // Reset NumAllocated to make sure we return consecutive registers.
5195 // Okay, this register is good, we can use it.
5198 // If we allocated enough consecutive registers, succeed.
5199 if (NumAllocated == NumRegs) {
5200 unsigned RegStart = (i-NumAllocated)+1;
5201 unsigned RegEnd = i+1;
5202 // Mark all of the allocated registers used.
5203 for (unsigned i = RegStart; i != RegEnd; ++i)
5204 Regs.push_back(RegClassRegs[i]);
5206 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5207 OpInfo.ConstraintVT);
5208 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5213 // Otherwise, we couldn't allocate enough registers for this.
5216 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5217 /// processed uses a memory 'm' constraint.
5219 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5220 const TargetLowering &TLI) {
5221 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5222 InlineAsm::ConstraintInfo &CI = CInfos[i];
5223 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5224 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5225 if (CType == TargetLowering::C_Memory)
5229 // Indirect operand accesses access memory.
5237 /// visitInlineAsm - Handle a call to an InlineAsm object.
5239 void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
5240 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5242 /// ConstraintOperands - Information about all of the constraints.
5243 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5245 std::set<unsigned> OutputRegs, InputRegs;
5247 // Do a prepass over the constraints, canonicalizing them, and building up the
5248 // ConstraintOperands list.
5249 std::vector<InlineAsm::ConstraintInfo>
5250 ConstraintInfos = IA->ParseConstraints();
5252 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5254 SDValue Chain, Flag;
5256 // We won't need to flush pending loads if this asm doesn't touch
5257 // memory and is nonvolatile.
5258 if (hasMemory || IA->hasSideEffects())
5261 Chain = DAG.getRoot();
5263 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5264 unsigned ResNo = 0; // ResNo - The result number of the next output.
5265 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5266 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5267 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5269 EVT OpVT = MVT::Other;
5271 // Compute the value type for each operand.
5272 switch (OpInfo.Type) {
5273 case InlineAsm::isOutput:
5274 // Indirect outputs just consume an argument.
5275 if (OpInfo.isIndirect) {
5276 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5280 // The return value of the call is this value. As such, there is no
5281 // corresponding argument.
5282 assert(!CS.getType()->isVoidTy() &&
5284 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5285 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5287 assert(ResNo == 0 && "Asm only has one result!");
5288 OpVT = TLI.getValueType(CS.getType());
5292 case InlineAsm::isInput:
5293 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5295 case InlineAsm::isClobber:
5300 // If this is an input or an indirect output, process the call argument.
5301 // BasicBlocks are labels, currently appearing only in asm's.
5302 if (OpInfo.CallOperandVal) {
5303 // Strip bitcasts, if any. This mostly comes up for functions.
5304 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5306 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5307 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5309 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5312 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5315 OpInfo.ConstraintVT = OpVT;
5318 // Second pass over the constraints: compute which constraint option to use
5319 // and assign registers to constraints that want a specific physreg.
5320 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5321 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5323 // If this is an output operand with a matching input operand, look up the
5324 // matching input. If their types mismatch, e.g. one is an integer, the
5325 // other is floating point, or their sizes are different, flag it as an
5327 if (OpInfo.hasMatchingInput()) {
5328 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5330 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5331 if ((OpInfo.ConstraintVT.isInteger() !=
5332 Input.ConstraintVT.isInteger()) ||
5333 (OpInfo.ConstraintVT.getSizeInBits() !=
5334 Input.ConstraintVT.getSizeInBits())) {
5335 report_fatal_error("Unsupported asm: input constraint"
5336 " with a matching output constraint of"
5337 " incompatible type!");
5339 Input.ConstraintVT = OpInfo.ConstraintVT;
5343 // Compute the constraint code and ConstraintType to use.
5344 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5346 // If this is a memory input, and if the operand is not indirect, do what we
5347 // need to to provide an address for the memory input.
5348 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5349 !OpInfo.isIndirect) {
5350 assert(OpInfo.Type == InlineAsm::isInput &&
5351 "Can only indirectify direct input operands!");
5353 // Memory operands really want the address of the value. If we don't have
5354 // an indirect input, put it in the constpool if we can, otherwise spill
5355 // it to a stack slot.
5357 // If the operand is a float, integer, or vector constant, spill to a
5358 // constant pool entry to get its address.
5359 Value *OpVal = OpInfo.CallOperandVal;
5360 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5361 isa<ConstantVector>(OpVal)) {
5362 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5363 TLI.getPointerTy());
5365 // Otherwise, create a stack slot and emit a store to it before the
5367 const Type *Ty = OpVal->getType();
5368 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5369 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5370 MachineFunction &MF = DAG.getMachineFunction();
5371 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5372 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5373 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5374 OpInfo.CallOperand, StackSlot, NULL, 0,
5376 OpInfo.CallOperand = StackSlot;
5379 // There is no longer a Value* corresponding to this operand.
5380 OpInfo.CallOperandVal = 0;
5382 // It is now an indirect operand.
5383 OpInfo.isIndirect = true;
5386 // If this constraint is for a specific register, allocate it before
5388 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5389 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5392 ConstraintInfos.clear();
5394 // Second pass - Loop over all of the operands, assigning virtual or physregs
5395 // to register class operands.
5396 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5397 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5399 // C_Register operands have already been allocated, Other/Memory don't need
5401 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5402 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5405 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5406 std::vector<SDValue> AsmNodeOperands;
5407 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5408 AsmNodeOperands.push_back(
5409 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5410 TLI.getPointerTy()));
5412 // If we have a !srcloc metadata node associated with it, we want to attach
5413 // this to the ultimately generated inline asm machineinstr. To do this, we
5414 // pass in the third operand as this (potentially null) inline asm MDNode.
5415 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5416 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5418 // Loop over all of the inputs, copying the operand values into the
5419 // appropriate registers and processing the output regs.
5420 RegsForValue RetValRegs;
5422 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5423 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5425 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5426 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5428 switch (OpInfo.Type) {
5429 case InlineAsm::isOutput: {
5430 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5431 OpInfo.ConstraintType != TargetLowering::C_Register) {
5432 // Memory output, or 'other' output (e.g. 'X' constraint).
5433 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5435 // Add information to the INLINEASM node to know about this output.
5436 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5437 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5438 TLI.getPointerTy()));
5439 AsmNodeOperands.push_back(OpInfo.CallOperand);
5443 // Otherwise, this is a register or register class output.
5445 // Copy the output from the appropriate register. Find a register that
5447 if (OpInfo.AssignedRegs.Regs.empty())
5448 report_fatal_error("Couldn't allocate output reg for constraint '" +
5449 Twine(OpInfo.ConstraintCode) + "'!");
5451 // If this is an indirect operand, store through the pointer after the
5453 if (OpInfo.isIndirect) {
5454 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5455 OpInfo.CallOperandVal));
5457 // This is the result value of the call.
5458 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5459 // Concatenate this output onto the outputs list.
5460 RetValRegs.append(OpInfo.AssignedRegs);
5463 // Add information to the INLINEASM node to know that this register is
5465 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5466 InlineAsm::Kind_RegDefEarlyClobber :
5467 InlineAsm::Kind_RegDef,
5474 case InlineAsm::isInput: {
5475 SDValue InOperandVal = OpInfo.CallOperand;
5477 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5478 // If this is required to match an output register we have already set,
5479 // just use its register.
5480 unsigned OperandNo = OpInfo.getMatchedOperand();
5482 // Scan until we find the definition we already emitted of this operand.
5483 // When we find it, create a RegsForValue operand.
5484 unsigned CurOp = InlineAsm::Op_FirstOperand;
5485 for (; OperandNo; --OperandNo) {
5486 // Advance to the next operand.
5488 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5489 assert((InlineAsm::isRegDefKind(OpFlag) ||
5490 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5491 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5492 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5496 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5497 if (InlineAsm::isRegDefKind(OpFlag) ||
5498 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5499 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5500 if (OpInfo.isIndirect) {
5501 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5502 LLVMContext &Ctx = CurMBB->getParent()->getFunction()->getContext();
5503 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5504 " don't know how to handle tied "
5505 "indirect register inputs");
5508 RegsForValue MatchedRegs;
5509 MatchedRegs.TLI = &TLI;
5510 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5511 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5512 MatchedRegs.RegVTs.push_back(RegVT);
5513 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5514 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5516 MatchedRegs.Regs.push_back
5517 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5519 // Use the produced MatchedRegs object to
5520 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5522 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5523 true, OpInfo.getMatchedOperand(),
5524 DAG, AsmNodeOperands);
5528 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5529 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5530 "Unexpected number of operands");
5531 // Add information to the INLINEASM node to know about this input.
5532 // See InlineAsm.h isUseOperandTiedToDef.
5533 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5534 OpInfo.getMatchedOperand());
5535 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5536 TLI.getPointerTy()));
5537 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5541 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5542 assert(!OpInfo.isIndirect &&
5543 "Don't know how to handle indirect other inputs yet!");
5545 std::vector<SDValue> Ops;
5546 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5547 hasMemory, Ops, DAG);
5549 report_fatal_error("Invalid operand for inline asm constraint '" +
5550 Twine(OpInfo.ConstraintCode) + "'!");
5552 // Add information to the INLINEASM node to know about this input.
5553 unsigned ResOpType =
5554 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5555 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5556 TLI.getPointerTy()));
5557 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5561 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5562 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5563 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5564 "Memory operands expect pointer values");
5566 // Add information to the INLINEASM node to know about this input.
5567 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5568 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5569 TLI.getPointerTy()));
5570 AsmNodeOperands.push_back(InOperandVal);
5574 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5575 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5576 "Unknown constraint type!");
5577 assert(!OpInfo.isIndirect &&
5578 "Don't know how to handle indirect register inputs yet!");
5580 // Copy the input into the appropriate registers.
5581 if (OpInfo.AssignedRegs.Regs.empty() ||
5582 !OpInfo.AssignedRegs.areValueTypesLegal())
5583 report_fatal_error("Couldn't allocate input reg for constraint '" +
5584 Twine(OpInfo.ConstraintCode) + "'!");
5586 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5589 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5590 DAG, AsmNodeOperands);
5593 case InlineAsm::isClobber: {
5594 // Add the clobbered value to the operand list, so that the register
5595 // allocator is aware that the physreg got clobbered.
5596 if (!OpInfo.AssignedRegs.Regs.empty())
5597 OpInfo.AssignedRegs.AddInlineAsmOperands(
5598 InlineAsm::Kind_RegDefEarlyClobber,
5606 // Finish up input operands. Set the input chain and add the flag last.
5607 AsmNodeOperands[0] = Chain;
5608 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5610 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5611 DAG.getVTList(MVT::Other, MVT::Flag),
5612 &AsmNodeOperands[0], AsmNodeOperands.size());
5613 Flag = Chain.getValue(1);
5615 // If this asm returns a register value, copy the result from that register
5616 // and set it as the value of the call.
5617 if (!RetValRegs.Regs.empty()) {
5618 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5621 // FIXME: Why don't we do this for inline asms with MRVs?
5622 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5623 EVT ResultType = TLI.getValueType(CS.getType());
5625 // If any of the results of the inline asm is a vector, it may have the
5626 // wrong width/num elts. This can happen for register classes that can
5627 // contain multiple different value types. The preg or vreg allocated may
5628 // not have the same VT as was expected. Convert it to the right type
5629 // with bit_convert.
5630 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5631 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5634 } else if (ResultType != Val.getValueType() &&
5635 ResultType.isInteger() && Val.getValueType().isInteger()) {
5636 // If a result value was tied to an input value, the computed result may
5637 // have a wider width than the expected result. Extract the relevant
5639 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5642 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5645 setValue(CS.getInstruction(), Val);
5646 // Don't need to use this as a chain in this case.
5647 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5651 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5653 // Process indirect outputs, first output all of the flagged copies out of
5655 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5656 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5657 Value *Ptr = IndirectStoresToEmit[i].second;
5658 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5660 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5664 // Emit the non-flagged stores from the physregs.
5665 SmallVector<SDValue, 8> OutChains;
5666 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5667 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5668 StoresToEmit[i].first,
5669 getValue(StoresToEmit[i].second),
5670 StoresToEmit[i].second, 0,
5672 OutChains.push_back(Val);
5675 if (!OutChains.empty())
5676 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5677 &OutChains[0], OutChains.size());
5682 void SelectionDAGBuilder::visitVAStart(CallInst &I) {
5683 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5684 MVT::Other, getRoot(),
5685 getValue(I.getOperand(1)),
5686 DAG.getSrcValue(I.getOperand(1))));
5689 void SelectionDAGBuilder::visitVAArg(VAArgInst &I) {
5690 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5691 getRoot(), getValue(I.getOperand(0)),
5692 DAG.getSrcValue(I.getOperand(0)));
5694 DAG.setRoot(V.getValue(1));
5697 void SelectionDAGBuilder::visitVAEnd(CallInst &I) {
5698 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5699 MVT::Other, getRoot(),
5700 getValue(I.getOperand(1)),
5701 DAG.getSrcValue(I.getOperand(1))));
5704 void SelectionDAGBuilder::visitVACopy(CallInst &I) {
5705 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5706 MVT::Other, getRoot(),
5707 getValue(I.getOperand(1)),
5708 getValue(I.getOperand(2)),
5709 DAG.getSrcValue(I.getOperand(1)),
5710 DAG.getSrcValue(I.getOperand(2))));
5713 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5714 /// implementation, which just calls LowerCall.
5715 /// FIXME: When all targets are
5716 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5717 std::pair<SDValue, SDValue>
5718 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5719 bool RetSExt, bool RetZExt, bool isVarArg,
5720 bool isInreg, unsigned NumFixedArgs,
5721 CallingConv::ID CallConv, bool isTailCall,
5722 bool isReturnValueUsed,
5724 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5725 // Handle all of the outgoing arguments.
5726 SmallVector<ISD::OutputArg, 32> Outs;
5727 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5728 SmallVector<EVT, 4> ValueVTs;
5729 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5730 for (unsigned Value = 0, NumValues = ValueVTs.size();
5731 Value != NumValues; ++Value) {
5732 EVT VT = ValueVTs[Value];
5733 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5734 SDValue Op = SDValue(Args[i].Node.getNode(),
5735 Args[i].Node.getResNo() + Value);
5736 ISD::ArgFlagsTy Flags;
5737 unsigned OriginalAlignment =
5738 getTargetData()->getABITypeAlignment(ArgTy);
5744 if (Args[i].isInReg)
5748 if (Args[i].isByVal) {
5750 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5751 const Type *ElementTy = Ty->getElementType();
5752 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5753 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5754 // For ByVal, alignment should come from FE. BE will guess if this
5755 // info is not there but there are cases it cannot get right.
5756 if (Args[i].Alignment)
5757 FrameAlign = Args[i].Alignment;
5758 Flags.setByValAlign(FrameAlign);
5759 Flags.setByValSize(FrameSize);
5763 Flags.setOrigAlign(OriginalAlignment);
5765 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5766 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5767 SmallVector<SDValue, 4> Parts(NumParts);
5768 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5771 ExtendKind = ISD::SIGN_EXTEND;
5772 else if (Args[i].isZExt)
5773 ExtendKind = ISD::ZERO_EXTEND;
5775 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
5776 PartVT, ExtendKind);
5778 for (unsigned j = 0; j != NumParts; ++j) {
5779 // if it isn't first piece, alignment must be 1
5780 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5781 if (NumParts > 1 && j == 0)
5782 MyFlags.Flags.setSplit();
5784 MyFlags.Flags.setOrigAlign(1);
5786 Outs.push_back(MyFlags);
5791 // Handle the incoming return values from the call.
5792 SmallVector<ISD::InputArg, 32> Ins;
5793 SmallVector<EVT, 4> RetTys;
5794 ComputeValueVTs(*this, RetTy, RetTys);
5795 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5797 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5798 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5799 for (unsigned i = 0; i != NumRegs; ++i) {
5800 ISD::InputArg MyFlags;
5801 MyFlags.VT = RegisterVT;
5802 MyFlags.Used = isReturnValueUsed;
5804 MyFlags.Flags.setSExt();
5806 MyFlags.Flags.setZExt();
5808 MyFlags.Flags.setInReg();
5809 Ins.push_back(MyFlags);
5813 SmallVector<SDValue, 4> InVals;
5814 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5815 Outs, Ins, dl, DAG, InVals);
5817 // Verify that the target's LowerCall behaved as expected.
5818 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
5819 "LowerCall didn't return a valid chain!");
5820 assert((!isTailCall || InVals.empty()) &&
5821 "LowerCall emitted a return value for a tail call!");
5822 assert((isTailCall || InVals.size() == Ins.size()) &&
5823 "LowerCall didn't emit the correct number of values!");
5825 // For a tail call, the return value is merely live-out and there aren't
5826 // any nodes in the DAG representing it. Return a special value to
5827 // indicate that a tail call has been emitted and no more Instructions
5828 // should be processed in the current block.
5831 return std::make_pair(SDValue(), SDValue());
5834 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5835 assert(InVals[i].getNode() &&
5836 "LowerCall emitted a null value!");
5837 assert(Ins[i].VT == InVals[i].getValueType() &&
5838 "LowerCall emitted a value with the wrong type!");
5841 // Collect the legal value parts into potentially illegal values
5842 // that correspond to the original function's return values.
5843 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5845 AssertOp = ISD::AssertSext;
5847 AssertOp = ISD::AssertZext;
5848 SmallVector<SDValue, 4> ReturnValues;
5849 unsigned CurReg = 0;
5850 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5852 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5853 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5855 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
5856 NumRegs, RegisterVT, VT,
5861 // For a function returning void, there is no return value. We can't create
5862 // such a node, so we just return a null return value in that case. In
5863 // that case, nothing will actualy look at the value.
5864 if (ReturnValues.empty())
5865 return std::make_pair(SDValue(), Chain);
5867 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5868 DAG.getVTList(&RetTys[0], RetTys.size()),
5869 &ReturnValues[0], ReturnValues.size());
5870 return std::make_pair(Res, Chain);
5873 void TargetLowering::LowerOperationWrapper(SDNode *N,
5874 SmallVectorImpl<SDValue> &Results,
5875 SelectionDAG &DAG) {
5876 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5878 Results.push_back(Res);
5881 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5882 llvm_unreachable("LowerOperation not implemented for this target!");
5886 void SelectionDAGBuilder::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5887 SDValue Op = getValue(V);
5888 assert((Op.getOpcode() != ISD::CopyFromReg ||
5889 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5890 "Copy from a reg to the same reg!");
5891 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5893 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
5894 SDValue Chain = DAG.getEntryNode();
5895 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5896 PendingExports.push_back(Chain);
5899 #include "llvm/CodeGen/SelectionDAGISel.h"
5901 void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
5902 // If this is the entry block, emit arguments.
5903 Function &F = *LLVMBB->getParent();
5904 SelectionDAG &DAG = SDB->DAG;
5905 SDValue OldRoot = DAG.getRoot();
5906 DebugLoc dl = SDB->getCurDebugLoc();
5907 const TargetData *TD = TLI.getTargetData();
5908 SmallVector<ISD::InputArg, 16> Ins;
5910 // Check whether the function can return without sret-demotion.
5911 SmallVector<EVT, 4> OutVTs;
5912 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
5913 getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
5914 OutVTs, OutsFlags, TLI);
5915 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5917 FLI.CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(),
5918 OutVTs, OutsFlags, DAG);
5919 if (!FLI.CanLowerReturn) {
5920 // Put in an sret pointer parameter before all the other parameters.
5921 SmallVector<EVT, 1> ValueVTs;
5922 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
5924 // NOTE: Assuming that a pointer will never break down to more than one VT
5926 ISD::ArgFlagsTy Flags;
5928 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), ValueVTs[0]);
5929 ISD::InputArg RetArg(Flags, RegisterVT, true);
5930 Ins.push_back(RetArg);
5933 // Set up the incoming argument description vector.
5935 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5936 I != E; ++I, ++Idx) {
5937 SmallVector<EVT, 4> ValueVTs;
5938 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5939 bool isArgValueUsed = !I->use_empty();
5940 for (unsigned Value = 0, NumValues = ValueVTs.size();
5941 Value != NumValues; ++Value) {
5942 EVT VT = ValueVTs[Value];
5943 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
5944 ISD::ArgFlagsTy Flags;
5945 unsigned OriginalAlignment =
5946 TD->getABITypeAlignment(ArgTy);
5948 if (F.paramHasAttr(Idx, Attribute::ZExt))
5950 if (F.paramHasAttr(Idx, Attribute::SExt))
5952 if (F.paramHasAttr(Idx, Attribute::InReg))
5954 if (F.paramHasAttr(Idx, Attribute::StructRet))
5956 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
5958 const PointerType *Ty = cast<PointerType>(I->getType());
5959 const Type *ElementTy = Ty->getElementType();
5960 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
5961 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
5962 // For ByVal, alignment should be passed from FE. BE will guess if
5963 // this info is not there but there are cases it cannot get right.
5964 if (F.getParamAlignment(Idx))
5965 FrameAlign = F.getParamAlignment(Idx);
5966 Flags.setByValAlign(FrameAlign);
5967 Flags.setByValSize(FrameSize);
5969 if (F.paramHasAttr(Idx, Attribute::Nest))
5971 Flags.setOrigAlign(OriginalAlignment);
5973 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5974 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5975 for (unsigned i = 0; i != NumRegs; ++i) {
5976 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
5977 if (NumRegs > 1 && i == 0)
5978 MyFlags.Flags.setSplit();
5979 // if it isn't first piece, alignment must be 1
5981 MyFlags.Flags.setOrigAlign(1);
5982 Ins.push_back(MyFlags);
5987 // Call the target to set up the argument values.
5988 SmallVector<SDValue, 8> InVals;
5989 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
5993 // Verify that the target's LowerFormalArguments behaved as expected.
5994 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
5995 "LowerFormalArguments didn't return a valid chain!");
5996 assert(InVals.size() == Ins.size() &&
5997 "LowerFormalArguments didn't emit the correct number of values!");
5999 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6000 assert(InVals[i].getNode() &&
6001 "LowerFormalArguments emitted a null value!");
6002 assert(Ins[i].VT == InVals[i].getValueType() &&
6003 "LowerFormalArguments emitted a value with the wrong type!");
6007 // Update the DAG with the new chain value resulting from argument lowering.
6008 DAG.setRoot(NewRoot);
6010 // Set up the argument values.
6013 if (!FLI.CanLowerReturn) {
6014 // Create a virtual register for the sret pointer, and put in a copy
6015 // from the sret argument into it.
6016 SmallVector<EVT, 1> ValueVTs;
6017 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6018 EVT VT = ValueVTs[0];
6019 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6020 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6021 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6022 RegVT, VT, AssertOp);
6024 MachineFunction& MF = SDB->DAG.getMachineFunction();
6025 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6026 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6027 FLI.DemoteRegister = SRetReg;
6028 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6030 DAG.setRoot(NewRoot);
6032 // i indexes lowered arguments. Bump it past the hidden sret argument.
6033 // Idx indexes LLVM arguments. Don't touch it.
6037 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6039 SmallVector<SDValue, 4> ArgValues;
6040 SmallVector<EVT, 4> ValueVTs;
6041 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6042 unsigned NumValues = ValueVTs.size();
6043 for (unsigned Value = 0; Value != NumValues; ++Value) {
6044 EVT VT = ValueVTs[Value];
6045 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6046 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6048 if (!I->use_empty()) {
6049 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6050 if (F.paramHasAttr(Idx, Attribute::SExt))
6051 AssertOp = ISD::AssertSext;
6052 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6053 AssertOp = ISD::AssertZext;
6055 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6056 NumParts, PartVT, VT,
6063 if (!I->use_empty()) {
6065 if (!ArgValues.empty())
6066 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6067 SDB->getCurDebugLoc());
6068 SDB->setValue(I, Res);
6070 // If this argument is live outside of the entry block, insert a copy from
6071 // whereever we got it to the vreg that other BB's will reference it as.
6072 SDB->CopyToExportRegsIfNeeded(I);
6076 assert(i == InVals.size() && "Argument register count mismatch!");
6078 // Finally, if the target has anything special to do, allow it to do so.
6079 // FIXME: this should insert code into the DAG!
6080 EmitFunctionEntryCode(F, SDB->DAG.getMachineFunction());
6083 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6084 /// ensure constants are generated when needed. Remember the virtual registers
6085 /// that need to be added to the Machine PHI nodes as input. We cannot just
6086 /// directly add them, because expansion might result in multiple MBB's for one
6087 /// BB. As such, the start of the BB might correspond to a different MBB than
6091 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
6092 TerminatorInst *TI = LLVMBB->getTerminator();
6094 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6096 // Check successor nodes' PHI nodes that expect a constant to be available
6098 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6099 BasicBlock *SuccBB = TI->getSuccessor(succ);
6100 if (!isa<PHINode>(SuccBB->begin())) continue;
6101 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6103 // If this terminator has multiple identical successors (common for
6104 // switches), only handle each succ once.
6105 if (!SuccsHandled.insert(SuccMBB)) continue;
6107 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6110 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6111 // nodes and Machine PHI nodes, but the incoming operands have not been
6113 for (BasicBlock::iterator I = SuccBB->begin();
6114 (PN = dyn_cast<PHINode>(I)); ++I) {
6115 // Ignore dead phi's.
6116 if (PN->use_empty()) continue;
6119 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6121 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
6122 unsigned &RegOut = SDB->ConstantsOut[C];
6124 RegOut = FuncInfo->CreateRegForValue(C);
6125 SDB->CopyValueToVirtualRegister(C, RegOut);
6129 Reg = FuncInfo->ValueMap[PHIOp];
6131 assert(isa<AllocaInst>(PHIOp) &&
6132 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6133 "Didn't codegen value into a register!??");
6134 Reg = FuncInfo->CreateRegForValue(PHIOp);
6135 SDB->CopyValueToVirtualRegister(PHIOp, Reg);
6139 // Remember that this register needs to added to the machine PHI node as
6140 // the input for this MBB.
6141 SmallVector<EVT, 4> ValueVTs;
6142 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6143 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6144 EVT VT = ValueVTs[vti];
6145 unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6146 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6147 SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6148 Reg += NumRegisters;
6152 SDB->ConstantsOut.clear();
6155 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
6156 /// supports legal types, and it emits MachineInstrs directly instead of
6157 /// creating SelectionDAG nodes.
6160 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
6162 TerminatorInst *TI = LLVMBB->getTerminator();
6164 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6165 unsigned OrigNumPHINodesToUpdate = SDB->PHINodesToUpdate.size();
6167 // Check successor nodes' PHI nodes that expect a constant to be available
6169 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6170 BasicBlock *SuccBB = TI->getSuccessor(succ);
6171 if (!isa<PHINode>(SuccBB->begin())) continue;
6172 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6174 // If this terminator has multiple identical successors (common for
6175 // switches), only handle each succ once.
6176 if (!SuccsHandled.insert(SuccMBB)) continue;
6178 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6181 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6182 // nodes and Machine PHI nodes, but the incoming operands have not been
6184 for (BasicBlock::iterator I = SuccBB->begin();
6185 (PN = dyn_cast<PHINode>(I)); ++I) {
6186 // Ignore dead phi's.
6187 if (PN->use_empty()) continue;
6189 // Only handle legal types. Two interesting things to note here. First,
6190 // by bailing out early, we may leave behind some dead instructions,
6191 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6192 // own moves. Second, this check is necessary becuase FastISel doesn't
6193 // use CreateRegForValue to create registers, so it always creates
6194 // exactly one register for each non-void instruction.
6195 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6196 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6199 VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT);
6201 SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6206 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6208 unsigned Reg = F->getRegForValue(PHIOp);
6210 SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6213 SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));