1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameLowering.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
61 /// LimitFloatPrecision - Generate low-precision inline sequences for
62 /// some float libcalls (6, 8 or 12 bits).
63 static unsigned LimitFloatPrecision;
65 static cl::opt<unsigned, true>
66 LimitFPPrecision("limit-float-precision",
67 cl::desc("Generate low-precision inline sequences "
68 "for some float libcalls"),
69 cl::location(LimitFloatPrecision),
72 // Limit the width of DAG chains. This is important in general to prevent
73 // prevent DAG-based analysis from blowing up. For example, alias analysis and
74 // load clustering may not complete in reasonable time. It is difficult to
75 // recognize and avoid this situation within each individual analysis, and
76 // future analyses are likely to have the same behavior. Limiting DAG width is
77 // the safe approach, and will be especially important with global DAGs.
79 // MaxParallelChains default is arbitrarily high to avoid affecting
80 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
81 // sequence over this should have been converted to llvm.memcpy by the
82 // frontend. It easy to induce this behavior with .ll code such as:
83 // %buffer = alloca [4096 x i8]
84 // %data = load [4096 x i8]* %argPtr
85 // store [4096 x i8] %data, [4096 x i8]* %buffer
86 static const unsigned MaxParallelChains = 64;
88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
89 const SDValue *Parts, unsigned NumParts,
90 EVT PartVT, EVT ValueVT);
92 /// getCopyFromParts - Create a value that contains the specified legal parts
93 /// combined into the value they represent. If the parts combine to a type
94 /// larger then ValueVT then AssertOp can be used to specify whether the extra
95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
96 /// (ISD::AssertSext).
97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
99 unsigned NumParts, EVT PartVT, EVT ValueVT,
100 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
101 if (ValueVT.isVector())
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
104 assert(NumParts > 0 && "No parts to assemble!");
105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
106 SDValue Val = Parts[0];
109 // Assemble the value from multiple parts.
110 if (ValueVT.isInteger()) {
111 unsigned PartBits = PartVT.getSizeInBits();
112 unsigned ValueBits = ValueVT.getSizeInBits();
114 // Assemble the power of 2 part.
115 unsigned RoundParts = NumParts & (NumParts - 1) ?
116 1 << Log2_32(NumParts) : NumParts;
117 unsigned RoundBits = PartBits * RoundParts;
118 EVT RoundVT = RoundBits == ValueBits ?
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
124 if (RoundParts > 2) {
125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
128 RoundParts / 2, PartVT, HalfVT);
130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
134 if (TLI.isBigEndian())
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
139 if (RoundParts < NumParts) {
140 // Assemble the trailing non-power-of-2 part.
141 unsigned OddParts = NumParts - RoundParts;
142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
143 Hi = getCopyFromParts(DAG, DL,
144 Parts + RoundParts, OddParts, PartVT, OddVT);
146 // Combine the round and odd parts.
148 if (TLI.isBigEndian())
150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
153 DAG.getConstant(Lo.getValueType().getSizeInBits(),
154 TLI.getPointerTy()));
155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
158 } else if (PartVT.isFloatingPoint()) {
159 // FP split into multiple FP parts (for ppcf128)
160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
165 if (TLI.isBigEndian())
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
169 // FP split into integer parts (soft fp)
170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
171 !PartVT.isVector() && "Unexpected split");
172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
177 // There is now one part, held in Val. Correct it to match ValueVT.
178 PartVT = Val.getValueType();
180 if (PartVT == ValueVT)
183 if (PartVT.isInteger() && ValueVT.isInteger()) {
184 if (ValueVT.bitsLT(PartVT)) {
185 // For a truncate, see if we have any information to
186 // indicate whether the truncated bits will always be
187 // zero or sign-extension.
188 if (AssertOp != ISD::DELETED_NODE)
189 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
190 DAG.getValueType(ValueVT));
191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
197 // FP_ROUND's are always exact here.
198 if (ValueVT.bitsLT(Val.getValueType()))
199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
200 DAG.getIntPtrConstant(1));
202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
208 llvm_unreachable("Unknown mismatch!");
212 /// getCopyFromParts - Create a value that contains the specified legal parts
213 /// combined into the value they represent. If the parts combine to a type
214 /// larger then ValueVT then AssertOp can be used to specify whether the extra
215 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
216 /// (ISD::AssertSext).
217 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
218 const SDValue *Parts, unsigned NumParts,
219 EVT PartVT, EVT ValueVT) {
220 assert(ValueVT.isVector() && "Not a vector value");
221 assert(NumParts > 0 && "No parts to assemble!");
222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
223 SDValue Val = Parts[0];
225 // Handle a multi-element vector.
227 EVT IntermediateVT, RegisterVT;
228 unsigned NumIntermediates;
230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
231 NumIntermediates, RegisterVT);
232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
233 NumParts = NumRegs; // Silence a compiler warning.
234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
235 assert(RegisterVT == Parts[0].getValueType() &&
236 "Part type doesn't match part!");
238 // Assemble the parts into intermediate operands.
239 SmallVector<SDValue, 8> Ops(NumIntermediates);
240 if (NumIntermediates == NumParts) {
241 // If the register was not expanded, truncate or copy the value,
243 for (unsigned i = 0; i != NumParts; ++i)
244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
245 PartVT, IntermediateVT);
246 } else if (NumParts > 0) {
247 // If the intermediate type was expanded, build the intermediate
248 // operands from the parts.
249 assert(NumParts % NumIntermediates == 0 &&
250 "Must expand into a divisible number of parts!");
251 unsigned Factor = NumParts / NumIntermediates;
252 for (unsigned i = 0; i != NumIntermediates; ++i)
253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
254 PartVT, IntermediateVT);
257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
258 // intermediate operands.
259 Val = DAG.getNode(IntermediateVT.isVector() ?
260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
261 ValueVT, &Ops[0], NumIntermediates);
264 // There is now one part, held in Val. Correct it to match ValueVT.
265 PartVT = Val.getValueType();
267 if (PartVT == ValueVT)
270 if (PartVT.isVector()) {
271 // If the element type of the source/dest vectors are the same, but the
272 // parts vector has more elements than the value vector, then we have a
273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
277 "Cannot narrow, it would be a lossy transformation");
278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
279 DAG.getIntPtrConstant(0));
282 // Vector/Vector bitcast.
283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits())
284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
287 "Cannot handle this kind of promotion");
288 // Promoted vector extract
289 bool Smaller = ValueVT.bitsLE(PartVT);
290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
295 // Trivial bitcast if the types are the same size and the destination
296 // vector type is legal.
297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
298 TLI.isTypeLegal(ValueVT))
299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
301 // Handle cases such as i8 -> <1 x i1>
302 assert(ValueVT.getVectorNumElements() == 1 &&
303 "Only trivial scalar-to-vector conversions should get here!");
305 if (ValueVT.getVectorNumElements() == 1 &&
306 ValueVT.getVectorElementType() != PartVT) {
307 bool Smaller = ValueVT.bitsLE(PartVT);
308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
309 DL, ValueVT.getScalarType(), Val);
312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
318 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
319 SDValue Val, SDValue *Parts, unsigned NumParts,
322 /// getCopyToParts - Create a series of nodes that contain the specified value
323 /// split into legal parts. If the parts contain more bits than Val, then, for
324 /// integers, ExtendKind can be used to specify how to generate the extra bits.
325 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
326 SDValue Val, SDValue *Parts, unsigned NumParts,
328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
329 EVT ValueVT = Val.getValueType();
331 // Handle the vector case separately.
332 if (ValueVT.isVector())
333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
336 unsigned PartBits = PartVT.getSizeInBits();
337 unsigned OrigNumParts = NumParts;
338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
343 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
344 if (PartVT == ValueVT) {
345 assert(NumParts == 1 && "No-op copy with multiple parts!");
350 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
351 // If the parts cover more bits than the value has, promote the value.
352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
353 assert(NumParts == 1 && "Do not know what to promote to!");
354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
356 assert(PartVT.isInteger() && ValueVT.isInteger() &&
357 "Unknown mismatch!");
358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
361 } else if (PartBits == ValueVT.getSizeInBits()) {
362 // Different types of the same size.
363 assert(NumParts == 1 && PartVT != ValueVT);
364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
366 // If the parts cover less bits than value has, truncate the value.
367 assert(PartVT.isInteger() && ValueVT.isInteger() &&
368 "Unknown mismatch!");
369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
373 // The value may have changed - recompute ValueVT.
374 ValueVT = Val.getValueType();
375 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
376 "Failed to tile the value with PartVT!");
379 assert(PartVT == ValueVT && "Type conversion failed!");
384 // Expand the value into multiple parts.
385 if (NumParts & (NumParts - 1)) {
386 // The number of parts is not a power of 2. Split off and copy the tail.
387 assert(PartVT.isInteger() && ValueVT.isInteger() &&
388 "Do not know what to expand to!");
389 unsigned RoundParts = 1 << Log2_32(NumParts);
390 unsigned RoundBits = RoundParts * PartBits;
391 unsigned OddParts = NumParts - RoundParts;
392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
393 DAG.getIntPtrConstant(RoundBits));
394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
396 if (TLI.isBigEndian())
397 // The odd parts were reversed by getCopyToParts - unreverse them.
398 std::reverse(Parts + RoundParts, Parts + NumParts);
400 NumParts = RoundParts;
401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 // The number of parts is a power of 2. Repeatedly bisect the value using
407 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
408 EVT::getIntegerVT(*DAG.getContext(),
409 ValueVT.getSizeInBits()),
412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
413 for (unsigned i = 0; i < NumParts; i += StepSize) {
414 unsigned ThisBits = StepSize * PartBits / 2;
415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
416 SDValue &Part0 = Parts[i];
417 SDValue &Part1 = Parts[i+StepSize/2];
419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
420 ThisVT, Part0, DAG.getIntPtrConstant(1));
421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
422 ThisVT, Part0, DAG.getIntPtrConstant(0));
424 if (ThisBits == PartBits && ThisVT != PartVT) {
425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
431 if (TLI.isBigEndian())
432 std::reverse(Parts, Parts + OrigNumParts);
436 /// getCopyToPartsVector - Create a series of nodes that contain the specified
437 /// value split into legal parts.
438 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
439 SDValue Val, SDValue *Parts, unsigned NumParts,
441 EVT ValueVT = Val.getValueType();
442 assert(ValueVT.isVector() && "Not a vector");
443 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
446 if (PartVT == ValueVT) {
448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
449 // Bitconvert vector->vector case.
450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
451 } else if (PartVT.isVector() &&
452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
454 EVT ElementVT = PartVT.getVectorElementType();
455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
457 SmallVector<SDValue, 16> Ops;
458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
460 ElementVT, Val, DAG.getIntPtrConstant(i)));
462 for (unsigned i = ValueVT.getVectorNumElements(),
463 e = PartVT.getVectorNumElements(); i != e; ++i)
464 Ops.push_back(DAG.getUNDEF(ElementVT));
466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
468 // FIXME: Use CONCAT for 2x -> 4x.
470 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
472 } else if (PartVT.isVector() &&
473 PartVT.getVectorElementType().bitsGE(
474 ValueVT.getVectorElementType()) &&
475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
477 // Promoted vector extract
478 bool Smaller = PartVT.bitsLE(ValueVT);
479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
482 // Vector -> scalar conversion.
483 assert(ValueVT.getVectorNumElements() == 1 &&
484 "Only trivial vector-to-scalar conversions should get here!");
485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
486 PartVT, Val, DAG.getIntPtrConstant(0));
488 bool Smaller = ValueVT.bitsLE(PartVT);
489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
497 // Handle a multi-element vector.
498 EVT IntermediateVT, RegisterVT;
499 unsigned NumIntermediates;
500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
502 NumIntermediates, RegisterVT);
503 unsigned NumElements = ValueVT.getVectorNumElements();
505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
506 NumParts = NumRegs; // Silence a compiler warning.
507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
509 // Split the vector into intermediate operands.
510 SmallVector<SDValue, 8> Ops(NumIntermediates);
511 for (unsigned i = 0; i != NumIntermediates; ++i) {
512 if (IntermediateVT.isVector())
513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
518 IntermediateVT, Val, DAG.getIntPtrConstant(i));
521 // Split the intermediate operands into legal parts.
522 if (NumParts == NumIntermediates) {
523 // If the register was not expanded, promote or copy the value,
525 for (unsigned i = 0; i != NumParts; ++i)
526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
527 } else if (NumParts > 0) {
528 // If the intermediate type was expanded, split each the value into
530 assert(NumParts % NumIntermediates == 0 &&
531 "Must expand into a divisible number of parts!");
532 unsigned Factor = NumParts / NumIntermediates;
533 for (unsigned i = 0; i != NumIntermediates; ++i)
534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
542 /// RegsForValue - This struct represents the registers (physical or virtual)
543 /// that a particular set of values is assigned, and the type information
544 /// about the value. The most common situation is to represent one value at a
545 /// time, but struct or array values are handled element-wise as multiple
546 /// values. The splitting of aggregates is performed recursively, so that we
547 /// never have aggregate-typed registers. The values at this point do not
548 /// necessarily have legal types, so each value may require one or more
549 /// registers of some legal type.
551 struct RegsForValue {
552 /// ValueVTs - The value types of the values, which may not be legal, and
553 /// may need be promoted or synthesized from one or more registers.
555 SmallVector<EVT, 4> ValueVTs;
557 /// RegVTs - The value types of the registers. This is the same size as
558 /// ValueVTs and it records, for each value, what the type of the assigned
559 /// register or registers are. (Individual values are never synthesized
560 /// from more than one type of register.)
562 /// With virtual registers, the contents of RegVTs is redundant with TLI's
563 /// getRegisterType member function, however when with physical registers
564 /// it is necessary to have a separate record of the types.
566 SmallVector<EVT, 4> RegVTs;
568 /// Regs - This list holds the registers assigned to the values.
569 /// Each legal or promoted value requires one register, and each
570 /// expanded value requires multiple registers.
572 SmallVector<unsigned, 4> Regs;
576 RegsForValue(const SmallVector<unsigned, 4> ®s,
577 EVT regvt, EVT valuevt)
578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
580 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
581 unsigned Reg, const Type *Ty) {
582 ComputeValueVTs(tli, Ty, ValueVTs);
584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
585 EVT ValueVT = ValueVTs[Value];
586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
588 for (unsigned i = 0; i != NumRegs; ++i)
589 Regs.push_back(Reg + i);
590 RegVTs.push_back(RegisterVT);
595 /// areValueTypesLegal - Return true if types of all the values are legal.
596 bool areValueTypesLegal(const TargetLowering &TLI) {
597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
598 EVT RegisterVT = RegVTs[Value];
599 if (!TLI.isTypeLegal(RegisterVT))
605 /// append - Add the specified values to this one.
606 void append(const RegsForValue &RHS) {
607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
609 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
613 /// this value and returns the result as a ValueVTs value. This uses
614 /// Chain/Flag as the input and updates them for the output Chain/Flag.
615 /// If the Flag pointer is NULL, no flag is used.
616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
618 SDValue &Chain, SDValue *Flag) const;
620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
621 /// specified value into the registers specified by this object. This uses
622 /// Chain/Flag as the input and updates them for the output Chain/Flag.
623 /// If the Flag pointer is NULL, no flag is used.
624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
625 SDValue &Chain, SDValue *Flag) const;
627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
628 /// operand list. This adds the code marker, matching input operand index
629 /// (if applicable), and includes the number of values added into it.
630 void AddInlineAsmOperands(unsigned Kind,
631 bool HasMatching, unsigned MatchingIdx,
633 std::vector<SDValue> &Ops) const;
637 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
638 /// this value and returns the result as a ValueVT value. This uses
639 /// Chain/Flag as the input and updates them for the output Chain/Flag.
640 /// If the Flag pointer is NULL, no flag is used.
641 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
642 FunctionLoweringInfo &FuncInfo,
644 SDValue &Chain, SDValue *Flag) const {
645 // A Value with type {} or [0 x %t] needs no registers.
646 if (ValueVTs.empty())
649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
651 // Assemble the legal parts into the final values.
652 SmallVector<SDValue, 4> Values(ValueVTs.size());
653 SmallVector<SDValue, 8> Parts;
654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
655 // Copy the legal parts from the registers.
656 EVT ValueVT = ValueVTs[Value];
657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
658 EVT RegisterVT = RegVTs[Value];
660 Parts.resize(NumRegs);
661 for (unsigned i = 0; i != NumRegs; ++i) {
664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
667 *Flag = P.getValue(2);
670 Chain = P.getValue(1);
673 // If the source register was virtual and if we know something about it,
674 // add an assert node.
675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
676 !RegisterVT.isInteger() || RegisterVT.isVector())
679 const FunctionLoweringInfo::LiveOutInfo *LOI =
680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
684 unsigned RegSize = RegisterVT.getSizeInBits();
685 unsigned NumSignBits = LOI->NumSignBits;
686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
688 // FIXME: We capture more information than the dag can represent. For
689 // now, just use the tightest assertzext/assertsext possible.
691 EVT FromVT(MVT::Other);
692 if (NumSignBits == RegSize)
693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
694 else if (NumZeroBits >= RegSize-1)
695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
696 else if (NumSignBits > RegSize-8)
697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
698 else if (NumZeroBits >= RegSize-8)
699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
700 else if (NumSignBits > RegSize-16)
701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
702 else if (NumZeroBits >= RegSize-16)
703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
704 else if (NumSignBits > RegSize-32)
705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
706 else if (NumZeroBits >= RegSize-32)
707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
711 // Add an assertion node.
712 assert(FromVT != MVT::Other);
713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
714 RegisterVT, P, DAG.getValueType(FromVT));
717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
718 NumRegs, RegisterVT, ValueVT);
723 return DAG.getNode(ISD::MERGE_VALUES, dl,
724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
725 &Values[0], ValueVTs.size());
728 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
729 /// specified value into the registers specified by this object. This uses
730 /// Chain/Flag as the input and updates them for the output Chain/Flag.
731 /// If the Flag pointer is NULL, no flag is used.
732 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
733 SDValue &Chain, SDValue *Flag) const {
734 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
736 // Get the list of the values's legal parts.
737 unsigned NumRegs = Regs.size();
738 SmallVector<SDValue, 8> Parts(NumRegs);
739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
740 EVT ValueVT = ValueVTs[Value];
741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
742 EVT RegisterVT = RegVTs[Value];
744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
745 &Parts[Part], NumParts, RegisterVT);
749 // Copy the parts into the registers.
750 SmallVector<SDValue, 8> Chains(NumRegs);
751 for (unsigned i = 0; i != NumRegs; ++i) {
754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
757 *Flag = Part.getValue(1);
760 Chains[i] = Part.getValue(0);
763 if (NumRegs == 1 || Flag)
764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
765 // flagged to it. That is the CopyToReg nodes and the user are considered
766 // a single scheduling unit. If we create a TokenFactor and return it as
767 // chain, then the TokenFactor is both a predecessor (operand) of the
768 // user as well as a successor (the TF operands are flagged to the user).
769 // c1, f1 = CopyToReg
770 // c2, f2 = CopyToReg
771 // c3 = TokenFactor c1, c2
774 Chain = Chains[NumRegs-1];
776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
779 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
780 /// operand list. This adds the code marker and includes the number of
781 /// values added into it.
782 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
783 unsigned MatchingIdx,
785 std::vector<SDValue> &Ops) const {
786 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
791 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
794 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
795 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
796 EVT RegisterVT = RegVTs[Value];
797 for (unsigned i = 0; i != NumRegs; ++i) {
798 assert(Reg < Regs.size() && "Mismatch in # registers expected");
799 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
804 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
807 TD = DAG.getTarget().getTargetData();
810 /// clear - Clear out the current SelectionDAG and the associated
811 /// state and prepare this SelectionDAGBuilder object to be used
812 /// for a new block. This doesn't clear out information about
813 /// additional blocks that are needed to complete switch lowering
814 /// or PHI node updating; that information is cleared out as it is
816 void SelectionDAGBuilder::clear() {
818 UnusedArgNodeMap.clear();
819 PendingLoads.clear();
820 PendingExports.clear();
821 CurDebugLoc = DebugLoc();
825 /// clearDanglingDebugInfo - Clear the dangling debug information
826 /// map. This function is seperated from the clear so that debug
827 /// information that is dangling in a basic block can be properly
828 /// resolved in a different basic block. This allows the
829 /// SelectionDAG to resolve dangling debug information attached
831 void SelectionDAGBuilder::clearDanglingDebugInfo() {
832 DanglingDebugInfoMap.clear();
835 /// getRoot - Return the current virtual root of the Selection DAG,
836 /// flushing any PendingLoad items. This must be done before emitting
837 /// a store or any other node that may need to be ordered after any
838 /// prior load instructions.
840 SDValue SelectionDAGBuilder::getRoot() {
841 if (PendingLoads.empty())
842 return DAG.getRoot();
844 if (PendingLoads.size() == 1) {
845 SDValue Root = PendingLoads[0];
847 PendingLoads.clear();
851 // Otherwise, we have to make a token factor node.
852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
853 &PendingLoads[0], PendingLoads.size());
854 PendingLoads.clear();
859 /// getControlRoot - Similar to getRoot, but instead of flushing all the
860 /// PendingLoad items, flush all the PendingExports items. It is necessary
861 /// to do this before emitting a terminator instruction.
863 SDValue SelectionDAGBuilder::getControlRoot() {
864 SDValue Root = DAG.getRoot();
866 if (PendingExports.empty())
869 // Turn all of the CopyToReg chains into one factored node.
870 if (Root.getOpcode() != ISD::EntryToken) {
871 unsigned i = 0, e = PendingExports.size();
872 for (; i != e; ++i) {
873 assert(PendingExports[i].getNode()->getNumOperands() > 1);
874 if (PendingExports[i].getNode()->getOperand(0) == Root)
875 break; // Don't add the root if we already indirectly depend on it.
879 PendingExports.push_back(Root);
882 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
884 PendingExports.size());
885 PendingExports.clear();
890 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
891 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
892 DAG.AssignOrdering(Node, SDNodeOrder);
894 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
895 AssignOrderingToNode(Node->getOperand(I).getNode());
898 void SelectionDAGBuilder::visit(const Instruction &I) {
899 // Set up outgoing PHI node register values before emitting the terminator.
900 if (isa<TerminatorInst>(&I))
901 HandlePHINodesInSuccessorBlocks(I.getParent());
903 CurDebugLoc = I.getDebugLoc();
905 visit(I.getOpcode(), I);
907 if (!isa<TerminatorInst>(&I) && !HasTailCall)
908 CopyToExportRegsIfNeeded(&I);
910 CurDebugLoc = DebugLoc();
913 void SelectionDAGBuilder::visitPHI(const PHINode &) {
914 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
917 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
918 // Note: this doesn't use InstVisitor, because it has to work with
919 // ConstantExpr's in addition to instructions.
921 default: llvm_unreachable("Unknown instruction type encountered!");
922 // Build the switch statement using the Instruction.def file.
923 #define HANDLE_INST(NUM, OPCODE, CLASS) \
924 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
925 #include "llvm/Instruction.def"
928 // Assign the ordering to the freshly created DAG nodes.
929 if (NodeMap.count(&I)) {
931 AssignOrderingToNode(getValue(&I).getNode());
935 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
936 // generate the debug data structures now that we've seen its definition.
937 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
939 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
941 const DbgValueInst *DI = DDI.getDI();
942 DebugLoc dl = DDI.getdl();
943 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
944 MDNode *Variable = DI->getVariable();
945 uint64_t Offset = DI->getOffset();
948 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
949 SDV = DAG.getDbgValue(Variable, Val.getNode(),
950 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
951 DAG.AddDbgValue(SDV, Val.getNode(), false);
954 DEBUG(dbgs() << "Dropping debug info for " << DI);
955 DanglingDebugInfoMap[V] = DanglingDebugInfo();
959 // getValue - Return an SDValue for the given Value.
960 SDValue SelectionDAGBuilder::getValue(const Value *V) {
961 // If we already have an SDValue for this value, use it. It's important
962 // to do this first, so that we don't create a CopyFromReg if we already
963 // have a regular SDValue.
964 SDValue &N = NodeMap[V];
965 if (N.getNode()) return N;
967 // If there's a virtual register allocated and initialized for this
969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
970 if (It != FuncInfo.ValueMap.end()) {
971 unsigned InReg = It->second;
972 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
973 SDValue Chain = DAG.getEntryNode();
974 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
975 resolveDanglingDebugInfo(V, N);
979 // Otherwise create a new SDValue and remember it.
980 SDValue Val = getValueImpl(V);
982 resolveDanglingDebugInfo(V, Val);
986 /// getNonRegisterValue - Return an SDValue for the given Value, but
987 /// don't look in FuncInfo.ValueMap for a virtual register.
988 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
989 // If we already have an SDValue for this value, use it.
990 SDValue &N = NodeMap[V];
991 if (N.getNode()) return N;
993 // Otherwise create a new SDValue and remember it.
994 SDValue Val = getValueImpl(V);
996 resolveDanglingDebugInfo(V, Val);
1000 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1001 /// Create an SDValue for the given value.
1002 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1003 if (const Constant *C = dyn_cast<Constant>(V)) {
1004 EVT VT = TLI.getValueType(V->getType(), true);
1006 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1007 return DAG.getConstant(*CI, VT);
1009 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1010 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1012 if (isa<ConstantPointerNull>(C))
1013 return DAG.getConstant(0, TLI.getPointerTy());
1015 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1016 return DAG.getConstantFP(*CFP, VT);
1018 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1019 return DAG.getUNDEF(VT);
1021 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1022 visit(CE->getOpcode(), *CE);
1023 SDValue N1 = NodeMap[V];
1024 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1028 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1029 SmallVector<SDValue, 4> Constants;
1030 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1032 SDNode *Val = getValue(*OI).getNode();
1033 // If the operand is an empty aggregate, there are no values.
1035 // Add each leaf value from the operand to the Constants list
1036 // to form a flattened list of all the values.
1037 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1038 Constants.push_back(SDValue(Val, i));
1041 return DAG.getMergeValues(&Constants[0], Constants.size(),
1045 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1046 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1047 "Unknown struct or array constant!");
1049 SmallVector<EVT, 4> ValueVTs;
1050 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1051 unsigned NumElts = ValueVTs.size();
1053 return SDValue(); // empty struct
1054 SmallVector<SDValue, 4> Constants(NumElts);
1055 for (unsigned i = 0; i != NumElts; ++i) {
1056 EVT EltVT = ValueVTs[i];
1057 if (isa<UndefValue>(C))
1058 Constants[i] = DAG.getUNDEF(EltVT);
1059 else if (EltVT.isFloatingPoint())
1060 Constants[i] = DAG.getConstantFP(0, EltVT);
1062 Constants[i] = DAG.getConstant(0, EltVT);
1065 return DAG.getMergeValues(&Constants[0], NumElts,
1069 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1070 return DAG.getBlockAddress(BA, VT);
1072 const VectorType *VecTy = cast<VectorType>(V->getType());
1073 unsigned NumElements = VecTy->getNumElements();
1075 // Now that we know the number and type of the elements, get that number of
1076 // elements into the Ops array based on what kind of constant it is.
1077 SmallVector<SDValue, 16> Ops;
1078 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1079 for (unsigned i = 0; i != NumElements; ++i)
1080 Ops.push_back(getValue(CP->getOperand(i)));
1082 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1083 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1086 if (EltVT.isFloatingPoint())
1087 Op = DAG.getConstantFP(0, EltVT);
1089 Op = DAG.getConstant(0, EltVT);
1090 Ops.assign(NumElements, Op);
1093 // Create a BUILD_VECTOR node.
1094 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1095 VT, &Ops[0], Ops.size());
1098 // If this is a static alloca, generate it as the frameindex instead of
1100 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1101 DenseMap<const AllocaInst*, int>::iterator SI =
1102 FuncInfo.StaticAllocaMap.find(AI);
1103 if (SI != FuncInfo.StaticAllocaMap.end())
1104 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1107 // If this is an instruction which fast-isel has deferred, select it now.
1108 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1109 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1110 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1111 SDValue Chain = DAG.getEntryNode();
1112 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1115 llvm_unreachable("Can't get register for value!");
1119 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1120 SDValue Chain = getControlRoot();
1121 SmallVector<ISD::OutputArg, 8> Outs;
1122 SmallVector<SDValue, 8> OutVals;
1124 if (!FuncInfo.CanLowerReturn) {
1125 unsigned DemoteReg = FuncInfo.DemoteRegister;
1126 const Function *F = I.getParent()->getParent();
1128 // Emit a store of the return value through the virtual register.
1129 // Leave Outs empty so that LowerReturn won't try to load return
1130 // registers the usual way.
1131 SmallVector<EVT, 1> PtrValueVTs;
1132 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1135 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1136 SDValue RetOp = getValue(I.getOperand(0));
1138 SmallVector<EVT, 4> ValueVTs;
1139 SmallVector<uint64_t, 4> Offsets;
1140 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1141 unsigned NumValues = ValueVTs.size();
1143 SmallVector<SDValue, 4> Chains(NumValues);
1144 for (unsigned i = 0; i != NumValues; ++i) {
1145 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1146 RetPtr.getValueType(), RetPtr,
1147 DAG.getIntPtrConstant(Offsets[i]));
1149 DAG.getStore(Chain, getCurDebugLoc(),
1150 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1151 // FIXME: better loc info would be nice.
1152 Add, MachinePointerInfo(), false, false, 0);
1155 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1156 MVT::Other, &Chains[0], NumValues);
1157 } else if (I.getNumOperands() != 0) {
1158 SmallVector<EVT, 4> ValueVTs;
1159 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1160 unsigned NumValues = ValueVTs.size();
1162 SDValue RetOp = getValue(I.getOperand(0));
1163 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1164 EVT VT = ValueVTs[j];
1166 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1168 const Function *F = I.getParent()->getParent();
1169 if (F->paramHasAttr(0, Attribute::SExt))
1170 ExtendKind = ISD::SIGN_EXTEND;
1171 else if (F->paramHasAttr(0, Attribute::ZExt))
1172 ExtendKind = ISD::ZERO_EXTEND;
1174 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1175 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1177 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1178 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1179 SmallVector<SDValue, 4> Parts(NumParts);
1180 getCopyToParts(DAG, getCurDebugLoc(),
1181 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1182 &Parts[0], NumParts, PartVT, ExtendKind);
1184 // 'inreg' on function refers to return value
1185 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1186 if (F->paramHasAttr(0, Attribute::InReg))
1189 // Propagate extension type if any
1190 if (ExtendKind == ISD::SIGN_EXTEND)
1192 else if (ExtendKind == ISD::ZERO_EXTEND)
1195 for (unsigned i = 0; i < NumParts; ++i) {
1196 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1198 OutVals.push_back(Parts[i]);
1204 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1205 CallingConv::ID CallConv =
1206 DAG.getMachineFunction().getFunction()->getCallingConv();
1207 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1208 Outs, OutVals, getCurDebugLoc(), DAG);
1210 // Verify that the target's LowerReturn behaved as expected.
1211 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1212 "LowerReturn didn't return a valid chain!");
1214 // Update the DAG with the new chain value resulting from return lowering.
1218 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1219 /// created for it, emit nodes to copy the value into the virtual
1221 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1223 if (V->getType()->isEmptyTy())
1226 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1227 if (VMI != FuncInfo.ValueMap.end()) {
1228 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1229 CopyValueToVirtualRegister(V, VMI->second);
1233 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1234 /// the current basic block, add it to ValueMap now so that we'll get a
1236 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1237 // No need to export constants.
1238 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1240 // Already exported?
1241 if (FuncInfo.isExportedInst(V)) return;
1243 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1244 CopyValueToVirtualRegister(V, Reg);
1247 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1248 const BasicBlock *FromBB) {
1249 // The operands of the setcc have to be in this block. We don't know
1250 // how to export them from some other block.
1251 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1252 // Can export from current BB.
1253 if (VI->getParent() == FromBB)
1256 // Is already exported, noop.
1257 return FuncInfo.isExportedInst(V);
1260 // If this is an argument, we can export it if the BB is the entry block or
1261 // if it is already exported.
1262 if (isa<Argument>(V)) {
1263 if (FromBB == &FromBB->getParent()->getEntryBlock())
1266 // Otherwise, can only export this if it is already exported.
1267 return FuncInfo.isExportedInst(V);
1270 // Otherwise, constants can always be exported.
1274 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1275 uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src,
1276 MachineBasicBlock *Dst) {
1277 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1280 BasicBlock *SrcBB = const_cast<BasicBlock*>(Src->getBasicBlock());
1281 BasicBlock *DstBB = const_cast<BasicBlock*>(Dst->getBasicBlock());
1282 return BPI->getEdgeWeight(SrcBB, DstBB);
1285 void SelectionDAGBuilder::addSuccessorWithWeight(MachineBasicBlock *Src,
1286 MachineBasicBlock *Dst) {
1287 uint32_t weight = getEdgeWeight(Src, Dst);
1288 Src->addSuccessor(Dst, weight);
1292 static bool InBlock(const Value *V, const BasicBlock *BB) {
1293 if (const Instruction *I = dyn_cast<Instruction>(V))
1294 return I->getParent() == BB;
1298 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1299 /// This function emits a branch and is used at the leaves of an OR or an
1300 /// AND operator tree.
1303 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1304 MachineBasicBlock *TBB,
1305 MachineBasicBlock *FBB,
1306 MachineBasicBlock *CurBB,
1307 MachineBasicBlock *SwitchBB) {
1308 const BasicBlock *BB = CurBB->getBasicBlock();
1310 // If the leaf of the tree is a comparison, merge the condition into
1312 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1313 // The operands of the cmp have to be in this block. We don't know
1314 // how to export them from some other block. If this is the first block
1315 // of the sequence, no exporting is needed.
1316 if (CurBB == SwitchBB ||
1317 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1318 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1319 ISD::CondCode Condition;
1320 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1321 Condition = getICmpCondCode(IC->getPredicate());
1322 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1323 Condition = getFCmpCondCode(FC->getPredicate());
1325 Condition = ISD::SETEQ; // silence warning.
1326 llvm_unreachable("Unknown compare instruction");
1329 CaseBlock CB(Condition, BOp->getOperand(0),
1330 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1331 SwitchCases.push_back(CB);
1336 // Create a CaseBlock record representing this branch.
1337 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1338 NULL, TBB, FBB, CurBB);
1339 SwitchCases.push_back(CB);
1342 /// FindMergedConditions - If Cond is an expression like
1343 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1344 MachineBasicBlock *TBB,
1345 MachineBasicBlock *FBB,
1346 MachineBasicBlock *CurBB,
1347 MachineBasicBlock *SwitchBB,
1349 // If this node is not part of the or/and tree, emit it as a branch.
1350 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1351 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1352 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1353 BOp->getParent() != CurBB->getBasicBlock() ||
1354 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1355 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1356 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1360 // Create TmpBB after CurBB.
1361 MachineFunction::iterator BBI = CurBB;
1362 MachineFunction &MF = DAG.getMachineFunction();
1363 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1364 CurBB->getParent()->insert(++BBI, TmpBB);
1366 if (Opc == Instruction::Or) {
1367 // Codegen X | Y as:
1375 // Emit the LHS condition.
1376 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1378 // Emit the RHS condition into TmpBB.
1379 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1381 assert(Opc == Instruction::And && "Unknown merge op!");
1382 // Codegen X & Y as:
1389 // This requires creation of TmpBB after CurBB.
1391 // Emit the LHS condition.
1392 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1394 // Emit the RHS condition into TmpBB.
1395 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1399 /// If the set of cases should be emitted as a series of branches, return true.
1400 /// If we should emit this as a bunch of and/or'd together conditions, return
1403 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1404 if (Cases.size() != 2) return true;
1406 // If this is two comparisons of the same values or'd or and'd together, they
1407 // will get folded into a single comparison, so don't emit two blocks.
1408 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1409 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1410 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1411 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1415 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1416 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1417 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1418 Cases[0].CC == Cases[1].CC &&
1419 isa<Constant>(Cases[0].CmpRHS) &&
1420 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1421 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1423 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1430 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1431 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1433 // Update machine-CFG edges.
1434 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1436 // Figure out which block is immediately after the current one.
1437 MachineBasicBlock *NextBlock = 0;
1438 MachineFunction::iterator BBI = BrMBB;
1439 if (++BBI != FuncInfo.MF->end())
1442 if (I.isUnconditional()) {
1443 // Update machine-CFG edges.
1444 BrMBB->addSuccessor(Succ0MBB);
1446 // If this is not a fall-through branch, emit the branch.
1447 if (Succ0MBB != NextBlock)
1448 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1449 MVT::Other, getControlRoot(),
1450 DAG.getBasicBlock(Succ0MBB)));
1455 // If this condition is one of the special cases we handle, do special stuff
1457 const Value *CondVal = I.getCondition();
1458 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1460 // If this is a series of conditions that are or'd or and'd together, emit
1461 // this as a sequence of branches instead of setcc's with and/or operations.
1462 // As long as jumps are not expensive, this should improve performance.
1463 // For example, instead of something like:
1476 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1477 if (!TLI.isJumpExpensive() &&
1479 (BOp->getOpcode() == Instruction::And ||
1480 BOp->getOpcode() == Instruction::Or)) {
1481 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1483 // If the compares in later blocks need to use values not currently
1484 // exported from this block, export them now. This block should always
1485 // be the first entry.
1486 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1488 // Allow some cases to be rejected.
1489 if (ShouldEmitAsBranches(SwitchCases)) {
1490 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1491 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1492 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1495 // Emit the branch for this block.
1496 visitSwitchCase(SwitchCases[0], BrMBB);
1497 SwitchCases.erase(SwitchCases.begin());
1501 // Okay, we decided not to do this, remove any inserted MBB's and clear
1503 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1504 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1506 SwitchCases.clear();
1510 // Create a CaseBlock record representing this branch.
1511 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1512 NULL, Succ0MBB, Succ1MBB, BrMBB);
1514 // Use visitSwitchCase to actually insert the fast branch sequence for this
1516 visitSwitchCase(CB, BrMBB);
1519 /// visitSwitchCase - Emits the necessary code to represent a single node in
1520 /// the binary search tree resulting from lowering a switch instruction.
1521 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1522 MachineBasicBlock *SwitchBB) {
1524 SDValue CondLHS = getValue(CB.CmpLHS);
1525 DebugLoc dl = getCurDebugLoc();
1527 // Build the setcc now.
1528 if (CB.CmpMHS == NULL) {
1529 // Fold "(X == true)" to X and "(X == false)" to !X to
1530 // handle common cases produced by branch lowering.
1531 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1532 CB.CC == ISD::SETEQ)
1534 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1535 CB.CC == ISD::SETEQ) {
1536 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1537 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1539 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1541 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1543 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1544 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1546 SDValue CmpOp = getValue(CB.CmpMHS);
1547 EVT VT = CmpOp.getValueType();
1549 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1550 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1553 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1554 VT, CmpOp, DAG.getConstant(Low, VT));
1555 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1556 DAG.getConstant(High-Low, VT), ISD::SETULE);
1560 // Update successor info
1561 addSuccessorWithWeight(SwitchBB, CB.TrueBB);
1562 addSuccessorWithWeight(SwitchBB, CB.FalseBB);
1564 // Set NextBlock to be the MBB immediately after the current one, if any.
1565 // This is used to avoid emitting unnecessary branches to the next block.
1566 MachineBasicBlock *NextBlock = 0;
1567 MachineFunction::iterator BBI = SwitchBB;
1568 if (++BBI != FuncInfo.MF->end())
1571 // If the lhs block is the next block, invert the condition so that we can
1572 // fall through to the lhs instead of the rhs block.
1573 if (CB.TrueBB == NextBlock) {
1574 std::swap(CB.TrueBB, CB.FalseBB);
1575 SDValue True = DAG.getConstant(1, Cond.getValueType());
1576 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1579 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1580 MVT::Other, getControlRoot(), Cond,
1581 DAG.getBasicBlock(CB.TrueBB));
1583 // Insert the false branch. Do this even if it's a fall through branch,
1584 // this makes it easier to do DAG optimizations which require inverting
1585 // the branch condition.
1586 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1587 DAG.getBasicBlock(CB.FalseBB));
1589 DAG.setRoot(BrCond);
1592 /// visitJumpTable - Emit JumpTable node in the current MBB
1593 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1594 // Emit the code for the jump table
1595 assert(JT.Reg != -1U && "Should lower JT Header first!");
1596 EVT PTy = TLI.getPointerTy();
1597 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1599 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1600 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1601 MVT::Other, Index.getValue(1),
1603 DAG.setRoot(BrJumpTable);
1606 /// visitJumpTableHeader - This function emits necessary code to produce index
1607 /// in the JumpTable from switch case.
1608 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1609 JumpTableHeader &JTH,
1610 MachineBasicBlock *SwitchBB) {
1611 // Subtract the lowest switch case value from the value being switched on and
1612 // conditional branch to default mbb if the result is greater than the
1613 // difference between smallest and largest cases.
1614 SDValue SwitchOp = getValue(JTH.SValue);
1615 EVT VT = SwitchOp.getValueType();
1616 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1617 DAG.getConstant(JTH.First, VT));
1619 // The SDNode we just created, which holds the value being switched on minus
1620 // the smallest case value, needs to be copied to a virtual register so it
1621 // can be used as an index into the jump table in a subsequent basic block.
1622 // This value may be smaller or larger than the target's pointer type, and
1623 // therefore require extension or truncating.
1624 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1626 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1627 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1628 JumpTableReg, SwitchOp);
1629 JT.Reg = JumpTableReg;
1631 // Emit the range check for the jump table, and branch to the default block
1632 // for the switch statement if the value being switched on exceeds the largest
1633 // case in the switch.
1634 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1635 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1636 DAG.getConstant(JTH.Last-JTH.First,VT),
1639 // Set NextBlock to be the MBB immediately after the current one, if any.
1640 // This is used to avoid emitting unnecessary branches to the next block.
1641 MachineBasicBlock *NextBlock = 0;
1642 MachineFunction::iterator BBI = SwitchBB;
1644 if (++BBI != FuncInfo.MF->end())
1647 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1648 MVT::Other, CopyTo, CMP,
1649 DAG.getBasicBlock(JT.Default));
1651 if (JT.MBB != NextBlock)
1652 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1653 DAG.getBasicBlock(JT.MBB));
1655 DAG.setRoot(BrCond);
1658 /// visitBitTestHeader - This function emits necessary code to produce value
1659 /// suitable for "bit tests"
1660 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1661 MachineBasicBlock *SwitchBB) {
1662 // Subtract the minimum value
1663 SDValue SwitchOp = getValue(B.SValue);
1664 EVT VT = SwitchOp.getValueType();
1665 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1666 DAG.getConstant(B.First, VT));
1669 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1670 TLI.getSetCCResultType(Sub.getValueType()),
1671 Sub, DAG.getConstant(B.Range, VT),
1674 // Determine the type of the test operands.
1675 bool UsePtrType = false;
1676 if (!TLI.isTypeLegal(VT))
1679 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1680 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) {
1681 // Switch table case range are encoded into series of masks.
1682 // Just use pointer type, it's guaranteed to fit.
1688 VT = TLI.getPointerTy();
1689 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1693 B.Reg = FuncInfo.CreateReg(VT);
1694 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1697 // Set NextBlock to be the MBB immediately after the current one, if any.
1698 // This is used to avoid emitting unnecessary branches to the next block.
1699 MachineBasicBlock *NextBlock = 0;
1700 MachineFunction::iterator BBI = SwitchBB;
1701 if (++BBI != FuncInfo.MF->end())
1704 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1706 addSuccessorWithWeight(SwitchBB, B.Default);
1707 addSuccessorWithWeight(SwitchBB, MBB);
1709 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1710 MVT::Other, CopyTo, RangeCmp,
1711 DAG.getBasicBlock(B.Default));
1713 if (MBB != NextBlock)
1714 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1715 DAG.getBasicBlock(MBB));
1717 DAG.setRoot(BrRange);
1720 /// visitBitTestCase - this function produces one "bit test"
1721 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1722 MachineBasicBlock* NextMBB,
1725 MachineBasicBlock *SwitchBB) {
1727 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1730 if (CountPopulation_64(B.Mask) == 1) {
1731 // Testing for a single bit; just compare the shift count with what it
1732 // would need to be to shift a 1 bit in that position.
1733 Cmp = DAG.getSetCC(getCurDebugLoc(),
1734 TLI.getSetCCResultType(VT),
1736 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1739 // Make desired shift
1740 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1741 DAG.getConstant(1, VT), ShiftOp);
1743 // Emit bit tests and jumps
1744 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1745 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1746 Cmp = DAG.getSetCC(getCurDebugLoc(),
1747 TLI.getSetCCResultType(VT),
1748 AndOp, DAG.getConstant(0, VT),
1752 addSuccessorWithWeight(SwitchBB, B.TargetBB);
1753 addSuccessorWithWeight(SwitchBB, NextMBB);
1755 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1756 MVT::Other, getControlRoot(),
1757 Cmp, DAG.getBasicBlock(B.TargetBB));
1759 // Set NextBlock to be the MBB immediately after the current one, if any.
1760 // This is used to avoid emitting unnecessary branches to the next block.
1761 MachineBasicBlock *NextBlock = 0;
1762 MachineFunction::iterator BBI = SwitchBB;
1763 if (++BBI != FuncInfo.MF->end())
1766 if (NextMBB != NextBlock)
1767 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1768 DAG.getBasicBlock(NextMBB));
1773 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1774 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1776 // Retrieve successors.
1777 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1778 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1780 const Value *Callee(I.getCalledValue());
1781 if (isa<InlineAsm>(Callee))
1784 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1786 // If the value of the invoke is used outside of its defining block, make it
1787 // available as a virtual register.
1788 CopyToExportRegsIfNeeded(&I);
1790 // Update successor info
1791 InvokeMBB->addSuccessor(Return);
1792 InvokeMBB->addSuccessor(LandingPad);
1794 // Drop into normal successor.
1795 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1796 MVT::Other, getControlRoot(),
1797 DAG.getBasicBlock(Return)));
1800 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1803 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1804 /// small case ranges).
1805 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1806 CaseRecVector& WorkList,
1808 MachineBasicBlock *Default,
1809 MachineBasicBlock *SwitchBB) {
1810 Case& BackCase = *(CR.Range.second-1);
1812 // Size is the number of Cases represented by this range.
1813 size_t Size = CR.Range.second - CR.Range.first;
1817 // Get the MachineFunction which holds the current MBB. This is used when
1818 // inserting any additional MBBs necessary to represent the switch.
1819 MachineFunction *CurMF = FuncInfo.MF;
1821 // Figure out which block is immediately after the current one.
1822 MachineBasicBlock *NextBlock = 0;
1823 MachineFunction::iterator BBI = CR.CaseBB;
1825 if (++BBI != FuncInfo.MF->end())
1828 // If any two of the cases has the same destination, and if one value
1829 // is the same as the other, but has one bit unset that the other has set,
1830 // use bit manipulation to do two compares at once. For example:
1831 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1832 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1833 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1834 if (Size == 2 && CR.CaseBB == SwitchBB) {
1835 Case &Small = *CR.Range.first;
1836 Case &Big = *(CR.Range.second-1);
1838 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1839 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1840 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1842 // Check that there is only one bit different.
1843 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1844 (SmallValue | BigValue) == BigValue) {
1845 // Isolate the common bit.
1846 APInt CommonBit = BigValue & ~SmallValue;
1847 assert((SmallValue | CommonBit) == BigValue &&
1848 CommonBit.countPopulation() == 1 && "Not a common bit?");
1850 SDValue CondLHS = getValue(SV);
1851 EVT VT = CondLHS.getValueType();
1852 DebugLoc DL = getCurDebugLoc();
1854 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1855 DAG.getConstant(CommonBit, VT));
1856 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1857 Or, DAG.getConstant(BigValue, VT),
1860 // Update successor info.
1861 SwitchBB->addSuccessor(Small.BB);
1862 SwitchBB->addSuccessor(Default);
1864 // Insert the true branch.
1865 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1866 getControlRoot(), Cond,
1867 DAG.getBasicBlock(Small.BB));
1869 // Insert the false branch.
1870 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1871 DAG.getBasicBlock(Default));
1873 DAG.setRoot(BrCond);
1879 // Rearrange the case blocks so that the last one falls through if possible.
1880 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1881 // The last case block won't fall through into 'NextBlock' if we emit the
1882 // branches in this order. See if rearranging a case value would help.
1883 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1884 if (I->BB == NextBlock) {
1885 std::swap(*I, BackCase);
1891 // Create a CaseBlock record representing a conditional branch to
1892 // the Case's target mbb if the value being switched on SV is equal
1894 MachineBasicBlock *CurBlock = CR.CaseBB;
1895 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1896 MachineBasicBlock *FallThrough;
1898 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1899 CurMF->insert(BBI, FallThrough);
1901 // Put SV in a virtual register to make it available from the new blocks.
1902 ExportFromCurrentBlock(SV);
1904 // If the last case doesn't match, go to the default block.
1905 FallThrough = Default;
1908 const Value *RHS, *LHS, *MHS;
1910 if (I->High == I->Low) {
1911 // This is just small small case range :) containing exactly 1 case
1913 LHS = SV; RHS = I->High; MHS = NULL;
1916 LHS = I->Low; MHS = SV; RHS = I->High;
1918 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1920 // If emitting the first comparison, just call visitSwitchCase to emit the
1921 // code into the current block. Otherwise, push the CaseBlock onto the
1922 // vector to be later processed by SDISel, and insert the node's MBB
1923 // before the next MBB.
1924 if (CurBlock == SwitchBB)
1925 visitSwitchCase(CB, SwitchBB);
1927 SwitchCases.push_back(CB);
1929 CurBlock = FallThrough;
1935 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1936 return !DisableJumpTables &&
1937 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1938 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1941 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1942 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1943 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
1944 return (LastExt - FirstExt + 1ULL);
1947 /// handleJTSwitchCase - Emit jumptable for current switch case range
1948 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1949 CaseRecVector& WorkList,
1951 MachineBasicBlock* Default,
1952 MachineBasicBlock *SwitchBB) {
1953 Case& FrontCase = *CR.Range.first;
1954 Case& BackCase = *(CR.Range.second-1);
1956 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1957 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1959 APInt TSize(First.getBitWidth(), 0);
1960 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1964 if (!areJTsAllowed(TLI) || TSize.ult(4))
1967 APInt Range = ComputeRange(First, Last);
1968 double Density = TSize.roundToDouble() / Range.roundToDouble();
1972 DEBUG(dbgs() << "Lowering jump table\n"
1973 << "First entry: " << First << ". Last entry: " << Last << '\n'
1974 << "Range: " << Range
1975 << ". Size: " << TSize << ". Density: " << Density << "\n\n");
1977 // Get the MachineFunction which holds the current MBB. This is used when
1978 // inserting any additional MBBs necessary to represent the switch.
1979 MachineFunction *CurMF = FuncInfo.MF;
1981 // Figure out which block is immediately after the current one.
1982 MachineFunction::iterator BBI = CR.CaseBB;
1985 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1987 // Create a new basic block to hold the code for loading the address
1988 // of the jump table, and jumping to it. Update successor information;
1989 // we will either branch to the default case for the switch, or the jump
1991 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1992 CurMF->insert(BBI, JumpTableBB);
1994 addSuccessorWithWeight(CR.CaseBB, Default);
1995 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
1997 // Build a vector of destination BBs, corresponding to each target
1998 // of the jump table. If the value of the jump table slot corresponds to
1999 // a case statement, push the case's BB onto the vector, otherwise, push
2001 std::vector<MachineBasicBlock*> DestBBs;
2003 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2004 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2005 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2007 if (Low.sle(TEI) && TEI.sle(High)) {
2008 DestBBs.push_back(I->BB);
2012 DestBBs.push_back(Default);
2016 // Update successor info. Add one edge to each unique successor.
2017 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2018 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2019 E = DestBBs.end(); I != E; ++I) {
2020 if (!SuccsHandled[(*I)->getNumber()]) {
2021 SuccsHandled[(*I)->getNumber()] = true;
2022 addSuccessorWithWeight(JumpTableBB, *I);
2026 // Create a jump table index for this jump table.
2027 unsigned JTEncoding = TLI.getJumpTableEncoding();
2028 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2029 ->createJumpTableIndex(DestBBs);
2031 // Set the jump table information so that we can codegen it as a second
2032 // MachineBasicBlock
2033 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2034 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2035 if (CR.CaseBB == SwitchBB)
2036 visitJumpTableHeader(JT, JTH, SwitchBB);
2038 JTCases.push_back(JumpTableBlock(JTH, JT));
2043 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2045 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2046 CaseRecVector& WorkList,
2048 MachineBasicBlock *Default,
2049 MachineBasicBlock *SwitchBB) {
2050 // Get the MachineFunction which holds the current MBB. This is used when
2051 // inserting any additional MBBs necessary to represent the switch.
2052 MachineFunction *CurMF = FuncInfo.MF;
2054 // Figure out which block is immediately after the current one.
2055 MachineFunction::iterator BBI = CR.CaseBB;
2058 Case& FrontCase = *CR.Range.first;
2059 Case& BackCase = *(CR.Range.second-1);
2060 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2062 // Size is the number of Cases represented by this range.
2063 unsigned Size = CR.Range.second - CR.Range.first;
2065 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2066 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2068 CaseItr Pivot = CR.Range.first + Size/2;
2070 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2071 // (heuristically) allow us to emit JumpTable's later.
2072 APInt TSize(First.getBitWidth(), 0);
2073 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2077 APInt LSize = FrontCase.size();
2078 APInt RSize = TSize-LSize;
2079 DEBUG(dbgs() << "Selecting best pivot: \n"
2080 << "First: " << First << ", Last: " << Last <<'\n'
2081 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2082 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2084 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2085 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2086 APInt Range = ComputeRange(LEnd, RBegin);
2087 assert((Range - 2ULL).isNonNegative() &&
2088 "Invalid case distance");
2089 // Use volatile double here to avoid excess precision issues on some hosts,
2090 // e.g. that use 80-bit X87 registers.
2091 volatile double LDensity =
2092 (double)LSize.roundToDouble() /
2093 (LEnd - First + 1ULL).roundToDouble();
2094 volatile double RDensity =
2095 (double)RSize.roundToDouble() /
2096 (Last - RBegin + 1ULL).roundToDouble();
2097 double Metric = Range.logBase2()*(LDensity+RDensity);
2098 // Should always split in some non-trivial place
2099 DEBUG(dbgs() <<"=>Step\n"
2100 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2101 << "LDensity: " << LDensity
2102 << ", RDensity: " << RDensity << '\n'
2103 << "Metric: " << Metric << '\n');
2104 if (FMetric < Metric) {
2107 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2113 if (areJTsAllowed(TLI)) {
2114 // If our case is dense we *really* should handle it earlier!
2115 assert((FMetric > 0) && "Should handle dense range earlier!");
2117 Pivot = CR.Range.first + Size/2;
2120 CaseRange LHSR(CR.Range.first, Pivot);
2121 CaseRange RHSR(Pivot, CR.Range.second);
2122 Constant *C = Pivot->Low;
2123 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2125 // We know that we branch to the LHS if the Value being switched on is
2126 // less than the Pivot value, C. We use this to optimize our binary
2127 // tree a bit, by recognizing that if SV is greater than or equal to the
2128 // LHS's Case Value, and that Case Value is exactly one less than the
2129 // Pivot's Value, then we can branch directly to the LHS's Target,
2130 // rather than creating a leaf node for it.
2131 if ((LHSR.second - LHSR.first) == 1 &&
2132 LHSR.first->High == CR.GE &&
2133 cast<ConstantInt>(C)->getValue() ==
2134 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2135 TrueBB = LHSR.first->BB;
2137 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2138 CurMF->insert(BBI, TrueBB);
2139 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2141 // Put SV in a virtual register to make it available from the new blocks.
2142 ExportFromCurrentBlock(SV);
2145 // Similar to the optimization above, if the Value being switched on is
2146 // known to be less than the Constant CR.LT, and the current Case Value
2147 // is CR.LT - 1, then we can branch directly to the target block for
2148 // the current Case Value, rather than emitting a RHS leaf node for it.
2149 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2150 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2151 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2152 FalseBB = RHSR.first->BB;
2154 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2155 CurMF->insert(BBI, FalseBB);
2156 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2158 // Put SV in a virtual register to make it available from the new blocks.
2159 ExportFromCurrentBlock(SV);
2162 // Create a CaseBlock record representing a conditional branch to
2163 // the LHS node if the value being switched on SV is less than C.
2164 // Otherwise, branch to LHS.
2165 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2167 if (CR.CaseBB == SwitchBB)
2168 visitSwitchCase(CB, SwitchBB);
2170 SwitchCases.push_back(CB);
2175 /// handleBitTestsSwitchCase - if current case range has few destination and
2176 /// range span less, than machine word bitwidth, encode case range into series
2177 /// of masks and emit bit tests with these masks.
2178 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2179 CaseRecVector& WorkList,
2181 MachineBasicBlock* Default,
2182 MachineBasicBlock *SwitchBB){
2183 EVT PTy = TLI.getPointerTy();
2184 unsigned IntPtrBits = PTy.getSizeInBits();
2186 Case& FrontCase = *CR.Range.first;
2187 Case& BackCase = *(CR.Range.second-1);
2189 // Get the MachineFunction which holds the current MBB. This is used when
2190 // inserting any additional MBBs necessary to represent the switch.
2191 MachineFunction *CurMF = FuncInfo.MF;
2193 // If target does not have legal shift left, do not emit bit tests at all.
2194 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2198 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2200 // Single case counts one, case range - two.
2201 numCmps += (I->Low == I->High ? 1 : 2);
2204 // Count unique destinations
2205 SmallSet<MachineBasicBlock*, 4> Dests;
2206 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2207 Dests.insert(I->BB);
2208 if (Dests.size() > 3)
2209 // Don't bother the code below, if there are too much unique destinations
2212 DEBUG(dbgs() << "Total number of unique destinations: "
2213 << Dests.size() << '\n'
2214 << "Total number of comparisons: " << numCmps << '\n');
2216 // Compute span of values.
2217 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2218 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2219 APInt cmpRange = maxValue - minValue;
2221 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2222 << "Low bound: " << minValue << '\n'
2223 << "High bound: " << maxValue << '\n');
2225 if (cmpRange.uge(IntPtrBits) ||
2226 (!(Dests.size() == 1 && numCmps >= 3) &&
2227 !(Dests.size() == 2 && numCmps >= 5) &&
2228 !(Dests.size() >= 3 && numCmps >= 6)))
2231 DEBUG(dbgs() << "Emitting bit tests\n");
2232 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2234 // Optimize the case where all the case values fit in a
2235 // word without having to subtract minValue. In this case,
2236 // we can optimize away the subtraction.
2237 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2238 cmpRange = maxValue;
2240 lowBound = minValue;
2243 CaseBitsVector CasesBits;
2244 unsigned i, count = 0;
2246 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2247 MachineBasicBlock* Dest = I->BB;
2248 for (i = 0; i < count; ++i)
2249 if (Dest == CasesBits[i].BB)
2253 assert((count < 3) && "Too much destinations to test!");
2254 CasesBits.push_back(CaseBits(0, Dest, 0));
2258 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2259 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2261 uint64_t lo = (lowValue - lowBound).getZExtValue();
2262 uint64_t hi = (highValue - lowBound).getZExtValue();
2264 for (uint64_t j = lo; j <= hi; j++) {
2265 CasesBits[i].Mask |= 1ULL << j;
2266 CasesBits[i].Bits++;
2270 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2274 // Figure out which block is immediately after the current one.
2275 MachineFunction::iterator BBI = CR.CaseBB;
2278 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2280 DEBUG(dbgs() << "Cases:\n");
2281 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2282 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2283 << ", Bits: " << CasesBits[i].Bits
2284 << ", BB: " << CasesBits[i].BB << '\n');
2286 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2287 CurMF->insert(BBI, CaseBB);
2288 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2292 // Put SV in a virtual register to make it available from the new blocks.
2293 ExportFromCurrentBlock(SV);
2296 BitTestBlock BTB(lowBound, cmpRange, SV,
2297 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2298 CR.CaseBB, Default, BTC);
2300 if (CR.CaseBB == SwitchBB)
2301 visitBitTestHeader(BTB, SwitchBB);
2303 BitTestCases.push_back(BTB);
2308 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2309 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2310 const SwitchInst& SI) {
2313 // Start with "simple" cases
2314 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2315 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2316 Cases.push_back(Case(SI.getSuccessorValue(i),
2317 SI.getSuccessorValue(i),
2320 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2322 // Merge case into clusters
2323 if (Cases.size() >= 2)
2324 // Must recompute end() each iteration because it may be
2325 // invalidated by erase if we hold on to it
2326 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2327 J != Cases.end(); ) {
2328 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2329 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2330 MachineBasicBlock* nextBB = J->BB;
2331 MachineBasicBlock* currentBB = I->BB;
2333 // If the two neighboring cases go to the same destination, merge them
2334 // into a single case.
2335 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2343 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2344 if (I->Low != I->High)
2345 // A range counts double, since it requires two compares.
2352 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2353 MachineBasicBlock *Last) {
2355 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2356 if (JTCases[i].first.HeaderBB == First)
2357 JTCases[i].first.HeaderBB = Last;
2359 // Update BitTestCases.
2360 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2361 if (BitTestCases[i].Parent == First)
2362 BitTestCases[i].Parent = Last;
2365 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2366 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2368 // Figure out which block is immediately after the current one.
2369 MachineBasicBlock *NextBlock = 0;
2370 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2372 // If there is only the default destination, branch to it if it is not the
2373 // next basic block. Otherwise, just fall through.
2374 if (SI.getNumOperands() == 2) {
2375 // Update machine-CFG edges.
2377 // If this is not a fall-through branch, emit the branch.
2378 SwitchMBB->addSuccessor(Default);
2379 if (Default != NextBlock)
2380 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2381 MVT::Other, getControlRoot(),
2382 DAG.getBasicBlock(Default)));
2387 // If there are any non-default case statements, create a vector of Cases
2388 // representing each one, and sort the vector so that we can efficiently
2389 // create a binary search tree from them.
2391 size_t numCmps = Clusterify(Cases, SI);
2392 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2393 << ". Total compares: " << numCmps << '\n');
2396 // Get the Value to be switched on and default basic blocks, which will be
2397 // inserted into CaseBlock records, representing basic blocks in the binary
2399 const Value *SV = SI.getOperand(0);
2401 // Push the initial CaseRec onto the worklist
2402 CaseRecVector WorkList;
2403 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2404 CaseRange(Cases.begin(),Cases.end())));
2406 while (!WorkList.empty()) {
2407 // Grab a record representing a case range to process off the worklist
2408 CaseRec CR = WorkList.back();
2409 WorkList.pop_back();
2411 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2414 // If the range has few cases (two or less) emit a series of specific
2416 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2419 // If the switch has more than 5 blocks, and at least 40% dense, and the
2420 // target supports indirect branches, then emit a jump table rather than
2421 // lowering the switch to a binary tree of conditional branches.
2422 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2425 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2426 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2427 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2431 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2432 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2434 // Update machine-CFG edges with unique successors.
2435 SmallVector<BasicBlock*, 32> succs;
2436 succs.reserve(I.getNumSuccessors());
2437 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2438 succs.push_back(I.getSuccessor(i));
2439 array_pod_sort(succs.begin(), succs.end());
2440 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2441 for (unsigned i = 0, e = succs.size(); i != e; ++i) {
2442 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]];
2443 addSuccessorWithWeight(IndirectBrMBB, Succ);
2446 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2447 MVT::Other, getControlRoot(),
2448 getValue(I.getAddress())));
2451 void SelectionDAGBuilder::visitFSub(const User &I) {
2452 // -0.0 - X --> fneg
2453 const Type *Ty = I.getType();
2454 if (isa<Constant>(I.getOperand(0)) &&
2455 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2456 SDValue Op2 = getValue(I.getOperand(1));
2457 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2458 Op2.getValueType(), Op2));
2462 visitBinary(I, ISD::FSUB);
2465 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2466 SDValue Op1 = getValue(I.getOperand(0));
2467 SDValue Op2 = getValue(I.getOperand(1));
2468 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2469 Op1.getValueType(), Op1, Op2));
2472 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2473 SDValue Op1 = getValue(I.getOperand(0));
2474 SDValue Op2 = getValue(I.getOperand(1));
2476 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2478 // Coerce the shift amount to the right type if we can.
2479 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2480 unsigned ShiftSize = ShiftTy.getSizeInBits();
2481 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2482 DebugLoc DL = getCurDebugLoc();
2484 // If the operand is smaller than the shift count type, promote it.
2485 if (ShiftSize > Op2Size)
2486 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2488 // If the operand is larger than the shift count type but the shift
2489 // count type has enough bits to represent any shift value, truncate
2490 // it now. This is a common case and it exposes the truncate to
2491 // optimization early.
2492 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2493 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2494 // Otherwise we'll need to temporarily settle for some other convenient
2495 // type. Type legalization will make adjustments once the shiftee is split.
2497 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2500 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2501 Op1.getValueType(), Op1, Op2));
2504 void SelectionDAGBuilder::visitICmp(const User &I) {
2505 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2506 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2507 predicate = IC->getPredicate();
2508 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2509 predicate = ICmpInst::Predicate(IC->getPredicate());
2510 SDValue Op1 = getValue(I.getOperand(0));
2511 SDValue Op2 = getValue(I.getOperand(1));
2512 ISD::CondCode Opcode = getICmpCondCode(predicate);
2514 EVT DestVT = TLI.getValueType(I.getType());
2515 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2518 void SelectionDAGBuilder::visitFCmp(const User &I) {
2519 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2520 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2521 predicate = FC->getPredicate();
2522 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2523 predicate = FCmpInst::Predicate(FC->getPredicate());
2524 SDValue Op1 = getValue(I.getOperand(0));
2525 SDValue Op2 = getValue(I.getOperand(1));
2526 ISD::CondCode Condition = getFCmpCondCode(predicate);
2527 EVT DestVT = TLI.getValueType(I.getType());
2528 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2531 void SelectionDAGBuilder::visitSelect(const User &I) {
2532 SmallVector<EVT, 4> ValueVTs;
2533 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2534 unsigned NumValues = ValueVTs.size();
2535 if (NumValues == 0) return;
2537 SmallVector<SDValue, 4> Values(NumValues);
2538 SDValue Cond = getValue(I.getOperand(0));
2539 SDValue TrueVal = getValue(I.getOperand(1));
2540 SDValue FalseVal = getValue(I.getOperand(2));
2542 for (unsigned i = 0; i != NumValues; ++i)
2543 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2544 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2546 SDValue(TrueVal.getNode(),
2547 TrueVal.getResNo() + i),
2548 SDValue(FalseVal.getNode(),
2549 FalseVal.getResNo() + i));
2551 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2552 DAG.getVTList(&ValueVTs[0], NumValues),
2553 &Values[0], NumValues));
2556 void SelectionDAGBuilder::visitTrunc(const User &I) {
2557 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2558 SDValue N = getValue(I.getOperand(0));
2559 EVT DestVT = TLI.getValueType(I.getType());
2560 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2563 void SelectionDAGBuilder::visitZExt(const User &I) {
2564 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2565 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2566 SDValue N = getValue(I.getOperand(0));
2567 EVT DestVT = TLI.getValueType(I.getType());
2568 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2571 void SelectionDAGBuilder::visitSExt(const User &I) {
2572 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2573 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2574 SDValue N = getValue(I.getOperand(0));
2575 EVT DestVT = TLI.getValueType(I.getType());
2576 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2579 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2580 // FPTrunc is never a no-op cast, no need to check
2581 SDValue N = getValue(I.getOperand(0));
2582 EVT DestVT = TLI.getValueType(I.getType());
2583 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2584 DestVT, N, DAG.getIntPtrConstant(0)));
2587 void SelectionDAGBuilder::visitFPExt(const User &I){
2588 // FPTrunc is never a no-op cast, no need to check
2589 SDValue N = getValue(I.getOperand(0));
2590 EVT DestVT = TLI.getValueType(I.getType());
2591 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2594 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2595 // FPToUI is never a no-op cast, no need to check
2596 SDValue N = getValue(I.getOperand(0));
2597 EVT DestVT = TLI.getValueType(I.getType());
2598 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2601 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2602 // FPToSI is never a no-op cast, no need to check
2603 SDValue N = getValue(I.getOperand(0));
2604 EVT DestVT = TLI.getValueType(I.getType());
2605 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2608 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2609 // UIToFP is never a no-op cast, no need to check
2610 SDValue N = getValue(I.getOperand(0));
2611 EVT DestVT = TLI.getValueType(I.getType());
2612 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2615 void SelectionDAGBuilder::visitSIToFP(const User &I){
2616 // SIToFP is never a no-op cast, no need to check
2617 SDValue N = getValue(I.getOperand(0));
2618 EVT DestVT = TLI.getValueType(I.getType());
2619 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2622 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2623 // What to do depends on the size of the integer and the size of the pointer.
2624 // We can either truncate, zero extend, or no-op, accordingly.
2625 SDValue N = getValue(I.getOperand(0));
2626 EVT DestVT = TLI.getValueType(I.getType());
2627 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2630 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2631 // What to do depends on the size of the integer and the size of the pointer.
2632 // We can either truncate, zero extend, or no-op, accordingly.
2633 SDValue N = getValue(I.getOperand(0));
2634 EVT DestVT = TLI.getValueType(I.getType());
2635 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2638 void SelectionDAGBuilder::visitBitCast(const User &I) {
2639 SDValue N = getValue(I.getOperand(0));
2640 EVT DestVT = TLI.getValueType(I.getType());
2642 // BitCast assures us that source and destination are the same size so this is
2643 // either a BITCAST or a no-op.
2644 if (DestVT != N.getValueType())
2645 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2646 DestVT, N)); // convert types.
2648 setValue(&I, N); // noop cast.
2651 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2652 SDValue InVec = getValue(I.getOperand(0));
2653 SDValue InVal = getValue(I.getOperand(1));
2654 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2656 getValue(I.getOperand(2)));
2657 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2658 TLI.getValueType(I.getType()),
2659 InVec, InVal, InIdx));
2662 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2663 SDValue InVec = getValue(I.getOperand(0));
2664 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2666 getValue(I.getOperand(1)));
2667 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2668 TLI.getValueType(I.getType()), InVec, InIdx));
2671 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2672 // from SIndx and increasing to the element length (undefs are allowed).
2673 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2674 unsigned MaskNumElts = Mask.size();
2675 for (unsigned i = 0; i != MaskNumElts; ++i)
2676 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2681 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2682 SmallVector<int, 8> Mask;
2683 SDValue Src1 = getValue(I.getOperand(0));
2684 SDValue Src2 = getValue(I.getOperand(1));
2686 // Convert the ConstantVector mask operand into an array of ints, with -1
2687 // representing undef values.
2688 SmallVector<Constant*, 8> MaskElts;
2689 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2690 unsigned MaskNumElts = MaskElts.size();
2691 for (unsigned i = 0; i != MaskNumElts; ++i) {
2692 if (isa<UndefValue>(MaskElts[i]))
2695 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2698 EVT VT = TLI.getValueType(I.getType());
2699 EVT SrcVT = Src1.getValueType();
2700 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2702 if (SrcNumElts == MaskNumElts) {
2703 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2708 // Normalize the shuffle vector since mask and vector length don't match.
2709 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2710 // Mask is longer than the source vectors and is a multiple of the source
2711 // vectors. We can use concatenate vector to make the mask and vectors
2713 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2714 // The shuffle is concatenating two vectors together.
2715 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2720 // Pad both vectors with undefs to make them the same length as the mask.
2721 unsigned NumConcat = MaskNumElts / SrcNumElts;
2722 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2723 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2724 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2726 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2727 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2731 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2732 getCurDebugLoc(), VT,
2733 &MOps1[0], NumConcat);
2734 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2735 getCurDebugLoc(), VT,
2736 &MOps2[0], NumConcat);
2738 // Readjust mask for new input vector length.
2739 SmallVector<int, 8> MappedOps;
2740 for (unsigned i = 0; i != MaskNumElts; ++i) {
2742 if (Idx < (int)SrcNumElts)
2743 MappedOps.push_back(Idx);
2745 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2748 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2753 if (SrcNumElts > MaskNumElts) {
2754 // Analyze the access pattern of the vector to see if we can extract
2755 // two subvectors and do the shuffle. The analysis is done by calculating
2756 // the range of elements the mask access on both vectors.
2757 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2758 int MaxRange[2] = {-1, -1};
2760 for (unsigned i = 0; i != MaskNumElts; ++i) {
2766 if (Idx >= (int)SrcNumElts) {
2770 if (Idx > MaxRange[Input])
2771 MaxRange[Input] = Idx;
2772 if (Idx < MinRange[Input])
2773 MinRange[Input] = Idx;
2776 // Check if the access is smaller than the vector size and can we find
2777 // a reasonable extract index.
2778 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2780 int StartIdx[2]; // StartIdx to extract from
2781 for (int Input=0; Input < 2; ++Input) {
2782 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2783 RangeUse[Input] = 0; // Unused
2784 StartIdx[Input] = 0;
2785 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2786 // Fits within range but we should see if we can find a good
2787 // start index that is a multiple of the mask length.
2788 if (MaxRange[Input] < (int)MaskNumElts) {
2789 RangeUse[Input] = 1; // Extract from beginning of the vector
2790 StartIdx[Input] = 0;
2792 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2793 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2794 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2795 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2800 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2801 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2804 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2805 // Extract appropriate subvector and generate a vector shuffle
2806 for (int Input=0; Input < 2; ++Input) {
2807 SDValue &Src = Input == 0 ? Src1 : Src2;
2808 if (RangeUse[Input] == 0)
2809 Src = DAG.getUNDEF(VT);
2811 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2812 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2815 // Calculate new mask.
2816 SmallVector<int, 8> MappedOps;
2817 for (unsigned i = 0; i != MaskNumElts; ++i) {
2820 MappedOps.push_back(Idx);
2821 else if (Idx < (int)SrcNumElts)
2822 MappedOps.push_back(Idx - StartIdx[0]);
2824 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2827 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2833 // We can't use either concat vectors or extract subvectors so fall back to
2834 // replacing the shuffle with extract and build vector.
2835 // to insert and build vector.
2836 EVT EltVT = VT.getVectorElementType();
2837 EVT PtrVT = TLI.getPointerTy();
2838 SmallVector<SDValue,8> Ops;
2839 for (unsigned i = 0; i != MaskNumElts; ++i) {
2841 Ops.push_back(DAG.getUNDEF(EltVT));
2846 if (Idx < (int)SrcNumElts)
2847 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2848 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2850 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2852 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2858 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2859 VT, &Ops[0], Ops.size()));
2862 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2863 const Value *Op0 = I.getOperand(0);
2864 const Value *Op1 = I.getOperand(1);
2865 const Type *AggTy = I.getType();
2866 const Type *ValTy = Op1->getType();
2867 bool IntoUndef = isa<UndefValue>(Op0);
2868 bool FromUndef = isa<UndefValue>(Op1);
2870 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2872 SmallVector<EVT, 4> AggValueVTs;
2873 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2874 SmallVector<EVT, 4> ValValueVTs;
2875 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2877 unsigned NumAggValues = AggValueVTs.size();
2878 unsigned NumValValues = ValValueVTs.size();
2879 SmallVector<SDValue, 4> Values(NumAggValues);
2881 SDValue Agg = getValue(Op0);
2883 // Copy the beginning value(s) from the original aggregate.
2884 for (; i != LinearIndex; ++i)
2885 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2886 SDValue(Agg.getNode(), Agg.getResNo() + i);
2887 // Copy values from the inserted value(s).
2889 SDValue Val = getValue(Op1);
2890 for (; i != LinearIndex + NumValValues; ++i)
2891 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2892 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2894 // Copy remaining value(s) from the original aggregate.
2895 for (; i != NumAggValues; ++i)
2896 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2897 SDValue(Agg.getNode(), Agg.getResNo() + i);
2899 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2900 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2901 &Values[0], NumAggValues));
2904 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2905 const Value *Op0 = I.getOperand(0);
2906 const Type *AggTy = Op0->getType();
2907 const Type *ValTy = I.getType();
2908 bool OutOfUndef = isa<UndefValue>(Op0);
2910 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2912 SmallVector<EVT, 4> ValValueVTs;
2913 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2915 unsigned NumValValues = ValValueVTs.size();
2917 // Ignore a extractvalue that produces an empty object
2918 if (!NumValValues) {
2919 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2923 SmallVector<SDValue, 4> Values(NumValValues);
2925 SDValue Agg = getValue(Op0);
2926 // Copy out the selected value(s).
2927 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2928 Values[i - LinearIndex] =
2930 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2931 SDValue(Agg.getNode(), Agg.getResNo() + i);
2933 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2934 DAG.getVTList(&ValValueVTs[0], NumValValues),
2935 &Values[0], NumValValues));
2938 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2939 SDValue N = getValue(I.getOperand(0));
2940 const Type *Ty = I.getOperand(0)->getType();
2942 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2944 const Value *Idx = *OI;
2945 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2946 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2949 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2950 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2951 DAG.getIntPtrConstant(Offset));
2954 Ty = StTy->getElementType(Field);
2956 Ty = cast<SequentialType>(Ty)->getElementType();
2958 // If this is a constant subscript, handle it quickly.
2959 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2960 if (CI->isZero()) continue;
2962 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2964 EVT PTy = TLI.getPointerTy();
2965 unsigned PtrBits = PTy.getSizeInBits();
2967 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2969 DAG.getConstant(Offs, MVT::i64));
2971 OffsVal = DAG.getIntPtrConstant(Offs);
2973 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2978 // N = N + Idx * ElementSize;
2979 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2980 TD->getTypeAllocSize(Ty));
2981 SDValue IdxN = getValue(Idx);
2983 // If the index is smaller or larger than intptr_t, truncate or extend
2985 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2987 // If this is a multiply by a power of two, turn it into a shl
2988 // immediately. This is a very common case.
2989 if (ElementSize != 1) {
2990 if (ElementSize.isPowerOf2()) {
2991 unsigned Amt = ElementSize.logBase2();
2992 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2993 N.getValueType(), IdxN,
2994 DAG.getConstant(Amt, TLI.getPointerTy()));
2996 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2997 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2998 N.getValueType(), IdxN, Scale);
3002 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3003 N.getValueType(), N, IdxN);
3010 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3011 // If this is a fixed sized alloca in the entry block of the function,
3012 // allocate it statically on the stack.
3013 if (FuncInfo.StaticAllocaMap.count(&I))
3014 return; // getValue will auto-populate this.
3016 const Type *Ty = I.getAllocatedType();
3017 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
3019 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
3022 SDValue AllocSize = getValue(I.getArraySize());
3024 EVT IntPtr = TLI.getPointerTy();
3025 if (AllocSize.getValueType() != IntPtr)
3026 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3028 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3030 DAG.getConstant(TySize, IntPtr));
3032 // Handle alignment. If the requested alignment is less than or equal to
3033 // the stack alignment, ignore it. If the size is greater than or equal to
3034 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3035 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3036 if (Align <= StackAlign)
3039 // Round the size of the allocation up to the stack alignment size
3040 // by add SA-1 to the size.
3041 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3042 AllocSize.getValueType(), AllocSize,
3043 DAG.getIntPtrConstant(StackAlign-1));
3045 // Mask out the low bits for alignment purposes.
3046 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3047 AllocSize.getValueType(), AllocSize,
3048 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3050 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3051 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3052 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3055 DAG.setRoot(DSA.getValue(1));
3057 // Inform the Frame Information that we have just allocated a variable-sized
3059 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3062 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3063 const Value *SV = I.getOperand(0);
3064 SDValue Ptr = getValue(SV);
3066 const Type *Ty = I.getType();
3068 bool isVolatile = I.isVolatile();
3069 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3070 unsigned Alignment = I.getAlignment();
3071 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3073 SmallVector<EVT, 4> ValueVTs;
3074 SmallVector<uint64_t, 4> Offsets;
3075 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3076 unsigned NumValues = ValueVTs.size();
3081 bool ConstantMemory = false;
3082 if (I.isVolatile() || NumValues > MaxParallelChains)
3083 // Serialize volatile loads with other side effects.
3085 else if (AA->pointsToConstantMemory(
3086 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3087 // Do not serialize (non-volatile) loads of constant memory with anything.
3088 Root = DAG.getEntryNode();
3089 ConstantMemory = true;
3091 // Do not serialize non-volatile loads against each other.
3092 Root = DAG.getRoot();
3095 SmallVector<SDValue, 4> Values(NumValues);
3096 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3098 EVT PtrVT = Ptr.getValueType();
3099 unsigned ChainI = 0;
3100 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3101 // Serializing loads here may result in excessive register pressure, and
3102 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3103 // could recover a bit by hoisting nodes upward in the chain by recognizing
3104 // they are side-effect free or do not alias. The optimizer should really
3105 // avoid this case by converting large object/array copies to llvm.memcpy
3106 // (MaxParallelChains should always remain as failsafe).
3107 if (ChainI == MaxParallelChains) {
3108 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3109 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3110 MVT::Other, &Chains[0], ChainI);
3114 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3116 DAG.getConstant(Offsets[i], PtrVT));
3117 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3118 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3119 isNonTemporal, Alignment, TBAAInfo);
3122 Chains[ChainI] = L.getValue(1);
3125 if (!ConstantMemory) {
3126 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3127 MVT::Other, &Chains[0], ChainI);
3131 PendingLoads.push_back(Chain);
3134 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3135 DAG.getVTList(&ValueVTs[0], NumValues),
3136 &Values[0], NumValues));
3139 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3140 const Value *SrcV = I.getOperand(0);
3141 const Value *PtrV = I.getOperand(1);
3143 SmallVector<EVT, 4> ValueVTs;
3144 SmallVector<uint64_t, 4> Offsets;
3145 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3146 unsigned NumValues = ValueVTs.size();
3150 // Get the lowered operands. Note that we do this after
3151 // checking if NumResults is zero, because with zero results
3152 // the operands won't have values in the map.
3153 SDValue Src = getValue(SrcV);
3154 SDValue Ptr = getValue(PtrV);
3156 SDValue Root = getRoot();
3157 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3159 EVT PtrVT = Ptr.getValueType();
3160 bool isVolatile = I.isVolatile();
3161 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3162 unsigned Alignment = I.getAlignment();
3163 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3165 unsigned ChainI = 0;
3166 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3167 // See visitLoad comments.
3168 if (ChainI == MaxParallelChains) {
3169 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3170 MVT::Other, &Chains[0], ChainI);
3174 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3175 DAG.getConstant(Offsets[i], PtrVT));
3176 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3177 SDValue(Src.getNode(), Src.getResNo() + i),
3178 Add, MachinePointerInfo(PtrV, Offsets[i]),
3179 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3180 Chains[ChainI] = St;
3183 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3184 MVT::Other, &Chains[0], ChainI);
3186 AssignOrderingToNode(StoreNode.getNode());
3187 DAG.setRoot(StoreNode);
3190 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3192 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3193 unsigned Intrinsic) {
3194 bool HasChain = !I.doesNotAccessMemory();
3195 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3197 // Build the operand list.
3198 SmallVector<SDValue, 8> Ops;
3199 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3201 // We don't need to serialize loads against other loads.
3202 Ops.push_back(DAG.getRoot());
3204 Ops.push_back(getRoot());
3208 // Info is set by getTgtMemInstrinsic
3209 TargetLowering::IntrinsicInfo Info;
3210 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3212 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3213 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3214 Info.opc == ISD::INTRINSIC_W_CHAIN)
3215 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3217 // Add all operands of the call to the operand list.
3218 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3219 SDValue Op = getValue(I.getArgOperand(i));
3220 assert(TLI.isTypeLegal(Op.getValueType()) &&
3221 "Intrinsic uses a non-legal type?");
3225 SmallVector<EVT, 4> ValueVTs;
3226 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3228 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3229 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3230 "Intrinsic uses a non-legal type?");
3235 ValueVTs.push_back(MVT::Other);
3237 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3241 if (IsTgtIntrinsic) {
3242 // This is target intrinsic that touches memory
3243 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3244 VTs, &Ops[0], Ops.size(),
3246 MachinePointerInfo(Info.ptrVal, Info.offset),
3247 Info.align, Info.vol,
3248 Info.readMem, Info.writeMem);
3249 } else if (!HasChain) {
3250 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3251 VTs, &Ops[0], Ops.size());
3252 } else if (!I.getType()->isVoidTy()) {
3253 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3254 VTs, &Ops[0], Ops.size());
3256 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3257 VTs, &Ops[0], Ops.size());
3261 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3263 PendingLoads.push_back(Chain);
3268 if (!I.getType()->isVoidTy()) {
3269 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3270 EVT VT = TLI.getValueType(PTy);
3271 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3274 setValue(&I, Result);
3278 /// GetSignificand - Get the significand and build it into a floating-point
3279 /// number with exponent of 1:
3281 /// Op = (Op & 0x007fffff) | 0x3f800000;
3283 /// where Op is the hexidecimal representation of floating point value.
3285 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3286 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3287 DAG.getConstant(0x007fffff, MVT::i32));
3288 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3289 DAG.getConstant(0x3f800000, MVT::i32));
3290 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3293 /// GetExponent - Get the exponent:
3295 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3297 /// where Op is the hexidecimal representation of floating point value.
3299 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3301 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3302 DAG.getConstant(0x7f800000, MVT::i32));
3303 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3304 DAG.getConstant(23, TLI.getPointerTy()));
3305 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3306 DAG.getConstant(127, MVT::i32));
3307 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3310 /// getF32Constant - Get 32-bit floating point constant.
3312 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3313 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3316 /// Inlined utility function to implement binary input atomic intrinsics for
3317 /// visitIntrinsicCall: I is a call instruction
3318 /// Op is the associated NodeType for I
3320 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3322 SDValue Root = getRoot();
3324 DAG.getAtomic(Op, getCurDebugLoc(),
3325 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3327 getValue(I.getArgOperand(0)),
3328 getValue(I.getArgOperand(1)),
3329 I.getArgOperand(0));
3331 DAG.setRoot(L.getValue(1));
3335 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3337 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3338 SDValue Op1 = getValue(I.getArgOperand(0));
3339 SDValue Op2 = getValue(I.getArgOperand(1));
3341 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3342 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3346 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3347 /// limited-precision mode.
3349 SelectionDAGBuilder::visitExp(const CallInst &I) {
3351 DebugLoc dl = getCurDebugLoc();
3353 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3354 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3355 SDValue Op = getValue(I.getArgOperand(0));
3357 // Put the exponent in the right bit position for later addition to the
3360 // #define LOG2OFe 1.4426950f
3361 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3362 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3363 getF32Constant(DAG, 0x3fb8aa3b));
3364 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3366 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3367 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3368 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3370 // IntegerPartOfX <<= 23;
3371 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3372 DAG.getConstant(23, TLI.getPointerTy()));
3374 if (LimitFloatPrecision <= 6) {
3375 // For floating-point precision of 6:
3377 // TwoToFractionalPartOfX =
3379 // (0.735607626f + 0.252464424f * x) * x;
3381 // error 0.0144103317, which is 6 bits
3382 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3383 getF32Constant(DAG, 0x3e814304));
3384 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3385 getF32Constant(DAG, 0x3f3c50c8));
3386 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3387 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3388 getF32Constant(DAG, 0x3f7f5e7e));
3389 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3391 // Add the exponent into the result in integer domain.
3392 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3393 TwoToFracPartOfX, IntegerPartOfX);
3395 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3396 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3397 // For floating-point precision of 12:
3399 // TwoToFractionalPartOfX =
3402 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3404 // 0.000107046256 error, which is 13 to 14 bits
3405 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3406 getF32Constant(DAG, 0x3da235e3));
3407 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3408 getF32Constant(DAG, 0x3e65b8f3));
3409 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3410 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3411 getF32Constant(DAG, 0x3f324b07));
3412 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3413 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3414 getF32Constant(DAG, 0x3f7ff8fd));
3415 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3417 // Add the exponent into the result in integer domain.
3418 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3419 TwoToFracPartOfX, IntegerPartOfX);
3421 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3422 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3423 // For floating-point precision of 18:
3425 // TwoToFractionalPartOfX =
3429 // (0.554906021e-1f +
3430 // (0.961591928e-2f +
3431 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3433 // error 2.47208000*10^(-7), which is better than 18 bits
3434 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3435 getF32Constant(DAG, 0x3924b03e));
3436 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3437 getF32Constant(DAG, 0x3ab24b87));
3438 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3439 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3440 getF32Constant(DAG, 0x3c1d8c17));
3441 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3442 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3443 getF32Constant(DAG, 0x3d634a1d));
3444 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3445 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3446 getF32Constant(DAG, 0x3e75fe14));
3447 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3448 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3449 getF32Constant(DAG, 0x3f317234));
3450 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3451 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3452 getF32Constant(DAG, 0x3f800000));
3453 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3456 // Add the exponent into the result in integer domain.
3457 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3458 TwoToFracPartOfX, IntegerPartOfX);
3460 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3463 // No special expansion.
3464 result = DAG.getNode(ISD::FEXP, dl,
3465 getValue(I.getArgOperand(0)).getValueType(),
3466 getValue(I.getArgOperand(0)));
3469 setValue(&I, result);
3472 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3473 /// limited-precision mode.
3475 SelectionDAGBuilder::visitLog(const CallInst &I) {
3477 DebugLoc dl = getCurDebugLoc();
3479 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3480 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3481 SDValue Op = getValue(I.getArgOperand(0));
3482 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3484 // Scale the exponent by log(2) [0.69314718f].
3485 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3486 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3487 getF32Constant(DAG, 0x3f317218));
3489 // Get the significand and build it into a floating-point number with
3491 SDValue X = GetSignificand(DAG, Op1, dl);
3493 if (LimitFloatPrecision <= 6) {
3494 // For floating-point precision of 6:
3498 // (1.4034025f - 0.23903021f * x) * x;
3500 // error 0.0034276066, which is better than 8 bits
3501 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3502 getF32Constant(DAG, 0xbe74c456));
3503 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3504 getF32Constant(DAG, 0x3fb3a2b1));
3505 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3506 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3507 getF32Constant(DAG, 0x3f949a29));
3509 result = DAG.getNode(ISD::FADD, dl,
3510 MVT::f32, LogOfExponent, LogOfMantissa);
3511 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3512 // For floating-point precision of 12:
3518 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3520 // error 0.000061011436, which is 14 bits
3521 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3522 getF32Constant(DAG, 0xbd67b6d6));
3523 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3524 getF32Constant(DAG, 0x3ee4f4b8));
3525 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3526 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3527 getF32Constant(DAG, 0x3fbc278b));
3528 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3529 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3530 getF32Constant(DAG, 0x40348e95));
3531 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3532 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3533 getF32Constant(DAG, 0x3fdef31a));
3535 result = DAG.getNode(ISD::FADD, dl,
3536 MVT::f32, LogOfExponent, LogOfMantissa);
3537 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3538 // For floating-point precision of 18:
3546 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3548 // error 0.0000023660568, which is better than 18 bits
3549 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3550 getF32Constant(DAG, 0xbc91e5ac));
3551 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3552 getF32Constant(DAG, 0x3e4350aa));
3553 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3554 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3555 getF32Constant(DAG, 0x3f60d3e3));
3556 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3557 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3558 getF32Constant(DAG, 0x4011cdf0));
3559 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3560 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3561 getF32Constant(DAG, 0x406cfd1c));
3562 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3563 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3564 getF32Constant(DAG, 0x408797cb));
3565 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3566 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3567 getF32Constant(DAG, 0x4006dcab));
3569 result = DAG.getNode(ISD::FADD, dl,
3570 MVT::f32, LogOfExponent, LogOfMantissa);
3573 // No special expansion.
3574 result = DAG.getNode(ISD::FLOG, dl,
3575 getValue(I.getArgOperand(0)).getValueType(),
3576 getValue(I.getArgOperand(0)));
3579 setValue(&I, result);
3582 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3583 /// limited-precision mode.
3585 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3587 DebugLoc dl = getCurDebugLoc();
3589 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3590 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3591 SDValue Op = getValue(I.getArgOperand(0));
3592 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3594 // Get the exponent.
3595 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3597 // Get the significand and build it into a floating-point number with
3599 SDValue X = GetSignificand(DAG, Op1, dl);
3601 // Different possible minimax approximations of significand in
3602 // floating-point for various degrees of accuracy over [1,2].
3603 if (LimitFloatPrecision <= 6) {
3604 // For floating-point precision of 6:
3606 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3608 // error 0.0049451742, which is more than 7 bits
3609 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3610 getF32Constant(DAG, 0xbeb08fe0));
3611 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3612 getF32Constant(DAG, 0x40019463));
3613 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3614 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3615 getF32Constant(DAG, 0x3fd6633d));
3617 result = DAG.getNode(ISD::FADD, dl,
3618 MVT::f32, LogOfExponent, Log2ofMantissa);
3619 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3620 // For floating-point precision of 12:
3626 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3628 // error 0.0000876136000, which is better than 13 bits
3629 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3630 getF32Constant(DAG, 0xbda7262e));
3631 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3632 getF32Constant(DAG, 0x3f25280b));
3633 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3634 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3635 getF32Constant(DAG, 0x4007b923));
3636 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3637 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3638 getF32Constant(DAG, 0x40823e2f));
3639 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3640 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3641 getF32Constant(DAG, 0x4020d29c));
3643 result = DAG.getNode(ISD::FADD, dl,
3644 MVT::f32, LogOfExponent, Log2ofMantissa);
3645 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3646 // For floating-point precision of 18:
3655 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3657 // error 0.0000018516, which is better than 18 bits
3658 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3659 getF32Constant(DAG, 0xbcd2769e));
3660 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3661 getF32Constant(DAG, 0x3e8ce0b9));
3662 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3663 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3664 getF32Constant(DAG, 0x3fa22ae7));
3665 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3666 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3667 getF32Constant(DAG, 0x40525723));
3668 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3669 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3670 getF32Constant(DAG, 0x40aaf200));
3671 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3672 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3673 getF32Constant(DAG, 0x40c39dad));
3674 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3675 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3676 getF32Constant(DAG, 0x4042902c));
3678 result = DAG.getNode(ISD::FADD, dl,
3679 MVT::f32, LogOfExponent, Log2ofMantissa);
3682 // No special expansion.
3683 result = DAG.getNode(ISD::FLOG2, dl,
3684 getValue(I.getArgOperand(0)).getValueType(),
3685 getValue(I.getArgOperand(0)));
3688 setValue(&I, result);
3691 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3692 /// limited-precision mode.
3694 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3696 DebugLoc dl = getCurDebugLoc();
3698 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3699 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3700 SDValue Op = getValue(I.getArgOperand(0));
3701 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3703 // Scale the exponent by log10(2) [0.30102999f].
3704 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3705 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3706 getF32Constant(DAG, 0x3e9a209a));
3708 // Get the significand and build it into a floating-point number with
3710 SDValue X = GetSignificand(DAG, Op1, dl);
3712 if (LimitFloatPrecision <= 6) {
3713 // For floating-point precision of 6:
3715 // Log10ofMantissa =
3717 // (0.60948995f - 0.10380950f * x) * x;
3719 // error 0.0014886165, which is 6 bits
3720 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3721 getF32Constant(DAG, 0xbdd49a13));
3722 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3723 getF32Constant(DAG, 0x3f1c0789));
3724 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3725 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3726 getF32Constant(DAG, 0x3f011300));
3728 result = DAG.getNode(ISD::FADD, dl,
3729 MVT::f32, LogOfExponent, Log10ofMantissa);
3730 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3731 // For floating-point precision of 12:
3733 // Log10ofMantissa =
3736 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3738 // error 0.00019228036, which is better than 12 bits
3739 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3740 getF32Constant(DAG, 0x3d431f31));
3741 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3742 getF32Constant(DAG, 0x3ea21fb2));
3743 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3744 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3745 getF32Constant(DAG, 0x3f6ae232));
3746 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3747 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3748 getF32Constant(DAG, 0x3f25f7c3));
3750 result = DAG.getNode(ISD::FADD, dl,
3751 MVT::f32, LogOfExponent, Log10ofMantissa);
3752 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3753 // For floating-point precision of 18:
3755 // Log10ofMantissa =
3760 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3762 // error 0.0000037995730, which is better than 18 bits
3763 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3764 getF32Constant(DAG, 0x3c5d51ce));
3765 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3766 getF32Constant(DAG, 0x3e00685a));
3767 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3768 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3769 getF32Constant(DAG, 0x3efb6798));
3770 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3771 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3772 getF32Constant(DAG, 0x3f88d192));
3773 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3774 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3775 getF32Constant(DAG, 0x3fc4316c));
3776 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3777 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3778 getF32Constant(DAG, 0x3f57ce70));
3780 result = DAG.getNode(ISD::FADD, dl,
3781 MVT::f32, LogOfExponent, Log10ofMantissa);
3784 // No special expansion.
3785 result = DAG.getNode(ISD::FLOG10, dl,
3786 getValue(I.getArgOperand(0)).getValueType(),
3787 getValue(I.getArgOperand(0)));
3790 setValue(&I, result);
3793 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3794 /// limited-precision mode.
3796 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3798 DebugLoc dl = getCurDebugLoc();
3800 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3801 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3802 SDValue Op = getValue(I.getArgOperand(0));
3804 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3806 // FractionalPartOfX = x - (float)IntegerPartOfX;
3807 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3808 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3810 // IntegerPartOfX <<= 23;
3811 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3812 DAG.getConstant(23, TLI.getPointerTy()));
3814 if (LimitFloatPrecision <= 6) {
3815 // For floating-point precision of 6:
3817 // TwoToFractionalPartOfX =
3819 // (0.735607626f + 0.252464424f * x) * x;
3821 // error 0.0144103317, which is 6 bits
3822 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3823 getF32Constant(DAG, 0x3e814304));
3824 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3825 getF32Constant(DAG, 0x3f3c50c8));
3826 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3827 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3828 getF32Constant(DAG, 0x3f7f5e7e));
3829 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3830 SDValue TwoToFractionalPartOfX =
3831 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3833 result = DAG.getNode(ISD::BITCAST, dl,
3834 MVT::f32, TwoToFractionalPartOfX);
3835 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3836 // For floating-point precision of 12:
3838 // TwoToFractionalPartOfX =
3841 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3843 // error 0.000107046256, which is 13 to 14 bits
3844 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3845 getF32Constant(DAG, 0x3da235e3));
3846 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3847 getF32Constant(DAG, 0x3e65b8f3));
3848 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3849 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3850 getF32Constant(DAG, 0x3f324b07));
3851 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3852 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3853 getF32Constant(DAG, 0x3f7ff8fd));
3854 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3855 SDValue TwoToFractionalPartOfX =
3856 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3858 result = DAG.getNode(ISD::BITCAST, dl,
3859 MVT::f32, TwoToFractionalPartOfX);
3860 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3861 // For floating-point precision of 18:
3863 // TwoToFractionalPartOfX =
3867 // (0.554906021e-1f +
3868 // (0.961591928e-2f +
3869 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3870 // error 2.47208000*10^(-7), which is better than 18 bits
3871 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3872 getF32Constant(DAG, 0x3924b03e));
3873 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3874 getF32Constant(DAG, 0x3ab24b87));
3875 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3876 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3877 getF32Constant(DAG, 0x3c1d8c17));
3878 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3879 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3880 getF32Constant(DAG, 0x3d634a1d));
3881 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3882 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3883 getF32Constant(DAG, 0x3e75fe14));
3884 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3885 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3886 getF32Constant(DAG, 0x3f317234));
3887 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3888 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3889 getF32Constant(DAG, 0x3f800000));
3890 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3891 SDValue TwoToFractionalPartOfX =
3892 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3894 result = DAG.getNode(ISD::BITCAST, dl,
3895 MVT::f32, TwoToFractionalPartOfX);
3898 // No special expansion.
3899 result = DAG.getNode(ISD::FEXP2, dl,
3900 getValue(I.getArgOperand(0)).getValueType(),
3901 getValue(I.getArgOperand(0)));
3904 setValue(&I, result);
3907 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3908 /// limited-precision mode with x == 10.0f.
3910 SelectionDAGBuilder::visitPow(const CallInst &I) {
3912 const Value *Val = I.getArgOperand(0);
3913 DebugLoc dl = getCurDebugLoc();
3914 bool IsExp10 = false;
3916 if (getValue(Val).getValueType() == MVT::f32 &&
3917 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3918 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3919 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3920 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3922 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3927 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3928 SDValue Op = getValue(I.getArgOperand(1));
3930 // Put the exponent in the right bit position for later addition to the
3933 // #define LOG2OF10 3.3219281f
3934 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3935 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3936 getF32Constant(DAG, 0x40549a78));
3937 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3939 // FractionalPartOfX = x - (float)IntegerPartOfX;
3940 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3941 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3943 // IntegerPartOfX <<= 23;
3944 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3945 DAG.getConstant(23, TLI.getPointerTy()));
3947 if (LimitFloatPrecision <= 6) {
3948 // For floating-point precision of 6:
3950 // twoToFractionalPartOfX =
3952 // (0.735607626f + 0.252464424f * x) * x;
3954 // error 0.0144103317, which is 6 bits
3955 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3956 getF32Constant(DAG, 0x3e814304));
3957 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3958 getF32Constant(DAG, 0x3f3c50c8));
3959 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3960 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3961 getF32Constant(DAG, 0x3f7f5e7e));
3962 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3963 SDValue TwoToFractionalPartOfX =
3964 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3966 result = DAG.getNode(ISD::BITCAST, dl,
3967 MVT::f32, TwoToFractionalPartOfX);
3968 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3969 // For floating-point precision of 12:
3971 // TwoToFractionalPartOfX =
3974 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3976 // error 0.000107046256, which is 13 to 14 bits
3977 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3978 getF32Constant(DAG, 0x3da235e3));
3979 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3980 getF32Constant(DAG, 0x3e65b8f3));
3981 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3982 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3983 getF32Constant(DAG, 0x3f324b07));
3984 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3985 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3986 getF32Constant(DAG, 0x3f7ff8fd));
3987 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3988 SDValue TwoToFractionalPartOfX =
3989 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3991 result = DAG.getNode(ISD::BITCAST, dl,
3992 MVT::f32, TwoToFractionalPartOfX);
3993 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3994 // For floating-point precision of 18:
3996 // TwoToFractionalPartOfX =
4000 // (0.554906021e-1f +
4001 // (0.961591928e-2f +
4002 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4003 // error 2.47208000*10^(-7), which is better than 18 bits
4004 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4005 getF32Constant(DAG, 0x3924b03e));
4006 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4007 getF32Constant(DAG, 0x3ab24b87));
4008 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4009 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4010 getF32Constant(DAG, 0x3c1d8c17));
4011 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4012 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4013 getF32Constant(DAG, 0x3d634a1d));
4014 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4015 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4016 getF32Constant(DAG, 0x3e75fe14));
4017 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4018 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4019 getF32Constant(DAG, 0x3f317234));
4020 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4021 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4022 getF32Constant(DAG, 0x3f800000));
4023 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4024 SDValue TwoToFractionalPartOfX =
4025 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4027 result = DAG.getNode(ISD::BITCAST, dl,
4028 MVT::f32, TwoToFractionalPartOfX);
4031 // No special expansion.
4032 result = DAG.getNode(ISD::FPOW, dl,
4033 getValue(I.getArgOperand(0)).getValueType(),
4034 getValue(I.getArgOperand(0)),
4035 getValue(I.getArgOperand(1)));
4038 setValue(&I, result);
4042 /// ExpandPowI - Expand a llvm.powi intrinsic.
4043 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4044 SelectionDAG &DAG) {
4045 // If RHS is a constant, we can expand this out to a multiplication tree,
4046 // otherwise we end up lowering to a call to __powidf2 (for example). When
4047 // optimizing for size, we only want to do this if the expansion would produce
4048 // a small number of multiplies, otherwise we do the full expansion.
4049 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4050 // Get the exponent as a positive value.
4051 unsigned Val = RHSC->getSExtValue();
4052 if ((int)Val < 0) Val = -Val;
4054 // powi(x, 0) -> 1.0
4056 return DAG.getConstantFP(1.0, LHS.getValueType());
4058 const Function *F = DAG.getMachineFunction().getFunction();
4059 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4060 // If optimizing for size, don't insert too many multiplies. This
4061 // inserts up to 5 multiplies.
4062 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4063 // We use the simple binary decomposition method to generate the multiply
4064 // sequence. There are more optimal ways to do this (for example,
4065 // powi(x,15) generates one more multiply than it should), but this has
4066 // the benefit of being both really simple and much better than a libcall.
4067 SDValue Res; // Logically starts equal to 1.0
4068 SDValue CurSquare = LHS;
4072 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4074 Res = CurSquare; // 1.0*CurSquare.
4077 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4078 CurSquare, CurSquare);
4082 // If the original was negative, invert the result, producing 1/(x*x*x).
4083 if (RHSC->getSExtValue() < 0)
4084 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4085 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4090 // Otherwise, expand to a libcall.
4091 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4094 // getTruncatedArgReg - Find underlying register used for an truncated
4096 static unsigned getTruncatedArgReg(const SDValue &N) {
4097 if (N.getOpcode() != ISD::TRUNCATE)
4100 const SDValue &Ext = N.getOperand(0);
4101 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4102 const SDValue &CFR = Ext.getOperand(0);
4103 if (CFR.getOpcode() == ISD::CopyFromReg)
4104 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4106 if (CFR.getOpcode() == ISD::TRUNCATE)
4107 return getTruncatedArgReg(CFR);
4112 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4113 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4114 /// At the end of instruction selection, they will be inserted to the entry BB.
4116 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4119 const Argument *Arg = dyn_cast<Argument>(V);
4123 MachineFunction &MF = DAG.getMachineFunction();
4124 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4125 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4127 // Ignore inlined function arguments here.
4128 DIVariable DV(Variable);
4129 if (DV.isInlinedFnArgument(MF.getFunction()))
4133 if (Arg->hasByValAttr()) {
4134 // Byval arguments' frame index is recorded during argument lowering.
4135 // Use this info directly.
4136 Reg = TRI->getFrameRegister(MF);
4137 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4138 // If byval argument ofset is not recorded then ignore this.
4144 if (N.getOpcode() == ISD::CopyFromReg)
4145 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4147 Reg = getTruncatedArgReg(N);
4148 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4149 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4150 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4157 // Check if ValueMap has reg number.
4158 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4159 if (VMI != FuncInfo.ValueMap.end())
4163 if (!Reg && N.getNode()) {
4164 // Check if frame index is available.
4165 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4166 if (FrameIndexSDNode *FINode =
4167 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4168 Reg = TRI->getFrameRegister(MF);
4169 Offset = FINode->getIndex();
4176 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4177 TII->get(TargetOpcode::DBG_VALUE))
4178 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4179 FuncInfo.ArgDbgValues.push_back(&*MIB);
4183 // VisualStudio defines setjmp as _setjmp
4184 #if defined(_MSC_VER) && defined(setjmp) && \
4185 !defined(setjmp_undefined_for_msvc)
4186 # pragma push_macro("setjmp")
4188 # define setjmp_undefined_for_msvc
4191 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4192 /// we want to emit this as a call to a named external function, return the name
4193 /// otherwise lower it and return null.
4195 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4196 DebugLoc dl = getCurDebugLoc();
4199 switch (Intrinsic) {
4201 // By default, turn this into a target intrinsic node.
4202 visitTargetIntrinsic(I, Intrinsic);
4204 case Intrinsic::vastart: visitVAStart(I); return 0;
4205 case Intrinsic::vaend: visitVAEnd(I); return 0;
4206 case Intrinsic::vacopy: visitVACopy(I); return 0;
4207 case Intrinsic::returnaddress:
4208 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4209 getValue(I.getArgOperand(0))));
4211 case Intrinsic::frameaddress:
4212 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4213 getValue(I.getArgOperand(0))));
4215 case Intrinsic::setjmp:
4216 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4217 case Intrinsic::longjmp:
4218 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4219 case Intrinsic::memcpy: {
4220 // Assert for address < 256 since we support only user defined address
4222 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4224 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4226 "Unknown address space");
4227 SDValue Op1 = getValue(I.getArgOperand(0));
4228 SDValue Op2 = getValue(I.getArgOperand(1));
4229 SDValue Op3 = getValue(I.getArgOperand(2));
4230 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4231 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4232 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4233 MachinePointerInfo(I.getArgOperand(0)),
4234 MachinePointerInfo(I.getArgOperand(1))));
4237 case Intrinsic::memset: {
4238 // Assert for address < 256 since we support only user defined address
4240 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4242 "Unknown address space");
4243 SDValue Op1 = getValue(I.getArgOperand(0));
4244 SDValue Op2 = getValue(I.getArgOperand(1));
4245 SDValue Op3 = getValue(I.getArgOperand(2));
4246 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4247 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4248 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4249 MachinePointerInfo(I.getArgOperand(0))));
4252 case Intrinsic::memmove: {
4253 // Assert for address < 256 since we support only user defined address
4255 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4257 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4259 "Unknown address space");
4260 SDValue Op1 = getValue(I.getArgOperand(0));
4261 SDValue Op2 = getValue(I.getArgOperand(1));
4262 SDValue Op3 = getValue(I.getArgOperand(2));
4263 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4264 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4265 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4266 MachinePointerInfo(I.getArgOperand(0)),
4267 MachinePointerInfo(I.getArgOperand(1))));
4270 case Intrinsic::dbg_declare: {
4271 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4272 MDNode *Variable = DI.getVariable();
4273 const Value *Address = DI.getAddress();
4274 if (!Address || !DIVariable(DI.getVariable()).Verify())
4277 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4278 // but do not always have a corresponding SDNode built. The SDNodeOrder
4279 // absolute, but not relative, values are different depending on whether
4280 // debug info exists.
4283 // Check if address has undef value.
4284 if (isa<UndefValue>(Address) ||
4285 (Address->use_empty() && !isa<Argument>(Address))) {
4286 DEBUG(dbgs() << "Dropping debug info for " << DI);
4290 SDValue &N = NodeMap[Address];
4291 if (!N.getNode() && isa<Argument>(Address))
4292 // Check unused arguments map.
4293 N = UnusedArgNodeMap[Address];
4296 // Parameters are handled specially.
4298 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4299 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4300 Address = BCI->getOperand(0);
4301 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4303 if (isParameter && !AI) {
4304 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4306 // Byval parameter. We have a frame index at this point.
4307 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4308 0, dl, SDNodeOrder);
4310 // Address is an argument, so try to emit its dbg value using
4311 // virtual register info from the FuncInfo.ValueMap.
4312 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4316 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4317 0, dl, SDNodeOrder);
4319 // Can't do anything with other non-AI cases yet.
4320 DEBUG(dbgs() << "Dropping debug info for " << DI);
4323 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4325 // If Address is an argument then try to emit its dbg value using
4326 // virtual register info from the FuncInfo.ValueMap.
4327 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4328 // If variable is pinned by a alloca in dominating bb then
4329 // use StaticAllocaMap.
4330 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4331 if (AI->getParent() != DI.getParent()) {
4332 DenseMap<const AllocaInst*, int>::iterator SI =
4333 FuncInfo.StaticAllocaMap.find(AI);
4334 if (SI != FuncInfo.StaticAllocaMap.end()) {
4335 SDV = DAG.getDbgValue(Variable, SI->second,
4336 0, dl, SDNodeOrder);
4337 DAG.AddDbgValue(SDV, 0, false);
4342 DEBUG(dbgs() << "Dropping debug info for " << DI);
4347 case Intrinsic::dbg_value: {
4348 const DbgValueInst &DI = cast<DbgValueInst>(I);
4349 if (!DIVariable(DI.getVariable()).Verify())
4352 MDNode *Variable = DI.getVariable();
4353 uint64_t Offset = DI.getOffset();
4354 const Value *V = DI.getValue();
4358 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4359 // but do not always have a corresponding SDNode built. The SDNodeOrder
4360 // absolute, but not relative, values are different depending on whether
4361 // debug info exists.
4364 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4365 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4366 DAG.AddDbgValue(SDV, 0, false);
4368 // Do not use getValue() in here; we don't want to generate code at
4369 // this point if it hasn't been done yet.
4370 SDValue N = NodeMap[V];
4371 if (!N.getNode() && isa<Argument>(V))
4372 // Check unused arguments map.
4373 N = UnusedArgNodeMap[V];
4375 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4376 SDV = DAG.getDbgValue(Variable, N.getNode(),
4377 N.getResNo(), Offset, dl, SDNodeOrder);
4378 DAG.AddDbgValue(SDV, N.getNode(), false);
4380 } else if (!V->use_empty() ) {
4381 // Do not call getValue(V) yet, as we don't want to generate code.
4382 // Remember it for later.
4383 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4384 DanglingDebugInfoMap[V] = DDI;
4386 // We may expand this to cover more cases. One case where we have no
4387 // data available is an unreferenced parameter.
4388 DEBUG(dbgs() << "Dropping debug info for " << DI);
4392 // Build a debug info table entry.
4393 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4394 V = BCI->getOperand(0);
4395 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4396 // Don't handle byval struct arguments or VLAs, for example.
4399 DenseMap<const AllocaInst*, int>::iterator SI =
4400 FuncInfo.StaticAllocaMap.find(AI);
4401 if (SI == FuncInfo.StaticAllocaMap.end())
4403 int FI = SI->second;
4405 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4406 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4407 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4410 case Intrinsic::eh_exception: {
4411 // Insert the EXCEPTIONADDR instruction.
4412 assert(FuncInfo.MBB->isLandingPad() &&
4413 "Call to eh.exception not in landing pad!");
4414 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4416 Ops[0] = DAG.getRoot();
4417 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4419 DAG.setRoot(Op.getValue(1));
4423 case Intrinsic::eh_selector: {
4424 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4425 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4426 if (CallMBB->isLandingPad())
4427 AddCatchInfo(I, &MMI, CallMBB);
4430 FuncInfo.CatchInfoLost.insert(&I);
4432 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4433 unsigned Reg = TLI.getExceptionSelectorRegister();
4434 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4437 // Insert the EHSELECTION instruction.
4438 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4440 Ops[0] = getValue(I.getArgOperand(0));
4442 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4443 DAG.setRoot(Op.getValue(1));
4444 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4448 case Intrinsic::eh_typeid_for: {
4449 // Find the type id for the given typeinfo.
4450 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4451 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4452 Res = DAG.getConstant(TypeID, MVT::i32);
4457 case Intrinsic::eh_return_i32:
4458 case Intrinsic::eh_return_i64:
4459 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4460 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4463 getValue(I.getArgOperand(0)),
4464 getValue(I.getArgOperand(1))));
4466 case Intrinsic::eh_unwind_init:
4467 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4469 case Intrinsic::eh_dwarf_cfa: {
4470 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4471 TLI.getPointerTy());
4472 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4474 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4475 TLI.getPointerTy()),
4477 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4479 DAG.getConstant(0, TLI.getPointerTy()));
4480 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4484 case Intrinsic::eh_sjlj_callsite: {
4485 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4486 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4487 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4488 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4490 MMI.setCurrentCallSite(CI->getZExtValue());
4493 case Intrinsic::eh_sjlj_setjmp: {
4494 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4495 getValue(I.getArgOperand(0))));
4498 case Intrinsic::eh_sjlj_longjmp: {
4499 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4500 getRoot(), getValue(I.getArgOperand(0))));
4503 case Intrinsic::eh_sjlj_dispatch_setup: {
4504 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4505 getRoot(), getValue(I.getArgOperand(0))));
4509 case Intrinsic::x86_mmx_pslli_w:
4510 case Intrinsic::x86_mmx_pslli_d:
4511 case Intrinsic::x86_mmx_pslli_q:
4512 case Intrinsic::x86_mmx_psrli_w:
4513 case Intrinsic::x86_mmx_psrli_d:
4514 case Intrinsic::x86_mmx_psrli_q:
4515 case Intrinsic::x86_mmx_psrai_w:
4516 case Intrinsic::x86_mmx_psrai_d: {
4517 SDValue ShAmt = getValue(I.getArgOperand(1));
4518 if (isa<ConstantSDNode>(ShAmt)) {
4519 visitTargetIntrinsic(I, Intrinsic);
4522 unsigned NewIntrinsic = 0;
4523 EVT ShAmtVT = MVT::v2i32;
4524 switch (Intrinsic) {
4525 case Intrinsic::x86_mmx_pslli_w:
4526 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4528 case Intrinsic::x86_mmx_pslli_d:
4529 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4531 case Intrinsic::x86_mmx_pslli_q:
4532 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4534 case Intrinsic::x86_mmx_psrli_w:
4535 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4537 case Intrinsic::x86_mmx_psrli_d:
4538 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4540 case Intrinsic::x86_mmx_psrli_q:
4541 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4543 case Intrinsic::x86_mmx_psrai_w:
4544 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4546 case Intrinsic::x86_mmx_psrai_d:
4547 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4549 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4552 // The vector shift intrinsics with scalars uses 32b shift amounts but
4553 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4555 // We must do this early because v2i32 is not a legal type.
4556 DebugLoc dl = getCurDebugLoc();
4559 ShOps[1] = DAG.getConstant(0, MVT::i32);
4560 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4561 EVT DestVT = TLI.getValueType(I.getType());
4562 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4563 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4564 DAG.getConstant(NewIntrinsic, MVT::i32),
4565 getValue(I.getArgOperand(0)), ShAmt);
4569 case Intrinsic::convertff:
4570 case Intrinsic::convertfsi:
4571 case Intrinsic::convertfui:
4572 case Intrinsic::convertsif:
4573 case Intrinsic::convertuif:
4574 case Intrinsic::convertss:
4575 case Intrinsic::convertsu:
4576 case Intrinsic::convertus:
4577 case Intrinsic::convertuu: {
4578 ISD::CvtCode Code = ISD::CVT_INVALID;
4579 switch (Intrinsic) {
4580 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4581 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4582 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4583 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4584 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4585 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4586 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4587 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4588 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4590 EVT DestVT = TLI.getValueType(I.getType());
4591 const Value *Op1 = I.getArgOperand(0);
4592 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4593 DAG.getValueType(DestVT),
4594 DAG.getValueType(getValue(Op1).getValueType()),
4595 getValue(I.getArgOperand(1)),
4596 getValue(I.getArgOperand(2)),
4601 case Intrinsic::sqrt:
4602 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4603 getValue(I.getArgOperand(0)).getValueType(),
4604 getValue(I.getArgOperand(0))));
4606 case Intrinsic::powi:
4607 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4608 getValue(I.getArgOperand(1)), DAG));
4610 case Intrinsic::sin:
4611 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4612 getValue(I.getArgOperand(0)).getValueType(),
4613 getValue(I.getArgOperand(0))));
4615 case Intrinsic::cos:
4616 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4617 getValue(I.getArgOperand(0)).getValueType(),
4618 getValue(I.getArgOperand(0))));
4620 case Intrinsic::log:
4623 case Intrinsic::log2:
4626 case Intrinsic::log10:
4629 case Intrinsic::exp:
4632 case Intrinsic::exp2:
4635 case Intrinsic::pow:
4638 case Intrinsic::convert_to_fp16:
4639 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4640 MVT::i16, getValue(I.getArgOperand(0))));
4642 case Intrinsic::convert_from_fp16:
4643 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4644 MVT::f32, getValue(I.getArgOperand(0))));
4646 case Intrinsic::pcmarker: {
4647 SDValue Tmp = getValue(I.getArgOperand(0));
4648 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4651 case Intrinsic::readcyclecounter: {
4652 SDValue Op = getRoot();
4653 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4654 DAG.getVTList(MVT::i64, MVT::Other),
4657 DAG.setRoot(Res.getValue(1));
4660 case Intrinsic::bswap:
4661 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4662 getValue(I.getArgOperand(0)).getValueType(),
4663 getValue(I.getArgOperand(0))));
4665 case Intrinsic::cttz: {
4666 SDValue Arg = getValue(I.getArgOperand(0));
4667 EVT Ty = Arg.getValueType();
4668 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4671 case Intrinsic::ctlz: {
4672 SDValue Arg = getValue(I.getArgOperand(0));
4673 EVT Ty = Arg.getValueType();
4674 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4677 case Intrinsic::ctpop: {
4678 SDValue Arg = getValue(I.getArgOperand(0));
4679 EVT Ty = Arg.getValueType();
4680 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4683 case Intrinsic::stacksave: {
4684 SDValue Op = getRoot();
4685 Res = DAG.getNode(ISD::STACKSAVE, dl,
4686 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4688 DAG.setRoot(Res.getValue(1));
4691 case Intrinsic::stackrestore: {
4692 Res = getValue(I.getArgOperand(0));
4693 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4696 case Intrinsic::stackprotector: {
4697 // Emit code into the DAG to store the stack guard onto the stack.
4698 MachineFunction &MF = DAG.getMachineFunction();
4699 MachineFrameInfo *MFI = MF.getFrameInfo();
4700 EVT PtrTy = TLI.getPointerTy();
4702 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4703 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4705 int FI = FuncInfo.StaticAllocaMap[Slot];
4706 MFI->setStackProtectorIndex(FI);
4708 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4710 // Store the stack protector onto the stack.
4711 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4712 MachinePointerInfo::getFixedStack(FI),
4718 case Intrinsic::objectsize: {
4719 // If we don't know by now, we're never going to know.
4720 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4722 assert(CI && "Non-constant type in __builtin_object_size?");
4724 SDValue Arg = getValue(I.getCalledValue());
4725 EVT Ty = Arg.getValueType();
4728 Res = DAG.getConstant(-1ULL, Ty);
4730 Res = DAG.getConstant(0, Ty);
4735 case Intrinsic::var_annotation:
4736 // Discard annotate attributes
4739 case Intrinsic::init_trampoline: {
4740 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4744 Ops[1] = getValue(I.getArgOperand(0));
4745 Ops[2] = getValue(I.getArgOperand(1));
4746 Ops[3] = getValue(I.getArgOperand(2));
4747 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4748 Ops[5] = DAG.getSrcValue(F);
4750 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4751 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4755 DAG.setRoot(Res.getValue(1));
4758 case Intrinsic::gcroot:
4760 const Value *Alloca = I.getArgOperand(0);
4761 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4763 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4764 GFI->addStackRoot(FI->getIndex(), TypeMap);
4767 case Intrinsic::gcread:
4768 case Intrinsic::gcwrite:
4769 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4771 case Intrinsic::flt_rounds:
4772 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4774 case Intrinsic::trap: {
4775 StringRef TrapFuncName = getTrapFunctionName();
4776 if (TrapFuncName.empty()) {
4777 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4780 TargetLowering::ArgListTy Args;
4781 std::pair<SDValue, SDValue> Result =
4782 TLI.LowerCallTo(getRoot(), I.getType(),
4783 false, false, false, false, 0, CallingConv::C,
4784 /*isTailCall=*/false, /*isReturnValueUsed=*/true,
4785 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
4786 Args, DAG, getCurDebugLoc());
4787 DAG.setRoot(Result.second);
4790 case Intrinsic::uadd_with_overflow:
4791 return implVisitAluOverflow(I, ISD::UADDO);
4792 case Intrinsic::sadd_with_overflow:
4793 return implVisitAluOverflow(I, ISD::SADDO);
4794 case Intrinsic::usub_with_overflow:
4795 return implVisitAluOverflow(I, ISD::USUBO);
4796 case Intrinsic::ssub_with_overflow:
4797 return implVisitAluOverflow(I, ISD::SSUBO);
4798 case Intrinsic::umul_with_overflow:
4799 return implVisitAluOverflow(I, ISD::UMULO);
4800 case Intrinsic::smul_with_overflow:
4801 return implVisitAluOverflow(I, ISD::SMULO);
4803 case Intrinsic::prefetch: {
4805 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4807 Ops[1] = getValue(I.getArgOperand(0));
4808 Ops[2] = getValue(I.getArgOperand(1));
4809 Ops[3] = getValue(I.getArgOperand(2));
4810 Ops[4] = getValue(I.getArgOperand(3));
4811 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4812 DAG.getVTList(MVT::Other),
4814 EVT::getIntegerVT(*Context, 8),
4815 MachinePointerInfo(I.getArgOperand(0)),
4817 false, /* volatile */
4819 rw==1)); /* write */
4822 case Intrinsic::memory_barrier: {
4825 for (int x = 1; x < 6; ++x)
4826 Ops[x] = getValue(I.getArgOperand(x - 1));
4828 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4831 case Intrinsic::atomic_cmp_swap: {
4832 SDValue Root = getRoot();
4834 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4835 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4837 getValue(I.getArgOperand(0)),
4838 getValue(I.getArgOperand(1)),
4839 getValue(I.getArgOperand(2)),
4840 MachinePointerInfo(I.getArgOperand(0)));
4842 DAG.setRoot(L.getValue(1));
4845 case Intrinsic::atomic_load_add:
4846 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4847 case Intrinsic::atomic_load_sub:
4848 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4849 case Intrinsic::atomic_load_or:
4850 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4851 case Intrinsic::atomic_load_xor:
4852 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4853 case Intrinsic::atomic_load_and:
4854 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4855 case Intrinsic::atomic_load_nand:
4856 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4857 case Intrinsic::atomic_load_max:
4858 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4859 case Intrinsic::atomic_load_min:
4860 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4861 case Intrinsic::atomic_load_umin:
4862 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4863 case Intrinsic::atomic_load_umax:
4864 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4865 case Intrinsic::atomic_swap:
4866 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4868 case Intrinsic::invariant_start:
4869 case Intrinsic::lifetime_start:
4870 // Discard region information.
4871 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4873 case Intrinsic::invariant_end:
4874 case Intrinsic::lifetime_end:
4875 // Discard region information.
4880 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4882 MachineBasicBlock *LandingPad) {
4883 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4884 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4885 const Type *RetTy = FTy->getReturnType();
4886 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4887 MCSymbol *BeginLabel = 0;
4889 TargetLowering::ArgListTy Args;
4890 TargetLowering::ArgListEntry Entry;
4891 Args.reserve(CS.arg_size());
4893 // Check whether the function can return without sret-demotion.
4894 SmallVector<ISD::OutputArg, 4> Outs;
4895 SmallVector<uint64_t, 4> Offsets;
4896 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4897 Outs, TLI, &Offsets);
4899 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4900 DAG.getMachineFunction(),
4901 FTy->isVarArg(), Outs,
4904 SDValue DemoteStackSlot;
4905 int DemoteStackIdx = -100;
4907 if (!CanLowerReturn) {
4908 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4909 FTy->getReturnType());
4910 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4911 FTy->getReturnType());
4912 MachineFunction &MF = DAG.getMachineFunction();
4913 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4914 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4916 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4917 Entry.Node = DemoteStackSlot;
4918 Entry.Ty = StackSlotPtrType;
4919 Entry.isSExt = false;
4920 Entry.isZExt = false;
4921 Entry.isInReg = false;
4922 Entry.isSRet = true;
4923 Entry.isNest = false;
4924 Entry.isByVal = false;
4925 Entry.Alignment = Align;
4926 Args.push_back(Entry);
4927 RetTy = Type::getVoidTy(FTy->getContext());
4930 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4932 const Value *V = *i;
4935 if (V->getType()->isEmptyTy())
4938 SDValue ArgNode = getValue(V);
4939 Entry.Node = ArgNode; Entry.Ty = V->getType();
4941 unsigned attrInd = i - CS.arg_begin() + 1;
4942 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4943 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4944 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4945 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4946 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4947 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4948 Entry.Alignment = CS.getParamAlignment(attrInd);
4949 Args.push_back(Entry);
4953 // Insert a label before the invoke call to mark the try range. This can be
4954 // used to detect deletion of the invoke via the MachineModuleInfo.
4955 BeginLabel = MMI.getContext().CreateTempSymbol();
4957 // For SjLj, keep track of which landing pads go with which invokes
4958 // so as to maintain the ordering of pads in the LSDA.
4959 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4960 if (CallSiteIndex) {
4961 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4962 // Now that the call site is handled, stop tracking it.
4963 MMI.setCurrentCallSite(0);
4966 // Both PendingLoads and PendingExports must be flushed here;
4967 // this call might not return.
4969 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4972 // Check if target-independent constraints permit a tail call here.
4973 // Target-dependent constraints are checked within TLI.LowerCallTo.
4975 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4978 // If there's a possibility that fast-isel has already selected some amount
4979 // of the current basic block, don't emit a tail call.
4980 if (isTailCall && EnableFastISel)
4983 std::pair<SDValue,SDValue> Result =
4984 TLI.LowerCallTo(getRoot(), RetTy,
4985 CS.paramHasAttr(0, Attribute::SExt),
4986 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4987 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4988 CS.getCallingConv(),
4990 !CS.getInstruction()->use_empty(),
4991 Callee, Args, DAG, getCurDebugLoc());
4992 assert((isTailCall || Result.second.getNode()) &&
4993 "Non-null chain expected with non-tail call!");
4994 assert((Result.second.getNode() || !Result.first.getNode()) &&
4995 "Null value expected with tail call!");
4996 if (Result.first.getNode()) {
4997 setValue(CS.getInstruction(), Result.first);
4998 } else if (!CanLowerReturn && Result.second.getNode()) {
4999 // The instruction result is the result of loading from the
5000 // hidden sret parameter.
5001 SmallVector<EVT, 1> PVTs;
5002 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5004 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5005 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5006 EVT PtrVT = PVTs[0];
5007 unsigned NumValues = Outs.size();
5008 SmallVector<SDValue, 4> Values(NumValues);
5009 SmallVector<SDValue, 4> Chains(NumValues);
5011 for (unsigned i = 0; i < NumValues; ++i) {
5012 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5014 DAG.getConstant(Offsets[i], PtrVT));
5015 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
5017 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5020 Chains[i] = L.getValue(1);
5023 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5024 MVT::Other, &Chains[0], NumValues);
5025 PendingLoads.push_back(Chain);
5027 // Collect the legal value parts into potentially illegal values
5028 // that correspond to the original function's return values.
5029 SmallVector<EVT, 4> RetTys;
5030 RetTy = FTy->getReturnType();
5031 ComputeValueVTs(TLI, RetTy, RetTys);
5032 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5033 SmallVector<SDValue, 4> ReturnValues;
5034 unsigned CurReg = 0;
5035 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5037 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
5038 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
5040 SDValue ReturnValue =
5041 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
5042 RegisterVT, VT, AssertOp);
5043 ReturnValues.push_back(ReturnValue);
5047 setValue(CS.getInstruction(),
5048 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5049 DAG.getVTList(&RetTys[0], RetTys.size()),
5050 &ReturnValues[0], ReturnValues.size()));
5053 // Assign order to nodes here. If the call does not produce a result, it won't
5054 // be mapped to a SDNode and visit() will not assign it an order number.
5055 if (!Result.second.getNode()) {
5056 // As a special case, a null chain means that a tail call has been emitted and
5057 // the DAG root is already updated.
5060 AssignOrderingToNode(DAG.getRoot().getNode());
5062 DAG.setRoot(Result.second);
5064 AssignOrderingToNode(Result.second.getNode());
5068 // Insert a label at the end of the invoke call to mark the try range. This
5069 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5070 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5071 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5073 // Inform MachineModuleInfo of range.
5074 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5078 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5079 /// value is equal or not-equal to zero.
5080 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5081 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5083 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5084 if (IC->isEquality())
5085 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5086 if (C->isNullValue())
5088 // Unknown instruction.
5094 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5096 SelectionDAGBuilder &Builder) {
5098 // Check to see if this load can be trivially constant folded, e.g. if the
5099 // input is from a string literal.
5100 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5101 // Cast pointer to the type we really want to load.
5102 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5103 PointerType::getUnqual(LoadTy));
5105 if (const Constant *LoadCst =
5106 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5108 return Builder.getValue(LoadCst);
5111 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5112 // still constant memory, the input chain can be the entry node.
5114 bool ConstantMemory = false;
5116 // Do not serialize (non-volatile) loads of constant memory with anything.
5117 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5118 Root = Builder.DAG.getEntryNode();
5119 ConstantMemory = true;
5121 // Do not serialize non-volatile loads against each other.
5122 Root = Builder.DAG.getRoot();
5125 SDValue Ptr = Builder.getValue(PtrVal);
5126 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5127 Ptr, MachinePointerInfo(PtrVal),
5129 false /*nontemporal*/, 1 /* align=1 */);
5131 if (!ConstantMemory)
5132 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5137 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5138 /// If so, return true and lower it, otherwise return false and it will be
5139 /// lowered like a normal call.
5140 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5141 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5142 if (I.getNumArgOperands() != 3)
5145 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5146 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5147 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5148 !I.getType()->isIntegerTy())
5151 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5153 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5154 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5155 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5156 bool ActuallyDoIt = true;
5159 switch (Size->getZExtValue()) {
5161 LoadVT = MVT::Other;
5163 ActuallyDoIt = false;
5167 LoadTy = Type::getInt16Ty(Size->getContext());
5171 LoadTy = Type::getInt32Ty(Size->getContext());
5175 LoadTy = Type::getInt64Ty(Size->getContext());
5179 LoadVT = MVT::v4i32;
5180 LoadTy = Type::getInt32Ty(Size->getContext());
5181 LoadTy = VectorType::get(LoadTy, 4);
5186 // This turns into unaligned loads. We only do this if the target natively
5187 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5188 // we'll only produce a small number of byte loads.
5190 // Require that we can find a legal MVT, and only do this if the target
5191 // supports unaligned loads of that type. Expanding into byte loads would
5193 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5194 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5195 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5196 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5197 ActuallyDoIt = false;
5201 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5202 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5204 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5206 EVT CallVT = TLI.getValueType(I.getType(), true);
5207 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5217 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5218 // Handle inline assembly differently.
5219 if (isa<InlineAsm>(I.getCalledValue())) {
5224 // See if any floating point values are being passed to this function. This is
5225 // used to emit an undefined reference to fltused on Windows.
5226 const FunctionType *FT =
5227 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5228 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5229 if (FT->isVarArg() &&
5230 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5231 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5232 const Type* T = I.getArgOperand(i)->getType();
5233 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T);
5235 if (!i->isFloatingPointTy()) continue;
5236 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5242 const char *RenameFn = 0;
5243 if (Function *F = I.getCalledFunction()) {
5244 if (F->isDeclaration()) {
5245 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5246 if (unsigned IID = II->getIntrinsicID(F)) {
5247 RenameFn = visitIntrinsicCall(I, IID);
5252 if (unsigned IID = F->getIntrinsicID()) {
5253 RenameFn = visitIntrinsicCall(I, IID);
5259 // Check for well-known libc/libm calls. If the function is internal, it
5260 // can't be a library call.
5261 if (!F->hasLocalLinkage() && F->hasName()) {
5262 StringRef Name = F->getName();
5263 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5264 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5265 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5266 I.getType() == I.getArgOperand(0)->getType() &&
5267 I.getType() == I.getArgOperand(1)->getType()) {
5268 SDValue LHS = getValue(I.getArgOperand(0));
5269 SDValue RHS = getValue(I.getArgOperand(1));
5270 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5271 LHS.getValueType(), LHS, RHS));
5274 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5275 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5276 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5277 I.getType() == I.getArgOperand(0)->getType()) {
5278 SDValue Tmp = getValue(I.getArgOperand(0));
5279 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5280 Tmp.getValueType(), Tmp));
5283 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5284 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5285 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5286 I.getType() == I.getArgOperand(0)->getType() &&
5287 I.onlyReadsMemory()) {
5288 SDValue Tmp = getValue(I.getArgOperand(0));
5289 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5290 Tmp.getValueType(), Tmp));
5293 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5294 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5295 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5296 I.getType() == I.getArgOperand(0)->getType() &&
5297 I.onlyReadsMemory()) {
5298 SDValue Tmp = getValue(I.getArgOperand(0));
5299 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5300 Tmp.getValueType(), Tmp));
5303 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5304 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5305 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5306 I.getType() == I.getArgOperand(0)->getType() &&
5307 I.onlyReadsMemory()) {
5308 SDValue Tmp = getValue(I.getArgOperand(0));
5309 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5310 Tmp.getValueType(), Tmp));
5313 } else if (Name == "memcmp") {
5314 if (visitMemCmpCall(I))
5322 Callee = getValue(I.getCalledValue());
5324 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5326 // Check if we can potentially perform a tail call. More detailed checking is
5327 // be done within LowerCallTo, after more information about the call is known.
5328 LowerCallTo(&I, Callee, I.isTailCall());
5333 /// AsmOperandInfo - This contains information for each constraint that we are
5335 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5337 /// CallOperand - If this is the result output operand or a clobber
5338 /// this is null, otherwise it is the incoming operand to the CallInst.
5339 /// This gets modified as the asm is processed.
5340 SDValue CallOperand;
5342 /// AssignedRegs - If this is a register or register class operand, this
5343 /// contains the set of register corresponding to the operand.
5344 RegsForValue AssignedRegs;
5346 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5347 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5350 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5351 /// busy in OutputRegs/InputRegs.
5352 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5353 std::set<unsigned> &OutputRegs,
5354 std::set<unsigned> &InputRegs,
5355 const TargetRegisterInfo &TRI) const {
5357 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5358 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5361 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5362 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5366 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5367 /// corresponds to. If there is no Value* for this operand, it returns
5369 EVT getCallOperandValEVT(LLVMContext &Context,
5370 const TargetLowering &TLI,
5371 const TargetData *TD) const {
5372 if (CallOperandVal == 0) return MVT::Other;
5374 if (isa<BasicBlock>(CallOperandVal))
5375 return TLI.getPointerTy();
5377 const llvm::Type *OpTy = CallOperandVal->getType();
5379 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5380 // If this is an indirect operand, the operand is a pointer to the
5383 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5385 report_fatal_error("Indirect operand for inline asm not a pointer!");
5386 OpTy = PtrTy->getElementType();
5389 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5390 if (const StructType *STy = dyn_cast<StructType>(OpTy))
5391 if (STy->getNumElements() == 1)
5392 OpTy = STy->getElementType(0);
5394 // If OpTy is not a single value, it may be a struct/union that we
5395 // can tile with integers.
5396 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5397 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5406 OpTy = IntegerType::get(Context, BitSize);
5411 return TLI.getValueType(OpTy, true);
5415 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5417 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5418 const TargetRegisterInfo &TRI) {
5419 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5421 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5422 for (; *Aliases; ++Aliases)
5423 Regs.insert(*Aliases);
5427 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5429 } // end anonymous namespace
5431 /// isAllocatableRegister - If the specified register is safe to allocate,
5432 /// i.e. it isn't a stack pointer or some other special register, return the
5433 /// register class for the register. Otherwise, return null.
5434 static const TargetRegisterClass *
5435 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5436 const TargetLowering &TLI,
5437 const TargetRegisterInfo *TRI) {
5438 EVT FoundVT = MVT::Other;
5439 const TargetRegisterClass *FoundRC = 0;
5440 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5441 E = TRI->regclass_end(); RCI != E; ++RCI) {
5442 EVT ThisVT = MVT::Other;
5444 const TargetRegisterClass *RC = *RCI;
5445 if (!RC->isAllocatable())
5447 // If none of the value types for this register class are valid, we
5448 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5449 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5451 if (TLI.isTypeLegal(*I)) {
5452 // If we have already found this register in a different register class,
5453 // choose the one with the largest VT specified. For example, on
5454 // PowerPC, we favor f64 register classes over f32.
5455 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5462 if (ThisVT == MVT::Other) continue;
5464 // NOTE: This isn't ideal. In particular, this might allocate the
5465 // frame pointer in functions that need it (due to them not being taken
5466 // out of allocation, because a variable sized allocation hasn't been seen
5467 // yet). This is a slight code pessimization, but should still work.
5468 ArrayRef<unsigned> RawOrder = RC->getRawAllocationOrder(MF);
5469 if (std::find(RawOrder.begin(), RawOrder.end(), Reg) != RawOrder.end()) {
5470 // We found a matching register class. Keep looking at others in case
5471 // we find one with larger registers that this physreg is also in.
5480 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5481 /// specified operand. We prefer to assign virtual registers, to allow the
5482 /// register allocator to handle the assignment process. However, if the asm
5483 /// uses features that we can't model on machineinstrs, we have SDISel do the
5484 /// allocation. This produces generally horrible, but correct, code.
5486 /// OpInfo describes the operand.
5487 /// Input and OutputRegs are the set of already allocated physical registers.
5489 static void GetRegistersForValue(SelectionDAG &DAG,
5490 const TargetLowering &TLI,
5492 SDISelAsmOperandInfo &OpInfo,
5493 std::set<unsigned> &OutputRegs,
5494 std::set<unsigned> &InputRegs) {
5495 LLVMContext &Context = *DAG.getContext();
5497 // Compute whether this value requires an input register, an output register,
5499 bool isOutReg = false;
5500 bool isInReg = false;
5501 switch (OpInfo.Type) {
5502 case InlineAsm::isOutput:
5505 // If there is an input constraint that matches this, we need to reserve
5506 // the input register so no other inputs allocate to it.
5507 isInReg = OpInfo.hasMatchingInput();
5509 case InlineAsm::isInput:
5513 case InlineAsm::isClobber:
5520 MachineFunction &MF = DAG.getMachineFunction();
5521 SmallVector<unsigned, 4> Regs;
5523 // If this is a constraint for a single physreg, or a constraint for a
5524 // register class, find it.
5525 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5526 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5527 OpInfo.ConstraintVT);
5529 unsigned NumRegs = 1;
5530 if (OpInfo.ConstraintVT != MVT::Other) {
5531 // If this is a FP input in an integer register (or visa versa) insert a bit
5532 // cast of the input value. More generally, handle any case where the input
5533 // value disagrees with the register class we plan to stick this in.
5534 if (OpInfo.Type == InlineAsm::isInput &&
5535 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5536 // Try to convert to the first EVT that the reg class contains. If the
5537 // types are identical size, use a bitcast to convert (e.g. two differing
5539 EVT RegVT = *PhysReg.second->vt_begin();
5540 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5541 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5542 RegVT, OpInfo.CallOperand);
5543 OpInfo.ConstraintVT = RegVT;
5544 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5545 // If the input is a FP value and we want it in FP registers, do a
5546 // bitcast to the corresponding integer type. This turns an f64 value
5547 // into i64, which can be passed with two i32 values on a 32-bit
5549 RegVT = EVT::getIntegerVT(Context,
5550 OpInfo.ConstraintVT.getSizeInBits());
5551 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5552 RegVT, OpInfo.CallOperand);
5553 OpInfo.ConstraintVT = RegVT;
5557 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5561 EVT ValueVT = OpInfo.ConstraintVT;
5563 // If this is a constraint for a specific physical register, like {r17},
5565 if (unsigned AssignedReg = PhysReg.first) {
5566 const TargetRegisterClass *RC = PhysReg.second;
5567 if (OpInfo.ConstraintVT == MVT::Other)
5568 ValueVT = *RC->vt_begin();
5570 // Get the actual register value type. This is important, because the user
5571 // may have asked for (e.g.) the AX register in i32 type. We need to
5572 // remember that AX is actually i16 to get the right extension.
5573 RegVT = *RC->vt_begin();
5575 // This is a explicit reference to a physical register.
5576 Regs.push_back(AssignedReg);
5578 // If this is an expanded reference, add the rest of the regs to Regs.
5580 TargetRegisterClass::iterator I = RC->begin();
5581 for (; *I != AssignedReg; ++I)
5582 assert(I != RC->end() && "Didn't find reg!");
5584 // Already added the first reg.
5586 for (; NumRegs; --NumRegs, ++I) {
5587 assert(I != RC->end() && "Ran out of registers to allocate!");
5592 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5593 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5594 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5598 // Otherwise, if this was a reference to an LLVM register class, create vregs
5599 // for this reference.
5600 if (const TargetRegisterClass *RC = PhysReg.second) {
5601 RegVT = *RC->vt_begin();
5602 if (OpInfo.ConstraintVT == MVT::Other)
5605 // Create the appropriate number of virtual registers.
5606 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5607 for (; NumRegs; --NumRegs)
5608 Regs.push_back(RegInfo.createVirtualRegister(RC));
5610 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5614 // This is a reference to a register class that doesn't directly correspond
5615 // to an LLVM register class. Allocate NumRegs consecutive, available,
5616 // registers from the class.
5617 std::vector<unsigned> RegClassRegs
5618 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5619 OpInfo.ConstraintVT);
5621 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5622 BitVector Reserved = TRI->getReservedRegs(MF);
5623 unsigned NumAllocated = 0;
5624 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5625 unsigned Reg = RegClassRegs[i];
5626 // Filter out the reserved registers, but note that reserved registers are
5627 // not fully determined at this point. We may still decide we need a frame
5629 if (Reserved.test(Reg))
5631 // See if this register is available.
5632 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5633 (isInReg && InputRegs.count(Reg))) { // Already used.
5634 // Make sure we find consecutive registers.
5639 // Check to see if this register is allocatable (i.e. don't give out the
5641 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5642 if (!RC) { // Couldn't allocate this register.
5643 // Reset NumAllocated to make sure we return consecutive registers.
5648 // Okay, this register is good, we can use it.
5651 // If we allocated enough consecutive registers, succeed.
5652 if (NumAllocated == NumRegs) {
5653 unsigned RegStart = (i-NumAllocated)+1;
5654 unsigned RegEnd = i+1;
5655 // Mark all of the allocated registers used.
5656 for (unsigned i = RegStart; i != RegEnd; ++i)
5657 Regs.push_back(RegClassRegs[i]);
5659 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5660 OpInfo.ConstraintVT);
5661 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5666 // Otherwise, we couldn't allocate enough registers for this.
5669 /// visitInlineAsm - Handle a call to an InlineAsm object.
5671 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5672 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5674 /// ConstraintOperands - Information about all of the constraints.
5675 SDISelAsmOperandInfoVector ConstraintOperands;
5677 std::set<unsigned> OutputRegs, InputRegs;
5679 TargetLowering::AsmOperandInfoVector
5680 TargetConstraints = TLI.ParseConstraints(CS);
5682 bool hasMemory = false;
5684 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5685 unsigned ResNo = 0; // ResNo - The result number of the next output.
5686 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5687 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5688 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5690 EVT OpVT = MVT::Other;
5692 // Compute the value type for each operand.
5693 switch (OpInfo.Type) {
5694 case InlineAsm::isOutput:
5695 // Indirect outputs just consume an argument.
5696 if (OpInfo.isIndirect) {
5697 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5701 // The return value of the call is this value. As such, there is no
5702 // corresponding argument.
5703 assert(!CS.getType()->isVoidTy() &&
5705 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5706 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5708 assert(ResNo == 0 && "Asm only has one result!");
5709 OpVT = TLI.getValueType(CS.getType());
5713 case InlineAsm::isInput:
5714 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5716 case InlineAsm::isClobber:
5721 // If this is an input or an indirect output, process the call argument.
5722 // BasicBlocks are labels, currently appearing only in asm's.
5723 if (OpInfo.CallOperandVal) {
5724 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5725 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5727 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5730 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5733 OpInfo.ConstraintVT = OpVT;
5735 // Indirect operand accesses access memory.
5736 if (OpInfo.isIndirect)
5739 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5740 TargetLowering::ConstraintType
5741 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5742 if (CType == TargetLowering::C_Memory) {
5750 SDValue Chain, Flag;
5752 // We won't need to flush pending loads if this asm doesn't touch
5753 // memory and is nonvolatile.
5754 if (hasMemory || IA->hasSideEffects())
5757 Chain = DAG.getRoot();
5759 // Second pass over the constraints: compute which constraint option to use
5760 // and assign registers to constraints that want a specific physreg.
5761 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5762 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5764 // If this is an output operand with a matching input operand, look up the
5765 // matching input. If their types mismatch, e.g. one is an integer, the
5766 // other is floating point, or their sizes are different, flag it as an
5768 if (OpInfo.hasMatchingInput()) {
5769 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5771 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5772 if ((OpInfo.ConstraintVT.isInteger() !=
5773 Input.ConstraintVT.isInteger()) ||
5774 (OpInfo.ConstraintVT.getSizeInBits() !=
5775 Input.ConstraintVT.getSizeInBits())) {
5776 report_fatal_error("Unsupported asm: input constraint"
5777 " with a matching output constraint of"
5778 " incompatible type!");
5780 Input.ConstraintVT = OpInfo.ConstraintVT;
5784 // Compute the constraint code and ConstraintType to use.
5785 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5787 // If this is a memory input, and if the operand is not indirect, do what we
5788 // need to to provide an address for the memory input.
5789 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5790 !OpInfo.isIndirect) {
5791 assert((OpInfo.isMultipleAlternative ||
5792 (OpInfo.Type == InlineAsm::isInput)) &&
5793 "Can only indirectify direct input operands!");
5795 // Memory operands really want the address of the value. If we don't have
5796 // an indirect input, put it in the constpool if we can, otherwise spill
5797 // it to a stack slot.
5798 // TODO: This isn't quite right. We need to handle these according to
5799 // the addressing mode that the constraint wants. Also, this may take
5800 // an additional register for the computation and we don't want that
5803 // If the operand is a float, integer, or vector constant, spill to a
5804 // constant pool entry to get its address.
5805 const Value *OpVal = OpInfo.CallOperandVal;
5806 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5807 isa<ConstantVector>(OpVal)) {
5808 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5809 TLI.getPointerTy());
5811 // Otherwise, create a stack slot and emit a store to it before the
5813 const Type *Ty = OpVal->getType();
5814 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5815 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5816 MachineFunction &MF = DAG.getMachineFunction();
5817 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5818 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5819 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5820 OpInfo.CallOperand, StackSlot,
5821 MachinePointerInfo::getFixedStack(SSFI),
5823 OpInfo.CallOperand = StackSlot;
5826 // There is no longer a Value* corresponding to this operand.
5827 OpInfo.CallOperandVal = 0;
5829 // It is now an indirect operand.
5830 OpInfo.isIndirect = true;
5833 // If this constraint is for a specific register, allocate it before
5835 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5836 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
5840 // Second pass - Loop over all of the operands, assigning virtual or physregs
5841 // to register class operands.
5842 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5843 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5845 // C_Register operands have already been allocated, Other/Memory don't need
5847 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5848 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
5852 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5853 std::vector<SDValue> AsmNodeOperands;
5854 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5855 AsmNodeOperands.push_back(
5856 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5857 TLI.getPointerTy()));
5859 // If we have a !srcloc metadata node associated with it, we want to attach
5860 // this to the ultimately generated inline asm machineinstr. To do this, we
5861 // pass in the third operand as this (potentially null) inline asm MDNode.
5862 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5863 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5865 // Remember the HasSideEffect and AlignStack bits as operand 3.
5866 unsigned ExtraInfo = 0;
5867 if (IA->hasSideEffects())
5868 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5869 if (IA->isAlignStack())
5870 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5871 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
5872 TLI.getPointerTy()));
5874 // Loop over all of the inputs, copying the operand values into the
5875 // appropriate registers and processing the output regs.
5876 RegsForValue RetValRegs;
5878 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5879 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5881 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5882 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5884 switch (OpInfo.Type) {
5885 case InlineAsm::isOutput: {
5886 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5887 OpInfo.ConstraintType != TargetLowering::C_Register) {
5888 // Memory output, or 'other' output (e.g. 'X' constraint).
5889 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5891 // Add information to the INLINEASM node to know about this output.
5892 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5893 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5894 TLI.getPointerTy()));
5895 AsmNodeOperands.push_back(OpInfo.CallOperand);
5899 // Otherwise, this is a register or register class output.
5901 // Copy the output from the appropriate register. Find a register that
5903 if (OpInfo.AssignedRegs.Regs.empty())
5904 report_fatal_error("Couldn't allocate output reg for constraint '" +
5905 Twine(OpInfo.ConstraintCode) + "'!");
5907 // If this is an indirect operand, store through the pointer after the
5909 if (OpInfo.isIndirect) {
5910 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5911 OpInfo.CallOperandVal));
5913 // This is the result value of the call.
5914 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5915 // Concatenate this output onto the outputs list.
5916 RetValRegs.append(OpInfo.AssignedRegs);
5919 // Add information to the INLINEASM node to know that this register is
5921 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5922 InlineAsm::Kind_RegDefEarlyClobber :
5923 InlineAsm::Kind_RegDef,
5930 case InlineAsm::isInput: {
5931 SDValue InOperandVal = OpInfo.CallOperand;
5933 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5934 // If this is required to match an output register we have already set,
5935 // just use its register.
5936 unsigned OperandNo = OpInfo.getMatchedOperand();
5938 // Scan until we find the definition we already emitted of this operand.
5939 // When we find it, create a RegsForValue operand.
5940 unsigned CurOp = InlineAsm::Op_FirstOperand;
5941 for (; OperandNo; --OperandNo) {
5942 // Advance to the next operand.
5944 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5945 assert((InlineAsm::isRegDefKind(OpFlag) ||
5946 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5947 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5948 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5952 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5953 if (InlineAsm::isRegDefKind(OpFlag) ||
5954 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5955 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5956 if (OpInfo.isIndirect) {
5957 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5958 LLVMContext &Ctx = *DAG.getContext();
5959 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5960 " don't know how to handle tied "
5961 "indirect register inputs");
5964 RegsForValue MatchedRegs;
5965 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5966 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5967 MatchedRegs.RegVTs.push_back(RegVT);
5968 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5969 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5971 MatchedRegs.Regs.push_back
5972 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5974 // Use the produced MatchedRegs object to
5975 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5977 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5978 true, OpInfo.getMatchedOperand(),
5979 DAG, AsmNodeOperands);
5983 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5984 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5985 "Unexpected number of operands");
5986 // Add information to the INLINEASM node to know about this input.
5987 // See InlineAsm.h isUseOperandTiedToDef.
5988 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5989 OpInfo.getMatchedOperand());
5990 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5991 TLI.getPointerTy()));
5992 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5996 // Treat indirect 'X' constraint as memory.
5997 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5999 OpInfo.ConstraintType = TargetLowering::C_Memory;
6001 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6002 std::vector<SDValue> Ops;
6003 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6006 report_fatal_error("Invalid operand for inline asm constraint '" +
6007 Twine(OpInfo.ConstraintCode) + "'!");
6009 // Add information to the INLINEASM node to know about this input.
6010 unsigned ResOpType =
6011 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6012 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6013 TLI.getPointerTy()));
6014 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6018 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6019 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6020 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6021 "Memory operands expect pointer values");
6023 // Add information to the INLINEASM node to know about this input.
6024 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6025 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6026 TLI.getPointerTy()));
6027 AsmNodeOperands.push_back(InOperandVal);
6031 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6032 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6033 "Unknown constraint type!");
6034 assert(!OpInfo.isIndirect &&
6035 "Don't know how to handle indirect register inputs yet!");
6037 // Copy the input into the appropriate registers.
6038 if (OpInfo.AssignedRegs.Regs.empty() ||
6039 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
6040 report_fatal_error("Couldn't allocate input reg for constraint '" +
6041 Twine(OpInfo.ConstraintCode) + "'!");
6043 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6046 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6047 DAG, AsmNodeOperands);
6050 case InlineAsm::isClobber: {
6051 // Add the clobbered value to the operand list, so that the register
6052 // allocator is aware that the physreg got clobbered.
6053 if (!OpInfo.AssignedRegs.Regs.empty())
6054 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6062 // Finish up input operands. Set the input chain and add the flag last.
6063 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6064 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6066 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6067 DAG.getVTList(MVT::Other, MVT::Glue),
6068 &AsmNodeOperands[0], AsmNodeOperands.size());
6069 Flag = Chain.getValue(1);
6071 // If this asm returns a register value, copy the result from that register
6072 // and set it as the value of the call.
6073 if (!RetValRegs.Regs.empty()) {
6074 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6077 // FIXME: Why don't we do this for inline asms with MRVs?
6078 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6079 EVT ResultType = TLI.getValueType(CS.getType());
6081 // If any of the results of the inline asm is a vector, it may have the
6082 // wrong width/num elts. This can happen for register classes that can
6083 // contain multiple different value types. The preg or vreg allocated may
6084 // not have the same VT as was expected. Convert it to the right type
6085 // with bit_convert.
6086 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6087 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6090 } else if (ResultType != Val.getValueType() &&
6091 ResultType.isInteger() && Val.getValueType().isInteger()) {
6092 // If a result value was tied to an input value, the computed result may
6093 // have a wider width than the expected result. Extract the relevant
6095 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6098 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6101 setValue(CS.getInstruction(), Val);
6102 // Don't need to use this as a chain in this case.
6103 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6107 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6109 // Process indirect outputs, first output all of the flagged copies out of
6111 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6112 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6113 const Value *Ptr = IndirectStoresToEmit[i].second;
6114 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6116 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6119 // Emit the non-flagged stores from the physregs.
6120 SmallVector<SDValue, 8> OutChains;
6121 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6122 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6123 StoresToEmit[i].first,
6124 getValue(StoresToEmit[i].second),
6125 MachinePointerInfo(StoresToEmit[i].second),
6127 OutChains.push_back(Val);
6130 if (!OutChains.empty())
6131 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6132 &OutChains[0], OutChains.size());
6137 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6138 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6139 MVT::Other, getRoot(),
6140 getValue(I.getArgOperand(0)),
6141 DAG.getSrcValue(I.getArgOperand(0))));
6144 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6145 const TargetData &TD = *TLI.getTargetData();
6146 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6147 getRoot(), getValue(I.getOperand(0)),
6148 DAG.getSrcValue(I.getOperand(0)),
6149 TD.getABITypeAlignment(I.getType()));
6151 DAG.setRoot(V.getValue(1));
6154 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6155 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6156 MVT::Other, getRoot(),
6157 getValue(I.getArgOperand(0)),
6158 DAG.getSrcValue(I.getArgOperand(0))));
6161 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6162 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6163 MVT::Other, getRoot(),
6164 getValue(I.getArgOperand(0)),
6165 getValue(I.getArgOperand(1)),
6166 DAG.getSrcValue(I.getArgOperand(0)),
6167 DAG.getSrcValue(I.getArgOperand(1))));
6170 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6171 /// implementation, which just calls LowerCall.
6172 /// FIXME: When all targets are
6173 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6174 std::pair<SDValue, SDValue>
6175 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
6176 bool RetSExt, bool RetZExt, bool isVarArg,
6177 bool isInreg, unsigned NumFixedArgs,
6178 CallingConv::ID CallConv, bool isTailCall,
6179 bool isReturnValueUsed,
6181 ArgListTy &Args, SelectionDAG &DAG,
6182 DebugLoc dl) const {
6183 // Handle all of the outgoing arguments.
6184 SmallVector<ISD::OutputArg, 32> Outs;
6185 SmallVector<SDValue, 32> OutVals;
6186 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6187 SmallVector<EVT, 4> ValueVTs;
6188 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6189 for (unsigned Value = 0, NumValues = ValueVTs.size();
6190 Value != NumValues; ++Value) {
6191 EVT VT = ValueVTs[Value];
6192 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6193 SDValue Op = SDValue(Args[i].Node.getNode(),
6194 Args[i].Node.getResNo() + Value);
6195 ISD::ArgFlagsTy Flags;
6196 unsigned OriginalAlignment =
6197 getTargetData()->getABITypeAlignment(ArgTy);
6203 if (Args[i].isInReg)
6207 if (Args[i].isByVal) {
6209 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
6210 const Type *ElementTy = Ty->getElementType();
6211 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy));
6212 // For ByVal, alignment should come from FE. BE will guess if this
6213 // info is not there but there are cases it cannot get right.
6214 unsigned FrameAlign;
6215 if (Args[i].Alignment)
6216 FrameAlign = Args[i].Alignment;
6218 FrameAlign = getByValTypeAlignment(ElementTy);
6219 Flags.setByValAlign(FrameAlign);
6223 Flags.setOrigAlign(OriginalAlignment);
6225 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6226 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6227 SmallVector<SDValue, 4> Parts(NumParts);
6228 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6231 ExtendKind = ISD::SIGN_EXTEND;
6232 else if (Args[i].isZExt)
6233 ExtendKind = ISD::ZERO_EXTEND;
6235 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6236 PartVT, ExtendKind);
6238 for (unsigned j = 0; j != NumParts; ++j) {
6239 // if it isn't first piece, alignment must be 1
6240 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6242 if (NumParts > 1 && j == 0)
6243 MyFlags.Flags.setSplit();
6245 MyFlags.Flags.setOrigAlign(1);
6247 Outs.push_back(MyFlags);
6248 OutVals.push_back(Parts[j]);
6253 // Handle the incoming return values from the call.
6254 SmallVector<ISD::InputArg, 32> Ins;
6255 SmallVector<EVT, 4> RetTys;
6256 ComputeValueVTs(*this, RetTy, RetTys);
6257 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6259 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6260 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6261 for (unsigned i = 0; i != NumRegs; ++i) {
6262 ISD::InputArg MyFlags;
6263 MyFlags.VT = RegisterVT.getSimpleVT();
6264 MyFlags.Used = isReturnValueUsed;
6266 MyFlags.Flags.setSExt();
6268 MyFlags.Flags.setZExt();
6270 MyFlags.Flags.setInReg();
6271 Ins.push_back(MyFlags);
6275 SmallVector<SDValue, 4> InVals;
6276 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6277 Outs, OutVals, Ins, dl, DAG, InVals);
6279 // Verify that the target's LowerCall behaved as expected.
6280 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6281 "LowerCall didn't return a valid chain!");
6282 assert((!isTailCall || InVals.empty()) &&
6283 "LowerCall emitted a return value for a tail call!");
6284 assert((isTailCall || InVals.size() == Ins.size()) &&
6285 "LowerCall didn't emit the correct number of values!");
6287 // For a tail call, the return value is merely live-out and there aren't
6288 // any nodes in the DAG representing it. Return a special value to
6289 // indicate that a tail call has been emitted and no more Instructions
6290 // should be processed in the current block.
6293 return std::make_pair(SDValue(), SDValue());
6296 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6297 assert(InVals[i].getNode() &&
6298 "LowerCall emitted a null value!");
6299 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6300 "LowerCall emitted a value with the wrong type!");
6303 // Collect the legal value parts into potentially illegal values
6304 // that correspond to the original function's return values.
6305 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6307 AssertOp = ISD::AssertSext;
6309 AssertOp = ISD::AssertZext;
6310 SmallVector<SDValue, 4> ReturnValues;
6311 unsigned CurReg = 0;
6312 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6314 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6315 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6317 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6318 NumRegs, RegisterVT, VT,
6323 // For a function returning void, there is no return value. We can't create
6324 // such a node, so we just return a null return value in that case. In
6325 // that case, nothing will actually look at the value.
6326 if (ReturnValues.empty())
6327 return std::make_pair(SDValue(), Chain);
6329 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6330 DAG.getVTList(&RetTys[0], RetTys.size()),
6331 &ReturnValues[0], ReturnValues.size());
6332 return std::make_pair(Res, Chain);
6335 void TargetLowering::LowerOperationWrapper(SDNode *N,
6336 SmallVectorImpl<SDValue> &Results,
6337 SelectionDAG &DAG) const {
6338 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6340 Results.push_back(Res);
6343 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6344 llvm_unreachable("LowerOperation not implemented for this target!");
6349 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6350 SDValue Op = getNonRegisterValue(V);
6351 assert((Op.getOpcode() != ISD::CopyFromReg ||
6352 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6353 "Copy from a reg to the same reg!");
6354 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6356 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6357 SDValue Chain = DAG.getEntryNode();
6358 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6359 PendingExports.push_back(Chain);
6362 #include "llvm/CodeGen/SelectionDAGISel.h"
6364 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6365 /// entry block, return true. This includes arguments used by switches, since
6366 /// the switch may expand into multiple basic blocks.
6367 static bool isOnlyUsedInEntryBlock(const Argument *A) {
6368 // With FastISel active, we may be splitting blocks, so force creation
6369 // of virtual registers for all non-dead arguments.
6371 return A->use_empty();
6373 const BasicBlock *Entry = A->getParent()->begin();
6374 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6376 const User *U = *UI;
6377 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6378 return false; // Use not in entry block.
6383 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6384 // If this is the entry block, emit arguments.
6385 const Function &F = *LLVMBB->getParent();
6386 SelectionDAG &DAG = SDB->DAG;
6387 DebugLoc dl = SDB->getCurDebugLoc();
6388 const TargetData *TD = TLI.getTargetData();
6389 SmallVector<ISD::InputArg, 16> Ins;
6391 // Check whether the function can return without sret-demotion.
6392 SmallVector<ISD::OutputArg, 4> Outs;
6393 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6396 if (!FuncInfo->CanLowerReturn) {
6397 // Put in an sret pointer parameter before all the other parameters.
6398 SmallVector<EVT, 1> ValueVTs;
6399 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6401 // NOTE: Assuming that a pointer will never break down to more than one VT
6403 ISD::ArgFlagsTy Flags;
6405 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6406 ISD::InputArg RetArg(Flags, RegisterVT, true);
6407 Ins.push_back(RetArg);
6410 // Set up the incoming argument description vector.
6412 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6413 I != E; ++I, ++Idx) {
6414 SmallVector<EVT, 4> ValueVTs;
6415 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6416 bool isArgValueUsed = !I->use_empty();
6417 for (unsigned Value = 0, NumValues = ValueVTs.size();
6418 Value != NumValues; ++Value) {
6419 EVT VT = ValueVTs[Value];
6420 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6421 ISD::ArgFlagsTy Flags;
6422 unsigned OriginalAlignment =
6423 TD->getABITypeAlignment(ArgTy);
6425 if (F.paramHasAttr(Idx, Attribute::ZExt))
6427 if (F.paramHasAttr(Idx, Attribute::SExt))
6429 if (F.paramHasAttr(Idx, Attribute::InReg))
6431 if (F.paramHasAttr(Idx, Attribute::StructRet))
6433 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6435 const PointerType *Ty = cast<PointerType>(I->getType());
6436 const Type *ElementTy = Ty->getElementType();
6437 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6438 // For ByVal, alignment should be passed from FE. BE will guess if
6439 // this info is not there but there are cases it cannot get right.
6440 unsigned FrameAlign;
6441 if (F.getParamAlignment(Idx))
6442 FrameAlign = F.getParamAlignment(Idx);
6444 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6445 Flags.setByValAlign(FrameAlign);
6447 if (F.paramHasAttr(Idx, Attribute::Nest))
6449 Flags.setOrigAlign(OriginalAlignment);
6451 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6452 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6453 for (unsigned i = 0; i != NumRegs; ++i) {
6454 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6455 if (NumRegs > 1 && i == 0)
6456 MyFlags.Flags.setSplit();
6457 // if it isn't first piece, alignment must be 1
6459 MyFlags.Flags.setOrigAlign(1);
6460 Ins.push_back(MyFlags);
6465 // Call the target to set up the argument values.
6466 SmallVector<SDValue, 8> InVals;
6467 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6471 // Verify that the target's LowerFormalArguments behaved as expected.
6472 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6473 "LowerFormalArguments didn't return a valid chain!");
6474 assert(InVals.size() == Ins.size() &&
6475 "LowerFormalArguments didn't emit the correct number of values!");
6477 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6478 assert(InVals[i].getNode() &&
6479 "LowerFormalArguments emitted a null value!");
6480 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6481 "LowerFormalArguments emitted a value with the wrong type!");
6485 // Update the DAG with the new chain value resulting from argument lowering.
6486 DAG.setRoot(NewRoot);
6488 // Set up the argument values.
6491 if (!FuncInfo->CanLowerReturn) {
6492 // Create a virtual register for the sret pointer, and put in a copy
6493 // from the sret argument into it.
6494 SmallVector<EVT, 1> ValueVTs;
6495 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6496 EVT VT = ValueVTs[0];
6497 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6498 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6499 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6500 RegVT, VT, AssertOp);
6502 MachineFunction& MF = SDB->DAG.getMachineFunction();
6503 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6504 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6505 FuncInfo->DemoteRegister = SRetReg;
6506 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6508 DAG.setRoot(NewRoot);
6510 // i indexes lowered arguments. Bump it past the hidden sret argument.
6511 // Idx indexes LLVM arguments. Don't touch it.
6515 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6517 SmallVector<SDValue, 4> ArgValues;
6518 SmallVector<EVT, 4> ValueVTs;
6519 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6520 unsigned NumValues = ValueVTs.size();
6522 // If this argument is unused then remember its value. It is used to generate
6523 // debugging information.
6524 if (I->use_empty() && NumValues)
6525 SDB->setUnusedArgValue(I, InVals[i]);
6527 for (unsigned Val = 0; Val != NumValues; ++Val) {
6528 EVT VT = ValueVTs[Val];
6529 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6530 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6532 if (!I->use_empty()) {
6533 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6534 if (F.paramHasAttr(Idx, Attribute::SExt))
6535 AssertOp = ISD::AssertSext;
6536 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6537 AssertOp = ISD::AssertZext;
6539 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6540 NumParts, PartVT, VT,
6547 // We don't need to do anything else for unused arguments.
6548 if (ArgValues.empty())
6551 // Note down frame index for byval arguments.
6552 if (I->hasByValAttr())
6553 if (FrameIndexSDNode *FI =
6554 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6555 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6557 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6558 SDB->getCurDebugLoc());
6559 SDB->setValue(I, Res);
6561 // If this argument is live outside of the entry block, insert a copy from
6562 // wherever we got it to the vreg that other BB's will reference it as.
6563 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6564 // If we can, though, try to skip creating an unnecessary vreg.
6565 // FIXME: This isn't very clean... it would be nice to make this more
6566 // general. It's also subtly incompatible with the hacks FastISel
6568 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6569 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6570 FuncInfo->ValueMap[I] = Reg;
6574 if (!isOnlyUsedInEntryBlock(I)) {
6575 FuncInfo->InitializeRegForValue(I);
6576 SDB->CopyToExportRegsIfNeeded(I);
6580 assert(i == InVals.size() && "Argument register count mismatch!");
6582 // Finally, if the target has anything special to do, allow it to do so.
6583 // FIXME: this should insert code into the DAG!
6584 EmitFunctionEntryCode();
6587 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6588 /// ensure constants are generated when needed. Remember the virtual registers
6589 /// that need to be added to the Machine PHI nodes as input. We cannot just
6590 /// directly add them, because expansion might result in multiple MBB's for one
6591 /// BB. As such, the start of the BB might correspond to a different MBB than
6595 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6596 const TerminatorInst *TI = LLVMBB->getTerminator();
6598 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6600 // Check successor nodes' PHI nodes that expect a constant to be available
6602 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6603 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6604 if (!isa<PHINode>(SuccBB->begin())) continue;
6605 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6607 // If this terminator has multiple identical successors (common for
6608 // switches), only handle each succ once.
6609 if (!SuccsHandled.insert(SuccMBB)) continue;
6611 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6613 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6614 // nodes and Machine PHI nodes, but the incoming operands have not been
6616 for (BasicBlock::const_iterator I = SuccBB->begin();
6617 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6618 // Ignore dead phi's.
6619 if (PN->use_empty()) continue;
6622 if (PN->getType()->isEmptyTy())
6626 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6628 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6629 unsigned &RegOut = ConstantsOut[C];
6631 RegOut = FuncInfo.CreateRegs(C->getType());
6632 CopyValueToVirtualRegister(C, RegOut);
6636 DenseMap<const Value *, unsigned>::iterator I =
6637 FuncInfo.ValueMap.find(PHIOp);
6638 if (I != FuncInfo.ValueMap.end())
6641 assert(isa<AllocaInst>(PHIOp) &&
6642 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6643 "Didn't codegen value into a register!??");
6644 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6645 CopyValueToVirtualRegister(PHIOp, Reg);
6649 // Remember that this register needs to added to the machine PHI node as
6650 // the input for this MBB.
6651 SmallVector<EVT, 4> ValueVTs;
6652 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6653 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6654 EVT VT = ValueVTs[vti];
6655 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6656 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6657 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6658 Reg += NumRegisters;
6662 ConstantsOut.clear();