1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
81 // Limit the width of DAG chains. This is important in general to prevent
82 // prevent DAG-based analysis from blowing up. For example, alias analysis and
83 // load clustering may not complete in reasonable time. It is difficult to
84 // recognize and avoid this situation within each individual analysis, and
85 // future analyses are likely to have the same behavior. Limiting DAG width is
86 // the safe approach, and will be especially important with global DAGs.
88 // MaxParallelChains default is arbitrarily high to avoid affecting
89 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
90 // sequence over this should have been converted to llvm.memcpy by the
91 // frontend. It easy to induce this behavior with .ll code such as:
92 // %buffer = alloca [4096 x i8]
93 // %data = load [4096 x i8]* %argPtr
94 // store [4096 x i8] %data, [4096 x i8]* %buffer
95 static const unsigned MaxParallelChains = 64;
97 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
98 const SDValue *Parts, unsigned NumParts,
99 MVT PartVT, EVT ValueVT, const Value *V);
101 /// getCopyFromParts - Create a value that contains the specified legal parts
102 /// combined into the value they represent. If the parts combine to a type
103 /// larger then ValueVT then AssertOp can be used to specify whether the extra
104 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
105 /// (ISD::AssertSext).
106 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
107 const SDValue *Parts,
108 unsigned NumParts, MVT PartVT, EVT ValueVT,
110 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
111 if (ValueVT.isVector())
112 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
115 assert(NumParts > 0 && "No parts to assemble!");
116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
117 SDValue Val = Parts[0];
120 // Assemble the value from multiple parts.
121 if (ValueVT.isInteger()) {
122 unsigned PartBits = PartVT.getSizeInBits();
123 unsigned ValueBits = ValueVT.getSizeInBits();
125 // Assemble the power of 2 part.
126 unsigned RoundParts = NumParts & (NumParts - 1) ?
127 1 << Log2_32(NumParts) : NumParts;
128 unsigned RoundBits = PartBits * RoundParts;
129 EVT RoundVT = RoundBits == ValueBits ?
130 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
133 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
135 if (RoundParts > 2) {
136 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
138 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
139 RoundParts / 2, PartVT, HalfVT, V);
141 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
142 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
145 if (TLI.isBigEndian())
148 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
150 if (RoundParts < NumParts) {
151 // Assemble the trailing non-power-of-2 part.
152 unsigned OddParts = NumParts - RoundParts;
153 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
154 Hi = getCopyFromParts(DAG, DL,
155 Parts + RoundParts, OddParts, PartVT, OddVT, V);
157 // Combine the round and odd parts.
159 if (TLI.isBigEndian())
161 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
162 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
163 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
164 DAG.getConstant(Lo.getValueType().getSizeInBits(),
165 TLI.getPointerTy()));
166 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
167 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
169 } else if (PartVT.isFloatingPoint()) {
170 // FP split into multiple FP parts (for ppcf128)
171 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
174 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
175 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
176 if (TLI.hasBigEndianPartOrdering(ValueVT))
178 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
180 // FP split into integer parts (soft fp)
181 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
182 !PartVT.isVector() && "Unexpected split");
183 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
184 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
188 // There is now one part, held in Val. Correct it to match ValueVT.
189 EVT PartEVT = Val.getValueType();
191 if (PartEVT == ValueVT)
194 if (PartEVT.isInteger() && ValueVT.isInteger()) {
195 if (ValueVT.bitsLT(PartEVT)) {
196 // For a truncate, see if we have any information to
197 // indicate whether the truncated bits will always be
198 // zero or sign-extension.
199 if (AssertOp != ISD::DELETED_NODE)
200 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
201 DAG.getValueType(ValueVT));
202 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
204 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
207 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
208 // FP_ROUND's are always exact here.
209 if (ValueVT.bitsLT(Val.getValueType()))
210 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
211 DAG.getTargetConstant(1, TLI.getPointerTy()));
213 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
216 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
217 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
219 llvm_unreachable("Unknown mismatch!");
222 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
223 const Twine &ErrMsg) {
224 const Instruction *I = dyn_cast_or_null<Instruction>(V);
226 return Ctx.emitError(ErrMsg);
228 const char *AsmError = ", possible invalid constraint for vector type";
229 if (const CallInst *CI = dyn_cast<CallInst>(I))
230 if (isa<InlineAsm>(CI->getCalledValue()))
231 return Ctx.emitError(I, ErrMsg + AsmError);
233 return Ctx.emitError(I, ErrMsg);
236 /// getCopyFromPartsVector - Create a value that contains the specified legal
237 /// parts combined into the value they represent. If the parts combine to a
238 /// type larger then ValueVT then AssertOp can be used to specify whether the
239 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
240 /// ValueVT (ISD::AssertSext).
241 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
242 const SDValue *Parts, unsigned NumParts,
243 MVT PartVT, EVT ValueVT, const Value *V) {
244 assert(ValueVT.isVector() && "Not a vector value");
245 assert(NumParts > 0 && "No parts to assemble!");
246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
247 SDValue Val = Parts[0];
249 // Handle a multi-element vector.
253 unsigned NumIntermediates;
255 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
256 NumIntermediates, RegisterVT);
257 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
258 NumParts = NumRegs; // Silence a compiler warning.
259 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
260 assert(RegisterVT == Parts[0].getSimpleValueType() &&
261 "Part type doesn't match part!");
263 // Assemble the parts into intermediate operands.
264 SmallVector<SDValue, 8> Ops(NumIntermediates);
265 if (NumIntermediates == NumParts) {
266 // If the register was not expanded, truncate or copy the value,
268 for (unsigned i = 0; i != NumParts; ++i)
269 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
270 PartVT, IntermediateVT, V);
271 } else if (NumParts > 0) {
272 // If the intermediate type was expanded, build the intermediate
273 // operands from the parts.
274 assert(NumParts % NumIntermediates == 0 &&
275 "Must expand into a divisible number of parts!");
276 unsigned Factor = NumParts / NumIntermediates;
277 for (unsigned i = 0; i != NumIntermediates; ++i)
278 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
279 PartVT, IntermediateVT, V);
282 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
283 // intermediate operands.
284 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
289 // There is now one part, held in Val. Correct it to match ValueVT.
290 EVT PartEVT = Val.getValueType();
292 if (PartEVT == ValueVT)
295 if (PartEVT.isVector()) {
296 // If the element type of the source/dest vectors are the same, but the
297 // parts vector has more elements than the value vector, then we have a
298 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
300 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
301 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
302 "Cannot narrow, it would be a lossy transformation");
303 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
304 DAG.getConstant(0, TLI.getVectorIdxTy()));
307 // Vector/Vector bitcast.
308 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
309 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
311 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
312 "Cannot handle this kind of promotion");
313 // Promoted vector extract
314 bool Smaller = ValueVT.bitsLE(PartEVT);
315 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
320 // Trivial bitcast if the types are the same size and the destination
321 // vector type is legal.
322 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
323 TLI.isTypeLegal(ValueVT))
324 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
326 // Handle cases such as i8 -> <1 x i1>
327 if (ValueVT.getVectorNumElements() != 1) {
328 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
329 "non-trivial scalar-to-vector conversion");
330 return DAG.getUNDEF(ValueVT);
333 if (ValueVT.getVectorNumElements() == 1 &&
334 ValueVT.getVectorElementType() != PartEVT) {
335 bool Smaller = ValueVT.bitsLE(PartEVT);
336 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
337 DL, ValueVT.getScalarType(), Val);
340 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
343 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
344 SDValue Val, SDValue *Parts, unsigned NumParts,
345 MVT PartVT, const Value *V);
347 /// getCopyToParts - Create a series of nodes that contain the specified value
348 /// split into legal parts. If the parts contain more bits than Val, then, for
349 /// integers, ExtendKind can be used to specify how to generate the extra bits.
350 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
351 SDValue Val, SDValue *Parts, unsigned NumParts,
352 MVT PartVT, const Value *V,
353 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
354 EVT ValueVT = Val.getValueType();
356 // Handle the vector case separately.
357 if (ValueVT.isVector())
358 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
360 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
361 unsigned PartBits = PartVT.getSizeInBits();
362 unsigned OrigNumParts = NumParts;
363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
368 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
369 EVT PartEVT = PartVT;
370 if (PartEVT == ValueVT) {
371 assert(NumParts == 1 && "No-op copy with multiple parts!");
376 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
377 // If the parts cover more bits than the value has, promote the value.
378 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
379 assert(NumParts == 1 && "Do not know what to promote to!");
380 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
382 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
383 ValueVT.isInteger() &&
384 "Unknown mismatch!");
385 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
386 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
387 if (PartVT == MVT::x86mmx)
388 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
390 } else if (PartBits == ValueVT.getSizeInBits()) {
391 // Different types of the same size.
392 assert(NumParts == 1 && PartEVT != ValueVT);
393 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
395 // If the parts cover less bits than value has, truncate the value.
396 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
397 ValueVT.isInteger() &&
398 "Unknown mismatch!");
399 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
400 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
401 if (PartVT == MVT::x86mmx)
402 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
405 // The value may have changed - recompute ValueVT.
406 ValueVT = Val.getValueType();
407 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
408 "Failed to tile the value with PartVT!");
411 if (PartEVT != ValueVT)
412 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
413 "scalar-to-vector conversion failed");
419 // Expand the value into multiple parts.
420 if (NumParts & (NumParts - 1)) {
421 // The number of parts is not a power of 2. Split off and copy the tail.
422 assert(PartVT.isInteger() && ValueVT.isInteger() &&
423 "Do not know what to expand to!");
424 unsigned RoundParts = 1 << Log2_32(NumParts);
425 unsigned RoundBits = RoundParts * PartBits;
426 unsigned OddParts = NumParts - RoundParts;
427 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
428 DAG.getIntPtrConstant(RoundBits));
429 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
431 if (TLI.isBigEndian())
432 // The odd parts were reversed by getCopyToParts - unreverse them.
433 std::reverse(Parts + RoundParts, Parts + NumParts);
435 NumParts = RoundParts;
436 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
437 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
440 // The number of parts is a power of 2. Repeatedly bisect the value using
442 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
443 EVT::getIntegerVT(*DAG.getContext(),
444 ValueVT.getSizeInBits()),
447 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
448 for (unsigned i = 0; i < NumParts; i += StepSize) {
449 unsigned ThisBits = StepSize * PartBits / 2;
450 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
451 SDValue &Part0 = Parts[i];
452 SDValue &Part1 = Parts[i+StepSize/2];
454 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
455 ThisVT, Part0, DAG.getIntPtrConstant(1));
456 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
457 ThisVT, Part0, DAG.getIntPtrConstant(0));
459 if (ThisBits == PartBits && ThisVT != PartVT) {
460 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
461 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
466 if (TLI.isBigEndian())
467 std::reverse(Parts, Parts + OrigNumParts);
471 /// getCopyToPartsVector - Create a series of nodes that contain the specified
472 /// value split into legal parts.
473 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
474 SDValue Val, SDValue *Parts, unsigned NumParts,
475 MVT PartVT, const Value *V) {
476 EVT ValueVT = Val.getValueType();
477 assert(ValueVT.isVector() && "Not a vector");
478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
481 EVT PartEVT = PartVT;
482 if (PartEVT == ValueVT) {
484 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
485 // Bitconvert vector->vector case.
486 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
487 } else if (PartVT.isVector() &&
488 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
489 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
490 EVT ElementVT = PartVT.getVectorElementType();
491 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
493 SmallVector<SDValue, 16> Ops;
494 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
495 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
496 ElementVT, Val, DAG.getConstant(i,
497 TLI.getVectorIdxTy())));
499 for (unsigned i = ValueVT.getVectorNumElements(),
500 e = PartVT.getVectorNumElements(); i != e; ++i)
501 Ops.push_back(DAG.getUNDEF(ElementVT));
503 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
505 // FIXME: Use CONCAT for 2x -> 4x.
507 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
508 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
509 } else if (PartVT.isVector() &&
510 PartEVT.getVectorElementType().bitsGE(
511 ValueVT.getVectorElementType()) &&
512 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
514 // Promoted vector extract
515 bool Smaller = PartEVT.bitsLE(ValueVT);
516 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
519 // Vector -> scalar conversion.
520 assert(ValueVT.getVectorNumElements() == 1 &&
521 "Only trivial vector-to-scalar conversions should get here!");
522 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
523 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
525 bool Smaller = ValueVT.bitsLE(PartVT);
526 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
534 // Handle a multi-element vector.
537 unsigned NumIntermediates;
538 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
540 NumIntermediates, RegisterVT);
541 unsigned NumElements = ValueVT.getVectorNumElements();
543 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
544 NumParts = NumRegs; // Silence a compiler warning.
545 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
547 // Split the vector into intermediate operands.
548 SmallVector<SDValue, 8> Ops(NumIntermediates);
549 for (unsigned i = 0; i != NumIntermediates; ++i) {
550 if (IntermediateVT.isVector())
551 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
553 DAG.getConstant(i * (NumElements / NumIntermediates),
554 TLI.getVectorIdxTy()));
556 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
558 DAG.getConstant(i, TLI.getVectorIdxTy()));
561 // Split the intermediate operands into legal parts.
562 if (NumParts == NumIntermediates) {
563 // If the register was not expanded, promote or copy the value,
565 for (unsigned i = 0; i != NumParts; ++i)
566 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
567 } else if (NumParts > 0) {
568 // If the intermediate type was expanded, split each the value into
570 assert(NumIntermediates != 0 && "division by zero");
571 assert(NumParts % NumIntermediates == 0 &&
572 "Must expand into a divisible number of parts!");
573 unsigned Factor = NumParts / NumIntermediates;
574 for (unsigned i = 0; i != NumIntermediates; ++i)
575 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 /// RegsForValue - This struct represents the registers (physical or virtual)
581 /// that a particular set of values is assigned, and the type information
582 /// about the value. The most common situation is to represent one value at a
583 /// time, but struct or array values are handled element-wise as multiple
584 /// values. The splitting of aggregates is performed recursively, so that we
585 /// never have aggregate-typed registers. The values at this point do not
586 /// necessarily have legal types, so each value may require one or more
587 /// registers of some legal type.
589 struct RegsForValue {
590 /// ValueVTs - The value types of the values, which may not be legal, and
591 /// may need be promoted or synthesized from one or more registers.
593 SmallVector<EVT, 4> ValueVTs;
595 /// RegVTs - The value types of the registers. This is the same size as
596 /// ValueVTs and it records, for each value, what the type of the assigned
597 /// register or registers are. (Individual values are never synthesized
598 /// from more than one type of register.)
600 /// With virtual registers, the contents of RegVTs is redundant with TLI's
601 /// getRegisterType member function, however when with physical registers
602 /// it is necessary to have a separate record of the types.
604 SmallVector<MVT, 4> RegVTs;
606 /// Regs - This list holds the registers assigned to the values.
607 /// Each legal or promoted value requires one register, and each
608 /// expanded value requires multiple registers.
610 SmallVector<unsigned, 4> Regs;
614 RegsForValue(const SmallVector<unsigned, 4> ®s,
615 MVT regvt, EVT valuevt)
616 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
618 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
619 unsigned Reg, Type *Ty) {
620 ComputeValueVTs(tli, Ty, ValueVTs);
622 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
623 EVT ValueVT = ValueVTs[Value];
624 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
625 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
626 for (unsigned i = 0; i != NumRegs; ++i)
627 Regs.push_back(Reg + i);
628 RegVTs.push_back(RegisterVT);
633 /// append - Add the specified values to this one.
634 void append(const RegsForValue &RHS) {
635 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
636 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
637 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
640 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
641 /// this value and returns the result as a ValueVTs value. This uses
642 /// Chain/Flag as the input and updates them for the output Chain/Flag.
643 /// If the Flag pointer is NULL, no flag is used.
644 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
646 SDValue &Chain, SDValue *Flag,
647 const Value *V = nullptr) const;
649 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
650 /// specified value into the registers specified by this object. This uses
651 /// Chain/Flag as the input and updates them for the output Chain/Flag.
652 /// If the Flag pointer is NULL, no flag is used.
654 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
655 SDValue *Flag, const Value *V,
656 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
659 /// operand list. This adds the code marker, matching input operand index
660 /// (if applicable), and includes the number of values added into it.
661 void AddInlineAsmOperands(unsigned Kind,
662 bool HasMatching, unsigned MatchingIdx,
664 std::vector<SDValue> &Ops) const;
668 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
669 /// this value and returns the result as a ValueVT value. This uses
670 /// Chain/Flag as the input and updates them for the output Chain/Flag.
671 /// If the Flag pointer is NULL, no flag is used.
672 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
673 FunctionLoweringInfo &FuncInfo,
675 SDValue &Chain, SDValue *Flag,
676 const Value *V) const {
677 // A Value with type {} or [0 x %t] needs no registers.
678 if (ValueVTs.empty())
681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
683 // Assemble the legal parts into the final values.
684 SmallVector<SDValue, 4> Values(ValueVTs.size());
685 SmallVector<SDValue, 8> Parts;
686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
687 // Copy the legal parts from the registers.
688 EVT ValueVT = ValueVTs[Value];
689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
690 MVT RegisterVT = RegVTs[Value];
692 Parts.resize(NumRegs);
693 for (unsigned i = 0; i != NumRegs; ++i) {
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
699 *Flag = P.getValue(2);
702 Chain = P.getValue(1);
705 // If the source register was virtual and if we know something about it,
706 // add an assert node.
707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
708 !RegisterVT.isInteger() || RegisterVT.isVector())
711 const FunctionLoweringInfo::LiveOutInfo *LOI =
712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
716 unsigned RegSize = RegisterVT.getSizeInBits();
717 unsigned NumSignBits = LOI->NumSignBits;
718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
720 if (NumZeroBits == RegSize) {
721 // The current value is a zero.
722 // Explicitly express that as it would be easier for
723 // optimizations to kick in.
724 Parts[i] = DAG.getConstant(0, RegisterVT);
728 // FIXME: We capture more information than the dag can represent. For
729 // now, just use the tightest assertzext/assertsext possible.
731 EVT FromVT(MVT::Other);
732 if (NumSignBits == RegSize)
733 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
734 else if (NumZeroBits >= RegSize-1)
735 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
736 else if (NumSignBits > RegSize-8)
737 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
738 else if (NumZeroBits >= RegSize-8)
739 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
740 else if (NumSignBits > RegSize-16)
741 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
742 else if (NumZeroBits >= RegSize-16)
743 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
744 else if (NumSignBits > RegSize-32)
745 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
746 else if (NumZeroBits >= RegSize-32)
747 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
751 // Add an assertion node.
752 assert(FromVT != MVT::Other);
753 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
754 RegisterVT, P, DAG.getValueType(FromVT));
757 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
758 NumRegs, RegisterVT, ValueVT, V);
763 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
766 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
767 /// specified value into the registers specified by this object. This uses
768 /// Chain/Flag as the input and updates them for the output Chain/Flag.
769 /// If the Flag pointer is NULL, no flag is used.
770 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
771 SDValue &Chain, SDValue *Flag, const Value *V,
772 ISD::NodeType PreferredExtendType) const {
773 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
774 ISD::NodeType ExtendKind = PreferredExtendType;
776 // Get the list of the values's legal parts.
777 unsigned NumRegs = Regs.size();
778 SmallVector<SDValue, 8> Parts(NumRegs);
779 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
780 EVT ValueVT = ValueVTs[Value];
781 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
782 MVT RegisterVT = RegVTs[Value];
784 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
785 ExtendKind = ISD::ZERO_EXTEND;
787 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
788 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
792 // Copy the parts into the registers.
793 SmallVector<SDValue, 8> Chains(NumRegs);
794 for (unsigned i = 0; i != NumRegs; ++i) {
797 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
799 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
800 *Flag = Part.getValue(1);
803 Chains[i] = Part.getValue(0);
806 if (NumRegs == 1 || Flag)
807 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
808 // flagged to it. That is the CopyToReg nodes and the user are considered
809 // a single scheduling unit. If we create a TokenFactor and return it as
810 // chain, then the TokenFactor is both a predecessor (operand) of the
811 // user as well as a successor (the TF operands are flagged to the user).
812 // c1, f1 = CopyToReg
813 // c2, f2 = CopyToReg
814 // c3 = TokenFactor c1, c2
817 Chain = Chains[NumRegs-1];
819 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
822 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
823 /// operand list. This adds the code marker and includes the number of
824 /// values added into it.
825 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
826 unsigned MatchingIdx,
828 std::vector<SDValue> &Ops) const {
829 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
831 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
833 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
834 else if (!Regs.empty() &&
835 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
836 // Put the register class of the virtual registers in the flag word. That
837 // way, later passes can recompute register class constraints for inline
838 // assembly as well as normal instructions.
839 // Don't do this for tied operands that can use the regclass information
841 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
842 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
843 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
846 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
849 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
850 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
851 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
852 MVT RegisterVT = RegVTs[Value];
853 for (unsigned i = 0; i != NumRegs; ++i) {
854 assert(Reg < Regs.size() && "Mismatch in # registers expected");
855 unsigned TheReg = Regs[Reg++];
856 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
858 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
859 // If we clobbered the stack pointer, MFI should know about it.
860 assert(DAG.getMachineFunction().getFrameInfo()->
861 hasInlineAsmWithSPAdjust());
867 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
868 const TargetLibraryInfo *li) {
872 DL = DAG.getTarget().getDataLayout();
873 Context = DAG.getContext();
874 LPadToCallSiteMap.clear();
877 /// clear - Clear out the current SelectionDAG and the associated
878 /// state and prepare this SelectionDAGBuilder object to be used
879 /// for a new block. This doesn't clear out information about
880 /// additional blocks that are needed to complete switch lowering
881 /// or PHI node updating; that information is cleared out as it is
883 void SelectionDAGBuilder::clear() {
885 UnusedArgNodeMap.clear();
886 PendingLoads.clear();
887 PendingExports.clear();
890 SDNodeOrder = LowestSDNodeOrder;
891 StatepointLowering.clear();
894 /// clearDanglingDebugInfo - Clear the dangling debug information
895 /// map. This function is separated from the clear so that debug
896 /// information that is dangling in a basic block can be properly
897 /// resolved in a different basic block. This allows the
898 /// SelectionDAG to resolve dangling debug information attached
900 void SelectionDAGBuilder::clearDanglingDebugInfo() {
901 DanglingDebugInfoMap.clear();
904 /// getRoot - Return the current virtual root of the Selection DAG,
905 /// flushing any PendingLoad items. This must be done before emitting
906 /// a store or any other node that may need to be ordered after any
907 /// prior load instructions.
909 SDValue SelectionDAGBuilder::getRoot() {
910 if (PendingLoads.empty())
911 return DAG.getRoot();
913 if (PendingLoads.size() == 1) {
914 SDValue Root = PendingLoads[0];
916 PendingLoads.clear();
920 // Otherwise, we have to make a token factor node.
921 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
923 PendingLoads.clear();
928 /// getControlRoot - Similar to getRoot, but instead of flushing all the
929 /// PendingLoad items, flush all the PendingExports items. It is necessary
930 /// to do this before emitting a terminator instruction.
932 SDValue SelectionDAGBuilder::getControlRoot() {
933 SDValue Root = DAG.getRoot();
935 if (PendingExports.empty())
938 // Turn all of the CopyToReg chains into one factored node.
939 if (Root.getOpcode() != ISD::EntryToken) {
940 unsigned i = 0, e = PendingExports.size();
941 for (; i != e; ++i) {
942 assert(PendingExports[i].getNode()->getNumOperands() > 1);
943 if (PendingExports[i].getNode()->getOperand(0) == Root)
944 break; // Don't add the root if we already indirectly depend on it.
948 PendingExports.push_back(Root);
951 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
953 PendingExports.clear();
958 void SelectionDAGBuilder::visit(const Instruction &I) {
959 // Set up outgoing PHI node register values before emitting the terminator.
960 if (isa<TerminatorInst>(&I))
961 HandlePHINodesInSuccessorBlocks(I.getParent());
967 visit(I.getOpcode(), I);
969 if (!isa<TerminatorInst>(&I) && !HasTailCall)
970 CopyToExportRegsIfNeeded(&I);
975 void SelectionDAGBuilder::visitPHI(const PHINode &) {
976 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
979 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
980 // Note: this doesn't use InstVisitor, because it has to work with
981 // ConstantExpr's in addition to instructions.
983 default: llvm_unreachable("Unknown instruction type encountered!");
984 // Build the switch statement using the Instruction.def file.
985 #define HANDLE_INST(NUM, OPCODE, CLASS) \
986 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
987 #include "llvm/IR/Instruction.def"
991 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
992 // generate the debug data structures now that we've seen its definition.
993 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
995 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
997 const DbgValueInst *DI = DDI.getDI();
998 DebugLoc dl = DDI.getdl();
999 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1000 MDNode *Variable = DI->getVariable();
1001 MDNode *Expr = DI->getExpression();
1002 uint64_t Offset = DI->getOffset();
1003 // A dbg.value for an alloca is always indirect.
1004 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1006 if (Val.getNode()) {
1007 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, Offset, IsIndirect,
1009 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1010 IsIndirect, Offset, dl, DbgSDNodeOrder);
1011 DAG.AddDbgValue(SDV, Val.getNode(), false);
1014 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1015 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1019 /// getCopyFromRegs - If there was virtual register allocated for the value V
1020 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1021 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1022 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1025 if (It != FuncInfo.ValueMap.end()) {
1026 unsigned InReg = It->second;
1027 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1029 SDValue Chain = DAG.getEntryNode();
1030 res = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1031 resolveDanglingDebugInfo(V, res);
1037 /// getValue - Return an SDValue for the given Value.
1038 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1039 // If we already have an SDValue for this value, use it. It's important
1040 // to do this first, so that we don't create a CopyFromReg if we already
1041 // have a regular SDValue.
1042 SDValue &N = NodeMap[V];
1043 if (N.getNode()) return N;
1045 // If there's a virtual register allocated and initialized for this
1047 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
1048 if (copyFromReg.getNode()) {
1052 // Otherwise create a new SDValue and remember it.
1053 SDValue Val = getValueImpl(V);
1055 resolveDanglingDebugInfo(V, Val);
1059 /// getNonRegisterValue - Return an SDValue for the given Value, but
1060 /// don't look in FuncInfo.ValueMap for a virtual register.
1061 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1062 // If we already have an SDValue for this value, use it.
1063 SDValue &N = NodeMap[V];
1064 if (N.getNode()) return N;
1066 // Otherwise create a new SDValue and remember it.
1067 SDValue Val = getValueImpl(V);
1069 resolveDanglingDebugInfo(V, Val);
1073 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1074 /// Create an SDValue for the given value.
1075 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1078 if (const Constant *C = dyn_cast<Constant>(V)) {
1079 EVT VT = TLI.getValueType(V->getType(), true);
1081 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1082 return DAG.getConstant(*CI, VT);
1084 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1085 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1087 if (isa<ConstantPointerNull>(C)) {
1088 unsigned AS = V->getType()->getPointerAddressSpace();
1089 return DAG.getConstant(0, TLI.getPointerTy(AS));
1092 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1093 return DAG.getConstantFP(*CFP, VT);
1095 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1096 return DAG.getUNDEF(VT);
1098 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1099 visit(CE->getOpcode(), *CE);
1100 SDValue N1 = NodeMap[V];
1101 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1105 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1106 SmallVector<SDValue, 4> Constants;
1107 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1109 SDNode *Val = getValue(*OI).getNode();
1110 // If the operand is an empty aggregate, there are no values.
1112 // Add each leaf value from the operand to the Constants list
1113 // to form a flattened list of all the values.
1114 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1115 Constants.push_back(SDValue(Val, i));
1118 return DAG.getMergeValues(Constants, getCurSDLoc());
1121 if (const ConstantDataSequential *CDS =
1122 dyn_cast<ConstantDataSequential>(C)) {
1123 SmallVector<SDValue, 4> Ops;
1124 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1125 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1126 // Add each leaf value from the operand to the Constants list
1127 // to form a flattened list of all the values.
1128 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1129 Ops.push_back(SDValue(Val, i));
1132 if (isa<ArrayType>(CDS->getType()))
1133 return DAG.getMergeValues(Ops, getCurSDLoc());
1134 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1138 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1139 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1140 "Unknown struct or array constant!");
1142 SmallVector<EVT, 4> ValueVTs;
1143 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1144 unsigned NumElts = ValueVTs.size();
1146 return SDValue(); // empty struct
1147 SmallVector<SDValue, 4> Constants(NumElts);
1148 for (unsigned i = 0; i != NumElts; ++i) {
1149 EVT EltVT = ValueVTs[i];
1150 if (isa<UndefValue>(C))
1151 Constants[i] = DAG.getUNDEF(EltVT);
1152 else if (EltVT.isFloatingPoint())
1153 Constants[i] = DAG.getConstantFP(0, EltVT);
1155 Constants[i] = DAG.getConstant(0, EltVT);
1158 return DAG.getMergeValues(Constants, getCurSDLoc());
1161 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1162 return DAG.getBlockAddress(BA, VT);
1164 VectorType *VecTy = cast<VectorType>(V->getType());
1165 unsigned NumElements = VecTy->getNumElements();
1167 // Now that we know the number and type of the elements, get that number of
1168 // elements into the Ops array based on what kind of constant it is.
1169 SmallVector<SDValue, 16> Ops;
1170 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1171 for (unsigned i = 0; i != NumElements; ++i)
1172 Ops.push_back(getValue(CV->getOperand(i)));
1174 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1175 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1178 if (EltVT.isFloatingPoint())
1179 Op = DAG.getConstantFP(0, EltVT);
1181 Op = DAG.getConstant(0, EltVT);
1182 Ops.assign(NumElements, Op);
1185 // Create a BUILD_VECTOR node.
1186 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1189 // If this is a static alloca, generate it as the frameindex instead of
1191 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1192 DenseMap<const AllocaInst*, int>::iterator SI =
1193 FuncInfo.StaticAllocaMap.find(AI);
1194 if (SI != FuncInfo.StaticAllocaMap.end())
1195 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1198 // If this is an instruction which fast-isel has deferred, select it now.
1199 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1200 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1201 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1202 SDValue Chain = DAG.getEntryNode();
1203 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1206 llvm_unreachable("Can't get register for value!");
1209 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1210 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1211 SDValue Chain = getControlRoot();
1212 SmallVector<ISD::OutputArg, 8> Outs;
1213 SmallVector<SDValue, 8> OutVals;
1215 if (!FuncInfo.CanLowerReturn) {
1216 unsigned DemoteReg = FuncInfo.DemoteRegister;
1217 const Function *F = I.getParent()->getParent();
1219 // Emit a store of the return value through the virtual register.
1220 // Leave Outs empty so that LowerReturn won't try to load return
1221 // registers the usual way.
1222 SmallVector<EVT, 1> PtrValueVTs;
1223 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1226 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1227 SDValue RetOp = getValue(I.getOperand(0));
1229 SmallVector<EVT, 4> ValueVTs;
1230 SmallVector<uint64_t, 4> Offsets;
1231 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1232 unsigned NumValues = ValueVTs.size();
1234 SmallVector<SDValue, 4> Chains(NumValues);
1235 for (unsigned i = 0; i != NumValues; ++i) {
1236 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1237 RetPtr.getValueType(), RetPtr,
1238 DAG.getIntPtrConstant(Offsets[i]));
1240 DAG.getStore(Chain, getCurSDLoc(),
1241 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1242 // FIXME: better loc info would be nice.
1243 Add, MachinePointerInfo(), false, false, 0);
1246 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1247 MVT::Other, Chains);
1248 } else if (I.getNumOperands() != 0) {
1249 SmallVector<EVT, 4> ValueVTs;
1250 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1251 unsigned NumValues = ValueVTs.size();
1253 SDValue RetOp = getValue(I.getOperand(0));
1255 const Function *F = I.getParent()->getParent();
1257 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1258 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1260 ExtendKind = ISD::SIGN_EXTEND;
1261 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1263 ExtendKind = ISD::ZERO_EXTEND;
1265 LLVMContext &Context = F->getContext();
1266 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1269 for (unsigned j = 0; j != NumValues; ++j) {
1270 EVT VT = ValueVTs[j];
1272 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1273 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1275 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1276 MVT PartVT = TLI.getRegisterType(Context, VT);
1277 SmallVector<SDValue, 4> Parts(NumParts);
1278 getCopyToParts(DAG, getCurSDLoc(),
1279 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1280 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1282 // 'inreg' on function refers to return value
1283 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1287 // Propagate extension type if any
1288 if (ExtendKind == ISD::SIGN_EXTEND)
1290 else if (ExtendKind == ISD::ZERO_EXTEND)
1293 for (unsigned i = 0; i < NumParts; ++i) {
1294 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1295 VT, /*isfixed=*/true, 0, 0));
1296 OutVals.push_back(Parts[i]);
1302 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1303 CallingConv::ID CallConv =
1304 DAG.getMachineFunction().getFunction()->getCallingConv();
1305 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1306 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1308 // Verify that the target's LowerReturn behaved as expected.
1309 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1310 "LowerReturn didn't return a valid chain!");
1312 // Update the DAG with the new chain value resulting from return lowering.
1316 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1317 /// created for it, emit nodes to copy the value into the virtual
1319 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1321 if (V->getType()->isEmptyTy())
1324 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1325 if (VMI != FuncInfo.ValueMap.end()) {
1326 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1327 CopyValueToVirtualRegister(V, VMI->second);
1331 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1332 /// the current basic block, add it to ValueMap now so that we'll get a
1334 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1335 // No need to export constants.
1336 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1338 // Already exported?
1339 if (FuncInfo.isExportedInst(V)) return;
1341 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1342 CopyValueToVirtualRegister(V, Reg);
1345 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1346 const BasicBlock *FromBB) {
1347 // The operands of the setcc have to be in this block. We don't know
1348 // how to export them from some other block.
1349 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1350 // Can export from current BB.
1351 if (VI->getParent() == FromBB)
1354 // Is already exported, noop.
1355 return FuncInfo.isExportedInst(V);
1358 // If this is an argument, we can export it if the BB is the entry block or
1359 // if it is already exported.
1360 if (isa<Argument>(V)) {
1361 if (FromBB == &FromBB->getParent()->getEntryBlock())
1364 // Otherwise, can only export this if it is already exported.
1365 return FuncInfo.isExportedInst(V);
1368 // Otherwise, constants can always be exported.
1372 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1373 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1374 const MachineBasicBlock *Dst) const {
1375 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1378 const BasicBlock *SrcBB = Src->getBasicBlock();
1379 const BasicBlock *DstBB = Dst->getBasicBlock();
1380 return BPI->getEdgeWeight(SrcBB, DstBB);
1383 void SelectionDAGBuilder::
1384 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1385 uint32_t Weight /* = 0 */) {
1387 Weight = getEdgeWeight(Src, Dst);
1388 Src->addSuccessor(Dst, Weight);
1392 static bool InBlock(const Value *V, const BasicBlock *BB) {
1393 if (const Instruction *I = dyn_cast<Instruction>(V))
1394 return I->getParent() == BB;
1398 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1399 /// This function emits a branch and is used at the leaves of an OR or an
1400 /// AND operator tree.
1403 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1404 MachineBasicBlock *TBB,
1405 MachineBasicBlock *FBB,
1406 MachineBasicBlock *CurBB,
1407 MachineBasicBlock *SwitchBB,
1410 const BasicBlock *BB = CurBB->getBasicBlock();
1412 // If the leaf of the tree is a comparison, merge the condition into
1414 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1415 // The operands of the cmp have to be in this block. We don't know
1416 // how to export them from some other block. If this is the first block
1417 // of the sequence, no exporting is needed.
1418 if (CurBB == SwitchBB ||
1419 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1420 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1421 ISD::CondCode Condition;
1422 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1423 Condition = getICmpCondCode(IC->getPredicate());
1424 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1425 Condition = getFCmpCondCode(FC->getPredicate());
1426 if (TM.Options.NoNaNsFPMath)
1427 Condition = getFCmpCodeWithoutNaN(Condition);
1429 (void)Condition; // silence warning.
1430 llvm_unreachable("Unknown compare instruction");
1433 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1434 TBB, FBB, CurBB, TWeight, FWeight);
1435 SwitchCases.push_back(CB);
1440 // Create a CaseBlock record representing this branch.
1441 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1442 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1443 SwitchCases.push_back(CB);
1446 /// Scale down both weights to fit into uint32_t.
1447 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1448 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1449 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1450 NewTrue = NewTrue / Scale;
1451 NewFalse = NewFalse / Scale;
1454 /// FindMergedConditions - If Cond is an expression like
1455 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1456 MachineBasicBlock *TBB,
1457 MachineBasicBlock *FBB,
1458 MachineBasicBlock *CurBB,
1459 MachineBasicBlock *SwitchBB,
1460 unsigned Opc, uint32_t TWeight,
1462 // If this node is not part of the or/and tree, emit it as a branch.
1463 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1464 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1465 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1466 BOp->getParent() != CurBB->getBasicBlock() ||
1467 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1468 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1469 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1474 // Create TmpBB after CurBB.
1475 MachineFunction::iterator BBI = CurBB;
1476 MachineFunction &MF = DAG.getMachineFunction();
1477 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1478 CurBB->getParent()->insert(++BBI, TmpBB);
1480 if (Opc == Instruction::Or) {
1481 // Codegen X | Y as:
1490 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1491 // The requirement is that
1492 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1493 // = TrueProb for orignal BB.
1494 // Assuming the orignal weights are A and B, one choice is to set BB1's
1495 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1497 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1498 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1499 // TmpBB, but the math is more complicated.
1501 uint64_t NewTrueWeight = TWeight;
1502 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1503 ScaleWeights(NewTrueWeight, NewFalseWeight);
1504 // Emit the LHS condition.
1505 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1506 NewTrueWeight, NewFalseWeight);
1508 NewTrueWeight = TWeight;
1509 NewFalseWeight = 2 * (uint64_t)FWeight;
1510 ScaleWeights(NewTrueWeight, NewFalseWeight);
1511 // Emit the RHS condition into TmpBB.
1512 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1513 NewTrueWeight, NewFalseWeight);
1515 assert(Opc == Instruction::And && "Unknown merge op!");
1516 // Codegen X & Y as:
1524 // This requires creation of TmpBB after CurBB.
1526 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1527 // The requirement is that
1528 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1529 // = FalseProb for orignal BB.
1530 // Assuming the orignal weights are A and B, one choice is to set BB1's
1531 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1533 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1535 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1536 uint64_t NewFalseWeight = FWeight;
1537 ScaleWeights(NewTrueWeight, NewFalseWeight);
1538 // Emit the LHS condition.
1539 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1540 NewTrueWeight, NewFalseWeight);
1542 NewTrueWeight = 2 * (uint64_t)TWeight;
1543 NewFalseWeight = FWeight;
1544 ScaleWeights(NewTrueWeight, NewFalseWeight);
1545 // Emit the RHS condition into TmpBB.
1546 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1547 NewTrueWeight, NewFalseWeight);
1551 /// If the set of cases should be emitted as a series of branches, return true.
1552 /// If we should emit this as a bunch of and/or'd together conditions, return
1555 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1556 if (Cases.size() != 2) return true;
1558 // If this is two comparisons of the same values or'd or and'd together, they
1559 // will get folded into a single comparison, so don't emit two blocks.
1560 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1561 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1562 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1563 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1567 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1568 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1569 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1570 Cases[0].CC == Cases[1].CC &&
1571 isa<Constant>(Cases[0].CmpRHS) &&
1572 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1573 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1575 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1582 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1583 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1585 // Update machine-CFG edges.
1586 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1588 // Figure out which block is immediately after the current one.
1589 MachineBasicBlock *NextBlock = nullptr;
1590 MachineFunction::iterator BBI = BrMBB;
1591 if (++BBI != FuncInfo.MF->end())
1594 if (I.isUnconditional()) {
1595 // Update machine-CFG edges.
1596 BrMBB->addSuccessor(Succ0MBB);
1598 // If this is not a fall-through branch or optimizations are switched off,
1600 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1601 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1602 MVT::Other, getControlRoot(),
1603 DAG.getBasicBlock(Succ0MBB)));
1608 // If this condition is one of the special cases we handle, do special stuff
1610 const Value *CondVal = I.getCondition();
1611 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1613 // If this is a series of conditions that are or'd or and'd together, emit
1614 // this as a sequence of branches instead of setcc's with and/or operations.
1615 // As long as jumps are not expensive, this should improve performance.
1616 // For example, instead of something like:
1629 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1630 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1631 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1632 BOp->getOpcode() == Instruction::Or)) {
1633 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1634 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1635 getEdgeWeight(BrMBB, Succ1MBB));
1636 // If the compares in later blocks need to use values not currently
1637 // exported from this block, export them now. This block should always
1638 // be the first entry.
1639 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1641 // Allow some cases to be rejected.
1642 if (ShouldEmitAsBranches(SwitchCases)) {
1643 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1644 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1645 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1648 // Emit the branch for this block.
1649 visitSwitchCase(SwitchCases[0], BrMBB);
1650 SwitchCases.erase(SwitchCases.begin());
1654 // Okay, we decided not to do this, remove any inserted MBB's and clear
1656 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1657 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1659 SwitchCases.clear();
1663 // Create a CaseBlock record representing this branch.
1664 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1665 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1667 // Use visitSwitchCase to actually insert the fast branch sequence for this
1669 visitSwitchCase(CB, BrMBB);
1672 /// visitSwitchCase - Emits the necessary code to represent a single node in
1673 /// the binary search tree resulting from lowering a switch instruction.
1674 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1675 MachineBasicBlock *SwitchBB) {
1677 SDValue CondLHS = getValue(CB.CmpLHS);
1678 SDLoc dl = getCurSDLoc();
1680 // Build the setcc now.
1682 // Fold "(X == true)" to X and "(X == false)" to !X to
1683 // handle common cases produced by branch lowering.
1684 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1685 CB.CC == ISD::SETEQ)
1687 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1688 CB.CC == ISD::SETEQ) {
1689 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1690 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1692 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1694 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1696 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1697 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1699 SDValue CmpOp = getValue(CB.CmpMHS);
1700 EVT VT = CmpOp.getValueType();
1702 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1703 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1706 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1707 VT, CmpOp, DAG.getConstant(Low, VT));
1708 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1709 DAG.getConstant(High-Low, VT), ISD::SETULE);
1713 // Update successor info
1714 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1715 // TrueBB and FalseBB are always different unless the incoming IR is
1716 // degenerate. This only happens when running llc on weird IR.
1717 if (CB.TrueBB != CB.FalseBB)
1718 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1720 // Set NextBlock to be the MBB immediately after the current one, if any.
1721 // This is used to avoid emitting unnecessary branches to the next block.
1722 MachineBasicBlock *NextBlock = nullptr;
1723 MachineFunction::iterator BBI = SwitchBB;
1724 if (++BBI != FuncInfo.MF->end())
1727 // If the lhs block is the next block, invert the condition so that we can
1728 // fall through to the lhs instead of the rhs block.
1729 if (CB.TrueBB == NextBlock) {
1730 std::swap(CB.TrueBB, CB.FalseBB);
1731 SDValue True = DAG.getConstant(1, Cond.getValueType());
1732 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1735 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1736 MVT::Other, getControlRoot(), Cond,
1737 DAG.getBasicBlock(CB.TrueBB));
1739 // Insert the false branch. Do this even if it's a fall through branch,
1740 // this makes it easier to do DAG optimizations which require inverting
1741 // the branch condition.
1742 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1743 DAG.getBasicBlock(CB.FalseBB));
1745 DAG.setRoot(BrCond);
1748 /// visitJumpTable - Emit JumpTable node in the current MBB
1749 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1750 // Emit the code for the jump table
1751 assert(JT.Reg != -1U && "Should lower JT Header first!");
1752 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1753 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1755 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1756 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1757 MVT::Other, Index.getValue(1),
1759 DAG.setRoot(BrJumpTable);
1762 /// visitJumpTableHeader - This function emits necessary code to produce index
1763 /// in the JumpTable from switch case.
1764 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1765 JumpTableHeader &JTH,
1766 MachineBasicBlock *SwitchBB) {
1767 // Subtract the lowest switch case value from the value being switched on and
1768 // conditional branch to default mbb if the result is greater than the
1769 // difference between smallest and largest cases.
1770 SDValue SwitchOp = getValue(JTH.SValue);
1771 EVT VT = SwitchOp.getValueType();
1772 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1773 DAG.getConstant(JTH.First, VT));
1775 // The SDNode we just created, which holds the value being switched on minus
1776 // the smallest case value, needs to be copied to a virtual register so it
1777 // can be used as an index into the jump table in a subsequent basic block.
1778 // This value may be smaller or larger than the target's pointer type, and
1779 // therefore require extension or truncating.
1780 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1781 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1783 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1784 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1785 JumpTableReg, SwitchOp);
1786 JT.Reg = JumpTableReg;
1788 // Emit the range check for the jump table, and branch to the default block
1789 // for the switch statement if the value being switched on exceeds the largest
1790 // case in the switch.
1792 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1793 Sub.getValueType()),
1794 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1796 // Set NextBlock to be the MBB immediately after the current one, if any.
1797 // This is used to avoid emitting unnecessary branches to the next block.
1798 MachineBasicBlock *NextBlock = nullptr;
1799 MachineFunction::iterator BBI = SwitchBB;
1801 if (++BBI != FuncInfo.MF->end())
1804 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1805 MVT::Other, CopyTo, CMP,
1806 DAG.getBasicBlock(JT.Default));
1808 if (JT.MBB != NextBlock)
1809 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1810 DAG.getBasicBlock(JT.MBB));
1812 DAG.setRoot(BrCond);
1815 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1816 /// tail spliced into a stack protector check success bb.
1818 /// For a high level explanation of how this fits into the stack protector
1819 /// generation see the comment on the declaration of class
1820 /// StackProtectorDescriptor.
1821 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1822 MachineBasicBlock *ParentBB) {
1824 // First create the loads to the guard/stack slot for the comparison.
1825 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1826 EVT PtrTy = TLI.getPointerTy();
1828 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1829 int FI = MFI->getStackProtectorIndex();
1831 const Value *IRGuard = SPD.getGuard();
1832 SDValue GuardPtr = getValue(IRGuard);
1833 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1836 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1840 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1841 // guard value from the virtual register holding the value. Otherwise, emit a
1842 // volatile load to retrieve the stack guard value.
1843 unsigned GuardReg = SPD.getGuardReg();
1845 if (GuardReg && TLI.useLoadStackGuardNode())
1846 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1849 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1850 GuardPtr, MachinePointerInfo(IRGuard, 0),
1851 true, false, false, Align);
1853 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1855 MachinePointerInfo::getFixedStack(FI),
1856 true, false, false, Align);
1858 // Perform the comparison via a subtract/getsetcc.
1859 EVT VT = Guard.getValueType();
1860 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1863 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1864 Sub.getValueType()),
1865 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1867 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1868 // branch to failure MBB.
1869 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1870 MVT::Other, StackSlot.getOperand(0),
1871 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1872 // Otherwise branch to success MBB.
1873 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1875 DAG.getBasicBlock(SPD.getSuccessMBB()));
1880 /// Codegen the failure basic block for a stack protector check.
1882 /// A failure stack protector machine basic block consists simply of a call to
1883 /// __stack_chk_fail().
1885 /// For a high level explanation of how this fits into the stack protector
1886 /// generation see the comment on the declaration of class
1887 /// StackProtectorDescriptor.
1889 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1890 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1892 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1893 nullptr, 0, false, getCurSDLoc(), false, false).second;
1897 /// visitBitTestHeader - This function emits necessary code to produce value
1898 /// suitable for "bit tests"
1899 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1900 MachineBasicBlock *SwitchBB) {
1901 // Subtract the minimum value
1902 SDValue SwitchOp = getValue(B.SValue);
1903 EVT VT = SwitchOp.getValueType();
1904 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1905 DAG.getConstant(B.First, VT));
1908 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1910 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1911 Sub.getValueType()),
1912 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1914 // Determine the type of the test operands.
1915 bool UsePtrType = false;
1916 if (!TLI.isTypeLegal(VT))
1919 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1920 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1921 // Switch table case range are encoded into series of masks.
1922 // Just use pointer type, it's guaranteed to fit.
1928 VT = TLI.getPointerTy();
1929 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1932 B.RegVT = VT.getSimpleVT();
1933 B.Reg = FuncInfo.CreateReg(B.RegVT);
1934 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1937 // Set NextBlock to be the MBB immediately after the current one, if any.
1938 // This is used to avoid emitting unnecessary branches to the next block.
1939 MachineBasicBlock *NextBlock = nullptr;
1940 MachineFunction::iterator BBI = SwitchBB;
1941 if (++BBI != FuncInfo.MF->end())
1944 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1946 addSuccessorWithWeight(SwitchBB, B.Default);
1947 addSuccessorWithWeight(SwitchBB, MBB);
1949 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1950 MVT::Other, CopyTo, RangeCmp,
1951 DAG.getBasicBlock(B.Default));
1953 if (MBB != NextBlock)
1954 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1955 DAG.getBasicBlock(MBB));
1957 DAG.setRoot(BrRange);
1960 /// visitBitTestCase - this function produces one "bit test"
1961 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1962 MachineBasicBlock* NextMBB,
1963 uint32_t BranchWeightToNext,
1966 MachineBasicBlock *SwitchBB) {
1968 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1971 unsigned PopCount = countPopulation(B.Mask);
1972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1973 if (PopCount == 1) {
1974 // Testing for a single bit; just compare the shift count with what it
1975 // would need to be to shift a 1 bit in that position.
1977 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1978 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1979 } else if (PopCount == BB.Range) {
1980 // There is only one zero bit in the range, test for it directly.
1982 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1983 DAG.getConstant(countTrailingOnes(B.Mask), VT), ISD::SETNE);
1985 // Make desired shift
1986 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1987 DAG.getConstant(1, VT), ShiftOp);
1989 // Emit bit tests and jumps
1990 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1991 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1992 Cmp = DAG.getSetCC(getCurSDLoc(),
1993 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1994 DAG.getConstant(0, VT), ISD::SETNE);
1997 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1998 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1999 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2000 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2002 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
2003 MVT::Other, getControlRoot(),
2004 Cmp, DAG.getBasicBlock(B.TargetBB));
2006 // Set NextBlock to be the MBB immediately after the current one, if any.
2007 // This is used to avoid emitting unnecessary branches to the next block.
2008 MachineBasicBlock *NextBlock = nullptr;
2009 MachineFunction::iterator BBI = SwitchBB;
2010 if (++BBI != FuncInfo.MF->end())
2013 if (NextMBB != NextBlock)
2014 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
2015 DAG.getBasicBlock(NextMBB));
2020 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2021 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2023 // Retrieve successors.
2024 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2025 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2027 const Value *Callee(I.getCalledValue());
2028 const Function *Fn = dyn_cast<Function>(Callee);
2029 if (isa<InlineAsm>(Callee))
2031 else if (Fn && Fn->isIntrinsic()) {
2032 switch (Fn->getIntrinsicID()) {
2034 llvm_unreachable("Cannot invoke this intrinsic");
2035 case Intrinsic::donothing:
2036 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2038 case Intrinsic::experimental_patchpoint_void:
2039 case Intrinsic::experimental_patchpoint_i64:
2040 visitPatchpoint(&I, LandingPad);
2042 case Intrinsic::experimental_gc_statepoint:
2043 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
2047 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2049 // If the value of the invoke is used outside of its defining block, make it
2050 // available as a virtual register.
2051 // We already took care of the exported value for the statepoint instruction
2052 // during call to the LowerStatepoint.
2053 if (!isStatepoint(I)) {
2054 CopyToExportRegsIfNeeded(&I);
2057 // Update successor info
2058 addSuccessorWithWeight(InvokeMBB, Return);
2059 addSuccessorWithWeight(InvokeMBB, LandingPad);
2061 // Drop into normal successor.
2062 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2063 MVT::Other, getControlRoot(),
2064 DAG.getBasicBlock(Return)));
2067 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2068 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2071 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2072 assert(FuncInfo.MBB->isLandingPad() &&
2073 "Call to landingpad not in landing pad!");
2075 MachineBasicBlock *MBB = FuncInfo.MBB;
2076 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2077 AddLandingPadInfo(LP, MMI, MBB);
2079 // If there aren't registers to copy the values into (e.g., during SjLj
2080 // exceptions), then don't bother to create these DAG nodes.
2081 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2082 if (TLI.getExceptionPointerRegister() == 0 &&
2083 TLI.getExceptionSelectorRegister() == 0)
2086 SmallVector<EVT, 2> ValueVTs;
2087 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2088 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2090 // Get the two live-in registers as SDValues. The physregs have already been
2091 // copied into virtual registers.
2093 if (FuncInfo.ExceptionPointerVirtReg) {
2094 Ops[0] = DAG.getZExtOrTrunc(
2095 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2096 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2097 getCurSDLoc(), ValueVTs[0]);
2099 Ops[0] = DAG.getConstant(0, TLI.getPointerTy());
2101 Ops[1] = DAG.getZExtOrTrunc(
2102 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2103 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2104 getCurSDLoc(), ValueVTs[1]);
2107 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2108 DAG.getVTList(ValueVTs), Ops);
2113 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2114 MachineBasicBlock *LPadBB) {
2115 SDValue Chain = getControlRoot();
2117 // Get the typeid that we will dispatch on later.
2118 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2119 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2120 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2121 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2122 SDValue Sel = DAG.getConstant(TypeID, TLI.getPointerTy());
2123 Chain = DAG.getCopyToReg(Chain, getCurSDLoc(), VReg, Sel);
2125 // Branch to the main landing pad block.
2126 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2127 ClauseMBB->addSuccessor(LPadBB);
2128 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain,
2129 DAG.getBasicBlock(LPadBB)));
2133 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2134 /// small case ranges).
2135 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2136 CaseRecVector& WorkList,
2138 MachineBasicBlock *Default,
2139 MachineBasicBlock *SwitchBB) {
2140 // Size is the number of Cases represented by this range.
2141 size_t Size = CR.Range.second - CR.Range.first;
2145 // Get the MachineFunction which holds the current MBB. This is used when
2146 // inserting any additional MBBs necessary to represent the switch.
2147 MachineFunction *CurMF = FuncInfo.MF;
2149 // Figure out which block is immediately after the current one.
2150 MachineBasicBlock *NextBlock = nullptr;
2151 MachineFunction::iterator BBI = CR.CaseBB;
2153 if (++BBI != FuncInfo.MF->end())
2156 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2157 // If any two of the cases has the same destination, and if one value
2158 // is the same as the other, but has one bit unset that the other has set,
2159 // use bit manipulation to do two compares at once. For example:
2160 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2161 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2162 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2163 if (Size == 2 && CR.CaseBB == SwitchBB) {
2164 Case &Small = *CR.Range.first;
2165 Case &Big = *(CR.Range.second-1);
2167 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2168 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2169 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2171 // Check that there is only one bit different.
2172 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2173 (SmallValue | BigValue) == BigValue) {
2174 // Isolate the common bit.
2175 APInt CommonBit = BigValue & ~SmallValue;
2176 assert((SmallValue | CommonBit) == BigValue &&
2177 CommonBit.countPopulation() == 1 && "Not a common bit?");
2179 SDValue CondLHS = getValue(SV);
2180 EVT VT = CondLHS.getValueType();
2181 SDLoc DL = getCurSDLoc();
2183 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2184 DAG.getConstant(CommonBit, VT));
2185 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2186 Or, DAG.getConstant(BigValue, VT),
2189 // Update successor info.
2190 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2191 addSuccessorWithWeight(SwitchBB, Small.BB,
2192 Small.ExtraWeight + Big.ExtraWeight);
2193 addSuccessorWithWeight(SwitchBB, Default,
2194 // The default destination is the first successor in IR.
2195 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2197 // Insert the true branch.
2198 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2199 getControlRoot(), Cond,
2200 DAG.getBasicBlock(Small.BB));
2202 // Insert the false branch.
2203 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2204 DAG.getBasicBlock(Default));
2206 DAG.setRoot(BrCond);
2212 // Order cases by weight so the most likely case will be checked first.
2213 uint32_t UnhandledWeights = 0;
2215 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2216 uint32_t IWeight = I->ExtraWeight;
2217 UnhandledWeights += IWeight;
2218 for (CaseItr J = CR.Range.first; J < I; ++J) {
2219 uint32_t JWeight = J->ExtraWeight;
2220 if (IWeight > JWeight)
2225 // Rearrange the case blocks so that the last one falls through if possible.
2226 Case &BackCase = *(CR.Range.second-1);
2228 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2229 // The last case block won't fall through into 'NextBlock' if we emit the
2230 // branches in this order. See if rearranging a case value would help.
2231 // We start at the bottom as it's the case with the least weight.
2232 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2233 if (I->BB == NextBlock) {
2234 std::swap(*I, BackCase);
2239 // Create a CaseBlock record representing a conditional branch to
2240 // the Case's target mbb if the value being switched on SV is equal
2242 MachineBasicBlock *CurBlock = CR.CaseBB;
2243 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2244 MachineBasicBlock *FallThrough;
2246 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2247 CurMF->insert(BBI, FallThrough);
2249 // Put SV in a virtual register to make it available from the new blocks.
2250 ExportFromCurrentBlock(SV);
2252 // If the last case doesn't match, go to the default block.
2253 FallThrough = Default;
2256 const Value *RHS, *LHS, *MHS;
2258 if (I->High == I->Low) {
2259 // This is just small small case range :) containing exactly 1 case
2261 LHS = SV; RHS = I->High; MHS = nullptr;
2264 LHS = I->Low; MHS = SV; RHS = I->High;
2267 // The false weight should be sum of all un-handled cases.
2268 UnhandledWeights -= I->ExtraWeight;
2269 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2271 /* trueweight */ I->ExtraWeight,
2272 /* falseweight */ UnhandledWeights);
2274 // If emitting the first comparison, just call visitSwitchCase to emit the
2275 // code into the current block. Otherwise, push the CaseBlock onto the
2276 // vector to be later processed by SDISel, and insert the node's MBB
2277 // before the next MBB.
2278 if (CurBlock == SwitchBB)
2279 visitSwitchCase(CB, SwitchBB);
2281 SwitchCases.push_back(CB);
2283 CurBlock = FallThrough;
2289 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2290 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2291 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2294 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2295 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2296 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2297 return (LastExt - FirstExt + 1ULL);
2300 /// handleJTSwitchCase - Emit jumptable for current switch case range
2301 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2302 CaseRecVector &WorkList,
2304 MachineBasicBlock *Default,
2305 MachineBasicBlock *SwitchBB) {
2306 Case& FrontCase = *CR.Range.first;
2307 Case& BackCase = *(CR.Range.second-1);
2309 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2310 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2312 APInt TSize(First.getBitWidth(), 0);
2313 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2316 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2317 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2320 APInt Range = ComputeRange(First, Last);
2321 // The density is TSize / Range. Require at least 40%.
2322 // It should not be possible for IntTSize to saturate for sane code, but make
2323 // sure we handle Range saturation correctly.
2324 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2325 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2326 if (IntTSize * 10 < IntRange * 4)
2329 DEBUG(dbgs() << "Lowering jump table\n"
2330 << "First entry: " << First << ". Last entry: " << Last << '\n'
2331 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2333 // Get the MachineFunction which holds the current MBB. This is used when
2334 // inserting any additional MBBs necessary to represent the switch.
2335 MachineFunction *CurMF = FuncInfo.MF;
2337 // Figure out which block is immediately after the current one.
2338 MachineFunction::iterator BBI = CR.CaseBB;
2341 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2343 // Create a new basic block to hold the code for loading the address
2344 // of the jump table, and jumping to it. Update successor information;
2345 // we will either branch to the default case for the switch, or the jump
2347 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2348 CurMF->insert(BBI, JumpTableBB);
2350 addSuccessorWithWeight(CR.CaseBB, Default);
2351 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2353 // Build a vector of destination BBs, corresponding to each target
2354 // of the jump table. If the value of the jump table slot corresponds to
2355 // a case statement, push the case's BB onto the vector, otherwise, push
2357 std::vector<MachineBasicBlock*> DestBBs;
2359 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2360 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2361 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2363 if (Low.sle(TEI) && TEI.sle(High)) {
2364 DestBBs.push_back(I->BB);
2368 DestBBs.push_back(Default);
2372 // Calculate weight for each unique destination in CR.
2373 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2375 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2376 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2377 DestWeights.find(I->BB);
2378 if (Itr != DestWeights.end())
2379 Itr->second += I->ExtraWeight;
2381 DestWeights[I->BB] = I->ExtraWeight;
2384 // Update successor info. Add one edge to each unique successor.
2385 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2386 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2387 E = DestBBs.end(); I != E; ++I) {
2388 if (!SuccsHandled[(*I)->getNumber()]) {
2389 SuccsHandled[(*I)->getNumber()] = true;
2390 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2391 DestWeights.find(*I);
2392 addSuccessorWithWeight(JumpTableBB, *I,
2393 Itr != DestWeights.end() ? Itr->second : 0);
2397 // Create a jump table index for this jump table.
2398 unsigned JTEncoding = TLI.getJumpTableEncoding();
2399 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2400 ->createJumpTableIndex(DestBBs);
2402 // Set the jump table information so that we can codegen it as a second
2403 // MachineBasicBlock
2404 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2405 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2406 if (CR.CaseBB == SwitchBB)
2407 visitJumpTableHeader(JT, JTH, SwitchBB);
2409 JTCases.push_back(JumpTableBlock(JTH, JT));
2413 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2415 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2416 CaseRecVector& WorkList,
2418 MachineBasicBlock* SwitchBB) {
2419 Case& FrontCase = *CR.Range.first;
2420 Case& BackCase = *(CR.Range.second-1);
2422 // Size is the number of Cases represented by this range.
2423 unsigned Size = CR.Range.second - CR.Range.first;
2425 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2426 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2428 CaseItr Pivot = CR.Range.first + Size/2;
2430 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2431 // (heuristically) allow us to emit JumpTable's later.
2432 APInt TSize(First.getBitWidth(), 0);
2433 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2437 APInt LSize = FrontCase.size();
2438 APInt RSize = TSize-LSize;
2439 DEBUG(dbgs() << "Selecting best pivot: \n"
2440 << "First: " << First << ", Last: " << Last <<'\n'
2441 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2443 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2445 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2446 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2447 APInt Range = ComputeRange(LEnd, RBegin);
2448 assert((Range - 2ULL).isNonNegative() &&
2449 "Invalid case distance");
2450 // Use volatile double here to avoid excess precision issues on some hosts,
2451 // e.g. that use 80-bit X87 registers.
2452 // Only consider the density of sub-ranges that actually have sufficient
2453 // entries to be lowered as a jump table.
2454 volatile double LDensity =
2455 LSize.ult(TLI.getMinimumJumpTableEntries())
2457 : LSize.roundToDouble() / (LEnd - First + 1ULL).roundToDouble();
2458 volatile double RDensity =
2459 RSize.ult(TLI.getMinimumJumpTableEntries())
2461 : RSize.roundToDouble() / (Last - RBegin + 1ULL).roundToDouble();
2462 volatile double Metric = Range.logBase2() * (LDensity + RDensity);
2463 // Should always split in some non-trivial place
2464 DEBUG(dbgs() <<"=>Step\n"
2465 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2466 << "LDensity: " << LDensity
2467 << ", RDensity: " << RDensity << '\n'
2468 << "Metric: " << Metric << '\n');
2469 if (FMetric < Metric) {
2472 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2479 if (FMetric == 0 || !areJTsAllowed(TLI))
2480 Pivot = CR.Range.first + Size/2;
2481 splitSwitchCase(CR, Pivot, WorkList, SV, SwitchBB);
2485 void SelectionDAGBuilder::splitSwitchCase(CaseRec &CR, CaseItr Pivot,
2486 CaseRecVector &WorkList,
2488 MachineBasicBlock *SwitchBB) {
2489 // Get the MachineFunction which holds the current MBB. This is used when
2490 // inserting any additional MBBs necessary to represent the switch.
2491 MachineFunction *CurMF = FuncInfo.MF;
2493 // Figure out which block is immediately after the current one.
2494 MachineFunction::iterator BBI = CR.CaseBB;
2497 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2499 CaseRange LHSR(CR.Range.first, Pivot);
2500 CaseRange RHSR(Pivot, CR.Range.second);
2501 const Constant *C = Pivot->Low;
2502 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2504 // We know that we branch to the LHS if the Value being switched on is
2505 // less than the Pivot value, C. We use this to optimize our binary
2506 // tree a bit, by recognizing that if SV is greater than or equal to the
2507 // LHS's Case Value, and that Case Value is exactly one less than the
2508 // Pivot's Value, then we can branch directly to the LHS's Target,
2509 // rather than creating a leaf node for it.
2510 if ((LHSR.second - LHSR.first) == 1 && LHSR.first->High == CR.GE &&
2511 cast<ConstantInt>(C)->getValue() ==
2512 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2513 TrueBB = LHSR.first->BB;
2515 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2516 CurMF->insert(BBI, TrueBB);
2517 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2519 // Put SV in a virtual register to make it available from the new blocks.
2520 ExportFromCurrentBlock(SV);
2523 // Similar to the optimization above, if the Value being switched on is
2524 // known to be less than the Constant CR.LT, and the current Case Value
2525 // is CR.LT - 1, then we can branch directly to the target block for
2526 // the current Case Value, rather than emitting a RHS leaf node for it.
2527 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2528 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2529 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2530 FalseBB = RHSR.first->BB;
2532 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2533 CurMF->insert(BBI, FalseBB);
2534 WorkList.push_back(CaseRec(FalseBB, CR.LT, C, RHSR));
2536 // Put SV in a virtual register to make it available from the new blocks.
2537 ExportFromCurrentBlock(SV);
2540 // Create a CaseBlock record representing a conditional branch to
2541 // the LHS node if the value being switched on SV is less than C.
2542 // Otherwise, branch to LHS.
2543 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2545 if (CR.CaseBB == SwitchBB)
2546 visitSwitchCase(CB, SwitchBB);
2548 SwitchCases.push_back(CB);
2551 /// handleBitTestsSwitchCase - if current case range has few destination and
2552 /// range span less, than machine word bitwidth, encode case range into series
2553 /// of masks and emit bit tests with these masks.
2554 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2555 CaseRecVector& WorkList,
2557 MachineBasicBlock* Default,
2558 MachineBasicBlock* SwitchBB) {
2559 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2560 EVT PTy = TLI.getPointerTy();
2561 unsigned IntPtrBits = PTy.getSizeInBits();
2563 Case& FrontCase = *CR.Range.first;
2564 Case& BackCase = *(CR.Range.second-1);
2566 // Get the MachineFunction which holds the current MBB. This is used when
2567 // inserting any additional MBBs necessary to represent the switch.
2568 MachineFunction *CurMF = FuncInfo.MF;
2570 // If target does not have legal shift left, do not emit bit tests at all.
2571 if (!TLI.isOperationLegal(ISD::SHL, PTy))
2575 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2576 // Single case counts one, case range - two.
2577 numCmps += (I->Low == I->High ? 1 : 2);
2580 // Count unique destinations
2581 SmallSet<MachineBasicBlock*, 4> Dests;
2582 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2583 Dests.insert(I->BB);
2584 if (Dests.size() > 3)
2585 // Don't bother the code below, if there are too much unique destinations
2588 DEBUG(dbgs() << "Total number of unique destinations: "
2589 << Dests.size() << '\n'
2590 << "Total number of comparisons: " << numCmps << '\n');
2592 // Compute span of values.
2593 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2594 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2595 APInt cmpRange = maxValue - minValue;
2597 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2598 << "Low bound: " << minValue << '\n'
2599 << "High bound: " << maxValue << '\n');
2601 if (cmpRange.uge(IntPtrBits) ||
2602 (!(Dests.size() == 1 && numCmps >= 3) &&
2603 !(Dests.size() == 2 && numCmps >= 5) &&
2604 !(Dests.size() >= 3 && numCmps >= 6)))
2607 DEBUG(dbgs() << "Emitting bit tests\n");
2608 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2610 // Optimize the case where all the case values fit in a
2611 // word without having to subtract minValue. In this case,
2612 // we can optimize away the subtraction.
2613 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2614 cmpRange = maxValue;
2616 lowBound = minValue;
2619 CaseBitsVector CasesBits;
2620 unsigned i, count = 0;
2622 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2623 MachineBasicBlock* Dest = I->BB;
2624 for (i = 0; i < count; ++i)
2625 if (Dest == CasesBits[i].BB)
2629 assert((count < 3) && "Too much destinations to test!");
2630 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2634 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2635 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2637 uint64_t lo = (lowValue - lowBound).getZExtValue();
2638 uint64_t hi = (highValue - lowBound).getZExtValue();
2639 CasesBits[i].ExtraWeight += I->ExtraWeight;
2641 for (uint64_t j = lo; j <= hi; j++) {
2642 CasesBits[i].Mask |= 1ULL << j;
2643 CasesBits[i].Bits++;
2647 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2651 // Figure out which block is immediately after the current one.
2652 MachineFunction::iterator BBI = CR.CaseBB;
2655 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2657 DEBUG(dbgs() << "Cases:\n");
2658 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2659 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2660 << ", Bits: " << CasesBits[i].Bits
2661 << ", BB: " << CasesBits[i].BB << '\n');
2663 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2664 CurMF->insert(BBI, CaseBB);
2665 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2667 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2669 // Put SV in a virtual register to make it available from the new blocks.
2670 ExportFromCurrentBlock(SV);
2673 BitTestBlock BTB(lowBound, cmpRange, SV,
2674 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2675 CR.CaseBB, Default, std::move(BTC));
2677 if (CR.CaseBB == SwitchBB)
2678 visitBitTestHeader(BTB, SwitchBB);
2680 BitTestCases.push_back(std::move(BTB));
2685 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2686 void SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2687 const SwitchInst& SI) {
2688 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2689 // Start with "simple" cases.
2690 for (SwitchInst::ConstCaseIt i : SI.cases()) {
2691 const BasicBlock *SuccBB = i.getCaseSuccessor();
2692 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2694 uint32_t ExtraWeight =
2695 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2697 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2698 SMBB, ExtraWeight));
2700 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2702 // Merge case into clusters
2703 if (Cases.size() >= 2)
2704 // Must recompute end() each iteration because it may be
2705 // invalidated by erase if we hold on to it
2706 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2707 J != Cases.end(); ) {
2708 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2709 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2710 MachineBasicBlock* nextBB = J->BB;
2711 MachineBasicBlock* currentBB = I->BB;
2713 // If the two neighboring cases go to the same destination, merge them
2714 // into a single case.
2715 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2717 I->ExtraWeight += J->ExtraWeight;
2726 for (auto &I : Cases)
2727 // A range counts double, since it requires two compares.
2728 numCmps += I.Low != I.High ? 2 : 1;
2730 dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2731 << ". Total compares: " << numCmps << '\n';
2735 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2736 MachineBasicBlock *Last) {
2738 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2739 if (JTCases[i].first.HeaderBB == First)
2740 JTCases[i].first.HeaderBB = Last;
2742 // Update BitTestCases.
2743 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2744 if (BitTestCases[i].Parent == First)
2745 BitTestCases[i].Parent = Last;
2748 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2749 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2751 // Figure out which block is immediately after the current one.
2752 MachineBasicBlock *NextBlock = nullptr;
2753 if (SwitchMBB + 1 != FuncInfo.MF->end())
2754 NextBlock = SwitchMBB + 1;
2757 // Create a vector of Cases, sorted so that we can efficiently create a binary
2758 // search tree from them.
2760 Clusterify(Cases, SI);
2762 // Get the default destination MBB.
2763 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2765 if (isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg()) &&
2767 // Replace an unreachable default destination with the most popular case
2769 DenseMap<const BasicBlock *, unsigned> Popularity;
2770 unsigned MaxPop = 0;
2771 const BasicBlock *MaxBB = nullptr;
2772 for (auto I : SI.cases()) {
2773 const BasicBlock *BB = I.getCaseSuccessor();
2774 if (++Popularity[BB] > MaxPop) {
2775 MaxPop = Popularity[BB];
2783 Default = FuncInfo.MBBMap[MaxBB];
2785 // Remove cases that were pointing to the destination that is now the default.
2786 Cases.erase(std::remove_if(Cases.begin(), Cases.end(),
2787 [&](const Case &C) { return C.BB == Default; }),
2791 // If there is only the default destination, go there directly.
2792 if (Cases.empty()) {
2793 // Update machine-CFG edges.
2794 SwitchMBB->addSuccessor(Default);
2796 // If this is not a fall-through branch, emit the branch.
2797 if (Default != NextBlock) {
2798 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2799 getControlRoot(), DAG.getBasicBlock(Default)));
2804 // Get the Value to be switched on.
2805 const Value *SV = SI.getCondition();
2807 // Push the initial CaseRec onto the worklist
2808 CaseRecVector WorkList;
2809 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2810 CaseRange(Cases.begin(),Cases.end())));
2812 while (!WorkList.empty()) {
2813 // Grab a record representing a case range to process off the worklist
2814 CaseRec CR = WorkList.back();
2815 WorkList.pop_back();
2817 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2820 // If the range has few cases (two or less) emit a series of specific
2822 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2825 // If the switch has more than N blocks, and is at least 40% dense, and the
2826 // target supports indirect branches, then emit a jump table rather than
2827 // lowering the switch to a binary tree of conditional branches.
2828 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2829 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2832 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2833 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2834 handleBTSplitSwitchCase(CR, WorkList, SV, SwitchMBB);
2838 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2839 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2841 // Update machine-CFG edges with unique successors.
2842 SmallSet<BasicBlock*, 32> Done;
2843 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2844 BasicBlock *BB = I.getSuccessor(i);
2845 bool Inserted = Done.insert(BB).second;
2849 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2850 addSuccessorWithWeight(IndirectBrMBB, Succ);
2853 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2854 MVT::Other, getControlRoot(),
2855 getValue(I.getAddress())));
2858 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2859 if (DAG.getTarget().Options.TrapUnreachable)
2860 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2863 void SelectionDAGBuilder::visitFSub(const User &I) {
2864 // -0.0 - X --> fneg
2865 Type *Ty = I.getType();
2866 if (isa<Constant>(I.getOperand(0)) &&
2867 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2868 SDValue Op2 = getValue(I.getOperand(1));
2869 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2870 Op2.getValueType(), Op2));
2874 visitBinary(I, ISD::FSUB);
2877 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2878 SDValue Op1 = getValue(I.getOperand(0));
2879 SDValue Op2 = getValue(I.getOperand(1));
2884 if (const OverflowingBinaryOperator *OFBinOp =
2885 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2886 nuw = OFBinOp->hasNoUnsignedWrap();
2887 nsw = OFBinOp->hasNoSignedWrap();
2889 if (const PossiblyExactOperator *ExactOp =
2890 dyn_cast<const PossiblyExactOperator>(&I))
2891 exact = ExactOp->isExact();
2893 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2894 Op1, Op2, nuw, nsw, exact);
2895 setValue(&I, BinNodeValue);
2898 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2899 SDValue Op1 = getValue(I.getOperand(0));
2900 SDValue Op2 = getValue(I.getOperand(1));
2903 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2905 // Coerce the shift amount to the right type if we can.
2906 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2907 unsigned ShiftSize = ShiftTy.getSizeInBits();
2908 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2909 SDLoc DL = getCurSDLoc();
2911 // If the operand is smaller than the shift count type, promote it.
2912 if (ShiftSize > Op2Size)
2913 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2915 // If the operand is larger than the shift count type but the shift
2916 // count type has enough bits to represent any shift value, truncate
2917 // it now. This is a common case and it exposes the truncate to
2918 // optimization early.
2919 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2920 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2921 // Otherwise we'll need to temporarily settle for some other convenient
2922 // type. Type legalization will make adjustments once the shiftee is split.
2924 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2931 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2933 if (const OverflowingBinaryOperator *OFBinOp =
2934 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2935 nuw = OFBinOp->hasNoUnsignedWrap();
2936 nsw = OFBinOp->hasNoSignedWrap();
2938 if (const PossiblyExactOperator *ExactOp =
2939 dyn_cast<const PossiblyExactOperator>(&I))
2940 exact = ExactOp->isExact();
2943 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2948 void SelectionDAGBuilder::visitSDiv(const User &I) {
2949 SDValue Op1 = getValue(I.getOperand(0));
2950 SDValue Op2 = getValue(I.getOperand(1));
2952 // Turn exact SDivs into multiplications.
2953 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2955 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2956 !isa<ConstantSDNode>(Op1) &&
2957 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2958 setValue(&I, DAG.getTargetLoweringInfo()
2959 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2961 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2965 void SelectionDAGBuilder::visitICmp(const User &I) {
2966 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2967 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2968 predicate = IC->getPredicate();
2969 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2970 predicate = ICmpInst::Predicate(IC->getPredicate());
2971 SDValue Op1 = getValue(I.getOperand(0));
2972 SDValue Op2 = getValue(I.getOperand(1));
2973 ISD::CondCode Opcode = getICmpCondCode(predicate);
2975 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2976 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2979 void SelectionDAGBuilder::visitFCmp(const User &I) {
2980 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2981 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2982 predicate = FC->getPredicate();
2983 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2984 predicate = FCmpInst::Predicate(FC->getPredicate());
2985 SDValue Op1 = getValue(I.getOperand(0));
2986 SDValue Op2 = getValue(I.getOperand(1));
2987 ISD::CondCode Condition = getFCmpCondCode(predicate);
2988 if (TM.Options.NoNaNsFPMath)
2989 Condition = getFCmpCodeWithoutNaN(Condition);
2990 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2991 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2994 void SelectionDAGBuilder::visitSelect(const User &I) {
2995 SmallVector<EVT, 4> ValueVTs;
2996 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2997 unsigned NumValues = ValueVTs.size();
2998 if (NumValues == 0) return;
3000 SmallVector<SDValue, 4> Values(NumValues);
3001 SDValue Cond = getValue(I.getOperand(0));
3002 SDValue TrueVal = getValue(I.getOperand(1));
3003 SDValue FalseVal = getValue(I.getOperand(2));
3004 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
3005 ISD::VSELECT : ISD::SELECT;
3007 for (unsigned i = 0; i != NumValues; ++i)
3008 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
3009 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
3011 SDValue(TrueVal.getNode(),
3012 TrueVal.getResNo() + i),
3013 SDValue(FalseVal.getNode(),
3014 FalseVal.getResNo() + i));
3016 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3017 DAG.getVTList(ValueVTs), Values));
3020 void SelectionDAGBuilder::visitTrunc(const User &I) {
3021 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
3022 SDValue N = getValue(I.getOperand(0));
3023 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3024 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3027 void SelectionDAGBuilder::visitZExt(const User &I) {
3028 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3029 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
3030 SDValue N = getValue(I.getOperand(0));
3031 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3032 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
3035 void SelectionDAGBuilder::visitSExt(const User &I) {
3036 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3037 // SExt also can't be a cast to bool for same reason. So, nothing much to do
3038 SDValue N = getValue(I.getOperand(0));
3039 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3040 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
3043 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
3044 // FPTrunc is never a no-op cast, no need to check
3045 SDValue N = getValue(I.getOperand(0));
3046 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3047 EVT DestVT = TLI.getValueType(I.getType());
3048 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
3049 DAG.getTargetConstant(0, TLI.getPointerTy())));
3052 void SelectionDAGBuilder::visitFPExt(const User &I) {
3053 // FPExt is never a no-op cast, no need to check
3054 SDValue N = getValue(I.getOperand(0));
3055 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3056 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3059 void SelectionDAGBuilder::visitFPToUI(const User &I) {
3060 // FPToUI is never a no-op cast, no need to check
3061 SDValue N = getValue(I.getOperand(0));
3062 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3063 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3066 void SelectionDAGBuilder::visitFPToSI(const User &I) {
3067 // FPToSI is never a no-op cast, no need to check
3068 SDValue N = getValue(I.getOperand(0));
3069 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3070 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3073 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3074 // UIToFP is never a no-op cast, no need to check
3075 SDValue N = getValue(I.getOperand(0));
3076 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3077 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3080 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3081 // SIToFP is never a no-op cast, no need to check
3082 SDValue N = getValue(I.getOperand(0));
3083 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3084 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3087 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3088 // What to do depends on the size of the integer and the size of the pointer.
3089 // We can either truncate, zero extend, or no-op, accordingly.
3090 SDValue N = getValue(I.getOperand(0));
3091 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3092 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3095 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3096 // What to do depends on the size of the integer and the size of the pointer.
3097 // We can either truncate, zero extend, or no-op, accordingly.
3098 SDValue N = getValue(I.getOperand(0));
3099 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3100 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3103 void SelectionDAGBuilder::visitBitCast(const User &I) {
3104 SDValue N = getValue(I.getOperand(0));
3105 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3107 // BitCast assures us that source and destination are the same size so this is
3108 // either a BITCAST or a no-op.
3109 if (DestVT != N.getValueType())
3110 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3111 DestVT, N)); // convert types.
3112 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3113 // might fold any kind of constant expression to an integer constant and that
3114 // is not what we are looking for. Only regcognize a bitcast of a genuine
3115 // constant integer as an opaque constant.
3116 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3117 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3120 setValue(&I, N); // noop cast.
3123 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3124 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3125 const Value *SV = I.getOperand(0);
3126 SDValue N = getValue(SV);
3127 EVT DestVT = TLI.getValueType(I.getType());
3129 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3130 unsigned DestAS = I.getType()->getPointerAddressSpace();
3132 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3133 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3138 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3139 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3140 SDValue InVec = getValue(I.getOperand(0));
3141 SDValue InVal = getValue(I.getOperand(1));
3142 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3143 getCurSDLoc(), TLI.getVectorIdxTy());
3144 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3145 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
3148 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3149 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3150 SDValue InVec = getValue(I.getOperand(0));
3151 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3152 getCurSDLoc(), TLI.getVectorIdxTy());
3153 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3154 TLI.getValueType(I.getType()), InVec, InIdx));
3157 // Utility for visitShuffleVector - Return true if every element in Mask,
3158 // beginning from position Pos and ending in Pos+Size, falls within the
3159 // specified sequential range [L, L+Pos). or is undef.
3160 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3161 unsigned Pos, unsigned Size, int Low) {
3162 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3163 if (Mask[i] >= 0 && Mask[i] != Low)
3168 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3169 SDValue Src1 = getValue(I.getOperand(0));
3170 SDValue Src2 = getValue(I.getOperand(1));
3172 SmallVector<int, 8> Mask;
3173 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3174 unsigned MaskNumElts = Mask.size();
3176 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3177 EVT VT = TLI.getValueType(I.getType());
3178 EVT SrcVT = Src1.getValueType();
3179 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3181 if (SrcNumElts == MaskNumElts) {
3182 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3187 // Normalize the shuffle vector since mask and vector length don't match.
3188 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3189 // Mask is longer than the source vectors and is a multiple of the source
3190 // vectors. We can use concatenate vector to make the mask and vectors
3192 if (SrcNumElts*2 == MaskNumElts) {
3193 // First check for Src1 in low and Src2 in high
3194 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3195 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3196 // The shuffle is concatenating two vectors together.
3197 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3201 // Then check for Src2 in low and Src1 in high
3202 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3203 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3204 // The shuffle is concatenating two vectors together.
3205 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3211 // Pad both vectors with undefs to make them the same length as the mask.
3212 unsigned NumConcat = MaskNumElts / SrcNumElts;
3213 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3214 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3215 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3217 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3218 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3222 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3223 getCurSDLoc(), VT, MOps1);
3224 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3225 getCurSDLoc(), VT, MOps2);
3227 // Readjust mask for new input vector length.
3228 SmallVector<int, 8> MappedOps;
3229 for (unsigned i = 0; i != MaskNumElts; ++i) {
3231 if (Idx >= (int)SrcNumElts)
3232 Idx -= SrcNumElts - MaskNumElts;
3233 MappedOps.push_back(Idx);
3236 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3241 if (SrcNumElts > MaskNumElts) {
3242 // Analyze the access pattern of the vector to see if we can extract
3243 // two subvectors and do the shuffle. The analysis is done by calculating
3244 // the range of elements the mask access on both vectors.
3245 int MinRange[2] = { static_cast<int>(SrcNumElts),
3246 static_cast<int>(SrcNumElts)};
3247 int MaxRange[2] = {-1, -1};
3249 for (unsigned i = 0; i != MaskNumElts; ++i) {
3255 if (Idx >= (int)SrcNumElts) {
3259 if (Idx > MaxRange[Input])
3260 MaxRange[Input] = Idx;
3261 if (Idx < MinRange[Input])
3262 MinRange[Input] = Idx;
3265 // Check if the access is smaller than the vector size and can we find
3266 // a reasonable extract index.
3267 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3269 int StartIdx[2]; // StartIdx to extract from
3270 for (unsigned Input = 0; Input < 2; ++Input) {
3271 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3272 RangeUse[Input] = 0; // Unused
3273 StartIdx[Input] = 0;
3277 // Find a good start index that is a multiple of the mask length. Then
3278 // see if the rest of the elements are in range.
3279 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3280 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3281 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3282 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3285 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3286 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3289 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3290 // Extract appropriate subvector and generate a vector shuffle
3291 for (unsigned Input = 0; Input < 2; ++Input) {
3292 SDValue &Src = Input == 0 ? Src1 : Src2;
3293 if (RangeUse[Input] == 0)
3294 Src = DAG.getUNDEF(VT);
3297 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
3298 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
3301 // Calculate new mask.
3302 SmallVector<int, 8> MappedOps;
3303 for (unsigned i = 0; i != MaskNumElts; ++i) {
3306 if (Idx < (int)SrcNumElts)
3309 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3311 MappedOps.push_back(Idx);
3314 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3320 // We can't use either concat vectors or extract subvectors so fall back to
3321 // replacing the shuffle with extract and build vector.
3322 // to insert and build vector.
3323 EVT EltVT = VT.getVectorElementType();
3324 EVT IdxVT = TLI.getVectorIdxTy();
3325 SmallVector<SDValue,8> Ops;
3326 for (unsigned i = 0; i != MaskNumElts; ++i) {
3331 Res = DAG.getUNDEF(EltVT);
3333 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3334 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3336 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3337 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3343 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3346 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3347 const Value *Op0 = I.getOperand(0);
3348 const Value *Op1 = I.getOperand(1);
3349 Type *AggTy = I.getType();
3350 Type *ValTy = Op1->getType();
3351 bool IntoUndef = isa<UndefValue>(Op0);
3352 bool FromUndef = isa<UndefValue>(Op1);
3354 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3356 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3357 SmallVector<EVT, 4> AggValueVTs;
3358 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3359 SmallVector<EVT, 4> ValValueVTs;
3360 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3362 unsigned NumAggValues = AggValueVTs.size();
3363 unsigned NumValValues = ValValueVTs.size();
3364 SmallVector<SDValue, 4> Values(NumAggValues);
3366 // Ignore an insertvalue that produces an empty object
3367 if (!NumAggValues) {
3368 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3372 SDValue Agg = getValue(Op0);
3374 // Copy the beginning value(s) from the original aggregate.
3375 for (; i != LinearIndex; ++i)
3376 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3377 SDValue(Agg.getNode(), Agg.getResNo() + i);
3378 // Copy values from the inserted value(s).
3380 SDValue Val = getValue(Op1);
3381 for (; i != LinearIndex + NumValValues; ++i)
3382 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3383 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3385 // Copy remaining value(s) from the original aggregate.
3386 for (; i != NumAggValues; ++i)
3387 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3388 SDValue(Agg.getNode(), Agg.getResNo() + i);
3390 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3391 DAG.getVTList(AggValueVTs), Values));
3394 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3395 const Value *Op0 = I.getOperand(0);
3396 Type *AggTy = Op0->getType();
3397 Type *ValTy = I.getType();
3398 bool OutOfUndef = isa<UndefValue>(Op0);
3400 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3402 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3403 SmallVector<EVT, 4> ValValueVTs;
3404 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3406 unsigned NumValValues = ValValueVTs.size();
3408 // Ignore a extractvalue that produces an empty object
3409 if (!NumValValues) {
3410 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3414 SmallVector<SDValue, 4> Values(NumValValues);
3416 SDValue Agg = getValue(Op0);
3417 // Copy out the selected value(s).
3418 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3419 Values[i - LinearIndex] =
3421 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3422 SDValue(Agg.getNode(), Agg.getResNo() + i);
3424 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3425 DAG.getVTList(ValValueVTs), Values));
3428 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3429 Value *Op0 = I.getOperand(0);
3430 // Note that the pointer operand may be a vector of pointers. Take the scalar
3431 // element which holds a pointer.
3432 Type *Ty = Op0->getType()->getScalarType();
3433 unsigned AS = Ty->getPointerAddressSpace();
3434 SDValue N = getValue(Op0);
3436 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3438 const Value *Idx = *OI;
3439 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3440 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3443 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3444 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3445 DAG.getConstant(Offset, N.getValueType()));
3448 Ty = StTy->getElementType(Field);
3450 Ty = cast<SequentialType>(Ty)->getElementType();
3452 // If this is a constant subscript, handle it quickly.
3453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3454 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3455 if (CI->isZero()) continue;
3457 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3459 EVT PTy = TLI.getPointerTy(AS);
3460 unsigned PtrBits = PTy.getSizeInBits();
3462 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3463 DAG.getConstant(Offs, MVT::i64));
3465 OffsVal = DAG.getConstant(Offs, PTy);
3467 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3472 // N = N + Idx * ElementSize;
3474 APInt(TLI.getPointerSizeInBits(AS), DL->getTypeAllocSize(Ty));
3475 SDValue IdxN = getValue(Idx);
3477 // If the index is smaller or larger than intptr_t, truncate or extend
3479 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3481 // If this is a multiply by a power of two, turn it into a shl
3482 // immediately. This is a very common case.
3483 if (ElementSize != 1) {
3484 if (ElementSize.isPowerOf2()) {
3485 unsigned Amt = ElementSize.logBase2();
3486 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3487 N.getValueType(), IdxN,
3488 DAG.getConstant(Amt, IdxN.getValueType()));
3490 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3491 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3492 N.getValueType(), IdxN, Scale);
3496 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3497 N.getValueType(), N, IdxN);
3504 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3505 // If this is a fixed sized alloca in the entry block of the function,
3506 // allocate it statically on the stack.
3507 if (FuncInfo.StaticAllocaMap.count(&I))
3508 return; // getValue will auto-populate this.
3510 Type *Ty = I.getAllocatedType();
3511 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3512 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3514 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3517 SDValue AllocSize = getValue(I.getArraySize());
3519 EVT IntPtr = TLI.getPointerTy();
3520 if (AllocSize.getValueType() != IntPtr)
3521 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3523 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3525 DAG.getConstant(TySize, IntPtr));
3527 // Handle alignment. If the requested alignment is less than or equal to
3528 // the stack alignment, ignore it. If the size is greater than or equal to
3529 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3530 unsigned StackAlign =
3531 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3532 if (Align <= StackAlign)
3535 // Round the size of the allocation up to the stack alignment size
3536 // by add SA-1 to the size.
3537 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3538 AllocSize.getValueType(), AllocSize,
3539 DAG.getIntPtrConstant(StackAlign-1));
3541 // Mask out the low bits for alignment purposes.
3542 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3543 AllocSize.getValueType(), AllocSize,
3544 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3546 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3547 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3548 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3550 DAG.setRoot(DSA.getValue(1));
3552 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3555 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3557 return visitAtomicLoad(I);
3559 const Value *SV = I.getOperand(0);
3560 SDValue Ptr = getValue(SV);
3562 Type *Ty = I.getType();
3564 bool isVolatile = I.isVolatile();
3565 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3566 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3567 unsigned Alignment = I.getAlignment();
3570 I.getAAMetadata(AAInfo);
3571 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3573 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3574 SmallVector<EVT, 4> ValueVTs;
3575 SmallVector<uint64_t, 4> Offsets;
3576 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3577 unsigned NumValues = ValueVTs.size();
3582 bool ConstantMemory = false;
3583 if (isVolatile || NumValues > MaxParallelChains)
3584 // Serialize volatile loads with other side effects.
3586 else if (AA->pointsToConstantMemory(
3587 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3588 // Do not serialize (non-volatile) loads of constant memory with anything.
3589 Root = DAG.getEntryNode();
3590 ConstantMemory = true;
3592 // Do not serialize non-volatile loads against each other.
3593 Root = DAG.getRoot();
3597 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3599 SmallVector<SDValue, 4> Values(NumValues);
3600 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3602 EVT PtrVT = Ptr.getValueType();
3603 unsigned ChainI = 0;
3604 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3605 // Serializing loads here may result in excessive register pressure, and
3606 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3607 // could recover a bit by hoisting nodes upward in the chain by recognizing
3608 // they are side-effect free or do not alias. The optimizer should really
3609 // avoid this case by converting large object/array copies to llvm.memcpy
3610 // (MaxParallelChains should always remain as failsafe).
3611 if (ChainI == MaxParallelChains) {
3612 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3613 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3614 makeArrayRef(Chains.data(), ChainI));
3618 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3620 DAG.getConstant(Offsets[i], PtrVT));
3621 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3622 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3623 isNonTemporal, isInvariant, Alignment, AAInfo,
3627 Chains[ChainI] = L.getValue(1);
3630 if (!ConstantMemory) {
3631 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3632 makeArrayRef(Chains.data(), ChainI));
3636 PendingLoads.push_back(Chain);
3639 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3640 DAG.getVTList(ValueVTs), Values));
3643 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3645 return visitAtomicStore(I);
3647 const Value *SrcV = I.getOperand(0);
3648 const Value *PtrV = I.getOperand(1);
3650 SmallVector<EVT, 4> ValueVTs;
3651 SmallVector<uint64_t, 4> Offsets;
3652 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
3653 ValueVTs, &Offsets);
3654 unsigned NumValues = ValueVTs.size();
3658 // Get the lowered operands. Note that we do this after
3659 // checking if NumResults is zero, because with zero results
3660 // the operands won't have values in the map.
3661 SDValue Src = getValue(SrcV);
3662 SDValue Ptr = getValue(PtrV);
3664 SDValue Root = getRoot();
3665 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3667 EVT PtrVT = Ptr.getValueType();
3668 bool isVolatile = I.isVolatile();
3669 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3670 unsigned Alignment = I.getAlignment();
3673 I.getAAMetadata(AAInfo);
3675 unsigned ChainI = 0;
3676 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3677 // See visitLoad comments.
3678 if (ChainI == MaxParallelChains) {
3679 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3680 makeArrayRef(Chains.data(), ChainI));
3684 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3685 DAG.getConstant(Offsets[i], PtrVT));
3686 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3687 SDValue(Src.getNode(), Src.getResNo() + i),
3688 Add, MachinePointerInfo(PtrV, Offsets[i]),
3689 isVolatile, isNonTemporal, Alignment, AAInfo);
3690 Chains[ChainI] = St;
3693 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3694 makeArrayRef(Chains.data(), ChainI));
3695 DAG.setRoot(StoreNode);
3698 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3699 SDLoc sdl = getCurSDLoc();
3701 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3702 Value *PtrOperand = I.getArgOperand(1);
3703 SDValue Ptr = getValue(PtrOperand);
3704 SDValue Src0 = getValue(I.getArgOperand(0));
3705 SDValue Mask = getValue(I.getArgOperand(3));
3706 EVT VT = Src0.getValueType();
3707 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3709 Alignment = DAG.getEVTAlignment(VT);
3712 I.getAAMetadata(AAInfo);
3714 MachineMemOperand *MMO =
3715 DAG.getMachineFunction().
3716 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3717 MachineMemOperand::MOStore, VT.getStoreSize(),
3719 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3721 DAG.setRoot(StoreNode);
3722 setValue(&I, StoreNode);
3725 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3726 SDLoc sdl = getCurSDLoc();
3728 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3729 Value *PtrOperand = I.getArgOperand(0);
3730 SDValue Ptr = getValue(PtrOperand);
3731 SDValue Src0 = getValue(I.getArgOperand(3));
3732 SDValue Mask = getValue(I.getArgOperand(2));
3734 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3735 EVT VT = TLI.getValueType(I.getType());
3736 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3738 Alignment = DAG.getEVTAlignment(VT);
3741 I.getAAMetadata(AAInfo);
3742 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3744 SDValue InChain = DAG.getRoot();
3745 if (AA->pointsToConstantMemory(
3746 AliasAnalysis::Location(PtrOperand,
3747 AA->getTypeStoreSize(I.getType()),
3749 // Do not serialize (non-volatile) loads of constant memory with anything.
3750 InChain = DAG.getEntryNode();
3753 MachineMemOperand *MMO =
3754 DAG.getMachineFunction().
3755 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3756 MachineMemOperand::MOLoad, VT.getStoreSize(),
3757 Alignment, AAInfo, Ranges);
3759 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3761 SDValue OutChain = Load.getValue(1);
3762 DAG.setRoot(OutChain);
3766 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3767 SDLoc dl = getCurSDLoc();
3768 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3769 AtomicOrdering FailureOrder = I.getFailureOrdering();
3770 SynchronizationScope Scope = I.getSynchScope();
3772 SDValue InChain = getRoot();
3774 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3775 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3776 SDValue L = DAG.getAtomicCmpSwap(
3777 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3778 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3779 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3780 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3782 SDValue OutChain = L.getValue(2);
3785 DAG.setRoot(OutChain);
3788 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3789 SDLoc dl = getCurSDLoc();
3791 switch (I.getOperation()) {
3792 default: llvm_unreachable("Unknown atomicrmw operation");
3793 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3794 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3795 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3796 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3797 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3798 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3799 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3800 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3801 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3802 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3803 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3805 AtomicOrdering Order = I.getOrdering();
3806 SynchronizationScope Scope = I.getSynchScope();
3808 SDValue InChain = getRoot();
3811 DAG.getAtomic(NT, dl,
3812 getValue(I.getValOperand()).getSimpleValueType(),
3814 getValue(I.getPointerOperand()),
3815 getValue(I.getValOperand()),
3816 I.getPointerOperand(),
3817 /* Alignment=*/ 0, Order, Scope);
3819 SDValue OutChain = L.getValue(1);
3822 DAG.setRoot(OutChain);
3825 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3826 SDLoc dl = getCurSDLoc();
3827 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3830 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3831 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3832 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3835 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3836 SDLoc dl = getCurSDLoc();
3837 AtomicOrdering Order = I.getOrdering();
3838 SynchronizationScope Scope = I.getSynchScope();
3840 SDValue InChain = getRoot();
3842 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3843 EVT VT = TLI.getValueType(I.getType());
3845 if (I.getAlignment() < VT.getSizeInBits() / 8)
3846 report_fatal_error("Cannot generate unaligned atomic load");
3848 MachineMemOperand *MMO =
3849 DAG.getMachineFunction().
3850 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3851 MachineMemOperand::MOVolatile |
3852 MachineMemOperand::MOLoad,
3854 I.getAlignment() ? I.getAlignment() :
3855 DAG.getEVTAlignment(VT));
3857 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3859 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3860 getValue(I.getPointerOperand()), MMO,
3863 SDValue OutChain = L.getValue(1);
3866 DAG.setRoot(OutChain);
3869 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3870 SDLoc dl = getCurSDLoc();
3872 AtomicOrdering Order = I.getOrdering();
3873 SynchronizationScope Scope = I.getSynchScope();
3875 SDValue InChain = getRoot();
3877 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3878 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3880 if (I.getAlignment() < VT.getSizeInBits() / 8)
3881 report_fatal_error("Cannot generate unaligned atomic store");
3884 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3886 getValue(I.getPointerOperand()),
3887 getValue(I.getValueOperand()),
3888 I.getPointerOperand(), I.getAlignment(),
3891 DAG.setRoot(OutChain);
3894 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3896 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3897 unsigned Intrinsic) {
3898 bool HasChain = !I.doesNotAccessMemory();
3899 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3901 // Build the operand list.
3902 SmallVector<SDValue, 8> Ops;
3903 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3905 // We don't need to serialize loads against other loads.
3906 Ops.push_back(DAG.getRoot());
3908 Ops.push_back(getRoot());
3912 // Info is set by getTgtMemInstrinsic
3913 TargetLowering::IntrinsicInfo Info;
3914 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3915 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3917 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3918 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3919 Info.opc == ISD::INTRINSIC_W_CHAIN)
3920 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3922 // Add all operands of the call to the operand list.
3923 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3924 SDValue Op = getValue(I.getArgOperand(i));
3928 SmallVector<EVT, 4> ValueVTs;
3929 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3932 ValueVTs.push_back(MVT::Other);
3934 SDVTList VTs = DAG.getVTList(ValueVTs);
3938 if (IsTgtIntrinsic) {
3939 // This is target intrinsic that touches memory
3940 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3941 VTs, Ops, Info.memVT,
3942 MachinePointerInfo(Info.ptrVal, Info.offset),
3943 Info.align, Info.vol,
3944 Info.readMem, Info.writeMem, Info.size);
3945 } else if (!HasChain) {
3946 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3947 } else if (!I.getType()->isVoidTy()) {
3948 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3950 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3954 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3956 PendingLoads.push_back(Chain);
3961 if (!I.getType()->isVoidTy()) {
3962 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3963 EVT VT = TLI.getValueType(PTy);
3964 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3967 setValue(&I, Result);
3971 /// GetSignificand - Get the significand and build it into a floating-point
3972 /// number with exponent of 1:
3974 /// Op = (Op & 0x007fffff) | 0x3f800000;
3976 /// where Op is the hexadecimal representation of floating point value.
3978 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3979 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3980 DAG.getConstant(0x007fffff, MVT::i32));
3981 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3982 DAG.getConstant(0x3f800000, MVT::i32));
3983 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3986 /// GetExponent - Get the exponent:
3988 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3990 /// where Op is the hexadecimal representation of floating point value.
3992 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3994 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3995 DAG.getConstant(0x7f800000, MVT::i32));
3996 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3997 DAG.getConstant(23, TLI.getPointerTy()));
3998 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3999 DAG.getConstant(127, MVT::i32));
4000 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
4003 /// getF32Constant - Get 32-bit floating point constant.
4005 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
4006 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
4010 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
4011 /// limited-precision mode.
4012 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4013 const TargetLowering &TLI) {
4014 if (Op.getValueType() == MVT::f32 &&
4015 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4017 // Put the exponent in the right bit position for later addition to the
4020 // #define LOG2OFe 1.4426950f
4021 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
4022 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4023 getF32Constant(DAG, 0x3fb8aa3b));
4024 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4026 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
4027 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4028 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4030 // IntegerPartOfX <<= 23;
4031 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4032 DAG.getConstant(23, TLI.getPointerTy()));
4034 SDValue TwoToFracPartOfX;
4035 if (LimitFloatPrecision <= 6) {
4036 // For floating-point precision of 6:
4038 // TwoToFractionalPartOfX =
4040 // (0.735607626f + 0.252464424f * x) * x;
4042 // error 0.0144103317, which is 6 bits
4043 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4044 getF32Constant(DAG, 0x3e814304));
4045 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4046 getF32Constant(DAG, 0x3f3c50c8));
4047 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4048 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4049 getF32Constant(DAG, 0x3f7f5e7e));
4050 } else if (LimitFloatPrecision <= 12) {
4051 // For floating-point precision of 12:
4053 // TwoToFractionalPartOfX =
4056 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4058 // 0.000107046256 error, which is 13 to 14 bits
4059 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4060 getF32Constant(DAG, 0x3da235e3));
4061 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4062 getF32Constant(DAG, 0x3e65b8f3));
4063 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4064 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4065 getF32Constant(DAG, 0x3f324b07));
4066 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4067 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4068 getF32Constant(DAG, 0x3f7ff8fd));
4069 } else { // LimitFloatPrecision <= 18
4070 // For floating-point precision of 18:
4072 // TwoToFractionalPartOfX =
4076 // (0.554906021e-1f +
4077 // (0.961591928e-2f +
4078 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4080 // error 2.47208000*10^(-7), which is better than 18 bits
4081 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4082 getF32Constant(DAG, 0x3924b03e));
4083 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4084 getF32Constant(DAG, 0x3ab24b87));
4085 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4086 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4087 getF32Constant(DAG, 0x3c1d8c17));
4088 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4089 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4090 getF32Constant(DAG, 0x3d634a1d));
4091 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4092 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4093 getF32Constant(DAG, 0x3e75fe14));
4094 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4095 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4096 getF32Constant(DAG, 0x3f317234));
4097 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4098 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4099 getF32Constant(DAG, 0x3f800000));
4102 // Add the exponent into the result in integer domain.
4103 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
4104 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4105 DAG.getNode(ISD::ADD, dl, MVT::i32,
4106 t13, IntegerPartOfX));
4109 // No special expansion.
4110 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4113 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4114 /// limited-precision mode.
4115 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4116 const TargetLowering &TLI) {
4117 if (Op.getValueType() == MVT::f32 &&
4118 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4119 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4121 // Scale the exponent by log(2) [0.69314718f].
4122 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4123 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4124 getF32Constant(DAG, 0x3f317218));
4126 // Get the significand and build it into a floating-point number with
4128 SDValue X = GetSignificand(DAG, Op1, dl);
4130 SDValue LogOfMantissa;
4131 if (LimitFloatPrecision <= 6) {
4132 // For floating-point precision of 6:
4136 // (1.4034025f - 0.23903021f * x) * x;
4138 // error 0.0034276066, which is better than 8 bits
4139 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4140 getF32Constant(DAG, 0xbe74c456));
4141 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4142 getF32Constant(DAG, 0x3fb3a2b1));
4143 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4144 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4145 getF32Constant(DAG, 0x3f949a29));
4146 } else if (LimitFloatPrecision <= 12) {
4147 // For floating-point precision of 12:
4153 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4155 // error 0.000061011436, which is 14 bits
4156 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4157 getF32Constant(DAG, 0xbd67b6d6));
4158 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4159 getF32Constant(DAG, 0x3ee4f4b8));
4160 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4161 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4162 getF32Constant(DAG, 0x3fbc278b));
4163 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4164 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4165 getF32Constant(DAG, 0x40348e95));
4166 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4167 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4168 getF32Constant(DAG, 0x3fdef31a));
4169 } else { // LimitFloatPrecision <= 18
4170 // For floating-point precision of 18:
4178 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4180 // error 0.0000023660568, which is better than 18 bits
4181 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4182 getF32Constant(DAG, 0xbc91e5ac));
4183 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4184 getF32Constant(DAG, 0x3e4350aa));
4185 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4186 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4187 getF32Constant(DAG, 0x3f60d3e3));
4188 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4189 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4190 getF32Constant(DAG, 0x4011cdf0));
4191 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4192 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4193 getF32Constant(DAG, 0x406cfd1c));
4194 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4195 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4196 getF32Constant(DAG, 0x408797cb));
4197 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4198 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4199 getF32Constant(DAG, 0x4006dcab));
4202 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4205 // No special expansion.
4206 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4209 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4210 /// limited-precision mode.
4211 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4212 const TargetLowering &TLI) {
4213 if (Op.getValueType() == MVT::f32 &&
4214 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4215 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4217 // Get the exponent.
4218 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4220 // Get the significand and build it into a floating-point number with
4222 SDValue X = GetSignificand(DAG, Op1, dl);
4224 // Different possible minimax approximations of significand in
4225 // floating-point for various degrees of accuracy over [1,2].
4226 SDValue Log2ofMantissa;
4227 if (LimitFloatPrecision <= 6) {
4228 // For floating-point precision of 6:
4230 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4232 // error 0.0049451742, which is more than 7 bits
4233 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4234 getF32Constant(DAG, 0xbeb08fe0));
4235 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4236 getF32Constant(DAG, 0x40019463));
4237 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4238 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4239 getF32Constant(DAG, 0x3fd6633d));
4240 } else if (LimitFloatPrecision <= 12) {
4241 // For floating-point precision of 12:
4247 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4249 // error 0.0000876136000, which is better than 13 bits
4250 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4251 getF32Constant(DAG, 0xbda7262e));
4252 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4253 getF32Constant(DAG, 0x3f25280b));
4254 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4255 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4256 getF32Constant(DAG, 0x4007b923));
4257 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4258 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4259 getF32Constant(DAG, 0x40823e2f));
4260 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4261 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4262 getF32Constant(DAG, 0x4020d29c));
4263 } else { // LimitFloatPrecision <= 18
4264 // For floating-point precision of 18:
4273 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4275 // error 0.0000018516, which is better than 18 bits
4276 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4277 getF32Constant(DAG, 0xbcd2769e));
4278 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4279 getF32Constant(DAG, 0x3e8ce0b9));
4280 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4281 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4282 getF32Constant(DAG, 0x3fa22ae7));
4283 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4284 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4285 getF32Constant(DAG, 0x40525723));
4286 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4287 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4288 getF32Constant(DAG, 0x40aaf200));
4289 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4290 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4291 getF32Constant(DAG, 0x40c39dad));
4292 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4293 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4294 getF32Constant(DAG, 0x4042902c));
4297 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4300 // No special expansion.
4301 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4304 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4305 /// limited-precision mode.
4306 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4307 const TargetLowering &TLI) {
4308 if (Op.getValueType() == MVT::f32 &&
4309 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4310 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4312 // Scale the exponent by log10(2) [0.30102999f].
4313 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4314 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4315 getF32Constant(DAG, 0x3e9a209a));
4317 // Get the significand and build it into a floating-point number with
4319 SDValue X = GetSignificand(DAG, Op1, dl);
4321 SDValue Log10ofMantissa;
4322 if (LimitFloatPrecision <= 6) {
4323 // For floating-point precision of 6:
4325 // Log10ofMantissa =
4327 // (0.60948995f - 0.10380950f * x) * x;
4329 // error 0.0014886165, which is 6 bits
4330 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4331 getF32Constant(DAG, 0xbdd49a13));
4332 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4333 getF32Constant(DAG, 0x3f1c0789));
4334 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4335 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4336 getF32Constant(DAG, 0x3f011300));
4337 } else if (LimitFloatPrecision <= 12) {
4338 // For floating-point precision of 12:
4340 // Log10ofMantissa =
4343 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4345 // error 0.00019228036, which is better than 12 bits
4346 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4347 getF32Constant(DAG, 0x3d431f31));
4348 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4349 getF32Constant(DAG, 0x3ea21fb2));
4350 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4351 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4352 getF32Constant(DAG, 0x3f6ae232));
4353 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4354 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4355 getF32Constant(DAG, 0x3f25f7c3));
4356 } else { // LimitFloatPrecision <= 18
4357 // For floating-point precision of 18:
4359 // Log10ofMantissa =
4364 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4366 // error 0.0000037995730, which is better than 18 bits
4367 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4368 getF32Constant(DAG, 0x3c5d51ce));
4369 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4370 getF32Constant(DAG, 0x3e00685a));
4371 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4372 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4373 getF32Constant(DAG, 0x3efb6798));
4374 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4375 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4376 getF32Constant(DAG, 0x3f88d192));
4377 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4378 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4379 getF32Constant(DAG, 0x3fc4316c));
4380 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4381 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4382 getF32Constant(DAG, 0x3f57ce70));
4385 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4388 // No special expansion.
4389 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4392 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4393 /// limited-precision mode.
4394 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4395 const TargetLowering &TLI) {
4396 if (Op.getValueType() == MVT::f32 &&
4397 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4398 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4400 // FractionalPartOfX = x - (float)IntegerPartOfX;
4401 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4402 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4404 // IntegerPartOfX <<= 23;
4405 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4406 DAG.getConstant(23, TLI.getPointerTy()));
4408 SDValue TwoToFractionalPartOfX;
4409 if (LimitFloatPrecision <= 6) {
4410 // For floating-point precision of 6:
4412 // TwoToFractionalPartOfX =
4414 // (0.735607626f + 0.252464424f * x) * x;
4416 // error 0.0144103317, which is 6 bits
4417 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4418 getF32Constant(DAG, 0x3e814304));
4419 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4420 getF32Constant(DAG, 0x3f3c50c8));
4421 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4422 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4423 getF32Constant(DAG, 0x3f7f5e7e));
4424 } else if (LimitFloatPrecision <= 12) {
4425 // For floating-point precision of 12:
4427 // TwoToFractionalPartOfX =
4430 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4432 // error 0.000107046256, which is 13 to 14 bits
4433 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4434 getF32Constant(DAG, 0x3da235e3));
4435 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4436 getF32Constant(DAG, 0x3e65b8f3));
4437 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4438 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4439 getF32Constant(DAG, 0x3f324b07));
4440 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4441 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4442 getF32Constant(DAG, 0x3f7ff8fd));
4443 } else { // LimitFloatPrecision <= 18
4444 // For floating-point precision of 18:
4446 // TwoToFractionalPartOfX =
4450 // (0.554906021e-1f +
4451 // (0.961591928e-2f +
4452 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4453 // error 2.47208000*10^(-7), which is better than 18 bits
4454 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4455 getF32Constant(DAG, 0x3924b03e));
4456 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4457 getF32Constant(DAG, 0x3ab24b87));
4458 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4459 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4460 getF32Constant(DAG, 0x3c1d8c17));
4461 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4462 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4463 getF32Constant(DAG, 0x3d634a1d));
4464 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4465 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4466 getF32Constant(DAG, 0x3e75fe14));
4467 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4468 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4469 getF32Constant(DAG, 0x3f317234));
4470 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4471 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4472 getF32Constant(DAG, 0x3f800000));
4475 // Add the exponent into the result in integer domain.
4476 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4477 TwoToFractionalPartOfX);
4478 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4479 DAG.getNode(ISD::ADD, dl, MVT::i32,
4480 t13, IntegerPartOfX));
4483 // No special expansion.
4484 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4487 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4488 /// limited-precision mode with x == 10.0f.
4489 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4490 SelectionDAG &DAG, const TargetLowering &TLI) {
4491 bool IsExp10 = false;
4492 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4493 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4494 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4496 IsExp10 = LHSC->isExactlyValue(Ten);
4501 // Put the exponent in the right bit position for later addition to the
4504 // #define LOG2OF10 3.3219281f
4505 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4506 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4507 getF32Constant(DAG, 0x40549a78));
4508 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4510 // FractionalPartOfX = x - (float)IntegerPartOfX;
4511 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4512 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4514 // IntegerPartOfX <<= 23;
4515 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4516 DAG.getConstant(23, TLI.getPointerTy()));
4518 SDValue TwoToFractionalPartOfX;
4519 if (LimitFloatPrecision <= 6) {
4520 // For floating-point precision of 6:
4522 // twoToFractionalPartOfX =
4524 // (0.735607626f + 0.252464424f * x) * x;
4526 // error 0.0144103317, which is 6 bits
4527 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4528 getF32Constant(DAG, 0x3e814304));
4529 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4530 getF32Constant(DAG, 0x3f3c50c8));
4531 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4532 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4533 getF32Constant(DAG, 0x3f7f5e7e));
4534 } else if (LimitFloatPrecision <= 12) {
4535 // For floating-point precision of 12:
4537 // TwoToFractionalPartOfX =
4540 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4542 // error 0.000107046256, which is 13 to 14 bits
4543 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4544 getF32Constant(DAG, 0x3da235e3));
4545 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4546 getF32Constant(DAG, 0x3e65b8f3));
4547 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4548 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4549 getF32Constant(DAG, 0x3f324b07));
4550 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4551 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4552 getF32Constant(DAG, 0x3f7ff8fd));
4553 } else { // LimitFloatPrecision <= 18
4554 // For floating-point precision of 18:
4556 // TwoToFractionalPartOfX =
4560 // (0.554906021e-1f +
4561 // (0.961591928e-2f +
4562 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4563 // error 2.47208000*10^(-7), which is better than 18 bits
4564 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4565 getF32Constant(DAG, 0x3924b03e));
4566 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4567 getF32Constant(DAG, 0x3ab24b87));
4568 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4569 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4570 getF32Constant(DAG, 0x3c1d8c17));
4571 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4572 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4573 getF32Constant(DAG, 0x3d634a1d));
4574 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4575 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4576 getF32Constant(DAG, 0x3e75fe14));
4577 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4578 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4579 getF32Constant(DAG, 0x3f317234));
4580 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4581 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4582 getF32Constant(DAG, 0x3f800000));
4585 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4586 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4587 DAG.getNode(ISD::ADD, dl, MVT::i32,
4588 t13, IntegerPartOfX));
4591 // No special expansion.
4592 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4596 /// ExpandPowI - Expand a llvm.powi intrinsic.
4597 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4598 SelectionDAG &DAG) {
4599 // If RHS is a constant, we can expand this out to a multiplication tree,
4600 // otherwise we end up lowering to a call to __powidf2 (for example). When
4601 // optimizing for size, we only want to do this if the expansion would produce
4602 // a small number of multiplies, otherwise we do the full expansion.
4603 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4604 // Get the exponent as a positive value.
4605 unsigned Val = RHSC->getSExtValue();
4606 if ((int)Val < 0) Val = -Val;
4608 // powi(x, 0) -> 1.0
4610 return DAG.getConstantFP(1.0, LHS.getValueType());
4612 const Function *F = DAG.getMachineFunction().getFunction();
4613 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
4614 // If optimizing for size, don't insert too many multiplies. This
4615 // inserts up to 5 multiplies.
4616 countPopulation(Val) + Log2_32(Val) < 7) {
4617 // We use the simple binary decomposition method to generate the multiply
4618 // sequence. There are more optimal ways to do this (for example,
4619 // powi(x,15) generates one more multiply than it should), but this has
4620 // the benefit of being both really simple and much better than a libcall.
4621 SDValue Res; // Logically starts equal to 1.0
4622 SDValue CurSquare = LHS;
4626 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4628 Res = CurSquare; // 1.0*CurSquare.
4631 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4632 CurSquare, CurSquare);
4636 // If the original was negative, invert the result, producing 1/(x*x*x).
4637 if (RHSC->getSExtValue() < 0)
4638 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4639 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4644 // Otherwise, expand to a libcall.
4645 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4648 // getTruncatedArgReg - Find underlying register used for an truncated
4650 static unsigned getTruncatedArgReg(const SDValue &N) {
4651 if (N.getOpcode() != ISD::TRUNCATE)
4654 const SDValue &Ext = N.getOperand(0);
4655 if (Ext.getOpcode() == ISD::AssertZext ||
4656 Ext.getOpcode() == ISD::AssertSext) {
4657 const SDValue &CFR = Ext.getOperand(0);
4658 if (CFR.getOpcode() == ISD::CopyFromReg)
4659 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4660 if (CFR.getOpcode() == ISD::TRUNCATE)
4661 return getTruncatedArgReg(CFR);
4666 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4667 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4668 /// At the end of instruction selection, they will be inserted to the entry BB.
4669 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V,
4671 MDNode *Expr, int64_t Offset,
4674 const Argument *Arg = dyn_cast<Argument>(V);
4678 MachineFunction &MF = DAG.getMachineFunction();
4679 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4681 // Ignore inlined function arguments here.
4682 DIVariable DV(Variable);
4683 if (DV.isInlinedFnArgument(MF.getFunction()))
4686 Optional<MachineOperand> Op;
4687 // Some arguments' frame index is recorded during argument lowering.
4688 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4689 Op = MachineOperand::CreateFI(FI);
4691 if (!Op && N.getNode()) {
4693 if (N.getOpcode() == ISD::CopyFromReg)
4694 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4696 Reg = getTruncatedArgReg(N);
4697 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4698 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4699 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4704 Op = MachineOperand::CreateReg(Reg, false);
4708 // Check if ValueMap has reg number.
4709 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4710 if (VMI != FuncInfo.ValueMap.end())
4711 Op = MachineOperand::CreateReg(VMI->second, false);
4714 if (!Op && N.getNode())
4715 // Check if frame index is available.
4716 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4717 if (FrameIndexSDNode *FINode =
4718 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4719 Op = MachineOperand::CreateFI(FINode->getIndex());
4725 FuncInfo.ArgDbgValues.push_back(
4726 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE),
4727 IsIndirect, Op->getReg(), Offset, Variable, Expr));
4729 FuncInfo.ArgDbgValues.push_back(
4730 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4733 .addMetadata(Variable)
4734 .addMetadata(Expr));
4739 // VisualStudio defines setjmp as _setjmp
4740 #if defined(_MSC_VER) && defined(setjmp) && \
4741 !defined(setjmp_undefined_for_msvc)
4742 # pragma push_macro("setjmp")
4744 # define setjmp_undefined_for_msvc
4747 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4748 /// we want to emit this as a call to a named external function, return the name
4749 /// otherwise lower it and return null.
4751 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4752 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4753 SDLoc sdl = getCurSDLoc();
4754 DebugLoc dl = getCurDebugLoc();
4757 switch (Intrinsic) {
4759 // By default, turn this into a target intrinsic node.
4760 visitTargetIntrinsic(I, Intrinsic);
4762 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4763 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4764 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4765 case Intrinsic::returnaddress:
4766 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4767 getValue(I.getArgOperand(0))));
4769 case Intrinsic::frameaddress:
4770 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4771 getValue(I.getArgOperand(0))));
4773 case Intrinsic::read_register: {
4774 Value *Reg = I.getArgOperand(0);
4776 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4777 EVT VT = TLI.getValueType(I.getType());
4778 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4781 case Intrinsic::write_register: {
4782 Value *Reg = I.getArgOperand(0);
4783 Value *RegValue = I.getArgOperand(1);
4784 SDValue Chain = getValue(RegValue).getOperand(0);
4786 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4787 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4788 RegName, getValue(RegValue)));
4791 case Intrinsic::setjmp:
4792 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4793 case Intrinsic::longjmp:
4794 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4795 case Intrinsic::memcpy: {
4796 // FIXME: this definition of "user defined address space" is x86-specific
4797 // Assert for address < 256 since we support only user defined address
4799 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4801 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4803 "Unknown address space");
4804 SDValue Op1 = getValue(I.getArgOperand(0));
4805 SDValue Op2 = getValue(I.getArgOperand(1));
4806 SDValue Op3 = getValue(I.getArgOperand(2));
4807 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4809 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4810 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4811 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4812 MachinePointerInfo(I.getArgOperand(0)),
4813 MachinePointerInfo(I.getArgOperand(1))));
4816 case Intrinsic::memset: {
4817 // FIXME: this definition of "user defined address space" is x86-specific
4818 // Assert for address < 256 since we support only user defined address
4820 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4822 "Unknown address space");
4823 SDValue Op1 = getValue(I.getArgOperand(0));
4824 SDValue Op2 = getValue(I.getArgOperand(1));
4825 SDValue Op3 = getValue(I.getArgOperand(2));
4826 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4828 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4829 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4830 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4831 MachinePointerInfo(I.getArgOperand(0))));
4834 case Intrinsic::memmove: {
4835 // FIXME: this definition of "user defined address space" is x86-specific
4836 // Assert for address < 256 since we support only user defined address
4838 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4840 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4842 "Unknown address space");
4843 SDValue Op1 = getValue(I.getArgOperand(0));
4844 SDValue Op2 = getValue(I.getArgOperand(1));
4845 SDValue Op3 = getValue(I.getArgOperand(2));
4846 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4848 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4849 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4850 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4851 MachinePointerInfo(I.getArgOperand(0)),
4852 MachinePointerInfo(I.getArgOperand(1))));
4855 case Intrinsic::dbg_declare: {
4856 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4857 MDNode *Variable = DI.getVariable();
4858 MDNode *Expression = DI.getExpression();
4859 const Value *Address = DI.getAddress();
4860 DIVariable DIVar(Variable);
4861 assert((!DIVar || DIVar.isVariable()) &&
4862 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4863 if (!Address || !DIVar) {
4864 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4868 // Check if address has undef value.
4869 if (isa<UndefValue>(Address) ||
4870 (Address->use_empty() && !isa<Argument>(Address))) {
4871 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4875 SDValue &N = NodeMap[Address];
4876 if (!N.getNode() && isa<Argument>(Address))
4877 // Check unused arguments map.
4878 N = UnusedArgNodeMap[Address];
4881 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4882 Address = BCI->getOperand(0);
4883 // Parameters are handled specially.
4885 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4886 isa<Argument>(Address));
4888 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4890 if (isParameter && !AI) {
4891 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4893 // Byval parameter. We have a frame index at this point.
4894 SDV = DAG.getFrameIndexDbgValue(
4895 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4897 // Address is an argument, so try to emit its dbg value using
4898 // virtual register info from the FuncInfo.ValueMap.
4899 EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false, N);
4903 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4904 true, 0, dl, SDNodeOrder);
4906 // Can't do anything with other non-AI cases yet.
4907 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4908 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4909 DEBUG(Address->dump());
4912 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4914 // If Address is an argument then try to emit its dbg value using
4915 // virtual register info from the FuncInfo.ValueMap.
4916 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false,
4918 // If variable is pinned by a alloca in dominating bb then
4919 // use StaticAllocaMap.
4920 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4921 if (AI->getParent() != DI.getParent()) {
4922 DenseMap<const AllocaInst*, int>::iterator SI =
4923 FuncInfo.StaticAllocaMap.find(AI);
4924 if (SI != FuncInfo.StaticAllocaMap.end()) {
4925 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4926 0, dl, SDNodeOrder);
4927 DAG.AddDbgValue(SDV, nullptr, false);
4932 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4937 case Intrinsic::dbg_value: {
4938 const DbgValueInst &DI = cast<DbgValueInst>(I);
4939 DIVariable DIVar(DI.getVariable());
4940 assert((!DIVar || DIVar.isVariable()) &&
4941 "Variable in DbgValueInst should be either null or a DIVariable.");
4945 MDNode *Variable = DI.getVariable();
4946 MDNode *Expression = DI.getExpression();
4947 uint64_t Offset = DI.getOffset();
4948 const Value *V = DI.getValue();
4953 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4954 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4956 DAG.AddDbgValue(SDV, nullptr, false);
4958 // Do not use getValue() in here; we don't want to generate code at
4959 // this point if it hasn't been done yet.
4960 SDValue N = NodeMap[V];
4961 if (!N.getNode() && isa<Argument>(V))
4962 // Check unused arguments map.
4963 N = UnusedArgNodeMap[V];
4965 // A dbg.value for an alloca is always indirect.
4966 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4967 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, Offset,
4969 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4970 IsIndirect, Offset, dl, SDNodeOrder);
4971 DAG.AddDbgValue(SDV, N.getNode(), false);
4973 } else if (!V->use_empty() ) {
4974 // Do not call getValue(V) yet, as we don't want to generate code.
4975 // Remember it for later.
4976 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4977 DanglingDebugInfoMap[V] = DDI;
4979 // We may expand this to cover more cases. One case where we have no
4980 // data available is an unreferenced parameter.
4981 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4985 // Build a debug info table entry.
4986 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4987 V = BCI->getOperand(0);
4988 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4989 // Don't handle byval struct arguments or VLAs, for example.
4991 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4992 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4995 DenseMap<const AllocaInst*, int>::iterator SI =
4996 FuncInfo.StaticAllocaMap.find(AI);
4997 if (SI == FuncInfo.StaticAllocaMap.end())
4998 return nullptr; // VLAs.
5002 case Intrinsic::eh_typeid_for: {
5003 // Find the type id for the given typeinfo.
5004 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
5005 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
5006 Res = DAG.getConstant(TypeID, MVT::i32);
5011 case Intrinsic::eh_return_i32:
5012 case Intrinsic::eh_return_i64:
5013 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
5014 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
5017 getValue(I.getArgOperand(0)),
5018 getValue(I.getArgOperand(1))));
5020 case Intrinsic::eh_unwind_init:
5021 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
5023 case Intrinsic::eh_dwarf_cfa: {
5024 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
5025 TLI.getPointerTy());
5026 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
5027 CfaArg.getValueType(),
5028 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
5029 CfaArg.getValueType()),
5031 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
5032 DAG.getConstant(0, TLI.getPointerTy()));
5033 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
5037 case Intrinsic::eh_sjlj_callsite: {
5038 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5039 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
5040 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
5041 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
5043 MMI.setCurrentCallSite(CI->getZExtValue());
5046 case Intrinsic::eh_sjlj_functioncontext: {
5047 // Get and store the index of the function context.
5048 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5050 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
5051 int FI = FuncInfo.StaticAllocaMap[FnCtx];
5052 MFI->setFunctionContextIndex(FI);
5055 case Intrinsic::eh_sjlj_setjmp: {
5058 Ops[1] = getValue(I.getArgOperand(0));
5059 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
5060 DAG.getVTList(MVT::i32, MVT::Other), Ops);
5061 setValue(&I, Op.getValue(0));
5062 DAG.setRoot(Op.getValue(1));
5065 case Intrinsic::eh_sjlj_longjmp: {
5066 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
5067 getRoot(), getValue(I.getArgOperand(0))));
5071 case Intrinsic::masked_load:
5074 case Intrinsic::masked_store:
5075 visitMaskedStore(I);
5077 case Intrinsic::x86_mmx_pslli_w:
5078 case Intrinsic::x86_mmx_pslli_d:
5079 case Intrinsic::x86_mmx_pslli_q:
5080 case Intrinsic::x86_mmx_psrli_w:
5081 case Intrinsic::x86_mmx_psrli_d:
5082 case Intrinsic::x86_mmx_psrli_q:
5083 case Intrinsic::x86_mmx_psrai_w:
5084 case Intrinsic::x86_mmx_psrai_d: {
5085 SDValue ShAmt = getValue(I.getArgOperand(1));
5086 if (isa<ConstantSDNode>(ShAmt)) {
5087 visitTargetIntrinsic(I, Intrinsic);
5090 unsigned NewIntrinsic = 0;
5091 EVT ShAmtVT = MVT::v2i32;
5092 switch (Intrinsic) {
5093 case Intrinsic::x86_mmx_pslli_w:
5094 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
5096 case Intrinsic::x86_mmx_pslli_d:
5097 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
5099 case Intrinsic::x86_mmx_pslli_q:
5100 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
5102 case Intrinsic::x86_mmx_psrli_w:
5103 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
5105 case Intrinsic::x86_mmx_psrli_d:
5106 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
5108 case Intrinsic::x86_mmx_psrli_q:
5109 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
5111 case Intrinsic::x86_mmx_psrai_w:
5112 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
5114 case Intrinsic::x86_mmx_psrai_d:
5115 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
5117 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5120 // The vector shift intrinsics with scalars uses 32b shift amounts but
5121 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5123 // We must do this early because v2i32 is not a legal type.
5126 ShOps[1] = DAG.getConstant(0, MVT::i32);
5127 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
5128 EVT DestVT = TLI.getValueType(I.getType());
5129 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5130 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5131 DAG.getConstant(NewIntrinsic, MVT::i32),
5132 getValue(I.getArgOperand(0)), ShAmt);
5136 case Intrinsic::x86_avx_vinsertf128_pd_256:
5137 case Intrinsic::x86_avx_vinsertf128_ps_256:
5138 case Intrinsic::x86_avx_vinsertf128_si_256:
5139 case Intrinsic::x86_avx2_vinserti128: {
5140 EVT DestVT = TLI.getValueType(I.getType());
5141 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
5142 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
5143 ElVT.getVectorNumElements();
5145 DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
5146 getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)),
5147 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5151 case Intrinsic::x86_avx_vextractf128_pd_256:
5152 case Intrinsic::x86_avx_vextractf128_ps_256:
5153 case Intrinsic::x86_avx_vextractf128_si_256:
5154 case Intrinsic::x86_avx2_vextracti128: {
5155 EVT DestVT = TLI.getValueType(I.getType());
5156 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5157 DestVT.getVectorNumElements();
5158 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5159 getValue(I.getArgOperand(0)),
5160 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5164 case Intrinsic::convertff:
5165 case Intrinsic::convertfsi:
5166 case Intrinsic::convertfui:
5167 case Intrinsic::convertsif:
5168 case Intrinsic::convertuif:
5169 case Intrinsic::convertss:
5170 case Intrinsic::convertsu:
5171 case Intrinsic::convertus:
5172 case Intrinsic::convertuu: {
5173 ISD::CvtCode Code = ISD::CVT_INVALID;
5174 switch (Intrinsic) {
5175 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5176 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5177 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5178 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5179 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5180 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5181 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5182 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5183 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5184 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5186 EVT DestVT = TLI.getValueType(I.getType());
5187 const Value *Op1 = I.getArgOperand(0);
5188 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5189 DAG.getValueType(DestVT),
5190 DAG.getValueType(getValue(Op1).getValueType()),
5191 getValue(I.getArgOperand(1)),
5192 getValue(I.getArgOperand(2)),
5197 case Intrinsic::powi:
5198 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5199 getValue(I.getArgOperand(1)), DAG));
5201 case Intrinsic::log:
5202 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5204 case Intrinsic::log2:
5205 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5207 case Intrinsic::log10:
5208 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5210 case Intrinsic::exp:
5211 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5213 case Intrinsic::exp2:
5214 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5216 case Intrinsic::pow:
5217 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5218 getValue(I.getArgOperand(1)), DAG, TLI));
5220 case Intrinsic::sqrt:
5221 case Intrinsic::fabs:
5222 case Intrinsic::sin:
5223 case Intrinsic::cos:
5224 case Intrinsic::floor:
5225 case Intrinsic::ceil:
5226 case Intrinsic::trunc:
5227 case Intrinsic::rint:
5228 case Intrinsic::nearbyint:
5229 case Intrinsic::round: {
5231 switch (Intrinsic) {
5232 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5233 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5234 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5235 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5236 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5237 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5238 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5239 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5240 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5241 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5242 case Intrinsic::round: Opcode = ISD::FROUND; break;
5245 setValue(&I, DAG.getNode(Opcode, sdl,
5246 getValue(I.getArgOperand(0)).getValueType(),
5247 getValue(I.getArgOperand(0))));
5250 case Intrinsic::minnum:
5251 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
5252 getValue(I.getArgOperand(0)).getValueType(),
5253 getValue(I.getArgOperand(0)),
5254 getValue(I.getArgOperand(1))));
5256 case Intrinsic::maxnum:
5257 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
5258 getValue(I.getArgOperand(0)).getValueType(),
5259 getValue(I.getArgOperand(0)),
5260 getValue(I.getArgOperand(1))));
5262 case Intrinsic::copysign:
5263 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5264 getValue(I.getArgOperand(0)).getValueType(),
5265 getValue(I.getArgOperand(0)),
5266 getValue(I.getArgOperand(1))));
5268 case Intrinsic::fma:
5269 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5270 getValue(I.getArgOperand(0)).getValueType(),
5271 getValue(I.getArgOperand(0)),
5272 getValue(I.getArgOperand(1)),
5273 getValue(I.getArgOperand(2))));
5275 case Intrinsic::fmuladd: {
5276 EVT VT = TLI.getValueType(I.getType());
5277 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5278 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5279 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5280 getValue(I.getArgOperand(0)).getValueType(),
5281 getValue(I.getArgOperand(0)),
5282 getValue(I.getArgOperand(1)),
5283 getValue(I.getArgOperand(2))));
5285 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5286 getValue(I.getArgOperand(0)).getValueType(),
5287 getValue(I.getArgOperand(0)),
5288 getValue(I.getArgOperand(1)));
5289 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5290 getValue(I.getArgOperand(0)).getValueType(),
5292 getValue(I.getArgOperand(2)));
5297 case Intrinsic::convert_to_fp16:
5298 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5299 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5300 getValue(I.getArgOperand(0)),
5301 DAG.getTargetConstant(0, MVT::i32))));
5303 case Intrinsic::convert_from_fp16:
5305 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
5306 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5307 getValue(I.getArgOperand(0)))));
5309 case Intrinsic::pcmarker: {
5310 SDValue Tmp = getValue(I.getArgOperand(0));
5311 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5314 case Intrinsic::readcyclecounter: {
5315 SDValue Op = getRoot();
5316 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5317 DAG.getVTList(MVT::i64, MVT::Other), Op);
5319 DAG.setRoot(Res.getValue(1));
5322 case Intrinsic::bswap:
5323 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5324 getValue(I.getArgOperand(0)).getValueType(),
5325 getValue(I.getArgOperand(0))));
5327 case Intrinsic::cttz: {
5328 SDValue Arg = getValue(I.getArgOperand(0));
5329 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5330 EVT Ty = Arg.getValueType();
5331 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5335 case Intrinsic::ctlz: {
5336 SDValue Arg = getValue(I.getArgOperand(0));
5337 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5338 EVT Ty = Arg.getValueType();
5339 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5343 case Intrinsic::ctpop: {
5344 SDValue Arg = getValue(I.getArgOperand(0));
5345 EVT Ty = Arg.getValueType();
5346 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5349 case Intrinsic::stacksave: {
5350 SDValue Op = getRoot();
5351 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5352 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
5354 DAG.setRoot(Res.getValue(1));
5357 case Intrinsic::stackrestore: {
5358 Res = getValue(I.getArgOperand(0));
5359 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5362 case Intrinsic::stackprotector: {
5363 // Emit code into the DAG to store the stack guard onto the stack.
5364 MachineFunction &MF = DAG.getMachineFunction();
5365 MachineFrameInfo *MFI = MF.getFrameInfo();
5366 EVT PtrTy = TLI.getPointerTy();
5367 SDValue Src, Chain = getRoot();
5368 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5369 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5371 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5372 // global variable __stack_chk_guard.
5374 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5375 if (BC->getOpcode() == Instruction::BitCast)
5376 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5378 if (GV && TLI.useLoadStackGuardNode()) {
5379 // Emit a LOAD_STACK_GUARD node.
5380 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5382 MachinePointerInfo MPInfo(GV);
5383 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5384 unsigned Flags = MachineMemOperand::MOLoad |
5385 MachineMemOperand::MOInvariant;
5386 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5387 PtrTy.getSizeInBits() / 8,
5388 DAG.getEVTAlignment(PtrTy));
5389 Node->setMemRefs(MemRefs, MemRefs + 1);
5391 // Copy the guard value to a virtual register so that it can be
5392 // retrieved in the epilogue.
5393 Src = SDValue(Node, 0);
5394 const TargetRegisterClass *RC =
5395 TLI.getRegClassFor(Src.getSimpleValueType());
5396 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5398 SPDescriptor.setGuardReg(Reg);
5399 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5401 Src = getValue(I.getArgOperand(0)); // The guard's value.
5404 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5406 int FI = FuncInfo.StaticAllocaMap[Slot];
5407 MFI->setStackProtectorIndex(FI);
5409 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5411 // Store the stack protector onto the stack.
5412 Res = DAG.getStore(Chain, sdl, Src, FIN,
5413 MachinePointerInfo::getFixedStack(FI),
5419 case Intrinsic::objectsize: {
5420 // If we don't know by now, we're never going to know.
5421 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5423 assert(CI && "Non-constant type in __builtin_object_size?");
5425 SDValue Arg = getValue(I.getCalledValue());
5426 EVT Ty = Arg.getValueType();
5429 Res = DAG.getConstant(-1ULL, Ty);
5431 Res = DAG.getConstant(0, Ty);
5436 case Intrinsic::annotation:
5437 case Intrinsic::ptr_annotation:
5438 // Drop the intrinsic, but forward the value
5439 setValue(&I, getValue(I.getOperand(0)));
5441 case Intrinsic::assume:
5442 case Intrinsic::var_annotation:
5443 // Discard annotate attributes and assumptions
5446 case Intrinsic::init_trampoline: {
5447 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5451 Ops[1] = getValue(I.getArgOperand(0));
5452 Ops[2] = getValue(I.getArgOperand(1));
5453 Ops[3] = getValue(I.getArgOperand(2));
5454 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5455 Ops[5] = DAG.getSrcValue(F);
5457 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5462 case Intrinsic::adjust_trampoline: {
5463 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5465 getValue(I.getArgOperand(0))));
5468 case Intrinsic::gcroot:
5470 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5471 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5473 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5474 GFI->addStackRoot(FI->getIndex(), TypeMap);
5477 case Intrinsic::gcread:
5478 case Intrinsic::gcwrite:
5479 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5480 case Intrinsic::flt_rounds:
5481 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5484 case Intrinsic::expect: {
5485 // Just replace __builtin_expect(exp, c) with EXP.
5486 setValue(&I, getValue(I.getArgOperand(0)));
5490 case Intrinsic::debugtrap:
5491 case Intrinsic::trap: {
5492 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5493 if (TrapFuncName.empty()) {
5494 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5495 ISD::TRAP : ISD::DEBUGTRAP;
5496 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5499 TargetLowering::ArgListTy Args;
5501 TargetLowering::CallLoweringInfo CLI(DAG);
5502 CLI.setDebugLoc(sdl).setChain(getRoot())
5503 .setCallee(CallingConv::C, I.getType(),
5504 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5505 std::move(Args), 0);
5507 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5508 DAG.setRoot(Result.second);
5512 case Intrinsic::uadd_with_overflow:
5513 case Intrinsic::sadd_with_overflow:
5514 case Intrinsic::usub_with_overflow:
5515 case Intrinsic::ssub_with_overflow:
5516 case Intrinsic::umul_with_overflow:
5517 case Intrinsic::smul_with_overflow: {
5519 switch (Intrinsic) {
5520 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5521 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5522 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5523 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5524 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5525 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5526 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5528 SDValue Op1 = getValue(I.getArgOperand(0));
5529 SDValue Op2 = getValue(I.getArgOperand(1));
5531 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5532 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5535 case Intrinsic::prefetch: {
5537 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5539 Ops[1] = getValue(I.getArgOperand(0));
5540 Ops[2] = getValue(I.getArgOperand(1));
5541 Ops[3] = getValue(I.getArgOperand(2));
5542 Ops[4] = getValue(I.getArgOperand(3));
5543 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5544 DAG.getVTList(MVT::Other), Ops,
5545 EVT::getIntegerVT(*Context, 8),
5546 MachinePointerInfo(I.getArgOperand(0)),
5548 false, /* volatile */
5550 rw==1)); /* write */
5553 case Intrinsic::lifetime_start:
5554 case Intrinsic::lifetime_end: {
5555 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5556 // Stack coloring is not enabled in O0, discard region information.
5557 if (TM.getOptLevel() == CodeGenOpt::None)
5560 SmallVector<Value *, 4> Allocas;
5561 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5563 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5564 E = Allocas.end(); Object != E; ++Object) {
5565 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5567 // Could not find an Alloca.
5568 if (!LifetimeObject)
5571 // First check that the Alloca is static, otherwise it won't have a
5572 // valid frame index.
5573 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5574 if (SI == FuncInfo.StaticAllocaMap.end())
5577 int FI = SI->second;
5581 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5582 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5584 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5589 case Intrinsic::invariant_start:
5590 // Discard region information.
5591 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5593 case Intrinsic::invariant_end:
5594 // Discard region information.
5596 case Intrinsic::stackprotectorcheck: {
5597 // Do not actually emit anything for this basic block. Instead we initialize
5598 // the stack protector descriptor and export the guard variable so we can
5599 // access it in FinishBasicBlock.
5600 const BasicBlock *BB = I.getParent();
5601 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5602 ExportFromCurrentBlock(SPDescriptor.getGuard());
5604 // Flush our exports since we are going to process a terminator.
5605 (void)getControlRoot();
5608 case Intrinsic::clear_cache:
5609 return TLI.getClearCacheBuiltinName();
5610 case Intrinsic::donothing:
5613 case Intrinsic::experimental_stackmap: {
5617 case Intrinsic::experimental_patchpoint_void:
5618 case Intrinsic::experimental_patchpoint_i64: {
5619 visitPatchpoint(&I);
5622 case Intrinsic::experimental_gc_statepoint: {
5626 case Intrinsic::experimental_gc_result_int:
5627 case Intrinsic::experimental_gc_result_float:
5628 case Intrinsic::experimental_gc_result_ptr:
5629 case Intrinsic::experimental_gc_result: {
5633 case Intrinsic::experimental_gc_relocate: {
5637 case Intrinsic::instrprof_increment:
5638 llvm_unreachable("instrprof failed to lower an increment");
5640 case Intrinsic::frameallocate: {
5641 MachineFunction &MF = DAG.getMachineFunction();
5642 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5644 // Do the allocation and map it as a normal value.
5645 // FIXME: Maybe we should add this to the alloca map so that we don't have
5646 // to register allocate it?
5647 uint64_t Size = cast<ConstantInt>(I.getArgOperand(0))->getZExtValue();
5648 int Alloc = MF.getFrameInfo()->CreateFrameAllocation(Size);
5649 MVT PtrVT = TLI.getPointerTy(0);
5650 SDValue FIVal = DAG.getFrameIndex(Alloc, PtrVT);
5651 setValue(&I, FIVal);
5653 // Directly emit a FRAME_ALLOC machine instr. Label assignment emission is
5654 // the same on all targets.
5655 MCSymbol *FrameAllocSym =
5656 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(MF.getName());
5657 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5658 TII->get(TargetOpcode::FRAME_ALLOC))
5659 .addSym(FrameAllocSym)
5660 .addFrameIndex(Alloc);
5665 case Intrinsic::framerecover: {
5666 // i8* @llvm.framerecover(i8* %fn, i8* %fp)
5667 MachineFunction &MF = DAG.getMachineFunction();
5668 MVT PtrVT = TLI.getPointerTy(0);
5670 // Get the symbol that defines the frame offset.
5671 Function *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5672 MCSymbol *FrameAllocSym =
5673 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(Fn->getName());
5675 // Create a TargetExternalSymbol for the label to avoid any target lowering
5676 // that would make this PC relative.
5677 StringRef Name = FrameAllocSym->getName();
5678 assert(Name.size() == strlen(Name.data()) && "not null terminated");
5679 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
5681 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
5683 // Add the offset to the FP.
5684 Value *FP = I.getArgOperand(1);
5685 SDValue FPVal = getValue(FP);
5686 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5691 case Intrinsic::eh_begincatch:
5692 case Intrinsic::eh_endcatch:
5693 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5697 std::pair<SDValue, SDValue>
5698 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5699 MachineBasicBlock *LandingPad) {
5700 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5701 MCSymbol *BeginLabel = nullptr;
5704 // Insert a label before the invoke call to mark the try range. This can be
5705 // used to detect deletion of the invoke via the MachineModuleInfo.
5706 BeginLabel = MMI.getContext().CreateTempSymbol();
5708 // For SjLj, keep track of which landing pads go with which invokes
5709 // so as to maintain the ordering of pads in the LSDA.
5710 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5711 if (CallSiteIndex) {
5712 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5713 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5715 // Now that the call site is handled, stop tracking it.
5716 MMI.setCurrentCallSite(0);
5719 // Both PendingLoads and PendingExports must be flushed here;
5720 // this call might not return.
5722 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5724 CLI.setChain(getRoot());
5726 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5727 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5729 assert((CLI.IsTailCall || Result.second.getNode()) &&
5730 "Non-null chain expected with non-tail call!");
5731 assert((Result.second.getNode() || !Result.first.getNode()) &&
5732 "Null value expected with tail call!");
5734 if (!Result.second.getNode()) {
5735 // As a special case, a null chain means that a tail call has been emitted
5736 // and the DAG root is already updated.
5739 // Since there's no actual continuation from this block, nothing can be
5740 // relying on us setting vregs for them.
5741 PendingExports.clear();
5743 DAG.setRoot(Result.second);
5747 // Insert a label at the end of the invoke call to mark the try range. This
5748 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5749 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5750 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5752 // Inform MachineModuleInfo of range.
5753 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5759 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5761 MachineBasicBlock *LandingPad) {
5762 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5763 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5764 Type *RetTy = FTy->getReturnType();
5766 TargetLowering::ArgListTy Args;
5767 TargetLowering::ArgListEntry Entry;
5768 Args.reserve(CS.arg_size());
5770 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5772 const Value *V = *i;
5775 if (V->getType()->isEmptyTy())
5778 SDValue ArgNode = getValue(V);
5779 Entry.Node = ArgNode; Entry.Ty = V->getType();
5781 // Skip the first return-type Attribute to get to params.
5782 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5783 Args.push_back(Entry);
5786 // Check if target-independent constraints permit a tail call here.
5787 // Target-dependent constraints are checked within TLI->LowerCallTo.
5788 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5791 TargetLowering::CallLoweringInfo CLI(DAG);
5792 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5793 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5794 .setTailCall(isTailCall);
5795 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5797 if (Result.first.getNode())
5798 setValue(CS.getInstruction(), Result.first);
5801 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5802 /// value is equal or not-equal to zero.
5803 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5804 for (const User *U : V->users()) {
5805 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5806 if (IC->isEquality())
5807 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5808 if (C->isNullValue())
5810 // Unknown instruction.
5816 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5818 SelectionDAGBuilder &Builder) {
5820 // Check to see if this load can be trivially constant folded, e.g. if the
5821 // input is from a string literal.
5822 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5823 // Cast pointer to the type we really want to load.
5824 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5825 PointerType::getUnqual(LoadTy));
5827 if (const Constant *LoadCst =
5828 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5830 return Builder.getValue(LoadCst);
5833 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5834 // still constant memory, the input chain can be the entry node.
5836 bool ConstantMemory = false;
5838 // Do not serialize (non-volatile) loads of constant memory with anything.
5839 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5840 Root = Builder.DAG.getEntryNode();
5841 ConstantMemory = true;
5843 // Do not serialize non-volatile loads against each other.
5844 Root = Builder.DAG.getRoot();
5847 SDValue Ptr = Builder.getValue(PtrVal);
5848 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5849 Ptr, MachinePointerInfo(PtrVal),
5851 false /*nontemporal*/,
5852 false /*isinvariant*/, 1 /* align=1 */);
5854 if (!ConstantMemory)
5855 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5859 /// processIntegerCallValue - Record the value for an instruction that
5860 /// produces an integer result, converting the type where necessary.
5861 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5864 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5866 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5868 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5869 setValue(&I, Value);
5872 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5873 /// If so, return true and lower it, otherwise return false and it will be
5874 /// lowered like a normal call.
5875 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5876 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5877 if (I.getNumArgOperands() != 3)
5880 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5881 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5882 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5883 !I.getType()->isIntegerTy())
5886 const Value *Size = I.getArgOperand(2);
5887 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5888 if (CSize && CSize->getZExtValue() == 0) {
5889 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5890 setValue(&I, DAG.getConstant(0, CallVT));
5894 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5895 std::pair<SDValue, SDValue> Res =
5896 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5897 getValue(LHS), getValue(RHS), getValue(Size),
5898 MachinePointerInfo(LHS),
5899 MachinePointerInfo(RHS));
5900 if (Res.first.getNode()) {
5901 processIntegerCallValue(I, Res.first, true);
5902 PendingLoads.push_back(Res.second);
5906 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5907 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5908 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5909 bool ActuallyDoIt = true;
5912 switch (CSize->getZExtValue()) {
5914 LoadVT = MVT::Other;
5916 ActuallyDoIt = false;
5920 LoadTy = Type::getInt16Ty(CSize->getContext());
5924 LoadTy = Type::getInt32Ty(CSize->getContext());
5928 LoadTy = Type::getInt64Ty(CSize->getContext());
5932 LoadVT = MVT::v4i32;
5933 LoadTy = Type::getInt32Ty(CSize->getContext());
5934 LoadTy = VectorType::get(LoadTy, 4);
5939 // This turns into unaligned loads. We only do this if the target natively
5940 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5941 // we'll only produce a small number of byte loads.
5943 // Require that we can find a legal MVT, and only do this if the target
5944 // supports unaligned loads of that type. Expanding into byte loads would
5946 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5947 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5948 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5949 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5950 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5951 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5952 // TODO: Check alignment of src and dest ptrs.
5953 if (!TLI.isTypeLegal(LoadVT) ||
5954 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5955 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5956 ActuallyDoIt = false;
5960 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5961 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5963 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5965 processIntegerCallValue(I, Res, false);
5974 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5975 /// form. If so, return true and lower it, otherwise return false and it
5976 /// will be lowered like a normal call.
5977 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5978 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5979 if (I.getNumArgOperands() != 3)
5982 const Value *Src = I.getArgOperand(0);
5983 const Value *Char = I.getArgOperand(1);
5984 const Value *Length = I.getArgOperand(2);
5985 if (!Src->getType()->isPointerTy() ||
5986 !Char->getType()->isIntegerTy() ||
5987 !Length->getType()->isIntegerTy() ||
5988 !I.getType()->isPointerTy())
5991 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5992 std::pair<SDValue, SDValue> Res =
5993 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5994 getValue(Src), getValue(Char), getValue(Length),
5995 MachinePointerInfo(Src));
5996 if (Res.first.getNode()) {
5997 setValue(&I, Res.first);
5998 PendingLoads.push_back(Res.second);
6005 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
6006 /// optimized form. If so, return true and lower it, otherwise return false
6007 /// and it will be lowered like a normal call.
6008 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
6009 // Verify that the prototype makes sense. char *strcpy(char *, char *)
6010 if (I.getNumArgOperands() != 2)
6013 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6014 if (!Arg0->getType()->isPointerTy() ||
6015 !Arg1->getType()->isPointerTy() ||
6016 !I.getType()->isPointerTy())
6019 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6020 std::pair<SDValue, SDValue> Res =
6021 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
6022 getValue(Arg0), getValue(Arg1),
6023 MachinePointerInfo(Arg0),
6024 MachinePointerInfo(Arg1), isStpcpy);
6025 if (Res.first.getNode()) {
6026 setValue(&I, Res.first);
6027 DAG.setRoot(Res.second);
6034 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
6035 /// If so, return true and lower it, otherwise return false and it will be
6036 /// lowered like a normal call.
6037 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
6038 // Verify that the prototype makes sense. int strcmp(void*,void*)
6039 if (I.getNumArgOperands() != 2)
6042 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6043 if (!Arg0->getType()->isPointerTy() ||
6044 !Arg1->getType()->isPointerTy() ||
6045 !I.getType()->isIntegerTy())
6048 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6049 std::pair<SDValue, SDValue> Res =
6050 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
6051 getValue(Arg0), getValue(Arg1),
6052 MachinePointerInfo(Arg0),
6053 MachinePointerInfo(Arg1));
6054 if (Res.first.getNode()) {
6055 processIntegerCallValue(I, Res.first, true);
6056 PendingLoads.push_back(Res.second);
6063 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
6064 /// form. If so, return true and lower it, otherwise return false and it
6065 /// will be lowered like a normal call.
6066 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
6067 // Verify that the prototype makes sense. size_t strlen(char *)
6068 if (I.getNumArgOperands() != 1)
6071 const Value *Arg0 = I.getArgOperand(0);
6072 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
6075 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6076 std::pair<SDValue, SDValue> Res =
6077 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
6078 getValue(Arg0), MachinePointerInfo(Arg0));
6079 if (Res.first.getNode()) {
6080 processIntegerCallValue(I, Res.first, false);
6081 PendingLoads.push_back(Res.second);
6088 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
6089 /// form. If so, return true and lower it, otherwise return false and it
6090 /// will be lowered like a normal call.
6091 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
6092 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
6093 if (I.getNumArgOperands() != 2)
6096 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6097 if (!Arg0->getType()->isPointerTy() ||
6098 !Arg1->getType()->isIntegerTy() ||
6099 !I.getType()->isIntegerTy())
6102 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6103 std::pair<SDValue, SDValue> Res =
6104 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
6105 getValue(Arg0), getValue(Arg1),
6106 MachinePointerInfo(Arg0));
6107 if (Res.first.getNode()) {
6108 processIntegerCallValue(I, Res.first, false);
6109 PendingLoads.push_back(Res.second);
6116 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
6117 /// operation (as expected), translate it to an SDNode with the specified opcode
6118 /// and return true.
6119 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
6121 // Sanity check that it really is a unary floating-point call.
6122 if (I.getNumArgOperands() != 1 ||
6123 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
6124 I.getType() != I.getArgOperand(0)->getType() ||
6125 !I.onlyReadsMemory())
6128 SDValue Tmp = getValue(I.getArgOperand(0));
6129 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
6133 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
6134 /// operation (as expected), translate it to an SDNode with the specified opcode
6135 /// and return true.
6136 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
6138 // Sanity check that it really is a binary floating-point call.
6139 if (I.getNumArgOperands() != 2 ||
6140 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
6141 I.getType() != I.getArgOperand(0)->getType() ||
6142 I.getType() != I.getArgOperand(1)->getType() ||
6143 !I.onlyReadsMemory())
6146 SDValue Tmp0 = getValue(I.getArgOperand(0));
6147 SDValue Tmp1 = getValue(I.getArgOperand(1));
6148 EVT VT = Tmp0.getValueType();
6149 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
6153 void SelectionDAGBuilder::visitCall(const CallInst &I) {
6154 // Handle inline assembly differently.
6155 if (isa<InlineAsm>(I.getCalledValue())) {
6160 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
6161 ComputeUsesVAFloatArgument(I, &MMI);
6163 const char *RenameFn = nullptr;
6164 if (Function *F = I.getCalledFunction()) {
6165 if (F->isDeclaration()) {
6166 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
6167 if (unsigned IID = II->getIntrinsicID(F)) {
6168 RenameFn = visitIntrinsicCall(I, IID);
6173 if (unsigned IID = F->getIntrinsicID()) {
6174 RenameFn = visitIntrinsicCall(I, IID);
6180 // Check for well-known libc/libm calls. If the function is internal, it
6181 // can't be a library call.
6183 if (!F->hasLocalLinkage() && F->hasName() &&
6184 LibInfo->getLibFunc(F->getName(), Func) &&
6185 LibInfo->hasOptimizedCodeGen(Func)) {
6188 case LibFunc::copysign:
6189 case LibFunc::copysignf:
6190 case LibFunc::copysignl:
6191 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
6192 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
6193 I.getType() == I.getArgOperand(0)->getType() &&
6194 I.getType() == I.getArgOperand(1)->getType() &&
6195 I.onlyReadsMemory()) {
6196 SDValue LHS = getValue(I.getArgOperand(0));
6197 SDValue RHS = getValue(I.getArgOperand(1));
6198 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
6199 LHS.getValueType(), LHS, RHS));
6204 case LibFunc::fabsf:
6205 case LibFunc::fabsl:
6206 if (visitUnaryFloatCall(I, ISD::FABS))
6210 case LibFunc::fminf:
6211 case LibFunc::fminl:
6212 if (visitBinaryFloatCall(I, ISD::FMINNUM))
6216 case LibFunc::fmaxf:
6217 case LibFunc::fmaxl:
6218 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
6224 if (visitUnaryFloatCall(I, ISD::FSIN))
6230 if (visitUnaryFloatCall(I, ISD::FCOS))
6234 case LibFunc::sqrtf:
6235 case LibFunc::sqrtl:
6236 case LibFunc::sqrt_finite:
6237 case LibFunc::sqrtf_finite:
6238 case LibFunc::sqrtl_finite:
6239 if (visitUnaryFloatCall(I, ISD::FSQRT))
6242 case LibFunc::floor:
6243 case LibFunc::floorf:
6244 case LibFunc::floorl:
6245 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6248 case LibFunc::nearbyint:
6249 case LibFunc::nearbyintf:
6250 case LibFunc::nearbyintl:
6251 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6255 case LibFunc::ceilf:
6256 case LibFunc::ceill:
6257 if (visitUnaryFloatCall(I, ISD::FCEIL))
6261 case LibFunc::rintf:
6262 case LibFunc::rintl:
6263 if (visitUnaryFloatCall(I, ISD::FRINT))
6266 case LibFunc::round:
6267 case LibFunc::roundf:
6268 case LibFunc::roundl:
6269 if (visitUnaryFloatCall(I, ISD::FROUND))
6272 case LibFunc::trunc:
6273 case LibFunc::truncf:
6274 case LibFunc::truncl:
6275 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6279 case LibFunc::log2f:
6280 case LibFunc::log2l:
6281 if (visitUnaryFloatCall(I, ISD::FLOG2))
6285 case LibFunc::exp2f:
6286 case LibFunc::exp2l:
6287 if (visitUnaryFloatCall(I, ISD::FEXP2))
6290 case LibFunc::memcmp:
6291 if (visitMemCmpCall(I))
6294 case LibFunc::memchr:
6295 if (visitMemChrCall(I))
6298 case LibFunc::strcpy:
6299 if (visitStrCpyCall(I, false))
6302 case LibFunc::stpcpy:
6303 if (visitStrCpyCall(I, true))
6306 case LibFunc::strcmp:
6307 if (visitStrCmpCall(I))
6310 case LibFunc::strlen:
6311 if (visitStrLenCall(I))
6314 case LibFunc::strnlen:
6315 if (visitStrNLenCall(I))
6324 Callee = getValue(I.getCalledValue());
6326 Callee = DAG.getExternalSymbol(RenameFn,
6327 DAG.getTargetLoweringInfo().getPointerTy());
6329 // Check if we can potentially perform a tail call. More detailed checking is
6330 // be done within LowerCallTo, after more information about the call is known.
6331 LowerCallTo(&I, Callee, I.isTailCall());
6336 /// AsmOperandInfo - This contains information for each constraint that we are
6338 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6340 /// CallOperand - If this is the result output operand or a clobber
6341 /// this is null, otherwise it is the incoming operand to the CallInst.
6342 /// This gets modified as the asm is processed.
6343 SDValue CallOperand;
6345 /// AssignedRegs - If this is a register or register class operand, this
6346 /// contains the set of register corresponding to the operand.
6347 RegsForValue AssignedRegs;
6349 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6350 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6353 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6354 /// corresponds to. If there is no Value* for this operand, it returns
6356 EVT getCallOperandValEVT(LLVMContext &Context,
6357 const TargetLowering &TLI,
6358 const DataLayout *DL) const {
6359 if (!CallOperandVal) return MVT::Other;
6361 if (isa<BasicBlock>(CallOperandVal))
6362 return TLI.getPointerTy();
6364 llvm::Type *OpTy = CallOperandVal->getType();
6366 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6367 // If this is an indirect operand, the operand is a pointer to the
6370 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6372 report_fatal_error("Indirect operand for inline asm not a pointer!");
6373 OpTy = PtrTy->getElementType();
6376 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6377 if (StructType *STy = dyn_cast<StructType>(OpTy))
6378 if (STy->getNumElements() == 1)
6379 OpTy = STy->getElementType(0);
6381 // If OpTy is not a single value, it may be a struct/union that we
6382 // can tile with integers.
6383 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6384 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6393 OpTy = IntegerType::get(Context, BitSize);
6398 return TLI.getValueType(OpTy, true);
6402 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6404 } // end anonymous namespace
6406 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6407 /// specified operand. We prefer to assign virtual registers, to allow the
6408 /// register allocator to handle the assignment process. However, if the asm
6409 /// uses features that we can't model on machineinstrs, we have SDISel do the
6410 /// allocation. This produces generally horrible, but correct, code.
6412 /// OpInfo describes the operand.
6414 static void GetRegistersForValue(SelectionDAG &DAG,
6415 const TargetLowering &TLI,
6417 SDISelAsmOperandInfo &OpInfo) {
6418 LLVMContext &Context = *DAG.getContext();
6420 MachineFunction &MF = DAG.getMachineFunction();
6421 SmallVector<unsigned, 4> Regs;
6423 // If this is a constraint for a single physreg, or a constraint for a
6424 // register class, find it.
6425 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6426 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6427 OpInfo.ConstraintCode,
6428 OpInfo.ConstraintVT);
6430 unsigned NumRegs = 1;
6431 if (OpInfo.ConstraintVT != MVT::Other) {
6432 // If this is a FP input in an integer register (or visa versa) insert a bit
6433 // cast of the input value. More generally, handle any case where the input
6434 // value disagrees with the register class we plan to stick this in.
6435 if (OpInfo.Type == InlineAsm::isInput &&
6436 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6437 // Try to convert to the first EVT that the reg class contains. If the
6438 // types are identical size, use a bitcast to convert (e.g. two differing
6440 MVT RegVT = *PhysReg.second->vt_begin();
6441 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6442 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6443 RegVT, OpInfo.CallOperand);
6444 OpInfo.ConstraintVT = RegVT;
6445 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6446 // If the input is a FP value and we want it in FP registers, do a
6447 // bitcast to the corresponding integer type. This turns an f64 value
6448 // into i64, which can be passed with two i32 values on a 32-bit
6450 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6451 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6452 RegVT, OpInfo.CallOperand);
6453 OpInfo.ConstraintVT = RegVT;
6457 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6461 EVT ValueVT = OpInfo.ConstraintVT;
6463 // If this is a constraint for a specific physical register, like {r17},
6465 if (unsigned AssignedReg = PhysReg.first) {
6466 const TargetRegisterClass *RC = PhysReg.second;
6467 if (OpInfo.ConstraintVT == MVT::Other)
6468 ValueVT = *RC->vt_begin();
6470 // Get the actual register value type. This is important, because the user
6471 // may have asked for (e.g.) the AX register in i32 type. We need to
6472 // remember that AX is actually i16 to get the right extension.
6473 RegVT = *RC->vt_begin();
6475 // This is a explicit reference to a physical register.
6476 Regs.push_back(AssignedReg);
6478 // If this is an expanded reference, add the rest of the regs to Regs.
6480 TargetRegisterClass::iterator I = RC->begin();
6481 for (; *I != AssignedReg; ++I)
6482 assert(I != RC->end() && "Didn't find reg!");
6484 // Already added the first reg.
6486 for (; NumRegs; --NumRegs, ++I) {
6487 assert(I != RC->end() && "Ran out of registers to allocate!");
6492 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6496 // Otherwise, if this was a reference to an LLVM register class, create vregs
6497 // for this reference.
6498 if (const TargetRegisterClass *RC = PhysReg.second) {
6499 RegVT = *RC->vt_begin();
6500 if (OpInfo.ConstraintVT == MVT::Other)
6503 // Create the appropriate number of virtual registers.
6504 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6505 for (; NumRegs; --NumRegs)
6506 Regs.push_back(RegInfo.createVirtualRegister(RC));
6508 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6512 // Otherwise, we couldn't allocate enough registers for this.
6515 /// visitInlineAsm - Handle a call to an InlineAsm object.
6517 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6518 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6520 /// ConstraintOperands - Information about all of the constraints.
6521 SDISelAsmOperandInfoVector ConstraintOperands;
6523 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6524 TargetLowering::AsmOperandInfoVector TargetConstraints =
6525 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
6527 bool hasMemory = false;
6529 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6530 unsigned ResNo = 0; // ResNo - The result number of the next output.
6531 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6532 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6533 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6535 MVT OpVT = MVT::Other;
6537 // Compute the value type for each operand.
6538 switch (OpInfo.Type) {
6539 case InlineAsm::isOutput:
6540 // Indirect outputs just consume an argument.
6541 if (OpInfo.isIndirect) {
6542 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6546 // The return value of the call is this value. As such, there is no
6547 // corresponding argument.
6548 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6549 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6550 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
6552 assert(ResNo == 0 && "Asm only has one result!");
6553 OpVT = TLI.getSimpleValueType(CS.getType());
6557 case InlineAsm::isInput:
6558 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6560 case InlineAsm::isClobber:
6565 // If this is an input or an indirect output, process the call argument.
6566 // BasicBlocks are labels, currently appearing only in asm's.
6567 if (OpInfo.CallOperandVal) {
6568 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6569 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6571 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6575 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
6578 OpInfo.ConstraintVT = OpVT;
6580 // Indirect operand accesses access memory.
6581 if (OpInfo.isIndirect)
6584 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6585 TargetLowering::ConstraintType
6586 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6587 if (CType == TargetLowering::C_Memory) {
6595 SDValue Chain, Flag;
6597 // We won't need to flush pending loads if this asm doesn't touch
6598 // memory and is nonvolatile.
6599 if (hasMemory || IA->hasSideEffects())
6602 Chain = DAG.getRoot();
6604 // Second pass over the constraints: compute which constraint option to use
6605 // and assign registers to constraints that want a specific physreg.
6606 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6607 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6609 // If this is an output operand with a matching input operand, look up the
6610 // matching input. If their types mismatch, e.g. one is an integer, the
6611 // other is floating point, or their sizes are different, flag it as an
6613 if (OpInfo.hasMatchingInput()) {
6614 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6616 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6617 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6618 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6619 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6620 OpInfo.ConstraintVT);
6621 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6622 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6623 Input.ConstraintVT);
6624 if ((OpInfo.ConstraintVT.isInteger() !=
6625 Input.ConstraintVT.isInteger()) ||
6626 (MatchRC.second != InputRC.second)) {
6627 report_fatal_error("Unsupported asm: input constraint"
6628 " with a matching output constraint of"
6629 " incompatible type!");
6631 Input.ConstraintVT = OpInfo.ConstraintVT;
6635 // Compute the constraint code and ConstraintType to use.
6636 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6638 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6639 OpInfo.Type == InlineAsm::isClobber)
6642 // If this is a memory input, and if the operand is not indirect, do what we
6643 // need to to provide an address for the memory input.
6644 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6645 !OpInfo.isIndirect) {
6646 assert((OpInfo.isMultipleAlternative ||
6647 (OpInfo.Type == InlineAsm::isInput)) &&
6648 "Can only indirectify direct input operands!");
6650 // Memory operands really want the address of the value. If we don't have
6651 // an indirect input, put it in the constpool if we can, otherwise spill
6652 // it to a stack slot.
6653 // TODO: This isn't quite right. We need to handle these according to
6654 // the addressing mode that the constraint wants. Also, this may take
6655 // an additional register for the computation and we don't want that
6658 // If the operand is a float, integer, or vector constant, spill to a
6659 // constant pool entry to get its address.
6660 const Value *OpVal = OpInfo.CallOperandVal;
6661 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6662 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6663 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6664 TLI.getPointerTy());
6666 // Otherwise, create a stack slot and emit a store to it before the
6668 Type *Ty = OpVal->getType();
6669 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
6670 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
6671 MachineFunction &MF = DAG.getMachineFunction();
6672 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6673 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6674 Chain = DAG.getStore(Chain, getCurSDLoc(),
6675 OpInfo.CallOperand, StackSlot,
6676 MachinePointerInfo::getFixedStack(SSFI),
6678 OpInfo.CallOperand = StackSlot;
6681 // There is no longer a Value* corresponding to this operand.
6682 OpInfo.CallOperandVal = nullptr;
6684 // It is now an indirect operand.
6685 OpInfo.isIndirect = true;
6688 // If this constraint is for a specific register, allocate it before
6690 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6691 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6694 // Second pass - Loop over all of the operands, assigning virtual or physregs
6695 // to register class operands.
6696 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6697 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6699 // C_Register operands have already been allocated, Other/Memory don't need
6701 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6702 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6705 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6706 std::vector<SDValue> AsmNodeOperands;
6707 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6708 AsmNodeOperands.push_back(
6709 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6710 TLI.getPointerTy()));
6712 // If we have a !srcloc metadata node associated with it, we want to attach
6713 // this to the ultimately generated inline asm machineinstr. To do this, we
6714 // pass in the third operand as this (potentially null) inline asm MDNode.
6715 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6716 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6718 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6719 // bits as operand 3.
6720 unsigned ExtraInfo = 0;
6721 if (IA->hasSideEffects())
6722 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6723 if (IA->isAlignStack())
6724 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6725 // Set the asm dialect.
6726 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6728 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6729 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6730 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6732 // Compute the constraint code and ConstraintType to use.
6733 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6735 // Ideally, we would only check against memory constraints. However, the
6736 // meaning of an other constraint can be target-specific and we can't easily
6737 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6738 // for other constriants as well.
6739 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6740 OpInfo.ConstraintType == TargetLowering::C_Other) {
6741 if (OpInfo.Type == InlineAsm::isInput)
6742 ExtraInfo |= InlineAsm::Extra_MayLoad;
6743 else if (OpInfo.Type == InlineAsm::isOutput)
6744 ExtraInfo |= InlineAsm::Extra_MayStore;
6745 else if (OpInfo.Type == InlineAsm::isClobber)
6746 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6750 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6751 TLI.getPointerTy()));
6753 // Loop over all of the inputs, copying the operand values into the
6754 // appropriate registers and processing the output regs.
6755 RegsForValue RetValRegs;
6757 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6758 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6760 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6761 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6763 switch (OpInfo.Type) {
6764 case InlineAsm::isOutput: {
6765 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6766 OpInfo.ConstraintType != TargetLowering::C_Register) {
6767 // Memory output, or 'other' output (e.g. 'X' constraint).
6768 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6770 // Add information to the INLINEASM node to know about this output.
6771 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6772 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6773 TLI.getPointerTy()));
6774 AsmNodeOperands.push_back(OpInfo.CallOperand);
6778 // Otherwise, this is a register or register class output.
6780 // Copy the output from the appropriate register. Find a register that
6782 if (OpInfo.AssignedRegs.Regs.empty()) {
6783 LLVMContext &Ctx = *DAG.getContext();
6784 Ctx.emitError(CS.getInstruction(),
6785 "couldn't allocate output register for constraint '" +
6786 Twine(OpInfo.ConstraintCode) + "'");
6790 // If this is an indirect operand, store through the pointer after the
6792 if (OpInfo.isIndirect) {
6793 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6794 OpInfo.CallOperandVal));
6796 // This is the result value of the call.
6797 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6798 // Concatenate this output onto the outputs list.
6799 RetValRegs.append(OpInfo.AssignedRegs);
6802 // Add information to the INLINEASM node to know that this register is
6805 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6806 ? InlineAsm::Kind_RegDefEarlyClobber
6807 : InlineAsm::Kind_RegDef,
6808 false, 0, DAG, AsmNodeOperands);
6811 case InlineAsm::isInput: {
6812 SDValue InOperandVal = OpInfo.CallOperand;
6814 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6815 // If this is required to match an output register we have already set,
6816 // just use its register.
6817 unsigned OperandNo = OpInfo.getMatchedOperand();
6819 // Scan until we find the definition we already emitted of this operand.
6820 // When we find it, create a RegsForValue operand.
6821 unsigned CurOp = InlineAsm::Op_FirstOperand;
6822 for (; OperandNo; --OperandNo) {
6823 // Advance to the next operand.
6825 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6826 assert((InlineAsm::isRegDefKind(OpFlag) ||
6827 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6828 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6829 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6833 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6834 if (InlineAsm::isRegDefKind(OpFlag) ||
6835 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6836 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6837 if (OpInfo.isIndirect) {
6838 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6839 LLVMContext &Ctx = *DAG.getContext();
6840 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6841 " don't know how to handle tied "
6842 "indirect register inputs");
6846 RegsForValue MatchedRegs;
6847 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6848 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6849 MatchedRegs.RegVTs.push_back(RegVT);
6850 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6851 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6853 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6854 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6856 LLVMContext &Ctx = *DAG.getContext();
6857 Ctx.emitError(CS.getInstruction(),
6858 "inline asm error: This value"
6859 " type register class is not natively supported!");
6863 // Use the produced MatchedRegs object to
6864 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6865 Chain, &Flag, CS.getInstruction());
6866 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6867 true, OpInfo.getMatchedOperand(),
6868 DAG, AsmNodeOperands);
6872 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6873 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6874 "Unexpected number of operands");
6875 // Add information to the INLINEASM node to know about this input.
6876 // See InlineAsm.h isUseOperandTiedToDef.
6877 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6878 OpInfo.getMatchedOperand());
6879 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6880 TLI.getPointerTy()));
6881 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6885 // Treat indirect 'X' constraint as memory.
6886 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6888 OpInfo.ConstraintType = TargetLowering::C_Memory;
6890 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6891 std::vector<SDValue> Ops;
6892 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6895 LLVMContext &Ctx = *DAG.getContext();
6896 Ctx.emitError(CS.getInstruction(),
6897 "invalid operand for inline asm constraint '" +
6898 Twine(OpInfo.ConstraintCode) + "'");
6902 // Add information to the INLINEASM node to know about this input.
6903 unsigned ResOpType =
6904 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6905 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6906 TLI.getPointerTy()));
6907 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6911 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6912 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6913 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6914 "Memory operands expect pointer values");
6916 // Add information to the INLINEASM node to know about this input.
6917 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6918 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6919 TLI.getPointerTy()));
6920 AsmNodeOperands.push_back(InOperandVal);
6924 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6925 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6926 "Unknown constraint type!");
6928 // TODO: Support this.
6929 if (OpInfo.isIndirect) {
6930 LLVMContext &Ctx = *DAG.getContext();
6931 Ctx.emitError(CS.getInstruction(),
6932 "Don't know how to handle indirect register inputs yet "
6933 "for constraint '" +
6934 Twine(OpInfo.ConstraintCode) + "'");
6938 // Copy the input into the appropriate registers.
6939 if (OpInfo.AssignedRegs.Regs.empty()) {
6940 LLVMContext &Ctx = *DAG.getContext();
6941 Ctx.emitError(CS.getInstruction(),
6942 "couldn't allocate input reg for constraint '" +
6943 Twine(OpInfo.ConstraintCode) + "'");
6947 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6948 Chain, &Flag, CS.getInstruction());
6950 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6951 DAG, AsmNodeOperands);
6954 case InlineAsm::isClobber: {
6955 // Add the clobbered value to the operand list, so that the register
6956 // allocator is aware that the physreg got clobbered.
6957 if (!OpInfo.AssignedRegs.Regs.empty())
6958 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6966 // Finish up input operands. Set the input chain and add the flag last.
6967 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6968 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6970 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6971 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6972 Flag = Chain.getValue(1);
6974 // If this asm returns a register value, copy the result from that register
6975 // and set it as the value of the call.
6976 if (!RetValRegs.Regs.empty()) {
6977 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6978 Chain, &Flag, CS.getInstruction());
6980 // FIXME: Why don't we do this for inline asms with MRVs?
6981 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6982 EVT ResultType = TLI.getValueType(CS.getType());
6984 // If any of the results of the inline asm is a vector, it may have the
6985 // wrong width/num elts. This can happen for register classes that can
6986 // contain multiple different value types. The preg or vreg allocated may
6987 // not have the same VT as was expected. Convert it to the right type
6988 // with bit_convert.
6989 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6990 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6993 } else if (ResultType != Val.getValueType() &&
6994 ResultType.isInteger() && Val.getValueType().isInteger()) {
6995 // If a result value was tied to an input value, the computed result may
6996 // have a wider width than the expected result. Extract the relevant
6998 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
7001 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
7004 setValue(CS.getInstruction(), Val);
7005 // Don't need to use this as a chain in this case.
7006 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
7010 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
7012 // Process indirect outputs, first output all of the flagged copies out of
7014 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
7015 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
7016 const Value *Ptr = IndirectStoresToEmit[i].second;
7017 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
7019 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
7022 // Emit the non-flagged stores from the physregs.
7023 SmallVector<SDValue, 8> OutChains;
7024 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
7025 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
7026 StoresToEmit[i].first,
7027 getValue(StoresToEmit[i].second),
7028 MachinePointerInfo(StoresToEmit[i].second),
7030 OutChains.push_back(Val);
7033 if (!OutChains.empty())
7034 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
7039 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
7040 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
7041 MVT::Other, getRoot(),
7042 getValue(I.getArgOperand(0)),
7043 DAG.getSrcValue(I.getArgOperand(0))));
7046 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
7047 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7048 const DataLayout &DL = *TLI.getDataLayout();
7049 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
7050 getRoot(), getValue(I.getOperand(0)),
7051 DAG.getSrcValue(I.getOperand(0)),
7052 DL.getABITypeAlignment(I.getType()));
7054 DAG.setRoot(V.getValue(1));
7057 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
7058 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
7059 MVT::Other, getRoot(),
7060 getValue(I.getArgOperand(0)),
7061 DAG.getSrcValue(I.getArgOperand(0))));
7064 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
7065 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
7066 MVT::Other, getRoot(),
7067 getValue(I.getArgOperand(0)),
7068 getValue(I.getArgOperand(1)),
7069 DAG.getSrcValue(I.getArgOperand(0)),
7070 DAG.getSrcValue(I.getArgOperand(1))));
7073 /// \brief Lower an argument list according to the target calling convention.
7075 /// \return A tuple of <return-value, token-chain>
7077 /// This is a helper for lowering intrinsics that follow a target calling
7078 /// convention or require stack pointer adjustment. Only a subset of the
7079 /// intrinsic's operands need to participate in the calling convention.
7080 std::pair<SDValue, SDValue>
7081 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
7082 unsigned NumArgs, SDValue Callee,
7084 MachineBasicBlock *LandingPad,
7085 bool IsPatchPoint) {
7086 TargetLowering::ArgListTy Args;
7087 Args.reserve(NumArgs);
7089 // Populate the argument list.
7090 // Attributes for args start at offset 1, after the return attribute.
7091 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
7092 ArgI != ArgE; ++ArgI) {
7093 const Value *V = CS->getOperand(ArgI);
7095 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
7097 TargetLowering::ArgListEntry Entry;
7098 Entry.Node = getValue(V);
7099 Entry.Ty = V->getType();
7100 Entry.setAttributes(&CS, AttrI);
7101 Args.push_back(Entry);
7104 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
7105 TargetLowering::CallLoweringInfo CLI(DAG);
7106 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
7107 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
7108 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
7110 return lowerInvokable(CLI, LandingPad);
7113 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
7114 /// or patchpoint target node's operand list.
7116 /// Constants are converted to TargetConstants purely as an optimization to
7117 /// avoid constant materialization and register allocation.
7119 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
7120 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
7121 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
7122 /// address materialization and register allocation, but may also be required
7123 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
7124 /// alloca in the entry block, then the runtime may assume that the alloca's
7125 /// StackMap location can be read immediately after compilation and that the
7126 /// location is valid at any point during execution (this is similar to the
7127 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
7128 /// only available in a register, then the runtime would need to trap when
7129 /// execution reaches the StackMap in order to read the alloca's location.
7130 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
7131 SmallVectorImpl<SDValue> &Ops,
7132 SelectionDAGBuilder &Builder) {
7133 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
7134 SDValue OpVal = Builder.getValue(CS.getArgument(i));
7135 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
7137 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
7139 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
7140 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
7141 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
7143 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
7145 Ops.push_back(OpVal);
7149 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
7150 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
7151 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
7152 // [live variables...])
7154 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
7156 SDValue Chain, InFlag, Callee, NullPtr;
7157 SmallVector<SDValue, 32> Ops;
7159 SDLoc DL = getCurSDLoc();
7160 Callee = getValue(CI.getCalledValue());
7161 NullPtr = DAG.getIntPtrConstant(0, true);
7163 // The stackmap intrinsic only records the live variables (the arguemnts
7164 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
7165 // intrinsic, this won't be lowered to a function call. This means we don't
7166 // have to worry about calling conventions and target specific lowering code.
7167 // Instead we perform the call lowering right here.
7169 // chain, flag = CALLSEQ_START(chain, 0)
7170 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
7171 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
7173 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
7174 InFlag = Chain.getValue(1);
7176 // Add the <id> and <numBytes> constants.
7177 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7178 Ops.push_back(DAG.getTargetConstant(
7179 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7180 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7181 Ops.push_back(DAG.getTargetConstant(
7182 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7184 // Push live variables for the stack map.
7185 addStackMapLiveVars(&CI, 2, Ops, *this);
7187 // We are not pushing any register mask info here on the operands list,
7188 // because the stackmap doesn't clobber anything.
7190 // Push the chain and the glue flag.
7191 Ops.push_back(Chain);
7192 Ops.push_back(InFlag);
7194 // Create the STACKMAP node.
7195 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7196 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
7197 Chain = SDValue(SM, 0);
7198 InFlag = Chain.getValue(1);
7200 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
7202 // Stackmaps don't generate values, so nothing goes into the NodeMap.
7204 // Set the root to the target-lowered call chain.
7207 // Inform the Frame Information that we have a stackmap in this function.
7208 FuncInfo.MF->getFrameInfo()->setHasStackMap();
7211 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
7212 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
7213 MachineBasicBlock *LandingPad) {
7214 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
7219 // [live variables...])
7221 CallingConv::ID CC = CS.getCallingConv();
7222 bool IsAnyRegCC = CC == CallingConv::AnyReg;
7223 bool HasDef = !CS->getType()->isVoidTy();
7224 SDValue Callee = getValue(CS->getOperand(2)); // <target>
7226 // Get the real number of arguments participating in the call <numArgs>
7227 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
7228 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
7230 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
7231 // Intrinsics include all meta-operands up to but not including CC.
7232 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7233 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
7234 "Not enough arguments provided to the patchpoint intrinsic");
7236 // For AnyRegCC the arguments are lowered later on manually.
7237 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
7238 std::pair<SDValue, SDValue> Result =
7239 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
7242 SDNode *CallEnd = Result.second.getNode();
7243 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7244 CallEnd = CallEnd->getOperand(0).getNode();
7246 /// Get a call instruction from the call sequence chain.
7247 /// Tail calls are not allowed.
7248 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7249 "Expected a callseq node.");
7250 SDNode *Call = CallEnd->getOperand(0).getNode();
7251 bool HasGlue = Call->getGluedNode();
7253 // Replace the target specific call node with the patchable intrinsic.
7254 SmallVector<SDValue, 8> Ops;
7256 // Add the <id> and <numBytes> constants.
7257 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
7258 Ops.push_back(DAG.getTargetConstant(
7259 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7260 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
7261 Ops.push_back(DAG.getTargetConstant(
7262 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7264 // Assume that the Callee is a constant address.
7265 // FIXME: handle function symbols in the future.
7267 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7268 /*isTarget=*/true));
7270 // Adjust <numArgs> to account for any arguments that have been passed on the
7272 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7273 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
7274 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
7275 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7277 // Add the calling convention
7278 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7280 // Add the arguments we omitted previously. The register allocator should
7281 // place these in any free register.
7283 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7284 Ops.push_back(getValue(CS.getArgument(i)));
7286 // Push the arguments from the call instruction up to the register mask.
7287 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
7288 Ops.append(Call->op_begin() + 2, e);
7290 // Push live variables for the stack map.
7291 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this);
7293 // Push the register mask info.
7295 Ops.push_back(*(Call->op_end()-2));
7297 Ops.push_back(*(Call->op_end()-1));
7299 // Push the chain (this is originally the first operand of the call, but
7300 // becomes now the last or second to last operand).
7301 Ops.push_back(*(Call->op_begin()));
7303 // Push the glue flag (last operand).
7305 Ops.push_back(*(Call->op_end()-1));
7308 if (IsAnyRegCC && HasDef) {
7309 // Create the return types based on the intrinsic definition
7310 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7311 SmallVector<EVT, 3> ValueVTs;
7312 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
7313 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7315 // There is always a chain and a glue type at the end
7316 ValueVTs.push_back(MVT::Other);
7317 ValueVTs.push_back(MVT::Glue);
7318 NodeTys = DAG.getVTList(ValueVTs);
7320 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7322 // Replace the target specific call node with a PATCHPOINT node.
7323 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7324 getCurSDLoc(), NodeTys, Ops);
7326 // Update the NodeMap.
7329 setValue(CS.getInstruction(), SDValue(MN, 0));
7331 setValue(CS.getInstruction(), Result.first);
7334 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7335 // call sequence. Furthermore the location of the chain and glue can change
7336 // when the AnyReg calling convention is used and the intrinsic returns a
7338 if (IsAnyRegCC && HasDef) {
7339 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7340 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7341 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7343 DAG.ReplaceAllUsesWith(Call, MN);
7344 DAG.DeleteNode(Call);
7346 // Inform the Frame Information that we have a patchpoint in this function.
7347 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7350 /// Returns an AttributeSet representing the attributes applied to the return
7351 /// value of the given call.
7352 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7353 SmallVector<Attribute::AttrKind, 2> Attrs;
7355 Attrs.push_back(Attribute::SExt);
7357 Attrs.push_back(Attribute::ZExt);
7359 Attrs.push_back(Attribute::InReg);
7361 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7365 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7366 /// implementation, which just calls LowerCall.
7367 /// FIXME: When all targets are
7368 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7369 std::pair<SDValue, SDValue>
7370 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7371 // Handle the incoming return values from the call.
7373 Type *OrigRetTy = CLI.RetTy;
7374 SmallVector<EVT, 4> RetTys;
7375 SmallVector<uint64_t, 4> Offsets;
7376 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7378 SmallVector<ISD::OutputArg, 4> Outs;
7379 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7381 bool CanLowerReturn =
7382 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7383 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7385 SDValue DemoteStackSlot;
7386 int DemoteStackIdx = -100;
7387 if (!CanLowerReturn) {
7388 // FIXME: equivalent assert?
7389 // assert(!CS.hasInAllocaArgument() &&
7390 // "sret demotion is incompatible with inalloca");
7391 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7392 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7393 MachineFunction &MF = CLI.DAG.getMachineFunction();
7394 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7395 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7397 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7399 Entry.Node = DemoteStackSlot;
7400 Entry.Ty = StackSlotPtrType;
7401 Entry.isSExt = false;
7402 Entry.isZExt = false;
7403 Entry.isInReg = false;
7404 Entry.isSRet = true;
7405 Entry.isNest = false;
7406 Entry.isByVal = false;
7407 Entry.isReturned = false;
7408 Entry.Alignment = Align;
7409 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7410 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7412 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7414 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7415 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7416 for (unsigned i = 0; i != NumRegs; ++i) {
7417 ISD::InputArg MyFlags;
7418 MyFlags.VT = RegisterVT;
7420 MyFlags.Used = CLI.IsReturnValueUsed;
7422 MyFlags.Flags.setSExt();
7424 MyFlags.Flags.setZExt();
7426 MyFlags.Flags.setInReg();
7427 CLI.Ins.push_back(MyFlags);
7432 // Handle all of the outgoing arguments.
7434 CLI.OutVals.clear();
7435 ArgListTy &Args = CLI.getArgs();
7436 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7437 SmallVector<EVT, 4> ValueVTs;
7438 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7439 Type *FinalType = Args[i].Ty;
7440 if (Args[i].isByVal)
7441 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7442 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7443 FinalType, CLI.CallConv, CLI.IsVarArg);
7444 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7446 EVT VT = ValueVTs[Value];
7447 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7448 SDValue Op = SDValue(Args[i].Node.getNode(),
7449 Args[i].Node.getResNo() + Value);
7450 ISD::ArgFlagsTy Flags;
7451 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7457 if (Args[i].isInReg)
7461 if (Args[i].isByVal)
7463 if (Args[i].isInAlloca) {
7464 Flags.setInAlloca();
7465 // Set the byval flag for CCAssignFn callbacks that don't know about
7466 // inalloca. This way we can know how many bytes we should've allocated
7467 // and how many bytes a callee cleanup function will pop. If we port
7468 // inalloca to more targets, we'll have to add custom inalloca handling
7469 // in the various CC lowering callbacks.
7472 if (Args[i].isByVal || Args[i].isInAlloca) {
7473 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7474 Type *ElementTy = Ty->getElementType();
7475 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7476 // For ByVal, alignment should come from FE. BE will guess if this
7477 // info is not there but there are cases it cannot get right.
7478 unsigned FrameAlign;
7479 if (Args[i].Alignment)
7480 FrameAlign = Args[i].Alignment;
7482 FrameAlign = getByValTypeAlignment(ElementTy);
7483 Flags.setByValAlign(FrameAlign);
7488 Flags.setInConsecutiveRegs();
7489 Flags.setOrigAlign(OriginalAlignment);
7491 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7492 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7493 SmallVector<SDValue, 4> Parts(NumParts);
7494 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7497 ExtendKind = ISD::SIGN_EXTEND;
7498 else if (Args[i].isZExt)
7499 ExtendKind = ISD::ZERO_EXTEND;
7501 // Conservatively only handle 'returned' on non-vectors for now
7502 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7503 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7504 "unexpected use of 'returned'");
7505 // Before passing 'returned' to the target lowering code, ensure that
7506 // either the register MVT and the actual EVT are the same size or that
7507 // the return value and argument are extended in the same way; in these
7508 // cases it's safe to pass the argument register value unchanged as the
7509 // return register value (although it's at the target's option whether
7511 // TODO: allow code generation to take advantage of partially preserved
7512 // registers rather than clobbering the entire register when the
7513 // parameter extension method is not compatible with the return
7515 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7516 (ExtendKind != ISD::ANY_EXTEND &&
7517 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7518 Flags.setReturned();
7521 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7522 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7524 for (unsigned j = 0; j != NumParts; ++j) {
7525 // if it isn't first piece, alignment must be 1
7526 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7527 i < CLI.NumFixedArgs,
7528 i, j*Parts[j].getValueType().getStoreSize());
7529 if (NumParts > 1 && j == 0)
7530 MyFlags.Flags.setSplit();
7532 MyFlags.Flags.setOrigAlign(1);
7534 CLI.Outs.push_back(MyFlags);
7535 CLI.OutVals.push_back(Parts[j]);
7538 if (NeedsRegBlock && Value == NumValues - 1)
7539 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7543 SmallVector<SDValue, 4> InVals;
7544 CLI.Chain = LowerCall(CLI, InVals);
7546 // Verify that the target's LowerCall behaved as expected.
7547 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7548 "LowerCall didn't return a valid chain!");
7549 assert((!CLI.IsTailCall || InVals.empty()) &&
7550 "LowerCall emitted a return value for a tail call!");
7551 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7552 "LowerCall didn't emit the correct number of values!");
7554 // For a tail call, the return value is merely live-out and there aren't
7555 // any nodes in the DAG representing it. Return a special value to
7556 // indicate that a tail call has been emitted and no more Instructions
7557 // should be processed in the current block.
7558 if (CLI.IsTailCall) {
7559 CLI.DAG.setRoot(CLI.Chain);
7560 return std::make_pair(SDValue(), SDValue());
7563 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7564 assert(InVals[i].getNode() &&
7565 "LowerCall emitted a null value!");
7566 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7567 "LowerCall emitted a value with the wrong type!");
7570 SmallVector<SDValue, 4> ReturnValues;
7571 if (!CanLowerReturn) {
7572 // The instruction result is the result of loading from the
7573 // hidden sret parameter.
7574 SmallVector<EVT, 1> PVTs;
7575 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7577 ComputeValueVTs(*this, PtrRetTy, PVTs);
7578 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7579 EVT PtrVT = PVTs[0];
7581 unsigned NumValues = RetTys.size();
7582 ReturnValues.resize(NumValues);
7583 SmallVector<SDValue, 4> Chains(NumValues);
7585 for (unsigned i = 0; i < NumValues; ++i) {
7586 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7587 CLI.DAG.getConstant(Offsets[i], PtrVT));
7588 SDValue L = CLI.DAG.getLoad(
7589 RetTys[i], CLI.DL, CLI.Chain, Add,
7590 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7592 ReturnValues[i] = L;
7593 Chains[i] = L.getValue(1);
7596 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7598 // Collect the legal value parts into potentially illegal values
7599 // that correspond to the original function's return values.
7600 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7602 AssertOp = ISD::AssertSext;
7603 else if (CLI.RetZExt)
7604 AssertOp = ISD::AssertZext;
7605 unsigned CurReg = 0;
7606 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7608 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7609 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7611 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7612 NumRegs, RegisterVT, VT, nullptr,
7617 // For a function returning void, there is no return value. We can't create
7618 // such a node, so we just return a null return value in that case. In
7619 // that case, nothing will actually look at the value.
7620 if (ReturnValues.empty())
7621 return std::make_pair(SDValue(), CLI.Chain);
7624 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7625 CLI.DAG.getVTList(RetTys), ReturnValues);
7626 return std::make_pair(Res, CLI.Chain);
7629 void TargetLowering::LowerOperationWrapper(SDNode *N,
7630 SmallVectorImpl<SDValue> &Results,
7631 SelectionDAG &DAG) const {
7632 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7634 Results.push_back(Res);
7637 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7638 llvm_unreachable("LowerOperation not implemented for this target!");
7642 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7643 SDValue Op = getNonRegisterValue(V);
7644 assert((Op.getOpcode() != ISD::CopyFromReg ||
7645 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7646 "Copy from a reg to the same reg!");
7647 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7650 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7651 SDValue Chain = DAG.getEntryNode();
7653 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7654 FuncInfo.PreferredExtendType.end())
7656 : FuncInfo.PreferredExtendType[V];
7657 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7658 PendingExports.push_back(Chain);
7661 #include "llvm/CodeGen/SelectionDAGISel.h"
7663 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7664 /// entry block, return true. This includes arguments used by switches, since
7665 /// the switch may expand into multiple basic blocks.
7666 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7667 // With FastISel active, we may be splitting blocks, so force creation
7668 // of virtual registers for all non-dead arguments.
7670 return A->use_empty();
7672 const BasicBlock *Entry = A->getParent()->begin();
7673 for (const User *U : A->users())
7674 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7675 return false; // Use not in entry block.
7680 void SelectionDAGISel::LowerArguments(const Function &F) {
7681 SelectionDAG &DAG = SDB->DAG;
7682 SDLoc dl = SDB->getCurSDLoc();
7683 const DataLayout *DL = TLI->getDataLayout();
7684 SmallVector<ISD::InputArg, 16> Ins;
7686 if (!FuncInfo->CanLowerReturn) {
7687 // Put in an sret pointer parameter before all the other parameters.
7688 SmallVector<EVT, 1> ValueVTs;
7689 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7691 // NOTE: Assuming that a pointer will never break down to more than one VT
7693 ISD::ArgFlagsTy Flags;
7695 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7696 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7697 ISD::InputArg::NoArgIndex, 0);
7698 Ins.push_back(RetArg);
7701 // Set up the incoming argument description vector.
7703 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7704 I != E; ++I, ++Idx) {
7705 SmallVector<EVT, 4> ValueVTs;
7706 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7707 bool isArgValueUsed = !I->use_empty();
7708 unsigned PartBase = 0;
7709 Type *FinalType = I->getType();
7710 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7711 FinalType = cast<PointerType>(FinalType)->getElementType();
7712 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7713 FinalType, F.getCallingConv(), F.isVarArg());
7714 for (unsigned Value = 0, NumValues = ValueVTs.size();
7715 Value != NumValues; ++Value) {
7716 EVT VT = ValueVTs[Value];
7717 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7718 ISD::ArgFlagsTy Flags;
7719 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7721 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7723 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7725 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7727 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7729 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7731 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7732 Flags.setInAlloca();
7733 // Set the byval flag for CCAssignFn callbacks that don't know about
7734 // inalloca. This way we can know how many bytes we should've allocated
7735 // and how many bytes a callee cleanup function will pop. If we port
7736 // inalloca to more targets, we'll have to add custom inalloca handling
7737 // in the various CC lowering callbacks.
7740 if (Flags.isByVal() || Flags.isInAlloca()) {
7741 PointerType *Ty = cast<PointerType>(I->getType());
7742 Type *ElementTy = Ty->getElementType();
7743 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7744 // For ByVal, alignment should be passed from FE. BE will guess if
7745 // this info is not there but there are cases it cannot get right.
7746 unsigned FrameAlign;
7747 if (F.getParamAlignment(Idx))
7748 FrameAlign = F.getParamAlignment(Idx);
7750 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7751 Flags.setByValAlign(FrameAlign);
7753 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7756 Flags.setInConsecutiveRegs();
7757 Flags.setOrigAlign(OriginalAlignment);
7759 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7760 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7761 for (unsigned i = 0; i != NumRegs; ++i) {
7762 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7763 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7764 if (NumRegs > 1 && i == 0)
7765 MyFlags.Flags.setSplit();
7766 // if it isn't first piece, alignment must be 1
7768 MyFlags.Flags.setOrigAlign(1);
7769 Ins.push_back(MyFlags);
7771 if (NeedsRegBlock && Value == NumValues - 1)
7772 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7773 PartBase += VT.getStoreSize();
7777 // Call the target to set up the argument values.
7778 SmallVector<SDValue, 8> InVals;
7779 SDValue NewRoot = TLI->LowerFormalArguments(
7780 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7782 // Verify that the target's LowerFormalArguments behaved as expected.
7783 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7784 "LowerFormalArguments didn't return a valid chain!");
7785 assert(InVals.size() == Ins.size() &&
7786 "LowerFormalArguments didn't emit the correct number of values!");
7788 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7789 assert(InVals[i].getNode() &&
7790 "LowerFormalArguments emitted a null value!");
7791 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7792 "LowerFormalArguments emitted a value with the wrong type!");
7796 // Update the DAG with the new chain value resulting from argument lowering.
7797 DAG.setRoot(NewRoot);
7799 // Set up the argument values.
7802 if (!FuncInfo->CanLowerReturn) {
7803 // Create a virtual register for the sret pointer, and put in a copy
7804 // from the sret argument into it.
7805 SmallVector<EVT, 1> ValueVTs;
7806 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7807 MVT VT = ValueVTs[0].getSimpleVT();
7808 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7809 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7810 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7811 RegVT, VT, nullptr, AssertOp);
7813 MachineFunction& MF = SDB->DAG.getMachineFunction();
7814 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7815 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7816 FuncInfo->DemoteRegister = SRetReg;
7818 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7819 DAG.setRoot(NewRoot);
7821 // i indexes lowered arguments. Bump it past the hidden sret argument.
7822 // Idx indexes LLVM arguments. Don't touch it.
7826 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7828 SmallVector<SDValue, 4> ArgValues;
7829 SmallVector<EVT, 4> ValueVTs;
7830 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7831 unsigned NumValues = ValueVTs.size();
7833 // If this argument is unused then remember its value. It is used to generate
7834 // debugging information.
7835 if (I->use_empty() && NumValues) {
7836 SDB->setUnusedArgValue(I, InVals[i]);
7838 // Also remember any frame index for use in FastISel.
7839 if (FrameIndexSDNode *FI =
7840 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7841 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7844 for (unsigned Val = 0; Val != NumValues; ++Val) {
7845 EVT VT = ValueVTs[Val];
7846 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7847 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7849 if (!I->use_empty()) {
7850 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7851 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7852 AssertOp = ISD::AssertSext;
7853 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7854 AssertOp = ISD::AssertZext;
7856 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7857 NumParts, PartVT, VT,
7858 nullptr, AssertOp));
7864 // We don't need to do anything else for unused arguments.
7865 if (ArgValues.empty())
7868 // Note down frame index.
7869 if (FrameIndexSDNode *FI =
7870 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7871 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7873 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7874 SDB->getCurSDLoc());
7876 SDB->setValue(I, Res);
7877 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7878 if (LoadSDNode *LNode =
7879 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7880 if (FrameIndexSDNode *FI =
7881 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7882 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7885 // If this argument is live outside of the entry block, insert a copy from
7886 // wherever we got it to the vreg that other BB's will reference it as.
7887 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7888 // If we can, though, try to skip creating an unnecessary vreg.
7889 // FIXME: This isn't very clean... it would be nice to make this more
7890 // general. It's also subtly incompatible with the hacks FastISel
7892 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7893 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7894 FuncInfo->ValueMap[I] = Reg;
7898 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7899 FuncInfo->InitializeRegForValue(I);
7900 SDB->CopyToExportRegsIfNeeded(I);
7904 assert(i == InVals.size() && "Argument register count mismatch!");
7906 // Finally, if the target has anything special to do, allow it to do so.
7907 EmitFunctionEntryCode();
7910 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7911 /// ensure constants are generated when needed. Remember the virtual registers
7912 /// that need to be added to the Machine PHI nodes as input. We cannot just
7913 /// directly add them, because expansion might result in multiple MBB's for one
7914 /// BB. As such, the start of the BB might correspond to a different MBB than
7918 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7919 const TerminatorInst *TI = LLVMBB->getTerminator();
7921 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7923 // Check successor nodes' PHI nodes that expect a constant to be available
7925 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7926 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7927 if (!isa<PHINode>(SuccBB->begin())) continue;
7928 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7930 // If this terminator has multiple identical successors (common for
7931 // switches), only handle each succ once.
7932 if (!SuccsHandled.insert(SuccMBB).second)
7935 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7937 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7938 // nodes and Machine PHI nodes, but the incoming operands have not been
7940 for (BasicBlock::const_iterator I = SuccBB->begin();
7941 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7942 // Ignore dead phi's.
7943 if (PN->use_empty()) continue;
7946 if (PN->getType()->isEmptyTy())
7950 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7952 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7953 unsigned &RegOut = ConstantsOut[C];
7955 RegOut = FuncInfo.CreateRegs(C->getType());
7956 CopyValueToVirtualRegister(C, RegOut);
7960 DenseMap<const Value *, unsigned>::iterator I =
7961 FuncInfo.ValueMap.find(PHIOp);
7962 if (I != FuncInfo.ValueMap.end())
7965 assert(isa<AllocaInst>(PHIOp) &&
7966 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7967 "Didn't codegen value into a register!??");
7968 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7969 CopyValueToVirtualRegister(PHIOp, Reg);
7973 // Remember that this register needs to added to the machine PHI node as
7974 // the input for this MBB.
7975 SmallVector<EVT, 4> ValueVTs;
7976 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7977 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7978 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7979 EVT VT = ValueVTs[vti];
7980 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7981 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7982 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7983 Reg += NumRegisters;
7988 ConstantsOut.clear();
7991 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7994 SelectionDAGBuilder::StackProtectorDescriptor::
7995 AddSuccessorMBB(const BasicBlock *BB,
7996 MachineBasicBlock *ParentMBB,
7998 MachineBasicBlock *SuccMBB) {
7999 // If SuccBB has not been created yet, create it.
8001 MachineFunction *MF = ParentMBB->getParent();
8002 MachineFunction::iterator BBI = ParentMBB;
8003 SuccMBB = MF->CreateMachineBasicBlock(BB);
8004 MF->insert(++BBI, SuccMBB);
8006 // Add it as a successor of ParentMBB.
8007 ParentMBB->addSuccessor(
8008 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));