1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
15 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
17 #include "StatepointLowering.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 #include "llvm/IR/CallSite.h"
25 #include "llvm/IR/Statepoint.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Target/TargetLowering.h"
33 class AddrSpaceCastInst;
40 class ExtractElementInst;
41 class ExtractValueInst;
48 class FunctionLoweringInfo;
49 class GetElementPtrInst;
55 class InsertElementInst;
56 class InsertValueInst;
59 class MachineBasicBlock;
61 class MachineRegisterInfo;
70 class ShuffleVectorInst;
75 class TargetLibraryInfo;
79 class UnreachableInst;
83 //===----------------------------------------------------------------------===//
84 /// SelectionDAGBuilder - This is the common target-independent lowering
85 /// implementation that is parameterized by a TargetLowering object.
87 class SelectionDAGBuilder {
88 /// CurInst - The current instruction being visited
89 const Instruction *CurInst;
91 DenseMap<const Value*, SDValue> NodeMap;
93 /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
94 /// to preserve debug information for incoming arguments.
95 DenseMap<const Value*, SDValue> UnusedArgNodeMap;
97 /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
98 class DanglingDebugInfo {
99 const DbgValueInst* DI;
101 unsigned SDNodeOrder;
103 DanglingDebugInfo() : DI(nullptr), dl(DebugLoc()), SDNodeOrder(0) { }
104 DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
105 DI(di), dl(DL), SDNodeOrder(SDNO) { }
106 const DbgValueInst* getDI() { return DI; }
107 DebugLoc getdl() { return dl; }
108 unsigned getSDNodeOrder() { return SDNodeOrder; }
111 /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
112 /// yet seen the referent. We defer handling these until we do see it.
113 DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
116 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
117 /// them up and then emit token factor nodes when possible. This allows us to
118 /// get simple disambiguation between loads without worrying about alias
120 SmallVector<SDValue, 8> PendingLoads;
122 /// State used while lowering a statepoint sequence (gc_statepoint,
123 /// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details.
124 StatepointLoweringState StatepointLowering;
127 /// PendingExports - CopyToReg nodes that copy values to virtual registers
128 /// for export to other blocks need to be emitted before any terminator
129 /// instruction, but they have no other ordering requirements. We bunch them
130 /// up and the emit a single tokenfactor for them just before terminator
132 SmallVector<SDValue, 8> PendingExports;
134 /// SDNodeOrder - A unique monotonically increasing number used to order the
135 /// SDNodes we create.
136 unsigned SDNodeOrder;
138 enum CaseClusterKind {
139 /// A cluster of adjacent case labels with the same destination, or just one
142 /// A cluster of cases suitable for jump table lowering.
144 /// A cluster of cases suitable for bit test lowering.
148 /// A cluster of case labels.
150 CaseClusterKind Kind;
151 const ConstantInt *Low, *High;
153 MachineBasicBlock *MBB;
154 unsigned JTCasesIndex;
155 unsigned BTCasesIndex;
157 BranchProbability Prob;
159 static CaseCluster range(const ConstantInt *Low, const ConstantInt *High,
160 MachineBasicBlock *MBB, BranchProbability Prob) {
170 static CaseCluster jumpTable(const ConstantInt *Low,
171 const ConstantInt *High, unsigned JTCasesIndex,
172 BranchProbability Prob) {
174 C.Kind = CC_JumpTable;
177 C.JTCasesIndex = JTCasesIndex;
182 static CaseCluster bitTests(const ConstantInt *Low, const ConstantInt *High,
183 unsigned BTCasesIndex, BranchProbability Prob) {
185 C.Kind = CC_BitTests;
188 C.BTCasesIndex = BTCasesIndex;
194 typedef std::vector<CaseCluster> CaseClusterVector;
195 typedef CaseClusterVector::iterator CaseClusterIt;
199 MachineBasicBlock* BB;
201 BranchProbability ExtraProb;
203 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
204 BranchProbability Prob):
205 Mask(mask), BB(bb), Bits(bits), ExtraProb(Prob) { }
207 CaseBits() : Mask(0), BB(nullptr), Bits(0) {}
210 typedef std::vector<CaseBits> CaseBitsVector;
212 /// Sort Clusters and merge adjacent cases.
213 void sortAndRangeify(CaseClusterVector &Clusters);
215 /// CaseBlock - This structure is used to communicate between
216 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
217 /// blocks needed by multi-case switch statements.
219 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
220 const Value *cmpmiddle, MachineBasicBlock *truebb,
221 MachineBasicBlock *falsebb, MachineBasicBlock *me,
222 BranchProbability trueprob = BranchProbability::getUnknown(),
223 BranchProbability falseprob = BranchProbability::getUnknown())
224 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
225 TrueBB(truebb), FalseBB(falsebb), ThisBB(me), TrueProb(trueprob),
226 FalseProb(falseprob) {}
228 // CC - the condition code to use for the case block's setcc node
231 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
232 // Emit by default LHS op RHS. MHS is used for range comparisons:
233 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
234 const Value *CmpLHS, *CmpMHS, *CmpRHS;
236 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
237 MachineBasicBlock *TrueBB, *FalseBB;
239 // ThisBB - the block into which to emit the code for the setcc and branches
240 MachineBasicBlock *ThisBB;
242 // TrueProb/FalseProb - branch weights.
243 BranchProbability TrueProb, FalseProb;
247 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
248 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
250 /// Reg - the virtual register containing the index of the jump table entry
253 /// JTI - the JumpTableIndex for this jump table in the function.
255 /// MBB - the MBB into which to emit the code for the indirect jump.
256 MachineBasicBlock *MBB;
257 /// Default - the MBB of the default bb, which is a successor of the range
258 /// check MBB. This is when updating PHI nodes in successors.
259 MachineBasicBlock *Default;
261 struct JumpTableHeader {
262 JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
264 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
268 MachineBasicBlock *HeaderBB;
271 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
274 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
275 BranchProbability Prob):
276 Mask(M), ThisBB(T), TargetBB(Tr), ExtraProb(Prob) { }
278 MachineBasicBlock *ThisBB;
279 MachineBasicBlock *TargetBB;
280 BranchProbability ExtraProb;
283 typedef SmallVector<BitTestCase, 3> BitTestInfo;
285 struct BitTestBlock {
286 BitTestBlock(APInt F, APInt R, const Value *SV, unsigned Rg, MVT RgVT,
287 bool E, bool CR, MachineBasicBlock *P, MachineBasicBlock *D,
288 BitTestInfo C, BranchProbability Pr)
289 : First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
290 ContiguousRange(CR), Parent(P), Default(D), Cases(std::move(C)),
298 bool ContiguousRange;
299 MachineBasicBlock *Parent;
300 MachineBasicBlock *Default;
302 BranchProbability Prob;
303 BranchProbability DefaultProb;
306 /// Minimum jump table density, in percent.
307 enum { MinJumpTableDensity = 40 };
309 /// Check whether a range of clusters is dense enough for a jump table.
310 bool isDense(const CaseClusterVector &Clusters, unsigned *TotalCases,
311 unsigned First, unsigned Last);
313 /// Build a jump table cluster from Clusters[First..Last]. Returns false if it
314 /// decides it's not a good idea.
315 bool buildJumpTable(CaseClusterVector &Clusters, unsigned First,
316 unsigned Last, const SwitchInst *SI,
317 MachineBasicBlock *DefaultMBB, CaseCluster &JTCluster);
319 /// Find clusters of cases suitable for jump table lowering.
320 void findJumpTables(CaseClusterVector &Clusters, const SwitchInst *SI,
321 MachineBasicBlock *DefaultMBB);
323 /// Check whether the range [Low,High] fits in a machine word.
324 bool rangeFitsInWord(const APInt &Low, const APInt &High);
326 /// Check whether these clusters are suitable for lowering with bit tests based
327 /// on the number of destinations, comparison metric, and range.
328 bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
329 const APInt &Low, const APInt &High);
331 /// Build a bit test cluster from Clusters[First..Last]. Returns false if it
332 /// decides it's not a good idea.
333 bool buildBitTests(CaseClusterVector &Clusters, unsigned First, unsigned Last,
334 const SwitchInst *SI, CaseCluster &BTCluster);
336 /// Find clusters of cases suitable for bit test lowering.
337 void findBitTestClusters(CaseClusterVector &Clusters, const SwitchInst *SI);
339 struct SwitchWorkListItem {
340 MachineBasicBlock *MBB;
341 CaseClusterIt FirstCluster;
342 CaseClusterIt LastCluster;
343 const ConstantInt *GE;
344 const ConstantInt *LT;
345 BranchProbability DefaultProb;
347 typedef SmallVector<SwitchWorkListItem, 4> SwitchWorkList;
349 /// Determine the rank by weight of CC in [First,Last]. If CC has more weight
350 /// than each cluster in the range, its rank is 0.
351 static unsigned caseClusterRank(const CaseCluster &CC, CaseClusterIt First,
354 /// Emit comparison and split W into two subtrees.
355 void splitWorkItem(SwitchWorkList &WorkList, const SwitchWorkListItem &W,
356 Value *Cond, MachineBasicBlock *SwitchMBB);
359 void lowerWorkItem(SwitchWorkListItem W, Value *Cond,
360 MachineBasicBlock *SwitchMBB,
361 MachineBasicBlock *DefaultMBB);
364 /// A class which encapsulates all of the information needed to generate a
365 /// stack protector check and signals to isel via its state being initialized
366 /// that a stack protector needs to be generated.
368 /// *NOTE* The following is a high level documentation of SelectionDAG Stack
369 /// Protector Generation. The reason that it is placed here is for a lack of
370 /// other good places to stick it.
372 /// High Level Overview of SelectionDAG Stack Protector Generation:
374 /// Previously, generation of stack protectors was done exclusively in the
375 /// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
376 /// splitting basic blocks at the IR level to create the success/failure basic
377 /// blocks in the tail of the basic block in question. As a result of this,
378 /// calls that would have qualified for the sibling call optimization were no
379 /// longer eligible for optimization since said calls were no longer right in
380 /// the "tail position" (i.e. the immediate predecessor of a ReturnInst
383 /// Then it was noticed that since the sibling call optimization causes the
384 /// callee to reuse the caller's stack, if we could delay the generation of
385 /// the stack protector check until later in CodeGen after the sibling call
386 /// decision was made, we get both the tail call optimization and the stack
389 /// A few goals in solving this problem were:
391 /// 1. Preserve the architecture independence of stack protector generation.
393 /// 2. Preserve the normal IR level stack protector check for platforms like
394 /// OpenBSD for which we support platform-specific stack protector
397 /// The main problem that guided the present solution is that one can not
398 /// solve this problem in an architecture independent manner at the IR level
399 /// only. This is because:
401 /// 1. The decision on whether or not to perform a sibling call on certain
402 /// platforms (for instance i386) requires lower level information
403 /// related to available registers that can not be known at the IR level.
405 /// 2. Even if the previous point were not true, the decision on whether to
406 /// perform a tail call is done in LowerCallTo in SelectionDAG which
407 /// occurs after the Stack Protector Pass. As a result, one would need to
408 /// put the relevant callinst into the stack protector check success
409 /// basic block (where the return inst is placed) and then move it back
410 /// later at SelectionDAG/MI time before the stack protector check if the
411 /// tail call optimization failed. The MI level option was nixed
412 /// immediately since it would require platform-specific pattern
413 /// matching. The SelectionDAG level option was nixed because
414 /// SelectionDAG only processes one IR level basic block at a time
415 /// implying one could not create a DAG Combine to move the callinst.
417 /// To get around this problem a few things were realized:
419 /// 1. While one can not handle multiple IR level basic blocks at the
420 /// SelectionDAG Level, one can generate multiple machine basic blocks
421 /// for one IR level basic block. This is how we handle bit tests and
424 /// 2. At the MI level, tail calls are represented via a special return
425 /// MIInst called "tcreturn". Thus if we know the basic block in which we
426 /// wish to insert the stack protector check, we get the correct behavior
427 /// by always inserting the stack protector check right before the return
428 /// statement. This is a "magical transformation" since no matter where
429 /// the stack protector check intrinsic is, we always insert the stack
430 /// protector check code at the end of the BB.
432 /// Given the aforementioned constraints, the following solution was devised:
434 /// 1. On platforms that do not support SelectionDAG stack protector check
435 /// generation, allow for the normal IR level stack protector check
436 /// generation to continue.
438 /// 2. On platforms that do support SelectionDAG stack protector check
441 /// a. Use the IR level stack protector pass to decide if a stack
442 /// protector is required/which BB we insert the stack protector check
443 /// in by reusing the logic already therein. If we wish to generate a
444 /// stack protector check in a basic block, we place a special IR
445 /// intrinsic called llvm.stackprotectorcheck right before the BB's
446 /// returninst or if there is a callinst that could potentially be
447 /// sibling call optimized, before the call inst.
449 /// b. Then when a BB with said intrinsic is processed, we codegen the BB
450 /// normally via SelectBasicBlock. In said process, when we visit the
451 /// stack protector check, we do not actually emit anything into the
452 /// BB. Instead, we just initialize the stack protector descriptor
453 /// class (which involves stashing information/creating the success
454 /// mbbb and the failure mbb if we have not created one for this
455 /// function yet) and export the guard variable that we are going to
458 /// c. After we finish selecting the basic block, in FinishBasicBlock if
459 /// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
460 /// initialized, we first find a splice point in the parent basic block
461 /// before the terminator and then splice the terminator of said basic
462 /// block into the success basic block. Then we code-gen a new tail for
463 /// the parent basic block consisting of the two loads, the comparison,
464 /// and finally two branches to the success/failure basic blocks. We
465 /// conclude by code-gening the failure basic block if we have not
466 /// code-gened it already (all stack protector checks we generate in
467 /// the same function, use the same failure basic block).
468 class StackProtectorDescriptor {
470 StackProtectorDescriptor() : ParentMBB(nullptr), SuccessMBB(nullptr),
471 FailureMBB(nullptr), Guard(nullptr),
474 /// Returns true if all fields of the stack protector descriptor are
475 /// initialized implying that we should/are ready to emit a stack protector.
476 bool shouldEmitStackProtector() const {
477 return ParentMBB && SuccessMBB && FailureMBB && Guard;
480 /// Initialize the stack protector descriptor structure for a new basic
482 void initialize(const BasicBlock *BB,
483 MachineBasicBlock *MBB,
484 const CallInst &StackProtCheckCall) {
485 // Make sure we are not initialized yet.
486 assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
487 "already initialized!");
489 SuccessMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ true);
490 FailureMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ false, FailureMBB);
492 Guard = StackProtCheckCall.getArgOperand(0);
495 /// Reset state that changes when we handle different basic blocks.
497 /// This currently includes:
499 /// 1. The specific basic block we are generating a
500 /// stack protector for (ParentMBB).
502 /// 2. The successor machine basic block that will contain the tail of
503 /// parent mbb after we create the stack protector check (SuccessMBB). This
504 /// BB is visited only on stack protector check success.
505 void resetPerBBState() {
507 SuccessMBB = nullptr;
510 /// Reset state that only changes when we switch functions.
512 /// This currently includes:
514 /// 1. FailureMBB since we reuse the failure code path for all stack
515 /// protector checks created in an individual function.
517 /// 2.The guard variable since the guard variable we are checking against is
519 void resetPerFunctionState() {
520 FailureMBB = nullptr;
525 MachineBasicBlock *getParentMBB() { return ParentMBB; }
526 MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
527 MachineBasicBlock *getFailureMBB() { return FailureMBB; }
528 const Value *getGuard() { return Guard; }
530 unsigned getGuardReg() const { return GuardReg; }
531 void setGuardReg(unsigned R) { GuardReg = R; }
534 /// The basic block for which we are generating the stack protector.
536 /// As a result of stack protector generation, we will splice the
537 /// terminators of this basic block into the successor mbb SuccessMBB and
538 /// replace it with a compare/branch to the successor mbbs
539 /// SuccessMBB/FailureMBB depending on whether or not the stack protector
541 MachineBasicBlock *ParentMBB;
543 /// A basic block visited on stack protector check success that contains the
544 /// terminators of ParentMBB.
545 MachineBasicBlock *SuccessMBB;
547 /// This basic block visited on stack protector check failure that will
548 /// contain a call to __stack_chk_fail().
549 MachineBasicBlock *FailureMBB;
551 /// The guard variable which we will compare against the stored value in the
552 /// stack protector stack slot.
555 /// The virtual register holding the stack guard value.
558 /// Add a successor machine basic block to ParentMBB. If the successor mbb
559 /// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
560 /// block will be created. Assign a large weight if IsLikely is true.
561 MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
562 MachineBasicBlock *ParentMBB,
564 MachineBasicBlock *SuccMBB = nullptr);
568 const TargetMachine &TM;
570 /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling
571 /// nodes without a corresponding SDNode.
572 static const unsigned LowestSDNodeOrder = 1;
575 const DataLayout *DL;
577 const TargetLibraryInfo *LibInfo;
579 /// SwitchCases - Vector of CaseBlock structures used to communicate
580 /// SwitchInst code generation information.
581 std::vector<CaseBlock> SwitchCases;
582 /// JTCases - Vector of JumpTable structures used to communicate
583 /// SwitchInst code generation information.
584 std::vector<JumpTableBlock> JTCases;
585 /// BitTestCases - Vector of BitTestBlock structures used to communicate
586 /// SwitchInst code generation information.
587 std::vector<BitTestBlock> BitTestCases;
588 /// A StackProtectorDescriptor structure used to communicate stack protector
589 /// information in between SelectBasicBlock and FinishBasicBlock.
590 StackProtectorDescriptor SPDescriptor;
592 // Emit PHI-node-operand constants only once even if used by multiple
594 DenseMap<const Constant *, unsigned> ConstantsOut;
596 /// FuncInfo - Information about the function as a whole.
598 FunctionLoweringInfo &FuncInfo;
600 /// GFI - Garbage collection metadata for the function.
603 /// LPadToCallSiteMap - Map a landing pad to the call site indexes.
604 DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
606 /// HasTailCall - This is set to true if a call in the current
607 /// block has been translated as a tail call. In this case,
608 /// no subsequent DAG nodes should be created.
612 LLVMContext *Context;
614 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
615 CodeGenOpt::Level ol)
616 : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
617 DAG(dag), FuncInfo(funcinfo),
621 void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
622 const TargetLibraryInfo *li);
624 /// clear - Clear out the current SelectionDAG and the associated
625 /// state and prepare this SelectionDAGBuilder object to be used
626 /// for a new block. This doesn't clear out information about
627 /// additional blocks that are needed to complete switch lowering
628 /// or PHI node updating; that information is cleared out as it is
632 /// clearDanglingDebugInfo - Clear the dangling debug information
633 /// map. This function is separated from the clear so that debug
634 /// information that is dangling in a basic block can be properly
635 /// resolved in a different basic block. This allows the
636 /// SelectionDAG to resolve dangling debug information attached
638 void clearDanglingDebugInfo();
640 /// getRoot - Return the current virtual root of the Selection DAG,
641 /// flushing any PendingLoad items. This must be done before emitting
642 /// a store or any other node that may need to be ordered after any
643 /// prior load instructions.
647 /// getControlRoot - Similar to getRoot, but instead of flushing all the
648 /// PendingLoad items, flush all the PendingExports items. It is necessary
649 /// to do this before emitting a terminator instruction.
651 SDValue getControlRoot();
653 SDLoc getCurSDLoc() const {
654 return SDLoc(CurInst, SDNodeOrder);
657 DebugLoc getCurDebugLoc() const {
658 return CurInst ? CurInst->getDebugLoc() : DebugLoc();
661 unsigned getSDNodeOrder() const { return SDNodeOrder; }
663 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
665 void visit(const Instruction &I);
667 void visit(unsigned Opcode, const User &I);
669 /// getCopyFromRegs - If there was virtual register allocated for the value V
670 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
671 SDValue getCopyFromRegs(const Value *V, Type *Ty);
673 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
674 // generate the debug data structures now that we've seen its definition.
675 void resolveDanglingDebugInfo(const Value *V, SDValue Val);
676 SDValue getValue(const Value *V);
677 bool findValue(const Value *V) const;
679 SDValue getNonRegisterValue(const Value *V);
680 SDValue getValueImpl(const Value *V);
682 void setValue(const Value *V, SDValue NewN) {
683 SDValue &N = NodeMap[V];
684 assert(!N.getNode() && "Already set a value for this node!");
688 void setUnusedArgValue(const Value *V, SDValue NewN) {
689 SDValue &N = UnusedArgNodeMap[V];
690 assert(!N.getNode() && "Already set a value for this node!");
694 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
695 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
696 MachineBasicBlock *SwitchBB,
697 Instruction::BinaryOps Opc, BranchProbability TW,
698 BranchProbability FW);
699 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
700 MachineBasicBlock *FBB,
701 MachineBasicBlock *CurBB,
702 MachineBasicBlock *SwitchBB,
703 BranchProbability TW, BranchProbability FW);
704 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
705 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
706 void CopyToExportRegsIfNeeded(const Value *V);
707 void ExportFromCurrentBlock(const Value *V);
708 void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
709 const BasicBlock *EHPadBB = nullptr);
711 std::pair<SDValue, SDValue> lowerCallOperands(
712 ImmutableCallSite CS,
717 const BasicBlock *EHPadBB = nullptr,
718 bool IsPatchPoint = false);
720 /// UpdateSplitBlock - When an MBB was split during scheduling, update the
721 /// references that need to refer to the last resulting block.
722 void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
724 // This function is responsible for the whole statepoint lowering process.
725 // It uniformly handles invoke and call statepoints.
726 void LowerStatepoint(ImmutableStatepoint Statepoint,
727 const BasicBlock *EHPadBB = nullptr);
729 std::pair<SDValue, SDValue>
730 lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
731 const BasicBlock *EHPadBB = nullptr);
733 // Terminator instructions.
734 void visitRet(const ReturnInst &I);
735 void visitBr(const BranchInst &I);
736 void visitSwitch(const SwitchInst &I);
737 void visitIndirectBr(const IndirectBrInst &I);
738 void visitUnreachable(const UnreachableInst &I);
739 void visitCleanupEndPad(const CleanupEndPadInst &I);
740 void visitCleanupRet(const CleanupReturnInst &I);
741 void visitCatchEndPad(const CatchEndPadInst &I);
742 void visitCatchRet(const CatchReturnInst &I);
743 void visitCatchPad(const CatchPadInst &I);
744 void visitTerminatePad(const TerminatePadInst &TPI);
745 void visitCleanupPad(const CleanupPadInst &CPI);
747 BranchProbability getEdgeProbability(const MachineBasicBlock *Src,
748 const MachineBasicBlock *Dst) const;
749 void addSuccessorWithProb(
750 MachineBasicBlock *Src, MachineBasicBlock *Dst,
751 BranchProbability Prob = BranchProbability::getUnknown());
754 void visitSwitchCase(CaseBlock &CB,
755 MachineBasicBlock *SwitchBB);
756 void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
757 MachineBasicBlock *ParentBB);
758 void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
759 void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
760 void visitBitTestCase(BitTestBlock &BB,
761 MachineBasicBlock* NextMBB,
762 BranchProbability BranchProbToNext,
765 MachineBasicBlock *SwitchBB);
766 void visitJumpTable(JumpTable &JT);
767 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
768 MachineBasicBlock *SwitchBB);
771 // These all get lowered before this pass.
772 void visitInvoke(const InvokeInst &I);
773 void visitResume(const ResumeInst &I);
775 void visitBinary(const User &I, unsigned OpCode);
776 void visitShift(const User &I, unsigned Opcode);
777 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
778 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
779 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
780 void visitFSub(const User &I);
781 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
782 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
783 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
784 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
785 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
786 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
787 void visitSDiv(const User &I);
788 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
789 void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
790 void visitOr (const User &I) { visitBinary(I, ISD::OR); }
791 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
792 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
793 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
794 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
795 void visitICmp(const User &I);
796 void visitFCmp(const User &I);
797 // Visit the conversion instructions
798 void visitTrunc(const User &I);
799 void visitZExt(const User &I);
800 void visitSExt(const User &I);
801 void visitFPTrunc(const User &I);
802 void visitFPExt(const User &I);
803 void visitFPToUI(const User &I);
804 void visitFPToSI(const User &I);
805 void visitUIToFP(const User &I);
806 void visitSIToFP(const User &I);
807 void visitPtrToInt(const User &I);
808 void visitIntToPtr(const User &I);
809 void visitBitCast(const User &I);
810 void visitAddrSpaceCast(const User &I);
812 void visitExtractElement(const User &I);
813 void visitInsertElement(const User &I);
814 void visitShuffleVector(const User &I);
816 void visitExtractValue(const ExtractValueInst &I);
817 void visitInsertValue(const InsertValueInst &I);
818 void visitLandingPad(const LandingPadInst &I);
820 void visitGetElementPtr(const User &I);
821 void visitSelect(const User &I);
823 void visitAlloca(const AllocaInst &I);
824 void visitLoad(const LoadInst &I);
825 void visitStore(const StoreInst &I);
826 void visitMaskedLoad(const CallInst &I);
827 void visitMaskedStore(const CallInst &I);
828 void visitMaskedGather(const CallInst &I);
829 void visitMaskedScatter(const CallInst &I);
830 void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
831 void visitAtomicRMW(const AtomicRMWInst &I);
832 void visitFence(const FenceInst &I);
833 void visitPHI(const PHINode &I);
834 void visitCall(const CallInst &I);
835 bool visitMemCmpCall(const CallInst &I);
836 bool visitMemChrCall(const CallInst &I);
837 bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
838 bool visitStrCmpCall(const CallInst &I);
839 bool visitStrLenCall(const CallInst &I);
840 bool visitStrNLenCall(const CallInst &I);
841 bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
842 bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode);
843 void visitAtomicLoad(const LoadInst &I);
844 void visitAtomicStore(const StoreInst &I);
846 void visitInlineAsm(ImmutableCallSite CS);
847 const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
848 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
850 void visitVAStart(const CallInst &I);
851 void visitVAArg(const VAArgInst &I);
852 void visitVAEnd(const CallInst &I);
853 void visitVACopy(const CallInst &I);
854 void visitStackmap(const CallInst &I);
855 void visitPatchpoint(ImmutableCallSite CS,
856 const BasicBlock *EHPadBB = nullptr);
858 // These three are implemented in StatepointLowering.cpp
859 void visitStatepoint(const CallInst &I);
860 void visitGCRelocate(const CallInst &I);
861 void visitGCResult(const CallInst &I);
863 void visitUserOp1(const Instruction &I) {
864 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
866 void visitUserOp2(const Instruction &I) {
867 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
870 void processIntegerCallValue(const Instruction &I,
871 SDValue Value, bool IsSigned);
873 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
875 /// EmitFuncArgumentDbgValue - If V is an function argument then create
876 /// corresponding DBG_VALUE machine instruction for it now. At the end of
877 /// instruction selection, they will be inserted to the entry BB.
878 bool EmitFuncArgumentDbgValue(const Value *V, DILocalVariable *Variable,
879 DIExpression *Expr, DILocation *DL,
880 int64_t Offset, bool IsIndirect,
883 /// Return the next block after MBB, or nullptr if there is none.
884 MachineBasicBlock *NextBlock(MachineBasicBlock *MBB);
886 /// Update the DAG and DAG builder with the relevant information after
887 /// a new root node has been created which could be a tail call.
888 void updateDAGForMaybeTailCall(SDValue MaybeTC);
891 /// RegsForValue - This struct represents the registers (physical or virtual)
892 /// that a particular set of values is assigned, and the type information about
893 /// the value. The most common situation is to represent one value at a time,
894 /// but struct or array values are handled element-wise as multiple values. The
895 /// splitting of aggregates is performed recursively, so that we never have
896 /// aggregate-typed registers. The values at this point do not necessarily have
897 /// legal types, so each value may require one or more registers of some legal
900 struct RegsForValue {
901 /// ValueVTs - The value types of the values, which may not be legal, and
902 /// may need be promoted or synthesized from one or more registers.
904 SmallVector<EVT, 4> ValueVTs;
906 /// RegVTs - The value types of the registers. This is the same size as
907 /// ValueVTs and it records, for each value, what the type of the assigned
908 /// register or registers are. (Individual values are never synthesized
909 /// from more than one type of register.)
911 /// With virtual registers, the contents of RegVTs is redundant with TLI's
912 /// getRegisterType member function, however when with physical registers
913 /// it is necessary to have a separate record of the types.
915 SmallVector<MVT, 4> RegVTs;
917 /// Regs - This list holds the registers assigned to the values.
918 /// Each legal or promoted value requires one register, and each
919 /// expanded value requires multiple registers.
921 SmallVector<unsigned, 4> Regs;
925 RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt);
927 RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
928 const DataLayout &DL, unsigned Reg, Type *Ty);
930 /// append - Add the specified values to this one.
931 void append(const RegsForValue &RHS) {
932 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
933 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
934 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
937 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
938 /// this value and returns the result as a ValueVTs value. This uses
939 /// Chain/Flag as the input and updates them for the output Chain/Flag.
940 /// If the Flag pointer is NULL, no flag is used.
941 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
943 SDValue &Chain, SDValue *Flag,
944 const Value *V = nullptr) const;
946 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the specified
947 /// value into the registers specified by this object. This uses Chain/Flag
948 /// as the input and updates them for the output Chain/Flag. If the Flag
949 /// pointer is nullptr, no flag is used. If V is not nullptr, then it is used
950 /// in printing better diagnostic messages on error.
952 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
953 SDValue *Flag, const Value *V = nullptr,
954 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
956 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
957 /// operand list. This adds the code marker, matching input operand index
958 /// (if applicable), and includes the number of values added into it.
959 void AddInlineAsmOperands(unsigned Kind,
960 bool HasMatching, unsigned MatchingIdx, SDLoc dl,
962 std::vector<SDValue> &Ops) const;
965 } // end namespace llvm