1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
15 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
17 #include "llvm/ADT/APInt.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SelectionDAGNodes.h"
21 #include "llvm/IR/CallSite.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/Support/ErrorHandling.h"
28 class AddrSpaceCastInst;
36 class ExtractElementInst;
37 class ExtractValueInst;
44 class FunctionLoweringInfo;
45 class GetElementPtrInst;
51 class InsertElementInst;
52 class InsertValueInst;
55 class MachineBasicBlock;
57 class MachineRegisterInfo;
66 class ShuffleVectorInst;
71 class TargetLibraryInfo;
75 class UnreachableInst;
79 //===----------------------------------------------------------------------===//
80 /// SelectionDAGBuilder - This is the common target-independent lowering
81 /// implementation that is parameterized by a TargetLowering object.
83 class SelectionDAGBuilder {
84 /// CurInst - The current instruction being visited
85 const Instruction *CurInst;
87 DenseMap<const Value*, SDValue> NodeMap;
89 /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
90 /// to preserve debug information for incoming arguments.
91 DenseMap<const Value*, SDValue> UnusedArgNodeMap;
93 /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
94 class DanglingDebugInfo {
95 const DbgValueInst* DI;
99 DanglingDebugInfo() : DI(nullptr), dl(DebugLoc()), SDNodeOrder(0) { }
100 DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
101 DI(di), dl(DL), SDNodeOrder(SDNO) { }
102 const DbgValueInst* getDI() { return DI; }
103 DebugLoc getdl() { return dl; }
104 unsigned getSDNodeOrder() { return SDNodeOrder; }
107 /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
108 /// yet seen the referent. We defer handling these until we do see it.
109 DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
112 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
113 /// them up and then emit token factor nodes when possible. This allows us to
114 /// get simple disambiguation between loads without worrying about alias
116 SmallVector<SDValue, 8> PendingLoads;
119 /// PendingExports - CopyToReg nodes that copy values to virtual registers
120 /// for export to other blocks need to be emitted before any terminator
121 /// instruction, but they have no other ordering requirements. We bunch them
122 /// up and the emit a single tokenfactor for them just before terminator
124 SmallVector<SDValue, 8> PendingExports;
126 /// SDNodeOrder - A unique monotonically increasing number used to order the
127 /// SDNodes we create.
128 unsigned SDNodeOrder;
130 /// Case - A struct to record the Value for a switch case, and the
131 /// case's target basic block.
134 const Constant *High;
135 MachineBasicBlock* BB;
136 uint32_t ExtraWeight;
138 Case() : Low(nullptr), High(nullptr), BB(nullptr), ExtraWeight(0) { }
139 Case(const Constant *low, const Constant *high, MachineBasicBlock *bb,
140 uint32_t extraweight) : Low(low), High(high), BB(bb),
141 ExtraWeight(extraweight) { }
144 const APInt &rHigh = cast<ConstantInt>(High)->getValue();
145 const APInt &rLow = cast<ConstantInt>(Low)->getValue();
146 return (rHigh - rLow + 1ULL);
152 MachineBasicBlock* BB;
154 uint32_t ExtraWeight;
156 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
158 Mask(mask), BB(bb), Bits(bits), ExtraWeight(Weight) { }
161 typedef std::vector<Case> CaseVector;
162 typedef std::vector<CaseBits> CaseBitsVector;
163 typedef CaseVector::iterator CaseItr;
164 typedef std::pair<CaseItr, CaseItr> CaseRange;
166 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
167 /// of conditional branches.
169 CaseRec(MachineBasicBlock *bb, const Constant *lt, const Constant *ge,
171 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
173 /// CaseBB - The MBB in which to emit the compare and branch
174 MachineBasicBlock *CaseBB;
175 /// LT, GE - If nonzero, we know the current case value must be less-than or
176 /// greater-than-or-equal-to these Constants.
179 /// Range - A pair of iterators representing the range of case values to be
180 /// processed at this point in the binary search tree.
184 typedef std::vector<CaseRec> CaseRecVector;
186 /// The comparison function for sorting the switch case values in the vector.
187 /// WARNING: Case ranges should be disjoint!
189 bool operator()(const Case &C1, const Case &C2) {
190 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
191 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
192 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
193 return CI1->getValue().slt(CI2->getValue());
198 bool operator()(const CaseBits &C1, const CaseBits &C2) {
199 return C1.Bits > C2.Bits;
203 size_t Clusterify(CaseVector &Cases, const SwitchInst &SI);
205 /// CaseBlock - This structure is used to communicate between
206 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
207 /// blocks needed by multi-case switch statements.
209 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
210 const Value *cmpmiddle,
211 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
212 MachineBasicBlock *me,
213 uint32_t trueweight = 0, uint32_t falseweight = 0)
214 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
215 TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
216 TrueWeight(trueweight), FalseWeight(falseweight) { }
218 // CC - the condition code to use for the case block's setcc node
221 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
222 // Emit by default LHS op RHS. MHS is used for range comparisons:
223 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
224 const Value *CmpLHS, *CmpMHS, *CmpRHS;
226 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
227 MachineBasicBlock *TrueBB, *FalseBB;
229 // ThisBB - the block into which to emit the code for the setcc and branches
230 MachineBasicBlock *ThisBB;
232 // TrueWeight/FalseWeight - branch weights.
233 uint32_t TrueWeight, FalseWeight;
237 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
238 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
240 /// Reg - the virtual register containing the index of the jump table entry
243 /// JTI - the JumpTableIndex for this jump table in the function.
245 /// MBB - the MBB into which to emit the code for the indirect jump.
246 MachineBasicBlock *MBB;
247 /// Default - the MBB of the default bb, which is a successor of the range
248 /// check MBB. This is when updating PHI nodes in successors.
249 MachineBasicBlock *Default;
251 struct JumpTableHeader {
252 JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
254 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
258 MachineBasicBlock *HeaderBB;
261 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
264 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
266 Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
268 MachineBasicBlock *ThisBB;
269 MachineBasicBlock *TargetBB;
270 uint32_t ExtraWeight;
273 typedef SmallVector<BitTestCase, 3> BitTestInfo;
275 struct BitTestBlock {
276 BitTestBlock(APInt F, APInt R, const Value* SV,
277 unsigned Rg, MVT RgVT, bool E,
278 MachineBasicBlock* P, MachineBasicBlock* D,
279 const BitTestInfo& C):
280 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
281 Parent(P), Default(D), Cases(C) { }
288 MachineBasicBlock *Parent;
289 MachineBasicBlock *Default;
293 /// A class which encapsulates all of the information needed to generate a
294 /// stack protector check and signals to isel via its state being initialized
295 /// that a stack protector needs to be generated.
297 /// *NOTE* The following is a high level documentation of SelectionDAG Stack
298 /// Protector Generation. The reason that it is placed here is for a lack of
299 /// other good places to stick it.
301 /// High Level Overview of SelectionDAG Stack Protector Generation:
303 /// Previously, generation of stack protectors was done exclusively in the
304 /// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
305 /// splitting basic blocks at the IR level to create the success/failure basic
306 /// blocks in the tail of the basic block in question. As a result of this,
307 /// calls that would have qualified for the sibling call optimization were no
308 /// longer eligible for optimization since said calls were no longer right in
309 /// the "tail position" (i.e. the immediate predecessor of a ReturnInst
312 /// Then it was noticed that since the sibling call optimization causes the
313 /// callee to reuse the caller's stack, if we could delay the generation of
314 /// the stack protector check until later in CodeGen after the sibling call
315 /// decision was made, we get both the tail call optimization and the stack
318 /// A few goals in solving this problem were:
320 /// 1. Preserve the architecture independence of stack protector generation.
322 /// 2. Preserve the normal IR level stack protector check for platforms like
323 /// OpenBSD for which we support platform-specific stack protector
326 /// The main problem that guided the present solution is that one can not
327 /// solve this problem in an architecture independent manner at the IR level
328 /// only. This is because:
330 /// 1. The decision on whether or not to perform a sibling call on certain
331 /// platforms (for instance i386) requires lower level information
332 /// related to available registers that can not be known at the IR level.
334 /// 2. Even if the previous point were not true, the decision on whether to
335 /// perform a tail call is done in LowerCallTo in SelectionDAG which
336 /// occurs after the Stack Protector Pass. As a result, one would need to
337 /// put the relevant callinst into the stack protector check success
338 /// basic block (where the return inst is placed) and then move it back
339 /// later at SelectionDAG/MI time before the stack protector check if the
340 /// tail call optimization failed. The MI level option was nixed
341 /// immediately since it would require platform-specific pattern
342 /// matching. The SelectionDAG level option was nixed because
343 /// SelectionDAG only processes one IR level basic block at a time
344 /// implying one could not create a DAG Combine to move the callinst.
346 /// To get around this problem a few things were realized:
348 /// 1. While one can not handle multiple IR level basic blocks at the
349 /// SelectionDAG Level, one can generate multiple machine basic blocks
350 /// for one IR level basic block. This is how we handle bit tests and
353 /// 2. At the MI level, tail calls are represented via a special return
354 /// MIInst called "tcreturn". Thus if we know the basic block in which we
355 /// wish to insert the stack protector check, we get the correct behavior
356 /// by always inserting the stack protector check right before the return
357 /// statement. This is a "magical transformation" since no matter where
358 /// the stack protector check intrinsic is, we always insert the stack
359 /// protector check code at the end of the BB.
361 /// Given the aforementioned constraints, the following solution was devised:
363 /// 1. On platforms that do not support SelectionDAG stack protector check
364 /// generation, allow for the normal IR level stack protector check
365 /// generation to continue.
367 /// 2. On platforms that do support SelectionDAG stack protector check
370 /// a. Use the IR level stack protector pass to decide if a stack
371 /// protector is required/which BB we insert the stack protector check
372 /// in by reusing the logic already therein. If we wish to generate a
373 /// stack protector check in a basic block, we place a special IR
374 /// intrinsic called llvm.stackprotectorcheck right before the BB's
375 /// returninst or if there is a callinst that could potentially be
376 /// sibling call optimized, before the call inst.
378 /// b. Then when a BB with said intrinsic is processed, we codegen the BB
379 /// normally via SelectBasicBlock. In said process, when we visit the
380 /// stack protector check, we do not actually emit anything into the
381 /// BB. Instead, we just initialize the stack protector descriptor
382 /// class (which involves stashing information/creating the success
383 /// mbbb and the failure mbb if we have not created one for this
384 /// function yet) and export the guard variable that we are going to
387 /// c. After we finish selecting the basic block, in FinishBasicBlock if
388 /// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
389 /// initialized, we first find a splice point in the parent basic block
390 /// before the terminator and then splice the terminator of said basic
391 /// block into the success basic block. Then we code-gen a new tail for
392 /// the parent basic block consisting of the two loads, the comparison,
393 /// and finally two branches to the success/failure basic blocks. We
394 /// conclude by code-gening the failure basic block if we have not
395 /// code-gened it already (all stack protector checks we generate in
396 /// the same function, use the same failure basic block).
397 class StackProtectorDescriptor {
399 StackProtectorDescriptor() : ParentMBB(nullptr), SuccessMBB(nullptr),
400 FailureMBB(nullptr), Guard(nullptr),
402 ~StackProtectorDescriptor() { }
404 /// Returns true if all fields of the stack protector descriptor are
405 /// initialized implying that we should/are ready to emit a stack protector.
406 bool shouldEmitStackProtector() const {
407 return ParentMBB && SuccessMBB && FailureMBB && Guard;
410 /// Initialize the stack protector descriptor structure for a new basic
412 void initialize(const BasicBlock *BB,
413 MachineBasicBlock *MBB,
414 const CallInst &StackProtCheckCall) {
415 // Make sure we are not initialized yet.
416 assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
417 "already initialized!");
419 SuccessMBB = AddSuccessorMBB(BB, MBB);
420 FailureMBB = AddSuccessorMBB(BB, MBB, FailureMBB);
422 Guard = StackProtCheckCall.getArgOperand(0);
425 /// Reset state that changes when we handle different basic blocks.
427 /// This currently includes:
429 /// 1. The specific basic block we are generating a
430 /// stack protector for (ParentMBB).
432 /// 2. The successor machine basic block that will contain the tail of
433 /// parent mbb after we create the stack protector check (SuccessMBB). This
434 /// BB is visited only on stack protector check success.
435 void resetPerBBState() {
437 SuccessMBB = nullptr;
440 /// Reset state that only changes when we switch functions.
442 /// This currently includes:
444 /// 1. FailureMBB since we reuse the failure code path for all stack
445 /// protector checks created in an individual function.
447 /// 2.The guard variable since the guard variable we are checking against is
449 void resetPerFunctionState() {
450 FailureMBB = nullptr;
454 MachineBasicBlock *getParentMBB() { return ParentMBB; }
455 MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
456 MachineBasicBlock *getFailureMBB() { return FailureMBB; }
457 const Value *getGuard() { return Guard; }
459 unsigned getGuardReg() const { return GuardReg; }
460 void setGuardReg(unsigned R) { GuardReg = R; }
463 /// The basic block for which we are generating the stack protector.
465 /// As a result of stack protector generation, we will splice the
466 /// terminators of this basic block into the successor mbb SuccessMBB and
467 /// replace it with a compare/branch to the successor mbbs
468 /// SuccessMBB/FailureMBB depending on whether or not the stack protector
470 MachineBasicBlock *ParentMBB;
472 /// A basic block visited on stack protector check success that contains the
473 /// terminators of ParentMBB.
474 MachineBasicBlock *SuccessMBB;
476 /// This basic block visited on stack protector check failure that will
477 /// contain a call to __stack_chk_fail().
478 MachineBasicBlock *FailureMBB;
480 /// The guard variable which we will compare against the stored value in the
481 /// stack protector stack slot.
484 /// The virtual register holding the stack guard value.
487 /// Add a successor machine basic block to ParentMBB. If the successor mbb
488 /// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
489 /// block will be created.
490 MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
491 MachineBasicBlock *ParentMBB,
492 MachineBasicBlock *SuccMBB = nullptr);
496 const TargetMachine &TM;
498 /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling
499 /// nodes without a corresponding SDNode.
500 static const unsigned LowestSDNodeOrder = 1;
503 const DataLayout *DL;
505 const TargetLibraryInfo *LibInfo;
507 /// SwitchCases - Vector of CaseBlock structures used to communicate
508 /// SwitchInst code generation information.
509 std::vector<CaseBlock> SwitchCases;
510 /// JTCases - Vector of JumpTable structures used to communicate
511 /// SwitchInst code generation information.
512 std::vector<JumpTableBlock> JTCases;
513 /// BitTestCases - Vector of BitTestBlock structures used to communicate
514 /// SwitchInst code generation information.
515 std::vector<BitTestBlock> BitTestCases;
516 /// A StackProtectorDescriptor structure used to communicate stack protector
517 /// information in between SelectBasicBlock and FinishBasicBlock.
518 StackProtectorDescriptor SPDescriptor;
520 // Emit PHI-node-operand constants only once even if used by multiple
522 DenseMap<const Constant *, unsigned> ConstantsOut;
524 /// FuncInfo - Information about the function as a whole.
526 FunctionLoweringInfo &FuncInfo;
528 /// OptLevel - What optimization level we're generating code for.
530 CodeGenOpt::Level OptLevel;
532 /// GFI - Garbage collection metadata for the function.
535 /// LPadToCallSiteMap - Map a landing pad to the call site indexes.
536 DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
538 /// HasTailCall - This is set to true if a call in the current
539 /// block has been translated as a tail call. In this case,
540 /// no subsequent DAG nodes should be created.
544 LLVMContext *Context;
546 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
547 CodeGenOpt::Level ol)
548 : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
549 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
553 void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
554 const TargetLibraryInfo *li);
556 /// clear - Clear out the current SelectionDAG and the associated
557 /// state and prepare this SelectionDAGBuilder object to be used
558 /// for a new block. This doesn't clear out information about
559 /// additional blocks that are needed to complete switch lowering
560 /// or PHI node updating; that information is cleared out as it is
564 /// clearDanglingDebugInfo - Clear the dangling debug information
565 /// map. This function is separated from the clear so that debug
566 /// information that is dangling in a basic block can be properly
567 /// resolved in a different basic block. This allows the
568 /// SelectionDAG to resolve dangling debug information attached
570 void clearDanglingDebugInfo();
572 /// getRoot - Return the current virtual root of the Selection DAG,
573 /// flushing any PendingLoad items. This must be done before emitting
574 /// a store or any other node that may need to be ordered after any
575 /// prior load instructions.
579 /// getControlRoot - Similar to getRoot, but instead of flushing all the
580 /// PendingLoad items, flush all the PendingExports items. It is necessary
581 /// to do this before emitting a terminator instruction.
583 SDValue getControlRoot();
585 SDLoc getCurSDLoc() const {
586 return SDLoc(CurInst, SDNodeOrder);
589 DebugLoc getCurDebugLoc() const {
590 return CurInst ? CurInst->getDebugLoc() : DebugLoc();
593 unsigned getSDNodeOrder() const { return SDNodeOrder; }
595 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
597 void visit(const Instruction &I);
599 void visit(unsigned Opcode, const User &I);
601 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
602 // generate the debug data structures now that we've seen its definition.
603 void resolveDanglingDebugInfo(const Value *V, SDValue Val);
604 SDValue getValue(const Value *V);
605 SDValue getNonRegisterValue(const Value *V);
606 SDValue getValueImpl(const Value *V);
608 void setValue(const Value *V, SDValue NewN) {
609 SDValue &N = NodeMap[V];
610 assert(!N.getNode() && "Already set a value for this node!");
614 void setUnusedArgValue(const Value *V, SDValue NewN) {
615 SDValue &N = UnusedArgNodeMap[V];
616 assert(!N.getNode() && "Already set a value for this node!");
620 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
621 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
622 MachineBasicBlock *SwitchBB, unsigned Opc,
623 uint32_t TW, uint32_t FW);
624 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
625 MachineBasicBlock *FBB,
626 MachineBasicBlock *CurBB,
627 MachineBasicBlock *SwitchBB,
628 uint32_t TW, uint32_t FW);
629 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
630 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
631 void CopyToExportRegsIfNeeded(const Value *V);
632 void ExportFromCurrentBlock(const Value *V);
633 void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
634 MachineBasicBlock *LandingPad = nullptr);
636 std::pair<SDValue, SDValue> LowerCallOperands(const CallInst &CI,
640 bool useVoidTy = false);
642 /// UpdateSplitBlock - When an MBB was split during scheduling, update the
643 /// references that need to refer to the last resulting block.
644 void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
647 // Terminator instructions.
648 void visitRet(const ReturnInst &I);
649 void visitBr(const BranchInst &I);
650 void visitSwitch(const SwitchInst &I);
651 void visitIndirectBr(const IndirectBrInst &I);
652 void visitUnreachable(const UnreachableInst &I);
654 // Helpers for visitSwitch
655 bool handleSmallSwitchRange(CaseRec& CR,
656 CaseRecVector& WorkList,
658 MachineBasicBlock* Default,
659 MachineBasicBlock *SwitchBB);
660 bool handleJTSwitchCase(CaseRec& CR,
661 CaseRecVector& WorkList,
663 MachineBasicBlock* Default,
664 MachineBasicBlock *SwitchBB);
665 bool handleBTSplitSwitchCase(CaseRec& CR,
666 CaseRecVector& WorkList,
668 MachineBasicBlock* Default,
669 MachineBasicBlock *SwitchBB);
670 bool handleBitTestsSwitchCase(CaseRec& CR,
671 CaseRecVector& WorkList,
673 MachineBasicBlock* Default,
674 MachineBasicBlock *SwitchBB);
676 uint32_t getEdgeWeight(const MachineBasicBlock *Src,
677 const MachineBasicBlock *Dst) const;
678 void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
679 uint32_t Weight = 0);
681 void visitSwitchCase(CaseBlock &CB,
682 MachineBasicBlock *SwitchBB);
683 void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
684 MachineBasicBlock *ParentBB);
685 void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
686 void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
687 void visitBitTestCase(BitTestBlock &BB,
688 MachineBasicBlock* NextMBB,
689 uint32_t BranchWeightToNext,
692 MachineBasicBlock *SwitchBB);
693 void visitJumpTable(JumpTable &JT);
694 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
695 MachineBasicBlock *SwitchBB);
698 // These all get lowered before this pass.
699 void visitInvoke(const InvokeInst &I);
700 void visitResume(const ResumeInst &I);
702 void visitBinary(const User &I, unsigned OpCode);
703 void visitShift(const User &I, unsigned Opcode);
704 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
705 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
706 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
707 void visitFSub(const User &I);
708 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
709 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
710 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
711 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
712 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
713 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
714 void visitSDiv(const User &I);
715 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
716 void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
717 void visitOr (const User &I) { visitBinary(I, ISD::OR); }
718 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
719 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
720 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
721 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
722 void visitICmp(const User &I);
723 void visitFCmp(const User &I);
724 // Visit the conversion instructions
725 void visitTrunc(const User &I);
726 void visitZExt(const User &I);
727 void visitSExt(const User &I);
728 void visitFPTrunc(const User &I);
729 void visitFPExt(const User &I);
730 void visitFPToUI(const User &I);
731 void visitFPToSI(const User &I);
732 void visitUIToFP(const User &I);
733 void visitSIToFP(const User &I);
734 void visitPtrToInt(const User &I);
735 void visitIntToPtr(const User &I);
736 void visitBitCast(const User &I);
737 void visitAddrSpaceCast(const User &I);
739 void visitExtractElement(const User &I);
740 void visitInsertElement(const User &I);
741 void visitShuffleVector(const User &I);
743 void visitExtractValue(const ExtractValueInst &I);
744 void visitInsertValue(const InsertValueInst &I);
745 void visitLandingPad(const LandingPadInst &I);
747 void visitGetElementPtr(const User &I);
748 void visitSelect(const User &I);
750 void visitAlloca(const AllocaInst &I);
751 void visitLoad(const LoadInst &I);
752 void visitStore(const StoreInst &I);
753 void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
754 void visitAtomicRMW(const AtomicRMWInst &I);
755 void visitFence(const FenceInst &I);
756 void visitPHI(const PHINode &I);
757 void visitCall(const CallInst &I);
758 bool visitMemCmpCall(const CallInst &I);
759 bool visitMemChrCall(const CallInst &I);
760 bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
761 bool visitStrCmpCall(const CallInst &I);
762 bool visitStrLenCall(const CallInst &I);
763 bool visitStrNLenCall(const CallInst &I);
764 bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
765 void visitAtomicLoad(const LoadInst &I);
766 void visitAtomicStore(const StoreInst &I);
768 void visitInlineAsm(ImmutableCallSite CS);
769 const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
770 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
772 void visitVAStart(const CallInst &I);
773 void visitVAArg(const VAArgInst &I);
774 void visitVAEnd(const CallInst &I);
775 void visitVACopy(const CallInst &I);
776 void visitStackmap(const CallInst &I);
777 void visitPatchpoint(const CallInst &I);
779 void visitUserOp1(const Instruction &I) {
780 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
782 void visitUserOp2(const Instruction &I) {
783 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
786 void processIntegerCallValue(const Instruction &I,
787 SDValue Value, bool IsSigned);
789 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
791 /// EmitFuncArgumentDbgValue - If V is an function argument then create
792 /// corresponding DBG_VALUE machine instruction for it now. At the end of
793 /// instruction selection, they will be inserted to the entry BB.
794 bool EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
795 int64_t Offset, bool IsIndirect,
799 } // end namespace llvm