1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #ifndef SELECTIONDAGBUILDER_H
15 #define SELECTIONDAGBUILDER_H
17 #include "llvm/Constants.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/Support/CallSite.h"
27 #include "llvm/Support/ErrorHandling.h"
39 class ExtractElementInst;
40 class ExtractValueInst;
47 class FunctionLoweringInfo;
48 class GetElementPtrInst;
54 class InsertElementInst;
55 class InsertValueInst;
58 class MachineBasicBlock;
59 class MachineFunction;
61 class MachineRegisterInfo;
65 class SDISelAsmOperandInfo;
68 class ShuffleVectorInst;
76 class UnreachableInst;
81 //===----------------------------------------------------------------------===//
82 /// SelectionDAGBuilder - This is the common target-independent lowering
83 /// implementation that is parameterized by a TargetLowering object.
84 /// Also, targets can overload any lowering method.
86 class SelectionDAGBuilder {
87 MachineBasicBlock *CurMBB;
89 /// CurDebugLoc - current file + line number. Changes as we build the DAG.
92 DenseMap<const Value*, SDValue> NodeMap;
95 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
96 /// them up and then emit token factor nodes when possible. This allows us to
97 /// get simple disambiguation between loads without worrying about alias
99 SmallVector<SDValue, 8> PendingLoads;
102 /// PendingExports - CopyToReg nodes that copy values to virtual registers
103 /// for export to other blocks need to be emitted before any terminator
104 /// instruction, but they have no other ordering requirements. We bunch them
105 /// up and the emit a single tokenfactor for them just before terminator
107 SmallVector<SDValue, 8> PendingExports;
109 /// SDNodeOrder - A unique monotonically increasing number used to order the
110 /// SDNodes we create.
111 unsigned SDNodeOrder;
113 /// Case - A struct to record the Value for a switch case, and the
114 /// case's target basic block.
118 MachineBasicBlock* BB;
120 Case() : Low(0), High(0), BB(0) { }
121 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
122 Low(low), High(high), BB(bb) { }
124 const APInt &rHigh = cast<ConstantInt>(High)->getValue();
125 const APInt &rLow = cast<ConstantInt>(Low)->getValue();
126 return (rHigh - rLow + 1ULL);
132 MachineBasicBlock* BB;
135 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
136 Mask(mask), BB(bb), Bits(bits) { }
139 typedef std::vector<Case> CaseVector;
140 typedef std::vector<CaseBits> CaseBitsVector;
141 typedef CaseVector::iterator CaseItr;
142 typedef std::pair<CaseItr, CaseItr> CaseRange;
144 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
145 /// of conditional branches.
147 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
148 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
150 /// CaseBB - The MBB in which to emit the compare and branch
151 MachineBasicBlock *CaseBB;
152 /// LT, GE - If nonzero, we know the current case value must be less-than or
153 /// greater-than-or-equal-to these Constants.
156 /// Range - A pair of iterators representing the range of case values to be
157 /// processed at this point in the binary search tree.
161 typedef std::vector<CaseRec> CaseRecVector;
163 /// The comparison function for sorting the switch case values in the vector.
164 /// WARNING: Case ranges should be disjoint!
166 bool operator()(const Case &C1, const Case &C2) {
167 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
168 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
169 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
170 return CI1->getValue().slt(CI2->getValue());
175 bool operator()(const CaseBits &C1, const CaseBits &C2) {
176 return C1.Bits > C2.Bits;
180 size_t Clusterify(CaseVector &Cases, const SwitchInst &SI);
182 /// CaseBlock - This structure is used to communicate between
183 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
184 /// blocks needed by multi-case switch statements.
186 CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
187 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
188 MachineBasicBlock *me)
189 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
190 TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
191 // CC - the condition code to use for the case block's setcc node
193 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
194 // Emit by default LHS op RHS. MHS is used for range comparisons:
195 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
196 Value *CmpLHS, *CmpMHS, *CmpRHS;
197 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
198 MachineBasicBlock *TrueBB, *FalseBB;
199 // ThisBB - the block into which to emit the code for the setcc and branches
200 MachineBasicBlock *ThisBB;
203 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
204 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
206 /// Reg - the virtual register containing the index of the jump table entry
209 /// JTI - the JumpTableIndex for this jump table in the function.
211 /// MBB - the MBB into which to emit the code for the indirect jump.
212 MachineBasicBlock *MBB;
213 /// Default - the MBB of the default bb, which is a successor of the range
214 /// check MBB. This is when updating PHI nodes in successors.
215 MachineBasicBlock *Default;
217 struct JumpTableHeader {
218 JumpTableHeader(APInt F, APInt L, Value *SV, MachineBasicBlock *H,
220 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
224 MachineBasicBlock *HeaderBB;
227 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
230 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
231 Mask(M), ThisBB(T), TargetBB(Tr) { }
233 MachineBasicBlock *ThisBB;
234 MachineBasicBlock *TargetBB;
237 typedef SmallVector<BitTestCase, 3> BitTestInfo;
239 struct BitTestBlock {
240 BitTestBlock(APInt F, APInt R, Value* SV,
242 MachineBasicBlock* P, MachineBasicBlock* D,
243 const BitTestInfo& C):
244 First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
245 Parent(P), Default(D), Cases(C) { }
251 MachineBasicBlock *Parent;
252 MachineBasicBlock *Default;
257 // TLI - This is information that describes the available target features we
258 // need for lowering. This indicates when operations are unavailable,
259 // implemented with a libcall, etc.
262 const TargetData *TD;
265 /// SwitchCases - Vector of CaseBlock structures used to communicate
266 /// SwitchInst code generation information.
267 std::vector<CaseBlock> SwitchCases;
268 /// JTCases - Vector of JumpTable structures used to communicate
269 /// SwitchInst code generation information.
270 std::vector<JumpTableBlock> JTCases;
271 /// BitTestCases - Vector of BitTestBlock structures used to communicate
272 /// SwitchInst code generation information.
273 std::vector<BitTestBlock> BitTestCases;
275 /// PHINodesToUpdate - A list of phi instructions whose operand list will
276 /// be updated after processing the current basic block.
277 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
279 /// EdgeMapping - If an edge from CurMBB to any MBB is changed (e.g. due to
280 /// scheduler custom lowering), track the change here.
281 DenseMap<MachineBasicBlock*, MachineBasicBlock*> EdgeMapping;
283 // Emit PHI-node-operand constants only once even if used by multiple
285 DenseMap<Constant*, unsigned> ConstantsOut;
287 /// FuncInfo - Information about the function as a whole.
289 FunctionLoweringInfo &FuncInfo;
291 /// OptLevel - What optimization level we're generating code for.
293 CodeGenOpt::Level OptLevel;
295 /// GFI - Garbage collection metadata for the function.
298 /// HasTailCall - This is set to true if a call in the current
299 /// block has been translated as a tail call. In this case,
300 /// no subsequent DAG nodes should be created.
304 LLVMContext *Context;
306 SelectionDAGBuilder(SelectionDAG &dag, TargetLowering &tli,
307 FunctionLoweringInfo &funcinfo,
308 CodeGenOpt::Level ol)
309 : CurDebugLoc(DebugLoc::getUnknownLoc()), SDNodeOrder(0),
310 TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
312 Context(dag.getContext()) {
315 void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
317 /// clear - Clear out the curret SelectionDAG and the associated
318 /// state and prepare this SelectionDAGBuilder object to be used
319 /// for a new block. This doesn't clear out information about
320 /// additional blocks that are needed to complete switch lowering
321 /// or PHI node updating; that information is cleared out as it is
325 /// getRoot - Return the current virtual root of the Selection DAG,
326 /// flushing any PendingLoad items. This must be done before emitting
327 /// a store or any other node that may need to be ordered after any
328 /// prior load instructions.
332 /// getControlRoot - Similar to getRoot, but instead of flushing all the
333 /// PendingLoad items, flush all the PendingExports items. It is necessary
334 /// to do this before emitting a terminator instruction.
336 SDValue getControlRoot();
338 DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
339 void setCurDebugLoc(DebugLoc dl) { CurDebugLoc = dl; }
341 unsigned getSDNodeOrder() const { return SDNodeOrder; }
343 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
345 /// AssignOrderingToNode - Assign an ordering to the node. The order is gotten
346 /// from how the code appeared in the source. The ordering is used by the
347 /// scheduler to effectively turn off scheduling.
348 void AssignOrderingToNode(const SDNode *Node);
350 void visit(Instruction &I);
352 void visit(unsigned Opcode, User &I);
354 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
356 SDValue getValue(const Value *V);
358 void setValue(const Value *V, SDValue NewN) {
359 SDValue &N = NodeMap[V];
360 assert(N.getNode() == 0 && "Already set a value for this node!");
364 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
365 std::set<unsigned> &OutputRegs,
366 std::set<unsigned> &InputRegs);
368 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
369 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
371 void EmitBranchForMergedCondition(Value *Cond, MachineBasicBlock *TBB,
372 MachineBasicBlock *FBB,
373 MachineBasicBlock *CurBB);
374 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
375 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
376 void CopyToExportRegsIfNeeded(Value *V);
377 void ExportFromCurrentBlock(Value *V);
378 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
379 MachineBasicBlock *LandingPad = NULL);
382 // Terminator instructions.
383 void visitRet(ReturnInst &I);
384 void visitBr(BranchInst &I);
385 void visitSwitch(SwitchInst &I);
386 void visitIndirectBr(IndirectBrInst &I);
387 void visitUnreachable(UnreachableInst &I) { /* noop */ }
389 // Helpers for visitSwitch
390 bool handleSmallSwitchRange(CaseRec& CR,
391 CaseRecVector& WorkList,
393 MachineBasicBlock* Default);
394 bool handleJTSwitchCase(CaseRec& CR,
395 CaseRecVector& WorkList,
397 MachineBasicBlock* Default);
398 bool handleBTSplitSwitchCase(CaseRec& CR,
399 CaseRecVector& WorkList,
401 MachineBasicBlock* Default);
402 bool handleBitTestsSwitchCase(CaseRec& CR,
403 CaseRecVector& WorkList,
405 MachineBasicBlock* Default);
407 void visitSwitchCase(CaseBlock &CB);
408 void visitBitTestHeader(BitTestBlock &B);
409 void visitBitTestCase(MachineBasicBlock* NextMBB,
412 void visitJumpTable(JumpTable &JT);
413 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH);
416 // These all get lowered before this pass.
417 void visitInvoke(InvokeInst &I);
418 void visitUnwind(UnwindInst &I);
420 void visitBinary(User &I, unsigned OpCode);
421 void visitShift(User &I, unsigned Opcode);
422 void visitAdd(User &I) { visitBinary(I, ISD::ADD); }
423 void visitFAdd(User &I) { visitBinary(I, ISD::FADD); }
424 void visitSub(User &I) { visitBinary(I, ISD::SUB); }
425 void visitFSub(User &I);
426 void visitMul(User &I) { visitBinary(I, ISD::MUL); }
427 void visitFMul(User &I) { visitBinary(I, ISD::FMUL); }
428 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
429 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
430 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
431 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
432 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
433 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
434 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
435 void visitOr (User &I) { visitBinary(I, ISD::OR); }
436 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
437 void visitShl (User &I) { visitShift(I, ISD::SHL); }
438 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
439 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
440 void visitICmp(User &I);
441 void visitFCmp(User &I);
442 // Visit the conversion instructions
443 void visitTrunc(User &I);
444 void visitZExt(User &I);
445 void visitSExt(User &I);
446 void visitFPTrunc(User &I);
447 void visitFPExt(User &I);
448 void visitFPToUI(User &I);
449 void visitFPToSI(User &I);
450 void visitUIToFP(User &I);
451 void visitSIToFP(User &I);
452 void visitPtrToInt(User &I);
453 void visitIntToPtr(User &I);
454 void visitBitCast(User &I);
456 void visitExtractElement(User &I);
457 void visitInsertElement(User &I);
458 void visitShuffleVector(User &I);
460 void visitExtractValue(ExtractValueInst &I);
461 void visitInsertValue(InsertValueInst &I);
463 void visitGetElementPtr(User &I);
464 void visitSelect(User &I);
466 void visitAlloca(AllocaInst &I);
467 void visitLoad(LoadInst &I);
468 void visitStore(StoreInst &I);
469 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
470 void visitCall(CallInst &I);
471 bool visitMemCmpCall(CallInst &I);
473 void visitInlineAsm(CallSite CS);
474 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
475 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
477 void visitPow(CallInst &I);
478 void visitExp2(CallInst &I);
479 void visitExp(CallInst &I);
480 void visitLog(CallInst &I);
481 void visitLog2(CallInst &I);
482 void visitLog10(CallInst &I);
484 void visitVAStart(CallInst &I);
485 void visitVAArg(VAArgInst &I);
486 void visitVAEnd(CallInst &I);
487 void visitVACopy(CallInst &I);
489 void visitUserOp1(Instruction &I) {
490 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
492 void visitUserOp2(Instruction &I) {
493 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
496 const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
497 const char *implVisitAluOverflow(CallInst &I, ISD::NodeType Op);
500 } // end namespace llvm