1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #ifndef SELECTIONDAGBUILDER_H
15 #define SELECTIONDAGBUILDER_H
17 #include "llvm/Constants.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/Support/CallSite.h"
27 #include "llvm/Support/ErrorHandling.h"
40 class ExtractElementInst;
41 class ExtractValueInst;
48 class FunctionLoweringInfo;
49 class GetElementPtrInst;
55 class InsertElementInst;
56 class InsertValueInst;
59 class MachineBasicBlock;
61 class MachineRegisterInfo;
66 class SDISelAsmOperandInfo;
69 class ShuffleVectorInst;
77 class UnreachableInst;
82 //===----------------------------------------------------------------------===//
83 /// SelectionDAGBuilder - This is the common target-independent lowering
84 /// implementation that is parameterized by a TargetLowering object.
86 class SelectionDAGBuilder {
87 /// CurDebugLoc - current file + line number. Changes as we build the DAG.
90 DenseMap<const Value*, SDValue> NodeMap;
93 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
94 /// them up and then emit token factor nodes when possible. This allows us to
95 /// get simple disambiguation between loads without worrying about alias
97 SmallVector<SDValue, 8> PendingLoads;
100 /// PendingExports - CopyToReg nodes that copy values to virtual registers
101 /// for export to other blocks need to be emitted before any terminator
102 /// instruction, but they have no other ordering requirements. We bunch them
103 /// up and the emit a single tokenfactor for them just before terminator
105 SmallVector<SDValue, 8> PendingExports;
107 /// SDNodeOrder - A unique monotonically increasing number used to order the
108 /// SDNodes we create.
109 unsigned SDNodeOrder;
111 /// Case - A struct to record the Value for a switch case, and the
112 /// case's target basic block.
116 MachineBasicBlock* BB;
118 Case() : Low(0), High(0), BB(0) { }
119 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
120 Low(low), High(high), BB(bb) { }
122 const APInt &rHigh = cast<ConstantInt>(High)->getValue();
123 const APInt &rLow = cast<ConstantInt>(Low)->getValue();
124 return (rHigh - rLow + 1ULL);
130 MachineBasicBlock* BB;
133 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
134 Mask(mask), BB(bb), Bits(bits) { }
137 typedef std::vector<Case> CaseVector;
138 typedef std::vector<CaseBits> CaseBitsVector;
139 typedef CaseVector::iterator CaseItr;
140 typedef std::pair<CaseItr, CaseItr> CaseRange;
142 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
143 /// of conditional branches.
145 CaseRec(MachineBasicBlock *bb, const Constant *lt, const Constant *ge,
147 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
149 /// CaseBB - The MBB in which to emit the compare and branch
150 MachineBasicBlock *CaseBB;
151 /// LT, GE - If nonzero, we know the current case value must be less-than or
152 /// greater-than-or-equal-to these Constants.
155 /// Range - A pair of iterators representing the range of case values to be
156 /// processed at this point in the binary search tree.
160 typedef std::vector<CaseRec> CaseRecVector;
162 /// The comparison function for sorting the switch case values in the vector.
163 /// WARNING: Case ranges should be disjoint!
165 bool operator()(const Case &C1, const Case &C2) {
166 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
167 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
168 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
169 return CI1->getValue().slt(CI2->getValue());
174 bool operator()(const CaseBits &C1, const CaseBits &C2) {
175 return C1.Bits > C2.Bits;
179 size_t Clusterify(CaseVector &Cases, const SwitchInst &SI);
181 /// CaseBlock - This structure is used to communicate between
182 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
183 /// blocks needed by multi-case switch statements.
185 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
186 const Value *cmpmiddle,
187 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
188 MachineBasicBlock *me)
189 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
190 TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
191 // CC - the condition code to use for the case block's setcc node
193 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
194 // Emit by default LHS op RHS. MHS is used for range comparisons:
195 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
196 const Value *CmpLHS, *CmpMHS, *CmpRHS;
197 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
198 MachineBasicBlock *TrueBB, *FalseBB;
199 // ThisBB - the block into which to emit the code for the setcc and branches
200 MachineBasicBlock *ThisBB;
203 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
204 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
206 /// Reg - the virtual register containing the index of the jump table entry
209 /// JTI - the JumpTableIndex for this jump table in the function.
211 /// MBB - the MBB into which to emit the code for the indirect jump.
212 MachineBasicBlock *MBB;
213 /// Default - the MBB of the default bb, which is a successor of the range
214 /// check MBB. This is when updating PHI nodes in successors.
215 MachineBasicBlock *Default;
217 struct JumpTableHeader {
218 JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
220 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
224 MachineBasicBlock *HeaderBB;
227 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
230 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
231 Mask(M), ThisBB(T), TargetBB(Tr) { }
233 MachineBasicBlock *ThisBB;
234 MachineBasicBlock *TargetBB;
237 typedef SmallVector<BitTestCase, 3> BitTestInfo;
239 struct BitTestBlock {
240 BitTestBlock(APInt F, APInt R, const Value* SV,
242 MachineBasicBlock* P, MachineBasicBlock* D,
243 const BitTestInfo& C):
244 First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
245 Parent(P), Default(D), Cases(C) { }
251 MachineBasicBlock *Parent;
252 MachineBasicBlock *Default;
257 // TLI - This is information that describes the available target features we
258 // need for lowering. This indicates when operations are unavailable,
259 // implemented with a libcall, etc.
260 const TargetMachine &TM;
261 const TargetLowering &TLI;
263 const TargetData *TD;
266 /// SwitchCases - Vector of CaseBlock structures used to communicate
267 /// SwitchInst code generation information.
268 std::vector<CaseBlock> SwitchCases;
269 /// JTCases - Vector of JumpTable structures used to communicate
270 /// SwitchInst code generation information.
271 std::vector<JumpTableBlock> JTCases;
272 /// BitTestCases - Vector of BitTestBlock structures used to communicate
273 /// SwitchInst code generation information.
274 std::vector<BitTestBlock> BitTestCases;
276 /// EdgeMapping - If an edge from CurMBB to any MBB is changed (e.g. due to
277 /// scheduler custom lowering), track the change here.
278 DenseMap<MachineBasicBlock*, MachineBasicBlock*> EdgeMapping;
280 // Emit PHI-node-operand constants only once even if used by multiple
282 DenseMap<const Constant *, unsigned> ConstantsOut;
284 /// FuncInfo - Information about the function as a whole.
286 FunctionLoweringInfo &FuncInfo;
288 /// OptLevel - What optimization level we're generating code for.
290 CodeGenOpt::Level OptLevel;
292 /// GFI - Garbage collection metadata for the function.
295 /// HasTailCall - This is set to true if a call in the current
296 /// block has been translated as a tail call. In this case,
297 /// no subsequent DAG nodes should be created.
301 LLVMContext *Context;
303 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
304 CodeGenOpt::Level ol)
305 : SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
306 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
307 HasTailCall(false), Context(dag.getContext()) {
310 void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
312 /// clear - Clear out the current SelectionDAG and the associated
313 /// state and prepare this SelectionDAGBuilder object to be used
314 /// for a new block. This doesn't clear out information about
315 /// additional blocks that are needed to complete switch lowering
316 /// or PHI node updating; that information is cleared out as it is
320 /// getRoot - Return the current virtual root of the Selection DAG,
321 /// flushing any PendingLoad items. This must be done before emitting
322 /// a store or any other node that may need to be ordered after any
323 /// prior load instructions.
327 /// getControlRoot - Similar to getRoot, but instead of flushing all the
328 /// PendingLoad items, flush all the PendingExports items. It is necessary
329 /// to do this before emitting a terminator instruction.
331 SDValue getControlRoot();
333 DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
335 unsigned getSDNodeOrder() const { return SDNodeOrder; }
337 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
339 /// AssignOrderingToNode - Assign an ordering to the node. The order is gotten
340 /// from how the code appeared in the source. The ordering is used by the
341 /// scheduler to effectively turn off scheduling.
342 void AssignOrderingToNode(const SDNode *Node);
344 void visit(const Instruction &I);
346 void visit(unsigned Opcode, const User &I);
348 SDValue getValue(const Value *V);
350 void setValue(const Value *V, SDValue NewN) {
351 SDValue &N = NodeMap[V];
352 assert(N.getNode() == 0 && "Already set a value for this node!");
356 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
357 std::set<unsigned> &OutputRegs,
358 std::set<unsigned> &InputRegs);
360 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
361 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
362 MachineBasicBlock *SwitchBB, unsigned Opc);
363 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
364 MachineBasicBlock *FBB,
365 MachineBasicBlock *CurBB,
366 MachineBasicBlock *SwitchBB);
367 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
368 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
369 void CopyToExportRegsIfNeeded(const Value *V);
370 void ExportFromCurrentBlock(const Value *V);
371 void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
372 MachineBasicBlock *LandingPad = NULL);
375 // Terminator instructions.
376 void visitRet(const ReturnInst &I);
377 void visitBr(const BranchInst &I);
378 void visitSwitch(const SwitchInst &I);
379 void visitIndirectBr(const IndirectBrInst &I);
380 void visitUnreachable(const UnreachableInst &I) { /* noop */ }
382 // Helpers for visitSwitch
383 bool handleSmallSwitchRange(CaseRec& CR,
384 CaseRecVector& WorkList,
386 MachineBasicBlock* Default,
387 MachineBasicBlock *SwitchBB);
388 bool handleJTSwitchCase(CaseRec& CR,
389 CaseRecVector& WorkList,
391 MachineBasicBlock* Default,
392 MachineBasicBlock *SwitchBB);
393 bool handleBTSplitSwitchCase(CaseRec& CR,
394 CaseRecVector& WorkList,
396 MachineBasicBlock* Default,
397 MachineBasicBlock *SwitchBB);
398 bool handleBitTestsSwitchCase(CaseRec& CR,
399 CaseRecVector& WorkList,
401 MachineBasicBlock* Default,
402 MachineBasicBlock *SwitchBB);
404 void visitSwitchCase(CaseBlock &CB,
405 MachineBasicBlock *SwitchBB);
406 void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
407 void visitBitTestCase(MachineBasicBlock* NextMBB,
410 MachineBasicBlock *SwitchBB);
411 void visitJumpTable(JumpTable &JT);
412 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
413 MachineBasicBlock *SwitchBB);
416 // These all get lowered before this pass.
417 void visitInvoke(const InvokeInst &I);
418 void visitUnwind(const UnwindInst &I);
420 void visitBinary(const User &I, unsigned OpCode);
421 void visitShift(const User &I, unsigned Opcode);
422 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
423 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
424 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
425 void visitFSub(const User &I);
426 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
427 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
428 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
429 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
430 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
431 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
432 void visitSDiv(const User &I) { visitBinary(I, ISD::SDIV); }
433 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
434 void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
435 void visitOr (const User &I) { visitBinary(I, ISD::OR); }
436 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
437 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
438 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
439 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
440 void visitICmp(const User &I);
441 void visitFCmp(const User &I);
442 // Visit the conversion instructions
443 void visitTrunc(const User &I);
444 void visitZExt(const User &I);
445 void visitSExt(const User &I);
446 void visitFPTrunc(const User &I);
447 void visitFPExt(const User &I);
448 void visitFPToUI(const User &I);
449 void visitFPToSI(const User &I);
450 void visitUIToFP(const User &I);
451 void visitSIToFP(const User &I);
452 void visitPtrToInt(const User &I);
453 void visitIntToPtr(const User &I);
454 void visitBitCast(const User &I);
456 void visitExtractElement(const User &I);
457 void visitInsertElement(const User &I);
458 void visitShuffleVector(const User &I);
460 void visitExtractValue(const ExtractValueInst &I);
461 void visitInsertValue(const InsertValueInst &I);
463 void visitGetElementPtr(const User &I);
464 void visitSelect(const User &I);
466 void visitAlloca(const AllocaInst &I);
467 void visitLoad(const LoadInst &I);
468 void visitStore(const StoreInst &I);
469 void visitPHI(const PHINode &I);
470 void visitCall(const CallInst &I);
471 bool visitMemCmpCall(const CallInst &I);
473 void visitInlineAsm(ImmutableCallSite CS);
474 const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
475 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
477 void visitPow(const CallInst &I);
478 void visitExp2(const CallInst &I);
479 void visitExp(const CallInst &I);
480 void visitLog(const CallInst &I);
481 void visitLog2(const CallInst &I);
482 void visitLog10(const CallInst &I);
484 void visitVAStart(const CallInst &I);
485 void visitVAArg(const VAArgInst &I);
486 void visitVAEnd(const CallInst &I);
487 void visitVACopy(const CallInst &I);
489 void visitUserOp1(const Instruction &I) {
490 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
492 void visitUserOp2(const Instruction &I) {
493 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
496 const char *implVisitBinaryAtomic(const CallInst& I, ISD::NodeType Op);
497 const char *implVisitAluOverflow(const CallInst &I, ISD::NodeType Op);
499 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
501 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a
502 /// function argument, create the corresponding DBG_VALUE machine instruction
503 /// for it now. At the end of instruction selection, they will be inserted to
505 bool EmitFuncArgumentDbgValue(const DbgValueInst &DI,
506 const Value *V, MDNode *Variable,
507 uint64_t Offset, SDValue &N);
510 } // end namespace llvm