1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
15 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
17 #include "StatepointLowering.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGNodes.h"
23 #include "llvm/IR/CallSite.h"
24 #include "llvm/IR/Statepoint.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Target/TargetLowering.h"
32 class AddrSpaceCastInst;
40 class ExtractElementInst;
41 class ExtractValueInst;
48 class FunctionLoweringInfo;
49 class GetElementPtrInst;
55 class InsertElementInst;
56 class InsertValueInst;
59 class MachineBasicBlock;
61 class MachineRegisterInfo;
70 class ShuffleVectorInst;
75 class TargetLibraryInfo;
79 class UnreachableInst;
83 //===----------------------------------------------------------------------===//
84 /// SelectionDAGBuilder - This is the common target-independent lowering
85 /// implementation that is parameterized by a TargetLowering object.
87 class SelectionDAGBuilder {
88 /// CurInst - The current instruction being visited
89 const Instruction *CurInst;
91 DenseMap<const Value*, SDValue> NodeMap;
93 /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
94 /// to preserve debug information for incoming arguments.
95 DenseMap<const Value*, SDValue> UnusedArgNodeMap;
97 /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
98 class DanglingDebugInfo {
99 const DbgValueInst* DI;
101 unsigned SDNodeOrder;
103 DanglingDebugInfo() : DI(nullptr), dl(DebugLoc()), SDNodeOrder(0) { }
104 DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
105 DI(di), dl(DL), SDNodeOrder(SDNO) { }
106 const DbgValueInst* getDI() { return DI; }
107 DebugLoc getdl() { return dl; }
108 unsigned getSDNodeOrder() { return SDNodeOrder; }
111 /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
112 /// yet seen the referent. We defer handling these until we do see it.
113 DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
116 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
117 /// them up and then emit token factor nodes when possible. This allows us to
118 /// get simple disambiguation between loads without worrying about alias
120 SmallVector<SDValue, 8> PendingLoads;
122 /// State used while lowering a statepoint sequence (gc_statepoint,
123 /// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details.
124 StatepointLoweringState StatepointLowering;
127 /// PendingExports - CopyToReg nodes that copy values to virtual registers
128 /// for export to other blocks need to be emitted before any terminator
129 /// instruction, but they have no other ordering requirements. We bunch them
130 /// up and the emit a single tokenfactor for them just before terminator
132 SmallVector<SDValue, 8> PendingExports;
134 /// SDNodeOrder - A unique monotonically increasing number used to order the
135 /// SDNodes we create.
136 unsigned SDNodeOrder;
138 enum CaseClusterKind {
139 /// A cluster of adjacent case labels with the same destination, or just one
142 /// A cluster of cases suitable for jump table lowering.
144 /// A cluster of cases suitable for bit test lowering.
148 /// A cluster of case labels.
150 CaseClusterKind Kind;
151 const ConstantInt *Low, *High;
153 MachineBasicBlock *MBB;
154 unsigned JTCasesIndex;
155 unsigned BTCasesIndex;
159 static CaseCluster range(const ConstantInt *Low, const ConstantInt *High,
160 MachineBasicBlock *MBB, uint32_t Weight) {
170 static CaseCluster jumpTable(const ConstantInt *Low,
171 const ConstantInt *High, unsigned JTCasesIndex,
174 C.Kind = CC_JumpTable;
177 C.JTCasesIndex = JTCasesIndex;
182 static CaseCluster bitTests(const ConstantInt *Low, const ConstantInt *High,
183 unsigned BTCasesIndex, uint32_t Weight) {
185 C.Kind = CC_BitTests;
188 C.BTCasesIndex = BTCasesIndex;
194 typedef std::vector<CaseCluster> CaseClusterVector;
195 typedef CaseClusterVector::iterator CaseClusterIt;
199 MachineBasicBlock* BB;
201 uint32_t ExtraWeight;
203 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
205 Mask(mask), BB(bb), Bits(bits), ExtraWeight(Weight) { }
207 CaseBits() : Mask(0), BB(nullptr), Bits(0), ExtraWeight(0) {}
210 typedef std::vector<CaseBits> CaseBitsVector;
212 /// Sort Clusters and merge adjacent cases.
213 void sortAndRangeify(CaseClusterVector &Clusters);
215 /// CaseBlock - This structure is used to communicate between
216 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
217 /// blocks needed by multi-case switch statements.
219 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
220 const Value *cmpmiddle,
221 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
222 MachineBasicBlock *me,
223 uint32_t trueweight = 0, uint32_t falseweight = 0)
224 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
225 TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
226 TrueWeight(trueweight), FalseWeight(falseweight) { }
228 // CC - the condition code to use for the case block's setcc node
231 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
232 // Emit by default LHS op RHS. MHS is used for range comparisons:
233 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
234 const Value *CmpLHS, *CmpMHS, *CmpRHS;
236 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
237 MachineBasicBlock *TrueBB, *FalseBB;
239 // ThisBB - the block into which to emit the code for the setcc and branches
240 MachineBasicBlock *ThisBB;
242 // TrueWeight/FalseWeight - branch weights.
243 uint32_t TrueWeight, FalseWeight;
247 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
248 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
250 /// Reg - the virtual register containing the index of the jump table entry
253 /// JTI - the JumpTableIndex for this jump table in the function.
255 /// MBB - the MBB into which to emit the code for the indirect jump.
256 MachineBasicBlock *MBB;
257 /// Default - the MBB of the default bb, which is a successor of the range
258 /// check MBB. This is when updating PHI nodes in successors.
259 MachineBasicBlock *Default;
261 struct JumpTableHeader {
262 JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
264 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
268 MachineBasicBlock *HeaderBB;
271 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
274 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
276 Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
278 MachineBasicBlock *ThisBB;
279 MachineBasicBlock *TargetBB;
280 uint32_t ExtraWeight;
283 typedef SmallVector<BitTestCase, 3> BitTestInfo;
285 struct BitTestBlock {
286 BitTestBlock(APInt F, APInt R, const Value* SV,
287 unsigned Rg, MVT RgVT, bool E,
288 MachineBasicBlock* P, MachineBasicBlock* D,
290 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
291 Parent(P), Default(D), Cases(std::move(C)) { }
298 MachineBasicBlock *Parent;
299 MachineBasicBlock *Default;
303 /// Minimum jump table density, in percent.
304 enum { MinJumpTableDensity = 40 };
306 /// Check whether a range of clusters is dense enough for a jump table.
307 bool isDense(const CaseClusterVector &Clusters, unsigned *TotalCases,
308 unsigned First, unsigned Last);
310 /// Build a jump table cluster from Clusters[First..Last]. Returns false if it
311 /// decides it's not a good idea.
312 bool buildJumpTable(CaseClusterVector &Clusters, unsigned First,
313 unsigned Last, const SwitchInst *SI,
314 MachineBasicBlock *DefaultMBB, CaseCluster &JTCluster);
316 /// Find clusters of cases suitable for jump table lowering.
317 void findJumpTables(CaseClusterVector &Clusters, const SwitchInst *SI,
318 MachineBasicBlock *DefaultMBB);
320 /// Check whether the range [Low,High] fits in a machine word.
321 bool rangeFitsInWord(const APInt &Low, const APInt &High);
323 /// Check whether these clusters are suitable for lowering with bit tests based
324 /// on the number of destinations, comparison metric, and range.
325 bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
326 const APInt &Low, const APInt &High);
328 /// Build a bit test cluster from Clusters[First..Last]. Returns false if it
329 /// decides it's not a good idea.
330 bool buildBitTests(CaseClusterVector &Clusters, unsigned First, unsigned Last,
331 const SwitchInst *SI, CaseCluster &BTCluster);
333 /// Find clusters of cases suitable for bit test lowering.
334 void findBitTestClusters(CaseClusterVector &Clusters, const SwitchInst *SI);
336 struct SwitchWorkListItem {
337 MachineBasicBlock *MBB;
338 CaseClusterIt FirstCluster;
339 CaseClusterIt LastCluster;
340 const ConstantInt *GE;
341 const ConstantInt *LT;
343 typedef SmallVector<SwitchWorkListItem, 4> SwitchWorkList;
345 /// Emit comparison and split W into two subtrees.
346 void splitWorkItem(SwitchWorkList &WorkList, const SwitchWorkListItem &W,
347 Value *Cond, MachineBasicBlock *SwitchMBB);
350 void lowerWorkItem(SwitchWorkListItem W, Value *Cond,
351 MachineBasicBlock *SwitchMBB,
352 MachineBasicBlock *DefaultMBB);
355 /// A class which encapsulates all of the information needed to generate a
356 /// stack protector check and signals to isel via its state being initialized
357 /// that a stack protector needs to be generated.
359 /// *NOTE* The following is a high level documentation of SelectionDAG Stack
360 /// Protector Generation. The reason that it is placed here is for a lack of
361 /// other good places to stick it.
363 /// High Level Overview of SelectionDAG Stack Protector Generation:
365 /// Previously, generation of stack protectors was done exclusively in the
366 /// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
367 /// splitting basic blocks at the IR level to create the success/failure basic
368 /// blocks in the tail of the basic block in question. As a result of this,
369 /// calls that would have qualified for the sibling call optimization were no
370 /// longer eligible for optimization since said calls were no longer right in
371 /// the "tail position" (i.e. the immediate predecessor of a ReturnInst
374 /// Then it was noticed that since the sibling call optimization causes the
375 /// callee to reuse the caller's stack, if we could delay the generation of
376 /// the stack protector check until later in CodeGen after the sibling call
377 /// decision was made, we get both the tail call optimization and the stack
380 /// A few goals in solving this problem were:
382 /// 1. Preserve the architecture independence of stack protector generation.
384 /// 2. Preserve the normal IR level stack protector check for platforms like
385 /// OpenBSD for which we support platform-specific stack protector
388 /// The main problem that guided the present solution is that one can not
389 /// solve this problem in an architecture independent manner at the IR level
390 /// only. This is because:
392 /// 1. The decision on whether or not to perform a sibling call on certain
393 /// platforms (for instance i386) requires lower level information
394 /// related to available registers that can not be known at the IR level.
396 /// 2. Even if the previous point were not true, the decision on whether to
397 /// perform a tail call is done in LowerCallTo in SelectionDAG which
398 /// occurs after the Stack Protector Pass. As a result, one would need to
399 /// put the relevant callinst into the stack protector check success
400 /// basic block (where the return inst is placed) and then move it back
401 /// later at SelectionDAG/MI time before the stack protector check if the
402 /// tail call optimization failed. The MI level option was nixed
403 /// immediately since it would require platform-specific pattern
404 /// matching. The SelectionDAG level option was nixed because
405 /// SelectionDAG only processes one IR level basic block at a time
406 /// implying one could not create a DAG Combine to move the callinst.
408 /// To get around this problem a few things were realized:
410 /// 1. While one can not handle multiple IR level basic blocks at the
411 /// SelectionDAG Level, one can generate multiple machine basic blocks
412 /// for one IR level basic block. This is how we handle bit tests and
415 /// 2. At the MI level, tail calls are represented via a special return
416 /// MIInst called "tcreturn". Thus if we know the basic block in which we
417 /// wish to insert the stack protector check, we get the correct behavior
418 /// by always inserting the stack protector check right before the return
419 /// statement. This is a "magical transformation" since no matter where
420 /// the stack protector check intrinsic is, we always insert the stack
421 /// protector check code at the end of the BB.
423 /// Given the aforementioned constraints, the following solution was devised:
425 /// 1. On platforms that do not support SelectionDAG stack protector check
426 /// generation, allow for the normal IR level stack protector check
427 /// generation to continue.
429 /// 2. On platforms that do support SelectionDAG stack protector check
432 /// a. Use the IR level stack protector pass to decide if a stack
433 /// protector is required/which BB we insert the stack protector check
434 /// in by reusing the logic already therein. If we wish to generate a
435 /// stack protector check in a basic block, we place a special IR
436 /// intrinsic called llvm.stackprotectorcheck right before the BB's
437 /// returninst or if there is a callinst that could potentially be
438 /// sibling call optimized, before the call inst.
440 /// b. Then when a BB with said intrinsic is processed, we codegen the BB
441 /// normally via SelectBasicBlock. In said process, when we visit the
442 /// stack protector check, we do not actually emit anything into the
443 /// BB. Instead, we just initialize the stack protector descriptor
444 /// class (which involves stashing information/creating the success
445 /// mbbb and the failure mbb if we have not created one for this
446 /// function yet) and export the guard variable that we are going to
449 /// c. After we finish selecting the basic block, in FinishBasicBlock if
450 /// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
451 /// initialized, we first find a splice point in the parent basic block
452 /// before the terminator and then splice the terminator of said basic
453 /// block into the success basic block. Then we code-gen a new tail for
454 /// the parent basic block consisting of the two loads, the comparison,
455 /// and finally two branches to the success/failure basic blocks. We
456 /// conclude by code-gening the failure basic block if we have not
457 /// code-gened it already (all stack protector checks we generate in
458 /// the same function, use the same failure basic block).
459 class StackProtectorDescriptor {
461 StackProtectorDescriptor() : ParentMBB(nullptr), SuccessMBB(nullptr),
462 FailureMBB(nullptr), Guard(nullptr),
465 /// Returns true if all fields of the stack protector descriptor are
466 /// initialized implying that we should/are ready to emit a stack protector.
467 bool shouldEmitStackProtector() const {
468 return ParentMBB && SuccessMBB && FailureMBB && Guard;
471 /// Initialize the stack protector descriptor structure for a new basic
473 void initialize(const BasicBlock *BB,
474 MachineBasicBlock *MBB,
475 const CallInst &StackProtCheckCall) {
476 // Make sure we are not initialized yet.
477 assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
478 "already initialized!");
480 SuccessMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ true);
481 FailureMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ false, FailureMBB);
483 Guard = StackProtCheckCall.getArgOperand(0);
486 /// Reset state that changes when we handle different basic blocks.
488 /// This currently includes:
490 /// 1. The specific basic block we are generating a
491 /// stack protector for (ParentMBB).
493 /// 2. The successor machine basic block that will contain the tail of
494 /// parent mbb after we create the stack protector check (SuccessMBB). This
495 /// BB is visited only on stack protector check success.
496 void resetPerBBState() {
498 SuccessMBB = nullptr;
501 /// Reset state that only changes when we switch functions.
503 /// This currently includes:
505 /// 1. FailureMBB since we reuse the failure code path for all stack
506 /// protector checks created in an individual function.
508 /// 2.The guard variable since the guard variable we are checking against is
510 void resetPerFunctionState() {
511 FailureMBB = nullptr;
515 MachineBasicBlock *getParentMBB() { return ParentMBB; }
516 MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
517 MachineBasicBlock *getFailureMBB() { return FailureMBB; }
518 const Value *getGuard() { return Guard; }
520 unsigned getGuardReg() const { return GuardReg; }
521 void setGuardReg(unsigned R) { GuardReg = R; }
524 /// The basic block for which we are generating the stack protector.
526 /// As a result of stack protector generation, we will splice the
527 /// terminators of this basic block into the successor mbb SuccessMBB and
528 /// replace it with a compare/branch to the successor mbbs
529 /// SuccessMBB/FailureMBB depending on whether or not the stack protector
531 MachineBasicBlock *ParentMBB;
533 /// A basic block visited on stack protector check success that contains the
534 /// terminators of ParentMBB.
535 MachineBasicBlock *SuccessMBB;
537 /// This basic block visited on stack protector check failure that will
538 /// contain a call to __stack_chk_fail().
539 MachineBasicBlock *FailureMBB;
541 /// The guard variable which we will compare against the stored value in the
542 /// stack protector stack slot.
545 /// The virtual register holding the stack guard value.
548 /// Add a successor machine basic block to ParentMBB. If the successor mbb
549 /// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
550 /// block will be created. Assign a large weight if IsLikely is true.
551 MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
552 MachineBasicBlock *ParentMBB,
554 MachineBasicBlock *SuccMBB = nullptr);
558 const TargetMachine &TM;
560 /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling
561 /// nodes without a corresponding SDNode.
562 static const unsigned LowestSDNodeOrder = 1;
565 const DataLayout *DL;
567 const TargetLibraryInfo *LibInfo;
569 /// SwitchCases - Vector of CaseBlock structures used to communicate
570 /// SwitchInst code generation information.
571 std::vector<CaseBlock> SwitchCases;
572 /// JTCases - Vector of JumpTable structures used to communicate
573 /// SwitchInst code generation information.
574 std::vector<JumpTableBlock> JTCases;
575 /// BitTestCases - Vector of BitTestBlock structures used to communicate
576 /// SwitchInst code generation information.
577 std::vector<BitTestBlock> BitTestCases;
578 /// A StackProtectorDescriptor structure used to communicate stack protector
579 /// information in between SelectBasicBlock and FinishBasicBlock.
580 StackProtectorDescriptor SPDescriptor;
582 // Emit PHI-node-operand constants only once even if used by multiple
584 DenseMap<const Constant *, unsigned> ConstantsOut;
586 /// FuncInfo - Information about the function as a whole.
588 FunctionLoweringInfo &FuncInfo;
590 /// OptLevel - What optimization level we're generating code for.
592 CodeGenOpt::Level OptLevel;
594 /// GFI - Garbage collection metadata for the function.
597 /// LPadToCallSiteMap - Map a landing pad to the call site indexes.
598 DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
600 /// HasTailCall - This is set to true if a call in the current
601 /// block has been translated as a tail call. In this case,
602 /// no subsequent DAG nodes should be created.
606 LLVMContext *Context;
608 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
609 CodeGenOpt::Level ol)
610 : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
611 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
615 void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
616 const TargetLibraryInfo *li);
618 /// clear - Clear out the current SelectionDAG and the associated
619 /// state and prepare this SelectionDAGBuilder object to be used
620 /// for a new block. This doesn't clear out information about
621 /// additional blocks that are needed to complete switch lowering
622 /// or PHI node updating; that information is cleared out as it is
626 /// clearDanglingDebugInfo - Clear the dangling debug information
627 /// map. This function is separated from the clear so that debug
628 /// information that is dangling in a basic block can be properly
629 /// resolved in a different basic block. This allows the
630 /// SelectionDAG to resolve dangling debug information attached
632 void clearDanglingDebugInfo();
634 /// getRoot - Return the current virtual root of the Selection DAG,
635 /// flushing any PendingLoad items. This must be done before emitting
636 /// a store or any other node that may need to be ordered after any
637 /// prior load instructions.
641 /// getControlRoot - Similar to getRoot, but instead of flushing all the
642 /// PendingLoad items, flush all the PendingExports items. It is necessary
643 /// to do this before emitting a terminator instruction.
645 SDValue getControlRoot();
647 SDLoc getCurSDLoc() const {
648 return SDLoc(CurInst, SDNodeOrder);
651 DebugLoc getCurDebugLoc() const {
652 return CurInst ? CurInst->getDebugLoc() : DebugLoc();
655 unsigned getSDNodeOrder() const { return SDNodeOrder; }
657 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
659 void visit(const Instruction &I);
661 void visit(unsigned Opcode, const User &I);
663 /// getCopyFromRegs - If there was virtual register allocated for the value V
664 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
665 SDValue getCopyFromRegs(const Value *V, Type *Ty);
667 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
668 // generate the debug data structures now that we've seen its definition.
669 void resolveDanglingDebugInfo(const Value *V, SDValue Val);
670 SDValue getValue(const Value *V);
671 bool findValue(const Value *V) const;
673 SDValue getNonRegisterValue(const Value *V);
674 SDValue getValueImpl(const Value *V);
676 void setValue(const Value *V, SDValue NewN) {
677 SDValue &N = NodeMap[V];
678 assert(!N.getNode() && "Already set a value for this node!");
682 void removeValue(const Value *V) {
683 // This is to support hack in lowerCallFromStatepoint
684 // Should be removed when hack is resolved
688 void setUnusedArgValue(const Value *V, SDValue NewN) {
689 SDValue &N = UnusedArgNodeMap[V];
690 assert(!N.getNode() && "Already set a value for this node!");
694 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
695 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
696 MachineBasicBlock *SwitchBB, unsigned Opc,
697 uint32_t TW, uint32_t FW);
698 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
699 MachineBasicBlock *FBB,
700 MachineBasicBlock *CurBB,
701 MachineBasicBlock *SwitchBB,
702 uint32_t TW, uint32_t FW);
703 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
704 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
705 void CopyToExportRegsIfNeeded(const Value *V);
706 void ExportFromCurrentBlock(const Value *V);
707 void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
708 MachineBasicBlock *LandingPad = nullptr);
710 std::pair<SDValue, SDValue> lowerCallOperands(
711 ImmutableCallSite CS,
716 MachineBasicBlock *LandingPad = nullptr,
717 bool IsPatchPoint = false);
719 /// UpdateSplitBlock - When an MBB was split during scheduling, update the
720 /// references that need to refer to the last resulting block.
721 void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
723 // This function is responsible for the whole statepoint lowering process.
724 // It uniformly handles invoke and call statepoints.
725 void LowerStatepoint(ImmutableStatepoint Statepoint,
726 MachineBasicBlock *LandingPad = nullptr);
728 std::pair<SDValue, SDValue> lowerInvokable(
729 TargetLowering::CallLoweringInfo &CLI,
730 MachineBasicBlock *LandingPad);
732 // Terminator instructions.
733 void visitRet(const ReturnInst &I);
734 void visitBr(const BranchInst &I);
735 void visitSwitch(const SwitchInst &I);
736 void visitIndirectBr(const IndirectBrInst &I);
737 void visitUnreachable(const UnreachableInst &I);
739 uint32_t getEdgeWeight(const MachineBasicBlock *Src,
740 const MachineBasicBlock *Dst) const;
741 void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
742 uint32_t Weight = 0);
744 void visitSwitchCase(CaseBlock &CB,
745 MachineBasicBlock *SwitchBB);
746 void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
747 MachineBasicBlock *ParentBB);
748 void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
749 void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
750 void visitBitTestCase(BitTestBlock &BB,
751 MachineBasicBlock* NextMBB,
752 uint32_t BranchWeightToNext,
755 MachineBasicBlock *SwitchBB);
756 void visitJumpTable(JumpTable &JT);
757 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
758 MachineBasicBlock *SwitchBB);
759 unsigned visitLandingPadClauseBB(GlobalValue *ClauseGV,
760 MachineBasicBlock *LPadMBB);
763 // These all get lowered before this pass.
764 void visitInvoke(const InvokeInst &I);
765 void visitResume(const ResumeInst &I);
767 void visitBinary(const User &I, unsigned OpCode);
768 void visitShift(const User &I, unsigned Opcode);
769 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
770 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
771 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
772 void visitFSub(const User &I);
773 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
774 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
775 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
776 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
777 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
778 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
779 void visitSDiv(const User &I);
780 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
781 void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
782 void visitOr (const User &I) { visitBinary(I, ISD::OR); }
783 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
784 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
785 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
786 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
787 void visitICmp(const User &I);
788 void visitFCmp(const User &I);
789 // Visit the conversion instructions
790 void visitTrunc(const User &I);
791 void visitZExt(const User &I);
792 void visitSExt(const User &I);
793 void visitFPTrunc(const User &I);
794 void visitFPExt(const User &I);
795 void visitFPToUI(const User &I);
796 void visitFPToSI(const User &I);
797 void visitUIToFP(const User &I);
798 void visitSIToFP(const User &I);
799 void visitPtrToInt(const User &I);
800 void visitIntToPtr(const User &I);
801 void visitBitCast(const User &I);
802 void visitAddrSpaceCast(const User &I);
804 void visitExtractElement(const User &I);
805 void visitInsertElement(const User &I);
806 void visitShuffleVector(const User &I);
808 void visitExtractValue(const ExtractValueInst &I);
809 void visitInsertValue(const InsertValueInst &I);
810 void visitLandingPad(const LandingPadInst &I);
812 void visitGetElementPtr(const User &I);
813 void visitSelect(const User &I);
815 void visitAlloca(const AllocaInst &I);
816 void visitLoad(const LoadInst &I);
817 void visitStore(const StoreInst &I);
818 void visitMaskedLoad(const CallInst &I);
819 void visitMaskedStore(const CallInst &I);
820 void visitMaskedGather(const CallInst &I);
821 void visitMaskedScatter(const CallInst &I);
822 void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
823 void visitAtomicRMW(const AtomicRMWInst &I);
824 void visitFence(const FenceInst &I);
825 void visitPHI(const PHINode &I);
826 void visitCall(const CallInst &I);
827 bool visitMemCmpCall(const CallInst &I);
828 bool visitMemChrCall(const CallInst &I);
829 bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
830 bool visitStrCmpCall(const CallInst &I);
831 bool visitStrLenCall(const CallInst &I);
832 bool visitStrNLenCall(const CallInst &I);
833 bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
834 bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode);
835 void visitAtomicLoad(const LoadInst &I);
836 void visitAtomicStore(const StoreInst &I);
838 void visitInlineAsm(ImmutableCallSite CS);
839 const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
840 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
842 void visitVAStart(const CallInst &I);
843 void visitVAArg(const VAArgInst &I);
844 void visitVAEnd(const CallInst &I);
845 void visitVACopy(const CallInst &I);
846 void visitStackmap(const CallInst &I);
847 void visitPatchpoint(ImmutableCallSite CS,
848 MachineBasicBlock *LandingPad = nullptr);
850 // These three are implemented in StatepointLowering.cpp
851 void visitStatepoint(const CallInst &I);
852 void visitGCRelocate(const CallInst &I);
853 void visitGCResult(const CallInst &I);
855 void visitUserOp1(const Instruction &I) {
856 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
858 void visitUserOp2(const Instruction &I) {
859 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
862 void processIntegerCallValue(const Instruction &I,
863 SDValue Value, bool IsSigned);
865 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
867 /// EmitFuncArgumentDbgValue - If V is an function argument then create
868 /// corresponding DBG_VALUE machine instruction for it now. At the end of
869 /// instruction selection, they will be inserted to the entry BB.
870 bool EmitFuncArgumentDbgValue(const Value *V, DILocalVariable *Variable,
871 DIExpression *Expr, DILocation *DL,
872 int64_t Offset, bool IsIndirect,
875 /// Return the next block after MBB, or nullptr if there is none.
876 MachineBasicBlock *NextBlock(MachineBasicBlock *MBB);
878 /// Update the DAG and DAG builder with the relevant information after
879 /// a new root node has been created which could be a tail call.
880 void updateDAGForMaybeTailCall(SDValue MaybeTC);
883 /// RegsForValue - This struct represents the registers (physical or virtual)
884 /// that a particular set of values is assigned, and the type information about
885 /// the value. The most common situation is to represent one value at a time,
886 /// but struct or array values are handled element-wise as multiple values. The
887 /// splitting of aggregates is performed recursively, so that we never have
888 /// aggregate-typed registers. The values at this point do not necessarily have
889 /// legal types, so each value may require one or more registers of some legal
892 struct RegsForValue {
893 /// ValueVTs - The value types of the values, which may not be legal, and
894 /// may need be promoted or synthesized from one or more registers.
896 SmallVector<EVT, 4> ValueVTs;
898 /// RegVTs - The value types of the registers. This is the same size as
899 /// ValueVTs and it records, for each value, what the type of the assigned
900 /// register or registers are. (Individual values are never synthesized
901 /// from more than one type of register.)
903 /// With virtual registers, the contents of RegVTs is redundant with TLI's
904 /// getRegisterType member function, however when with physical registers
905 /// it is necessary to have a separate record of the types.
907 SmallVector<MVT, 4> RegVTs;
909 /// Regs - This list holds the registers assigned to the values.
910 /// Each legal or promoted value requires one register, and each
911 /// expanded value requires multiple registers.
913 SmallVector<unsigned, 4> Regs;
917 RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt);
919 RegsForValue(LLVMContext &Context, const TargetLowering &tli, unsigned Reg,
922 /// append - Add the specified values to this one.
923 void append(const RegsForValue &RHS) {
924 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
925 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
926 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
929 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
930 /// this value and returns the result as a ValueVTs value. This uses
931 /// Chain/Flag as the input and updates them for the output Chain/Flag.
932 /// If the Flag pointer is NULL, no flag is used.
933 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
935 SDValue &Chain, SDValue *Flag,
936 const Value *V = nullptr) const;
938 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the specified
939 /// value into the registers specified by this object. This uses Chain/Flag
940 /// as the input and updates them for the output Chain/Flag. If the Flag
941 /// pointer is nullptr, no flag is used. If V is not nullptr, then it is used
942 /// in printing better diagnostic messages on error.
944 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
945 SDValue *Flag, const Value *V = nullptr,
946 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
948 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
949 /// operand list. This adds the code marker, matching input operand index
950 /// (if applicable), and includes the number of values added into it.
951 void AddInlineAsmOperands(unsigned Kind,
952 bool HasMatching, unsigned MatchingIdx, SDLoc dl,
954 std::vector<SDValue> &Ops) const;
957 } // end namespace llvm