1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #ifndef SELECTIONDAGBUILDER_H
15 #define SELECTIONDAGBUILDER_H
17 #include "llvm/Constants.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/Support/CallSite.h"
27 #include "llvm/Support/ErrorHandling.h"
40 class ExtractElementInst;
41 class ExtractValueInst;
48 class FunctionLoweringInfo;
49 class GetElementPtrInst;
55 class InsertElementInst;
56 class InsertValueInst;
59 class MachineBasicBlock;
61 class MachineRegisterInfo;
66 class SDISelAsmOperandInfo;
69 class ShuffleVectorInst;
77 class UnreachableInst;
82 //===----------------------------------------------------------------------===//
83 /// SelectionDAGBuilder - This is the common target-independent lowering
84 /// implementation that is parameterized by a TargetLowering object.
86 class SelectionDAGBuilder {
87 /// CurDebugLoc - current file + line number. Changes as we build the DAG.
90 DenseMap<const Value*, SDValue> NodeMap;
92 /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
93 /// to preserve debug information for incoming arguments.
94 DenseMap<const Value*, SDValue> UnusedArgNodeMap;
97 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
98 /// them up and then emit token factor nodes when possible. This allows us to
99 /// get simple disambiguation between loads without worrying about alias
101 SmallVector<SDValue, 8> PendingLoads;
104 /// PendingExports - CopyToReg nodes that copy values to virtual registers
105 /// for export to other blocks need to be emitted before any terminator
106 /// instruction, but they have no other ordering requirements. We bunch them
107 /// up and the emit a single tokenfactor for them just before terminator
109 SmallVector<SDValue, 8> PendingExports;
111 /// SDNodeOrder - A unique monotonically increasing number used to order the
112 /// SDNodes we create.
113 unsigned SDNodeOrder;
115 /// Case - A struct to record the Value for a switch case, and the
116 /// case's target basic block.
120 MachineBasicBlock* BB;
122 Case() : Low(0), High(0), BB(0) { }
123 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
124 Low(low), High(high), BB(bb) { }
126 const APInt &rHigh = cast<ConstantInt>(High)->getValue();
127 const APInt &rLow = cast<ConstantInt>(Low)->getValue();
128 return (rHigh - rLow + 1ULL);
134 MachineBasicBlock* BB;
137 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
138 Mask(mask), BB(bb), Bits(bits) { }
141 typedef std::vector<Case> CaseVector;
142 typedef std::vector<CaseBits> CaseBitsVector;
143 typedef CaseVector::iterator CaseItr;
144 typedef std::pair<CaseItr, CaseItr> CaseRange;
146 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
147 /// of conditional branches.
149 CaseRec(MachineBasicBlock *bb, const Constant *lt, const Constant *ge,
151 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
153 /// CaseBB - The MBB in which to emit the compare and branch
154 MachineBasicBlock *CaseBB;
155 /// LT, GE - If nonzero, we know the current case value must be less-than or
156 /// greater-than-or-equal-to these Constants.
159 /// Range - A pair of iterators representing the range of case values to be
160 /// processed at this point in the binary search tree.
164 typedef std::vector<CaseRec> CaseRecVector;
166 /// The comparison function for sorting the switch case values in the vector.
167 /// WARNING: Case ranges should be disjoint!
169 bool operator()(const Case &C1, const Case &C2) {
170 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
171 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
172 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
173 return CI1->getValue().slt(CI2->getValue());
178 bool operator()(const CaseBits &C1, const CaseBits &C2) {
179 return C1.Bits > C2.Bits;
183 size_t Clusterify(CaseVector &Cases, const SwitchInst &SI);
185 /// CaseBlock - This structure is used to communicate between
186 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
187 /// blocks needed by multi-case switch statements.
189 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
190 const Value *cmpmiddle,
191 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
192 MachineBasicBlock *me)
193 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
194 TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
195 // CC - the condition code to use for the case block's setcc node
197 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
198 // Emit by default LHS op RHS. MHS is used for range comparisons:
199 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
200 const Value *CmpLHS, *CmpMHS, *CmpRHS;
201 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
202 MachineBasicBlock *TrueBB, *FalseBB;
203 // ThisBB - the block into which to emit the code for the setcc and branches
204 MachineBasicBlock *ThisBB;
207 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
208 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
210 /// Reg - the virtual register containing the index of the jump table entry
213 /// JTI - the JumpTableIndex for this jump table in the function.
215 /// MBB - the MBB into which to emit the code for the indirect jump.
216 MachineBasicBlock *MBB;
217 /// Default - the MBB of the default bb, which is a successor of the range
218 /// check MBB. This is when updating PHI nodes in successors.
219 MachineBasicBlock *Default;
221 struct JumpTableHeader {
222 JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
224 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
228 MachineBasicBlock *HeaderBB;
231 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
234 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
235 Mask(M), ThisBB(T), TargetBB(Tr) { }
237 MachineBasicBlock *ThisBB;
238 MachineBasicBlock *TargetBB;
241 typedef SmallVector<BitTestCase, 3> BitTestInfo;
243 struct BitTestBlock {
244 BitTestBlock(APInt F, APInt R, const Value* SV,
246 MachineBasicBlock* P, MachineBasicBlock* D,
247 const BitTestInfo& C):
248 First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
249 Parent(P), Default(D), Cases(C) { }
255 MachineBasicBlock *Parent;
256 MachineBasicBlock *Default;
261 // TLI - This is information that describes the available target features we
262 // need for lowering. This indicates when operations are unavailable,
263 // implemented with a libcall, etc.
264 const TargetMachine &TM;
265 const TargetLowering &TLI;
267 const TargetData *TD;
270 /// SwitchCases - Vector of CaseBlock structures used to communicate
271 /// SwitchInst code generation information.
272 std::vector<CaseBlock> SwitchCases;
273 /// JTCases - Vector of JumpTable structures used to communicate
274 /// SwitchInst code generation information.
275 std::vector<JumpTableBlock> JTCases;
276 /// BitTestCases - Vector of BitTestBlock structures used to communicate
277 /// SwitchInst code generation information.
278 std::vector<BitTestBlock> BitTestCases;
280 // Emit PHI-node-operand constants only once even if used by multiple
282 DenseMap<const Constant *, unsigned> ConstantsOut;
284 /// FuncInfo - Information about the function as a whole.
286 FunctionLoweringInfo &FuncInfo;
288 /// OptLevel - What optimization level we're generating code for.
290 CodeGenOpt::Level OptLevel;
292 /// GFI - Garbage collection metadata for the function.
295 /// HasTailCall - This is set to true if a call in the current
296 /// block has been translated as a tail call. In this case,
297 /// no subsequent DAG nodes should be created.
301 LLVMContext *Context;
303 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
304 CodeGenOpt::Level ol)
305 : SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
306 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
307 HasTailCall(false), Context(dag.getContext()) {
310 void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
312 /// clear - Clear out the current SelectionDAG and the associated
313 /// state and prepare this SelectionDAGBuilder object to be used
314 /// for a new block. This doesn't clear out information about
315 /// additional blocks that are needed to complete switch lowering
316 /// or PHI node updating; that information is cleared out as it is
320 /// getRoot - Return the current virtual root of the Selection DAG,
321 /// flushing any PendingLoad items. This must be done before emitting
322 /// a store or any other node that may need to be ordered after any
323 /// prior load instructions.
327 /// getControlRoot - Similar to getRoot, but instead of flushing all the
328 /// PendingLoad items, flush all the PendingExports items. It is necessary
329 /// to do this before emitting a terminator instruction.
331 SDValue getControlRoot();
333 DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
335 unsigned getSDNodeOrder() const { return SDNodeOrder; }
337 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
339 /// AssignOrderingToNode - Assign an ordering to the node. The order is gotten
340 /// from how the code appeared in the source. The ordering is used by the
341 /// scheduler to effectively turn off scheduling.
342 void AssignOrderingToNode(const SDNode *Node);
344 void visit(const Instruction &I);
346 void visit(unsigned Opcode, const User &I);
348 SDValue getValue(const Value *V);
350 void setValue(const Value *V, SDValue NewN) {
351 SDValue &N = NodeMap[V];
352 assert(N.getNode() == 0 && "Already set a value for this node!");
356 void setUnusedArgValue(const Value *V, SDValue NewN) {
357 SDValue &N = UnusedArgNodeMap[V];
358 assert(N.getNode() == 0 && "Already set a value for this node!");
362 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
363 std::set<unsigned> &OutputRegs,
364 std::set<unsigned> &InputRegs);
366 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
367 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
368 MachineBasicBlock *SwitchBB, unsigned Opc);
369 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
370 MachineBasicBlock *FBB,
371 MachineBasicBlock *CurBB,
372 MachineBasicBlock *SwitchBB);
373 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
374 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
375 void CopyToExportRegsIfNeeded(const Value *V);
376 void ExportFromCurrentBlock(const Value *V);
377 void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
378 MachineBasicBlock *LandingPad = NULL);
381 // Terminator instructions.
382 void visitRet(const ReturnInst &I);
383 void visitBr(const BranchInst &I);
384 void visitSwitch(const SwitchInst &I);
385 void visitIndirectBr(const IndirectBrInst &I);
386 void visitUnreachable(const UnreachableInst &I) { /* noop */ }
388 // Helpers for visitSwitch
389 bool handleSmallSwitchRange(CaseRec& CR,
390 CaseRecVector& WorkList,
392 MachineBasicBlock* Default,
393 MachineBasicBlock *SwitchBB);
394 bool handleJTSwitchCase(CaseRec& CR,
395 CaseRecVector& WorkList,
397 MachineBasicBlock* Default,
398 MachineBasicBlock *SwitchBB);
399 bool handleBTSplitSwitchCase(CaseRec& CR,
400 CaseRecVector& WorkList,
402 MachineBasicBlock* Default,
403 MachineBasicBlock *SwitchBB);
404 bool handleBitTestsSwitchCase(CaseRec& CR,
405 CaseRecVector& WorkList,
407 MachineBasicBlock* Default,
408 MachineBasicBlock *SwitchBB);
410 void visitSwitchCase(CaseBlock &CB,
411 MachineBasicBlock *SwitchBB);
412 void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
413 void visitBitTestCase(MachineBasicBlock* NextMBB,
416 MachineBasicBlock *SwitchBB);
417 void visitJumpTable(JumpTable &JT);
418 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
419 MachineBasicBlock *SwitchBB);
422 // These all get lowered before this pass.
423 void visitInvoke(const InvokeInst &I);
424 void visitUnwind(const UnwindInst &I);
426 void visitBinary(const User &I, unsigned OpCode);
427 void visitShift(const User &I, unsigned Opcode);
428 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
429 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
430 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
431 void visitFSub(const User &I);
432 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
433 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
434 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
435 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
436 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
437 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
438 void visitSDiv(const User &I) { visitBinary(I, ISD::SDIV); }
439 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
440 void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
441 void visitOr (const User &I) { visitBinary(I, ISD::OR); }
442 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
443 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
444 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
445 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
446 void visitICmp(const User &I);
447 void visitFCmp(const User &I);
448 // Visit the conversion instructions
449 void visitTrunc(const User &I);
450 void visitZExt(const User &I);
451 void visitSExt(const User &I);
452 void visitFPTrunc(const User &I);
453 void visitFPExt(const User &I);
454 void visitFPToUI(const User &I);
455 void visitFPToSI(const User &I);
456 void visitUIToFP(const User &I);
457 void visitSIToFP(const User &I);
458 void visitPtrToInt(const User &I);
459 void visitIntToPtr(const User &I);
460 void visitBitCast(const User &I);
462 void visitExtractElement(const User &I);
463 void visitInsertElement(const User &I);
464 void visitShuffleVector(const User &I);
466 void visitExtractValue(const ExtractValueInst &I);
467 void visitInsertValue(const InsertValueInst &I);
469 void visitGetElementPtr(const User &I);
470 void visitSelect(const User &I);
472 void visitAlloca(const AllocaInst &I);
473 void visitLoad(const LoadInst &I);
474 void visitStore(const StoreInst &I);
475 void visitPHI(const PHINode &I);
476 void visitCall(const CallInst &I);
477 bool visitMemCmpCall(const CallInst &I);
479 void visitInlineAsm(ImmutableCallSite CS);
480 const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
481 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
483 void visitPow(const CallInst &I);
484 void visitExp2(const CallInst &I);
485 void visitExp(const CallInst &I);
486 void visitLog(const CallInst &I);
487 void visitLog2(const CallInst &I);
488 void visitLog10(const CallInst &I);
490 void visitVAStart(const CallInst &I);
491 void visitVAArg(const VAArgInst &I);
492 void visitVAEnd(const CallInst &I);
493 void visitVACopy(const CallInst &I);
495 void visitUserOp1(const Instruction &I) {
496 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
498 void visitUserOp2(const Instruction &I) {
499 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
502 const char *implVisitBinaryAtomic(const CallInst& I, ISD::NodeType Op);
503 const char *implVisitAluOverflow(const CallInst &I, ISD::NodeType Op);
505 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
507 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a
508 /// function argument, create the corresponding DBG_VALUE machine instruction
509 /// for it now. At the end of instruction selection, they will be inserted to
511 bool EmitFuncArgumentDbgValue(const DbgValueInst &DI,
512 const Value *V, MDNode *Variable,
513 uint64_t Offset, const SDValue &N);
516 } // end namespace llvm