1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
15 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
17 #include "StatepointLowering.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SelectionDAGNodes.h"
22 #include "llvm/IR/CallSite.h"
23 #include "llvm/IR/Statepoint.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetLowering.h"
31 class AddrSpaceCastInst;
39 class ExtractElementInst;
40 class ExtractValueInst;
47 class FunctionLoweringInfo;
48 class GetElementPtrInst;
54 class InsertElementInst;
55 class InsertValueInst;
58 class MachineBasicBlock;
60 class MachineRegisterInfo;
69 class ShuffleVectorInst;
74 class TargetLibraryInfo;
78 class UnreachableInst;
82 //===----------------------------------------------------------------------===//
83 /// SelectionDAGBuilder - This is the common target-independent lowering
84 /// implementation that is parameterized by a TargetLowering object.
86 class SelectionDAGBuilder {
87 /// CurInst - The current instruction being visited
88 const Instruction *CurInst;
90 DenseMap<const Value*, SDValue> NodeMap;
92 /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
93 /// to preserve debug information for incoming arguments.
94 DenseMap<const Value*, SDValue> UnusedArgNodeMap;
96 /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
97 class DanglingDebugInfo {
98 const DbgValueInst* DI;
100 unsigned SDNodeOrder;
102 DanglingDebugInfo() : DI(nullptr), dl(DebugLoc()), SDNodeOrder(0) { }
103 DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
104 DI(di), dl(DL), SDNodeOrder(SDNO) { }
105 const DbgValueInst* getDI() { return DI; }
106 DebugLoc getdl() { return dl; }
107 unsigned getSDNodeOrder() { return SDNodeOrder; }
110 /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
111 /// yet seen the referent. We defer handling these until we do see it.
112 DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
115 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
116 /// them up and then emit token factor nodes when possible. This allows us to
117 /// get simple disambiguation between loads without worrying about alias
119 SmallVector<SDValue, 8> PendingLoads;
121 /// State used while lowering a statepoint sequence (gc_statepoint,
122 /// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details.
123 StatepointLoweringState StatepointLowering;
126 /// PendingExports - CopyToReg nodes that copy values to virtual registers
127 /// for export to other blocks need to be emitted before any terminator
128 /// instruction, but they have no other ordering requirements. We bunch them
129 /// up and the emit a single tokenfactor for them just before terminator
131 SmallVector<SDValue, 8> PendingExports;
133 /// SDNodeOrder - A unique monotonically increasing number used to order the
134 /// SDNodes we create.
135 unsigned SDNodeOrder;
137 /// Case - A struct to record the Value for a switch case, and the
138 /// case's target basic block.
141 const Constant *High;
142 MachineBasicBlock* BB;
143 uint32_t ExtraWeight;
145 Case() : Low(nullptr), High(nullptr), BB(nullptr), ExtraWeight(0) { }
146 Case(const Constant *low, const Constant *high, MachineBasicBlock *bb,
147 uint32_t extraweight) : Low(low), High(high), BB(bb),
148 ExtraWeight(extraweight) { }
151 const APInt &rHigh = cast<ConstantInt>(High)->getValue();
152 const APInt &rLow = cast<ConstantInt>(Low)->getValue();
153 return (rHigh - rLow + 1ULL);
159 MachineBasicBlock* BB;
161 uint32_t ExtraWeight;
163 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
165 Mask(mask), BB(bb), Bits(bits), ExtraWeight(Weight) { }
168 typedef std::vector<Case> CaseVector;
169 typedef std::vector<CaseBits> CaseBitsVector;
170 typedef CaseVector::iterator CaseItr;
171 typedef std::pair<CaseItr, CaseItr> CaseRange;
173 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
174 /// of conditional branches.
176 CaseRec(MachineBasicBlock *bb, const Constant *lt, const Constant *ge,
178 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
180 /// CaseBB - The MBB in which to emit the compare and branch
181 MachineBasicBlock *CaseBB;
182 /// LT, GE - If nonzero, we know the current case value must be less-than or
183 /// greater-than-or-equal-to these Constants.
186 /// Range - A pair of iterators representing the range of case values to be
187 /// processed at this point in the binary search tree.
191 typedef std::vector<CaseRec> CaseRecVector;
193 /// The comparison function for sorting the switch case values in the vector.
194 /// WARNING: Case ranges should be disjoint!
196 bool operator()(const Case &C1, const Case &C2) {
197 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
198 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
199 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
200 return CI1->getValue().slt(CI2->getValue());
205 bool operator()(const CaseBits &C1, const CaseBits &C2) {
206 return C1.Bits > C2.Bits;
210 void Clusterify(CaseVector &Cases, const SwitchInst &SI);
212 /// CaseBlock - This structure is used to communicate between
213 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
214 /// blocks needed by multi-case switch statements.
216 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
217 const Value *cmpmiddle,
218 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
219 MachineBasicBlock *me,
220 uint32_t trueweight = 0, uint32_t falseweight = 0)
221 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
222 TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
223 TrueWeight(trueweight), FalseWeight(falseweight) { }
225 // CC - the condition code to use for the case block's setcc node
228 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
229 // Emit by default LHS op RHS. MHS is used for range comparisons:
230 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
231 const Value *CmpLHS, *CmpMHS, *CmpRHS;
233 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
234 MachineBasicBlock *TrueBB, *FalseBB;
236 // ThisBB - the block into which to emit the code for the setcc and branches
237 MachineBasicBlock *ThisBB;
239 // TrueWeight/FalseWeight - branch weights.
240 uint32_t TrueWeight, FalseWeight;
244 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
245 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
247 /// Reg - the virtual register containing the index of the jump table entry
250 /// JTI - the JumpTableIndex for this jump table in the function.
252 /// MBB - the MBB into which to emit the code for the indirect jump.
253 MachineBasicBlock *MBB;
254 /// Default - the MBB of the default bb, which is a successor of the range
255 /// check MBB. This is when updating PHI nodes in successors.
256 MachineBasicBlock *Default;
258 struct JumpTableHeader {
259 JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
261 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
265 MachineBasicBlock *HeaderBB;
268 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
271 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
273 Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
275 MachineBasicBlock *ThisBB;
276 MachineBasicBlock *TargetBB;
277 uint32_t ExtraWeight;
280 typedef SmallVector<BitTestCase, 3> BitTestInfo;
282 struct BitTestBlock {
283 BitTestBlock(APInt F, APInt R, const Value* SV,
284 unsigned Rg, MVT RgVT, bool E,
285 MachineBasicBlock* P, MachineBasicBlock* D,
287 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
288 Parent(P), Default(D), Cases(std::move(C)) { }
295 MachineBasicBlock *Parent;
296 MachineBasicBlock *Default;
300 /// A class which encapsulates all of the information needed to generate a
301 /// stack protector check and signals to isel via its state being initialized
302 /// that a stack protector needs to be generated.
304 /// *NOTE* The following is a high level documentation of SelectionDAG Stack
305 /// Protector Generation. The reason that it is placed here is for a lack of
306 /// other good places to stick it.
308 /// High Level Overview of SelectionDAG Stack Protector Generation:
310 /// Previously, generation of stack protectors was done exclusively in the
311 /// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
312 /// splitting basic blocks at the IR level to create the success/failure basic
313 /// blocks in the tail of the basic block in question. As a result of this,
314 /// calls that would have qualified for the sibling call optimization were no
315 /// longer eligible for optimization since said calls were no longer right in
316 /// the "tail position" (i.e. the immediate predecessor of a ReturnInst
319 /// Then it was noticed that since the sibling call optimization causes the
320 /// callee to reuse the caller's stack, if we could delay the generation of
321 /// the stack protector check until later in CodeGen after the sibling call
322 /// decision was made, we get both the tail call optimization and the stack
325 /// A few goals in solving this problem were:
327 /// 1. Preserve the architecture independence of stack protector generation.
329 /// 2. Preserve the normal IR level stack protector check for platforms like
330 /// OpenBSD for which we support platform-specific stack protector
333 /// The main problem that guided the present solution is that one can not
334 /// solve this problem in an architecture independent manner at the IR level
335 /// only. This is because:
337 /// 1. The decision on whether or not to perform a sibling call on certain
338 /// platforms (for instance i386) requires lower level information
339 /// related to available registers that can not be known at the IR level.
341 /// 2. Even if the previous point were not true, the decision on whether to
342 /// perform a tail call is done in LowerCallTo in SelectionDAG which
343 /// occurs after the Stack Protector Pass. As a result, one would need to
344 /// put the relevant callinst into the stack protector check success
345 /// basic block (where the return inst is placed) and then move it back
346 /// later at SelectionDAG/MI time before the stack protector check if the
347 /// tail call optimization failed. The MI level option was nixed
348 /// immediately since it would require platform-specific pattern
349 /// matching. The SelectionDAG level option was nixed because
350 /// SelectionDAG only processes one IR level basic block at a time
351 /// implying one could not create a DAG Combine to move the callinst.
353 /// To get around this problem a few things were realized:
355 /// 1. While one can not handle multiple IR level basic blocks at the
356 /// SelectionDAG Level, one can generate multiple machine basic blocks
357 /// for one IR level basic block. This is how we handle bit tests and
360 /// 2. At the MI level, tail calls are represented via a special return
361 /// MIInst called "tcreturn". Thus if we know the basic block in which we
362 /// wish to insert the stack protector check, we get the correct behavior
363 /// by always inserting the stack protector check right before the return
364 /// statement. This is a "magical transformation" since no matter where
365 /// the stack protector check intrinsic is, we always insert the stack
366 /// protector check code at the end of the BB.
368 /// Given the aforementioned constraints, the following solution was devised:
370 /// 1. On platforms that do not support SelectionDAG stack protector check
371 /// generation, allow for the normal IR level stack protector check
372 /// generation to continue.
374 /// 2. On platforms that do support SelectionDAG stack protector check
377 /// a. Use the IR level stack protector pass to decide if a stack
378 /// protector is required/which BB we insert the stack protector check
379 /// in by reusing the logic already therein. If we wish to generate a
380 /// stack protector check in a basic block, we place a special IR
381 /// intrinsic called llvm.stackprotectorcheck right before the BB's
382 /// returninst or if there is a callinst that could potentially be
383 /// sibling call optimized, before the call inst.
385 /// b. Then when a BB with said intrinsic is processed, we codegen the BB
386 /// normally via SelectBasicBlock. In said process, when we visit the
387 /// stack protector check, we do not actually emit anything into the
388 /// BB. Instead, we just initialize the stack protector descriptor
389 /// class (which involves stashing information/creating the success
390 /// mbbb and the failure mbb if we have not created one for this
391 /// function yet) and export the guard variable that we are going to
394 /// c. After we finish selecting the basic block, in FinishBasicBlock if
395 /// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
396 /// initialized, we first find a splice point in the parent basic block
397 /// before the terminator and then splice the terminator of said basic
398 /// block into the success basic block. Then we code-gen a new tail for
399 /// the parent basic block consisting of the two loads, the comparison,
400 /// and finally two branches to the success/failure basic blocks. We
401 /// conclude by code-gening the failure basic block if we have not
402 /// code-gened it already (all stack protector checks we generate in
403 /// the same function, use the same failure basic block).
404 class StackProtectorDescriptor {
406 StackProtectorDescriptor() : ParentMBB(nullptr), SuccessMBB(nullptr),
407 FailureMBB(nullptr), Guard(nullptr),
409 ~StackProtectorDescriptor() { }
411 /// Returns true if all fields of the stack protector descriptor are
412 /// initialized implying that we should/are ready to emit a stack protector.
413 bool shouldEmitStackProtector() const {
414 return ParentMBB && SuccessMBB && FailureMBB && Guard;
417 /// Initialize the stack protector descriptor structure for a new basic
419 void initialize(const BasicBlock *BB,
420 MachineBasicBlock *MBB,
421 const CallInst &StackProtCheckCall) {
422 // Make sure we are not initialized yet.
423 assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
424 "already initialized!");
426 SuccessMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ true);
427 FailureMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ false, FailureMBB);
429 Guard = StackProtCheckCall.getArgOperand(0);
432 /// Reset state that changes when we handle different basic blocks.
434 /// This currently includes:
436 /// 1. The specific basic block we are generating a
437 /// stack protector for (ParentMBB).
439 /// 2. The successor machine basic block that will contain the tail of
440 /// parent mbb after we create the stack protector check (SuccessMBB). This
441 /// BB is visited only on stack protector check success.
442 void resetPerBBState() {
444 SuccessMBB = nullptr;
447 /// Reset state that only changes when we switch functions.
449 /// This currently includes:
451 /// 1. FailureMBB since we reuse the failure code path for all stack
452 /// protector checks created in an individual function.
454 /// 2.The guard variable since the guard variable we are checking against is
456 void resetPerFunctionState() {
457 FailureMBB = nullptr;
461 MachineBasicBlock *getParentMBB() { return ParentMBB; }
462 MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
463 MachineBasicBlock *getFailureMBB() { return FailureMBB; }
464 const Value *getGuard() { return Guard; }
466 unsigned getGuardReg() const { return GuardReg; }
467 void setGuardReg(unsigned R) { GuardReg = R; }
470 /// The basic block for which we are generating the stack protector.
472 /// As a result of stack protector generation, we will splice the
473 /// terminators of this basic block into the successor mbb SuccessMBB and
474 /// replace it with a compare/branch to the successor mbbs
475 /// SuccessMBB/FailureMBB depending on whether or not the stack protector
477 MachineBasicBlock *ParentMBB;
479 /// A basic block visited on stack protector check success that contains the
480 /// terminators of ParentMBB.
481 MachineBasicBlock *SuccessMBB;
483 /// This basic block visited on stack protector check failure that will
484 /// contain a call to __stack_chk_fail().
485 MachineBasicBlock *FailureMBB;
487 /// The guard variable which we will compare against the stored value in the
488 /// stack protector stack slot.
491 /// The virtual register holding the stack guard value.
494 /// Add a successor machine basic block to ParentMBB. If the successor mbb
495 /// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
496 /// block will be created. Assign a large weight if IsLikely is true.
497 MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
498 MachineBasicBlock *ParentMBB,
500 MachineBasicBlock *SuccMBB = nullptr);
504 const TargetMachine &TM;
506 /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling
507 /// nodes without a corresponding SDNode.
508 static const unsigned LowestSDNodeOrder = 1;
511 const DataLayout *DL;
513 const TargetLibraryInfo *LibInfo;
515 /// SwitchCases - Vector of CaseBlock structures used to communicate
516 /// SwitchInst code generation information.
517 std::vector<CaseBlock> SwitchCases;
518 /// JTCases - Vector of JumpTable structures used to communicate
519 /// SwitchInst code generation information.
520 std::vector<JumpTableBlock> JTCases;
521 /// BitTestCases - Vector of BitTestBlock structures used to communicate
522 /// SwitchInst code generation information.
523 std::vector<BitTestBlock> BitTestCases;
524 /// A StackProtectorDescriptor structure used to communicate stack protector
525 /// information in between SelectBasicBlock and FinishBasicBlock.
526 StackProtectorDescriptor SPDescriptor;
528 // Emit PHI-node-operand constants only once even if used by multiple
530 DenseMap<const Constant *, unsigned> ConstantsOut;
532 /// FuncInfo - Information about the function as a whole.
534 FunctionLoweringInfo &FuncInfo;
536 /// OptLevel - What optimization level we're generating code for.
538 CodeGenOpt::Level OptLevel;
540 /// GFI - Garbage collection metadata for the function.
543 /// LPadToCallSiteMap - Map a landing pad to the call site indexes.
544 DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
546 /// HasTailCall - This is set to true if a call in the current
547 /// block has been translated as a tail call. In this case,
548 /// no subsequent DAG nodes should be created.
552 LLVMContext *Context;
554 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
555 CodeGenOpt::Level ol)
556 : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
557 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
561 void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
562 const TargetLibraryInfo *li);
564 /// clear - Clear out the current SelectionDAG and the associated
565 /// state and prepare this SelectionDAGBuilder object to be used
566 /// for a new block. This doesn't clear out information about
567 /// additional blocks that are needed to complete switch lowering
568 /// or PHI node updating; that information is cleared out as it is
572 /// clearDanglingDebugInfo - Clear the dangling debug information
573 /// map. This function is separated from the clear so that debug
574 /// information that is dangling in a basic block can be properly
575 /// resolved in a different basic block. This allows the
576 /// SelectionDAG to resolve dangling debug information attached
578 void clearDanglingDebugInfo();
580 /// getRoot - Return the current virtual root of the Selection DAG,
581 /// flushing any PendingLoad items. This must be done before emitting
582 /// a store or any other node that may need to be ordered after any
583 /// prior load instructions.
587 /// getControlRoot - Similar to getRoot, but instead of flushing all the
588 /// PendingLoad items, flush all the PendingExports items. It is necessary
589 /// to do this before emitting a terminator instruction.
591 SDValue getControlRoot();
593 SDLoc getCurSDLoc() const {
594 return SDLoc(CurInst, SDNodeOrder);
597 DebugLoc getCurDebugLoc() const {
598 return CurInst ? CurInst->getDebugLoc() : DebugLoc();
601 unsigned getSDNodeOrder() const { return SDNodeOrder; }
603 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
605 void visit(const Instruction &I);
607 void visit(unsigned Opcode, const User &I);
609 /// getCopyFromRegs - If there was virtual register allocated for the value V
610 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
611 SDValue getCopyFromRegs(const Value *V, Type *Ty);
613 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
614 // generate the debug data structures now that we've seen its definition.
615 void resolveDanglingDebugInfo(const Value *V, SDValue Val);
616 SDValue getValue(const Value *V);
617 SDValue getNonRegisterValue(const Value *V);
618 SDValue getValueImpl(const Value *V);
620 void setValue(const Value *V, SDValue NewN) {
621 SDValue &N = NodeMap[V];
622 assert(!N.getNode() && "Already set a value for this node!");
626 void removeValue(const Value *V) {
627 // This is to support hack in lowerCallFromStatepoint
628 // Should be removed when hack is resolved
632 void setUnusedArgValue(const Value *V, SDValue NewN) {
633 SDValue &N = UnusedArgNodeMap[V];
634 assert(!N.getNode() && "Already set a value for this node!");
638 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
639 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
640 MachineBasicBlock *SwitchBB, unsigned Opc,
641 uint32_t TW, uint32_t FW);
642 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
643 MachineBasicBlock *FBB,
644 MachineBasicBlock *CurBB,
645 MachineBasicBlock *SwitchBB,
646 uint32_t TW, uint32_t FW);
647 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
648 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
649 void CopyToExportRegsIfNeeded(const Value *V);
650 void ExportFromCurrentBlock(const Value *V);
651 void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
652 MachineBasicBlock *LandingPad = nullptr);
654 std::pair<SDValue, SDValue> lowerCallOperands(
655 ImmutableCallSite CS,
659 bool UseVoidTy = false,
660 MachineBasicBlock *LandingPad = nullptr,
661 bool IsPatchPoint = false);
663 /// UpdateSplitBlock - When an MBB was split during scheduling, update the
664 /// references that need to refer to the last resulting block.
665 void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
667 // This function is responsible for the whole statepoint lowering process.
668 // It uniformly handles invoke and call statepoints.
669 void LowerStatepoint(ImmutableStatepoint Statepoint,
670 MachineBasicBlock *LandingPad = nullptr);
672 std::pair<SDValue, SDValue> lowerInvokable(
673 TargetLowering::CallLoweringInfo &CLI,
674 MachineBasicBlock *LandingPad);
676 // Terminator instructions.
677 void visitRet(const ReturnInst &I);
678 void visitBr(const BranchInst &I);
679 void visitSwitch(const SwitchInst &I);
680 void visitIndirectBr(const IndirectBrInst &I);
681 void visitUnreachable(const UnreachableInst &I);
683 // Helpers for visitSwitch
684 bool handleSmallSwitchRange(CaseRec& CR,
685 CaseRecVector& WorkList,
687 MachineBasicBlock* Default,
688 MachineBasicBlock *SwitchBB);
689 bool handleJTSwitchCase(CaseRec& CR,
690 CaseRecVector& WorkList,
692 MachineBasicBlock* Default,
693 MachineBasicBlock *SwitchBB);
694 bool handleBTSplitSwitchCase(CaseRec& CR,
695 CaseRecVector& WorkList,
697 MachineBasicBlock *SwitchBB);
698 void splitSwitchCase(CaseRec &CR, CaseItr Pivot, CaseRecVector &WorkList,
699 const Value *SV, MachineBasicBlock *SwitchBB);
700 bool handleBitTestsSwitchCase(CaseRec& CR,
701 CaseRecVector& WorkList,
703 MachineBasicBlock* Default,
704 MachineBasicBlock *SwitchBB);
706 uint32_t getEdgeWeight(const MachineBasicBlock *Src,
707 const MachineBasicBlock *Dst) const;
708 void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
709 uint32_t Weight = 0);
711 void visitSwitchCase(CaseBlock &CB,
712 MachineBasicBlock *SwitchBB);
713 void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
714 MachineBasicBlock *ParentBB);
715 void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
716 void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
717 void visitBitTestCase(BitTestBlock &BB,
718 MachineBasicBlock* NextMBB,
719 uint32_t BranchWeightToNext,
722 MachineBasicBlock *SwitchBB);
723 void visitJumpTable(JumpTable &JT);
724 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
725 MachineBasicBlock *SwitchBB);
726 unsigned visitLandingPadClauseBB(GlobalValue *ClauseGV,
727 MachineBasicBlock *LPadMBB);
730 // These all get lowered before this pass.
731 void visitInvoke(const InvokeInst &I);
732 void visitResume(const ResumeInst &I);
734 void visitBinary(const User &I, unsigned OpCode);
735 void visitShift(const User &I, unsigned Opcode);
736 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
737 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
738 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
739 void visitFSub(const User &I);
740 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
741 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
742 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
743 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
744 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
745 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
746 void visitSDiv(const User &I);
747 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
748 void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
749 void visitOr (const User &I) { visitBinary(I, ISD::OR); }
750 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
751 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
752 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
753 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
754 void visitICmp(const User &I);
755 void visitFCmp(const User &I);
756 // Visit the conversion instructions
757 void visitTrunc(const User &I);
758 void visitZExt(const User &I);
759 void visitSExt(const User &I);
760 void visitFPTrunc(const User &I);
761 void visitFPExt(const User &I);
762 void visitFPToUI(const User &I);
763 void visitFPToSI(const User &I);
764 void visitUIToFP(const User &I);
765 void visitSIToFP(const User &I);
766 void visitPtrToInt(const User &I);
767 void visitIntToPtr(const User &I);
768 void visitBitCast(const User &I);
769 void visitAddrSpaceCast(const User &I);
771 void visitExtractElement(const User &I);
772 void visitInsertElement(const User &I);
773 void visitShuffleVector(const User &I);
775 void visitExtractValue(const ExtractValueInst &I);
776 void visitInsertValue(const InsertValueInst &I);
777 void visitLandingPad(const LandingPadInst &I);
779 void visitGetElementPtr(const User &I);
780 void visitSelect(const User &I);
782 void visitAlloca(const AllocaInst &I);
783 void visitLoad(const LoadInst &I);
784 void visitStore(const StoreInst &I);
785 void visitMaskedLoad(const CallInst &I);
786 void visitMaskedStore(const CallInst &I);
787 void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
788 void visitAtomicRMW(const AtomicRMWInst &I);
789 void visitFence(const FenceInst &I);
790 void visitPHI(const PHINode &I);
791 void visitCall(const CallInst &I);
792 bool visitMemCmpCall(const CallInst &I);
793 bool visitMemChrCall(const CallInst &I);
794 bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
795 bool visitStrCmpCall(const CallInst &I);
796 bool visitStrLenCall(const CallInst &I);
797 bool visitStrNLenCall(const CallInst &I);
798 bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
799 bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode);
800 void visitAtomicLoad(const LoadInst &I);
801 void visitAtomicStore(const StoreInst &I);
803 void visitInlineAsm(ImmutableCallSite CS);
804 const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
805 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
807 void visitVAStart(const CallInst &I);
808 void visitVAArg(const VAArgInst &I);
809 void visitVAEnd(const CallInst &I);
810 void visitVACopy(const CallInst &I);
811 void visitStackmap(const CallInst &I);
812 void visitPatchpoint(ImmutableCallSite CS,
813 MachineBasicBlock *LandingPad = nullptr);
815 // These three are implemented in StatepointLowering.cpp
816 void visitStatepoint(const CallInst &I);
817 void visitGCRelocate(const CallInst &I);
818 void visitGCResult(const CallInst &I);
820 void visitUserOp1(const Instruction &I) {
821 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
823 void visitUserOp2(const Instruction &I) {
824 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
827 void processIntegerCallValue(const Instruction &I,
828 SDValue Value, bool IsSigned);
830 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
832 /// EmitFuncArgumentDbgValue - If V is an function argument then create
833 /// corresponding DBG_VALUE machine instruction for it now. At the end of
834 /// instruction selection, they will be inserted to the entry BB.
835 bool EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, MDNode *Expr,
836 int64_t Offset, bool IsIndirect,
840 } // end namespace llvm