1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAGISel.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/FunctionLoweringInfo.h"
24 #include "llvm/CodeGen/GCMetadata.h"
25 #include "llvm/CodeGen/GCStrategy.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
32 #include "llvm/CodeGen/SchedulerRegistry.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DebugInfo.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/InlineAsm.h"
38 #include "llvm/IR/Instructions.h"
39 #include "llvm/IR/IntrinsicInst.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/IR/Module.h"
43 #include "llvm/Support/Compiler.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/Timer.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLibraryInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetMachine.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "llvm/Target/TargetRegisterInfo.h"
55 #include "llvm/Target/TargetSubtargetInfo.h"
56 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
60 #define DEBUG_TYPE "isel"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
64 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
65 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
66 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
68 STATISTIC(NumFastIselFailLowerArguments,
69 "Number of entry blocks where fast isel failed to lower arguments");
73 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
74 cl::desc("Enable extra verbose messages in the \"fast\" "
75 "instruction selector"));
78 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
79 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
80 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
81 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
82 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
83 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
84 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
86 // Standard binary operators...
87 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
88 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
89 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
90 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
91 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
92 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
93 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
94 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
95 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
96 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
97 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
98 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
100 // Logical operators...
101 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
102 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
103 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
105 // Memory instructions...
106 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
107 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
108 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
109 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
110 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
111 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
112 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
114 // Convert instructions...
115 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
116 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
117 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
118 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
119 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
120 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
121 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
122 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
123 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
124 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
125 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
126 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
128 // Other instructions...
129 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
130 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
131 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
132 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
133 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
134 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
135 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
136 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
137 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
138 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
139 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
140 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
141 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
142 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
143 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
145 // Intrinsic instructions...
146 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
147 STATISTIC(NumFastIselFailSAddWithOverflow,
148 "Fast isel fails on sadd.with.overflow");
149 STATISTIC(NumFastIselFailUAddWithOverflow,
150 "Fast isel fails on uadd.with.overflow");
151 STATISTIC(NumFastIselFailSSubWithOverflow,
152 "Fast isel fails on ssub.with.overflow");
153 STATISTIC(NumFastIselFailUSubWithOverflow,
154 "Fast isel fails on usub.with.overflow");
155 STATISTIC(NumFastIselFailSMulWithOverflow,
156 "Fast isel fails on smul.with.overflow");
157 STATISTIC(NumFastIselFailUMulWithOverflow,
158 "Fast isel fails on umul.with.overflow");
159 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
160 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
161 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
162 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
166 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
167 cl::desc("Enable verbose messages in the \"fast\" "
168 "instruction selector"));
170 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
171 cl::desc("Enable abort calls when \"fast\" instruction selection "
172 "fails to lower an instruction"));
174 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
175 cl::desc("Enable abort calls when \"fast\" instruction selection "
176 "fails to lower a formal argument"));
180 cl::desc("use Machine Branch Probability Info"),
181 cl::init(true), cl::Hidden);
185 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
186 cl::desc("Pop up a window to show dags before the first "
187 "dag combine pass"));
189 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
190 cl::desc("Pop up a window to show dags before legalize types"));
192 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
193 cl::desc("Pop up a window to show dags before legalize"));
195 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before the second "
197 "dag combine pass"));
199 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
200 cl::desc("Pop up a window to show dags before the post legalize types"
201 " dag combine pass"));
203 ViewISelDAGs("view-isel-dags", cl::Hidden,
204 cl::desc("Pop up a window to show isel dags as they are selected"));
206 ViewSchedDAGs("view-sched-dags", cl::Hidden,
207 cl::desc("Pop up a window to show sched dags as they are processed"));
209 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
210 cl::desc("Pop up a window to show SUnit dags after they are processed"));
212 static const bool ViewDAGCombine1 = false,
213 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
214 ViewDAGCombine2 = false,
215 ViewDAGCombineLT = false,
216 ViewISelDAGs = false, ViewSchedDAGs = false,
217 ViewSUnitDAGs = false;
220 //===---------------------------------------------------------------------===//
222 /// RegisterScheduler class - Track the registration of instruction schedulers.
224 //===---------------------------------------------------------------------===//
225 MachinePassRegistry RegisterScheduler::Registry;
227 //===---------------------------------------------------------------------===//
229 /// ISHeuristic command line option for instruction schedulers.
231 //===---------------------------------------------------------------------===//
232 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
233 RegisterPassParser<RegisterScheduler> >
234 ISHeuristic("pre-RA-sched",
235 cl::init(&createDefaultScheduler), cl::Hidden,
236 cl::desc("Instruction schedulers available (before register"
239 static RegisterScheduler
240 defaultListDAGScheduler("default", "Best scheduler for the target",
241 createDefaultScheduler);
244 //===--------------------------------------------------------------------===//
245 /// \brief This class is used by SelectionDAGISel to temporarily override
246 /// the optimization level on a per-function basis.
247 class OptLevelChanger {
248 SelectionDAGISel &IS;
249 CodeGenOpt::Level SavedOptLevel;
253 OptLevelChanger(SelectionDAGISel &ISel,
254 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
255 SavedOptLevel = IS.OptLevel;
256 if (NewOptLevel == SavedOptLevel)
258 IS.OptLevel = NewOptLevel;
259 IS.TM.setOptLevel(NewOptLevel);
260 SavedFastISel = IS.TM.Options.EnableFastISel;
261 if (NewOptLevel == CodeGenOpt::None)
262 IS.TM.setFastISel(true);
263 DEBUG(dbgs() << "\nChanging optimization level for Function "
264 << IS.MF->getFunction()->getName() << "\n");
265 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
266 << " ; After: -O" << NewOptLevel << "\n");
270 if (IS.OptLevel == SavedOptLevel)
272 DEBUG(dbgs() << "\nRestoring optimization level for Function "
273 << IS.MF->getFunction()->getName() << "\n");
274 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
275 << " ; After: -O" << SavedOptLevel << "\n");
276 IS.OptLevel = SavedOptLevel;
277 IS.TM.setOptLevel(SavedOptLevel);
278 IS.TM.setFastISel(SavedFastISel);
282 //===--------------------------------------------------------------------===//
283 /// createDefaultScheduler - This creates an instruction scheduler appropriate
285 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
286 CodeGenOpt::Level OptLevel) {
287 const TargetLowering *TLI = IS->getTargetLowering();
288 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
290 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
291 TLI->getSchedulingPreference() == Sched::Source)
292 return createSourceListDAGScheduler(IS, OptLevel);
293 if (TLI->getSchedulingPreference() == Sched::RegPressure)
294 return createBURRListDAGScheduler(IS, OptLevel);
295 if (TLI->getSchedulingPreference() == Sched::Hybrid)
296 return createHybridListDAGScheduler(IS, OptLevel);
297 if (TLI->getSchedulingPreference() == Sched::VLIW)
298 return createVLIWDAGScheduler(IS, OptLevel);
299 assert(TLI->getSchedulingPreference() == Sched::ILP &&
300 "Unknown sched type!");
301 return createILPListDAGScheduler(IS, OptLevel);
305 // EmitInstrWithCustomInserter - This method should be implemented by targets
306 // that mark instructions with the 'usesCustomInserter' flag. These
307 // instructions are special in various ways, which require special support to
308 // insert. The specified MachineInstr is created but not inserted into any
309 // basic blocks, and this method is called to expand it into a sequence of
310 // instructions, potentially also creating new basic blocks and control flow.
311 // When new basic blocks are inserted and the edges from MBB to its successors
312 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
315 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
316 MachineBasicBlock *MBB) const {
318 dbgs() << "If a target marks an instruction with "
319 "'usesCustomInserter', it must implement "
320 "TargetLowering::EmitInstrWithCustomInserter!";
322 llvm_unreachable(nullptr);
325 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
326 SDNode *Node) const {
327 assert(!MI->hasPostISelHook() &&
328 "If a target marks an instruction with 'hasPostISelHook', "
329 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
332 //===----------------------------------------------------------------------===//
333 // SelectionDAGISel code
334 //===----------------------------------------------------------------------===//
336 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
337 CodeGenOpt::Level OL) :
338 MachineFunctionPass(ID), TM(tm),
339 FuncInfo(new FunctionLoweringInfo(TM)),
340 CurDAG(new SelectionDAG(tm, OL)),
341 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
345 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
346 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
347 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
348 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
351 SelectionDAGISel::~SelectionDAGISel() {
357 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
358 AU.addRequired<AliasAnalysis>();
359 AU.addPreserved<AliasAnalysis>();
360 AU.addRequired<GCModuleInfo>();
361 AU.addPreserved<GCModuleInfo>();
362 AU.addRequired<TargetLibraryInfo>();
363 if (UseMBPI && OptLevel != CodeGenOpt::None)
364 AU.addRequired<BranchProbabilityInfo>();
365 MachineFunctionPass::getAnalysisUsage(AU);
368 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
369 /// may trap on it. In this case we have to split the edge so that the path
370 /// through the predecessor block that doesn't go to the phi block doesn't
371 /// execute the possibly trapping instruction.
373 /// This is required for correctness, so it must be done at -O0.
375 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
376 // Loop for blocks with phi nodes.
377 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
378 PHINode *PN = dyn_cast<PHINode>(BB->begin());
382 // For each block with a PHI node, check to see if any of the input values
383 // are potentially trapping constant expressions. Constant expressions are
384 // the only potentially trapping value that can occur as the argument to a
386 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
387 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
388 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
389 if (!CE || !CE->canTrap()) continue;
391 // The only case we have to worry about is when the edge is critical.
392 // Since this block has a PHI Node, we assume it has multiple input
393 // edges: check to see if the pred has multiple successors.
394 BasicBlock *Pred = PN->getIncomingBlock(i);
395 if (Pred->getTerminator()->getNumSuccessors() == 1)
398 // Okay, we have to split this edge.
399 SplitCriticalEdge(Pred->getTerminator(),
400 GetSuccessorNumber(Pred, BB), SDISel, true);
406 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
407 // Do some sanity-checking on the command-line options.
408 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
409 "-fast-isel-verbose requires -fast-isel");
410 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
411 "-fast-isel-abort requires -fast-isel");
413 const Function &Fn = *mf.getFunction();
414 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
415 const TargetRegisterInfo &TRI = *TM.getSubtargetImpl()->getRegisterInfo();
416 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
419 RegInfo = &MF->getRegInfo();
420 AA = &getAnalysis<AliasAnalysis>();
421 LibInfo = &getAnalysis<TargetLibraryInfo>();
422 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
424 TargetSubtargetInfo &ST =
425 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
426 ST.resetSubtargetFeatures(MF);
427 TM.resetTargetOptions(MF);
429 // Reset OptLevel to None for optnone functions.
430 CodeGenOpt::Level NewOptLevel = OptLevel;
431 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
432 NewOptLevel = CodeGenOpt::None;
433 OptLevelChanger OLC(*this, NewOptLevel);
435 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
437 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
439 CurDAG->init(*MF, TLI);
440 FuncInfo->set(Fn, *MF, CurDAG);
442 if (UseMBPI && OptLevel != CodeGenOpt::None)
443 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
445 FuncInfo->BPI = nullptr;
447 SDB->init(GFI, *AA, LibInfo);
449 MF->setHasInlineAsm(false);
451 SelectAllBasicBlocks(Fn);
453 // If the first basic block in the function has live ins that need to be
454 // copied into vregs, emit the copies into the top of the block before
455 // emitting the code for the block.
456 MachineBasicBlock *EntryMBB = MF->begin();
457 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
459 DenseMap<unsigned, unsigned> LiveInMap;
460 if (!FuncInfo->ArgDbgValues.empty())
461 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
462 E = RegInfo->livein_end(); LI != E; ++LI)
464 LiveInMap.insert(std::make_pair(LI->first, LI->second));
466 // Insert DBG_VALUE instructions for function arguments to the entry block.
467 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
468 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
469 bool hasFI = MI->getOperand(0).isFI();
471 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
472 if (TargetRegisterInfo::isPhysicalRegister(Reg))
473 EntryMBB->insert(EntryMBB->begin(), MI);
475 MachineInstr *Def = RegInfo->getVRegDef(Reg);
477 MachineBasicBlock::iterator InsertPos = Def;
478 // FIXME: VR def may not be in entry block.
479 Def->getParent()->insert(std::next(InsertPos), MI);
481 DEBUG(dbgs() << "Dropping debug info for dead vreg"
482 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
485 // If Reg is live-in then update debug info to track its copy in a vreg.
486 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
487 if (LDI != LiveInMap.end()) {
488 assert(!hasFI && "There's no handling of frame pointer updating here yet "
490 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
491 MachineBasicBlock::iterator InsertPos = Def;
492 const MDNode *Variable =
493 MI->getOperand(MI->getNumOperands()-1).getMetadata();
494 bool IsIndirect = MI->isIndirectDebugValue();
495 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
496 // Def is never a terminator here, so it is ok to increment InsertPos.
497 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
498 TII.get(TargetOpcode::DBG_VALUE),
500 LDI->second, Offset, Variable);
502 // If this vreg is directly copied into an exported register then
503 // that COPY instructions also need DBG_VALUE, if it is the only
504 // user of LDI->second.
505 MachineInstr *CopyUseMI = nullptr;
506 for (MachineRegisterInfo::use_instr_iterator
507 UI = RegInfo->use_instr_begin(LDI->second),
508 E = RegInfo->use_instr_end(); UI != E; ) {
509 MachineInstr *UseMI = &*(UI++);
510 if (UseMI->isDebugValue()) continue;
511 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
512 CopyUseMI = UseMI; continue;
514 // Otherwise this is another use or second copy use.
515 CopyUseMI = nullptr; break;
518 MachineInstr *NewMI =
519 BuildMI(*MF, CopyUseMI->getDebugLoc(),
520 TII.get(TargetOpcode::DBG_VALUE),
522 CopyUseMI->getOperand(0).getReg(),
524 MachineBasicBlock::iterator Pos = CopyUseMI;
525 EntryMBB->insertAfter(Pos, NewMI);
530 // Determine if there are any calls in this machine function.
531 MachineFrameInfo *MFI = MF->getFrameInfo();
532 for (const auto &MBB : *MF) {
533 if (MFI->hasCalls() && MF->hasInlineAsm())
536 for (const auto &MI : MBB) {
537 const MCInstrDesc &MCID =
538 TM.getSubtargetImpl()->getInstrInfo()->get(MI.getOpcode());
539 if ((MCID.isCall() && !MCID.isReturn()) ||
540 MI.isStackAligningInlineAsm()) {
541 MFI->setHasCalls(true);
543 if (MI.isInlineAsm()) {
544 MF->setHasInlineAsm(true);
549 // Determine if there is a call to setjmp in the machine function.
550 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
552 // Replace forward-declared registers with the registers containing
553 // the desired value.
554 MachineRegisterInfo &MRI = MF->getRegInfo();
555 for (DenseMap<unsigned, unsigned>::iterator
556 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
558 unsigned From = I->first;
559 unsigned To = I->second;
560 // If To is also scheduled to be replaced, find what its ultimate
563 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
567 // Make sure the new register has a sufficiently constrained register class.
568 if (TargetRegisterInfo::isVirtualRegister(From) &&
569 TargetRegisterInfo::isVirtualRegister(To))
570 MRI.constrainRegClass(To, MRI.getRegClass(From));
572 MRI.replaceRegWith(From, To);
575 // Freeze the set of reserved registers now that MachineFrameInfo has been
576 // set up. All the information required by getReservedRegs() should be
578 MRI.freezeReservedRegs(*MF);
580 // Release function-specific state. SDB and CurDAG are already cleared
584 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
585 DEBUG(MF->print(dbgs()));
590 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
591 BasicBlock::const_iterator End,
593 // Lower all of the non-terminator instructions. If a call is emitted
594 // as a tail call, cease emitting nodes for this block. Terminators
595 // are handled below.
596 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
599 // Make sure the root of the DAG is up-to-date.
600 CurDAG->setRoot(SDB->getControlRoot());
601 HadTailCall = SDB->HasTailCall;
604 // Final step, emit the lowered DAG as machine code.
608 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
609 SmallPtrSet<SDNode*, 128> VisitedNodes;
610 SmallVector<SDNode*, 128> Worklist;
612 Worklist.push_back(CurDAG->getRoot().getNode());
618 SDNode *N = Worklist.pop_back_val();
620 // If we've already seen this node, ignore it.
621 if (!VisitedNodes.insert(N))
624 // Otherwise, add all chain operands to the worklist.
625 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
626 if (N->getOperand(i).getValueType() == MVT::Other)
627 Worklist.push_back(N->getOperand(i).getNode());
629 // If this is a CopyToReg with a vreg dest, process it.
630 if (N->getOpcode() != ISD::CopyToReg)
633 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
634 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
637 // Ignore non-scalar or non-integer values.
638 SDValue Src = N->getOperand(2);
639 EVT SrcVT = Src.getValueType();
640 if (!SrcVT.isInteger() || SrcVT.isVector())
643 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
644 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
645 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
646 } while (!Worklist.empty());
649 void SelectionDAGISel::CodeGenAndEmitDAG() {
650 std::string GroupName;
651 if (TimePassesIsEnabled)
652 GroupName = "Instruction Selection and Scheduling";
653 std::string BlockName;
654 int BlockNumber = -1;
657 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
658 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
662 BlockNumber = FuncInfo->MBB->getNumber();
663 BlockName = MF->getName().str() + ":" +
664 FuncInfo->MBB->getBasicBlock()->getName().str();
666 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
667 << " '" << BlockName << "'\n"; CurDAG->dump());
669 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
671 // Run the DAG combiner in pre-legalize mode.
673 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
674 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
677 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
678 << " '" << BlockName << "'\n"; CurDAG->dump());
680 // Second step, hack on the DAG until it only uses operations and types that
681 // the target supports.
682 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
687 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
688 Changed = CurDAG->LegalizeTypes();
691 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
692 << " '" << BlockName << "'\n"; CurDAG->dump());
694 CurDAG->NewNodesMustHaveLegalTypes = true;
697 if (ViewDAGCombineLT)
698 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
700 // Run the DAG combiner in post-type-legalize mode.
702 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
703 TimePassesIsEnabled);
704 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
707 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
708 << " '" << BlockName << "'\n"; CurDAG->dump());
713 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
714 Changed = CurDAG->LegalizeVectors();
719 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
720 CurDAG->LegalizeTypes();
723 if (ViewDAGCombineLT)
724 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
726 // Run the DAG combiner in post-type-legalize mode.
728 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
729 TimePassesIsEnabled);
730 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
733 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
734 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
737 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
740 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
744 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
745 << " '" << BlockName << "'\n"; CurDAG->dump());
747 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
749 // Run the DAG combiner in post-legalize mode.
751 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
752 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
755 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
756 << " '" << BlockName << "'\n"; CurDAG->dump());
758 if (OptLevel != CodeGenOpt::None)
759 ComputeLiveOutVRegInfo();
761 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
763 // Third, instruction select all of the operations to machine code, adding the
764 // code to the MachineBasicBlock.
766 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
767 DoInstructionSelection();
770 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
771 << " '" << BlockName << "'\n"; CurDAG->dump());
773 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
775 // Schedule machine code.
776 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
778 NamedRegionTimer T("Instruction Scheduling", GroupName,
779 TimePassesIsEnabled);
780 Scheduler->Run(CurDAG, FuncInfo->MBB);
783 if (ViewSUnitDAGs) Scheduler->viewGraph();
785 // Emit machine code to BB. This can change 'BB' to the last block being
787 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
789 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
791 // FuncInfo->InsertPt is passed by reference and set to the end of the
792 // scheduled instructions.
793 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
796 // If the block was split, make sure we update any references that are used to
797 // update PHI nodes later on.
798 if (FirstMBB != LastMBB)
799 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
801 // Free the scheduler state.
803 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
804 TimePassesIsEnabled);
808 // Free the SelectionDAG state, now that we're finished with it.
813 /// ISelUpdater - helper class to handle updates of the instruction selection
815 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
816 SelectionDAG::allnodes_iterator &ISelPosition;
818 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
819 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
821 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
822 /// deleted is the current ISelPosition node, update ISelPosition.
824 void NodeDeleted(SDNode *N, SDNode *E) override {
825 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
829 } // end anonymous namespace
831 void SelectionDAGISel::DoInstructionSelection() {
832 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
833 << FuncInfo->MBB->getNumber()
834 << " '" << FuncInfo->MBB->getName() << "'\n");
838 // Select target instructions for the DAG.
840 // Number all nodes with a topological order and set DAGSize.
841 DAGSize = CurDAG->AssignTopologicalOrder();
843 // Create a dummy node (which is not added to allnodes), that adds
844 // a reference to the root node, preventing it from being deleted,
845 // and tracking any changes of the root.
846 HandleSDNode Dummy(CurDAG->getRoot());
847 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
850 // Make sure that ISelPosition gets properly updated when nodes are deleted
851 // in calls made from this function.
852 ISelUpdater ISU(*CurDAG, ISelPosition);
854 // The AllNodes list is now topological-sorted. Visit the
855 // nodes by starting at the end of the list (the root of the
856 // graph) and preceding back toward the beginning (the entry
858 while (ISelPosition != CurDAG->allnodes_begin()) {
859 SDNode *Node = --ISelPosition;
860 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
861 // but there are currently some corner cases that it misses. Also, this
862 // makes it theoretically possible to disable the DAGCombiner.
863 if (Node->use_empty())
866 SDNode *ResNode = Select(Node);
868 // FIXME: This is pretty gross. 'Select' should be changed to not return
869 // anything at all and this code should be nuked with a tactical strike.
871 // If node should not be replaced, continue with the next one.
872 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
876 ReplaceUses(Node, ResNode);
879 // If after the replacement this node is not used any more,
880 // remove this dead node.
881 if (Node->use_empty()) // Don't delete EntryToken, etc.
882 CurDAG->RemoveDeadNode(Node);
885 CurDAG->setRoot(Dummy.getValue());
888 DEBUG(dbgs() << "===== Instruction selection ends:\n");
890 PostprocessISelDAG();
893 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
894 /// do other setup for EH landing-pad blocks.
895 void SelectionDAGISel::PrepareEHLandingPad() {
896 MachineBasicBlock *MBB = FuncInfo->MBB;
898 // Add a label to mark the beginning of the landing pad. Deletion of the
899 // landing pad can thus be detected via the MachineModuleInfo.
900 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
902 // Assign the call site to the landing pad's begin label.
903 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
905 const MCInstrDesc &II =
906 TM.getSubtargetImpl()->getInstrInfo()->get(TargetOpcode::EH_LABEL);
907 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
910 // Mark exception register as live in.
911 const TargetLowering *TLI = getTargetLowering();
912 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
913 if (unsigned Reg = TLI->getExceptionPointerRegister())
914 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
916 // Mark exception selector register as live in.
917 if (unsigned Reg = TLI->getExceptionSelectorRegister())
918 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
921 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
922 /// side-effect free and is either dead or folded into a generated instruction.
923 /// Return false if it needs to be emitted.
924 static bool isFoldedOrDeadInstruction(const Instruction *I,
925 FunctionLoweringInfo *FuncInfo) {
926 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
927 !isa<TerminatorInst>(I) && // Terminators aren't folded.
928 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
929 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
930 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
934 // Collect per Instruction statistics for fast-isel misses. Only those
935 // instructions that cause the bail are accounted for. It does not account for
936 // instructions higher in the block. Thus, summing the per instructions stats
937 // will not add up to what is reported by NumFastIselFailures.
938 static void collectFailStats(const Instruction *I) {
939 switch (I->getOpcode()) {
940 default: assert (0 && "<Invalid operator> ");
943 case Instruction::Ret: NumFastIselFailRet++; return;
944 case Instruction::Br: NumFastIselFailBr++; return;
945 case Instruction::Switch: NumFastIselFailSwitch++; return;
946 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
947 case Instruction::Invoke: NumFastIselFailInvoke++; return;
948 case Instruction::Resume: NumFastIselFailResume++; return;
949 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
951 // Standard binary operators...
952 case Instruction::Add: NumFastIselFailAdd++; return;
953 case Instruction::FAdd: NumFastIselFailFAdd++; return;
954 case Instruction::Sub: NumFastIselFailSub++; return;
955 case Instruction::FSub: NumFastIselFailFSub++; return;
956 case Instruction::Mul: NumFastIselFailMul++; return;
957 case Instruction::FMul: NumFastIselFailFMul++; return;
958 case Instruction::UDiv: NumFastIselFailUDiv++; return;
959 case Instruction::SDiv: NumFastIselFailSDiv++; return;
960 case Instruction::FDiv: NumFastIselFailFDiv++; return;
961 case Instruction::URem: NumFastIselFailURem++; return;
962 case Instruction::SRem: NumFastIselFailSRem++; return;
963 case Instruction::FRem: NumFastIselFailFRem++; return;
965 // Logical operators...
966 case Instruction::And: NumFastIselFailAnd++; return;
967 case Instruction::Or: NumFastIselFailOr++; return;
968 case Instruction::Xor: NumFastIselFailXor++; return;
970 // Memory instructions...
971 case Instruction::Alloca: NumFastIselFailAlloca++; return;
972 case Instruction::Load: NumFastIselFailLoad++; return;
973 case Instruction::Store: NumFastIselFailStore++; return;
974 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
975 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
976 case Instruction::Fence: NumFastIselFailFence++; return;
977 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
979 // Convert instructions...
980 case Instruction::Trunc: NumFastIselFailTrunc++; return;
981 case Instruction::ZExt: NumFastIselFailZExt++; return;
982 case Instruction::SExt: NumFastIselFailSExt++; return;
983 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
984 case Instruction::FPExt: NumFastIselFailFPExt++; return;
985 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
986 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
987 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
988 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
989 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
990 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
991 case Instruction::BitCast: NumFastIselFailBitCast++; return;
993 // Other instructions...
994 case Instruction::ICmp: NumFastIselFailICmp++; return;
995 case Instruction::FCmp: NumFastIselFailFCmp++; return;
996 case Instruction::PHI: NumFastIselFailPHI++; return;
997 case Instruction::Select: NumFastIselFailSelect++; return;
998 case Instruction::Call: {
999 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1000 switch (Intrinsic->getIntrinsicID()) {
1002 NumFastIselFailIntrinsicCall++; return;
1003 case Intrinsic::sadd_with_overflow:
1004 NumFastIselFailSAddWithOverflow++; return;
1005 case Intrinsic::uadd_with_overflow:
1006 NumFastIselFailUAddWithOverflow++; return;
1007 case Intrinsic::ssub_with_overflow:
1008 NumFastIselFailSSubWithOverflow++; return;
1009 case Intrinsic::usub_with_overflow:
1010 NumFastIselFailUSubWithOverflow++; return;
1011 case Intrinsic::smul_with_overflow:
1012 NumFastIselFailSMulWithOverflow++; return;
1013 case Intrinsic::umul_with_overflow:
1014 NumFastIselFailUMulWithOverflow++; return;
1015 case Intrinsic::frameaddress:
1016 NumFastIselFailFrameaddress++; return;
1017 case Intrinsic::sqrt:
1018 NumFastIselFailSqrt++; return;
1019 case Intrinsic::experimental_stackmap:
1020 NumFastIselFailStackMap++; return;
1021 case Intrinsic::experimental_patchpoint_void: // fall-through
1022 case Intrinsic::experimental_patchpoint_i64:
1023 NumFastIselFailPatchPoint++; return;
1026 NumFastIselFailCall++;
1029 case Instruction::Shl: NumFastIselFailShl++; return;
1030 case Instruction::LShr: NumFastIselFailLShr++; return;
1031 case Instruction::AShr: NumFastIselFailAShr++; return;
1032 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1033 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1034 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1035 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1036 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1037 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1038 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1043 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1044 // Initialize the Fast-ISel state, if needed.
1045 FastISel *FastIS = nullptr;
1046 if (TM.Options.EnableFastISel)
1047 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo);
1049 // Iterate over all basic blocks in the function.
1050 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1051 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1052 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1053 const BasicBlock *LLVMBB = *I;
1055 if (OptLevel != CodeGenOpt::None) {
1056 bool AllPredsVisited = true;
1057 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1059 if (!FuncInfo->VisitedBBs.count(*PI)) {
1060 AllPredsVisited = false;
1065 if (AllPredsVisited) {
1066 for (BasicBlock::const_iterator I = LLVMBB->begin();
1067 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1068 FuncInfo->ComputePHILiveOutRegInfo(PN);
1070 for (BasicBlock::const_iterator I = LLVMBB->begin();
1071 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1072 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1075 FuncInfo->VisitedBBs.insert(LLVMBB);
1078 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1079 BasicBlock::const_iterator const End = LLVMBB->end();
1080 BasicBlock::const_iterator BI = End;
1082 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1083 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1085 // Setup an EH landing-pad block.
1086 FuncInfo->ExceptionPointerVirtReg = 0;
1087 FuncInfo->ExceptionSelectorVirtReg = 0;
1088 if (FuncInfo->MBB->isLandingPad())
1089 PrepareEHLandingPad();
1091 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1093 FastIS->startNewBlock();
1095 // Emit code for any incoming arguments. This must happen before
1096 // beginning FastISel on the entry block.
1097 if (LLVMBB == &Fn.getEntryBlock()) {
1100 // Lower any arguments needed in this block if this is the entry block.
1101 if (!FastIS->LowerArguments()) {
1102 // Fast isel failed to lower these arguments
1103 ++NumFastIselFailLowerArguments;
1104 if (EnableFastISelAbortArgs)
1105 llvm_unreachable("FastISel didn't lower all arguments");
1107 // Use SelectionDAG argument lowering
1109 CurDAG->setRoot(SDB->getControlRoot());
1111 CodeGenAndEmitDAG();
1114 // If we inserted any instructions at the beginning, make a note of
1115 // where they are, so we can be sure to emit subsequent instructions
1117 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1118 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1120 FastIS->setLastLocalValue(nullptr);
1123 unsigned NumFastIselRemaining = std::distance(Begin, End);
1124 // Do FastISel on as many instructions as possible.
1125 for (; BI != Begin; --BI) {
1126 const Instruction *Inst = std::prev(BI);
1128 // If we no longer require this instruction, skip it.
1129 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1130 --NumFastIselRemaining;
1134 // Bottom-up: reset the insert pos at the top, after any local-value
1136 FastIS->recomputeInsertPt();
1138 // Try to select the instruction with FastISel.
1139 if (FastIS->SelectInstruction(Inst)) {
1140 --NumFastIselRemaining;
1141 ++NumFastIselSuccess;
1142 // If fast isel succeeded, skip over all the folded instructions, and
1143 // then see if there is a load right before the selected instructions.
1144 // Try to fold the load if so.
1145 const Instruction *BeforeInst = Inst;
1146 while (BeforeInst != Begin) {
1147 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1148 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1151 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1152 BeforeInst->hasOneUse() &&
1153 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1154 // If we succeeded, don't re-select the load.
1155 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1156 --NumFastIselRemaining;
1157 ++NumFastIselSuccess;
1163 if (EnableFastISelVerbose2)
1164 collectFailStats(Inst);
1167 // Then handle certain instructions as single-LLVM-Instruction blocks.
1168 if (isa<CallInst>(Inst)) {
1170 if (EnableFastISelVerbose || EnableFastISelAbort) {
1171 dbgs() << "FastISel missed call: ";
1175 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1176 unsigned &R = FuncInfo->ValueMap[Inst];
1178 R = FuncInfo->CreateRegs(Inst->getType());
1181 bool HadTailCall = false;
1182 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1183 SelectBasicBlock(Inst, BI, HadTailCall);
1185 // If the call was emitted as a tail call, we're done with the block.
1186 // We also need to delete any previously emitted instructions.
1188 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1193 // Recompute NumFastIselRemaining as Selection DAG instruction
1194 // selection may have handled the call, input args, etc.
1195 unsigned RemainingNow = std::distance(Begin, BI);
1196 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1197 NumFastIselRemaining = RemainingNow;
1201 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1202 // Don't abort, and use a different message for terminator misses.
1203 NumFastIselFailures += NumFastIselRemaining;
1204 if (EnableFastISelVerbose || EnableFastISelAbort) {
1205 dbgs() << "FastISel missed terminator: ";
1209 NumFastIselFailures += NumFastIselRemaining;
1210 if (EnableFastISelVerbose || EnableFastISelAbort) {
1211 dbgs() << "FastISel miss: ";
1214 if (EnableFastISelAbort)
1215 // The "fast" selector couldn't handle something and bailed.
1216 // For the purpose of debugging, just abort.
1217 llvm_unreachable("FastISel didn't select the entire block");
1222 FastIS->recomputeInsertPt();
1224 // Lower any arguments needed in this block if this is the entry block.
1225 if (LLVMBB == &Fn.getEntryBlock()) {
1234 ++NumFastIselBlocks;
1237 // Run SelectionDAG instruction selection on the remainder of the block
1238 // not handled by FastISel. If FastISel is not run, this is the entire
1241 SelectBasicBlock(Begin, BI, HadTailCall);
1245 FuncInfo->PHINodesToUpdate.clear();
1249 SDB->clearDanglingDebugInfo();
1250 SDB->SPDescriptor.resetPerFunctionState();
1253 /// Given that the input MI is before a partial terminator sequence TSeq, return
1254 /// true if M + TSeq also a partial terminator sequence.
1256 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1257 /// lowering copy vregs into physical registers, which are then passed into
1258 /// terminator instructors so we can satisfy ABI constraints. A partial
1259 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1260 /// may be the whole terminator sequence).
1261 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1262 // If we do not have a copy or an implicit def, we return true if and only if
1263 // MI is a debug value.
1264 if (!MI->isCopy() && !MI->isImplicitDef())
1265 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1266 // physical registers if there is debug info associated with the terminator
1267 // of our mbb. We want to include said debug info in our terminator
1268 // sequence, so we return true in that case.
1269 return MI->isDebugValue();
1271 // We have left the terminator sequence if we are not doing one of the
1274 // 1. Copying a vreg into a physical register.
1275 // 2. Copying a vreg into a vreg.
1276 // 3. Defining a register via an implicit def.
1278 // OPI should always be a register definition...
1279 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1280 if (!OPI->isReg() || !OPI->isDef())
1283 // Defining any register via an implicit def is always ok.
1284 if (MI->isImplicitDef())
1287 // Grab the copy source...
1288 MachineInstr::const_mop_iterator OPI2 = OPI;
1290 assert(OPI2 != MI->operands_end()
1291 && "Should have a copy implying we should have 2 arguments.");
1293 // Make sure that the copy dest is not a vreg when the copy source is a
1294 // physical register.
1295 if (!OPI2->isReg() ||
1296 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1297 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1303 /// Find the split point at which to splice the end of BB into its success stack
1304 /// protector check machine basic block.
1306 /// On many platforms, due to ABI constraints, terminators, even before register
1307 /// allocation, use physical registers. This creates an issue for us since
1308 /// physical registers at this point can not travel across basic
1309 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1310 /// when they enter functions and moves them through a sequence of copies back
1311 /// into the physical registers right before the terminator creating a
1312 /// ``Terminator Sequence''. This function is searching for the beginning of the
1313 /// terminator sequence so that we can ensure that we splice off not just the
1314 /// terminator, but additionally the copies that move the vregs into the
1315 /// physical registers.
1316 static MachineBasicBlock::iterator
1317 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1318 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1320 if (SplitPoint == BB->begin())
1323 MachineBasicBlock::iterator Start = BB->begin();
1324 MachineBasicBlock::iterator Previous = SplitPoint;
1327 while (MIIsInTerminatorSequence(Previous)) {
1328 SplitPoint = Previous;
1329 if (Previous == Start)
1338 SelectionDAGISel::FinishBasicBlock() {
1340 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1341 << FuncInfo->PHINodesToUpdate.size() << "\n";
1342 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1343 dbgs() << "Node " << i << " : ("
1344 << FuncInfo->PHINodesToUpdate[i].first
1345 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1347 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1348 SDB->JTCases.empty() &&
1349 SDB->BitTestCases.empty();
1351 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1352 // PHI nodes in successors.
1353 if (MustUpdatePHINodes) {
1354 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1355 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1356 assert(PHI->isPHI() &&
1357 "This is not a machine PHI node that we are updating!");
1358 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1360 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1364 // Handle stack protector.
1365 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1366 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1367 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1369 // Find the split point to split the parent mbb. At the same time copy all
1370 // physical registers used in the tail of parent mbb into virtual registers
1371 // before the split point and back into physical registers after the split
1372 // point. This prevents us needing to deal with Live-ins and many other
1373 // register allocation issues caused by us splitting the parent mbb. The
1374 // register allocator will clean up said virtual copies later on.
1375 MachineBasicBlock::iterator SplitPoint =
1376 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1378 // Splice the terminator of ParentMBB into SuccessMBB.
1379 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1383 // Add compare/jump on neq/jump to the parent BB.
1384 FuncInfo->MBB = ParentMBB;
1385 FuncInfo->InsertPt = ParentMBB->end();
1386 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1387 CurDAG->setRoot(SDB->getRoot());
1389 CodeGenAndEmitDAG();
1391 // CodeGen Failure MBB if we have not codegened it yet.
1392 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1393 if (!FailureMBB->size()) {
1394 FuncInfo->MBB = FailureMBB;
1395 FuncInfo->InsertPt = FailureMBB->end();
1396 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1397 CurDAG->setRoot(SDB->getRoot());
1399 CodeGenAndEmitDAG();
1402 // Clear the Per-BB State.
1403 SDB->SPDescriptor.resetPerBBState();
1406 // If we updated PHI Nodes, return early.
1407 if (MustUpdatePHINodes)
1410 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1411 // Lower header first, if it wasn't already lowered
1412 if (!SDB->BitTestCases[i].Emitted) {
1413 // Set the current basic block to the mbb we wish to insert the code into
1414 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1415 FuncInfo->InsertPt = FuncInfo->MBB->end();
1417 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1418 CurDAG->setRoot(SDB->getRoot());
1420 CodeGenAndEmitDAG();
1423 uint32_t UnhandledWeight = 0;
1424 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1425 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1427 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1428 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1429 // Set the current basic block to the mbb we wish to insert the code into
1430 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1431 FuncInfo->InsertPt = FuncInfo->MBB->end();
1434 SDB->visitBitTestCase(SDB->BitTestCases[i],
1435 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1437 SDB->BitTestCases[i].Reg,
1438 SDB->BitTestCases[i].Cases[j],
1441 SDB->visitBitTestCase(SDB->BitTestCases[i],
1442 SDB->BitTestCases[i].Default,
1444 SDB->BitTestCases[i].Reg,
1445 SDB->BitTestCases[i].Cases[j],
1449 CurDAG->setRoot(SDB->getRoot());
1451 CodeGenAndEmitDAG();
1455 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1457 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1458 MachineBasicBlock *PHIBB = PHI->getParent();
1459 assert(PHI->isPHI() &&
1460 "This is not a machine PHI node that we are updating!");
1461 // This is "default" BB. We have two jumps to it. From "header" BB and
1462 // from last "case" BB.
1463 if (PHIBB == SDB->BitTestCases[i].Default)
1464 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1465 .addMBB(SDB->BitTestCases[i].Parent)
1466 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1467 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1468 // One of "cases" BB.
1469 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1471 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1472 if (cBB->isSuccessor(PHIBB))
1473 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1477 SDB->BitTestCases.clear();
1479 // If the JumpTable record is filled in, then we need to emit a jump table.
1480 // Updating the PHI nodes is tricky in this case, since we need to determine
1481 // whether the PHI is a successor of the range check MBB or the jump table MBB
1482 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1483 // Lower header first, if it wasn't already lowered
1484 if (!SDB->JTCases[i].first.Emitted) {
1485 // Set the current basic block to the mbb we wish to insert the code into
1486 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1487 FuncInfo->InsertPt = FuncInfo->MBB->end();
1489 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1491 CurDAG->setRoot(SDB->getRoot());
1493 CodeGenAndEmitDAG();
1496 // Set the current basic block to the mbb we wish to insert the code into
1497 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1498 FuncInfo->InsertPt = FuncInfo->MBB->end();
1500 SDB->visitJumpTable(SDB->JTCases[i].second);
1501 CurDAG->setRoot(SDB->getRoot());
1503 CodeGenAndEmitDAG();
1506 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1508 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1509 MachineBasicBlock *PHIBB = PHI->getParent();
1510 assert(PHI->isPHI() &&
1511 "This is not a machine PHI node that we are updating!");
1512 // "default" BB. We can go there only from header BB.
1513 if (PHIBB == SDB->JTCases[i].second.Default)
1514 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1515 .addMBB(SDB->JTCases[i].first.HeaderBB);
1516 // JT BB. Just iterate over successors here
1517 if (FuncInfo->MBB->isSuccessor(PHIBB))
1518 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1521 SDB->JTCases.clear();
1523 // If the switch block involved a branch to one of the actual successors, we
1524 // need to update PHI nodes in that block.
1525 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1526 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1527 assert(PHI->isPHI() &&
1528 "This is not a machine PHI node that we are updating!");
1529 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1530 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1533 // If we generated any switch lowering information, build and codegen any
1534 // additional DAGs necessary.
1535 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1536 // Set the current basic block to the mbb we wish to insert the code into
1537 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1538 FuncInfo->InsertPt = FuncInfo->MBB->end();
1540 // Determine the unique successors.
1541 SmallVector<MachineBasicBlock *, 2> Succs;
1542 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1543 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1544 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1546 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1547 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1548 CurDAG->setRoot(SDB->getRoot());
1550 CodeGenAndEmitDAG();
1552 // Remember the last block, now that any splitting is done, for use in
1553 // populating PHI nodes in successors.
1554 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1556 // Handle any PHI nodes in successors of this chunk, as if we were coming
1557 // from the original BB before switch expansion. Note that PHI nodes can
1558 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1559 // handle them the right number of times.
1560 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1561 FuncInfo->MBB = Succs[i];
1562 FuncInfo->InsertPt = FuncInfo->MBB->end();
1563 // FuncInfo->MBB may have been removed from the CFG if a branch was
1565 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1566 for (MachineBasicBlock::iterator
1567 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1568 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1569 MachineInstrBuilder PHI(*MF, MBBI);
1570 // This value for this PHI node is recorded in PHINodesToUpdate.
1571 for (unsigned pn = 0; ; ++pn) {
1572 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1573 "Didn't find PHI entry!");
1574 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1575 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1583 SDB->SwitchCases.clear();
1587 /// Create the scheduler. If a specific scheduler was specified
1588 /// via the SchedulerRegistry, use it, otherwise select the
1589 /// one preferred by the target.
1591 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1592 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1596 RegisterScheduler::setDefault(Ctor);
1599 return Ctor(this, OptLevel);
1602 //===----------------------------------------------------------------------===//
1603 // Helper functions used by the generated instruction selector.
1604 //===----------------------------------------------------------------------===//
1605 // Calls to these methods are generated by tblgen.
1607 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1608 /// the dag combiner simplified the 255, we still want to match. RHS is the
1609 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1610 /// specified in the .td file (e.g. 255).
1611 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1612 int64_t DesiredMaskS) const {
1613 const APInt &ActualMask = RHS->getAPIntValue();
1614 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1616 // If the actual mask exactly matches, success!
1617 if (ActualMask == DesiredMask)
1620 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1621 if (ActualMask.intersects(~DesiredMask))
1624 // Otherwise, the DAG Combiner may have proven that the value coming in is
1625 // either already zero or is not demanded. Check for known zero input bits.
1626 APInt NeededMask = DesiredMask & ~ActualMask;
1627 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1630 // TODO: check to see if missing bits are just not demanded.
1632 // Otherwise, this pattern doesn't match.
1636 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1637 /// the dag combiner simplified the 255, we still want to match. RHS is the
1638 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1639 /// specified in the .td file (e.g. 255).
1640 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1641 int64_t DesiredMaskS) const {
1642 const APInt &ActualMask = RHS->getAPIntValue();
1643 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1645 // If the actual mask exactly matches, success!
1646 if (ActualMask == DesiredMask)
1649 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1650 if (ActualMask.intersects(~DesiredMask))
1653 // Otherwise, the DAG Combiner may have proven that the value coming in is
1654 // either already zero or is not demanded. Check for known zero input bits.
1655 APInt NeededMask = DesiredMask & ~ActualMask;
1657 APInt KnownZero, KnownOne;
1658 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1660 // If all the missing bits in the or are already known to be set, match!
1661 if ((NeededMask & KnownOne) == NeededMask)
1664 // TODO: check to see if missing bits are just not demanded.
1666 // Otherwise, this pattern doesn't match.
1671 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1672 /// by tblgen. Others should not call it.
1673 void SelectionDAGISel::
1674 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1675 std::vector<SDValue> InOps;
1676 std::swap(InOps, Ops);
1678 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1679 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1680 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1681 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1683 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1684 if (InOps[e-1].getValueType() == MVT::Glue)
1685 --e; // Don't process a glue operand if it is here.
1688 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1689 if (!InlineAsm::isMemKind(Flags)) {
1690 // Just skip over this operand, copying the operands verbatim.
1691 Ops.insert(Ops.end(), InOps.begin()+i,
1692 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1693 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1695 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1696 "Memory operand with multiple values?");
1697 // Otherwise, this is a memory operand. Ask the target to select it.
1698 std::vector<SDValue> SelOps;
1699 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1700 report_fatal_error("Could not match memory address. Inline asm"
1703 // Add this to the output node.
1705 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1706 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1707 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1712 // Add the glue input back if present.
1713 if (e != InOps.size())
1714 Ops.push_back(InOps.back());
1717 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1720 static SDNode *findGlueUse(SDNode *N) {
1721 unsigned FlagResNo = N->getNumValues()-1;
1722 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1723 SDUse &Use = I.getUse();
1724 if (Use.getResNo() == FlagResNo)
1725 return Use.getUser();
1730 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1731 /// This function recursively traverses up the operand chain, ignoring
1733 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1734 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1735 bool IgnoreChains) {
1736 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1737 // greater than all of its (recursive) operands. If we scan to a point where
1738 // 'use' is smaller than the node we're scanning for, then we know we will
1741 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1742 // happen because we scan down to newly selected nodes in the case of glue
1744 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1747 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1748 // won't fail if we scan it again.
1749 if (!Visited.insert(Use))
1752 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1753 // Ignore chain uses, they are validated by HandleMergeInputChains.
1754 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1757 SDNode *N = Use->getOperand(i).getNode();
1759 if (Use == ImmedUse || Use == Root)
1760 continue; // We are not looking for immediate use.
1765 // Traverse up the operand chain.
1766 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1772 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1773 /// operand node N of U during instruction selection that starts at Root.
1774 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1775 SDNode *Root) const {
1776 if (OptLevel == CodeGenOpt::None) return false;
1777 return N.hasOneUse();
1780 /// IsLegalToFold - Returns true if the specific operand node N of
1781 /// U can be folded during instruction selection that starts at Root.
1782 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1783 CodeGenOpt::Level OptLevel,
1784 bool IgnoreChains) {
1785 if (OptLevel == CodeGenOpt::None) return false;
1787 // If Root use can somehow reach N through a path that that doesn't contain
1788 // U then folding N would create a cycle. e.g. In the following
1789 // diagram, Root can reach N through X. If N is folded into into Root, then
1790 // X is both a predecessor and a successor of U.
1801 // * indicates nodes to be folded together.
1803 // If Root produces glue, then it gets (even more) interesting. Since it
1804 // will be "glued" together with its glue use in the scheduler, we need to
1805 // check if it might reach N.
1824 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1825 // (call it Fold), then X is a predecessor of GU and a successor of
1826 // Fold. But since Fold and GU are glued together, this will create
1827 // a cycle in the scheduling graph.
1829 // If the node has glue, walk down the graph to the "lowest" node in the
1831 EVT VT = Root->getValueType(Root->getNumValues()-1);
1832 while (VT == MVT::Glue) {
1833 SDNode *GU = findGlueUse(Root);
1837 VT = Root->getValueType(Root->getNumValues()-1);
1839 // If our query node has a glue result with a use, we've walked up it. If
1840 // the user (which has already been selected) has a chain or indirectly uses
1841 // the chain, our WalkChainUsers predicate will not consider it. Because of
1842 // this, we cannot ignore chains in this predicate.
1843 IgnoreChains = false;
1847 SmallPtrSet<SDNode*, 16> Visited;
1848 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1851 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1852 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1853 SelectInlineAsmMemoryOperands(Ops);
1855 EVT VTs[] = { MVT::Other, MVT::Glue };
1856 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
1858 return New.getNode();
1862 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1864 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
1865 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1866 unsigned Reg = getTargetLowering()->getRegisterByName(
1867 RegStr->getString().data(), Op->getValueType(0));
1868 SDValue New = CurDAG->getCopyFromReg(
1869 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
1871 return New.getNode();
1875 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1877 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1878 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1879 unsigned Reg = getTargetLowering()->getRegisterByName(
1880 RegStr->getString().data(), Op->getOperand(2).getValueType());
1881 SDValue New = CurDAG->getCopyToReg(
1882 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
1884 return New.getNode();
1889 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1890 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1893 /// GetVBR - decode a vbr encoding whose top bit is set.
1894 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1895 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1896 assert(Val >= 128 && "Not a VBR");
1897 Val &= 127; // Remove first vbr bit.
1902 NextBits = MatcherTable[Idx++];
1903 Val |= (NextBits&127) << Shift;
1905 } while (NextBits & 128);
1911 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1912 /// interior glue and chain results to use the new glue and chain results.
1913 void SelectionDAGISel::
1914 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1915 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1917 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1918 bool isMorphNodeTo) {
1919 SmallVector<SDNode*, 4> NowDeadNodes;
1921 // Now that all the normal results are replaced, we replace the chain and
1922 // glue results if present.
1923 if (!ChainNodesMatched.empty()) {
1924 assert(InputChain.getNode() &&
1925 "Matched input chains but didn't produce a chain");
1926 // Loop over all of the nodes we matched that produced a chain result.
1927 // Replace all the chain results with the final chain we ended up with.
1928 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1929 SDNode *ChainNode = ChainNodesMatched[i];
1931 // If this node was already deleted, don't look at it.
1932 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1935 // Don't replace the results of the root node if we're doing a
1937 if (ChainNode == NodeToMatch && isMorphNodeTo)
1940 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1941 if (ChainVal.getValueType() == MVT::Glue)
1942 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1943 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1944 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1946 // If the node became dead and we haven't already seen it, delete it.
1947 if (ChainNode->use_empty() &&
1948 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1949 NowDeadNodes.push_back(ChainNode);
1953 // If the result produces glue, update any glue results in the matched
1954 // pattern with the glue result.
1955 if (InputGlue.getNode()) {
1956 // Handle any interior nodes explicitly marked.
1957 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1958 SDNode *FRN = GlueResultNodesMatched[i];
1960 // If this node was already deleted, don't look at it.
1961 if (FRN->getOpcode() == ISD::DELETED_NODE)
1964 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1965 "Doesn't have a glue result");
1966 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1969 // If the node became dead and we haven't already seen it, delete it.
1970 if (FRN->use_empty() &&
1971 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1972 NowDeadNodes.push_back(FRN);
1976 if (!NowDeadNodes.empty())
1977 CurDAG->RemoveDeadNodes(NowDeadNodes);
1979 DEBUG(dbgs() << "ISEL: Match complete!\n");
1985 CR_LeadsToInteriorNode
1988 /// WalkChainUsers - Walk down the users of the specified chained node that is
1989 /// part of the pattern we're matching, looking at all of the users we find.
1990 /// This determines whether something is an interior node, whether we have a
1991 /// non-pattern node in between two pattern nodes (which prevent folding because
1992 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1993 /// between pattern nodes (in which case the TF becomes part of the pattern).
1995 /// The walk we do here is guaranteed to be small because we quickly get down to
1996 /// already selected nodes "below" us.
1998 WalkChainUsers(const SDNode *ChainedNode,
1999 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2000 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2001 ChainResult Result = CR_Simple;
2003 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2004 E = ChainedNode->use_end(); UI != E; ++UI) {
2005 // Make sure the use is of the chain, not some other value we produce.
2006 if (UI.getUse().getValueType() != MVT::Other) continue;
2010 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2013 // If we see an already-selected machine node, then we've gone beyond the
2014 // pattern that we're selecting down into the already selected chunk of the
2016 unsigned UserOpcode = User->getOpcode();
2017 if (User->isMachineOpcode() ||
2018 UserOpcode == ISD::CopyToReg ||
2019 UserOpcode == ISD::CopyFromReg ||
2020 UserOpcode == ISD::INLINEASM ||
2021 UserOpcode == ISD::EH_LABEL ||
2022 UserOpcode == ISD::LIFETIME_START ||
2023 UserOpcode == ISD::LIFETIME_END) {
2024 // If their node ID got reset to -1 then they've already been selected.
2025 // Treat them like a MachineOpcode.
2026 if (User->getNodeId() == -1)
2030 // If we have a TokenFactor, we handle it specially.
2031 if (User->getOpcode() != ISD::TokenFactor) {
2032 // If the node isn't a token factor and isn't part of our pattern, then it
2033 // must be a random chained node in between two nodes we're selecting.
2034 // This happens when we have something like:
2039 // Because we structurally match the load/store as a read/modify/write,
2040 // but the call is chained between them. We cannot fold in this case
2041 // because it would induce a cycle in the graph.
2042 if (!std::count(ChainedNodesInPattern.begin(),
2043 ChainedNodesInPattern.end(), User))
2044 return CR_InducesCycle;
2046 // Otherwise we found a node that is part of our pattern. For example in:
2050 // This would happen when we're scanning down from the load and see the
2051 // store as a user. Record that there is a use of ChainedNode that is
2052 // part of the pattern and keep scanning uses.
2053 Result = CR_LeadsToInteriorNode;
2054 InteriorChainedNodes.push_back(User);
2058 // If we found a TokenFactor, there are two cases to consider: first if the
2059 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2060 // uses of the TF are in our pattern) we just want to ignore it. Second,
2061 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2067 // | \ DAG's like cheese
2070 // [TokenFactor] [Op]
2077 // In this case, the TokenFactor becomes part of our match and we rewrite it
2078 // as a new TokenFactor.
2080 // To distinguish these two cases, do a recursive walk down the uses.
2081 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2083 // If the uses of the TokenFactor are just already-selected nodes, ignore
2084 // it, it is "below" our pattern.
2086 case CR_InducesCycle:
2087 // If the uses of the TokenFactor lead to nodes that are not part of our
2088 // pattern that are not selected, folding would turn this into a cycle,
2090 return CR_InducesCycle;
2091 case CR_LeadsToInteriorNode:
2092 break; // Otherwise, keep processing.
2095 // Okay, we know we're in the interesting interior case. The TokenFactor
2096 // is now going to be considered part of the pattern so that we rewrite its
2097 // uses (it may have uses that are not part of the pattern) with the
2098 // ultimate chain result of the generated code. We will also add its chain
2099 // inputs as inputs to the ultimate TokenFactor we create.
2100 Result = CR_LeadsToInteriorNode;
2101 ChainedNodesInPattern.push_back(User);
2102 InteriorChainedNodes.push_back(User);
2109 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2110 /// operation for when the pattern matched at least one node with a chains. The
2111 /// input vector contains a list of all of the chained nodes that we match. We
2112 /// must determine if this is a valid thing to cover (i.e. matching it won't
2113 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2114 /// be used as the input node chain for the generated nodes.
2116 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2117 SelectionDAG *CurDAG) {
2118 // Walk all of the chained nodes we've matched, recursively scanning down the
2119 // users of the chain result. This adds any TokenFactor nodes that are caught
2120 // in between chained nodes to the chained and interior nodes list.
2121 SmallVector<SDNode*, 3> InteriorChainedNodes;
2122 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2123 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2124 InteriorChainedNodes) == CR_InducesCycle)
2125 return SDValue(); // Would induce a cycle.
2128 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2129 // that we are interested in. Form our input TokenFactor node.
2130 SmallVector<SDValue, 3> InputChains;
2131 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2132 // Add the input chain of this node to the InputChains list (which will be
2133 // the operands of the generated TokenFactor) if it's not an interior node.
2134 SDNode *N = ChainNodesMatched[i];
2135 if (N->getOpcode() != ISD::TokenFactor) {
2136 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2139 // Otherwise, add the input chain.
2140 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2141 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2142 InputChains.push_back(InChain);
2146 // If we have a token factor, we want to add all inputs of the token factor
2147 // that are not part of the pattern we're matching.
2148 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2149 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2150 N->getOperand(op).getNode()))
2151 InputChains.push_back(N->getOperand(op));
2155 if (InputChains.size() == 1)
2156 return InputChains[0];
2157 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2158 MVT::Other, InputChains);
2161 /// MorphNode - Handle morphing a node in place for the selector.
2162 SDNode *SelectionDAGISel::
2163 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2164 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2165 // It is possible we're using MorphNodeTo to replace a node with no
2166 // normal results with one that has a normal result (or we could be
2167 // adding a chain) and the input could have glue and chains as well.
2168 // In this case we need to shift the operands down.
2169 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2170 // than the old isel though.
2171 int OldGlueResultNo = -1, OldChainResultNo = -1;
2173 unsigned NTMNumResults = Node->getNumValues();
2174 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2175 OldGlueResultNo = NTMNumResults-1;
2176 if (NTMNumResults != 1 &&
2177 Node->getValueType(NTMNumResults-2) == MVT::Other)
2178 OldChainResultNo = NTMNumResults-2;
2179 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2180 OldChainResultNo = NTMNumResults-1;
2182 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2183 // that this deletes operands of the old node that become dead.
2184 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2186 // MorphNodeTo can operate in two ways: if an existing node with the
2187 // specified operands exists, it can just return it. Otherwise, it
2188 // updates the node in place to have the requested operands.
2190 // If we updated the node in place, reset the node ID. To the isel,
2191 // this should be just like a newly allocated machine node.
2195 unsigned ResNumResults = Res->getNumValues();
2196 // Move the glue if needed.
2197 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2198 (unsigned)OldGlueResultNo != ResNumResults-1)
2199 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2200 SDValue(Res, ResNumResults-1));
2202 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2205 // Move the chain reference if needed.
2206 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2207 (unsigned)OldChainResultNo != ResNumResults-1)
2208 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2209 SDValue(Res, ResNumResults-1));
2211 // Otherwise, no replacement happened because the node already exists. Replace
2212 // Uses of the old node with the new one.
2214 CurDAG->ReplaceAllUsesWith(Node, Res);
2219 /// CheckSame - Implements OP_CheckSame.
2220 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2221 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2223 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2224 // Accept if it is exactly the same as a previously recorded node.
2225 unsigned RecNo = MatcherTable[MatcherIndex++];
2226 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2227 return N == RecordedNodes[RecNo].first;
2230 /// CheckChildSame - Implements OP_CheckChildXSame.
2231 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2232 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2234 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2236 if (ChildNo >= N.getNumOperands())
2237 return false; // Match fails if out of range child #.
2238 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2242 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2243 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2244 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2245 const SelectionDAGISel &SDISel) {
2246 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2249 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2250 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2251 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2252 const SelectionDAGISel &SDISel, SDNode *N) {
2253 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2256 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2257 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2259 uint16_t Opc = MatcherTable[MatcherIndex++];
2260 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2261 return N->getOpcode() == Opc;
2264 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2265 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2266 SDValue N, const TargetLowering *TLI) {
2267 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2268 if (N.getValueType() == VT) return true;
2270 // Handle the case when VT is iPTR.
2271 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2274 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2275 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2276 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2277 if (ChildNo >= N.getNumOperands())
2278 return false; // Match fails if out of range child #.
2279 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2282 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2283 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2285 return cast<CondCodeSDNode>(N)->get() ==
2286 (ISD::CondCode)MatcherTable[MatcherIndex++];
2289 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2290 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2291 SDValue N, const TargetLowering *TLI) {
2292 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2293 if (cast<VTSDNode>(N)->getVT() == VT)
2296 // Handle the case when VT is iPTR.
2297 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2300 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2301 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2303 int64_t Val = MatcherTable[MatcherIndex++];
2305 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2307 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2308 return C && C->getSExtValue() == Val;
2311 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2312 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2313 SDValue N, unsigned ChildNo) {
2314 if (ChildNo >= N.getNumOperands())
2315 return false; // Match fails if out of range child #.
2316 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2319 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2320 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2321 SDValue N, const SelectionDAGISel &SDISel) {
2322 int64_t Val = MatcherTable[MatcherIndex++];
2324 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2326 if (N->getOpcode() != ISD::AND) return false;
2328 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2329 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2332 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2333 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2334 SDValue N, const SelectionDAGISel &SDISel) {
2335 int64_t Val = MatcherTable[MatcherIndex++];
2337 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2339 if (N->getOpcode() != ISD::OR) return false;
2341 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2342 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2345 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2346 /// scope, evaluate the current node. If the current predicate is known to
2347 /// fail, set Result=true and return anything. If the current predicate is
2348 /// known to pass, set Result=false and return the MatcherIndex to continue
2349 /// with. If the current predicate is unknown, set Result=false and return the
2350 /// MatcherIndex to continue with.
2351 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2352 unsigned Index, SDValue N,
2354 const SelectionDAGISel &SDISel,
2355 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2356 switch (Table[Index++]) {
2359 return Index-1; // Could not evaluate this predicate.
2360 case SelectionDAGISel::OPC_CheckSame:
2361 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2363 case SelectionDAGISel::OPC_CheckChild0Same:
2364 case SelectionDAGISel::OPC_CheckChild1Same:
2365 case SelectionDAGISel::OPC_CheckChild2Same:
2366 case SelectionDAGISel::OPC_CheckChild3Same:
2367 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2368 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2370 case SelectionDAGISel::OPC_CheckPatternPredicate:
2371 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2373 case SelectionDAGISel::OPC_CheckPredicate:
2374 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2376 case SelectionDAGISel::OPC_CheckOpcode:
2377 Result = !::CheckOpcode(Table, Index, N.getNode());
2379 case SelectionDAGISel::OPC_CheckType:
2380 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering());
2382 case SelectionDAGISel::OPC_CheckChild0Type:
2383 case SelectionDAGISel::OPC_CheckChild1Type:
2384 case SelectionDAGISel::OPC_CheckChild2Type:
2385 case SelectionDAGISel::OPC_CheckChild3Type:
2386 case SelectionDAGISel::OPC_CheckChild4Type:
2387 case SelectionDAGISel::OPC_CheckChild5Type:
2388 case SelectionDAGISel::OPC_CheckChild6Type:
2389 case SelectionDAGISel::OPC_CheckChild7Type:
2390 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(),
2391 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2393 case SelectionDAGISel::OPC_CheckCondCode:
2394 Result = !::CheckCondCode(Table, Index, N);
2396 case SelectionDAGISel::OPC_CheckValueType:
2397 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering());
2399 case SelectionDAGISel::OPC_CheckInteger:
2400 Result = !::CheckInteger(Table, Index, N);
2402 case SelectionDAGISel::OPC_CheckChild0Integer:
2403 case SelectionDAGISel::OPC_CheckChild1Integer:
2404 case SelectionDAGISel::OPC_CheckChild2Integer:
2405 case SelectionDAGISel::OPC_CheckChild3Integer:
2406 case SelectionDAGISel::OPC_CheckChild4Integer:
2407 Result = !::CheckChildInteger(Table, Index, N,
2408 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2410 case SelectionDAGISel::OPC_CheckAndImm:
2411 Result = !::CheckAndImm(Table, Index, N, SDISel);
2413 case SelectionDAGISel::OPC_CheckOrImm:
2414 Result = !::CheckOrImm(Table, Index, N, SDISel);
2422 /// FailIndex - If this match fails, this is the index to continue with.
2425 /// NodeStack - The node stack when the scope was formed.
2426 SmallVector<SDValue, 4> NodeStack;
2428 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2429 unsigned NumRecordedNodes;
2431 /// NumMatchedMemRefs - The number of matched memref entries.
2432 unsigned NumMatchedMemRefs;
2434 /// InputChain/InputGlue - The current chain/glue
2435 SDValue InputChain, InputGlue;
2437 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2438 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2443 SDNode *SelectionDAGISel::
2444 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2445 unsigned TableSize) {
2446 // FIXME: Should these even be selected? Handle these cases in the caller?
2447 switch (NodeToMatch->getOpcode()) {
2450 case ISD::EntryToken: // These nodes remain the same.
2451 case ISD::BasicBlock:
2453 case ISD::RegisterMask:
2454 case ISD::HANDLENODE:
2455 case ISD::MDNODE_SDNODE:
2456 case ISD::TargetConstant:
2457 case ISD::TargetConstantFP:
2458 case ISD::TargetConstantPool:
2459 case ISD::TargetFrameIndex:
2460 case ISD::TargetExternalSymbol:
2461 case ISD::TargetBlockAddress:
2462 case ISD::TargetJumpTable:
2463 case ISD::TargetGlobalTLSAddress:
2464 case ISD::TargetGlobalAddress:
2465 case ISD::TokenFactor:
2466 case ISD::CopyFromReg:
2467 case ISD::CopyToReg:
2469 case ISD::LIFETIME_START:
2470 case ISD::LIFETIME_END:
2471 NodeToMatch->setNodeId(-1); // Mark selected.
2473 case ISD::AssertSext:
2474 case ISD::AssertZext:
2475 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2476 NodeToMatch->getOperand(0));
2478 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2479 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2480 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2481 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2484 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2486 // Set up the node stack with NodeToMatch as the only node on the stack.
2487 SmallVector<SDValue, 8> NodeStack;
2488 SDValue N = SDValue(NodeToMatch, 0);
2489 NodeStack.push_back(N);
2491 // MatchScopes - Scopes used when matching, if a match failure happens, this
2492 // indicates where to continue checking.
2493 SmallVector<MatchScope, 8> MatchScopes;
2495 // RecordedNodes - This is the set of nodes that have been recorded by the
2496 // state machine. The second value is the parent of the node, or null if the
2497 // root is recorded.
2498 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2500 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2502 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2504 // These are the current input chain and glue for use when generating nodes.
2505 // Various Emit operations change these. For example, emitting a copytoreg
2506 // uses and updates these.
2507 SDValue InputChain, InputGlue;
2509 // ChainNodesMatched - If a pattern matches nodes that have input/output
2510 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2511 // which ones they are. The result is captured into this list so that we can
2512 // update the chain results when the pattern is complete.
2513 SmallVector<SDNode*, 3> ChainNodesMatched;
2514 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2516 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2517 NodeToMatch->dump(CurDAG);
2520 // Determine where to start the interpreter. Normally we start at opcode #0,
2521 // but if the state machine starts with an OPC_SwitchOpcode, then we
2522 // accelerate the first lookup (which is guaranteed to be hot) with the
2523 // OpcodeOffset table.
2524 unsigned MatcherIndex = 0;
2526 if (!OpcodeOffset.empty()) {
2527 // Already computed the OpcodeOffset table, just index into it.
2528 if (N.getOpcode() < OpcodeOffset.size())
2529 MatcherIndex = OpcodeOffset[N.getOpcode()];
2530 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2532 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2533 // Otherwise, the table isn't computed, but the state machine does start
2534 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2535 // is the first time we're selecting an instruction.
2538 // Get the size of this case.
2539 unsigned CaseSize = MatcherTable[Idx++];
2541 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2542 if (CaseSize == 0) break;
2544 // Get the opcode, add the index to the table.
2545 uint16_t Opc = MatcherTable[Idx++];
2546 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2547 if (Opc >= OpcodeOffset.size())
2548 OpcodeOffset.resize((Opc+1)*2);
2549 OpcodeOffset[Opc] = Idx;
2553 // Okay, do the lookup for the first opcode.
2554 if (N.getOpcode() < OpcodeOffset.size())
2555 MatcherIndex = OpcodeOffset[N.getOpcode()];
2559 assert(MatcherIndex < TableSize && "Invalid index");
2561 unsigned CurrentOpcodeIndex = MatcherIndex;
2563 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2566 // Okay, the semantics of this operation are that we should push a scope
2567 // then evaluate the first child. However, pushing a scope only to have
2568 // the first check fail (which then pops it) is inefficient. If we can
2569 // determine immediately that the first check (or first several) will
2570 // immediately fail, don't even bother pushing a scope for them.
2574 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2575 if (NumToSkip & 128)
2576 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2577 // Found the end of the scope with no match.
2578 if (NumToSkip == 0) {
2583 FailIndex = MatcherIndex+NumToSkip;
2585 unsigned MatcherIndexOfPredicate = MatcherIndex;
2586 (void)MatcherIndexOfPredicate; // silence warning.
2588 // If we can't evaluate this predicate without pushing a scope (e.g. if
2589 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2590 // push the scope and evaluate the full predicate chain.
2592 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2593 Result, *this, RecordedNodes);
2597 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2598 << "index " << MatcherIndexOfPredicate
2599 << ", continuing at " << FailIndex << "\n");
2600 ++NumDAGIselRetries;
2602 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2603 // move to the next case.
2604 MatcherIndex = FailIndex;
2607 // If the whole scope failed to match, bail.
2608 if (FailIndex == 0) break;
2610 // Push a MatchScope which indicates where to go if the first child fails
2612 MatchScope NewEntry;
2613 NewEntry.FailIndex = FailIndex;
2614 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2615 NewEntry.NumRecordedNodes = RecordedNodes.size();
2616 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2617 NewEntry.InputChain = InputChain;
2618 NewEntry.InputGlue = InputGlue;
2619 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2620 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2621 MatchScopes.push_back(NewEntry);
2624 case OPC_RecordNode: {
2625 // Remember this node, it may end up being an operand in the pattern.
2626 SDNode *Parent = nullptr;
2627 if (NodeStack.size() > 1)
2628 Parent = NodeStack[NodeStack.size()-2].getNode();
2629 RecordedNodes.push_back(std::make_pair(N, Parent));
2633 case OPC_RecordChild0: case OPC_RecordChild1:
2634 case OPC_RecordChild2: case OPC_RecordChild3:
2635 case OPC_RecordChild4: case OPC_RecordChild5:
2636 case OPC_RecordChild6: case OPC_RecordChild7: {
2637 unsigned ChildNo = Opcode-OPC_RecordChild0;
2638 if (ChildNo >= N.getNumOperands())
2639 break; // Match fails if out of range child #.
2641 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2645 case OPC_RecordMemRef:
2646 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2649 case OPC_CaptureGlueInput:
2650 // If the current node has an input glue, capture it in InputGlue.
2651 if (N->getNumOperands() != 0 &&
2652 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2653 InputGlue = N->getOperand(N->getNumOperands()-1);
2656 case OPC_MoveChild: {
2657 unsigned ChildNo = MatcherTable[MatcherIndex++];
2658 if (ChildNo >= N.getNumOperands())
2659 break; // Match fails if out of range child #.
2660 N = N.getOperand(ChildNo);
2661 NodeStack.push_back(N);
2665 case OPC_MoveParent:
2666 // Pop the current node off the NodeStack.
2667 NodeStack.pop_back();
2668 assert(!NodeStack.empty() && "Node stack imbalance!");
2669 N = NodeStack.back();
2673 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2676 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2677 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2678 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2679 Opcode-OPC_CheckChild0Same))
2683 case OPC_CheckPatternPredicate:
2684 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2686 case OPC_CheckPredicate:
2687 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2691 case OPC_CheckComplexPat: {
2692 unsigned CPNum = MatcherTable[MatcherIndex++];
2693 unsigned RecNo = MatcherTable[MatcherIndex++];
2694 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2695 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2696 RecordedNodes[RecNo].first, CPNum,
2701 case OPC_CheckOpcode:
2702 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2706 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2710 case OPC_SwitchOpcode: {
2711 unsigned CurNodeOpcode = N.getOpcode();
2712 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2715 // Get the size of this case.
2716 CaseSize = MatcherTable[MatcherIndex++];
2718 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2719 if (CaseSize == 0) break;
2721 uint16_t Opc = MatcherTable[MatcherIndex++];
2722 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2724 // If the opcode matches, then we will execute this case.
2725 if (CurNodeOpcode == Opc)
2728 // Otherwise, skip over this case.
2729 MatcherIndex += CaseSize;
2732 // If no cases matched, bail out.
2733 if (CaseSize == 0) break;
2735 // Otherwise, execute the case we found.
2736 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2737 << " to " << MatcherIndex << "\n");
2741 case OPC_SwitchType: {
2742 MVT CurNodeVT = N.getSimpleValueType();
2743 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2746 // Get the size of this case.
2747 CaseSize = MatcherTable[MatcherIndex++];
2749 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2750 if (CaseSize == 0) break;
2752 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2753 if (CaseVT == MVT::iPTR)
2754 CaseVT = getTargetLowering()->getPointerTy();
2756 // If the VT matches, then we will execute this case.
2757 if (CurNodeVT == CaseVT)
2760 // Otherwise, skip over this case.
2761 MatcherIndex += CaseSize;
2764 // If no cases matched, bail out.
2765 if (CaseSize == 0) break;
2767 // Otherwise, execute the case we found.
2768 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2769 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2772 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2773 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2774 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2775 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2776 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(),
2777 Opcode-OPC_CheckChild0Type))
2780 case OPC_CheckCondCode:
2781 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2783 case OPC_CheckValueType:
2784 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2787 case OPC_CheckInteger:
2788 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2790 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2791 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2792 case OPC_CheckChild4Integer:
2793 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2794 Opcode-OPC_CheckChild0Integer)) break;
2796 case OPC_CheckAndImm:
2797 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2799 case OPC_CheckOrImm:
2800 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2803 case OPC_CheckFoldableChainNode: {
2804 assert(NodeStack.size() != 1 && "No parent node");
2805 // Verify that all intermediate nodes between the root and this one have
2807 bool HasMultipleUses = false;
2808 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2809 if (!NodeStack[i].hasOneUse()) {
2810 HasMultipleUses = true;
2813 if (HasMultipleUses) break;
2815 // Check to see that the target thinks this is profitable to fold and that
2816 // we can fold it without inducing cycles in the graph.
2817 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2819 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2820 NodeToMatch, OptLevel,
2821 true/*We validate our own chains*/))
2826 case OPC_EmitInteger: {
2827 MVT::SimpleValueType VT =
2828 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2829 int64_t Val = MatcherTable[MatcherIndex++];
2831 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2832 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2833 CurDAG->getTargetConstant(Val, VT), nullptr));
2836 case OPC_EmitRegister: {
2837 MVT::SimpleValueType VT =
2838 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2839 unsigned RegNo = MatcherTable[MatcherIndex++];
2840 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2841 CurDAG->getRegister(RegNo, VT), nullptr));
2844 case OPC_EmitRegister2: {
2845 // For targets w/ more than 256 register names, the register enum
2846 // values are stored in two bytes in the matcher table (just like
2848 MVT::SimpleValueType VT =
2849 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2850 unsigned RegNo = MatcherTable[MatcherIndex++];
2851 RegNo |= MatcherTable[MatcherIndex++] << 8;
2852 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2853 CurDAG->getRegister(RegNo, VT), nullptr));
2857 case OPC_EmitConvertToTarget: {
2858 // Convert from IMM/FPIMM to target version.
2859 unsigned RecNo = MatcherTable[MatcherIndex++];
2860 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2861 SDValue Imm = RecordedNodes[RecNo].first;
2863 if (Imm->getOpcode() == ISD::Constant) {
2864 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2865 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2866 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2867 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2868 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2871 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2875 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2876 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2877 // These are space-optimized forms of OPC_EmitMergeInputChains.
2878 assert(!InputChain.getNode() &&
2879 "EmitMergeInputChains should be the first chain producing node");
2880 assert(ChainNodesMatched.empty() &&
2881 "Should only have one EmitMergeInputChains per match");
2883 // Read all of the chained nodes.
2884 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2885 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2886 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2888 // FIXME: What if other value results of the node have uses not matched
2890 if (ChainNodesMatched.back() != NodeToMatch &&
2891 !RecordedNodes[RecNo].first.hasOneUse()) {
2892 ChainNodesMatched.clear();
2896 // Merge the input chains if they are not intra-pattern references.
2897 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2899 if (!InputChain.getNode())
2900 break; // Failed to merge.
2904 case OPC_EmitMergeInputChains: {
2905 assert(!InputChain.getNode() &&
2906 "EmitMergeInputChains should be the first chain producing node");
2907 // This node gets a list of nodes we matched in the input that have
2908 // chains. We want to token factor all of the input chains to these nodes
2909 // together. However, if any of the input chains is actually one of the
2910 // nodes matched in this pattern, then we have an intra-match reference.
2911 // Ignore these because the newly token factored chain should not refer to
2913 unsigned NumChains = MatcherTable[MatcherIndex++];
2914 assert(NumChains != 0 && "Can't TF zero chains");
2916 assert(ChainNodesMatched.empty() &&
2917 "Should only have one EmitMergeInputChains per match");
2919 // Read all of the chained nodes.
2920 for (unsigned i = 0; i != NumChains; ++i) {
2921 unsigned RecNo = MatcherTable[MatcherIndex++];
2922 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2923 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2925 // FIXME: What if other value results of the node have uses not matched
2927 if (ChainNodesMatched.back() != NodeToMatch &&
2928 !RecordedNodes[RecNo].first.hasOneUse()) {
2929 ChainNodesMatched.clear();
2934 // If the inner loop broke out, the match fails.
2935 if (ChainNodesMatched.empty())
2938 // Merge the input chains if they are not intra-pattern references.
2939 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2941 if (!InputChain.getNode())
2942 break; // Failed to merge.
2947 case OPC_EmitCopyToReg: {
2948 unsigned RecNo = MatcherTable[MatcherIndex++];
2949 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
2950 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2952 if (!InputChain.getNode())
2953 InputChain = CurDAG->getEntryNode();
2955 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2956 DestPhysReg, RecordedNodes[RecNo].first,
2959 InputGlue = InputChain.getValue(1);
2963 case OPC_EmitNodeXForm: {
2964 unsigned XFormNo = MatcherTable[MatcherIndex++];
2965 unsigned RecNo = MatcherTable[MatcherIndex++];
2966 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
2967 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2968 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
2973 case OPC_MorphNodeTo: {
2974 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2975 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2976 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2977 // Get the result VT list.
2978 unsigned NumVTs = MatcherTable[MatcherIndex++];
2979 SmallVector<EVT, 4> VTs;
2980 for (unsigned i = 0; i != NumVTs; ++i) {
2981 MVT::SimpleValueType VT =
2982 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2983 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy;
2987 if (EmitNodeInfo & OPFL_Chain)
2988 VTs.push_back(MVT::Other);
2989 if (EmitNodeInfo & OPFL_GlueOutput)
2990 VTs.push_back(MVT::Glue);
2992 // This is hot code, so optimize the two most common cases of 1 and 2
2995 if (VTs.size() == 1)
2996 VTList = CurDAG->getVTList(VTs[0]);
2997 else if (VTs.size() == 2)
2998 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3000 VTList = CurDAG->getVTList(VTs);
3002 // Get the operand list.
3003 unsigned NumOps = MatcherTable[MatcherIndex++];
3004 SmallVector<SDValue, 8> Ops;
3005 for (unsigned i = 0; i != NumOps; ++i) {
3006 unsigned RecNo = MatcherTable[MatcherIndex++];
3008 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3010 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3011 Ops.push_back(RecordedNodes[RecNo].first);
3014 // If there are variadic operands to add, handle them now.
3015 if (EmitNodeInfo & OPFL_VariadicInfo) {
3016 // Determine the start index to copy from.
3017 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3018 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3019 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3020 "Invalid variadic node");
3021 // Copy all of the variadic operands, not including a potential glue
3023 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3025 SDValue V = NodeToMatch->getOperand(i);
3026 if (V.getValueType() == MVT::Glue) break;
3031 // If this has chain/glue inputs, add them.
3032 if (EmitNodeInfo & OPFL_Chain)
3033 Ops.push_back(InputChain);
3034 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3035 Ops.push_back(InputGlue);
3038 SDNode *Res = nullptr;
3039 if (Opcode != OPC_MorphNodeTo) {
3040 // If this is a normal EmitNode command, just create the new node and
3041 // add the results to the RecordedNodes list.
3042 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3045 // Add all the non-glue/non-chain results to the RecordedNodes list.
3046 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3047 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3048 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3052 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3053 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3055 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3056 // We will visit the equivalent node later.
3057 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3061 // If the node had chain/glue results, update our notion of the current
3063 if (EmitNodeInfo & OPFL_GlueOutput) {
3064 InputGlue = SDValue(Res, VTs.size()-1);
3065 if (EmitNodeInfo & OPFL_Chain)
3066 InputChain = SDValue(Res, VTs.size()-2);
3067 } else if (EmitNodeInfo & OPFL_Chain)
3068 InputChain = SDValue(Res, VTs.size()-1);
3070 // If the OPFL_MemRefs glue is set on this node, slap all of the
3071 // accumulated memrefs onto it.
3073 // FIXME: This is vastly incorrect for patterns with multiple outputs
3074 // instructions that access memory and for ComplexPatterns that match
3076 if (EmitNodeInfo & OPFL_MemRefs) {
3077 // Only attach load or store memory operands if the generated
3078 // instruction may load or store.
3079 const MCInstrDesc &MCID =
3080 TM.getSubtargetImpl()->getInstrInfo()->get(TargetOpc);
3081 bool mayLoad = MCID.mayLoad();
3082 bool mayStore = MCID.mayStore();
3084 unsigned NumMemRefs = 0;
3085 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3086 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3087 if ((*I)->isLoad()) {
3090 } else if ((*I)->isStore()) {
3098 MachineSDNode::mmo_iterator MemRefs =
3099 MF->allocateMemRefsArray(NumMemRefs);
3101 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3102 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3103 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3104 if ((*I)->isLoad()) {
3107 } else if ((*I)->isStore()) {
3115 cast<MachineSDNode>(Res)
3116 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3120 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3121 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3123 // If this was a MorphNodeTo then we're completely done!
3124 if (Opcode == OPC_MorphNodeTo) {
3125 // Update chain and glue uses.
3126 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3127 InputGlue, GlueResultNodesMatched, true);
3134 case OPC_MarkGlueResults: {
3135 unsigned NumNodes = MatcherTable[MatcherIndex++];
3137 // Read and remember all the glue-result nodes.
3138 for (unsigned i = 0; i != NumNodes; ++i) {
3139 unsigned RecNo = MatcherTable[MatcherIndex++];
3141 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3143 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3144 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3149 case OPC_CompleteMatch: {
3150 // The match has been completed, and any new nodes (if any) have been
3151 // created. Patch up references to the matched dag to use the newly
3153 unsigned NumResults = MatcherTable[MatcherIndex++];
3155 for (unsigned i = 0; i != NumResults; ++i) {
3156 unsigned ResSlot = MatcherTable[MatcherIndex++];
3158 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3160 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3161 SDValue Res = RecordedNodes[ResSlot].first;
3163 assert(i < NodeToMatch->getNumValues() &&
3164 NodeToMatch->getValueType(i) != MVT::Other &&
3165 NodeToMatch->getValueType(i) != MVT::Glue &&
3166 "Invalid number of results to complete!");
3167 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3168 NodeToMatch->getValueType(i) == MVT::iPTR ||
3169 Res.getValueType() == MVT::iPTR ||
3170 NodeToMatch->getValueType(i).getSizeInBits() ==
3171 Res.getValueType().getSizeInBits()) &&
3172 "invalid replacement");
3173 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3176 // If the root node defines glue, add it to the glue nodes to update list.
3177 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3178 GlueResultNodesMatched.push_back(NodeToMatch);
3180 // Update chain and glue uses.
3181 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3182 InputGlue, GlueResultNodesMatched, false);
3184 assert(NodeToMatch->use_empty() &&
3185 "Didn't replace all uses of the node?");
3187 // FIXME: We just return here, which interacts correctly with SelectRoot
3188 // above. We should fix this to not return an SDNode* anymore.
3193 // If the code reached this point, then the match failed. See if there is
3194 // another child to try in the current 'Scope', otherwise pop it until we
3195 // find a case to check.
3196 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3197 ++NumDAGIselRetries;
3199 if (MatchScopes.empty()) {
3200 CannotYetSelect(NodeToMatch);
3204 // Restore the interpreter state back to the point where the scope was
3206 MatchScope &LastScope = MatchScopes.back();
3207 RecordedNodes.resize(LastScope.NumRecordedNodes);
3209 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3210 N = NodeStack.back();
3212 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3213 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3214 MatcherIndex = LastScope.FailIndex;
3216 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3218 InputChain = LastScope.InputChain;
3219 InputGlue = LastScope.InputGlue;
3220 if (!LastScope.HasChainNodesMatched)
3221 ChainNodesMatched.clear();
3222 if (!LastScope.HasGlueResultNodesMatched)
3223 GlueResultNodesMatched.clear();
3225 // Check to see what the offset is at the new MatcherIndex. If it is zero
3226 // we have reached the end of this scope, otherwise we have another child
3227 // in the current scope to try.
3228 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3229 if (NumToSkip & 128)
3230 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3232 // If we have another child in this scope to match, update FailIndex and
3234 if (NumToSkip != 0) {
3235 LastScope.FailIndex = MatcherIndex+NumToSkip;
3239 // End of this scope, pop it and try the next child in the containing
3241 MatchScopes.pop_back();
3248 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3250 raw_string_ostream Msg(msg);
3251 Msg << "Cannot select: ";
3253 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3254 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3255 N->getOpcode() != ISD::INTRINSIC_VOID) {
3256 N->printrFull(Msg, CurDAG);
3257 Msg << "\nIn function: " << MF->getName();
3259 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3261 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3262 if (iid < Intrinsic::num_intrinsics)
3263 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3264 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3265 Msg << "target intrinsic %" << TII->getName(iid);
3267 Msg << "unknown intrinsic #" << iid;
3269 report_fatal_error(Msg.str());
3272 char SelectionDAGISel::ID = 0;