1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/EHPersonalities.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGISel.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/InlineAsm.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/IntrinsicInst.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/IR/LLVMContext.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/MC/MCAsmInfo.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetIntrinsicInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Target/TargetOptions.h"
58 #include "llvm/Target/TargetRegisterInfo.h"
59 #include "llvm/Target/TargetSubtargetInfo.h"
60 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
64 #define DEBUG_TYPE "isel"
66 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
67 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
68 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
69 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
70 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
71 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
72 STATISTIC(NumFastIselFailLowerArguments,
73 "Number of entry blocks where fast isel failed to lower arguments");
77 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
78 cl::desc("Enable extra verbose messages in the \"fast\" "
79 "instruction selector"));
82 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
83 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
84 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
85 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
86 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
87 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
88 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
90 // Standard binary operators...
91 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
92 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
93 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
94 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
95 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
96 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
97 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
98 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
99 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
100 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
101 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
102 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
104 // Logical operators...
105 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
106 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
107 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
109 // Memory instructions...
110 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
111 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
112 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
113 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
114 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
115 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
116 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
118 // Convert instructions...
119 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
120 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
121 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
122 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
123 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
124 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
125 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
126 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
127 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
128 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
129 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
130 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
132 // Other instructions...
133 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
134 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
135 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
136 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
137 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
138 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
139 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
140 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
141 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
142 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
143 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
144 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
145 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
146 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
147 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
149 // Intrinsic instructions...
150 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
151 STATISTIC(NumFastIselFailSAddWithOverflow,
152 "Fast isel fails on sadd.with.overflow");
153 STATISTIC(NumFastIselFailUAddWithOverflow,
154 "Fast isel fails on uadd.with.overflow");
155 STATISTIC(NumFastIselFailSSubWithOverflow,
156 "Fast isel fails on ssub.with.overflow");
157 STATISTIC(NumFastIselFailUSubWithOverflow,
158 "Fast isel fails on usub.with.overflow");
159 STATISTIC(NumFastIselFailSMulWithOverflow,
160 "Fast isel fails on smul.with.overflow");
161 STATISTIC(NumFastIselFailUMulWithOverflow,
162 "Fast isel fails on umul.with.overflow");
163 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
164 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
165 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
166 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
170 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
171 cl::desc("Enable verbose messages in the \"fast\" "
172 "instruction selector"));
173 static cl::opt<int> EnableFastISelAbort(
174 "fast-isel-abort", cl::Hidden,
175 cl::desc("Enable abort calls when \"fast\" instruction selection "
176 "fails to lower an instruction: 0 disable the abort, 1 will "
177 "abort but for args, calls and terminators, 2 will also "
178 "abort for argument lowering, and 3 will never fallback "
179 "to SelectionDAG."));
183 cl::desc("use Machine Branch Probability Info"),
184 cl::init(true), cl::Hidden);
187 static cl::opt<std::string>
188 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
189 cl::desc("Only display the basic block whose name "
190 "matches this for all view-*-dags options"));
192 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
193 cl::desc("Pop up a window to show dags before the first "
194 "dag combine pass"));
196 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
197 cl::desc("Pop up a window to show dags before legalize types"));
199 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
200 cl::desc("Pop up a window to show dags before legalize"));
202 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
203 cl::desc("Pop up a window to show dags before the second "
204 "dag combine pass"));
206 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
207 cl::desc("Pop up a window to show dags before the post legalize types"
208 " dag combine pass"));
210 ViewISelDAGs("view-isel-dags", cl::Hidden,
211 cl::desc("Pop up a window to show isel dags as they are selected"));
213 ViewSchedDAGs("view-sched-dags", cl::Hidden,
214 cl::desc("Pop up a window to show sched dags as they are processed"));
216 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
217 cl::desc("Pop up a window to show SUnit dags after they are processed"));
219 static const bool ViewDAGCombine1 = false,
220 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
221 ViewDAGCombine2 = false,
222 ViewDAGCombineLT = false,
223 ViewISelDAGs = false, ViewSchedDAGs = false,
224 ViewSUnitDAGs = false;
227 //===---------------------------------------------------------------------===//
229 /// RegisterScheduler class - Track the registration of instruction schedulers.
231 //===---------------------------------------------------------------------===//
232 MachinePassRegistry RegisterScheduler::Registry;
234 //===---------------------------------------------------------------------===//
236 /// ISHeuristic command line option for instruction schedulers.
238 //===---------------------------------------------------------------------===//
239 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
240 RegisterPassParser<RegisterScheduler> >
241 ISHeuristic("pre-RA-sched",
242 cl::init(&createDefaultScheduler), cl::Hidden,
243 cl::desc("Instruction schedulers available (before register"
246 static RegisterScheduler
247 defaultListDAGScheduler("default", "Best scheduler for the target",
248 createDefaultScheduler);
251 //===--------------------------------------------------------------------===//
252 /// \brief This class is used by SelectionDAGISel to temporarily override
253 /// the optimization level on a per-function basis.
254 class OptLevelChanger {
255 SelectionDAGISel &IS;
256 CodeGenOpt::Level SavedOptLevel;
260 OptLevelChanger(SelectionDAGISel &ISel,
261 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
262 SavedOptLevel = IS.OptLevel;
263 if (NewOptLevel == SavedOptLevel)
265 IS.OptLevel = NewOptLevel;
266 IS.TM.setOptLevel(NewOptLevel);
267 DEBUG(dbgs() << "\nChanging optimization level for Function "
268 << IS.MF->getFunction()->getName() << "\n");
269 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
270 << " ; After: -O" << NewOptLevel << "\n");
271 SavedFastISel = IS.TM.Options.EnableFastISel;
272 if (NewOptLevel == CodeGenOpt::None) {
273 IS.TM.setFastISel(IS.TM.getO0WantsFastISel());
274 DEBUG(dbgs() << "\tFastISel is "
275 << (IS.TM.Options.EnableFastISel ? "enabled" : "disabled")
281 if (IS.OptLevel == SavedOptLevel)
283 DEBUG(dbgs() << "\nRestoring optimization level for Function "
284 << IS.MF->getFunction()->getName() << "\n");
285 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
286 << " ; After: -O" << SavedOptLevel << "\n");
287 IS.OptLevel = SavedOptLevel;
288 IS.TM.setOptLevel(SavedOptLevel);
289 IS.TM.setFastISel(SavedFastISel);
293 //===--------------------------------------------------------------------===//
294 /// createDefaultScheduler - This creates an instruction scheduler appropriate
296 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
297 CodeGenOpt::Level OptLevel) {
298 const TargetLowering *TLI = IS->TLI;
299 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
301 // Try first to see if the Target has its own way of selecting a scheduler
302 if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
303 return SchedulerCtor(IS, OptLevel);
306 if (OptLevel == CodeGenOpt::None ||
307 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
308 TLI->getSchedulingPreference() == Sched::Source)
309 return createSourceListDAGScheduler(IS, OptLevel);
310 if (TLI->getSchedulingPreference() == Sched::RegPressure)
311 return createBURRListDAGScheduler(IS, OptLevel);
312 if (TLI->getSchedulingPreference() == Sched::Hybrid)
313 return createHybridListDAGScheduler(IS, OptLevel);
314 if (TLI->getSchedulingPreference() == Sched::VLIW)
315 return createVLIWDAGScheduler(IS, OptLevel);
316 assert(TLI->getSchedulingPreference() == Sched::ILP &&
317 "Unknown sched type!");
318 return createILPListDAGScheduler(IS, OptLevel);
322 // EmitInstrWithCustomInserter - This method should be implemented by targets
323 // that mark instructions with the 'usesCustomInserter' flag. These
324 // instructions are special in various ways, which require special support to
325 // insert. The specified MachineInstr is created but not inserted into any
326 // basic blocks, and this method is called to expand it into a sequence of
327 // instructions, potentially also creating new basic blocks and control flow.
328 // When new basic blocks are inserted and the edges from MBB to its successors
329 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
332 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
333 MachineBasicBlock *MBB) const {
335 dbgs() << "If a target marks an instruction with "
336 "'usesCustomInserter', it must implement "
337 "TargetLowering::EmitInstrWithCustomInserter!";
339 llvm_unreachable(nullptr);
342 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
343 SDNode *Node) const {
344 assert(!MI->hasPostISelHook() &&
345 "If a target marks an instruction with 'hasPostISelHook', "
346 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
349 //===----------------------------------------------------------------------===//
350 // SelectionDAGISel code
351 //===----------------------------------------------------------------------===//
353 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
354 CodeGenOpt::Level OL) :
355 MachineFunctionPass(ID), TM(tm),
356 FuncInfo(new FunctionLoweringInfo()),
357 CurDAG(new SelectionDAG(tm, OL)),
358 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
362 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
363 initializeBranchProbabilityInfoWrapperPassPass(
364 *PassRegistry::getPassRegistry());
365 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
366 initializeTargetLibraryInfoWrapperPassPass(
367 *PassRegistry::getPassRegistry());
370 SelectionDAGISel::~SelectionDAGISel() {
376 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
377 AU.addRequired<AAResultsWrapperPass>();
378 AU.addRequired<GCModuleInfo>();
379 AU.addPreserved<GCModuleInfo>();
380 AU.addRequired<TargetLibraryInfoWrapperPass>();
381 if (UseMBPI && OptLevel != CodeGenOpt::None)
382 AU.addRequired<BranchProbabilityInfoWrapperPass>();
383 MachineFunctionPass::getAnalysisUsage(AU);
386 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
387 /// may trap on it. In this case we have to split the edge so that the path
388 /// through the predecessor block that doesn't go to the phi block doesn't
389 /// execute the possibly trapping instruction.
391 /// This is required for correctness, so it must be done at -O0.
393 static void SplitCriticalSideEffectEdges(Function &Fn) {
394 // Loop for blocks with phi nodes.
395 for (BasicBlock &BB : Fn) {
396 PHINode *PN = dyn_cast<PHINode>(BB.begin());
400 // For each block with a PHI node, check to see if any of the input values
401 // are potentially trapping constant expressions. Constant expressions are
402 // the only potentially trapping value that can occur as the argument to a
404 for (BasicBlock::iterator I = BB.begin(); (PN = dyn_cast<PHINode>(I)); ++I)
405 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
406 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
407 if (!CE || !CE->canTrap()) continue;
409 // The only case we have to worry about is when the edge is critical.
410 // Since this block has a PHI Node, we assume it has multiple input
411 // edges: check to see if the pred has multiple successors.
412 BasicBlock *Pred = PN->getIncomingBlock(i);
413 if (Pred->getTerminator()->getNumSuccessors() == 1)
416 // Okay, we have to split this edge.
418 Pred->getTerminator(), GetSuccessorNumber(Pred, &BB),
419 CriticalEdgeSplittingOptions().setMergeIdenticalEdges());
425 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
426 // Do some sanity-checking on the command-line options.
427 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
428 "-fast-isel-verbose requires -fast-isel");
429 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
430 "-fast-isel-abort > 0 requires -fast-isel");
432 const Function &Fn = *mf.getFunction();
435 // Reset the target options before resetting the optimization
437 // FIXME: This is a horrible hack and should be processed via
438 // codegen looking at the optimization level explicitly when
439 // it wants to look at it.
440 TM.resetTargetOptions(Fn);
441 // Reset OptLevel to None for optnone functions.
442 CodeGenOpt::Level NewOptLevel = OptLevel;
443 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
444 NewOptLevel = CodeGenOpt::None;
445 OptLevelChanger OLC(*this, NewOptLevel);
447 TII = MF->getSubtarget().getInstrInfo();
448 TLI = MF->getSubtarget().getTargetLowering();
449 RegInfo = &MF->getRegInfo();
450 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
451 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
452 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
454 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
456 SplitCriticalSideEffectEdges(const_cast<Function &>(Fn));
459 FuncInfo->set(Fn, *MF, CurDAG);
461 if (UseMBPI && OptLevel != CodeGenOpt::None)
462 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
464 FuncInfo->BPI = nullptr;
466 SDB->init(GFI, *AA, LibInfo);
468 MF->setHasInlineAsm(false);
470 FuncInfo->SplitCSR = false;
471 SmallVector<MachineBasicBlock*, 4> Returns;
473 // We split CSR if the target supports it for the given function
474 // and the function has only return exits.
475 if (TLI->supportSplitCSR(MF)) {
476 FuncInfo->SplitCSR = true;
478 // Collect all the return blocks.
479 for (const BasicBlock &BB : Fn) {
480 if (!succ_empty(&BB))
483 const TerminatorInst *Term = BB.getTerminator();
484 if (isa<UnreachableInst>(Term))
486 if (isa<ReturnInst>(Term)) {
487 Returns.push_back(FuncInfo->MBBMap[&BB]);
491 // Bail out if the exit block is not Return nor Unreachable.
492 FuncInfo->SplitCSR = false;
497 MachineBasicBlock *EntryMBB = &MF->front();
498 if (FuncInfo->SplitCSR)
499 // This performs initialization so lowering for SplitCSR will be correct.
500 TLI->initializeSplitCSR(EntryMBB);
502 SelectAllBasicBlocks(Fn);
504 // If the first basic block in the function has live ins that need to be
505 // copied into vregs, emit the copies into the top of the block before
506 // emitting the code for the block.
507 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
508 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
510 // Insert copies in the entry block and the return blocks.
511 if (FuncInfo->SplitCSR)
512 TLI->insertCopiesSplitCSR(EntryMBB, Returns);
514 DenseMap<unsigned, unsigned> LiveInMap;
515 if (!FuncInfo->ArgDbgValues.empty())
516 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
517 E = RegInfo->livein_end(); LI != E; ++LI)
519 LiveInMap.insert(std::make_pair(LI->first, LI->second));
521 // Insert DBG_VALUE instructions for function arguments to the entry block.
522 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
523 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
524 bool hasFI = MI->getOperand(0).isFI();
526 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
527 if (TargetRegisterInfo::isPhysicalRegister(Reg))
528 EntryMBB->insert(EntryMBB->begin(), MI);
530 MachineInstr *Def = RegInfo->getVRegDef(Reg);
532 MachineBasicBlock::iterator InsertPos = Def;
533 // FIXME: VR def may not be in entry block.
534 Def->getParent()->insert(std::next(InsertPos), MI);
536 DEBUG(dbgs() << "Dropping debug info for dead vreg"
537 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
540 // If Reg is live-in then update debug info to track its copy in a vreg.
541 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
542 if (LDI != LiveInMap.end()) {
543 assert(!hasFI && "There's no handling of frame pointer updating here yet "
545 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
546 MachineBasicBlock::iterator InsertPos = Def;
547 const MDNode *Variable = MI->getDebugVariable();
548 const MDNode *Expr = MI->getDebugExpression();
549 DebugLoc DL = MI->getDebugLoc();
550 bool IsIndirect = MI->isIndirectDebugValue();
551 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
552 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
553 "Expected inlined-at fields to agree");
554 // Def is never a terminator here, so it is ok to increment InsertPos.
555 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
556 IsIndirect, LDI->second, Offset, Variable, Expr);
558 // If this vreg is directly copied into an exported register then
559 // that COPY instructions also need DBG_VALUE, if it is the only
560 // user of LDI->second.
561 MachineInstr *CopyUseMI = nullptr;
562 for (MachineRegisterInfo::use_instr_iterator
563 UI = RegInfo->use_instr_begin(LDI->second),
564 E = RegInfo->use_instr_end(); UI != E; ) {
565 MachineInstr *UseMI = &*(UI++);
566 if (UseMI->isDebugValue()) continue;
567 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
568 CopyUseMI = UseMI; continue;
570 // Otherwise this is another use or second copy use.
571 CopyUseMI = nullptr; break;
574 // Use MI's debug location, which describes where Variable was
575 // declared, rather than whatever is attached to CopyUseMI.
576 MachineInstr *NewMI =
577 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
578 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
579 MachineBasicBlock::iterator Pos = CopyUseMI;
580 EntryMBB->insertAfter(Pos, NewMI);
585 // Determine if there are any calls in this machine function.
586 MachineFrameInfo *MFI = MF->getFrameInfo();
587 for (const auto &MBB : *MF) {
588 if (MFI->hasCalls() && MF->hasInlineAsm())
591 for (const auto &MI : MBB) {
592 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
593 if ((MCID.isCall() && !MCID.isReturn()) ||
594 MI.isStackAligningInlineAsm()) {
595 MFI->setHasCalls(true);
597 if (MI.isInlineAsm()) {
598 MF->setHasInlineAsm(true);
603 // Determine if there is a call to setjmp in the machine function.
604 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
606 // Replace forward-declared registers with the registers containing
607 // the desired value.
608 MachineRegisterInfo &MRI = MF->getRegInfo();
609 for (DenseMap<unsigned, unsigned>::iterator
610 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
612 unsigned From = I->first;
613 unsigned To = I->second;
614 // If To is also scheduled to be replaced, find what its ultimate
617 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
621 // Make sure the new register has a sufficiently constrained register class.
622 if (TargetRegisterInfo::isVirtualRegister(From) &&
623 TargetRegisterInfo::isVirtualRegister(To))
624 MRI.constrainRegClass(To, MRI.getRegClass(From));
628 // Replacing one register with another won't touch the kill flags.
629 // We need to conservatively clear the kill flags as a kill on the old
630 // register might dominate existing uses of the new register.
631 if (!MRI.use_empty(To))
632 MRI.clearKillFlags(From);
633 MRI.replaceRegWith(From, To);
636 if (TLI->hasCopyImplyingStackAdjustment(MF))
637 MFI->setHasCopyImplyingStackAdjustment(true);
639 // Freeze the set of reserved registers now that MachineFrameInfo has been
640 // set up. All the information required by getReservedRegs() should be
642 MRI.freezeReservedRegs(*MF);
644 // Release function-specific state. SDB and CurDAG are already cleared
648 // XXX-update: Right after instruction selection, check through the
649 // intentionally added fake conditional branches and mark them as unremovable.
650 for (auto& MBB : *MF) {
651 // Check whether MBB has two successors which only contains an unconditional
652 // branch to the same destination.
653 if (MBB.succ_size() != 2 ||
654 !MBB.getLastNonDebugInstr()->isUnconditionalBranch()) {
657 auto MBBSuccIter = MBB.succ_begin();
658 auto* Succ1 = *MBBSuccIter;
660 auto* Succ2 = *MBBSuccIter;
662 MachineBasicBlock* Succ1Succ = nullptr;
663 MachineBasicBlock* Succ2Succ = nullptr;
664 if ((Succ1->size() == 1 && Succ1->begin()->isUnconditionalBranch()) ||
665 (Succ1->size() == 0)) {
666 Succ1Succ = *Succ1->succ_begin();
668 if ((Succ2->size() == 1 && Succ2->begin()->isUnconditionalBranch()) ||
669 (Succ2->size() == 0)) {
670 Succ2Succ = *Succ2->succ_begin();
673 bool HasCommonDest = Succ1Succ && Succ1Succ == Succ2Succ;
675 auto MBBIter = MBB.end();
676 std::advance(MBBIter, -2);
677 assert(MBBIter->isConditionalBranch());
678 MBBIter->disableCanEliminateMachineInstr();
679 MBB.disableCanEliminateMachineBB();
680 Succ1->disableCanEliminateMachineBB();
681 Succ2->disableCanEliminateMachineBB();
682 Succ1Succ->disableCanEliminateMachineBB();
683 DEBUG(dbgs() << "Mark as unremovable machine basic block: " << MBB
684 << "\nMark as unremovable branch instruction: " << *MBBIter
689 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
690 DEBUG(MF->print(dbgs()));
695 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
696 BasicBlock::const_iterator End,
698 // Lower the instructions. If a call is emitted as a tail call, cease emitting
699 // nodes for this block.
700 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
703 // Make sure the root of the DAG is up-to-date.
704 CurDAG->setRoot(SDB->getControlRoot());
705 HadTailCall = SDB->HasTailCall;
708 // Final step, emit the lowered DAG as machine code.
712 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
713 SmallPtrSet<SDNode*, 128> VisitedNodes;
714 SmallVector<SDNode*, 128> Worklist;
716 Worklist.push_back(CurDAG->getRoot().getNode());
722 SDNode *N = Worklist.pop_back_val();
724 // If we've already seen this node, ignore it.
725 if (!VisitedNodes.insert(N).second)
728 // Otherwise, add all chain operands to the worklist.
729 for (const SDValue &Op : N->op_values())
730 if (Op.getValueType() == MVT::Other)
731 Worklist.push_back(Op.getNode());
733 // If this is a CopyToReg with a vreg dest, process it.
734 if (N->getOpcode() != ISD::CopyToReg)
737 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
738 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
741 // Ignore non-scalar or non-integer values.
742 SDValue Src = N->getOperand(2);
743 EVT SrcVT = Src.getValueType();
744 if (!SrcVT.isInteger() || SrcVT.isVector())
747 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
748 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
749 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
750 } while (!Worklist.empty());
753 void SelectionDAGISel::CodeGenAndEmitDAG() {
754 std::string GroupName;
755 if (TimePassesIsEnabled)
756 GroupName = "Instruction Selection and Scheduling";
757 std::string BlockName;
758 int BlockNumber = -1;
760 bool MatchFilterBB = false; (void)MatchFilterBB;
762 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
763 FilterDAGBasicBlockName ==
764 FuncInfo->MBB->getBasicBlock()->getName().str());
767 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
768 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
772 BlockNumber = FuncInfo->MBB->getNumber();
774 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
776 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
777 << " '" << BlockName << "'\n"; CurDAG->dump());
779 if (ViewDAGCombine1 && MatchFilterBB)
780 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
782 // Run the DAG combiner in pre-legalize mode.
784 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
785 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
788 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
789 << " '" << BlockName << "'\n"; CurDAG->dump());
791 // Second step, hack on the DAG until it only uses operations and types that
792 // the target supports.
793 if (ViewLegalizeTypesDAGs && MatchFilterBB)
794 CurDAG->viewGraph("legalize-types input for " + BlockName);
798 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
799 Changed = CurDAG->LegalizeTypes();
802 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
803 << " '" << BlockName << "'\n"; CurDAG->dump());
805 CurDAG->NewNodesMustHaveLegalTypes = true;
808 if (ViewDAGCombineLT && MatchFilterBB)
809 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
811 // Run the DAG combiner in post-type-legalize mode.
813 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
814 TimePassesIsEnabled);
815 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
818 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
819 << " '" << BlockName << "'\n"; CurDAG->dump());
824 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
825 Changed = CurDAG->LegalizeVectors();
830 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
831 CurDAG->LegalizeTypes();
834 if (ViewDAGCombineLT && MatchFilterBB)
835 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
837 // Run the DAG combiner in post-type-legalize mode.
839 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
840 TimePassesIsEnabled);
841 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
844 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
845 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
848 if (ViewLegalizeDAGs && MatchFilterBB)
849 CurDAG->viewGraph("legalize input for " + BlockName);
852 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
856 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
857 << " '" << BlockName << "'\n"; CurDAG->dump());
859 if (ViewDAGCombine2 && MatchFilterBB)
860 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
862 // Run the DAG combiner in post-legalize mode.
864 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
865 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
868 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
869 << " '" << BlockName << "'\n"; CurDAG->dump());
871 if (OptLevel != CodeGenOpt::None)
872 ComputeLiveOutVRegInfo();
874 if (ViewISelDAGs && MatchFilterBB)
875 CurDAG->viewGraph("isel input for " + BlockName);
877 // Third, instruction select all of the operations to machine code, adding the
878 // code to the MachineBasicBlock.
880 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
881 DoInstructionSelection();
884 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
885 << " '" << BlockName << "'\n"; CurDAG->dump());
887 if (ViewSchedDAGs && MatchFilterBB)
888 CurDAG->viewGraph("scheduler input for " + BlockName);
890 // Schedule machine code.
891 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
893 NamedRegionTimer T("Instruction Scheduling", GroupName,
894 TimePassesIsEnabled);
895 Scheduler->Run(CurDAG, FuncInfo->MBB);
898 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
900 // Emit machine code to BB. This can change 'BB' to the last block being
902 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
904 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
906 // FuncInfo->InsertPt is passed by reference and set to the end of the
907 // scheduled instructions.
908 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
911 // If the block was split, make sure we update any references that are used to
912 // update PHI nodes later on.
913 if (FirstMBB != LastMBB)
914 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
916 // Free the scheduler state.
918 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
919 TimePassesIsEnabled);
923 // Free the SelectionDAG state, now that we're finished with it.
928 /// ISelUpdater - helper class to handle updates of the instruction selection
930 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
931 SelectionDAG::allnodes_iterator &ISelPosition;
933 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
934 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
936 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
937 /// deleted is the current ISelPosition node, update ISelPosition.
939 void NodeDeleted(SDNode *N, SDNode *E) override {
940 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
944 } // end anonymous namespace
946 void SelectionDAGISel::DoInstructionSelection() {
947 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
948 << FuncInfo->MBB->getNumber()
949 << " '" << FuncInfo->MBB->getName() << "'\n");
953 // Select target instructions for the DAG.
955 // Number all nodes with a topological order and set DAGSize.
956 DAGSize = CurDAG->AssignTopologicalOrder();
958 // Create a dummy node (which is not added to allnodes), that adds
959 // a reference to the root node, preventing it from being deleted,
960 // and tracking any changes of the root.
961 HandleSDNode Dummy(CurDAG->getRoot());
962 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
965 // Make sure that ISelPosition gets properly updated when nodes are deleted
966 // in calls made from this function.
967 ISelUpdater ISU(*CurDAG, ISelPosition);
969 // The AllNodes list is now topological-sorted. Visit the
970 // nodes by starting at the end of the list (the root of the
971 // graph) and preceding back toward the beginning (the entry
973 while (ISelPosition != CurDAG->allnodes_begin()) {
974 SDNode *Node = &*--ISelPosition;
975 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
976 // but there are currently some corner cases that it misses. Also, this
977 // makes it theoretically possible to disable the DAGCombiner.
978 if (Node->use_empty())
981 SDNode *ResNode = Select(Node);
983 // FIXME: This is pretty gross. 'Select' should be changed to not return
984 // anything at all and this code should be nuked with a tactical strike.
986 // If node should not be replaced, continue with the next one.
987 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
991 ReplaceUses(Node, ResNode);
994 // If after the replacement this node is not used any more,
995 // remove this dead node.
996 if (Node->use_empty()) // Don't delete EntryToken, etc.
997 CurDAG->RemoveDeadNode(Node);
1000 CurDAG->setRoot(Dummy.getValue());
1003 DEBUG(dbgs() << "===== Instruction selection ends:\n");
1005 PostprocessISelDAG();
1008 static bool hasExceptionPointerOrCodeUser(const CatchPadInst *CPI) {
1009 for (const User *U : CPI->users()) {
1010 if (const IntrinsicInst *EHPtrCall = dyn_cast<IntrinsicInst>(U)) {
1011 Intrinsic::ID IID = EHPtrCall->getIntrinsicID();
1012 if (IID == Intrinsic::eh_exceptionpointer ||
1013 IID == Intrinsic::eh_exceptioncode)
1020 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
1021 /// do other setup for EH landing-pad blocks.
1022 bool SelectionDAGISel::PrepareEHLandingPad() {
1023 MachineBasicBlock *MBB = FuncInfo->MBB;
1024 const Constant *PersonalityFn = FuncInfo->Fn->getPersonalityFn();
1025 const BasicBlock *LLVMBB = MBB->getBasicBlock();
1026 const TargetRegisterClass *PtrRC =
1027 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));
1029 // Catchpads have one live-in register, which typically holds the exception
1031 if (const auto *CPI = dyn_cast<CatchPadInst>(LLVMBB->getFirstNonPHI())) {
1032 if (hasExceptionPointerOrCodeUser(CPI)) {
1033 // Get or create the virtual register to hold the pointer or code. Mark
1034 // the live in physreg and copy into the vreg.
1035 MCPhysReg EHPhysReg = TLI->getExceptionPointerRegister(PersonalityFn);
1036 assert(EHPhysReg && "target lacks exception pointer register");
1037 MBB->addLiveIn(EHPhysReg);
1038 unsigned VReg = FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
1039 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(),
1040 TII->get(TargetOpcode::COPY), VReg)
1041 .addReg(EHPhysReg, RegState::Kill);
1046 if (!LLVMBB->isLandingPad())
1049 // Add a label to mark the beginning of the landing pad. Deletion of the
1050 // landing pad can thus be detected via the MachineModuleInfo.
1051 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
1053 // Assign the call site to the landing pad's begin label.
1054 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
1056 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
1057 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
1060 // Mark exception register as live in.
1061 if (unsigned Reg = TLI->getExceptionPointerRegister(PersonalityFn))
1062 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
1064 // Mark exception selector register as live in.
1065 if (unsigned Reg = TLI->getExceptionSelectorRegister(PersonalityFn))
1066 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
1071 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
1072 /// side-effect free and is either dead or folded into a generated instruction.
1073 /// Return false if it needs to be emitted.
1074 static bool isFoldedOrDeadInstruction(const Instruction *I,
1075 FunctionLoweringInfo *FuncInfo) {
1076 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
1077 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1078 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1079 !I->isEHPad() && // EH pad instructions aren't folded.
1080 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1084 // Collect per Instruction statistics for fast-isel misses. Only those
1085 // instructions that cause the bail are accounted for. It does not account for
1086 // instructions higher in the block. Thus, summing the per instructions stats
1087 // will not add up to what is reported by NumFastIselFailures.
1088 static void collectFailStats(const Instruction *I) {
1089 switch (I->getOpcode()) {
1090 default: assert (0 && "<Invalid operator> ");
1093 case Instruction::Ret: NumFastIselFailRet++; return;
1094 case Instruction::Br: NumFastIselFailBr++; return;
1095 case Instruction::Switch: NumFastIselFailSwitch++; return;
1096 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1097 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1098 case Instruction::Resume: NumFastIselFailResume++; return;
1099 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1101 // Standard binary operators...
1102 case Instruction::Add: NumFastIselFailAdd++; return;
1103 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1104 case Instruction::Sub: NumFastIselFailSub++; return;
1105 case Instruction::FSub: NumFastIselFailFSub++; return;
1106 case Instruction::Mul: NumFastIselFailMul++; return;
1107 case Instruction::FMul: NumFastIselFailFMul++; return;
1108 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1109 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1110 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1111 case Instruction::URem: NumFastIselFailURem++; return;
1112 case Instruction::SRem: NumFastIselFailSRem++; return;
1113 case Instruction::FRem: NumFastIselFailFRem++; return;
1115 // Logical operators...
1116 case Instruction::And: NumFastIselFailAnd++; return;
1117 case Instruction::Or: NumFastIselFailOr++; return;
1118 case Instruction::Xor: NumFastIselFailXor++; return;
1120 // Memory instructions...
1121 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1122 case Instruction::Load: NumFastIselFailLoad++; return;
1123 case Instruction::Store: NumFastIselFailStore++; return;
1124 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1125 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1126 case Instruction::Fence: NumFastIselFailFence++; return;
1127 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1129 // Convert instructions...
1130 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1131 case Instruction::ZExt: NumFastIselFailZExt++; return;
1132 case Instruction::SExt: NumFastIselFailSExt++; return;
1133 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1134 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1135 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1136 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1137 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1138 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1139 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1140 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1141 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1143 // Other instructions...
1144 case Instruction::ICmp: NumFastIselFailICmp++; return;
1145 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1146 case Instruction::PHI: NumFastIselFailPHI++; return;
1147 case Instruction::Select: NumFastIselFailSelect++; return;
1148 case Instruction::Call: {
1149 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1150 switch (Intrinsic->getIntrinsicID()) {
1152 NumFastIselFailIntrinsicCall++; return;
1153 case Intrinsic::sadd_with_overflow:
1154 NumFastIselFailSAddWithOverflow++; return;
1155 case Intrinsic::uadd_with_overflow:
1156 NumFastIselFailUAddWithOverflow++; return;
1157 case Intrinsic::ssub_with_overflow:
1158 NumFastIselFailSSubWithOverflow++; return;
1159 case Intrinsic::usub_with_overflow:
1160 NumFastIselFailUSubWithOverflow++; return;
1161 case Intrinsic::smul_with_overflow:
1162 NumFastIselFailSMulWithOverflow++; return;
1163 case Intrinsic::umul_with_overflow:
1164 NumFastIselFailUMulWithOverflow++; return;
1165 case Intrinsic::frameaddress:
1166 NumFastIselFailFrameaddress++; return;
1167 case Intrinsic::sqrt:
1168 NumFastIselFailSqrt++; return;
1169 case Intrinsic::experimental_stackmap:
1170 NumFastIselFailStackMap++; return;
1171 case Intrinsic::experimental_patchpoint_void: // fall-through
1172 case Intrinsic::experimental_patchpoint_i64:
1173 NumFastIselFailPatchPoint++; return;
1176 NumFastIselFailCall++;
1179 case Instruction::Shl: NumFastIselFailShl++; return;
1180 case Instruction::LShr: NumFastIselFailLShr++; return;
1181 case Instruction::AShr: NumFastIselFailAShr++; return;
1182 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1183 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1184 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1185 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1186 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1187 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1188 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1193 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1194 // Initialize the Fast-ISel state, if needed.
1195 FastISel *FastIS = nullptr;
1196 if (TM.Options.EnableFastISel)
1197 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1199 // Iterate over all basic blocks in the function.
1200 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1201 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1202 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1203 const BasicBlock *LLVMBB = *I;
1205 if (OptLevel != CodeGenOpt::None) {
1206 bool AllPredsVisited = true;
1207 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1209 if (!FuncInfo->VisitedBBs.count(*PI)) {
1210 AllPredsVisited = false;
1215 if (AllPredsVisited) {
1216 for (BasicBlock::const_iterator I = LLVMBB->begin();
1217 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1218 FuncInfo->ComputePHILiveOutRegInfo(PN);
1220 for (BasicBlock::const_iterator I = LLVMBB->begin();
1221 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1222 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1225 FuncInfo->VisitedBBs.insert(LLVMBB);
1228 BasicBlock::const_iterator const Begin =
1229 LLVMBB->getFirstNonPHI()->getIterator();
1230 BasicBlock::const_iterator const End = LLVMBB->end();
1231 BasicBlock::const_iterator BI = End;
1233 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1235 continue; // Some blocks like catchpads have no code or MBB.
1236 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1238 // Setup an EH landing-pad block.
1239 FuncInfo->ExceptionPointerVirtReg = 0;
1240 FuncInfo->ExceptionSelectorVirtReg = 0;
1241 if (LLVMBB->isEHPad())
1242 if (!PrepareEHLandingPad())
1245 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1247 FastIS->startNewBlock();
1249 // Emit code for any incoming arguments. This must happen before
1250 // beginning FastISel on the entry block.
1251 if (LLVMBB == &Fn.getEntryBlock()) {
1254 // Lower any arguments needed in this block if this is the entry block.
1255 if (!FastIS->lowerArguments()) {
1256 // Fast isel failed to lower these arguments
1257 ++NumFastIselFailLowerArguments;
1258 if (EnableFastISelAbort > 1)
1259 report_fatal_error("FastISel didn't lower all arguments");
1261 // Use SelectionDAG argument lowering
1263 CurDAG->setRoot(SDB->getControlRoot());
1265 CodeGenAndEmitDAG();
1268 // If we inserted any instructions at the beginning, make a note of
1269 // where they are, so we can be sure to emit subsequent instructions
1271 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1272 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1274 FastIS->setLastLocalValue(nullptr);
1277 unsigned NumFastIselRemaining = std::distance(Begin, End);
1278 // Do FastISel on as many instructions as possible.
1279 for (; BI != Begin; --BI) {
1280 const Instruction *Inst = &*std::prev(BI);
1282 // If we no longer require this instruction, skip it.
1283 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1284 --NumFastIselRemaining;
1288 // Bottom-up: reset the insert pos at the top, after any local-value
1290 FastIS->recomputeInsertPt();
1292 // Try to select the instruction with FastISel.
1293 if (FastIS->selectInstruction(Inst)) {
1294 --NumFastIselRemaining;
1295 ++NumFastIselSuccess;
1296 // If fast isel succeeded, skip over all the folded instructions, and
1297 // then see if there is a load right before the selected instructions.
1298 // Try to fold the load if so.
1299 const Instruction *BeforeInst = Inst;
1300 while (BeforeInst != &*Begin) {
1301 BeforeInst = &*std::prev(BasicBlock::const_iterator(BeforeInst));
1302 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1305 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1306 BeforeInst->hasOneUse() &&
1307 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1308 // If we succeeded, don't re-select the load.
1309 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1310 --NumFastIselRemaining;
1311 ++NumFastIselSuccess;
1317 if (EnableFastISelVerbose2)
1318 collectFailStats(Inst);
1321 // Then handle certain instructions as single-LLVM-Instruction blocks.
1322 if (isa<CallInst>(Inst)) {
1324 if (EnableFastISelVerbose || EnableFastISelAbort) {
1325 dbgs() << "FastISel missed call: ";
1328 if (EnableFastISelAbort > 2)
1329 // FastISel selector couldn't handle something and bailed.
1330 // For the purpose of debugging, just abort.
1331 report_fatal_error("FastISel didn't select the entire block");
1333 if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() &&
1334 !Inst->use_empty()) {
1335 unsigned &R = FuncInfo->ValueMap[Inst];
1337 R = FuncInfo->CreateRegs(Inst->getType());
1340 bool HadTailCall = false;
1341 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1342 SelectBasicBlock(Inst->getIterator(), BI, HadTailCall);
1344 // If the call was emitted as a tail call, we're done with the block.
1345 // We also need to delete any previously emitted instructions.
1347 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1352 // Recompute NumFastIselRemaining as Selection DAG instruction
1353 // selection may have handled the call, input args, etc.
1354 unsigned RemainingNow = std::distance(Begin, BI);
1355 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1356 NumFastIselRemaining = RemainingNow;
1360 bool ShouldAbort = EnableFastISelAbort;
1361 if (EnableFastISelVerbose || EnableFastISelAbort) {
1362 if (isa<TerminatorInst>(Inst)) {
1363 // Use a different message for terminator misses.
1364 dbgs() << "FastISel missed terminator: ";
1365 // Don't abort unless for terminator unless the level is really high
1366 ShouldAbort = (EnableFastISelAbort > 2);
1368 dbgs() << "FastISel miss: ";
1373 // FastISel selector couldn't handle something and bailed.
1374 // For the purpose of debugging, just abort.
1375 report_fatal_error("FastISel didn't select the entire block");
1377 NumFastIselFailures += NumFastIselRemaining;
1381 FastIS->recomputeInsertPt();
1383 // Lower any arguments needed in this block if this is the entry block.
1384 if (LLVMBB == &Fn.getEntryBlock()) {
1393 ++NumFastIselBlocks;
1396 // Run SelectionDAG instruction selection on the remainder of the block
1397 // not handled by FastISel. If FastISel is not run, this is the entire
1400 SelectBasicBlock(Begin, BI, HadTailCall);
1404 FuncInfo->PHINodesToUpdate.clear();
1408 SDB->clearDanglingDebugInfo();
1409 SDB->SPDescriptor.resetPerFunctionState();
1412 /// Given that the input MI is before a partial terminator sequence TSeq, return
1413 /// true if M + TSeq also a partial terminator sequence.
1415 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1416 /// lowering copy vregs into physical registers, which are then passed into
1417 /// terminator instructors so we can satisfy ABI constraints. A partial
1418 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1419 /// may be the whole terminator sequence).
1420 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1421 // If we do not have a copy or an implicit def, we return true if and only if
1422 // MI is a debug value.
1423 if (!MI->isCopy() && !MI->isImplicitDef())
1424 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1425 // physical registers if there is debug info associated with the terminator
1426 // of our mbb. We want to include said debug info in our terminator
1427 // sequence, so we return true in that case.
1428 return MI->isDebugValue();
1430 // We have left the terminator sequence if we are not doing one of the
1433 // 1. Copying a vreg into a physical register.
1434 // 2. Copying a vreg into a vreg.
1435 // 3. Defining a register via an implicit def.
1437 // OPI should always be a register definition...
1438 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1439 if (!OPI->isReg() || !OPI->isDef())
1442 // Defining any register via an implicit def is always ok.
1443 if (MI->isImplicitDef())
1446 // Grab the copy source...
1447 MachineInstr::const_mop_iterator OPI2 = OPI;
1449 assert(OPI2 != MI->operands_end()
1450 && "Should have a copy implying we should have 2 arguments.");
1452 // Make sure that the copy dest is not a vreg when the copy source is a
1453 // physical register.
1454 if (!OPI2->isReg() ||
1455 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1456 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1462 /// Find the split point at which to splice the end of BB into its success stack
1463 /// protector check machine basic block.
1465 /// On many platforms, due to ABI constraints, terminators, even before register
1466 /// allocation, use physical registers. This creates an issue for us since
1467 /// physical registers at this point can not travel across basic
1468 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1469 /// when they enter functions and moves them through a sequence of copies back
1470 /// into the physical registers right before the terminator creating a
1471 /// ``Terminator Sequence''. This function is searching for the beginning of the
1472 /// terminator sequence so that we can ensure that we splice off not just the
1473 /// terminator, but additionally the copies that move the vregs into the
1474 /// physical registers.
1475 static MachineBasicBlock::iterator
1476 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1477 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1479 if (SplitPoint == BB->begin())
1482 MachineBasicBlock::iterator Start = BB->begin();
1483 MachineBasicBlock::iterator Previous = SplitPoint;
1486 while (MIIsInTerminatorSequence(Previous)) {
1487 SplitPoint = Previous;
1488 if (Previous == Start)
1497 SelectionDAGISel::FinishBasicBlock() {
1499 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1500 << FuncInfo->PHINodesToUpdate.size() << "\n";
1501 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1502 dbgs() << "Node " << i << " : ("
1503 << FuncInfo->PHINodesToUpdate[i].first
1504 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1506 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1507 // PHI nodes in successors.
1508 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1509 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1510 assert(PHI->isPHI() &&
1511 "This is not a machine PHI node that we are updating!");
1512 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1514 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1517 // Handle stack protector.
1518 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1519 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1520 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1522 // Find the split point to split the parent mbb. At the same time copy all
1523 // physical registers used in the tail of parent mbb into virtual registers
1524 // before the split point and back into physical registers after the split
1525 // point. This prevents us needing to deal with Live-ins and many other
1526 // register allocation issues caused by us splitting the parent mbb. The
1527 // register allocator will clean up said virtual copies later on.
1528 MachineBasicBlock::iterator SplitPoint =
1529 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1531 // Splice the terminator of ParentMBB into SuccessMBB.
1532 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1536 // Add compare/jump on neq/jump to the parent BB.
1537 FuncInfo->MBB = ParentMBB;
1538 FuncInfo->InsertPt = ParentMBB->end();
1539 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1540 CurDAG->setRoot(SDB->getRoot());
1542 CodeGenAndEmitDAG();
1544 // CodeGen Failure MBB if we have not codegened it yet.
1545 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1546 if (!FailureMBB->size()) {
1547 FuncInfo->MBB = FailureMBB;
1548 FuncInfo->InsertPt = FailureMBB->end();
1549 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1550 CurDAG->setRoot(SDB->getRoot());
1552 CodeGenAndEmitDAG();
1555 // Clear the Per-BB State.
1556 SDB->SPDescriptor.resetPerBBState();
1559 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1560 // Lower header first, if it wasn't already lowered
1561 if (!SDB->BitTestCases[i].Emitted) {
1562 // Set the current basic block to the mbb we wish to insert the code into
1563 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1564 FuncInfo->InsertPt = FuncInfo->MBB->end();
1566 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1567 CurDAG->setRoot(SDB->getRoot());
1569 CodeGenAndEmitDAG();
1572 BranchProbability UnhandledProb = SDB->BitTestCases[i].Prob;
1573 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1574 UnhandledProb -= SDB->BitTestCases[i].Cases[j].ExtraProb;
1575 // Set the current basic block to the mbb we wish to insert the code into
1576 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1577 FuncInfo->InsertPt = FuncInfo->MBB->end();
1580 // If all cases cover a contiguous range, it is not necessary to jump to
1581 // the default block after the last bit test fails. This is because the
1582 // range check during bit test header creation has guaranteed that every
1583 // case here doesn't go outside the range.
1584 MachineBasicBlock *NextMBB;
1585 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1586 NextMBB = SDB->BitTestCases[i].Cases[j + 1].TargetBB;
1587 else if (j + 1 != ej)
1588 NextMBB = SDB->BitTestCases[i].Cases[j + 1].ThisBB;
1590 NextMBB = SDB->BitTestCases[i].Default;
1592 SDB->visitBitTestCase(SDB->BitTestCases[i],
1595 SDB->BitTestCases[i].Reg,
1596 SDB->BitTestCases[i].Cases[j],
1599 CurDAG->setRoot(SDB->getRoot());
1601 CodeGenAndEmitDAG();
1603 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1608 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1610 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1611 MachineBasicBlock *PHIBB = PHI->getParent();
1612 assert(PHI->isPHI() &&
1613 "This is not a machine PHI node that we are updating!");
1614 // This is "default" BB. We have two jumps to it. From "header" BB and
1615 // from last "case" BB.
1616 if (PHIBB == SDB->BitTestCases[i].Default)
1617 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1618 .addMBB(SDB->BitTestCases[i].Parent)
1619 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1620 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1621 // One of "cases" BB.
1622 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1624 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1625 if (cBB->isSuccessor(PHIBB))
1626 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1630 SDB->BitTestCases.clear();
1632 // If the JumpTable record is filled in, then we need to emit a jump table.
1633 // Updating the PHI nodes is tricky in this case, since we need to determine
1634 // whether the PHI is a successor of the range check MBB or the jump table MBB
1635 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1636 // Lower header first, if it wasn't already lowered
1637 if (!SDB->JTCases[i].first.Emitted) {
1638 // Set the current basic block to the mbb we wish to insert the code into
1639 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1640 FuncInfo->InsertPt = FuncInfo->MBB->end();
1642 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1644 CurDAG->setRoot(SDB->getRoot());
1646 CodeGenAndEmitDAG();
1649 // Set the current basic block to the mbb we wish to insert the code into
1650 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1651 FuncInfo->InsertPt = FuncInfo->MBB->end();
1653 SDB->visitJumpTable(SDB->JTCases[i].second);
1654 CurDAG->setRoot(SDB->getRoot());
1656 CodeGenAndEmitDAG();
1659 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1661 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1662 MachineBasicBlock *PHIBB = PHI->getParent();
1663 assert(PHI->isPHI() &&
1664 "This is not a machine PHI node that we are updating!");
1665 // "default" BB. We can go there only from header BB.
1666 if (PHIBB == SDB->JTCases[i].second.Default)
1667 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1668 .addMBB(SDB->JTCases[i].first.HeaderBB);
1669 // JT BB. Just iterate over successors here
1670 if (FuncInfo->MBB->isSuccessor(PHIBB))
1671 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1674 SDB->JTCases.clear();
1676 // If we generated any switch lowering information, build and codegen any
1677 // additional DAGs necessary.
1678 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1679 // Set the current basic block to the mbb we wish to insert the code into
1680 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1681 FuncInfo->InsertPt = FuncInfo->MBB->end();
1683 // Determine the unique successors.
1684 SmallVector<MachineBasicBlock *, 2> Succs;
1685 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1686 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1687 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1689 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1690 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1691 CurDAG->setRoot(SDB->getRoot());
1693 CodeGenAndEmitDAG();
1695 // Remember the last block, now that any splitting is done, for use in
1696 // populating PHI nodes in successors.
1697 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1699 // Handle any PHI nodes in successors of this chunk, as if we were coming
1700 // from the original BB before switch expansion. Note that PHI nodes can
1701 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1702 // handle them the right number of times.
1703 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1704 FuncInfo->MBB = Succs[i];
1705 FuncInfo->InsertPt = FuncInfo->MBB->end();
1706 // FuncInfo->MBB may have been removed from the CFG if a branch was
1708 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1709 for (MachineBasicBlock::iterator
1710 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1711 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1712 MachineInstrBuilder PHI(*MF, MBBI);
1713 // This value for this PHI node is recorded in PHINodesToUpdate.
1714 for (unsigned pn = 0; ; ++pn) {
1715 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1716 "Didn't find PHI entry!");
1717 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1718 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1726 SDB->SwitchCases.clear();
1730 /// Create the scheduler. If a specific scheduler was specified
1731 /// via the SchedulerRegistry, use it, otherwise select the
1732 /// one preferred by the target.
1734 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1735 return ISHeuristic(this, OptLevel);
1738 //===----------------------------------------------------------------------===//
1739 // Helper functions used by the generated instruction selector.
1740 //===----------------------------------------------------------------------===//
1741 // Calls to these methods are generated by tblgen.
1743 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1744 /// the dag combiner simplified the 255, we still want to match. RHS is the
1745 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1746 /// specified in the .td file (e.g. 255).
1747 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1748 int64_t DesiredMaskS) const {
1749 const APInt &ActualMask = RHS->getAPIntValue();
1750 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1752 // If the actual mask exactly matches, success!
1753 if (ActualMask == DesiredMask)
1756 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1757 if (ActualMask.intersects(~DesiredMask))
1760 // Otherwise, the DAG Combiner may have proven that the value coming in is
1761 // either already zero or is not demanded. Check for known zero input bits.
1762 APInt NeededMask = DesiredMask & ~ActualMask;
1763 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1766 // TODO: check to see if missing bits are just not demanded.
1768 // Otherwise, this pattern doesn't match.
1772 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1773 /// the dag combiner simplified the 255, we still want to match. RHS is the
1774 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1775 /// specified in the .td file (e.g. 255).
1776 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1777 int64_t DesiredMaskS) const {
1778 const APInt &ActualMask = RHS->getAPIntValue();
1779 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1781 // If the actual mask exactly matches, success!
1782 if (ActualMask == DesiredMask)
1785 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1786 if (ActualMask.intersects(~DesiredMask))
1789 // Otherwise, the DAG Combiner may have proven that the value coming in is
1790 // either already zero or is not demanded. Check for known zero input bits.
1791 APInt NeededMask = DesiredMask & ~ActualMask;
1793 APInt KnownZero, KnownOne;
1794 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1796 // If all the missing bits in the or are already known to be set, match!
1797 if ((NeededMask & KnownOne) == NeededMask)
1800 // TODO: check to see if missing bits are just not demanded.
1802 // Otherwise, this pattern doesn't match.
1806 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1807 /// by tblgen. Others should not call it.
1808 void SelectionDAGISel::
1809 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL) {
1810 std::vector<SDValue> InOps;
1811 std::swap(InOps, Ops);
1813 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1814 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1815 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1816 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1818 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1819 if (InOps[e-1].getValueType() == MVT::Glue)
1820 --e; // Don't process a glue operand if it is here.
1823 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1824 if (!InlineAsm::isMemKind(Flags)) {
1825 // Just skip over this operand, copying the operands verbatim.
1826 Ops.insert(Ops.end(), InOps.begin()+i,
1827 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1828 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1830 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1831 "Memory operand with multiple values?");
1833 unsigned TiedToOperand;
1834 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1835 // We need the constraint ID from the operand this is tied to.
1836 unsigned CurOp = InlineAsm::Op_FirstOperand;
1837 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1838 for (; TiedToOperand; --TiedToOperand) {
1839 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1840 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1844 // Otherwise, this is a memory operand. Ask the target to select it.
1845 std::vector<SDValue> SelOps;
1846 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1847 InlineAsm::getMemoryConstraintID(Flags),
1849 report_fatal_error("Could not match memory address. Inline asm"
1852 // Add this to the output node.
1854 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1855 Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
1856 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1861 // Add the glue input back if present.
1862 if (e != InOps.size())
1863 Ops.push_back(InOps.back());
1866 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1869 static SDNode *findGlueUse(SDNode *N) {
1870 unsigned FlagResNo = N->getNumValues()-1;
1871 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1872 SDUse &Use = I.getUse();
1873 if (Use.getResNo() == FlagResNo)
1874 return Use.getUser();
1879 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1880 /// This function recursively traverses up the operand chain, ignoring
1882 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1883 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1884 bool IgnoreChains) {
1885 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1886 // greater than all of its (recursive) operands. If we scan to a point where
1887 // 'use' is smaller than the node we're scanning for, then we know we will
1890 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1891 // happen because we scan down to newly selected nodes in the case of glue
1893 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1896 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1897 // won't fail if we scan it again.
1898 if (!Visited.insert(Use).second)
1901 for (const SDValue &Op : Use->op_values()) {
1902 // Ignore chain uses, they are validated by HandleMergeInputChains.
1903 if (Op.getValueType() == MVT::Other && IgnoreChains)
1906 SDNode *N = Op.getNode();
1908 if (Use == ImmedUse || Use == Root)
1909 continue; // We are not looking for immediate use.
1914 // Traverse up the operand chain.
1915 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1921 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1922 /// operand node N of U during instruction selection that starts at Root.
1923 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1924 SDNode *Root) const {
1925 if (OptLevel == CodeGenOpt::None) return false;
1926 return N.hasOneUse();
1929 /// IsLegalToFold - Returns true if the specific operand node N of
1930 /// U can be folded during instruction selection that starts at Root.
1931 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1932 CodeGenOpt::Level OptLevel,
1933 bool IgnoreChains) {
1934 if (OptLevel == CodeGenOpt::None) return false;
1936 // If Root use can somehow reach N through a path that that doesn't contain
1937 // U then folding N would create a cycle. e.g. In the following
1938 // diagram, Root can reach N through X. If N is folded into into Root, then
1939 // X is both a predecessor and a successor of U.
1950 // * indicates nodes to be folded together.
1952 // If Root produces glue, then it gets (even more) interesting. Since it
1953 // will be "glued" together with its glue use in the scheduler, we need to
1954 // check if it might reach N.
1973 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1974 // (call it Fold), then X is a predecessor of GU and a successor of
1975 // Fold. But since Fold and GU are glued together, this will create
1976 // a cycle in the scheduling graph.
1978 // If the node has glue, walk down the graph to the "lowest" node in the
1980 EVT VT = Root->getValueType(Root->getNumValues()-1);
1981 while (VT == MVT::Glue) {
1982 SDNode *GU = findGlueUse(Root);
1986 VT = Root->getValueType(Root->getNumValues()-1);
1988 // If our query node has a glue result with a use, we've walked up it. If
1989 // the user (which has already been selected) has a chain or indirectly uses
1990 // the chain, our WalkChainUsers predicate will not consider it. Because of
1991 // this, we cannot ignore chains in this predicate.
1992 IgnoreChains = false;
1996 SmallPtrSet<SDNode*, 16> Visited;
1997 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
2000 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
2003 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
2004 SelectInlineAsmMemoryOperands(Ops, DL);
2006 const EVT VTs[] = {MVT::Other, MVT::Glue};
2007 SDValue New = CurDAG->getNode(ISD::INLINEASM, DL, VTs, Ops);
2009 return New.getNode();
2013 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
2015 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
2016 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
2018 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0),
2020 SDValue New = CurDAG->getCopyFromReg(
2021 Op->getOperand(0), dl, Reg, Op->getValueType(0));
2023 return New.getNode();
2027 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
2029 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
2030 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
2031 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
2032 Op->getOperand(2).getValueType(),
2034 SDValue New = CurDAG->getCopyToReg(
2035 Op->getOperand(0), dl, Reg, Op->getOperand(2));
2037 return New.getNode();
2042 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
2043 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
2046 /// GetVBR - decode a vbr encoding whose top bit is set.
2047 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline uint64_t
2048 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
2049 assert(Val >= 128 && "Not a VBR");
2050 Val &= 127; // Remove first vbr bit.
2055 NextBits = MatcherTable[Idx++];
2056 Val |= (NextBits&127) << Shift;
2058 } while (NextBits & 128);
2064 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
2065 /// interior glue and chain results to use the new glue and chain results.
2066 void SelectionDAGISel::
2067 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
2068 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
2070 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
2071 bool isMorphNodeTo) {
2072 SmallVector<SDNode*, 4> NowDeadNodes;
2074 // Now that all the normal results are replaced, we replace the chain and
2075 // glue results if present.
2076 if (!ChainNodesMatched.empty()) {
2077 assert(InputChain.getNode() &&
2078 "Matched input chains but didn't produce a chain");
2079 // Loop over all of the nodes we matched that produced a chain result.
2080 // Replace all the chain results with the final chain we ended up with.
2081 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2082 SDNode *ChainNode = ChainNodesMatched[i];
2084 // If this node was already deleted, don't look at it.
2085 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2088 // Don't replace the results of the root node if we're doing a
2090 if (ChainNode == NodeToMatch && isMorphNodeTo)
2093 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2094 if (ChainVal.getValueType() == MVT::Glue)
2095 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2096 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2097 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2099 // If the node became dead and we haven't already seen it, delete it.
2100 if (ChainNode->use_empty() &&
2101 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2102 NowDeadNodes.push_back(ChainNode);
2106 // If the result produces glue, update any glue results in the matched
2107 // pattern with the glue result.
2108 if (InputGlue.getNode()) {
2109 // Handle any interior nodes explicitly marked.
2110 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2111 SDNode *FRN = GlueResultNodesMatched[i];
2113 // If this node was already deleted, don't look at it.
2114 if (FRN->getOpcode() == ISD::DELETED_NODE)
2117 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2118 "Doesn't have a glue result");
2119 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2122 // If the node became dead and we haven't already seen it, delete it.
2123 if (FRN->use_empty() &&
2124 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2125 NowDeadNodes.push_back(FRN);
2129 if (!NowDeadNodes.empty())
2130 CurDAG->RemoveDeadNodes(NowDeadNodes);
2132 DEBUG(dbgs() << "ISEL: Match complete!\n");
2138 CR_LeadsToInteriorNode
2141 /// WalkChainUsers - Walk down the users of the specified chained node that is
2142 /// part of the pattern we're matching, looking at all of the users we find.
2143 /// This determines whether something is an interior node, whether we have a
2144 /// non-pattern node in between two pattern nodes (which prevent folding because
2145 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2146 /// between pattern nodes (in which case the TF becomes part of the pattern).
2148 /// The walk we do here is guaranteed to be small because we quickly get down to
2149 /// already selected nodes "below" us.
2151 WalkChainUsers(const SDNode *ChainedNode,
2152 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2153 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2154 ChainResult Result = CR_Simple;
2156 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2157 E = ChainedNode->use_end(); UI != E; ++UI) {
2158 // Make sure the use is of the chain, not some other value we produce.
2159 if (UI.getUse().getValueType() != MVT::Other) continue;
2163 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2166 // If we see an already-selected machine node, then we've gone beyond the
2167 // pattern that we're selecting down into the already selected chunk of the
2169 unsigned UserOpcode = User->getOpcode();
2170 if (User->isMachineOpcode() ||
2171 UserOpcode == ISD::CopyToReg ||
2172 UserOpcode == ISD::CopyFromReg ||
2173 UserOpcode == ISD::INLINEASM ||
2174 UserOpcode == ISD::EH_LABEL ||
2175 UserOpcode == ISD::LIFETIME_START ||
2176 UserOpcode == ISD::LIFETIME_END) {
2177 // If their node ID got reset to -1 then they've already been selected.
2178 // Treat them like a MachineOpcode.
2179 if (User->getNodeId() == -1)
2183 // If we have a TokenFactor, we handle it specially.
2184 if (User->getOpcode() != ISD::TokenFactor) {
2185 // If the node isn't a token factor and isn't part of our pattern, then it
2186 // must be a random chained node in between two nodes we're selecting.
2187 // This happens when we have something like:
2192 // Because we structurally match the load/store as a read/modify/write,
2193 // but the call is chained between them. We cannot fold in this case
2194 // because it would induce a cycle in the graph.
2195 if (!std::count(ChainedNodesInPattern.begin(),
2196 ChainedNodesInPattern.end(), User))
2197 return CR_InducesCycle;
2199 // Otherwise we found a node that is part of our pattern. For example in:
2203 // This would happen when we're scanning down from the load and see the
2204 // store as a user. Record that there is a use of ChainedNode that is
2205 // part of the pattern and keep scanning uses.
2206 Result = CR_LeadsToInteriorNode;
2207 InteriorChainedNodes.push_back(User);
2211 // If we found a TokenFactor, there are two cases to consider: first if the
2212 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2213 // uses of the TF are in our pattern) we just want to ignore it. Second,
2214 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2220 // | \ DAG's like cheese
2223 // [TokenFactor] [Op]
2230 // In this case, the TokenFactor becomes part of our match and we rewrite it
2231 // as a new TokenFactor.
2233 // To distinguish these two cases, do a recursive walk down the uses.
2234 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2236 // If the uses of the TokenFactor are just already-selected nodes, ignore
2237 // it, it is "below" our pattern.
2239 case CR_InducesCycle:
2240 // If the uses of the TokenFactor lead to nodes that are not part of our
2241 // pattern that are not selected, folding would turn this into a cycle,
2243 return CR_InducesCycle;
2244 case CR_LeadsToInteriorNode:
2245 break; // Otherwise, keep processing.
2248 // Okay, we know we're in the interesting interior case. The TokenFactor
2249 // is now going to be considered part of the pattern so that we rewrite its
2250 // uses (it may have uses that are not part of the pattern) with the
2251 // ultimate chain result of the generated code. We will also add its chain
2252 // inputs as inputs to the ultimate TokenFactor we create.
2253 Result = CR_LeadsToInteriorNode;
2254 ChainedNodesInPattern.push_back(User);
2255 InteriorChainedNodes.push_back(User);
2262 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2263 /// operation for when the pattern matched at least one node with a chains. The
2264 /// input vector contains a list of all of the chained nodes that we match. We
2265 /// must determine if this is a valid thing to cover (i.e. matching it won't
2266 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2267 /// be used as the input node chain for the generated nodes.
2269 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2270 SelectionDAG *CurDAG) {
2271 // Walk all of the chained nodes we've matched, recursively scanning down the
2272 // users of the chain result. This adds any TokenFactor nodes that are caught
2273 // in between chained nodes to the chained and interior nodes list.
2274 SmallVector<SDNode*, 3> InteriorChainedNodes;
2275 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2276 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2277 InteriorChainedNodes) == CR_InducesCycle)
2278 return SDValue(); // Would induce a cycle.
2281 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2282 // that we are interested in. Form our input TokenFactor node.
2283 SmallVector<SDValue, 3> InputChains;
2284 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2285 // Add the input chain of this node to the InputChains list (which will be
2286 // the operands of the generated TokenFactor) if it's not an interior node.
2287 SDNode *N = ChainNodesMatched[i];
2288 if (N->getOpcode() != ISD::TokenFactor) {
2289 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2292 // Otherwise, add the input chain.
2293 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2294 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2295 InputChains.push_back(InChain);
2299 // If we have a token factor, we want to add all inputs of the token factor
2300 // that are not part of the pattern we're matching.
2301 for (const SDValue &Op : N->op_values()) {
2302 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2304 InputChains.push_back(Op);
2308 if (InputChains.size() == 1)
2309 return InputChains[0];
2310 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2311 MVT::Other, InputChains);
2314 /// MorphNode - Handle morphing a node in place for the selector.
2315 SDNode *SelectionDAGISel::
2316 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2317 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2318 // It is possible we're using MorphNodeTo to replace a node with no
2319 // normal results with one that has a normal result (or we could be
2320 // adding a chain) and the input could have glue and chains as well.
2321 // In this case we need to shift the operands down.
2322 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2323 // than the old isel though.
2324 int OldGlueResultNo = -1, OldChainResultNo = -1;
2326 unsigned NTMNumResults = Node->getNumValues();
2327 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2328 OldGlueResultNo = NTMNumResults-1;
2329 if (NTMNumResults != 1 &&
2330 Node->getValueType(NTMNumResults-2) == MVT::Other)
2331 OldChainResultNo = NTMNumResults-2;
2332 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2333 OldChainResultNo = NTMNumResults-1;
2335 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2336 // that this deletes operands of the old node that become dead.
2337 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2339 // MorphNodeTo can operate in two ways: if an existing node with the
2340 // specified operands exists, it can just return it. Otherwise, it
2341 // updates the node in place to have the requested operands.
2343 // If we updated the node in place, reset the node ID. To the isel,
2344 // this should be just like a newly allocated machine node.
2348 unsigned ResNumResults = Res->getNumValues();
2349 // Move the glue if needed.
2350 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2351 (unsigned)OldGlueResultNo != ResNumResults-1)
2352 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2353 SDValue(Res, ResNumResults-1));
2355 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2358 // Move the chain reference if needed.
2359 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2360 (unsigned)OldChainResultNo != ResNumResults-1)
2361 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2362 SDValue(Res, ResNumResults-1));
2364 // Otherwise, no replacement happened because the node already exists. Replace
2365 // Uses of the old node with the new one.
2367 CurDAG->ReplaceAllUsesWith(Node, Res);
2372 /// CheckSame - Implements OP_CheckSame.
2373 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2374 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2376 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2377 // Accept if it is exactly the same as a previously recorded node.
2378 unsigned RecNo = MatcherTable[MatcherIndex++];
2379 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2380 return N == RecordedNodes[RecNo].first;
2383 /// CheckChildSame - Implements OP_CheckChildXSame.
2384 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2385 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2387 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2389 if (ChildNo >= N.getNumOperands())
2390 return false; // Match fails if out of range child #.
2391 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2395 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2396 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2397 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2398 const SelectionDAGISel &SDISel) {
2399 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2402 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2403 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2404 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2405 const SelectionDAGISel &SDISel, SDNode *N) {
2406 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2409 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2410 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2412 uint16_t Opc = MatcherTable[MatcherIndex++];
2413 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2414 return N->getOpcode() == Opc;
2417 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2418 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
2419 const TargetLowering *TLI, const DataLayout &DL) {
2420 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2421 if (N.getValueType() == VT) return true;
2423 // Handle the case when VT is iPTR.
2424 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(DL);
2427 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2428 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2429 SDValue N, const TargetLowering *TLI, const DataLayout &DL,
2431 if (ChildNo >= N.getNumOperands())
2432 return false; // Match fails if out of range child #.
2433 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI,
2437 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2438 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2440 return cast<CondCodeSDNode>(N)->get() ==
2441 (ISD::CondCode)MatcherTable[MatcherIndex++];
2444 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2445 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2446 SDValue N, const TargetLowering *TLI, const DataLayout &DL) {
2447 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2448 if (cast<VTSDNode>(N)->getVT() == VT)
2451 // Handle the case when VT is iPTR.
2452 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL);
2455 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2456 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2458 int64_t Val = MatcherTable[MatcherIndex++];
2460 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2462 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2463 return C && C->getSExtValue() == Val;
2466 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2467 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2468 SDValue N, unsigned ChildNo) {
2469 if (ChildNo >= N.getNumOperands())
2470 return false; // Match fails if out of range child #.
2471 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2474 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2475 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2476 SDValue N, const SelectionDAGISel &SDISel) {
2477 int64_t Val = MatcherTable[MatcherIndex++];
2479 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2481 if (N->getOpcode() != ISD::AND) return false;
2483 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2484 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2487 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2488 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2489 SDValue N, const SelectionDAGISel &SDISel) {
2490 int64_t Val = MatcherTable[MatcherIndex++];
2492 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2494 if (N->getOpcode() != ISD::OR) return false;
2496 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2497 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2500 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2501 /// scope, evaluate the current node. If the current predicate is known to
2502 /// fail, set Result=true and return anything. If the current predicate is
2503 /// known to pass, set Result=false and return the MatcherIndex to continue
2504 /// with. If the current predicate is unknown, set Result=false and return the
2505 /// MatcherIndex to continue with.
2506 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2507 unsigned Index, SDValue N,
2509 const SelectionDAGISel &SDISel,
2510 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2511 switch (Table[Index++]) {
2514 return Index-1; // Could not evaluate this predicate.
2515 case SelectionDAGISel::OPC_CheckSame:
2516 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2518 case SelectionDAGISel::OPC_CheckChild0Same:
2519 case SelectionDAGISel::OPC_CheckChild1Same:
2520 case SelectionDAGISel::OPC_CheckChild2Same:
2521 case SelectionDAGISel::OPC_CheckChild3Same:
2522 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2523 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2525 case SelectionDAGISel::OPC_CheckPatternPredicate:
2526 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2528 case SelectionDAGISel::OPC_CheckPredicate:
2529 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2531 case SelectionDAGISel::OPC_CheckOpcode:
2532 Result = !::CheckOpcode(Table, Index, N.getNode());
2534 case SelectionDAGISel::OPC_CheckType:
2535 Result = !::CheckType(Table, Index, N, SDISel.TLI,
2536 SDISel.CurDAG->getDataLayout());
2538 case SelectionDAGISel::OPC_CheckChild0Type:
2539 case SelectionDAGISel::OPC_CheckChild1Type:
2540 case SelectionDAGISel::OPC_CheckChild2Type:
2541 case SelectionDAGISel::OPC_CheckChild3Type:
2542 case SelectionDAGISel::OPC_CheckChild4Type:
2543 case SelectionDAGISel::OPC_CheckChild5Type:
2544 case SelectionDAGISel::OPC_CheckChild6Type:
2545 case SelectionDAGISel::OPC_CheckChild7Type:
2546 Result = !::CheckChildType(
2547 Table, Index, N, SDISel.TLI, SDISel.CurDAG->getDataLayout(),
2548 Table[Index - 1] - SelectionDAGISel::OPC_CheckChild0Type);
2550 case SelectionDAGISel::OPC_CheckCondCode:
2551 Result = !::CheckCondCode(Table, Index, N);
2553 case SelectionDAGISel::OPC_CheckValueType:
2554 Result = !::CheckValueType(Table, Index, N, SDISel.TLI,
2555 SDISel.CurDAG->getDataLayout());
2557 case SelectionDAGISel::OPC_CheckInteger:
2558 Result = !::CheckInteger(Table, Index, N);
2560 case SelectionDAGISel::OPC_CheckChild0Integer:
2561 case SelectionDAGISel::OPC_CheckChild1Integer:
2562 case SelectionDAGISel::OPC_CheckChild2Integer:
2563 case SelectionDAGISel::OPC_CheckChild3Integer:
2564 case SelectionDAGISel::OPC_CheckChild4Integer:
2565 Result = !::CheckChildInteger(Table, Index, N,
2566 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2568 case SelectionDAGISel::OPC_CheckAndImm:
2569 Result = !::CheckAndImm(Table, Index, N, SDISel);
2571 case SelectionDAGISel::OPC_CheckOrImm:
2572 Result = !::CheckOrImm(Table, Index, N, SDISel);
2580 /// FailIndex - If this match fails, this is the index to continue with.
2583 /// NodeStack - The node stack when the scope was formed.
2584 SmallVector<SDValue, 4> NodeStack;
2586 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2587 unsigned NumRecordedNodes;
2589 /// NumMatchedMemRefs - The number of matched memref entries.
2590 unsigned NumMatchedMemRefs;
2592 /// InputChain/InputGlue - The current chain/glue
2593 SDValue InputChain, InputGlue;
2595 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2596 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2599 /// \\brief A DAG update listener to keep the matching state
2600 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2601 /// change the DAG while matching. X86 addressing mode matcher is an example
2603 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2605 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2606 SmallVectorImpl<MatchScope> &MatchScopes;
2608 MatchStateUpdater(SelectionDAG &DAG,
2609 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2610 SmallVectorImpl<MatchScope> &MS) :
2611 SelectionDAG::DAGUpdateListener(DAG),
2612 RecordedNodes(RN), MatchScopes(MS) { }
2614 void NodeDeleted(SDNode *N, SDNode *E) override {
2615 // Some early-returns here to avoid the search if we deleted the node or
2616 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2617 // do, so it's unnecessary to update matching state at that point).
2618 // Neither of these can occur currently because we only install this
2619 // update listener during matching a complex patterns.
2620 if (!E || E->isMachineOpcode())
2622 // Performing linear search here does not matter because we almost never
2623 // run this code. You'd have to have a CSE during complex pattern
2625 for (auto &I : RecordedNodes)
2626 if (I.first.getNode() == N)
2629 for (auto &I : MatchScopes)
2630 for (auto &J : I.NodeStack)
2631 if (J.getNode() == N)
2637 SDNode *SelectionDAGISel::
2638 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2639 unsigned TableSize) {
2640 // FIXME: Should these even be selected? Handle these cases in the caller?
2641 switch (NodeToMatch->getOpcode()) {
2644 case ISD::EntryToken: // These nodes remain the same.
2645 case ISD::BasicBlock:
2647 case ISD::RegisterMask:
2648 case ISD::HANDLENODE:
2649 case ISD::MDNODE_SDNODE:
2650 case ISD::TargetConstant:
2651 case ISD::TargetConstantFP:
2652 case ISD::TargetConstantPool:
2653 case ISD::TargetFrameIndex:
2654 case ISD::TargetExternalSymbol:
2656 case ISD::TargetBlockAddress:
2657 case ISD::TargetJumpTable:
2658 case ISD::TargetGlobalTLSAddress:
2659 case ISD::TargetGlobalAddress:
2660 case ISD::TokenFactor:
2661 case ISD::CopyFromReg:
2662 case ISD::CopyToReg:
2664 case ISD::LIFETIME_START:
2665 case ISD::LIFETIME_END:
2666 NodeToMatch->setNodeId(-1); // Mark selected.
2668 case ISD::AssertSext:
2669 case ISD::AssertZext:
2670 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2671 NodeToMatch->getOperand(0));
2673 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2674 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2675 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2676 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2679 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2681 // Set up the node stack with NodeToMatch as the only node on the stack.
2682 SmallVector<SDValue, 8> NodeStack;
2683 SDValue N = SDValue(NodeToMatch, 0);
2684 NodeStack.push_back(N);
2686 // MatchScopes - Scopes used when matching, if a match failure happens, this
2687 // indicates where to continue checking.
2688 SmallVector<MatchScope, 8> MatchScopes;
2690 // RecordedNodes - This is the set of nodes that have been recorded by the
2691 // state machine. The second value is the parent of the node, or null if the
2692 // root is recorded.
2693 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2695 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2697 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2699 // These are the current input chain and glue for use when generating nodes.
2700 // Various Emit operations change these. For example, emitting a copytoreg
2701 // uses and updates these.
2702 SDValue InputChain, InputGlue;
2704 // ChainNodesMatched - If a pattern matches nodes that have input/output
2705 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2706 // which ones they are. The result is captured into this list so that we can
2707 // update the chain results when the pattern is complete.
2708 SmallVector<SDNode*, 3> ChainNodesMatched;
2709 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2711 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2712 NodeToMatch->dump(CurDAG);
2715 // Determine where to start the interpreter. Normally we start at opcode #0,
2716 // but if the state machine starts with an OPC_SwitchOpcode, then we
2717 // accelerate the first lookup (which is guaranteed to be hot) with the
2718 // OpcodeOffset table.
2719 unsigned MatcherIndex = 0;
2721 if (!OpcodeOffset.empty()) {
2722 // Already computed the OpcodeOffset table, just index into it.
2723 if (N.getOpcode() < OpcodeOffset.size())
2724 MatcherIndex = OpcodeOffset[N.getOpcode()];
2725 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2727 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2728 // Otherwise, the table isn't computed, but the state machine does start
2729 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2730 // is the first time we're selecting an instruction.
2733 // Get the size of this case.
2734 unsigned CaseSize = MatcherTable[Idx++];
2736 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2737 if (CaseSize == 0) break;
2739 // Get the opcode, add the index to the table.
2740 uint16_t Opc = MatcherTable[Idx++];
2741 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2742 if (Opc >= OpcodeOffset.size())
2743 OpcodeOffset.resize((Opc+1)*2);
2744 OpcodeOffset[Opc] = Idx;
2748 // Okay, do the lookup for the first opcode.
2749 if (N.getOpcode() < OpcodeOffset.size())
2750 MatcherIndex = OpcodeOffset[N.getOpcode()];
2754 assert(MatcherIndex < TableSize && "Invalid index");
2756 unsigned CurrentOpcodeIndex = MatcherIndex;
2758 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2761 // Okay, the semantics of this operation are that we should push a scope
2762 // then evaluate the first child. However, pushing a scope only to have
2763 // the first check fail (which then pops it) is inefficient. If we can
2764 // determine immediately that the first check (or first several) will
2765 // immediately fail, don't even bother pushing a scope for them.
2769 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2770 if (NumToSkip & 128)
2771 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2772 // Found the end of the scope with no match.
2773 if (NumToSkip == 0) {
2778 FailIndex = MatcherIndex+NumToSkip;
2780 unsigned MatcherIndexOfPredicate = MatcherIndex;
2781 (void)MatcherIndexOfPredicate; // silence warning.
2783 // If we can't evaluate this predicate without pushing a scope (e.g. if
2784 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2785 // push the scope and evaluate the full predicate chain.
2787 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2788 Result, *this, RecordedNodes);
2792 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2793 << "index " << MatcherIndexOfPredicate
2794 << ", continuing at " << FailIndex << "\n");
2795 ++NumDAGIselRetries;
2797 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2798 // move to the next case.
2799 MatcherIndex = FailIndex;
2802 // If the whole scope failed to match, bail.
2803 if (FailIndex == 0) break;
2805 // Push a MatchScope which indicates where to go if the first child fails
2807 MatchScope NewEntry;
2808 NewEntry.FailIndex = FailIndex;
2809 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2810 NewEntry.NumRecordedNodes = RecordedNodes.size();
2811 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2812 NewEntry.InputChain = InputChain;
2813 NewEntry.InputGlue = InputGlue;
2814 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2815 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2816 MatchScopes.push_back(NewEntry);
2819 case OPC_RecordNode: {
2820 // Remember this node, it may end up being an operand in the pattern.
2821 SDNode *Parent = nullptr;
2822 if (NodeStack.size() > 1)
2823 Parent = NodeStack[NodeStack.size()-2].getNode();
2824 RecordedNodes.push_back(std::make_pair(N, Parent));
2828 case OPC_RecordChild0: case OPC_RecordChild1:
2829 case OPC_RecordChild2: case OPC_RecordChild3:
2830 case OPC_RecordChild4: case OPC_RecordChild5:
2831 case OPC_RecordChild6: case OPC_RecordChild7: {
2832 unsigned ChildNo = Opcode-OPC_RecordChild0;
2833 if (ChildNo >= N.getNumOperands())
2834 break; // Match fails if out of range child #.
2836 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2840 case OPC_RecordMemRef:
2841 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2844 case OPC_CaptureGlueInput:
2845 // If the current node has an input glue, capture it in InputGlue.
2846 if (N->getNumOperands() != 0 &&
2847 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2848 InputGlue = N->getOperand(N->getNumOperands()-1);
2851 case OPC_MoveChild: {
2852 unsigned ChildNo = MatcherTable[MatcherIndex++];
2853 if (ChildNo >= N.getNumOperands())
2854 break; // Match fails if out of range child #.
2855 N = N.getOperand(ChildNo);
2856 NodeStack.push_back(N);
2860 case OPC_MoveParent:
2861 // Pop the current node off the NodeStack.
2862 NodeStack.pop_back();
2863 assert(!NodeStack.empty() && "Node stack imbalance!");
2864 N = NodeStack.back();
2868 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2871 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2872 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2873 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2874 Opcode-OPC_CheckChild0Same))
2878 case OPC_CheckPatternPredicate:
2879 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2881 case OPC_CheckPredicate:
2882 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2886 case OPC_CheckComplexPat: {
2887 unsigned CPNum = MatcherTable[MatcherIndex++];
2888 unsigned RecNo = MatcherTable[MatcherIndex++];
2889 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2891 // If target can modify DAG during matching, keep the matching state
2893 std::unique_ptr<MatchStateUpdater> MSU;
2894 if (ComplexPatternFuncMutatesDAG())
2895 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2898 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2899 RecordedNodes[RecNo].first, CPNum,
2904 case OPC_CheckOpcode:
2905 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2909 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI,
2910 CurDAG->getDataLayout()))
2914 case OPC_SwitchOpcode: {
2915 unsigned CurNodeOpcode = N.getOpcode();
2916 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2919 // Get the size of this case.
2920 CaseSize = MatcherTable[MatcherIndex++];
2922 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2923 if (CaseSize == 0) break;
2925 uint16_t Opc = MatcherTable[MatcherIndex++];
2926 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2928 // If the opcode matches, then we will execute this case.
2929 if (CurNodeOpcode == Opc)
2932 // Otherwise, skip over this case.
2933 MatcherIndex += CaseSize;
2936 // If no cases matched, bail out.
2937 if (CaseSize == 0) break;
2939 // Otherwise, execute the case we found.
2940 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2941 << " to " << MatcherIndex << "\n");
2945 case OPC_SwitchType: {
2946 MVT CurNodeVT = N.getSimpleValueType();
2947 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2950 // Get the size of this case.
2951 CaseSize = MatcherTable[MatcherIndex++];
2953 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2954 if (CaseSize == 0) break;
2956 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2957 if (CaseVT == MVT::iPTR)
2958 CaseVT = TLI->getPointerTy(CurDAG->getDataLayout());
2960 // If the VT matches, then we will execute this case.
2961 if (CurNodeVT == CaseVT)
2964 // Otherwise, skip over this case.
2965 MatcherIndex += CaseSize;
2968 // If no cases matched, bail out.
2969 if (CaseSize == 0) break;
2971 // Otherwise, execute the case we found.
2972 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2973 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2976 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2977 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2978 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2979 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2980 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2981 CurDAG->getDataLayout(),
2982 Opcode - OPC_CheckChild0Type))
2985 case OPC_CheckCondCode:
2986 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2988 case OPC_CheckValueType:
2989 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI,
2990 CurDAG->getDataLayout()))
2993 case OPC_CheckInteger:
2994 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2996 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2997 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2998 case OPC_CheckChild4Integer:
2999 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
3000 Opcode-OPC_CheckChild0Integer)) break;
3002 case OPC_CheckAndImm:
3003 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
3005 case OPC_CheckOrImm:
3006 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
3009 case OPC_CheckFoldableChainNode: {
3010 assert(NodeStack.size() != 1 && "No parent node");
3011 // Verify that all intermediate nodes between the root and this one have
3013 bool HasMultipleUses = false;
3014 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
3015 if (!NodeStack[i].hasOneUse()) {
3016 HasMultipleUses = true;
3019 if (HasMultipleUses) break;
3021 // Check to see that the target thinks this is profitable to fold and that
3022 // we can fold it without inducing cycles in the graph.
3023 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
3025 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
3026 NodeToMatch, OptLevel,
3027 true/*We validate our own chains*/))
3032 case OPC_EmitInteger: {
3033 MVT::SimpleValueType VT =
3034 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3035 int64_t Val = MatcherTable[MatcherIndex++];
3037 Val = GetVBR(Val, MatcherTable, MatcherIndex);
3038 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3039 CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch),
3043 case OPC_EmitRegister: {
3044 MVT::SimpleValueType VT =
3045 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3046 unsigned RegNo = MatcherTable[MatcherIndex++];
3047 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3048 CurDAG->getRegister(RegNo, VT), nullptr));
3051 case OPC_EmitRegister2: {
3052 // For targets w/ more than 256 register names, the register enum
3053 // values are stored in two bytes in the matcher table (just like
3055 MVT::SimpleValueType VT =
3056 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3057 unsigned RegNo = MatcherTable[MatcherIndex++];
3058 RegNo |= MatcherTable[MatcherIndex++] << 8;
3059 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3060 CurDAG->getRegister(RegNo, VT), nullptr));
3064 case OPC_EmitConvertToTarget: {
3065 // Convert from IMM/FPIMM to target version.
3066 unsigned RecNo = MatcherTable[MatcherIndex++];
3067 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
3068 SDValue Imm = RecordedNodes[RecNo].first;
3070 if (Imm->getOpcode() == ISD::Constant) {
3071 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
3072 Imm = CurDAG->getConstant(*Val, SDLoc(NodeToMatch), Imm.getValueType(),
3074 } else if (Imm->getOpcode() == ISD::ConstantFP) {
3075 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
3076 Imm = CurDAG->getConstantFP(*Val, SDLoc(NodeToMatch),
3077 Imm.getValueType(), true);
3080 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3084 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
3085 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
3086 // These are space-optimized forms of OPC_EmitMergeInputChains.
3087 assert(!InputChain.getNode() &&
3088 "EmitMergeInputChains should be the first chain producing node");
3089 assert(ChainNodesMatched.empty() &&
3090 "Should only have one EmitMergeInputChains per match");
3092 // Read all of the chained nodes.
3093 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3094 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3095 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3097 // FIXME: What if other value results of the node have uses not matched
3099 if (ChainNodesMatched.back() != NodeToMatch &&
3100 !RecordedNodes[RecNo].first.hasOneUse()) {
3101 ChainNodesMatched.clear();
3105 // Merge the input chains if they are not intra-pattern references.
3106 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3108 if (!InputChain.getNode())
3109 break; // Failed to merge.
3113 case OPC_EmitMergeInputChains: {
3114 assert(!InputChain.getNode() &&
3115 "EmitMergeInputChains should be the first chain producing node");
3116 // This node gets a list of nodes we matched in the input that have
3117 // chains. We want to token factor all of the input chains to these nodes
3118 // together. However, if any of the input chains is actually one of the
3119 // nodes matched in this pattern, then we have an intra-match reference.
3120 // Ignore these because the newly token factored chain should not refer to
3122 unsigned NumChains = MatcherTable[MatcherIndex++];
3123 assert(NumChains != 0 && "Can't TF zero chains");
3125 assert(ChainNodesMatched.empty() &&
3126 "Should only have one EmitMergeInputChains per match");
3128 // Read all of the chained nodes.
3129 for (unsigned i = 0; i != NumChains; ++i) {
3130 unsigned RecNo = MatcherTable[MatcherIndex++];
3131 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3132 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3134 // FIXME: What if other value results of the node have uses not matched
3136 if (ChainNodesMatched.back() != NodeToMatch &&
3137 !RecordedNodes[RecNo].first.hasOneUse()) {
3138 ChainNodesMatched.clear();
3143 // If the inner loop broke out, the match fails.
3144 if (ChainNodesMatched.empty())
3147 // Merge the input chains if they are not intra-pattern references.
3148 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3150 if (!InputChain.getNode())
3151 break; // Failed to merge.
3156 case OPC_EmitCopyToReg: {
3157 unsigned RecNo = MatcherTable[MatcherIndex++];
3158 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3159 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3161 if (!InputChain.getNode())
3162 InputChain = CurDAG->getEntryNode();
3164 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3165 DestPhysReg, RecordedNodes[RecNo].first,
3168 InputGlue = InputChain.getValue(1);
3172 case OPC_EmitNodeXForm: {
3173 unsigned XFormNo = MatcherTable[MatcherIndex++];
3174 unsigned RecNo = MatcherTable[MatcherIndex++];
3175 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3176 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3177 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3182 case OPC_MorphNodeTo: {
3183 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3184 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3185 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3186 // Get the result VT list.
3187 unsigned NumVTs = MatcherTable[MatcherIndex++];
3188 SmallVector<EVT, 4> VTs;
3189 for (unsigned i = 0; i != NumVTs; ++i) {
3190 MVT::SimpleValueType VT =
3191 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3192 if (VT == MVT::iPTR)
3193 VT = TLI->getPointerTy(CurDAG->getDataLayout()).SimpleTy;
3197 if (EmitNodeInfo & OPFL_Chain)
3198 VTs.push_back(MVT::Other);
3199 if (EmitNodeInfo & OPFL_GlueOutput)
3200 VTs.push_back(MVT::Glue);
3202 // This is hot code, so optimize the two most common cases of 1 and 2
3205 if (VTs.size() == 1)
3206 VTList = CurDAG->getVTList(VTs[0]);
3207 else if (VTs.size() == 2)
3208 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3210 VTList = CurDAG->getVTList(VTs);
3212 // Get the operand list.
3213 unsigned NumOps = MatcherTable[MatcherIndex++];
3214 SmallVector<SDValue, 8> Ops;
3215 for (unsigned i = 0; i != NumOps; ++i) {
3216 unsigned RecNo = MatcherTable[MatcherIndex++];
3218 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3220 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3221 Ops.push_back(RecordedNodes[RecNo].first);
3224 // If there are variadic operands to add, handle them now.
3225 if (EmitNodeInfo & OPFL_VariadicInfo) {
3226 // Determine the start index to copy from.
3227 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3228 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3229 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3230 "Invalid variadic node");
3231 // Copy all of the variadic operands, not including a potential glue
3233 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3235 SDValue V = NodeToMatch->getOperand(i);
3236 if (V.getValueType() == MVT::Glue) break;
3241 // If this has chain/glue inputs, add them.
3242 if (EmitNodeInfo & OPFL_Chain)
3243 Ops.push_back(InputChain);
3244 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3245 Ops.push_back(InputGlue);
3248 SDNode *Res = nullptr;
3249 if (Opcode != OPC_MorphNodeTo) {
3250 // If this is a normal EmitNode command, just create the new node and
3251 // add the results to the RecordedNodes list.
3252 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3255 // Add all the non-glue/non-chain results to the RecordedNodes list.
3256 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3257 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3258 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3262 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3263 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3265 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3266 // We will visit the equivalent node later.
3267 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3271 // If the node had chain/glue results, update our notion of the current
3273 if (EmitNodeInfo & OPFL_GlueOutput) {
3274 InputGlue = SDValue(Res, VTs.size()-1);
3275 if (EmitNodeInfo & OPFL_Chain)
3276 InputChain = SDValue(Res, VTs.size()-2);
3277 } else if (EmitNodeInfo & OPFL_Chain)
3278 InputChain = SDValue(Res, VTs.size()-1);
3280 // If the OPFL_MemRefs glue is set on this node, slap all of the
3281 // accumulated memrefs onto it.
3283 // FIXME: This is vastly incorrect for patterns with multiple outputs
3284 // instructions that access memory and for ComplexPatterns that match
3286 if (EmitNodeInfo & OPFL_MemRefs) {
3287 // Only attach load or store memory operands if the generated
3288 // instruction may load or store.
3289 const MCInstrDesc &MCID = TII->get(TargetOpc);
3290 bool mayLoad = MCID.mayLoad();
3291 bool mayStore = MCID.mayStore();
3293 unsigned NumMemRefs = 0;
3294 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3295 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3296 if ((*I)->isLoad()) {
3299 } else if ((*I)->isStore()) {
3307 MachineSDNode::mmo_iterator MemRefs =
3308 MF->allocateMemRefsArray(NumMemRefs);
3310 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3311 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3312 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3313 if ((*I)->isLoad()) {
3316 } else if ((*I)->isStore()) {
3324 cast<MachineSDNode>(Res)
3325 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3329 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3330 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3332 // If this was a MorphNodeTo then we're completely done!
3333 if (Opcode == OPC_MorphNodeTo) {
3334 // Update chain and glue uses.
3335 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3336 InputGlue, GlueResultNodesMatched, true);
3343 case OPC_MarkGlueResults: {
3344 unsigned NumNodes = MatcherTable[MatcherIndex++];
3346 // Read and remember all the glue-result nodes.
3347 for (unsigned i = 0; i != NumNodes; ++i) {
3348 unsigned RecNo = MatcherTable[MatcherIndex++];
3350 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3352 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3353 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3358 case OPC_CompleteMatch: {
3359 // The match has been completed, and any new nodes (if any) have been
3360 // created. Patch up references to the matched dag to use the newly
3362 unsigned NumResults = MatcherTable[MatcherIndex++];
3364 for (unsigned i = 0; i != NumResults; ++i) {
3365 unsigned ResSlot = MatcherTable[MatcherIndex++];
3367 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3369 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3370 SDValue Res = RecordedNodes[ResSlot].first;
3372 assert(i < NodeToMatch->getNumValues() &&
3373 NodeToMatch->getValueType(i) != MVT::Other &&
3374 NodeToMatch->getValueType(i) != MVT::Glue &&
3375 "Invalid number of results to complete!");
3376 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3377 NodeToMatch->getValueType(i) == MVT::iPTR ||
3378 Res.getValueType() == MVT::iPTR ||
3379 NodeToMatch->getValueType(i).getSizeInBits() ==
3380 Res.getValueType().getSizeInBits()) &&
3381 "invalid replacement");
3382 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3385 // If the root node defines glue, add it to the glue nodes to update list.
3386 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3387 GlueResultNodesMatched.push_back(NodeToMatch);
3389 // Update chain and glue uses.
3390 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3391 InputGlue, GlueResultNodesMatched, false);
3393 assert(NodeToMatch->use_empty() &&
3394 "Didn't replace all uses of the node?");
3396 // FIXME: We just return here, which interacts correctly with SelectRoot
3397 // above. We should fix this to not return an SDNode* anymore.
3402 // If the code reached this point, then the match failed. See if there is
3403 // another child to try in the current 'Scope', otherwise pop it until we
3404 // find a case to check.
3405 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3406 ++NumDAGIselRetries;
3408 if (MatchScopes.empty()) {
3409 CannotYetSelect(NodeToMatch);
3413 // Restore the interpreter state back to the point where the scope was
3415 MatchScope &LastScope = MatchScopes.back();
3416 RecordedNodes.resize(LastScope.NumRecordedNodes);
3418 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3419 N = NodeStack.back();
3421 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3422 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3423 MatcherIndex = LastScope.FailIndex;
3425 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3427 InputChain = LastScope.InputChain;
3428 InputGlue = LastScope.InputGlue;
3429 if (!LastScope.HasChainNodesMatched)
3430 ChainNodesMatched.clear();
3431 if (!LastScope.HasGlueResultNodesMatched)
3432 GlueResultNodesMatched.clear();
3434 // Check to see what the offset is at the new MatcherIndex. If it is zero
3435 // we have reached the end of this scope, otherwise we have another child
3436 // in the current scope to try.
3437 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3438 if (NumToSkip & 128)
3439 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3441 // If we have another child in this scope to match, update FailIndex and
3443 if (NumToSkip != 0) {
3444 LastScope.FailIndex = MatcherIndex+NumToSkip;
3448 // End of this scope, pop it and try the next child in the containing
3450 MatchScopes.pop_back();
3457 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3459 raw_string_ostream Msg(msg);
3460 Msg << "Cannot select: ";
3462 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3463 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3464 N->getOpcode() != ISD::INTRINSIC_VOID) {
3465 N->printrFull(Msg, CurDAG);
3466 Msg << "\nIn function: " << MF->getName();
3468 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3470 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3471 if (iid < Intrinsic::num_intrinsics)
3472 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3473 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3474 Msg << "target intrinsic %" << TII->getName(iid);
3476 Msg << "unknown intrinsic #" << iid;
3478 report_fatal_error(Msg.str());
3481 char SelectionDAGISel::ID = 0;