1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/DebugInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetIntrinsicInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLibraryInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/Timer.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/ADT/PostOrderIterator.h"
55 #include "llvm/ADT/Statistic.h"
59 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
60 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
61 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
62 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
63 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
68 cl::desc("Enable extra verbose messages in the \"fast\" "
69 "instruction selector"));
71 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
72 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
73 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
74 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
75 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
76 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
77 STATISTIC(NumFastIselFailUnwind,"Fast isel fails on Unwind");
78 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
80 // Standard binary operators...
81 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
82 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
83 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
84 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
85 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
86 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
87 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
88 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
89 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
90 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
91 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
92 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
94 // Logical operators...
95 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
96 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
97 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
99 // Memory instructions...
100 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
101 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
102 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
103 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
104 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
105 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
106 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
108 // Convert instructions...
109 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
110 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
111 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
112 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
113 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
114 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
115 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
116 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
117 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
118 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
119 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
120 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
122 // Other instructions...
123 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
124 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
125 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
126 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
127 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
128 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
129 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
130 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
131 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
132 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
133 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
134 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
135 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
136 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
137 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
141 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
142 cl::desc("Enable verbose messages in the \"fast\" "
143 "instruction selector"));
145 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
146 cl::desc("Enable abort calls when \"fast\" instruction fails"));
150 cl::desc("use Machine Branch Probability Info"),
151 cl::init(true), cl::Hidden);
155 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
156 cl::desc("Pop up a window to show dags before the first "
157 "dag combine pass"));
159 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
160 cl::desc("Pop up a window to show dags before legalize types"));
162 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
163 cl::desc("Pop up a window to show dags before legalize"));
165 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
166 cl::desc("Pop up a window to show dags before the second "
167 "dag combine pass"));
169 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
170 cl::desc("Pop up a window to show dags before the post legalize types"
171 " dag combine pass"));
173 ViewISelDAGs("view-isel-dags", cl::Hidden,
174 cl::desc("Pop up a window to show isel dags as they are selected"));
176 ViewSchedDAGs("view-sched-dags", cl::Hidden,
177 cl::desc("Pop up a window to show sched dags as they are processed"));
179 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
180 cl::desc("Pop up a window to show SUnit dags after they are processed"));
182 static const bool ViewDAGCombine1 = false,
183 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
184 ViewDAGCombine2 = false,
185 ViewDAGCombineLT = false,
186 ViewISelDAGs = false, ViewSchedDAGs = false,
187 ViewSUnitDAGs = false;
190 //===---------------------------------------------------------------------===//
192 /// RegisterScheduler class - Track the registration of instruction schedulers.
194 //===---------------------------------------------------------------------===//
195 MachinePassRegistry RegisterScheduler::Registry;
197 //===---------------------------------------------------------------------===//
199 /// ISHeuristic command line option for instruction schedulers.
201 //===---------------------------------------------------------------------===//
202 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
203 RegisterPassParser<RegisterScheduler> >
204 ISHeuristic("pre-RA-sched",
205 cl::init(&createDefaultScheduler),
206 cl::desc("Instruction schedulers available (before register"
209 static RegisterScheduler
210 defaultListDAGScheduler("default", "Best scheduler for the target",
211 createDefaultScheduler);
214 //===--------------------------------------------------------------------===//
215 /// createDefaultScheduler - This creates an instruction scheduler appropriate
217 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
218 CodeGenOpt::Level OptLevel) {
219 const TargetLowering &TLI = IS->getTargetLowering();
221 if (OptLevel == CodeGenOpt::None)
222 return createSourceListDAGScheduler(IS, OptLevel);
223 if (TLI.getSchedulingPreference() == Sched::RegPressure)
224 return createBURRListDAGScheduler(IS, OptLevel);
225 if (TLI.getSchedulingPreference() == Sched::Hybrid)
226 return createHybridListDAGScheduler(IS, OptLevel);
227 assert(TLI.getSchedulingPreference() == Sched::ILP &&
228 "Unknown sched type!");
229 return createILPListDAGScheduler(IS, OptLevel);
233 // EmitInstrWithCustomInserter - This method should be implemented by targets
234 // that mark instructions with the 'usesCustomInserter' flag. These
235 // instructions are special in various ways, which require special support to
236 // insert. The specified MachineInstr is created but not inserted into any
237 // basic blocks, and this method is called to expand it into a sequence of
238 // instructions, potentially also creating new basic blocks and control flow.
239 // When new basic blocks are inserted and the edges from MBB to its successors
240 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
243 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
244 MachineBasicBlock *MBB) const {
246 dbgs() << "If a target marks an instruction with "
247 "'usesCustomInserter', it must implement "
248 "TargetLowering::EmitInstrWithCustomInserter!";
254 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
255 SDNode *Node) const {
256 assert(!MI->hasPostISelHook() &&
257 "If a target marks an instruction with 'hasPostISelHook', "
258 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
261 //===----------------------------------------------------------------------===//
262 // SelectionDAGISel code
263 //===----------------------------------------------------------------------===//
265 void SelectionDAGISel::ISelUpdater::anchor() { }
267 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
268 CodeGenOpt::Level OL) :
269 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
270 FuncInfo(new FunctionLoweringInfo(TLI)),
271 CurDAG(new SelectionDAG(tm, OL)),
272 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
276 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
277 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
278 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
279 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
282 SelectionDAGISel::~SelectionDAGISel() {
288 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
289 AU.addRequired<AliasAnalysis>();
290 AU.addPreserved<AliasAnalysis>();
291 AU.addRequired<GCModuleInfo>();
292 AU.addPreserved<GCModuleInfo>();
293 AU.addRequired<TargetLibraryInfo>();
294 if (UseMBPI && OptLevel != CodeGenOpt::None)
295 AU.addRequired<BranchProbabilityInfo>();
296 MachineFunctionPass::getAnalysisUsage(AU);
299 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
300 /// may trap on it. In this case we have to split the edge so that the path
301 /// through the predecessor block that doesn't go to the phi block doesn't
302 /// execute the possibly trapping instruction.
304 /// This is required for correctness, so it must be done at -O0.
306 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
307 // Loop for blocks with phi nodes.
308 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
309 PHINode *PN = dyn_cast<PHINode>(BB->begin());
310 if (PN == 0) continue;
313 // For each block with a PHI node, check to see if any of the input values
314 // are potentially trapping constant expressions. Constant expressions are
315 // the only potentially trapping value that can occur as the argument to a
317 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
318 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
319 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
320 if (CE == 0 || !CE->canTrap()) continue;
322 // The only case we have to worry about is when the edge is critical.
323 // Since this block has a PHI Node, we assume it has multiple input
324 // edges: check to see if the pred has multiple successors.
325 BasicBlock *Pred = PN->getIncomingBlock(i);
326 if (Pred->getTerminator()->getNumSuccessors() == 1)
329 // Okay, we have to split this edge.
330 SplitCriticalEdge(Pred->getTerminator(),
331 GetSuccessorNumber(Pred, BB), SDISel, true);
337 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
338 // Do some sanity-checking on the command-line options.
339 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
340 "-fast-isel-verbose requires -fast-isel");
341 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
342 "-fast-isel-abort requires -fast-isel");
344 const Function &Fn = *mf.getFunction();
345 const TargetInstrInfo &TII = *TM.getInstrInfo();
346 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
349 RegInfo = &MF->getRegInfo();
350 AA = &getAnalysis<AliasAnalysis>();
351 LibInfo = &getAnalysis<TargetLibraryInfo>();
352 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
354 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
356 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
359 FuncInfo->set(Fn, *MF);
361 if (UseMBPI && OptLevel != CodeGenOpt::None)
362 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
366 SDB->init(GFI, *AA, LibInfo);
368 SelectAllBasicBlocks(Fn);
370 // If the first basic block in the function has live ins that need to be
371 // copied into vregs, emit the copies into the top of the block before
372 // emitting the code for the block.
373 MachineBasicBlock *EntryMBB = MF->begin();
374 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
376 DenseMap<unsigned, unsigned> LiveInMap;
377 if (!FuncInfo->ArgDbgValues.empty())
378 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
379 E = RegInfo->livein_end(); LI != E; ++LI)
381 LiveInMap.insert(std::make_pair(LI->first, LI->second));
383 // Insert DBG_VALUE instructions for function arguments to the entry block.
384 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
385 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
386 unsigned Reg = MI->getOperand(0).getReg();
387 if (TargetRegisterInfo::isPhysicalRegister(Reg))
388 EntryMBB->insert(EntryMBB->begin(), MI);
390 MachineInstr *Def = RegInfo->getVRegDef(Reg);
391 MachineBasicBlock::iterator InsertPos = Def;
392 // FIXME: VR def may not be in entry block.
393 Def->getParent()->insert(llvm::next(InsertPos), MI);
396 // If Reg is live-in then update debug info to track its copy in a vreg.
397 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
398 if (LDI != LiveInMap.end()) {
399 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
400 MachineBasicBlock::iterator InsertPos = Def;
401 const MDNode *Variable =
402 MI->getOperand(MI->getNumOperands()-1).getMetadata();
403 unsigned Offset = MI->getOperand(1).getImm();
404 // Def is never a terminator here, so it is ok to increment InsertPos.
405 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
406 TII.get(TargetOpcode::DBG_VALUE))
407 .addReg(LDI->second, RegState::Debug)
408 .addImm(Offset).addMetadata(Variable);
410 // If this vreg is directly copied into an exported register then
411 // that COPY instructions also need DBG_VALUE, if it is the only
412 // user of LDI->second.
413 MachineInstr *CopyUseMI = NULL;
414 for (MachineRegisterInfo::use_iterator
415 UI = RegInfo->use_begin(LDI->second);
416 MachineInstr *UseMI = UI.skipInstruction();) {
417 if (UseMI->isDebugValue()) continue;
418 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
419 CopyUseMI = UseMI; continue;
421 // Otherwise this is another use or second copy use.
422 CopyUseMI = NULL; break;
425 MachineInstr *NewMI =
426 BuildMI(*MF, CopyUseMI->getDebugLoc(),
427 TII.get(TargetOpcode::DBG_VALUE))
428 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
429 .addImm(Offset).addMetadata(Variable);
430 MachineBasicBlock::iterator Pos = CopyUseMI;
431 EntryMBB->insertAfter(Pos, NewMI);
436 // Determine if there are any calls in this machine function.
437 MachineFrameInfo *MFI = MF->getFrameInfo();
438 if (!MFI->hasCalls()) {
439 for (MachineFunction::const_iterator
440 I = MF->begin(), E = MF->end(); I != E; ++I) {
441 const MachineBasicBlock *MBB = I;
442 for (MachineBasicBlock::const_iterator
443 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
444 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
446 if ((MCID.isCall() && !MCID.isReturn()) ||
447 II->isStackAligningInlineAsm()) {
448 MFI->setHasCalls(true);
456 // Determine if there is a call to setjmp in the machine function.
457 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
459 // Replace forward-declared registers with the registers containing
460 // the desired value.
461 MachineRegisterInfo &MRI = MF->getRegInfo();
462 for (DenseMap<unsigned, unsigned>::iterator
463 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
465 unsigned From = I->first;
466 unsigned To = I->second;
467 // If To is also scheduled to be replaced, find what its ultimate
470 DenseMap<unsigned, unsigned>::iterator J =
471 FuncInfo->RegFixups.find(To);
476 MRI.replaceRegWith(From, To);
479 // Release function-specific state. SDB and CurDAG are already cleared
486 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
487 BasicBlock::const_iterator End,
489 // Lower all of the non-terminator instructions. If a call is emitted
490 // as a tail call, cease emitting nodes for this block. Terminators
491 // are handled below.
492 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
495 // Make sure the root of the DAG is up-to-date.
496 CurDAG->setRoot(SDB->getControlRoot());
497 HadTailCall = SDB->HasTailCall;
500 // Final step, emit the lowered DAG as machine code.
504 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
505 SmallPtrSet<SDNode*, 128> VisitedNodes;
506 SmallVector<SDNode*, 128> Worklist;
508 Worklist.push_back(CurDAG->getRoot().getNode());
515 SDNode *N = Worklist.pop_back_val();
517 // If we've already seen this node, ignore it.
518 if (!VisitedNodes.insert(N))
521 // Otherwise, add all chain operands to the worklist.
522 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
523 if (N->getOperand(i).getValueType() == MVT::Other)
524 Worklist.push_back(N->getOperand(i).getNode());
526 // If this is a CopyToReg with a vreg dest, process it.
527 if (N->getOpcode() != ISD::CopyToReg)
530 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
531 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
534 // Ignore non-scalar or non-integer values.
535 SDValue Src = N->getOperand(2);
536 EVT SrcVT = Src.getValueType();
537 if (!SrcVT.isInteger() || SrcVT.isVector())
540 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
541 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
542 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
543 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
544 } while (!Worklist.empty());
547 void SelectionDAGISel::CodeGenAndEmitDAG() {
548 std::string GroupName;
549 if (TimePassesIsEnabled)
550 GroupName = "Instruction Selection and Scheduling";
551 std::string BlockName;
552 int BlockNumber = -1;
555 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
556 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
560 BlockNumber = FuncInfo->MBB->getNumber();
561 BlockName = MF->getFunction()->getName().str() + ":" +
562 FuncInfo->MBB->getBasicBlock()->getName().str();
564 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
565 << " '" << BlockName << "'\n"; CurDAG->dump());
567 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
569 // Run the DAG combiner in pre-legalize mode.
571 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
572 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
575 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
576 << " '" << BlockName << "'\n"; CurDAG->dump());
578 // Second step, hack on the DAG until it only uses operations and types that
579 // the target supports.
580 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
585 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
586 Changed = CurDAG->LegalizeTypes();
589 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
590 << " '" << BlockName << "'\n"; CurDAG->dump());
593 if (ViewDAGCombineLT)
594 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
596 // Run the DAG combiner in post-type-legalize mode.
598 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
599 TimePassesIsEnabled);
600 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
603 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
604 << " '" << BlockName << "'\n"; CurDAG->dump());
608 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
609 Changed = CurDAG->LegalizeVectors();
614 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
615 CurDAG->LegalizeTypes();
618 if (ViewDAGCombineLT)
619 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
621 // Run the DAG combiner in post-type-legalize mode.
623 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
624 TimePassesIsEnabled);
625 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
628 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
629 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
632 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
635 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
639 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
640 << " '" << BlockName << "'\n"; CurDAG->dump());
642 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
644 // Run the DAG combiner in post-legalize mode.
646 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
647 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
650 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
651 << " '" << BlockName << "'\n"; CurDAG->dump());
653 if (OptLevel != CodeGenOpt::None)
654 ComputeLiveOutVRegInfo();
656 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
658 // Third, instruction select all of the operations to machine code, adding the
659 // code to the MachineBasicBlock.
661 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
662 DoInstructionSelection();
665 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
666 << " '" << BlockName << "'\n"; CurDAG->dump());
668 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
670 // Schedule machine code.
671 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
673 NamedRegionTimer T("Instruction Scheduling", GroupName,
674 TimePassesIsEnabled);
675 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
678 if (ViewSUnitDAGs) Scheduler->viewGraph();
680 // Emit machine code to BB. This can change 'BB' to the last block being
682 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
684 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
686 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
687 FuncInfo->InsertPt = Scheduler->InsertPos;
690 // If the block was split, make sure we update any references that are used to
691 // update PHI nodes later on.
692 if (FirstMBB != LastMBB)
693 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
695 // Free the scheduler state.
697 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
698 TimePassesIsEnabled);
702 // Free the SelectionDAG state, now that we're finished with it.
706 void SelectionDAGISel::DoInstructionSelection() {
707 DEBUG(errs() << "===== Instruction selection begins: BB#"
708 << FuncInfo->MBB->getNumber()
709 << " '" << FuncInfo->MBB->getName() << "'\n");
713 // Select target instructions for the DAG.
715 // Number all nodes with a topological order and set DAGSize.
716 DAGSize = CurDAG->AssignTopologicalOrder();
718 // Create a dummy node (which is not added to allnodes), that adds
719 // a reference to the root node, preventing it from being deleted,
720 // and tracking any changes of the root.
721 HandleSDNode Dummy(CurDAG->getRoot());
722 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
725 // The AllNodes list is now topological-sorted. Visit the
726 // nodes by starting at the end of the list (the root of the
727 // graph) and preceding back toward the beginning (the entry
729 while (ISelPosition != CurDAG->allnodes_begin()) {
730 SDNode *Node = --ISelPosition;
731 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
732 // but there are currently some corner cases that it misses. Also, this
733 // makes it theoretically possible to disable the DAGCombiner.
734 if (Node->use_empty())
737 SDNode *ResNode = Select(Node);
739 // FIXME: This is pretty gross. 'Select' should be changed to not return
740 // anything at all and this code should be nuked with a tactical strike.
742 // If node should not be replaced, continue with the next one.
743 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
747 ReplaceUses(Node, ResNode);
749 // If after the replacement this node is not used any more,
750 // remove this dead node.
751 if (Node->use_empty()) { // Don't delete EntryToken, etc.
752 ISelUpdater ISU(ISelPosition);
753 CurDAG->RemoveDeadNode(Node, &ISU);
757 CurDAG->setRoot(Dummy.getValue());
760 DEBUG(errs() << "===== Instruction selection ends:\n");
762 PostprocessISelDAG();
765 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
766 /// do other setup for EH landing-pad blocks.
767 void SelectionDAGISel::PrepareEHLandingPad() {
768 MachineBasicBlock *MBB = FuncInfo->MBB;
770 // Add a label to mark the beginning of the landing pad. Deletion of the
771 // landing pad can thus be detected via the MachineModuleInfo.
772 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
774 // Assign the call site to the landing pad's begin label.
775 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
777 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
778 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
781 // Mark exception register as live in.
782 unsigned Reg = TLI.getExceptionAddressRegister();
783 if (Reg) MBB->addLiveIn(Reg);
785 // Mark exception selector register as live in.
786 Reg = TLI.getExceptionSelectorRegister();
787 if (Reg) MBB->addLiveIn(Reg);
789 // FIXME: Hack around an exception handling flaw (PR1508): the personality
790 // function and list of typeids logically belong to the invoke (or, if you
791 // like, the basic block containing the invoke), and need to be associated
792 // with it in the dwarf exception handling tables. Currently however the
793 // information is provided by an intrinsic (eh.selector) that can be moved
794 // to unexpected places by the optimizers: if the unwind edge is critical,
795 // then breaking it can result in the intrinsics being in the successor of
796 // the landing pad, not the landing pad itself. This results
797 // in exceptions not being caught because no typeids are associated with
798 // the invoke. This may not be the only way things can go wrong, but it
799 // is the only way we try to work around for the moment.
800 const BasicBlock *LLVMBB = MBB->getBasicBlock();
801 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
803 if (Br && Br->isUnconditional()) { // Critical edge?
804 BasicBlock::const_iterator I, E;
805 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
806 if (isa<EHSelectorInst>(I))
810 // No catch info found - try to extract some from the successor.
811 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
815 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
816 /// load into the specified FoldInst. Note that we could have a sequence where
817 /// multiple LLVM IR instructions are folded into the same machineinstr. For
818 /// example we could have:
819 /// A: x = load i32 *P
820 /// B: y = icmp A, 42
823 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
824 /// any other folded instructions) because it is between A and C.
826 /// If we succeed in folding the load into the operation, return true.
828 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
829 const Instruction *FoldInst,
831 // We know that the load has a single use, but don't know what it is. If it
832 // isn't one of the folded instructions, then we can't succeed here. Handle
833 // this by scanning the single-use users of the load until we get to FoldInst.
834 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
836 const Instruction *TheUser = LI->use_back();
837 while (TheUser != FoldInst && // Scan up until we find FoldInst.
838 // Stay in the right block.
839 TheUser->getParent() == FoldInst->getParent() &&
840 --MaxUsers) { // Don't scan too far.
841 // If there are multiple or no uses of this instruction, then bail out.
842 if (!TheUser->hasOneUse())
845 TheUser = TheUser->use_back();
848 // If we didn't find the fold instruction, then we failed to collapse the
850 if (TheUser != FoldInst)
853 // Don't try to fold volatile loads. Target has to deal with alignment
855 if (LI->isVolatile()) return false;
857 // Figure out which vreg this is going into. If there is no assigned vreg yet
858 // then there actually was no reference to it. Perhaps the load is referenced
859 // by a dead instruction.
860 unsigned LoadReg = FastIS->getRegForValue(LI);
864 // Check to see what the uses of this vreg are. If it has no uses, or more
865 // than one use (at the machine instr level) then we can't fold it.
866 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
867 if (RI == RegInfo->reg_end())
870 // See if there is exactly one use of the vreg. If there are multiple uses,
871 // then the instruction got lowered to multiple machine instructions or the
872 // use of the loaded value ended up being multiple operands of the result, in
873 // either case, we can't fold this.
874 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
875 if (PostRI != RegInfo->reg_end())
878 assert(RI.getOperand().isUse() &&
879 "The only use of the vreg must be a use, we haven't emitted the def!");
881 MachineInstr *User = &*RI;
883 // Set the insertion point properly. Folding the load can cause generation of
884 // other random instructions (like sign extends) for addressing modes, make
885 // sure they get inserted in a logical place before the new instruction.
886 FuncInfo->InsertPt = User;
887 FuncInfo->MBB = User->getParent();
889 // Ask the target to try folding the load.
890 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
893 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
894 /// side-effect free and is either dead or folded into a generated instruction.
895 /// Return false if it needs to be emitted.
896 static bool isFoldedOrDeadInstruction(const Instruction *I,
897 FunctionLoweringInfo *FuncInfo) {
898 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
899 !isa<TerminatorInst>(I) && // Terminators aren't folded.
900 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
901 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
902 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
906 static void collectFailStats(const Instruction *I) {
907 switch (I->getOpcode()) {
908 default: assert (0 && "<Invalid operator> ");
911 case Instruction::Ret: NumFastIselFailRet++; return;
912 case Instruction::Br: NumFastIselFailBr++; return;
913 case Instruction::Switch: NumFastIselFailSwitch++; return;
914 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
915 case Instruction::Invoke: NumFastIselFailInvoke++; return;
916 case Instruction::Resume: NumFastIselFailResume++; return;
917 case Instruction::Unwind: NumFastIselFailUnwind++; return;
918 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
920 // Standard binary operators...
921 case Instruction::Add: NumFastIselFailAdd++; return;
922 case Instruction::FAdd: NumFastIselFailFAdd++; return;
923 case Instruction::Sub: NumFastIselFailSub++; return;
924 case Instruction::FSub: NumFastIselFailFSub++; return;
925 case Instruction::Mul: NumFastIselFailMul++; return;
926 case Instruction::FMul: NumFastIselFailFMul++; return;
927 case Instruction::UDiv: NumFastIselFailUDiv++; return;
928 case Instruction::SDiv: NumFastIselFailSDiv++; return;
929 case Instruction::FDiv: NumFastIselFailFDiv++; return;
930 case Instruction::URem: NumFastIselFailURem++; return;
931 case Instruction::SRem: NumFastIselFailSRem++; return;
932 case Instruction::FRem: NumFastIselFailFRem++; return;
934 // Logical operators...
935 case Instruction::And: NumFastIselFailAnd++; return;
936 case Instruction::Or: NumFastIselFailOr++; return;
937 case Instruction::Xor: NumFastIselFailXor++; return;
939 // Memory instructions...
940 case Instruction::Alloca: NumFastIselFailAlloca++; return;
941 case Instruction::Load: NumFastIselFailLoad++; return;
942 case Instruction::Store: NumFastIselFailStore++; return;
943 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
944 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
945 case Instruction::Fence: NumFastIselFailFence++; return;
946 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
948 // Convert instructions...
949 case Instruction::Trunc: NumFastIselFailTrunc++; return;
950 case Instruction::ZExt: NumFastIselFailZExt++; return;
951 case Instruction::SExt: NumFastIselFailSExt++; return;
952 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
953 case Instruction::FPExt: NumFastIselFailFPExt++; return;
954 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
955 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
956 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
957 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
958 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
959 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
960 case Instruction::BitCast: NumFastIselFailBitCast++; return;
962 // Other instructions...
963 case Instruction::ICmp: NumFastIselFailICmp++; return;
964 case Instruction::FCmp: NumFastIselFailFCmp++; return;
965 case Instruction::PHI: NumFastIselFailPHI++; return;
966 case Instruction::Select: NumFastIselFailSelect++; return;
967 case Instruction::Call: NumFastIselFailCall++; return;
968 case Instruction::Shl: NumFastIselFailShl++; return;
969 case Instruction::LShr: NumFastIselFailLShr++; return;
970 case Instruction::AShr: NumFastIselFailAShr++; return;
971 case Instruction::VAArg: NumFastIselFailVAArg++; return;
972 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
973 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
974 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
975 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
976 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
977 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
983 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
984 // Initialize the Fast-ISel state, if needed.
985 FastISel *FastIS = 0;
986 if (TM.Options.EnableFastISel)
987 FastIS = TLI.createFastISel(*FuncInfo);
989 // Iterate over all basic blocks in the function.
990 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
991 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
992 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
993 const BasicBlock *LLVMBB = *I;
995 if (OptLevel != CodeGenOpt::None) {
996 bool AllPredsVisited = true;
997 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
999 if (!FuncInfo->VisitedBBs.count(*PI)) {
1000 AllPredsVisited = false;
1005 if (AllPredsVisited) {
1006 for (BasicBlock::const_iterator I = LLVMBB->begin();
1007 isa<PHINode>(I); ++I)
1008 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
1010 for (BasicBlock::const_iterator I = LLVMBB->begin();
1011 isa<PHINode>(I); ++I)
1012 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
1015 FuncInfo->VisitedBBs.insert(LLVMBB);
1018 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1019 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1021 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1022 BasicBlock::const_iterator const End = LLVMBB->end();
1023 BasicBlock::const_iterator BI = End;
1025 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1027 // Setup an EH landing-pad block.
1028 if (FuncInfo->MBB->isLandingPad())
1029 PrepareEHLandingPad();
1031 // Lower any arguments needed in this block if this is the entry block.
1032 if (LLVMBB == &Fn.getEntryBlock())
1033 LowerArguments(LLVMBB);
1035 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1037 FastIS->startNewBlock();
1039 // Emit code for any incoming arguments. This must happen before
1040 // beginning FastISel on the entry block.
1041 if (LLVMBB == &Fn.getEntryBlock()) {
1042 CurDAG->setRoot(SDB->getControlRoot());
1044 CodeGenAndEmitDAG();
1046 // If we inserted any instructions at the beginning, make a note of
1047 // where they are, so we can be sure to emit subsequent instructions
1049 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1050 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1052 FastIS->setLastLocalValue(0);
1055 unsigned NumFastIselRemaining = std::distance(Begin, End);
1056 // Do FastISel on as many instructions as possible.
1057 for (; BI != Begin; --BI) {
1058 const Instruction *Inst = llvm::prior(BI);
1060 // If we no longer require this instruction, skip it.
1061 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1062 --NumFastIselRemaining;
1066 // Bottom-up: reset the insert pos at the top, after any local-value
1068 FastIS->recomputeInsertPt();
1070 // Try to select the instruction with FastISel.
1071 if (FastIS->SelectInstruction(Inst)) {
1072 --NumFastIselRemaining;
1073 ++NumFastIselSuccess;
1074 // If fast isel succeeded, skip over all the folded instructions, and
1075 // then see if there is a load right before the selected instructions.
1076 // Try to fold the load if so.
1077 const Instruction *BeforeInst = Inst;
1078 while (BeforeInst != Begin) {
1079 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1080 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1083 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1084 BeforeInst->hasOneUse() &&
1085 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1086 // If we succeeded, don't re-select the load.
1087 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1088 --NumFastIselRemaining;
1089 ++NumFastIselSuccess;
1095 if (EnableFastISelVerbose2)
1096 collectFailStats(Inst);
1099 // Then handle certain instructions as single-LLVM-Instruction blocks.
1100 if (isa<CallInst>(Inst)) {
1102 if (EnableFastISelVerbose || EnableFastISelAbort) {
1103 dbgs() << "FastISel missed call: ";
1107 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1108 unsigned &R = FuncInfo->ValueMap[Inst];
1110 R = FuncInfo->CreateRegs(Inst->getType());
1113 bool HadTailCall = false;
1114 SelectBasicBlock(Inst, BI, HadTailCall);
1116 // Recompute NumFastIselRemaining as Selection DAG instruction
1117 // selection may have handled the call, input args, etc.
1118 unsigned RemainingNow = std::distance(Begin, BI);
1119 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1121 // If the call was emitted as a tail call, we're done with the block.
1127 NumFastIselRemaining = RemainingNow;
1131 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1132 // Don't abort, and use a different message for terminator misses.
1133 NumFastIselFailures += NumFastIselRemaining;
1134 if (EnableFastISelVerbose || EnableFastISelAbort) {
1135 dbgs() << "FastISel missed terminator: ";
1139 NumFastIselFailures += NumFastIselRemaining;
1140 if (EnableFastISelVerbose || EnableFastISelAbort) {
1141 dbgs() << "FastISel miss: ";
1144 if (EnableFastISelAbort)
1145 // The "fast" selector couldn't handle something and bailed.
1146 // For the purpose of debugging, just abort.
1147 llvm_unreachable("FastISel didn't select the entire block");
1152 FastIS->recomputeInsertPt();
1158 ++NumFastIselBlocks;
1161 // Run SelectionDAG instruction selection on the remainder of the block
1162 // not handled by FastISel. If FastISel is not run, this is the entire
1165 SelectBasicBlock(Begin, BI, HadTailCall);
1169 FuncInfo->PHINodesToUpdate.clear();
1173 SDB->clearDanglingDebugInfo();
1177 SelectionDAGISel::FinishBasicBlock() {
1179 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1180 << FuncInfo->PHINodesToUpdate.size() << "\n";
1181 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1182 dbgs() << "Node " << i << " : ("
1183 << FuncInfo->PHINodesToUpdate[i].first
1184 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1186 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1187 // PHI nodes in successors.
1188 if (SDB->SwitchCases.empty() &&
1189 SDB->JTCases.empty() &&
1190 SDB->BitTestCases.empty()) {
1191 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1192 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1193 assert(PHI->isPHI() &&
1194 "This is not a machine PHI node that we are updating!");
1195 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1198 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1199 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1204 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1205 // Lower header first, if it wasn't already lowered
1206 if (!SDB->BitTestCases[i].Emitted) {
1207 // Set the current basic block to the mbb we wish to insert the code into
1208 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1209 FuncInfo->InsertPt = FuncInfo->MBB->end();
1211 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1212 CurDAG->setRoot(SDB->getRoot());
1214 CodeGenAndEmitDAG();
1217 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1218 // Set the current basic block to the mbb we wish to insert the code into
1219 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1220 FuncInfo->InsertPt = FuncInfo->MBB->end();
1223 SDB->visitBitTestCase(SDB->BitTestCases[i],
1224 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1225 SDB->BitTestCases[i].Reg,
1226 SDB->BitTestCases[i].Cases[j],
1229 SDB->visitBitTestCase(SDB->BitTestCases[i],
1230 SDB->BitTestCases[i].Default,
1231 SDB->BitTestCases[i].Reg,
1232 SDB->BitTestCases[i].Cases[j],
1236 CurDAG->setRoot(SDB->getRoot());
1238 CodeGenAndEmitDAG();
1242 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1244 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1245 MachineBasicBlock *PHIBB = PHI->getParent();
1246 assert(PHI->isPHI() &&
1247 "This is not a machine PHI node that we are updating!");
1248 // This is "default" BB. We have two jumps to it. From "header" BB and
1249 // from last "case" BB.
1250 if (PHIBB == SDB->BitTestCases[i].Default) {
1251 PHI->addOperand(MachineOperand::
1252 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1254 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1255 PHI->addOperand(MachineOperand::
1256 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1258 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1261 // One of "cases" BB.
1262 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1264 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1265 if (cBB->isSuccessor(PHIBB)) {
1266 PHI->addOperand(MachineOperand::
1267 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1269 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1274 SDB->BitTestCases.clear();
1276 // If the JumpTable record is filled in, then we need to emit a jump table.
1277 // Updating the PHI nodes is tricky in this case, since we need to determine
1278 // whether the PHI is a successor of the range check MBB or the jump table MBB
1279 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1280 // Lower header first, if it wasn't already lowered
1281 if (!SDB->JTCases[i].first.Emitted) {
1282 // Set the current basic block to the mbb we wish to insert the code into
1283 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1284 FuncInfo->InsertPt = FuncInfo->MBB->end();
1286 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1288 CurDAG->setRoot(SDB->getRoot());
1290 CodeGenAndEmitDAG();
1293 // Set the current basic block to the mbb we wish to insert the code into
1294 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1295 FuncInfo->InsertPt = FuncInfo->MBB->end();
1297 SDB->visitJumpTable(SDB->JTCases[i].second);
1298 CurDAG->setRoot(SDB->getRoot());
1300 CodeGenAndEmitDAG();
1303 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1305 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1306 MachineBasicBlock *PHIBB = PHI->getParent();
1307 assert(PHI->isPHI() &&
1308 "This is not a machine PHI node that we are updating!");
1309 // "default" BB. We can go there only from header BB.
1310 if (PHIBB == SDB->JTCases[i].second.Default) {
1312 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1315 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1317 // JT BB. Just iterate over successors here
1318 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1320 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1322 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1326 SDB->JTCases.clear();
1328 // If the switch block involved a branch to one of the actual successors, we
1329 // need to update PHI nodes in that block.
1330 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1331 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1332 assert(PHI->isPHI() &&
1333 "This is not a machine PHI node that we are updating!");
1334 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1336 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1337 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1341 // If we generated any switch lowering information, build and codegen any
1342 // additional DAGs necessary.
1343 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1344 // Set the current basic block to the mbb we wish to insert the code into
1345 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1346 FuncInfo->InsertPt = FuncInfo->MBB->end();
1348 // Determine the unique successors.
1349 SmallVector<MachineBasicBlock *, 2> Succs;
1350 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1351 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1352 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1354 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1355 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1356 CurDAG->setRoot(SDB->getRoot());
1358 CodeGenAndEmitDAG();
1360 // Remember the last block, now that any splitting is done, for use in
1361 // populating PHI nodes in successors.
1362 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1364 // Handle any PHI nodes in successors of this chunk, as if we were coming
1365 // from the original BB before switch expansion. Note that PHI nodes can
1366 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1367 // handle them the right number of times.
1368 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1369 FuncInfo->MBB = Succs[i];
1370 FuncInfo->InsertPt = FuncInfo->MBB->end();
1371 // FuncInfo->MBB may have been removed from the CFG if a branch was
1373 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1374 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1375 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1377 // This value for this PHI node is recorded in PHINodesToUpdate.
1378 for (unsigned pn = 0; ; ++pn) {
1379 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1380 "Didn't find PHI entry!");
1381 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1382 Phi->addOperand(MachineOperand::
1383 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1385 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1393 SDB->SwitchCases.clear();
1397 /// Create the scheduler. If a specific scheduler was specified
1398 /// via the SchedulerRegistry, use it, otherwise select the
1399 /// one preferred by the target.
1401 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1402 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1406 RegisterScheduler::setDefault(Ctor);
1409 return Ctor(this, OptLevel);
1412 //===----------------------------------------------------------------------===//
1413 // Helper functions used by the generated instruction selector.
1414 //===----------------------------------------------------------------------===//
1415 // Calls to these methods are generated by tblgen.
1417 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1418 /// the dag combiner simplified the 255, we still want to match. RHS is the
1419 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1420 /// specified in the .td file (e.g. 255).
1421 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1422 int64_t DesiredMaskS) const {
1423 const APInt &ActualMask = RHS->getAPIntValue();
1424 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1426 // If the actual mask exactly matches, success!
1427 if (ActualMask == DesiredMask)
1430 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1431 if (ActualMask.intersects(~DesiredMask))
1434 // Otherwise, the DAG Combiner may have proven that the value coming in is
1435 // either already zero or is not demanded. Check for known zero input bits.
1436 APInt NeededMask = DesiredMask & ~ActualMask;
1437 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1440 // TODO: check to see if missing bits are just not demanded.
1442 // Otherwise, this pattern doesn't match.
1446 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1447 /// the dag combiner simplified the 255, we still want to match. RHS is the
1448 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1449 /// specified in the .td file (e.g. 255).
1450 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1451 int64_t DesiredMaskS) const {
1452 const APInt &ActualMask = RHS->getAPIntValue();
1453 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1455 // If the actual mask exactly matches, success!
1456 if (ActualMask == DesiredMask)
1459 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1460 if (ActualMask.intersects(~DesiredMask))
1463 // Otherwise, the DAG Combiner may have proven that the value coming in is
1464 // either already zero or is not demanded. Check for known zero input bits.
1465 APInt NeededMask = DesiredMask & ~ActualMask;
1467 APInt KnownZero, KnownOne;
1468 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1470 // If all the missing bits in the or are already known to be set, match!
1471 if ((NeededMask & KnownOne) == NeededMask)
1474 // TODO: check to see if missing bits are just not demanded.
1476 // Otherwise, this pattern doesn't match.
1481 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1482 /// by tblgen. Others should not call it.
1483 void SelectionDAGISel::
1484 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1485 std::vector<SDValue> InOps;
1486 std::swap(InOps, Ops);
1488 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1489 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1490 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1491 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1493 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1494 if (InOps[e-1].getValueType() == MVT::Glue)
1495 --e; // Don't process a glue operand if it is here.
1498 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1499 if (!InlineAsm::isMemKind(Flags)) {
1500 // Just skip over this operand, copying the operands verbatim.
1501 Ops.insert(Ops.end(), InOps.begin()+i,
1502 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1503 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1505 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1506 "Memory operand with multiple values?");
1507 // Otherwise, this is a memory operand. Ask the target to select it.
1508 std::vector<SDValue> SelOps;
1509 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1510 report_fatal_error("Could not match memory address. Inline asm"
1513 // Add this to the output node.
1515 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1516 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1517 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1522 // Add the glue input back if present.
1523 if (e != InOps.size())
1524 Ops.push_back(InOps.back());
1527 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1530 static SDNode *findGlueUse(SDNode *N) {
1531 unsigned FlagResNo = N->getNumValues()-1;
1532 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1533 SDUse &Use = I.getUse();
1534 if (Use.getResNo() == FlagResNo)
1535 return Use.getUser();
1540 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1541 /// This function recursively traverses up the operand chain, ignoring
1543 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1544 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1545 bool IgnoreChains) {
1546 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1547 // greater than all of its (recursive) operands. If we scan to a point where
1548 // 'use' is smaller than the node we're scanning for, then we know we will
1551 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1552 // happen because we scan down to newly selected nodes in the case of glue
1554 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1557 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1558 // won't fail if we scan it again.
1559 if (!Visited.insert(Use))
1562 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1563 // Ignore chain uses, they are validated by HandleMergeInputChains.
1564 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1567 SDNode *N = Use->getOperand(i).getNode();
1569 if (Use == ImmedUse || Use == Root)
1570 continue; // We are not looking for immediate use.
1575 // Traverse up the operand chain.
1576 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1582 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1583 /// operand node N of U during instruction selection that starts at Root.
1584 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1585 SDNode *Root) const {
1586 if (OptLevel == CodeGenOpt::None) return false;
1587 return N.hasOneUse();
1590 /// IsLegalToFold - Returns true if the specific operand node N of
1591 /// U can be folded during instruction selection that starts at Root.
1592 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1593 CodeGenOpt::Level OptLevel,
1594 bool IgnoreChains) {
1595 if (OptLevel == CodeGenOpt::None) return false;
1597 // If Root use can somehow reach N through a path that that doesn't contain
1598 // U then folding N would create a cycle. e.g. In the following
1599 // diagram, Root can reach N through X. If N is folded into into Root, then
1600 // X is both a predecessor and a successor of U.
1611 // * indicates nodes to be folded together.
1613 // If Root produces glue, then it gets (even more) interesting. Since it
1614 // will be "glued" together with its glue use in the scheduler, we need to
1615 // check if it might reach N.
1634 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1635 // (call it Fold), then X is a predecessor of GU and a successor of
1636 // Fold. But since Fold and GU are glued together, this will create
1637 // a cycle in the scheduling graph.
1639 // If the node has glue, walk down the graph to the "lowest" node in the
1641 EVT VT = Root->getValueType(Root->getNumValues()-1);
1642 while (VT == MVT::Glue) {
1643 SDNode *GU = findGlueUse(Root);
1647 VT = Root->getValueType(Root->getNumValues()-1);
1649 // If our query node has a glue result with a use, we've walked up it. If
1650 // the user (which has already been selected) has a chain or indirectly uses
1651 // the chain, our WalkChainUsers predicate will not consider it. Because of
1652 // this, we cannot ignore chains in this predicate.
1653 IgnoreChains = false;
1657 SmallPtrSet<SDNode*, 16> Visited;
1658 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1661 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1662 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1663 SelectInlineAsmMemoryOperands(Ops);
1665 std::vector<EVT> VTs;
1666 VTs.push_back(MVT::Other);
1667 VTs.push_back(MVT::Glue);
1668 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1669 VTs, &Ops[0], Ops.size());
1671 return New.getNode();
1674 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1675 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1678 /// GetVBR - decode a vbr encoding whose top bit is set.
1679 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1680 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1681 assert(Val >= 128 && "Not a VBR");
1682 Val &= 127; // Remove first vbr bit.
1687 NextBits = MatcherTable[Idx++];
1688 Val |= (NextBits&127) << Shift;
1690 } while (NextBits & 128);
1696 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1697 /// interior glue and chain results to use the new glue and chain results.
1698 void SelectionDAGISel::
1699 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1700 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1702 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1703 bool isMorphNodeTo) {
1704 SmallVector<SDNode*, 4> NowDeadNodes;
1706 ISelUpdater ISU(ISelPosition);
1708 // Now that all the normal results are replaced, we replace the chain and
1709 // glue results if present.
1710 if (!ChainNodesMatched.empty()) {
1711 assert(InputChain.getNode() != 0 &&
1712 "Matched input chains but didn't produce a chain");
1713 // Loop over all of the nodes we matched that produced a chain result.
1714 // Replace all the chain results with the final chain we ended up with.
1715 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1716 SDNode *ChainNode = ChainNodesMatched[i];
1718 // If this node was already deleted, don't look at it.
1719 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1722 // Don't replace the results of the root node if we're doing a
1724 if (ChainNode == NodeToMatch && isMorphNodeTo)
1727 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1728 if (ChainVal.getValueType() == MVT::Glue)
1729 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1730 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1731 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1733 // If the node became dead and we haven't already seen it, delete it.
1734 if (ChainNode->use_empty() &&
1735 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1736 NowDeadNodes.push_back(ChainNode);
1740 // If the result produces glue, update any glue results in the matched
1741 // pattern with the glue result.
1742 if (InputGlue.getNode() != 0) {
1743 // Handle any interior nodes explicitly marked.
1744 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1745 SDNode *FRN = GlueResultNodesMatched[i];
1747 // If this node was already deleted, don't look at it.
1748 if (FRN->getOpcode() == ISD::DELETED_NODE)
1751 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1752 "Doesn't have a glue result");
1753 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1756 // If the node became dead and we haven't already seen it, delete it.
1757 if (FRN->use_empty() &&
1758 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1759 NowDeadNodes.push_back(FRN);
1763 if (!NowDeadNodes.empty())
1764 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1766 DEBUG(errs() << "ISEL: Match complete!\n");
1772 CR_LeadsToInteriorNode
1775 /// WalkChainUsers - Walk down the users of the specified chained node that is
1776 /// part of the pattern we're matching, looking at all of the users we find.
1777 /// This determines whether something is an interior node, whether we have a
1778 /// non-pattern node in between two pattern nodes (which prevent folding because
1779 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1780 /// between pattern nodes (in which case the TF becomes part of the pattern).
1782 /// The walk we do here is guaranteed to be small because we quickly get down to
1783 /// already selected nodes "below" us.
1785 WalkChainUsers(SDNode *ChainedNode,
1786 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1787 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1788 ChainResult Result = CR_Simple;
1790 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1791 E = ChainedNode->use_end(); UI != E; ++UI) {
1792 // Make sure the use is of the chain, not some other value we produce.
1793 if (UI.getUse().getValueType() != MVT::Other) continue;
1797 // If we see an already-selected machine node, then we've gone beyond the
1798 // pattern that we're selecting down into the already selected chunk of the
1800 if (User->isMachineOpcode() ||
1801 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1804 if (User->getOpcode() == ISD::CopyToReg ||
1805 User->getOpcode() == ISD::CopyFromReg ||
1806 User->getOpcode() == ISD::INLINEASM ||
1807 User->getOpcode() == ISD::EH_LABEL) {
1808 // If their node ID got reset to -1 then they've already been selected.
1809 // Treat them like a MachineOpcode.
1810 if (User->getNodeId() == -1)
1814 // If we have a TokenFactor, we handle it specially.
1815 if (User->getOpcode() != ISD::TokenFactor) {
1816 // If the node isn't a token factor and isn't part of our pattern, then it
1817 // must be a random chained node in between two nodes we're selecting.
1818 // This happens when we have something like:
1823 // Because we structurally match the load/store as a read/modify/write,
1824 // but the call is chained between them. We cannot fold in this case
1825 // because it would induce a cycle in the graph.
1826 if (!std::count(ChainedNodesInPattern.begin(),
1827 ChainedNodesInPattern.end(), User))
1828 return CR_InducesCycle;
1830 // Otherwise we found a node that is part of our pattern. For example in:
1834 // This would happen when we're scanning down from the load and see the
1835 // store as a user. Record that there is a use of ChainedNode that is
1836 // part of the pattern and keep scanning uses.
1837 Result = CR_LeadsToInteriorNode;
1838 InteriorChainedNodes.push_back(User);
1842 // If we found a TokenFactor, there are two cases to consider: first if the
1843 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1844 // uses of the TF are in our pattern) we just want to ignore it. Second,
1845 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1851 // | \ DAG's like cheese
1854 // [TokenFactor] [Op]
1861 // In this case, the TokenFactor becomes part of our match and we rewrite it
1862 // as a new TokenFactor.
1864 // To distinguish these two cases, do a recursive walk down the uses.
1865 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1867 // If the uses of the TokenFactor are just already-selected nodes, ignore
1868 // it, it is "below" our pattern.
1870 case CR_InducesCycle:
1871 // If the uses of the TokenFactor lead to nodes that are not part of our
1872 // pattern that are not selected, folding would turn this into a cycle,
1874 return CR_InducesCycle;
1875 case CR_LeadsToInteriorNode:
1876 break; // Otherwise, keep processing.
1879 // Okay, we know we're in the interesting interior case. The TokenFactor
1880 // is now going to be considered part of the pattern so that we rewrite its
1881 // uses (it may have uses that are not part of the pattern) with the
1882 // ultimate chain result of the generated code. We will also add its chain
1883 // inputs as inputs to the ultimate TokenFactor we create.
1884 Result = CR_LeadsToInteriorNode;
1885 ChainedNodesInPattern.push_back(User);
1886 InteriorChainedNodes.push_back(User);
1893 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1894 /// operation for when the pattern matched at least one node with a chains. The
1895 /// input vector contains a list of all of the chained nodes that we match. We
1896 /// must determine if this is a valid thing to cover (i.e. matching it won't
1897 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1898 /// be used as the input node chain for the generated nodes.
1900 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1901 SelectionDAG *CurDAG) {
1902 // Walk all of the chained nodes we've matched, recursively scanning down the
1903 // users of the chain result. This adds any TokenFactor nodes that are caught
1904 // in between chained nodes to the chained and interior nodes list.
1905 SmallVector<SDNode*, 3> InteriorChainedNodes;
1906 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1907 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1908 InteriorChainedNodes) == CR_InducesCycle)
1909 return SDValue(); // Would induce a cycle.
1912 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1913 // that we are interested in. Form our input TokenFactor node.
1914 SmallVector<SDValue, 3> InputChains;
1915 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1916 // Add the input chain of this node to the InputChains list (which will be
1917 // the operands of the generated TokenFactor) if it's not an interior node.
1918 SDNode *N = ChainNodesMatched[i];
1919 if (N->getOpcode() != ISD::TokenFactor) {
1920 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1923 // Otherwise, add the input chain.
1924 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1925 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1926 InputChains.push_back(InChain);
1930 // If we have a token factor, we want to add all inputs of the token factor
1931 // that are not part of the pattern we're matching.
1932 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1933 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1934 N->getOperand(op).getNode()))
1935 InputChains.push_back(N->getOperand(op));
1940 if (InputChains.size() == 1)
1941 return InputChains[0];
1942 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1943 MVT::Other, &InputChains[0], InputChains.size());
1946 /// MorphNode - Handle morphing a node in place for the selector.
1947 SDNode *SelectionDAGISel::
1948 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1949 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1950 // It is possible we're using MorphNodeTo to replace a node with no
1951 // normal results with one that has a normal result (or we could be
1952 // adding a chain) and the input could have glue and chains as well.
1953 // In this case we need to shift the operands down.
1954 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1955 // than the old isel though.
1956 int OldGlueResultNo = -1, OldChainResultNo = -1;
1958 unsigned NTMNumResults = Node->getNumValues();
1959 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1960 OldGlueResultNo = NTMNumResults-1;
1961 if (NTMNumResults != 1 &&
1962 Node->getValueType(NTMNumResults-2) == MVT::Other)
1963 OldChainResultNo = NTMNumResults-2;
1964 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1965 OldChainResultNo = NTMNumResults-1;
1967 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1968 // that this deletes operands of the old node that become dead.
1969 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1971 // MorphNodeTo can operate in two ways: if an existing node with the
1972 // specified operands exists, it can just return it. Otherwise, it
1973 // updates the node in place to have the requested operands.
1975 // If we updated the node in place, reset the node ID. To the isel,
1976 // this should be just like a newly allocated machine node.
1980 unsigned ResNumResults = Res->getNumValues();
1981 // Move the glue if needed.
1982 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1983 (unsigned)OldGlueResultNo != ResNumResults-1)
1984 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1985 SDValue(Res, ResNumResults-1));
1987 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1990 // Move the chain reference if needed.
1991 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1992 (unsigned)OldChainResultNo != ResNumResults-1)
1993 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1994 SDValue(Res, ResNumResults-1));
1996 // Otherwise, no replacement happened because the node already exists. Replace
1997 // Uses of the old node with the new one.
1999 CurDAG->ReplaceAllUsesWith(Node, Res);
2004 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2005 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2006 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2008 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2009 // Accept if it is exactly the same as a previously recorded node.
2010 unsigned RecNo = MatcherTable[MatcherIndex++];
2011 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2012 return N == RecordedNodes[RecNo].first;
2015 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2016 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2017 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2018 SelectionDAGISel &SDISel) {
2019 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2022 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2023 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2024 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2025 SelectionDAGISel &SDISel, SDNode *N) {
2026 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2029 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2030 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2032 uint16_t Opc = MatcherTable[MatcherIndex++];
2033 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2034 return N->getOpcode() == Opc;
2037 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2038 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2039 SDValue N, const TargetLowering &TLI) {
2040 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2041 if (N.getValueType() == VT) return true;
2043 // Handle the case when VT is iPTR.
2044 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2047 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2048 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2049 SDValue N, const TargetLowering &TLI,
2051 if (ChildNo >= N.getNumOperands())
2052 return false; // Match fails if out of range child #.
2053 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2057 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2058 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2060 return cast<CondCodeSDNode>(N)->get() ==
2061 (ISD::CondCode)MatcherTable[MatcherIndex++];
2064 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2065 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2066 SDValue N, const TargetLowering &TLI) {
2067 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2068 if (cast<VTSDNode>(N)->getVT() == VT)
2071 // Handle the case when VT is iPTR.
2072 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2075 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2076 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2078 int64_t Val = MatcherTable[MatcherIndex++];
2080 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2082 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2083 return C != 0 && C->getSExtValue() == Val;
2086 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2087 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2088 SDValue N, SelectionDAGISel &SDISel) {
2089 int64_t Val = MatcherTable[MatcherIndex++];
2091 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2093 if (N->getOpcode() != ISD::AND) return false;
2095 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2096 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2099 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2100 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2101 SDValue N, SelectionDAGISel &SDISel) {
2102 int64_t Val = MatcherTable[MatcherIndex++];
2104 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2106 if (N->getOpcode() != ISD::OR) return false;
2108 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2109 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2112 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2113 /// scope, evaluate the current node. If the current predicate is known to
2114 /// fail, set Result=true and return anything. If the current predicate is
2115 /// known to pass, set Result=false and return the MatcherIndex to continue
2116 /// with. If the current predicate is unknown, set Result=false and return the
2117 /// MatcherIndex to continue with.
2118 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2119 unsigned Index, SDValue N,
2120 bool &Result, SelectionDAGISel &SDISel,
2121 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2122 switch (Table[Index++]) {
2125 return Index-1; // Could not evaluate this predicate.
2126 case SelectionDAGISel::OPC_CheckSame:
2127 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2129 case SelectionDAGISel::OPC_CheckPatternPredicate:
2130 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2132 case SelectionDAGISel::OPC_CheckPredicate:
2133 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2135 case SelectionDAGISel::OPC_CheckOpcode:
2136 Result = !::CheckOpcode(Table, Index, N.getNode());
2138 case SelectionDAGISel::OPC_CheckType:
2139 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2141 case SelectionDAGISel::OPC_CheckChild0Type:
2142 case SelectionDAGISel::OPC_CheckChild1Type:
2143 case SelectionDAGISel::OPC_CheckChild2Type:
2144 case SelectionDAGISel::OPC_CheckChild3Type:
2145 case SelectionDAGISel::OPC_CheckChild4Type:
2146 case SelectionDAGISel::OPC_CheckChild5Type:
2147 case SelectionDAGISel::OPC_CheckChild6Type:
2148 case SelectionDAGISel::OPC_CheckChild7Type:
2149 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2150 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2152 case SelectionDAGISel::OPC_CheckCondCode:
2153 Result = !::CheckCondCode(Table, Index, N);
2155 case SelectionDAGISel::OPC_CheckValueType:
2156 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2158 case SelectionDAGISel::OPC_CheckInteger:
2159 Result = !::CheckInteger(Table, Index, N);
2161 case SelectionDAGISel::OPC_CheckAndImm:
2162 Result = !::CheckAndImm(Table, Index, N, SDISel);
2164 case SelectionDAGISel::OPC_CheckOrImm:
2165 Result = !::CheckOrImm(Table, Index, N, SDISel);
2173 /// FailIndex - If this match fails, this is the index to continue with.
2176 /// NodeStack - The node stack when the scope was formed.
2177 SmallVector<SDValue, 4> NodeStack;
2179 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2180 unsigned NumRecordedNodes;
2182 /// NumMatchedMemRefs - The number of matched memref entries.
2183 unsigned NumMatchedMemRefs;
2185 /// InputChain/InputGlue - The current chain/glue
2186 SDValue InputChain, InputGlue;
2188 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2189 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2194 SDNode *SelectionDAGISel::
2195 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2196 unsigned TableSize) {
2197 // FIXME: Should these even be selected? Handle these cases in the caller?
2198 switch (NodeToMatch->getOpcode()) {
2201 case ISD::EntryToken: // These nodes remain the same.
2202 case ISD::BasicBlock:
2204 //case ISD::VALUETYPE:
2205 //case ISD::CONDCODE:
2206 case ISD::HANDLENODE:
2207 case ISD::MDNODE_SDNODE:
2208 case ISD::TargetConstant:
2209 case ISD::TargetConstantFP:
2210 case ISD::TargetConstantPool:
2211 case ISD::TargetFrameIndex:
2212 case ISD::TargetExternalSymbol:
2213 case ISD::TargetBlockAddress:
2214 case ISD::TargetJumpTable:
2215 case ISD::TargetGlobalTLSAddress:
2216 case ISD::TargetGlobalAddress:
2217 case ISD::TokenFactor:
2218 case ISD::CopyFromReg:
2219 case ISD::CopyToReg:
2221 NodeToMatch->setNodeId(-1); // Mark selected.
2223 case ISD::AssertSext:
2224 case ISD::AssertZext:
2225 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2226 NodeToMatch->getOperand(0));
2228 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2229 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2232 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2234 // Set up the node stack with NodeToMatch as the only node on the stack.
2235 SmallVector<SDValue, 8> NodeStack;
2236 SDValue N = SDValue(NodeToMatch, 0);
2237 NodeStack.push_back(N);
2239 // MatchScopes - Scopes used when matching, if a match failure happens, this
2240 // indicates where to continue checking.
2241 SmallVector<MatchScope, 8> MatchScopes;
2243 // RecordedNodes - This is the set of nodes that have been recorded by the
2244 // state machine. The second value is the parent of the node, or null if the
2245 // root is recorded.
2246 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2248 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2250 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2252 // These are the current input chain and glue for use when generating nodes.
2253 // Various Emit operations change these. For example, emitting a copytoreg
2254 // uses and updates these.
2255 SDValue InputChain, InputGlue;
2257 // ChainNodesMatched - If a pattern matches nodes that have input/output
2258 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2259 // which ones they are. The result is captured into this list so that we can
2260 // update the chain results when the pattern is complete.
2261 SmallVector<SDNode*, 3> ChainNodesMatched;
2262 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2264 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2265 NodeToMatch->dump(CurDAG);
2268 // Determine where to start the interpreter. Normally we start at opcode #0,
2269 // but if the state machine starts with an OPC_SwitchOpcode, then we
2270 // accelerate the first lookup (which is guaranteed to be hot) with the
2271 // OpcodeOffset table.
2272 unsigned MatcherIndex = 0;
2274 if (!OpcodeOffset.empty()) {
2275 // Already computed the OpcodeOffset table, just index into it.
2276 if (N.getOpcode() < OpcodeOffset.size())
2277 MatcherIndex = OpcodeOffset[N.getOpcode()];
2278 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2280 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2281 // Otherwise, the table isn't computed, but the state machine does start
2282 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2283 // is the first time we're selecting an instruction.
2286 // Get the size of this case.
2287 unsigned CaseSize = MatcherTable[Idx++];
2289 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2290 if (CaseSize == 0) break;
2292 // Get the opcode, add the index to the table.
2293 uint16_t Opc = MatcherTable[Idx++];
2294 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2295 if (Opc >= OpcodeOffset.size())
2296 OpcodeOffset.resize((Opc+1)*2);
2297 OpcodeOffset[Opc] = Idx;
2301 // Okay, do the lookup for the first opcode.
2302 if (N.getOpcode() < OpcodeOffset.size())
2303 MatcherIndex = OpcodeOffset[N.getOpcode()];
2307 assert(MatcherIndex < TableSize && "Invalid index");
2309 unsigned CurrentOpcodeIndex = MatcherIndex;
2311 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2314 // Okay, the semantics of this operation are that we should push a scope
2315 // then evaluate the first child. However, pushing a scope only to have
2316 // the first check fail (which then pops it) is inefficient. If we can
2317 // determine immediately that the first check (or first several) will
2318 // immediately fail, don't even bother pushing a scope for them.
2322 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2323 if (NumToSkip & 128)
2324 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2325 // Found the end of the scope with no match.
2326 if (NumToSkip == 0) {
2331 FailIndex = MatcherIndex+NumToSkip;
2333 unsigned MatcherIndexOfPredicate = MatcherIndex;
2334 (void)MatcherIndexOfPredicate; // silence warning.
2336 // If we can't evaluate this predicate without pushing a scope (e.g. if
2337 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2338 // push the scope and evaluate the full predicate chain.
2340 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2341 Result, *this, RecordedNodes);
2345 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2346 << "index " << MatcherIndexOfPredicate
2347 << ", continuing at " << FailIndex << "\n");
2348 ++NumDAGIselRetries;
2350 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2351 // move to the next case.
2352 MatcherIndex = FailIndex;
2355 // If the whole scope failed to match, bail.
2356 if (FailIndex == 0) break;
2358 // Push a MatchScope which indicates where to go if the first child fails
2360 MatchScope NewEntry;
2361 NewEntry.FailIndex = FailIndex;
2362 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2363 NewEntry.NumRecordedNodes = RecordedNodes.size();
2364 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2365 NewEntry.InputChain = InputChain;
2366 NewEntry.InputGlue = InputGlue;
2367 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2368 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2369 MatchScopes.push_back(NewEntry);
2372 case OPC_RecordNode: {
2373 // Remember this node, it may end up being an operand in the pattern.
2375 if (NodeStack.size() > 1)
2376 Parent = NodeStack[NodeStack.size()-2].getNode();
2377 RecordedNodes.push_back(std::make_pair(N, Parent));
2381 case OPC_RecordChild0: case OPC_RecordChild1:
2382 case OPC_RecordChild2: case OPC_RecordChild3:
2383 case OPC_RecordChild4: case OPC_RecordChild5:
2384 case OPC_RecordChild6: case OPC_RecordChild7: {
2385 unsigned ChildNo = Opcode-OPC_RecordChild0;
2386 if (ChildNo >= N.getNumOperands())
2387 break; // Match fails if out of range child #.
2389 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2393 case OPC_RecordMemRef:
2394 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2397 case OPC_CaptureGlueInput:
2398 // If the current node has an input glue, capture it in InputGlue.
2399 if (N->getNumOperands() != 0 &&
2400 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2401 InputGlue = N->getOperand(N->getNumOperands()-1);
2404 case OPC_MoveChild: {
2405 unsigned ChildNo = MatcherTable[MatcherIndex++];
2406 if (ChildNo >= N.getNumOperands())
2407 break; // Match fails if out of range child #.
2408 N = N.getOperand(ChildNo);
2409 NodeStack.push_back(N);
2413 case OPC_MoveParent:
2414 // Pop the current node off the NodeStack.
2415 NodeStack.pop_back();
2416 assert(!NodeStack.empty() && "Node stack imbalance!");
2417 N = NodeStack.back();
2421 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2423 case OPC_CheckPatternPredicate:
2424 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2426 case OPC_CheckPredicate:
2427 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2431 case OPC_CheckComplexPat: {
2432 unsigned CPNum = MatcherTable[MatcherIndex++];
2433 unsigned RecNo = MatcherTable[MatcherIndex++];
2434 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2435 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2436 RecordedNodes[RecNo].first, CPNum,
2441 case OPC_CheckOpcode:
2442 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2446 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2449 case OPC_SwitchOpcode: {
2450 unsigned CurNodeOpcode = N.getOpcode();
2451 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2454 // Get the size of this case.
2455 CaseSize = MatcherTable[MatcherIndex++];
2457 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2458 if (CaseSize == 0) break;
2460 uint16_t Opc = MatcherTable[MatcherIndex++];
2461 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2463 // If the opcode matches, then we will execute this case.
2464 if (CurNodeOpcode == Opc)
2467 // Otherwise, skip over this case.
2468 MatcherIndex += CaseSize;
2471 // If no cases matched, bail out.
2472 if (CaseSize == 0) break;
2474 // Otherwise, execute the case we found.
2475 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2476 << " to " << MatcherIndex << "\n");
2480 case OPC_SwitchType: {
2481 MVT CurNodeVT = N.getValueType().getSimpleVT();
2482 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2485 // Get the size of this case.
2486 CaseSize = MatcherTable[MatcherIndex++];
2488 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2489 if (CaseSize == 0) break;
2491 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2492 if (CaseVT == MVT::iPTR)
2493 CaseVT = TLI.getPointerTy();
2495 // If the VT matches, then we will execute this case.
2496 if (CurNodeVT == CaseVT)
2499 // Otherwise, skip over this case.
2500 MatcherIndex += CaseSize;
2503 // If no cases matched, bail out.
2504 if (CaseSize == 0) break;
2506 // Otherwise, execute the case we found.
2507 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2508 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2511 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2512 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2513 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2514 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2515 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2516 Opcode-OPC_CheckChild0Type))
2519 case OPC_CheckCondCode:
2520 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2522 case OPC_CheckValueType:
2523 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2525 case OPC_CheckInteger:
2526 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2528 case OPC_CheckAndImm:
2529 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2531 case OPC_CheckOrImm:
2532 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2535 case OPC_CheckFoldableChainNode: {
2536 assert(NodeStack.size() != 1 && "No parent node");
2537 // Verify that all intermediate nodes between the root and this one have
2539 bool HasMultipleUses = false;
2540 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2541 if (!NodeStack[i].hasOneUse()) {
2542 HasMultipleUses = true;
2545 if (HasMultipleUses) break;
2547 // Check to see that the target thinks this is profitable to fold and that
2548 // we can fold it without inducing cycles in the graph.
2549 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2551 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2552 NodeToMatch, OptLevel,
2553 true/*We validate our own chains*/))
2558 case OPC_EmitInteger: {
2559 MVT::SimpleValueType VT =
2560 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2561 int64_t Val = MatcherTable[MatcherIndex++];
2563 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2564 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2565 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2568 case OPC_EmitRegister: {
2569 MVT::SimpleValueType VT =
2570 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2571 unsigned RegNo = MatcherTable[MatcherIndex++];
2572 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2573 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2576 case OPC_EmitRegister2: {
2577 // For targets w/ more than 256 register names, the register enum
2578 // values are stored in two bytes in the matcher table (just like
2580 MVT::SimpleValueType VT =
2581 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2582 unsigned RegNo = MatcherTable[MatcherIndex++];
2583 RegNo |= MatcherTable[MatcherIndex++] << 8;
2584 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2585 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2589 case OPC_EmitConvertToTarget: {
2590 // Convert from IMM/FPIMM to target version.
2591 unsigned RecNo = MatcherTable[MatcherIndex++];
2592 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2593 SDValue Imm = RecordedNodes[RecNo].first;
2595 if (Imm->getOpcode() == ISD::Constant) {
2596 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2597 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2598 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2599 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2600 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2603 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2607 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2608 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2609 // These are space-optimized forms of OPC_EmitMergeInputChains.
2610 assert(InputChain.getNode() == 0 &&
2611 "EmitMergeInputChains should be the first chain producing node");
2612 assert(ChainNodesMatched.empty() &&
2613 "Should only have one EmitMergeInputChains per match");
2615 // Read all of the chained nodes.
2616 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2617 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2618 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2620 // FIXME: What if other value results of the node have uses not matched
2622 if (ChainNodesMatched.back() != NodeToMatch &&
2623 !RecordedNodes[RecNo].first.hasOneUse()) {
2624 ChainNodesMatched.clear();
2628 // Merge the input chains if they are not intra-pattern references.
2629 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2631 if (InputChain.getNode() == 0)
2632 break; // Failed to merge.
2636 case OPC_EmitMergeInputChains: {
2637 assert(InputChain.getNode() == 0 &&
2638 "EmitMergeInputChains should be the first chain producing node");
2639 // This node gets a list of nodes we matched in the input that have
2640 // chains. We want to token factor all of the input chains to these nodes
2641 // together. However, if any of the input chains is actually one of the
2642 // nodes matched in this pattern, then we have an intra-match reference.
2643 // Ignore these because the newly token factored chain should not refer to
2645 unsigned NumChains = MatcherTable[MatcherIndex++];
2646 assert(NumChains != 0 && "Can't TF zero chains");
2648 assert(ChainNodesMatched.empty() &&
2649 "Should only have one EmitMergeInputChains per match");
2651 // Read all of the chained nodes.
2652 for (unsigned i = 0; i != NumChains; ++i) {
2653 unsigned RecNo = MatcherTable[MatcherIndex++];
2654 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2655 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2657 // FIXME: What if other value results of the node have uses not matched
2659 if (ChainNodesMatched.back() != NodeToMatch &&
2660 !RecordedNodes[RecNo].first.hasOneUse()) {
2661 ChainNodesMatched.clear();
2666 // If the inner loop broke out, the match fails.
2667 if (ChainNodesMatched.empty())
2670 // Merge the input chains if they are not intra-pattern references.
2671 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2673 if (InputChain.getNode() == 0)
2674 break; // Failed to merge.
2679 case OPC_EmitCopyToReg: {
2680 unsigned RecNo = MatcherTable[MatcherIndex++];
2681 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2682 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2684 if (InputChain.getNode() == 0)
2685 InputChain = CurDAG->getEntryNode();
2687 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2688 DestPhysReg, RecordedNodes[RecNo].first,
2691 InputGlue = InputChain.getValue(1);
2695 case OPC_EmitNodeXForm: {
2696 unsigned XFormNo = MatcherTable[MatcherIndex++];
2697 unsigned RecNo = MatcherTable[MatcherIndex++];
2698 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2699 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2700 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2705 case OPC_MorphNodeTo: {
2706 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2707 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2708 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2709 // Get the result VT list.
2710 unsigned NumVTs = MatcherTable[MatcherIndex++];
2711 SmallVector<EVT, 4> VTs;
2712 for (unsigned i = 0; i != NumVTs; ++i) {
2713 MVT::SimpleValueType VT =
2714 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2715 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2719 if (EmitNodeInfo & OPFL_Chain)
2720 VTs.push_back(MVT::Other);
2721 if (EmitNodeInfo & OPFL_GlueOutput)
2722 VTs.push_back(MVT::Glue);
2724 // This is hot code, so optimize the two most common cases of 1 and 2
2727 if (VTs.size() == 1)
2728 VTList = CurDAG->getVTList(VTs[0]);
2729 else if (VTs.size() == 2)
2730 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2732 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2734 // Get the operand list.
2735 unsigned NumOps = MatcherTable[MatcherIndex++];
2736 SmallVector<SDValue, 8> Ops;
2737 for (unsigned i = 0; i != NumOps; ++i) {
2738 unsigned RecNo = MatcherTable[MatcherIndex++];
2740 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2742 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2743 Ops.push_back(RecordedNodes[RecNo].first);
2746 // If there are variadic operands to add, handle them now.
2747 if (EmitNodeInfo & OPFL_VariadicInfo) {
2748 // Determine the start index to copy from.
2749 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2750 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2751 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2752 "Invalid variadic node");
2753 // Copy all of the variadic operands, not including a potential glue
2755 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2757 SDValue V = NodeToMatch->getOperand(i);
2758 if (V.getValueType() == MVT::Glue) break;
2763 // If this has chain/glue inputs, add them.
2764 if (EmitNodeInfo & OPFL_Chain)
2765 Ops.push_back(InputChain);
2766 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2767 Ops.push_back(InputGlue);
2771 if (Opcode != OPC_MorphNodeTo) {
2772 // If this is a normal EmitNode command, just create the new node and
2773 // add the results to the RecordedNodes list.
2774 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2775 VTList, Ops.data(), Ops.size());
2777 // Add all the non-glue/non-chain results to the RecordedNodes list.
2778 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2779 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2780 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2785 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2789 // If the node had chain/glue results, update our notion of the current
2791 if (EmitNodeInfo & OPFL_GlueOutput) {
2792 InputGlue = SDValue(Res, VTs.size()-1);
2793 if (EmitNodeInfo & OPFL_Chain)
2794 InputChain = SDValue(Res, VTs.size()-2);
2795 } else if (EmitNodeInfo & OPFL_Chain)
2796 InputChain = SDValue(Res, VTs.size()-1);
2798 // If the OPFL_MemRefs glue is set on this node, slap all of the
2799 // accumulated memrefs onto it.
2801 // FIXME: This is vastly incorrect for patterns with multiple outputs
2802 // instructions that access memory and for ComplexPatterns that match
2804 if (EmitNodeInfo & OPFL_MemRefs) {
2805 // Only attach load or store memory operands if the generated
2806 // instruction may load or store.
2807 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2808 bool mayLoad = MCID.mayLoad();
2809 bool mayStore = MCID.mayStore();
2811 unsigned NumMemRefs = 0;
2812 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2813 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2814 if ((*I)->isLoad()) {
2817 } else if ((*I)->isStore()) {
2825 MachineSDNode::mmo_iterator MemRefs =
2826 MF->allocateMemRefsArray(NumMemRefs);
2828 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2829 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2830 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2831 if ((*I)->isLoad()) {
2834 } else if ((*I)->isStore()) {
2842 cast<MachineSDNode>(Res)
2843 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2847 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2848 << " node: "; Res->dump(CurDAG); errs() << "\n");
2850 // If this was a MorphNodeTo then we're completely done!
2851 if (Opcode == OPC_MorphNodeTo) {
2852 // Update chain and glue uses.
2853 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2854 InputGlue, GlueResultNodesMatched, true);
2861 case OPC_MarkGlueResults: {
2862 unsigned NumNodes = MatcherTable[MatcherIndex++];
2864 // Read and remember all the glue-result nodes.
2865 for (unsigned i = 0; i != NumNodes; ++i) {
2866 unsigned RecNo = MatcherTable[MatcherIndex++];
2868 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2870 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2871 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2876 case OPC_CompleteMatch: {
2877 // The match has been completed, and any new nodes (if any) have been
2878 // created. Patch up references to the matched dag to use the newly
2880 unsigned NumResults = MatcherTable[MatcherIndex++];
2882 for (unsigned i = 0; i != NumResults; ++i) {
2883 unsigned ResSlot = MatcherTable[MatcherIndex++];
2885 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2887 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2888 SDValue Res = RecordedNodes[ResSlot].first;
2890 assert(i < NodeToMatch->getNumValues() &&
2891 NodeToMatch->getValueType(i) != MVT::Other &&
2892 NodeToMatch->getValueType(i) != MVT::Glue &&
2893 "Invalid number of results to complete!");
2894 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2895 NodeToMatch->getValueType(i) == MVT::iPTR ||
2896 Res.getValueType() == MVT::iPTR ||
2897 NodeToMatch->getValueType(i).getSizeInBits() ==
2898 Res.getValueType().getSizeInBits()) &&
2899 "invalid replacement");
2900 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2903 // If the root node defines glue, add it to the glue nodes to update list.
2904 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2905 GlueResultNodesMatched.push_back(NodeToMatch);
2907 // Update chain and glue uses.
2908 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2909 InputGlue, GlueResultNodesMatched, false);
2911 assert(NodeToMatch->use_empty() &&
2912 "Didn't replace all uses of the node?");
2914 // FIXME: We just return here, which interacts correctly with SelectRoot
2915 // above. We should fix this to not return an SDNode* anymore.
2920 // If the code reached this point, then the match failed. See if there is
2921 // another child to try in the current 'Scope', otherwise pop it until we
2922 // find a case to check.
2923 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2924 ++NumDAGIselRetries;
2926 if (MatchScopes.empty()) {
2927 CannotYetSelect(NodeToMatch);
2931 // Restore the interpreter state back to the point where the scope was
2933 MatchScope &LastScope = MatchScopes.back();
2934 RecordedNodes.resize(LastScope.NumRecordedNodes);
2936 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2937 N = NodeStack.back();
2939 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2940 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2941 MatcherIndex = LastScope.FailIndex;
2943 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2945 InputChain = LastScope.InputChain;
2946 InputGlue = LastScope.InputGlue;
2947 if (!LastScope.HasChainNodesMatched)
2948 ChainNodesMatched.clear();
2949 if (!LastScope.HasGlueResultNodesMatched)
2950 GlueResultNodesMatched.clear();
2952 // Check to see what the offset is at the new MatcherIndex. If it is zero
2953 // we have reached the end of this scope, otherwise we have another child
2954 // in the current scope to try.
2955 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2956 if (NumToSkip & 128)
2957 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2959 // If we have another child in this scope to match, update FailIndex and
2961 if (NumToSkip != 0) {
2962 LastScope.FailIndex = MatcherIndex+NumToSkip;
2966 // End of this scope, pop it and try the next child in the containing
2968 MatchScopes.pop_back();
2975 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2977 raw_string_ostream Msg(msg);
2978 Msg << "Cannot select: ";
2980 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2981 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2982 N->getOpcode() != ISD::INTRINSIC_VOID) {
2983 N->printrFull(Msg, CurDAG);
2985 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2987 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2988 if (iid < Intrinsic::num_intrinsics)
2989 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2990 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2991 Msg << "target intrinsic %" << TII->getName(iid);
2993 Msg << "unknown intrinsic #" << iid;
2995 report_fatal_error(Msg.str());
2998 char SelectionDAGISel::ID = 0;