1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/Timer.h"
53 EnableValueProp("enable-value-prop", cl::Hidden);
55 EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
60 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
61 cl::desc("Pop up a window to show dags before the first "
64 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
65 cl::desc("Pop up a window to show dags before legalize types"));
67 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
68 cl::desc("Pop up a window to show dags before legalize"));
70 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before the second "
74 ViewISelDAGs("view-isel-dags", cl::Hidden,
75 cl::desc("Pop up a window to show isel dags as they are selected"));
77 ViewSchedDAGs("view-sched-dags", cl::Hidden,
78 cl::desc("Pop up a window to show sched dags as they are processed"));
80 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
81 cl::desc("Pop up a window to show SUnit dags after they are processed"));
83 static const bool ViewDAGCombine1 = false,
84 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
85 ViewDAGCombine2 = false,
86 ViewISelDAGs = false, ViewSchedDAGs = false,
87 ViewSUnitDAGs = false;
90 //===---------------------------------------------------------------------===//
92 /// RegisterScheduler class - Track the registration of instruction schedulers.
94 //===---------------------------------------------------------------------===//
95 MachinePassRegistry RegisterScheduler::Registry;
97 //===---------------------------------------------------------------------===//
99 /// ISHeuristic command line option for instruction schedulers.
101 //===---------------------------------------------------------------------===//
102 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
103 RegisterPassParser<RegisterScheduler> >
104 ISHeuristic("pre-RA-sched",
105 cl::init(&createDefaultScheduler),
106 cl::desc("Instruction schedulers available (before register"
109 static RegisterScheduler
110 defaultListDAGScheduler("default", " Best scheduler for the target",
111 createDefaultScheduler);
113 namespace { struct SDISelAsmOperandInfo; }
115 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
116 /// insertvalue or extractvalue indices that identify a member, return
117 /// the linearized index of the start of the member.
119 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
120 const unsigned *Indices,
121 const unsigned *IndicesEnd,
122 unsigned CurIndex = 0) {
123 // Base case: We're done.
124 if (Indices && Indices == IndicesEnd)
127 // Given a struct type, recursively traverse the elements.
128 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
129 for (StructType::element_iterator EB = STy->element_begin(),
131 EE = STy->element_end();
133 if (Indices && *Indices == unsigned(EI - EB))
134 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
135 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
138 // Given an array type, recursively traverse the elements.
139 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
140 const Type *EltTy = ATy->getElementType();
141 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
142 if (Indices && *Indices == i)
143 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
144 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
147 // We haven't found the type we're looking for, so keep searching.
151 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
152 /// MVTs that represent all the individual underlying
153 /// non-aggregate types that comprise it.
155 /// If Offsets is non-null, it points to a vector to be filled in
156 /// with the in-memory offsets of each of the individual values.
158 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
159 SmallVectorImpl<MVT> &ValueVTs,
160 SmallVectorImpl<uint64_t> *Offsets = 0,
161 uint64_t StartingOffset = 0) {
162 // Given a struct type, recursively traverse the elements.
163 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
164 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
165 for (StructType::element_iterator EB = STy->element_begin(),
167 EE = STy->element_end();
169 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
170 StartingOffset + SL->getElementOffset(EI - EB));
173 // Given an array type, recursively traverse the elements.
174 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
175 const Type *EltTy = ATy->getElementType();
176 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
177 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
178 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
179 StartingOffset + i * EltSize);
182 // Base case: we can get an MVT for this LLVM IR type.
183 ValueVTs.push_back(TLI.getValueType(Ty));
185 Offsets->push_back(StartingOffset);
189 /// RegsForValue - This struct represents the registers (physical or virtual)
190 /// that a particular set of values is assigned, and the type information about
191 /// the value. The most common situation is to represent one value at a time,
192 /// but struct or array values are handled element-wise as multiple values.
193 /// The splitting of aggregates is performed recursively, so that we never
194 /// have aggregate-typed registers. The values at this point do not necessarily
195 /// have legal types, so each value may require one or more registers of some
198 struct VISIBILITY_HIDDEN RegsForValue {
199 /// TLI - The TargetLowering object.
201 const TargetLowering *TLI;
203 /// ValueVTs - The value types of the values, which may not be legal, and
204 /// may need be promoted or synthesized from one or more registers.
206 SmallVector<MVT, 4> ValueVTs;
208 /// RegVTs - The value types of the registers. This is the same size as
209 /// ValueVTs and it records, for each value, what the type of the assigned
210 /// register or registers are. (Individual values are never synthesized
211 /// from more than one type of register.)
213 /// With virtual registers, the contents of RegVTs is redundant with TLI's
214 /// getRegisterType member function, however when with physical registers
215 /// it is necessary to have a separate record of the types.
217 SmallVector<MVT, 4> RegVTs;
219 /// Regs - This list holds the registers assigned to the values.
220 /// Each legal or promoted value requires one register, and each
221 /// expanded value requires multiple registers.
223 SmallVector<unsigned, 4> Regs;
225 RegsForValue() : TLI(0) {}
227 RegsForValue(const TargetLowering &tli,
228 const SmallVector<unsigned, 4> ®s,
229 MVT regvt, MVT valuevt)
230 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
231 RegsForValue(const TargetLowering &tli,
232 const SmallVector<unsigned, 4> ®s,
233 const SmallVector<MVT, 4> ®vts,
234 const SmallVector<MVT, 4> &valuevts)
235 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
236 RegsForValue(const TargetLowering &tli,
237 unsigned Reg, const Type *Ty) : TLI(&tli) {
238 ComputeValueVTs(tli, Ty, ValueVTs);
240 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
241 MVT ValueVT = ValueVTs[Value];
242 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
243 MVT RegisterVT = TLI->getRegisterType(ValueVT);
244 for (unsigned i = 0; i != NumRegs; ++i)
245 Regs.push_back(Reg + i);
246 RegVTs.push_back(RegisterVT);
251 /// append - Add the specified values to this one.
252 void append(const RegsForValue &RHS) {
254 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
255 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
256 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
260 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
261 /// this value and returns the result as a ValueVTs value. This uses
262 /// Chain/Flag as the input and updates them for the output Chain/Flag.
263 /// If the Flag pointer is NULL, no flag is used.
264 SDValue getCopyFromRegs(SelectionDAG &DAG,
265 SDValue &Chain, SDValue *Flag) const;
267 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
268 /// specified value into the registers specified by this object. This uses
269 /// Chain/Flag as the input and updates them for the output Chain/Flag.
270 /// If the Flag pointer is NULL, no flag is used.
271 void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
272 SDValue &Chain, SDValue *Flag) const;
274 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
275 /// operand list. This adds the code marker and includes the number of
276 /// values added into it.
277 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
278 std::vector<SDValue> &Ops) const;
283 //===--------------------------------------------------------------------===//
284 /// createDefaultScheduler - This creates an instruction scheduler appropriate
286 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
288 MachineBasicBlock *BB,
290 TargetLowering &TLI = IS->getTargetLowering();
292 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
293 return createTDListDAGScheduler(IS, DAG, BB, Fast);
295 assert(TLI.getSchedulingPreference() ==
296 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
297 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
302 //===--------------------------------------------------------------------===//
303 /// FunctionLoweringInfo - This contains information that is global to a
304 /// function that is used when lowering a region of the function.
305 class FunctionLoweringInfo {
310 MachineRegisterInfo &RegInfo;
312 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
314 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
315 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
317 /// ValueMap - Since we emit code for the function a basic block at a time,
318 /// we must remember which virtual registers hold the values for
319 /// cross-basic-block values.
320 DenseMap<const Value*, unsigned> ValueMap;
322 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
323 /// the entry block. This allows the allocas to be efficiently referenced
324 /// anywhere in the function.
325 std::map<const AllocaInst*, int> StaticAllocaMap;
328 SmallSet<Instruction*, 8> CatchInfoLost;
329 SmallSet<Instruction*, 8> CatchInfoFound;
332 unsigned MakeReg(MVT VT) {
333 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
336 /// isExportedInst - Return true if the specified value is an instruction
337 /// exported from its block.
338 bool isExportedInst(const Value *V) {
339 return ValueMap.count(V);
342 unsigned CreateRegForValue(const Value *V);
344 unsigned InitializeRegForValue(const Value *V) {
345 unsigned &R = ValueMap[V];
346 assert(R == 0 && "Already initialized this value register!");
347 return R = CreateRegForValue(V);
351 unsigned NumSignBits;
352 APInt KnownOne, KnownZero;
353 LiveOutInfo() : NumSignBits(0) {}
356 /// LiveOutRegInfo - Information about live out vregs, indexed by their
357 /// register number offset by 'FirstVirtualRegister'.
358 std::vector<LiveOutInfo> LiveOutRegInfo;
362 /// isSelector - Return true if this instruction is a call to the
363 /// eh.selector intrinsic.
364 static bool isSelector(Instruction *I) {
365 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
366 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
367 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
371 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
372 /// PHI nodes or outside of the basic block that defines it, or used by a
373 /// switch or atomic instruction, which may expand to multiple basic blocks.
374 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
375 if (isa<PHINode>(I)) return true;
376 BasicBlock *BB = I->getParent();
377 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
378 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
379 // FIXME: Remove switchinst special case.
380 isa<SwitchInst>(*UI))
385 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
386 /// entry block, return true. This includes arguments used by switches, since
387 /// the switch may expand into multiple basic blocks.
388 static bool isOnlyUsedInEntryBlock(Argument *A) {
389 BasicBlock *Entry = A->getParent()->begin();
390 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
391 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
392 return false; // Use not in entry block.
396 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
397 Function &fn, MachineFunction &mf)
398 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
400 // Create a vreg for each argument register that is not dead and is used
401 // outside of the entry block for the function.
402 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
404 if (!isOnlyUsedInEntryBlock(AI))
405 InitializeRegForValue(AI);
407 // Initialize the mapping of values to registers. This is only set up for
408 // instruction values that are used outside of the block that defines
410 Function::iterator BB = Fn.begin(), EB = Fn.end();
411 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
412 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
413 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
414 const Type *Ty = AI->getAllocatedType();
415 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
417 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
420 TySize *= CUI->getZExtValue(); // Get total allocated size.
421 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
422 StaticAllocaMap[AI] =
423 MF.getFrameInfo()->CreateStackObject(TySize, Align);
426 for (; BB != EB; ++BB)
427 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
428 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
429 if (!isa<AllocaInst>(I) ||
430 !StaticAllocaMap.count(cast<AllocaInst>(I)))
431 InitializeRegForValue(I);
433 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
434 // also creates the initial PHI MachineInstrs, though none of the input
435 // operands are populated.
436 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
437 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
441 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
444 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
445 if (PN->use_empty()) continue;
447 MVT VT = TLI.getValueType(PN->getType());
448 unsigned NumRegisters = TLI.getNumRegisters(VT);
449 unsigned PHIReg = ValueMap[PN];
450 assert(PHIReg && "PHI node does not have an assigned virtual register!");
451 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
452 for (unsigned i = 0; i != NumRegisters; ++i)
453 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
458 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
459 /// the correctly promoted or expanded types. Assign these registers
460 /// consecutive vreg numbers and return the first assigned number.
462 /// In the case that the given value has struct or array type, this function
463 /// will assign registers for each member or element.
465 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
466 SmallVector<MVT, 4> ValueVTs;
467 ComputeValueVTs(TLI, V->getType(), ValueVTs);
469 unsigned FirstReg = 0;
470 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
471 MVT ValueVT = ValueVTs[Value];
472 MVT RegisterVT = TLI.getRegisterType(ValueVT);
474 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
475 for (unsigned i = 0; i != NumRegs; ++i) {
476 unsigned R = MakeReg(RegisterVT);
477 if (!FirstReg) FirstReg = R;
483 //===----------------------------------------------------------------------===//
484 /// SelectionDAGLowering - This is the common target-independent lowering
485 /// implementation that is parameterized by a TargetLowering object.
486 /// Also, targets can overload any lowering method.
489 class SelectionDAGLowering {
490 MachineBasicBlock *CurMBB;
492 DenseMap<const Value*, SDValue> NodeMap;
494 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
495 /// them up and then emit token factor nodes when possible. This allows us to
496 /// get simple disambiguation between loads without worrying about alias
498 SmallVector<SDValue, 8> PendingLoads;
500 /// PendingExports - CopyToReg nodes that copy values to virtual registers
501 /// for export to other blocks need to be emitted before any terminator
502 /// instruction, but they have no other ordering requirements. We bunch them
503 /// up and the emit a single tokenfactor for them just before terminator
505 std::vector<SDValue> PendingExports;
507 /// Case - A struct to record the Value for a switch case, and the
508 /// case's target basic block.
512 MachineBasicBlock* BB;
514 Case() : Low(0), High(0), BB(0) { }
515 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
516 Low(low), High(high), BB(bb) { }
517 uint64_t size() const {
518 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
519 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
520 return (rHigh - rLow + 1ULL);
526 MachineBasicBlock* BB;
529 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
530 Mask(mask), BB(bb), Bits(bits) { }
533 typedef std::vector<Case> CaseVector;
534 typedef std::vector<CaseBits> CaseBitsVector;
535 typedef CaseVector::iterator CaseItr;
536 typedef std::pair<CaseItr, CaseItr> CaseRange;
538 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
539 /// of conditional branches.
541 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
542 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
544 /// CaseBB - The MBB in which to emit the compare and branch
545 MachineBasicBlock *CaseBB;
546 /// LT, GE - If nonzero, we know the current case value must be less-than or
547 /// greater-than-or-equal-to these Constants.
550 /// Range - A pair of iterators representing the range of case values to be
551 /// processed at this point in the binary search tree.
555 typedef std::vector<CaseRec> CaseRecVector;
557 /// The comparison function for sorting the switch case values in the vector.
558 /// WARNING: Case ranges should be disjoint!
560 bool operator () (const Case& C1, const Case& C2) {
561 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
562 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
563 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
564 return CI1->getValue().slt(CI2->getValue());
569 bool operator () (const CaseBits& C1, const CaseBits& C2) {
570 return C1.Bits > C2.Bits;
574 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
577 // TLI - This is information that describes the available target features we
578 // need for lowering. This indicates when operations are unavailable,
579 // implemented with a libcall, etc.
582 const TargetData *TD;
585 /// SwitchCases - Vector of CaseBlock structures used to communicate
586 /// SwitchInst code generation information.
587 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
588 /// JTCases - Vector of JumpTable structures used to communicate
589 /// SwitchInst code generation information.
590 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
591 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
593 /// FuncInfo - Information about the function as a whole.
595 FunctionLoweringInfo &FuncInfo;
597 /// GCI - Garbage collection metadata for the function.
598 CollectorMetadata *GCI;
600 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
602 FunctionLoweringInfo &funcinfo,
603 CollectorMetadata *gci)
604 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
605 FuncInfo(funcinfo), GCI(gci) {
608 /// getRoot - Return the current virtual root of the Selection DAG,
609 /// flushing any PendingLoad items. This must be done before emitting
610 /// a store or any other node that may need to be ordered after any
611 /// prior load instructions.
614 if (PendingLoads.empty())
615 return DAG.getRoot();
617 if (PendingLoads.size() == 1) {
618 SDValue Root = PendingLoads[0];
620 PendingLoads.clear();
624 // Otherwise, we have to make a token factor node.
625 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
626 &PendingLoads[0], PendingLoads.size());
627 PendingLoads.clear();
632 /// getControlRoot - Similar to getRoot, but instead of flushing all the
633 /// PendingLoad items, flush all the PendingExports items. It is necessary
634 /// to do this before emitting a terminator instruction.
636 SDValue getControlRoot() {
637 SDValue Root = DAG.getRoot();
639 if (PendingExports.empty())
642 // Turn all of the CopyToReg chains into one factored node.
643 if (Root.getOpcode() != ISD::EntryToken) {
644 unsigned i = 0, e = PendingExports.size();
645 for (; i != e; ++i) {
646 assert(PendingExports[i].Val->getNumOperands() > 1);
647 if (PendingExports[i].Val->getOperand(0) == Root)
648 break; // Don't add the root if we already indirectly depend on it.
652 PendingExports.push_back(Root);
655 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
657 PendingExports.size());
658 PendingExports.clear();
663 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
665 void visit(Instruction &I) { visit(I.getOpcode(), I); }
667 void visit(unsigned Opcode, User &I) {
668 // Note: this doesn't use InstVisitor, because it has to work with
669 // ConstantExpr's in addition to instructions.
671 default: assert(0 && "Unknown instruction type encountered!");
673 // Build the switch statement using the Instruction.def file.
674 #define HANDLE_INST(NUM, OPCODE, CLASS) \
675 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
676 #include "llvm/Instruction.def"
680 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
682 SDValue getValue(const Value *V);
684 void setValue(const Value *V, SDValue NewN) {
685 SDValue &N = NodeMap[V];
686 assert(N.Val == 0 && "Already set a value for this node!");
690 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
691 std::set<unsigned> &OutputRegs,
692 std::set<unsigned> &InputRegs);
694 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
695 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
697 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
698 void ExportFromCurrentBlock(Value *V);
699 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
700 MachineBasicBlock *LandingPad = NULL);
702 // Terminator instructions.
703 void visitRet(ReturnInst &I);
704 void visitBr(BranchInst &I);
705 void visitSwitch(SwitchInst &I);
706 void visitUnreachable(UnreachableInst &I) { /* noop */ }
708 // Helpers for visitSwitch
709 bool handleSmallSwitchRange(CaseRec& CR,
710 CaseRecVector& WorkList,
712 MachineBasicBlock* Default);
713 bool handleJTSwitchCase(CaseRec& CR,
714 CaseRecVector& WorkList,
716 MachineBasicBlock* Default);
717 bool handleBTSplitSwitchCase(CaseRec& CR,
718 CaseRecVector& WorkList,
720 MachineBasicBlock* Default);
721 bool handleBitTestsSwitchCase(CaseRec& CR,
722 CaseRecVector& WorkList,
724 MachineBasicBlock* Default);
725 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
726 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
727 void visitBitTestCase(MachineBasicBlock* NextMBB,
729 SelectionDAGISel::BitTestCase &B);
730 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
731 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
732 SelectionDAGISel::JumpTableHeader &JTH);
734 // These all get lowered before this pass.
735 void visitInvoke(InvokeInst &I);
736 void visitUnwind(UnwindInst &I);
738 void visitBinary(User &I, unsigned OpCode);
739 void visitShift(User &I, unsigned Opcode);
740 void visitAdd(User &I) {
741 if (I.getType()->isFPOrFPVector())
742 visitBinary(I, ISD::FADD);
744 visitBinary(I, ISD::ADD);
746 void visitSub(User &I);
747 void visitMul(User &I) {
748 if (I.getType()->isFPOrFPVector())
749 visitBinary(I, ISD::FMUL);
751 visitBinary(I, ISD::MUL);
753 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
754 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
755 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
756 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
757 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
758 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
759 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
760 void visitOr (User &I) { visitBinary(I, ISD::OR); }
761 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
762 void visitShl (User &I) { visitShift(I, ISD::SHL); }
763 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
764 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
765 void visitICmp(User &I);
766 void visitFCmp(User &I);
767 void visitVICmp(User &I);
768 void visitVFCmp(User &I);
769 // Visit the conversion instructions
770 void visitTrunc(User &I);
771 void visitZExt(User &I);
772 void visitSExt(User &I);
773 void visitFPTrunc(User &I);
774 void visitFPExt(User &I);
775 void visitFPToUI(User &I);
776 void visitFPToSI(User &I);
777 void visitUIToFP(User &I);
778 void visitSIToFP(User &I);
779 void visitPtrToInt(User &I);
780 void visitIntToPtr(User &I);
781 void visitBitCast(User &I);
783 void visitExtractElement(User &I);
784 void visitInsertElement(User &I);
785 void visitShuffleVector(User &I);
787 void visitExtractValue(ExtractValueInst &I);
788 void visitInsertValue(InsertValueInst &I);
790 void visitGetElementPtr(User &I);
791 void visitSelect(User &I);
793 void visitMalloc(MallocInst &I);
794 void visitFree(FreeInst &I);
795 void visitAlloca(AllocaInst &I);
796 void visitLoad(LoadInst &I);
797 void visitStore(StoreInst &I);
798 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
799 void visitCall(CallInst &I);
800 void visitInlineAsm(CallSite CS);
801 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
802 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
804 void visitVAStart(CallInst &I);
805 void visitVAArg(VAArgInst &I);
806 void visitVAEnd(CallInst &I);
807 void visitVACopy(CallInst &I);
809 void visitUserOp1(Instruction &I) {
810 assert(0 && "UserOp1 should not exist at instruction selection time!");
813 void visitUserOp2(Instruction &I) {
814 assert(0 && "UserOp2 should not exist at instruction selection time!");
819 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
822 } // end namespace llvm
825 /// getCopyFromParts - Create a value that contains the specified legal parts
826 /// combined into the value they represent. If the parts combine to a type
827 /// larger then ValueVT then AssertOp can be used to specify whether the extra
828 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
829 /// (ISD::AssertSext).
830 static SDValue getCopyFromParts(SelectionDAG &DAG,
831 const SDValue *Parts,
835 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
836 assert(NumParts > 0 && "No parts to assemble!");
837 TargetLowering &TLI = DAG.getTargetLoweringInfo();
838 SDValue Val = Parts[0];
841 // Assemble the value from multiple parts.
842 if (!ValueVT.isVector()) {
843 unsigned PartBits = PartVT.getSizeInBits();
844 unsigned ValueBits = ValueVT.getSizeInBits();
846 // Assemble the power of 2 part.
847 unsigned RoundParts = NumParts & (NumParts - 1) ?
848 1 << Log2_32(NumParts) : NumParts;
849 unsigned RoundBits = PartBits * RoundParts;
850 MVT RoundVT = RoundBits == ValueBits ?
851 ValueVT : MVT::getIntegerVT(RoundBits);
854 if (RoundParts > 2) {
855 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
856 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
857 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
863 if (TLI.isBigEndian())
865 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
867 if (RoundParts < NumParts) {
868 // Assemble the trailing non-power-of-2 part.
869 unsigned OddParts = NumParts - RoundParts;
870 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
871 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
873 // Combine the round and odd parts.
875 if (TLI.isBigEndian())
877 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
878 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
879 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
880 DAG.getConstant(Lo.getValueType().getSizeInBits(),
881 TLI.getShiftAmountTy()));
882 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
883 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
886 // Handle a multi-element vector.
887 MVT IntermediateVT, RegisterVT;
888 unsigned NumIntermediates;
890 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
892 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
893 NumParts = NumRegs; // Silence a compiler warning.
894 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
895 assert(RegisterVT == Parts[0].getValueType() &&
896 "Part type doesn't match part!");
898 // Assemble the parts into intermediate operands.
899 SmallVector<SDValue, 8> Ops(NumIntermediates);
900 if (NumIntermediates == NumParts) {
901 // If the register was not expanded, truncate or copy the value,
903 for (unsigned i = 0; i != NumParts; ++i)
904 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
905 PartVT, IntermediateVT);
906 } else if (NumParts > 0) {
907 // If the intermediate type was expanded, build the intermediate operands
909 assert(NumParts % NumIntermediates == 0 &&
910 "Must expand into a divisible number of parts!");
911 unsigned Factor = NumParts / NumIntermediates;
912 for (unsigned i = 0; i != NumIntermediates; ++i)
913 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
914 PartVT, IntermediateVT);
917 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
919 Val = DAG.getNode(IntermediateVT.isVector() ?
920 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
921 ValueVT, &Ops[0], NumIntermediates);
925 // There is now one part, held in Val. Correct it to match ValueVT.
926 PartVT = Val.getValueType();
928 if (PartVT == ValueVT)
931 if (PartVT.isVector()) {
932 assert(ValueVT.isVector() && "Unknown vector conversion!");
933 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
936 if (ValueVT.isVector()) {
937 assert(ValueVT.getVectorElementType() == PartVT &&
938 ValueVT.getVectorNumElements() == 1 &&
939 "Only trivial scalar-to-vector conversions should get here!");
940 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
943 if (PartVT.isInteger() &&
944 ValueVT.isInteger()) {
945 if (ValueVT.bitsLT(PartVT)) {
946 // For a truncate, see if we have any information to
947 // indicate whether the truncated bits will always be
948 // zero or sign-extension.
949 if (AssertOp != ISD::DELETED_NODE)
950 Val = DAG.getNode(AssertOp, PartVT, Val,
951 DAG.getValueType(ValueVT));
952 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
954 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
958 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
959 if (ValueVT.bitsLT(Val.getValueType()))
960 // FP_ROUND's are always exact here.
961 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
962 DAG.getIntPtrConstant(1));
963 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
966 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
967 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
969 assert(0 && "Unknown mismatch!");
973 /// getCopyToParts - Create a series of nodes that contain the specified value
974 /// split into legal parts. If the parts contain more bits than Val, then, for
975 /// integers, ExtendKind can be used to specify how to generate the extra bits.
976 static void getCopyToParts(SelectionDAG &DAG,
981 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
982 TargetLowering &TLI = DAG.getTargetLoweringInfo();
983 MVT PtrVT = TLI.getPointerTy();
984 MVT ValueVT = Val.getValueType();
985 unsigned PartBits = PartVT.getSizeInBits();
986 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
991 if (!ValueVT.isVector()) {
992 if (PartVT == ValueVT) {
993 assert(NumParts == 1 && "No-op copy with multiple parts!");
998 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
999 // If the parts cover more bits than the value has, promote the value.
1000 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
1001 assert(NumParts == 1 && "Do not know what to promote to!");
1002 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
1003 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
1004 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1005 Val = DAG.getNode(ExtendKind, ValueVT, Val);
1007 assert(0 && "Unknown mismatch!");
1009 } else if (PartBits == ValueVT.getSizeInBits()) {
1010 // Different types of the same size.
1011 assert(NumParts == 1 && PartVT != ValueVT);
1012 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1013 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
1014 // If the parts cover less bits than value has, truncate the value.
1015 if (PartVT.isInteger() && ValueVT.isInteger()) {
1016 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1017 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1019 assert(0 && "Unknown mismatch!");
1023 // The value may have changed - recompute ValueVT.
1024 ValueVT = Val.getValueType();
1025 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
1026 "Failed to tile the value with PartVT!");
1028 if (NumParts == 1) {
1029 assert(PartVT == ValueVT && "Type conversion failed!");
1034 // Expand the value into multiple parts.
1035 if (NumParts & (NumParts - 1)) {
1036 // The number of parts is not a power of 2. Split off and copy the tail.
1037 assert(PartVT.isInteger() && ValueVT.isInteger() &&
1038 "Do not know what to expand to!");
1039 unsigned RoundParts = 1 << Log2_32(NumParts);
1040 unsigned RoundBits = RoundParts * PartBits;
1041 unsigned OddParts = NumParts - RoundParts;
1042 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
1043 DAG.getConstant(RoundBits,
1044 TLI.getShiftAmountTy()));
1045 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1046 if (TLI.isBigEndian())
1047 // The odd parts were reversed by getCopyToParts - unreverse them.
1048 std::reverse(Parts + RoundParts, Parts + NumParts);
1049 NumParts = RoundParts;
1050 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1051 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1054 // The number of parts is a power of 2. Repeatedly bisect the value using
1056 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
1057 MVT::getIntegerVT(ValueVT.getSizeInBits()),
1059 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1060 for (unsigned i = 0; i < NumParts; i += StepSize) {
1061 unsigned ThisBits = StepSize * PartBits / 2;
1062 MVT ThisVT = MVT::getIntegerVT (ThisBits);
1063 SDValue &Part0 = Parts[i];
1064 SDValue &Part1 = Parts[i+StepSize/2];
1066 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1067 DAG.getConstant(1, PtrVT));
1068 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1069 DAG.getConstant(0, PtrVT));
1071 if (ThisBits == PartBits && ThisVT != PartVT) {
1072 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1073 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1078 if (TLI.isBigEndian())
1079 std::reverse(Parts, Parts + NumParts);
1085 if (NumParts == 1) {
1086 if (PartVT != ValueVT) {
1087 if (PartVT.isVector()) {
1088 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1090 assert(ValueVT.getVectorElementType() == PartVT &&
1091 ValueVT.getVectorNumElements() == 1 &&
1092 "Only trivial vector-to-scalar conversions should get here!");
1093 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1094 DAG.getConstant(0, PtrVT));
1102 // Handle a multi-element vector.
1103 MVT IntermediateVT, RegisterVT;
1104 unsigned NumIntermediates;
1106 DAG.getTargetLoweringInfo()
1107 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1109 unsigned NumElements = ValueVT.getVectorNumElements();
1111 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1112 NumParts = NumRegs; // Silence a compiler warning.
1113 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1115 // Split the vector into intermediate operands.
1116 SmallVector<SDValue, 8> Ops(NumIntermediates);
1117 for (unsigned i = 0; i != NumIntermediates; ++i)
1118 if (IntermediateVT.isVector())
1119 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1120 IntermediateVT, Val,
1121 DAG.getConstant(i * (NumElements / NumIntermediates),
1124 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1125 IntermediateVT, Val,
1126 DAG.getConstant(i, PtrVT));
1128 // Split the intermediate operands into legal parts.
1129 if (NumParts == NumIntermediates) {
1130 // If the register was not expanded, promote or copy the value,
1132 for (unsigned i = 0; i != NumParts; ++i)
1133 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1134 } else if (NumParts > 0) {
1135 // If the intermediate type was expanded, split each the value into
1137 assert(NumParts % NumIntermediates == 0 &&
1138 "Must expand into a divisible number of parts!");
1139 unsigned Factor = NumParts / NumIntermediates;
1140 for (unsigned i = 0; i != NumIntermediates; ++i)
1141 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1146 SDValue SelectionDAGLowering::getValue(const Value *V) {
1147 SDValue &N = NodeMap[V];
1148 if (N.Val) return N;
1150 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1151 MVT VT = TLI.getValueType(V->getType(), true);
1153 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1154 return N = DAG.getConstant(CI->getValue(), VT);
1156 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1157 return N = DAG.getGlobalAddress(GV, VT);
1159 if (isa<ConstantPointerNull>(C))
1160 return N = DAG.getConstant(0, TLI.getPointerTy());
1162 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1163 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1165 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1166 !V->getType()->isAggregateType())
1167 return N = DAG.getNode(ISD::UNDEF, VT);
1169 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1170 visit(CE->getOpcode(), *CE);
1171 SDValue N1 = NodeMap[V];
1172 assert(N1.Val && "visit didn't populate the ValueMap!");
1176 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1177 SmallVector<SDValue, 4> Constants;
1178 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1180 SDNode *Val = getValue(*OI).Val;
1181 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1182 Constants.push_back(SDValue(Val, i));
1184 return DAG.getMergeValues(&Constants[0], Constants.size());
1187 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
1188 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1189 "Unknown struct or array constant!");
1191 SmallVector<MVT, 4> ValueVTs;
1192 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1193 unsigned NumElts = ValueVTs.size();
1195 return SDValue(); // empty struct
1196 SmallVector<SDValue, 4> Constants(NumElts);
1197 for (unsigned i = 0; i != NumElts; ++i) {
1198 MVT EltVT = ValueVTs[i];
1199 if (isa<UndefValue>(C))
1200 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1201 else if (EltVT.isFloatingPoint())
1202 Constants[i] = DAG.getConstantFP(0, EltVT);
1204 Constants[i] = DAG.getConstant(0, EltVT);
1206 return DAG.getMergeValues(&Constants[0], NumElts);
1209 const VectorType *VecTy = cast<VectorType>(V->getType());
1210 unsigned NumElements = VecTy->getNumElements();
1212 // Now that we know the number and type of the elements, get that number of
1213 // elements into the Ops array based on what kind of constant it is.
1214 SmallVector<SDValue, 16> Ops;
1215 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1216 for (unsigned i = 0; i != NumElements; ++i)
1217 Ops.push_back(getValue(CP->getOperand(i)));
1219 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1220 "Unknown vector constant!");
1221 MVT EltVT = TLI.getValueType(VecTy->getElementType());
1224 if (isa<UndefValue>(C))
1225 Op = DAG.getNode(ISD::UNDEF, EltVT);
1226 else if (EltVT.isFloatingPoint())
1227 Op = DAG.getConstantFP(0, EltVT);
1229 Op = DAG.getConstant(0, EltVT);
1230 Ops.assign(NumElements, Op);
1233 // Create a BUILD_VECTOR node.
1234 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1237 // If this is a static alloca, generate it as the frameindex instead of
1239 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1240 std::map<const AllocaInst*, int>::iterator SI =
1241 FuncInfo.StaticAllocaMap.find(AI);
1242 if (SI != FuncInfo.StaticAllocaMap.end())
1243 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1246 unsigned InReg = FuncInfo.ValueMap[V];
1247 assert(InReg && "Value not in map!");
1249 RegsForValue RFV(TLI, InReg, V->getType());
1250 SDValue Chain = DAG.getEntryNode();
1251 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1255 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1256 if (I.getNumOperands() == 0) {
1257 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1261 SmallVector<SDValue, 8> NewValues;
1262 NewValues.push_back(getControlRoot());
1263 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1264 SDValue RetOp = getValue(I.getOperand(i));
1266 SmallVector<MVT, 4> ValueVTs;
1267 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
1268 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
1269 MVT VT = ValueVTs[j];
1271 // FIXME: C calling convention requires the return type to be promoted to
1272 // at least 32-bit. But this is not necessary for non-C calling conventions.
1273 if (VT.isInteger()) {
1274 MVT MinVT = TLI.getRegisterType(MVT::i32);
1275 if (VT.bitsLT(MinVT))
1279 unsigned NumParts = TLI.getNumRegisters(VT);
1280 MVT PartVT = TLI.getRegisterType(VT);
1281 SmallVector<SDValue, 4> Parts(NumParts);
1282 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1284 const Function *F = I.getParent()->getParent();
1285 if (F->paramHasAttr(0, ParamAttr::SExt))
1286 ExtendKind = ISD::SIGN_EXTEND;
1287 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1288 ExtendKind = ISD::ZERO_EXTEND;
1290 getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j),
1291 &Parts[0], NumParts, PartVT, ExtendKind);
1293 for (unsigned i = 0; i < NumParts; ++i) {
1294 NewValues.push_back(Parts[i]);
1295 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1299 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1300 &NewValues[0], NewValues.size()));
1303 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1304 /// the current basic block, add it to ValueMap now so that we'll get a
1306 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1307 // No need to export constants.
1308 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1310 // Already exported?
1311 if (FuncInfo.isExportedInst(V)) return;
1313 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1314 CopyValueToVirtualRegister(V, Reg);
1317 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1318 const BasicBlock *FromBB) {
1319 // The operands of the setcc have to be in this block. We don't know
1320 // how to export them from some other block.
1321 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1322 // Can export from current BB.
1323 if (VI->getParent() == FromBB)
1326 // Is already exported, noop.
1327 return FuncInfo.isExportedInst(V);
1330 // If this is an argument, we can export it if the BB is the entry block or
1331 // if it is already exported.
1332 if (isa<Argument>(V)) {
1333 if (FromBB == &FromBB->getParent()->getEntryBlock())
1336 // Otherwise, can only export this if it is already exported.
1337 return FuncInfo.isExportedInst(V);
1340 // Otherwise, constants can always be exported.
1344 static bool InBlock(const Value *V, const BasicBlock *BB) {
1345 if (const Instruction *I = dyn_cast<Instruction>(V))
1346 return I->getParent() == BB;
1350 /// FindMergedConditions - If Cond is an expression like
1351 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1352 MachineBasicBlock *TBB,
1353 MachineBasicBlock *FBB,
1354 MachineBasicBlock *CurBB,
1356 // If this node is not part of the or/and tree, emit it as a branch.
1357 Instruction *BOp = dyn_cast<Instruction>(Cond);
1359 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1360 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1361 BOp->getParent() != CurBB->getBasicBlock() ||
1362 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1363 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1364 const BasicBlock *BB = CurBB->getBasicBlock();
1366 // If the leaf of the tree is a comparison, merge the condition into
1368 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1369 // The operands of the cmp have to be in this block. We don't know
1370 // how to export them from some other block. If this is the first block
1371 // of the sequence, no exporting is needed.
1373 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1374 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1375 BOp = cast<Instruction>(Cond);
1376 ISD::CondCode Condition;
1377 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1378 switch (IC->getPredicate()) {
1379 default: assert(0 && "Unknown icmp predicate opcode!");
1380 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1381 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1382 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1383 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1384 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1385 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1386 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1387 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1388 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1389 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1391 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1392 ISD::CondCode FPC, FOC;
1393 switch (FC->getPredicate()) {
1394 default: assert(0 && "Unknown fcmp predicate opcode!");
1395 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1396 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1397 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1398 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1399 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1400 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1401 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1402 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1403 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1404 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1405 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1406 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1407 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1408 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1409 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1410 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1412 if (FiniteOnlyFPMath())
1417 Condition = ISD::SETEQ; // silence warning.
1418 assert(0 && "Unknown compare instruction");
1421 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1422 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1423 SwitchCases.push_back(CB);
1427 // Create a CaseBlock record representing this branch.
1428 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1429 NULL, TBB, FBB, CurBB);
1430 SwitchCases.push_back(CB);
1435 // Create TmpBB after CurBB.
1436 MachineFunction::iterator BBI = CurBB;
1437 MachineFunction &MF = DAG.getMachineFunction();
1438 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1439 CurBB->getParent()->insert(++BBI, TmpBB);
1441 if (Opc == Instruction::Or) {
1442 // Codegen X | Y as:
1450 // Emit the LHS condition.
1451 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1453 // Emit the RHS condition into TmpBB.
1454 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1456 assert(Opc == Instruction::And && "Unknown merge op!");
1457 // Codegen X & Y as:
1464 // This requires creation of TmpBB after CurBB.
1466 // Emit the LHS condition.
1467 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1469 // Emit the RHS condition into TmpBB.
1470 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1474 /// If the set of cases should be emitted as a series of branches, return true.
1475 /// If we should emit this as a bunch of and/or'd together conditions, return
1478 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1479 if (Cases.size() != 2) return true;
1481 // If this is two comparisons of the same values or'd or and'd together, they
1482 // will get folded into a single comparison, so don't emit two blocks.
1483 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1484 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1485 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1486 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1493 void SelectionDAGLowering::visitBr(BranchInst &I) {
1494 // Update machine-CFG edges.
1495 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1497 // Figure out which block is immediately after the current one.
1498 MachineBasicBlock *NextBlock = 0;
1499 MachineFunction::iterator BBI = CurMBB;
1500 if (++BBI != CurMBB->getParent()->end())
1503 if (I.isUnconditional()) {
1504 // Update machine-CFG edges.
1505 CurMBB->addSuccessor(Succ0MBB);
1507 // If this is not a fall-through branch, emit the branch.
1508 if (Succ0MBB != NextBlock)
1509 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1510 DAG.getBasicBlock(Succ0MBB)));
1514 // If this condition is one of the special cases we handle, do special stuff
1516 Value *CondVal = I.getCondition();
1517 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1519 // If this is a series of conditions that are or'd or and'd together, emit
1520 // this as a sequence of branches instead of setcc's with and/or operations.
1521 // For example, instead of something like:
1534 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1535 if (BOp->hasOneUse() &&
1536 (BOp->getOpcode() == Instruction::And ||
1537 BOp->getOpcode() == Instruction::Or)) {
1538 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1539 // If the compares in later blocks need to use values not currently
1540 // exported from this block, export them now. This block should always
1541 // be the first entry.
1542 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1544 // Allow some cases to be rejected.
1545 if (ShouldEmitAsBranches(SwitchCases)) {
1546 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1547 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1548 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1551 // Emit the branch for this block.
1552 visitSwitchCase(SwitchCases[0]);
1553 SwitchCases.erase(SwitchCases.begin());
1557 // Okay, we decided not to do this, remove any inserted MBB's and clear
1559 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1560 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1562 SwitchCases.clear();
1566 // Create a CaseBlock record representing this branch.
1567 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1568 NULL, Succ0MBB, Succ1MBB, CurMBB);
1569 // Use visitSwitchCase to actually insert the fast branch sequence for this
1571 visitSwitchCase(CB);
1574 /// visitSwitchCase - Emits the necessary code to represent a single node in
1575 /// the binary search tree resulting from lowering a switch instruction.
1576 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1578 SDValue CondLHS = getValue(CB.CmpLHS);
1580 // Build the setcc now.
1581 if (CB.CmpMHS == NULL) {
1582 // Fold "(X == true)" to X and "(X == false)" to !X to
1583 // handle common cases produced by branch lowering.
1584 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1586 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1587 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1588 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1590 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1592 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1594 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1595 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1597 SDValue CmpOp = getValue(CB.CmpMHS);
1598 MVT VT = CmpOp.getValueType();
1600 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1601 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1603 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1604 Cond = DAG.getSetCC(MVT::i1, SUB,
1605 DAG.getConstant(High-Low, VT), ISD::SETULE);
1609 // Update successor info
1610 CurMBB->addSuccessor(CB.TrueBB);
1611 CurMBB->addSuccessor(CB.FalseBB);
1613 // Set NextBlock to be the MBB immediately after the current one, if any.
1614 // This is used to avoid emitting unnecessary branches to the next block.
1615 MachineBasicBlock *NextBlock = 0;
1616 MachineFunction::iterator BBI = CurMBB;
1617 if (++BBI != CurMBB->getParent()->end())
1620 // If the lhs block is the next block, invert the condition so that we can
1621 // fall through to the lhs instead of the rhs block.
1622 if (CB.TrueBB == NextBlock) {
1623 std::swap(CB.TrueBB, CB.FalseBB);
1624 SDValue True = DAG.getConstant(1, Cond.getValueType());
1625 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1627 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1628 DAG.getBasicBlock(CB.TrueBB));
1629 if (CB.FalseBB == NextBlock)
1630 DAG.setRoot(BrCond);
1632 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1633 DAG.getBasicBlock(CB.FalseBB)));
1636 /// visitJumpTable - Emit JumpTable node in the current MBB
1637 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1638 // Emit the code for the jump table
1639 assert(JT.Reg != -1U && "Should lower JT Header first!");
1640 MVT PTy = TLI.getPointerTy();
1641 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1642 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1643 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1648 /// visitJumpTableHeader - This function emits necessary code to produce index
1649 /// in the JumpTable from switch case.
1650 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1651 SelectionDAGISel::JumpTableHeader &JTH) {
1652 // Subtract the lowest switch case value from the value being switched on
1653 // and conditional branch to default mbb if the result is greater than the
1654 // difference between smallest and largest cases.
1655 SDValue SwitchOp = getValue(JTH.SValue);
1656 MVT VT = SwitchOp.getValueType();
1657 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1658 DAG.getConstant(JTH.First, VT));
1660 // The SDNode we just created, which holds the value being switched on
1661 // minus the the smallest case value, needs to be copied to a virtual
1662 // register so it can be used as an index into the jump table in a
1663 // subsequent basic block. This value may be smaller or larger than the
1664 // target's pointer type, and therefore require extension or truncating.
1665 if (VT.bitsGT(TLI.getPointerTy()))
1666 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1668 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1670 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1671 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1672 JT.Reg = JumpTableReg;
1674 // Emit the range check for the jump table, and branch to the default
1675 // block for the switch statement if the value being switched on exceeds
1676 // the largest case in the switch.
1677 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1678 DAG.getConstant(JTH.Last-JTH.First,VT),
1681 // Set NextBlock to be the MBB immediately after the current one, if any.
1682 // This is used to avoid emitting unnecessary branches to the next block.
1683 MachineBasicBlock *NextBlock = 0;
1684 MachineFunction::iterator BBI = CurMBB;
1685 if (++BBI != CurMBB->getParent()->end())
1688 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1689 DAG.getBasicBlock(JT.Default));
1691 if (JT.MBB == NextBlock)
1692 DAG.setRoot(BrCond);
1694 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1695 DAG.getBasicBlock(JT.MBB)));
1700 /// visitBitTestHeader - This function emits necessary code to produce value
1701 /// suitable for "bit tests"
1702 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1703 // Subtract the minimum value
1704 SDValue SwitchOp = getValue(B.SValue);
1705 MVT VT = SwitchOp.getValueType();
1706 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1707 DAG.getConstant(B.First, VT));
1710 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1711 DAG.getConstant(B.Range, VT),
1715 if (VT.bitsGT(TLI.getShiftAmountTy()))
1716 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1718 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1720 // Make desired shift
1721 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1722 DAG.getConstant(1, TLI.getPointerTy()),
1725 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1726 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1729 // Set NextBlock to be the MBB immediately after the current one, if any.
1730 // This is used to avoid emitting unnecessary branches to the next block.
1731 MachineBasicBlock *NextBlock = 0;
1732 MachineFunction::iterator BBI = CurMBB;
1733 if (++BBI != CurMBB->getParent()->end())
1736 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1738 CurMBB->addSuccessor(B.Default);
1739 CurMBB->addSuccessor(MBB);
1741 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1742 DAG.getBasicBlock(B.Default));
1744 if (MBB == NextBlock)
1745 DAG.setRoot(BrRange);
1747 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1748 DAG.getBasicBlock(MBB)));
1753 /// visitBitTestCase - this function produces one "bit test"
1754 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1756 SelectionDAGISel::BitTestCase &B) {
1757 // Emit bit tests and jumps
1758 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1759 TLI.getPointerTy());
1761 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1762 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1763 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1764 DAG.getConstant(0, TLI.getPointerTy()),
1767 CurMBB->addSuccessor(B.TargetBB);
1768 CurMBB->addSuccessor(NextMBB);
1770 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1771 AndCmp, DAG.getBasicBlock(B.TargetBB));
1773 // Set NextBlock to be the MBB immediately after the current one, if any.
1774 // This is used to avoid emitting unnecessary branches to the next block.
1775 MachineBasicBlock *NextBlock = 0;
1776 MachineFunction::iterator BBI = CurMBB;
1777 if (++BBI != CurMBB->getParent()->end())
1780 if (NextMBB == NextBlock)
1783 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1784 DAG.getBasicBlock(NextMBB)));
1789 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1790 // Retrieve successors.
1791 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1792 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1794 if (isa<InlineAsm>(I.getCalledValue()))
1797 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1799 // If the value of the invoke is used outside of its defining block, make it
1800 // available as a virtual register.
1801 if (!I.use_empty()) {
1802 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1803 if (VMI != FuncInfo.ValueMap.end())
1804 CopyValueToVirtualRegister(&I, VMI->second);
1807 // Update successor info
1808 CurMBB->addSuccessor(Return);
1809 CurMBB->addSuccessor(LandingPad);
1811 // Drop into normal successor.
1812 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1813 DAG.getBasicBlock(Return)));
1816 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1819 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1820 /// small case ranges).
1821 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1822 CaseRecVector& WorkList,
1824 MachineBasicBlock* Default) {
1825 Case& BackCase = *(CR.Range.second-1);
1827 // Size is the number of Cases represented by this range.
1828 unsigned Size = CR.Range.second - CR.Range.first;
1832 // Get the MachineFunction which holds the current MBB. This is used when
1833 // inserting any additional MBBs necessary to represent the switch.
1834 MachineFunction *CurMF = CurMBB->getParent();
1836 // Figure out which block is immediately after the current one.
1837 MachineBasicBlock *NextBlock = 0;
1838 MachineFunction::iterator BBI = CR.CaseBB;
1840 if (++BBI != CurMBB->getParent()->end())
1843 // TODO: If any two of the cases has the same destination, and if one value
1844 // is the same as the other, but has one bit unset that the other has set,
1845 // use bit manipulation to do two compares at once. For example:
1846 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1848 // Rearrange the case blocks so that the last one falls through if possible.
1849 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1850 // The last case block won't fall through into 'NextBlock' if we emit the
1851 // branches in this order. See if rearranging a case value would help.
1852 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1853 if (I->BB == NextBlock) {
1854 std::swap(*I, BackCase);
1860 // Create a CaseBlock record representing a conditional branch to
1861 // the Case's target mbb if the value being switched on SV is equal
1863 MachineBasicBlock *CurBlock = CR.CaseBB;
1864 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1865 MachineBasicBlock *FallThrough;
1867 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1868 CurMF->insert(BBI, FallThrough);
1870 // If the last case doesn't match, go to the default block.
1871 FallThrough = Default;
1874 Value *RHS, *LHS, *MHS;
1876 if (I->High == I->Low) {
1877 // This is just small small case range :) containing exactly 1 case
1879 LHS = SV; RHS = I->High; MHS = NULL;
1882 LHS = I->Low; MHS = SV; RHS = I->High;
1884 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1885 I->BB, FallThrough, CurBlock);
1887 // If emitting the first comparison, just call visitSwitchCase to emit the
1888 // code into the current block. Otherwise, push the CaseBlock onto the
1889 // vector to be later processed by SDISel, and insert the node's MBB
1890 // before the next MBB.
1891 if (CurBlock == CurMBB)
1892 visitSwitchCase(CB);
1894 SwitchCases.push_back(CB);
1896 CurBlock = FallThrough;
1902 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1903 return !DisableJumpTables &&
1904 (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1905 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1908 /// handleJTSwitchCase - Emit jumptable for current switch case range
1909 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1910 CaseRecVector& WorkList,
1912 MachineBasicBlock* Default) {
1913 Case& FrontCase = *CR.Range.first;
1914 Case& BackCase = *(CR.Range.second-1);
1916 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1917 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1920 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1924 if (!areJTsAllowed(TLI) || TSize <= 3)
1927 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1931 DOUT << "Lowering jump table\n"
1932 << "First entry: " << First << ". Last entry: " << Last << "\n"
1933 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1935 // Get the MachineFunction which holds the current MBB. This is used when
1936 // inserting any additional MBBs necessary to represent the switch.
1937 MachineFunction *CurMF = CurMBB->getParent();
1939 // Figure out which block is immediately after the current one.
1940 MachineBasicBlock *NextBlock = 0;
1941 MachineFunction::iterator BBI = CR.CaseBB;
1943 if (++BBI != CurMBB->getParent()->end())
1946 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1948 // Create a new basic block to hold the code for loading the address
1949 // of the jump table, and jumping to it. Update successor information;
1950 // we will either branch to the default case for the switch, or the jump
1952 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1953 CurMF->insert(BBI, JumpTableBB);
1954 CR.CaseBB->addSuccessor(Default);
1955 CR.CaseBB->addSuccessor(JumpTableBB);
1957 // Build a vector of destination BBs, corresponding to each target
1958 // of the jump table. If the value of the jump table slot corresponds to
1959 // a case statement, push the case's BB onto the vector, otherwise, push
1961 std::vector<MachineBasicBlock*> DestBBs;
1962 int64_t TEI = First;
1963 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1964 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1965 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1967 if ((Low <= TEI) && (TEI <= High)) {
1968 DestBBs.push_back(I->BB);
1972 DestBBs.push_back(Default);
1976 // Update successor info. Add one edge to each unique successor.
1977 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1978 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1979 E = DestBBs.end(); I != E; ++I) {
1980 if (!SuccsHandled[(*I)->getNumber()]) {
1981 SuccsHandled[(*I)->getNumber()] = true;
1982 JumpTableBB->addSuccessor(*I);
1986 // Create a jump table index for this jump table, or return an existing
1988 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1990 // Set the jump table information so that we can codegen it as a second
1991 // MachineBasicBlock
1992 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1993 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1994 (CR.CaseBB == CurMBB));
1995 if (CR.CaseBB == CurMBB)
1996 visitJumpTableHeader(JT, JTH);
1998 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
2003 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2005 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
2006 CaseRecVector& WorkList,
2008 MachineBasicBlock* Default) {
2009 // Get the MachineFunction which holds the current MBB. This is used when
2010 // inserting any additional MBBs necessary to represent the switch.
2011 MachineFunction *CurMF = CurMBB->getParent();
2013 // Figure out which block is immediately after the current one.
2014 MachineBasicBlock *NextBlock = 0;
2015 MachineFunction::iterator BBI = CR.CaseBB;
2017 if (++BBI != CurMBB->getParent()->end())
2020 Case& FrontCase = *CR.Range.first;
2021 Case& BackCase = *(CR.Range.second-1);
2022 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2024 // Size is the number of Cases represented by this range.
2025 unsigned Size = CR.Range.second - CR.Range.first;
2027 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2028 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2030 CaseItr Pivot = CR.Range.first + Size/2;
2032 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2033 // (heuristically) allow us to emit JumpTable's later.
2035 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2039 uint64_t LSize = FrontCase.size();
2040 uint64_t RSize = TSize-LSize;
2041 DOUT << "Selecting best pivot: \n"
2042 << "First: " << First << ", Last: " << Last <<"\n"
2043 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
2044 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2046 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2047 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
2048 assert((RBegin-LEnd>=1) && "Invalid case distance");
2049 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2050 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
2051 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
2052 // Should always split in some non-trivial place
2054 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2055 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2056 << "Metric: " << Metric << "\n";
2057 if (FMetric < Metric) {
2060 DOUT << "Current metric set to: " << FMetric << "\n";
2066 if (areJTsAllowed(TLI)) {
2067 // If our case is dense we *really* should handle it earlier!
2068 assert((FMetric > 0) && "Should handle dense range earlier!");
2070 Pivot = CR.Range.first + Size/2;
2073 CaseRange LHSR(CR.Range.first, Pivot);
2074 CaseRange RHSR(Pivot, CR.Range.second);
2075 Constant *C = Pivot->Low;
2076 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2078 // We know that we branch to the LHS if the Value being switched on is
2079 // less than the Pivot value, C. We use this to optimize our binary
2080 // tree a bit, by recognizing that if SV is greater than or equal to the
2081 // LHS's Case Value, and that Case Value is exactly one less than the
2082 // Pivot's Value, then we can branch directly to the LHS's Target,
2083 // rather than creating a leaf node for it.
2084 if ((LHSR.second - LHSR.first) == 1 &&
2085 LHSR.first->High == CR.GE &&
2086 cast<ConstantInt>(C)->getSExtValue() ==
2087 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2088 TrueBB = LHSR.first->BB;
2090 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2091 CurMF->insert(BBI, TrueBB);
2092 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2095 // Similar to the optimization above, if the Value being switched on is
2096 // known to be less than the Constant CR.LT, and the current Case Value
2097 // is CR.LT - 1, then we can branch directly to the target block for
2098 // the current Case Value, rather than emitting a RHS leaf node for it.
2099 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2100 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2101 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2102 FalseBB = RHSR.first->BB;
2104 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2105 CurMF->insert(BBI, FalseBB);
2106 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2109 // Create a CaseBlock record representing a conditional branch to
2110 // the LHS node if the value being switched on SV is less than C.
2111 // Otherwise, branch to LHS.
2112 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
2113 TrueBB, FalseBB, CR.CaseBB);
2115 if (CR.CaseBB == CurMBB)
2116 visitSwitchCase(CB);
2118 SwitchCases.push_back(CB);
2123 /// handleBitTestsSwitchCase - if current case range has few destination and
2124 /// range span less, than machine word bitwidth, encode case range into series
2125 /// of masks and emit bit tests with these masks.
2126 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2127 CaseRecVector& WorkList,
2129 MachineBasicBlock* Default){
2130 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
2132 Case& FrontCase = *CR.Range.first;
2133 Case& BackCase = *(CR.Range.second-1);
2135 // Get the MachineFunction which holds the current MBB. This is used when
2136 // inserting any additional MBBs necessary to represent the switch.
2137 MachineFunction *CurMF = CurMBB->getParent();
2139 unsigned numCmps = 0;
2140 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2142 // Single case counts one, case range - two.
2143 if (I->Low == I->High)
2149 // Count unique destinations
2150 SmallSet<MachineBasicBlock*, 4> Dests;
2151 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2152 Dests.insert(I->BB);
2153 if (Dests.size() > 3)
2154 // Don't bother the code below, if there are too much unique destinations
2157 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2158 << "Total number of comparisons: " << numCmps << "\n";
2160 // Compute span of values.
2161 Constant* minValue = FrontCase.Low;
2162 Constant* maxValue = BackCase.High;
2163 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2164 cast<ConstantInt>(minValue)->getSExtValue();
2165 DOUT << "Compare range: " << range << "\n"
2166 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2167 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2169 if (range>=IntPtrBits ||
2170 (!(Dests.size() == 1 && numCmps >= 3) &&
2171 !(Dests.size() == 2 && numCmps >= 5) &&
2172 !(Dests.size() >= 3 && numCmps >= 6)))
2175 DOUT << "Emitting bit tests\n";
2176 int64_t lowBound = 0;
2178 // Optimize the case where all the case values fit in a
2179 // word without having to subtract minValue. In this case,
2180 // we can optimize away the subtraction.
2181 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2182 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2183 range = cast<ConstantInt>(maxValue)->getSExtValue();
2185 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2188 CaseBitsVector CasesBits;
2189 unsigned i, count = 0;
2191 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2192 MachineBasicBlock* Dest = I->BB;
2193 for (i = 0; i < count; ++i)
2194 if (Dest == CasesBits[i].BB)
2198 assert((count < 3) && "Too much destinations to test!");
2199 CasesBits.push_back(CaseBits(0, Dest, 0));
2203 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2204 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2206 for (uint64_t j = lo; j <= hi; j++) {
2207 CasesBits[i].Mask |= 1ULL << j;
2208 CasesBits[i].Bits++;
2212 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2214 SelectionDAGISel::BitTestInfo BTC;
2216 // Figure out which block is immediately after the current one.
2217 MachineFunction::iterator BBI = CR.CaseBB;
2220 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2223 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2224 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2225 << ", BB: " << CasesBits[i].BB << "\n";
2227 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2228 CurMF->insert(BBI, CaseBB);
2229 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2234 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2235 -1U, (CR.CaseBB == CurMBB),
2236 CR.CaseBB, Default, BTC);
2238 if (CR.CaseBB == CurMBB)
2239 visitBitTestHeader(BTB);
2241 BitTestCases.push_back(BTB);
2247 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2248 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2249 const SwitchInst& SI) {
2250 unsigned numCmps = 0;
2252 // Start with "simple" cases
2253 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2254 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2255 Cases.push_back(Case(SI.getSuccessorValue(i),
2256 SI.getSuccessorValue(i),
2259 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2261 // Merge case into clusters
2262 if (Cases.size()>=2)
2263 // Must recompute end() each iteration because it may be
2264 // invalidated by erase if we hold on to it
2265 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2266 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2267 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2268 MachineBasicBlock* nextBB = J->BB;
2269 MachineBasicBlock* currentBB = I->BB;
2271 // If the two neighboring cases go to the same destination, merge them
2272 // into a single case.
2273 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2281 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2282 if (I->Low != I->High)
2283 // A range counts double, since it requires two compares.
2290 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2291 // Figure out which block is immediately after the current one.
2292 MachineBasicBlock *NextBlock = 0;
2293 MachineFunction::iterator BBI = CurMBB;
2295 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2297 // If there is only the default destination, branch to it if it is not the
2298 // next basic block. Otherwise, just fall through.
2299 if (SI.getNumOperands() == 2) {
2300 // Update machine-CFG edges.
2302 // If this is not a fall-through branch, emit the branch.
2303 CurMBB->addSuccessor(Default);
2304 if (Default != NextBlock)
2305 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2306 DAG.getBasicBlock(Default)));
2311 // If there are any non-default case statements, create a vector of Cases
2312 // representing each one, and sort the vector so that we can efficiently
2313 // create a binary search tree from them.
2315 unsigned numCmps = Clusterify(Cases, SI);
2316 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2317 << ". Total compares: " << numCmps << "\n";
2319 // Get the Value to be switched on and default basic blocks, which will be
2320 // inserted into CaseBlock records, representing basic blocks in the binary
2322 Value *SV = SI.getOperand(0);
2324 // Push the initial CaseRec onto the worklist
2325 CaseRecVector WorkList;
2326 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2328 while (!WorkList.empty()) {
2329 // Grab a record representing a case range to process off the worklist
2330 CaseRec CR = WorkList.back();
2331 WorkList.pop_back();
2333 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2336 // If the range has few cases (two or less) emit a series of specific
2338 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2341 // If the switch has more than 5 blocks, and at least 40% dense, and the
2342 // target supports indirect branches, then emit a jump table rather than
2343 // lowering the switch to a binary tree of conditional branches.
2344 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2347 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2348 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2349 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2354 void SelectionDAGLowering::visitSub(User &I) {
2355 // -0.0 - X --> fneg
2356 const Type *Ty = I.getType();
2357 if (isa<VectorType>(Ty)) {
2358 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2359 const VectorType *DestTy = cast<VectorType>(I.getType());
2360 const Type *ElTy = DestTy->getElementType();
2361 if (ElTy->isFloatingPoint()) {
2362 unsigned VL = DestTy->getNumElements();
2363 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2364 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2366 SDValue Op2 = getValue(I.getOperand(1));
2367 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2373 if (Ty->isFloatingPoint()) {
2374 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2375 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2376 SDValue Op2 = getValue(I.getOperand(1));
2377 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2382 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2385 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2386 SDValue Op1 = getValue(I.getOperand(0));
2387 SDValue Op2 = getValue(I.getOperand(1));
2389 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2392 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2393 SDValue Op1 = getValue(I.getOperand(0));
2394 SDValue Op2 = getValue(I.getOperand(1));
2395 if (!isa<VectorType>(I.getType())) {
2396 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2397 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2398 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2399 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2402 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2405 void SelectionDAGLowering::visitICmp(User &I) {
2406 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2407 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2408 predicate = IC->getPredicate();
2409 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2410 predicate = ICmpInst::Predicate(IC->getPredicate());
2411 SDValue Op1 = getValue(I.getOperand(0));
2412 SDValue Op2 = getValue(I.getOperand(1));
2413 ISD::CondCode Opcode;
2414 switch (predicate) {
2415 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2416 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2417 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2418 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2419 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2420 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2421 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2422 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2423 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2424 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2426 assert(!"Invalid ICmp predicate value");
2427 Opcode = ISD::SETEQ;
2430 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2433 void SelectionDAGLowering::visitFCmp(User &I) {
2434 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2435 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2436 predicate = FC->getPredicate();
2437 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2438 predicate = FCmpInst::Predicate(FC->getPredicate());
2439 SDValue Op1 = getValue(I.getOperand(0));
2440 SDValue Op2 = getValue(I.getOperand(1));
2441 ISD::CondCode Condition, FOC, FPC;
2442 switch (predicate) {
2443 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2444 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2445 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2446 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2447 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2448 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2449 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2450 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2451 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2452 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2453 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2454 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2455 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2456 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2457 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2458 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2460 assert(!"Invalid FCmp predicate value");
2461 FOC = FPC = ISD::SETFALSE;
2464 if (FiniteOnlyFPMath())
2468 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2471 void SelectionDAGLowering::visitVICmp(User &I) {
2472 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2473 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2474 predicate = IC->getPredicate();
2475 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2476 predicate = ICmpInst::Predicate(IC->getPredicate());
2477 SDValue Op1 = getValue(I.getOperand(0));
2478 SDValue Op2 = getValue(I.getOperand(1));
2479 ISD::CondCode Opcode;
2480 switch (predicate) {
2481 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2482 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2483 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2484 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2485 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2486 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2487 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2488 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2489 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2490 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2492 assert(!"Invalid ICmp predicate value");
2493 Opcode = ISD::SETEQ;
2496 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2499 void SelectionDAGLowering::visitVFCmp(User &I) {
2500 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2501 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2502 predicate = FC->getPredicate();
2503 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2504 predicate = FCmpInst::Predicate(FC->getPredicate());
2505 SDValue Op1 = getValue(I.getOperand(0));
2506 SDValue Op2 = getValue(I.getOperand(1));
2507 ISD::CondCode Condition, FOC, FPC;
2508 switch (predicate) {
2509 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2510 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2511 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2512 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2513 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2514 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2515 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2516 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2517 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2518 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2519 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2520 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2521 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2522 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2523 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2524 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2526 assert(!"Invalid VFCmp predicate value");
2527 FOC = FPC = ISD::SETFALSE;
2530 if (FiniteOnlyFPMath())
2535 MVT DestVT = TLI.getValueType(I.getType());
2537 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2540 void SelectionDAGLowering::visitSelect(User &I) {
2541 SDValue Cond = getValue(I.getOperand(0));
2542 SDValue TrueVal = getValue(I.getOperand(1));
2543 SDValue FalseVal = getValue(I.getOperand(2));
2544 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2545 TrueVal, FalseVal));
2549 void SelectionDAGLowering::visitTrunc(User &I) {
2550 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2551 SDValue N = getValue(I.getOperand(0));
2552 MVT DestVT = TLI.getValueType(I.getType());
2553 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2556 void SelectionDAGLowering::visitZExt(User &I) {
2557 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2558 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2559 SDValue N = getValue(I.getOperand(0));
2560 MVT DestVT = TLI.getValueType(I.getType());
2561 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2564 void SelectionDAGLowering::visitSExt(User &I) {
2565 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2566 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2567 SDValue N = getValue(I.getOperand(0));
2568 MVT DestVT = TLI.getValueType(I.getType());
2569 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2572 void SelectionDAGLowering::visitFPTrunc(User &I) {
2573 // FPTrunc is never a no-op cast, no need to check
2574 SDValue N = getValue(I.getOperand(0));
2575 MVT DestVT = TLI.getValueType(I.getType());
2576 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2579 void SelectionDAGLowering::visitFPExt(User &I){
2580 // FPTrunc is never a no-op cast, no need to check
2581 SDValue N = getValue(I.getOperand(0));
2582 MVT DestVT = TLI.getValueType(I.getType());
2583 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2586 void SelectionDAGLowering::visitFPToUI(User &I) {
2587 // FPToUI is never a no-op cast, no need to check
2588 SDValue N = getValue(I.getOperand(0));
2589 MVT DestVT = TLI.getValueType(I.getType());
2590 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2593 void SelectionDAGLowering::visitFPToSI(User &I) {
2594 // FPToSI is never a no-op cast, no need to check
2595 SDValue N = getValue(I.getOperand(0));
2596 MVT DestVT = TLI.getValueType(I.getType());
2597 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2600 void SelectionDAGLowering::visitUIToFP(User &I) {
2601 // UIToFP is never a no-op cast, no need to check
2602 SDValue N = getValue(I.getOperand(0));
2603 MVT DestVT = TLI.getValueType(I.getType());
2604 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2607 void SelectionDAGLowering::visitSIToFP(User &I){
2608 // UIToFP is never a no-op cast, no need to check
2609 SDValue N = getValue(I.getOperand(0));
2610 MVT DestVT = TLI.getValueType(I.getType());
2611 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2614 void SelectionDAGLowering::visitPtrToInt(User &I) {
2615 // What to do depends on the size of the integer and the size of the pointer.
2616 // We can either truncate, zero extend, or no-op, accordingly.
2617 SDValue N = getValue(I.getOperand(0));
2618 MVT SrcVT = N.getValueType();
2619 MVT DestVT = TLI.getValueType(I.getType());
2621 if (DestVT.bitsLT(SrcVT))
2622 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2624 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2625 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2626 setValue(&I, Result);
2629 void SelectionDAGLowering::visitIntToPtr(User &I) {
2630 // What to do depends on the size of the integer and the size of the pointer.
2631 // We can either truncate, zero extend, or no-op, accordingly.
2632 SDValue N = getValue(I.getOperand(0));
2633 MVT SrcVT = N.getValueType();
2634 MVT DestVT = TLI.getValueType(I.getType());
2635 if (DestVT.bitsLT(SrcVT))
2636 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2638 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2639 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2642 void SelectionDAGLowering::visitBitCast(User &I) {
2643 SDValue N = getValue(I.getOperand(0));
2644 MVT DestVT = TLI.getValueType(I.getType());
2646 // BitCast assures us that source and destination are the same size so this
2647 // is either a BIT_CONVERT or a no-op.
2648 if (DestVT != N.getValueType())
2649 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2651 setValue(&I, N); // noop cast.
2654 void SelectionDAGLowering::visitInsertElement(User &I) {
2655 SDValue InVec = getValue(I.getOperand(0));
2656 SDValue InVal = getValue(I.getOperand(1));
2657 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2658 getValue(I.getOperand(2)));
2660 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2661 TLI.getValueType(I.getType()),
2662 InVec, InVal, InIdx));
2665 void SelectionDAGLowering::visitExtractElement(User &I) {
2666 SDValue InVec = getValue(I.getOperand(0));
2667 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2668 getValue(I.getOperand(1)));
2669 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2670 TLI.getValueType(I.getType()), InVec, InIdx));
2673 void SelectionDAGLowering::visitShuffleVector(User &I) {
2674 SDValue V1 = getValue(I.getOperand(0));
2675 SDValue V2 = getValue(I.getOperand(1));
2676 SDValue Mask = getValue(I.getOperand(2));
2678 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2679 TLI.getValueType(I.getType()),
2683 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2684 const Value *Op0 = I.getOperand(0);
2685 const Value *Op1 = I.getOperand(1);
2686 const Type *AggTy = I.getType();
2687 const Type *ValTy = Op1->getType();
2688 bool IntoUndef = isa<UndefValue>(Op0);
2689 bool FromUndef = isa<UndefValue>(Op1);
2691 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2692 I.idx_begin(), I.idx_end());
2694 SmallVector<MVT, 4> AggValueVTs;
2695 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2696 SmallVector<MVT, 4> ValValueVTs;
2697 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2699 unsigned NumAggValues = AggValueVTs.size();
2700 unsigned NumValValues = ValValueVTs.size();
2701 SmallVector<SDValue, 4> Values(NumAggValues);
2703 SDValue Agg = getValue(Op0);
2704 SDValue Val = getValue(Op1);
2706 // Copy the beginning value(s) from the original aggregate.
2707 for (; i != LinearIndex; ++i)
2708 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2709 SDValue(Agg.Val, Agg.ResNo + i);
2710 // Copy values from the inserted value(s).
2711 for (; i != LinearIndex + NumValValues; ++i)
2712 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2713 SDValue(Val.Val, Val.ResNo + i - LinearIndex);
2714 // Copy remaining value(s) from the original aggregate.
2715 for (; i != NumAggValues; ++i)
2716 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2717 SDValue(Agg.Val, Agg.ResNo + i);
2719 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2720 &Values[0], NumAggValues));
2723 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2724 const Value *Op0 = I.getOperand(0);
2725 const Type *AggTy = Op0->getType();
2726 const Type *ValTy = I.getType();
2727 bool OutOfUndef = isa<UndefValue>(Op0);
2729 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2730 I.idx_begin(), I.idx_end());
2732 SmallVector<MVT, 4> ValValueVTs;
2733 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2735 unsigned NumValValues = ValValueVTs.size();
2736 SmallVector<SDValue, 4> Values(NumValValues);
2738 SDValue Agg = getValue(Op0);
2739 // Copy out the selected value(s).
2740 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2741 Values[i - LinearIndex] =
2742 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
2743 SDValue(Agg.Val, Agg.ResNo + i);
2745 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2746 &Values[0], NumValValues));
2750 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2751 SDValue N = getValue(I.getOperand(0));
2752 const Type *Ty = I.getOperand(0)->getType();
2754 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2757 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2758 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2761 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2762 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2763 DAG.getIntPtrConstant(Offset));
2765 Ty = StTy->getElementType(Field);
2767 Ty = cast<SequentialType>(Ty)->getElementType();
2769 // If this is a constant subscript, handle it quickly.
2770 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2771 if (CI->getZExtValue() == 0) continue;
2773 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2774 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2775 DAG.getIntPtrConstant(Offs));
2779 // N = N + Idx * ElementSize;
2780 uint64_t ElementSize = TD->getABITypeSize(Ty);
2781 SDValue IdxN = getValue(Idx);
2783 // If the index is smaller or larger than intptr_t, truncate or extend
2785 if (IdxN.getValueType().bitsLT(N.getValueType())) {
2786 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2787 } else if (IdxN.getValueType().bitsGT(N.getValueType()))
2788 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2790 // If this is a multiply by a power of two, turn it into a shl
2791 // immediately. This is a very common case.
2792 if (isPowerOf2_64(ElementSize)) {
2793 unsigned Amt = Log2_64(ElementSize);
2794 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2795 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2796 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2800 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2801 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2802 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2808 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2809 // If this is a fixed sized alloca in the entry block of the function,
2810 // allocate it statically on the stack.
2811 if (FuncInfo.StaticAllocaMap.count(&I))
2812 return; // getValue will auto-populate this.
2814 const Type *Ty = I.getAllocatedType();
2815 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2817 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2820 SDValue AllocSize = getValue(I.getArraySize());
2821 MVT IntPtr = TLI.getPointerTy();
2822 if (IntPtr.bitsLT(AllocSize.getValueType()))
2823 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2824 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2825 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2827 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2828 DAG.getIntPtrConstant(TySize));
2830 // Handle alignment. If the requested alignment is less than or equal to
2831 // the stack alignment, ignore it. If the size is greater than or equal to
2832 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2833 unsigned StackAlign =
2834 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2835 if (Align <= StackAlign)
2838 // Round the size of the allocation up to the stack alignment size
2839 // by add SA-1 to the size.
2840 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2841 DAG.getIntPtrConstant(StackAlign-1));
2842 // Mask out the low bits for alignment purposes.
2843 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2844 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2846 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2847 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2849 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2851 DAG.setRoot(DSA.getValue(1));
2853 // Inform the Frame Information that we have just allocated a variable-sized
2855 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2858 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2859 const Value *SV = I.getOperand(0);
2860 SDValue Ptr = getValue(SV);
2862 const Type *Ty = I.getType();
2863 bool isVolatile = I.isVolatile();
2864 unsigned Alignment = I.getAlignment();
2866 SmallVector<MVT, 4> ValueVTs;
2867 SmallVector<uint64_t, 4> Offsets;
2868 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2869 unsigned NumValues = ValueVTs.size();
2874 bool ConstantMemory = false;
2876 // Serialize volatile loads with other side effects.
2878 else if (AA.pointsToConstantMemory(SV)) {
2879 // Do not serialize (non-volatile) loads of constant memory with anything.
2880 Root = DAG.getEntryNode();
2881 ConstantMemory = true;
2883 // Do not serialize non-volatile loads against each other.
2884 Root = DAG.getRoot();
2887 SmallVector<SDValue, 4> Values(NumValues);
2888 SmallVector<SDValue, 4> Chains(NumValues);
2889 MVT PtrVT = Ptr.getValueType();
2890 for (unsigned i = 0; i != NumValues; ++i) {
2891 SDValue L = DAG.getLoad(ValueVTs[i], Root,
2892 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2893 DAG.getConstant(Offsets[i], PtrVT)),
2895 isVolatile, Alignment);
2897 Chains[i] = L.getValue(1);
2900 if (!ConstantMemory) {
2901 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2902 &Chains[0], NumValues);
2906 PendingLoads.push_back(Chain);
2909 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2910 &Values[0], NumValues));
2914 void SelectionDAGLowering::visitStore(StoreInst &I) {
2915 Value *SrcV = I.getOperand(0);
2916 Value *PtrV = I.getOperand(1);
2918 SmallVector<MVT, 4> ValueVTs;
2919 SmallVector<uint64_t, 4> Offsets;
2920 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2921 unsigned NumValues = ValueVTs.size();
2925 // Get the lowered operands. Note that we do this after
2926 // checking if NumResults is zero, because with zero results
2927 // the operands won't have values in the map.
2928 SDValue Src = getValue(SrcV);
2929 SDValue Ptr = getValue(PtrV);
2931 SDValue Root = getRoot();
2932 SmallVector<SDValue, 4> Chains(NumValues);
2933 MVT PtrVT = Ptr.getValueType();
2934 bool isVolatile = I.isVolatile();
2935 unsigned Alignment = I.getAlignment();
2936 for (unsigned i = 0; i != NumValues; ++i)
2937 Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i),
2938 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2939 DAG.getConstant(Offsets[i], PtrVT)),
2941 isVolatile, Alignment);
2943 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2946 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2948 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2949 unsigned Intrinsic) {
2950 bool HasChain = !I.doesNotAccessMemory();
2951 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2953 // Build the operand list.
2954 SmallVector<SDValue, 8> Ops;
2955 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2957 // We don't need to serialize loads against other loads.
2958 Ops.push_back(DAG.getRoot());
2960 Ops.push_back(getRoot());
2964 // Add the intrinsic ID as an integer operand.
2965 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2967 // Add all operands of the call to the operand list.
2968 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2969 SDValue Op = getValue(I.getOperand(i));
2970 assert(TLI.isTypeLegal(Op.getValueType()) &&
2971 "Intrinsic uses a non-legal type?");
2975 std::vector<MVT> VTs;
2976 if (I.getType() != Type::VoidTy) {
2977 MVT VT = TLI.getValueType(I.getType());
2978 if (VT.isVector()) {
2979 const VectorType *DestTy = cast<VectorType>(I.getType());
2980 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2982 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2983 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2986 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2990 VTs.push_back(MVT::Other);
2992 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2997 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2998 &Ops[0], Ops.size());
2999 else if (I.getType() != Type::VoidTy)
3000 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
3001 &Ops[0], Ops.size());
3003 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
3004 &Ops[0], Ops.size());
3007 SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
3009 PendingLoads.push_back(Chain);
3013 if (I.getType() != Type::VoidTy) {
3014 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3015 MVT VT = TLI.getValueType(PTy);
3016 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
3018 setValue(&I, Result);
3022 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3023 static GlobalVariable *ExtractTypeInfo (Value *V) {
3024 V = V->stripPointerCasts();
3025 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3026 assert ((GV || isa<ConstantPointerNull>(V)) &&
3027 "TypeInfo must be a global variable or NULL");
3031 /// addCatchInfo - Extract the personality and type infos from an eh.selector
3032 /// call, and add them to the specified machine basic block.
3033 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3034 MachineBasicBlock *MBB) {
3035 // Inform the MachineModuleInfo of the personality for this landing pad.
3036 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3037 assert(CE->getOpcode() == Instruction::BitCast &&
3038 isa<Function>(CE->getOperand(0)) &&
3039 "Personality should be a function");
3040 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3042 // Gather all the type infos for this landing pad and pass them along to
3043 // MachineModuleInfo.
3044 std::vector<GlobalVariable *> TyInfo;
3045 unsigned N = I.getNumOperands();
3047 for (unsigned i = N - 1; i > 2; --i) {
3048 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3049 unsigned FilterLength = CI->getZExtValue();
3050 unsigned FirstCatch = i + FilterLength + !FilterLength;
3051 assert (FirstCatch <= N && "Invalid filter length");
3053 if (FirstCatch < N) {
3054 TyInfo.reserve(N - FirstCatch);
3055 for (unsigned j = FirstCatch; j < N; ++j)
3056 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3057 MMI->addCatchTypeInfo(MBB, TyInfo);
3061 if (!FilterLength) {
3063 MMI->addCleanup(MBB);
3066 TyInfo.reserve(FilterLength - 1);
3067 for (unsigned j = i + 1; j < FirstCatch; ++j)
3068 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3069 MMI->addFilterTypeInfo(MBB, TyInfo);
3078 TyInfo.reserve(N - 3);
3079 for (unsigned j = 3; j < N; ++j)
3080 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3081 MMI->addCatchTypeInfo(MBB, TyInfo);
3086 /// Inlined utility function to implement binary input atomic intrinsics for
3087 // visitIntrinsicCall: I is a call instruction
3088 // Op is the associated NodeType for I
3090 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3091 SDValue Root = getRoot();
3092 SDValue L = DAG.getAtomic(Op, Root,
3093 getValue(I.getOperand(1)),
3094 getValue(I.getOperand(2)),
3097 DAG.setRoot(L.getValue(1));
3101 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3102 /// we want to emit this as a call to a named external function, return the name
3103 /// otherwise lower it and return null.
3105 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3106 switch (Intrinsic) {
3108 // By default, turn this into a target intrinsic node.
3109 visitTargetIntrinsic(I, Intrinsic);
3111 case Intrinsic::vastart: visitVAStart(I); return 0;
3112 case Intrinsic::vaend: visitVAEnd(I); return 0;
3113 case Intrinsic::vacopy: visitVACopy(I); return 0;
3114 case Intrinsic::returnaddress:
3115 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3116 getValue(I.getOperand(1))));
3118 case Intrinsic::frameaddress:
3119 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3120 getValue(I.getOperand(1))));
3122 case Intrinsic::setjmp:
3123 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3125 case Intrinsic::longjmp:
3126 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3128 case Intrinsic::memcpy_i32:
3129 case Intrinsic::memcpy_i64: {
3130 SDValue Op1 = getValue(I.getOperand(1));
3131 SDValue Op2 = getValue(I.getOperand(2));
3132 SDValue Op3 = getValue(I.getOperand(3));
3133 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3134 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3135 I.getOperand(1), 0, I.getOperand(2), 0));
3138 case Intrinsic::memset_i32:
3139 case Intrinsic::memset_i64: {
3140 SDValue Op1 = getValue(I.getOperand(1));
3141 SDValue Op2 = getValue(I.getOperand(2));
3142 SDValue Op3 = getValue(I.getOperand(3));
3143 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3144 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3145 I.getOperand(1), 0));
3148 case Intrinsic::memmove_i32:
3149 case Intrinsic::memmove_i64: {
3150 SDValue Op1 = getValue(I.getOperand(1));
3151 SDValue Op2 = getValue(I.getOperand(2));
3152 SDValue Op3 = getValue(I.getOperand(3));
3153 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3155 // If the source and destination are known to not be aliases, we can
3156 // lower memmove as memcpy.
3157 uint64_t Size = -1ULL;
3158 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3159 Size = C->getValue();
3160 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3161 AliasAnalysis::NoAlias) {
3162 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3163 I.getOperand(1), 0, I.getOperand(2), 0));
3167 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3168 I.getOperand(1), 0, I.getOperand(2), 0));
3171 case Intrinsic::dbg_stoppoint: {
3172 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3173 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3174 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3175 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3176 assert(DD && "Not a debug information descriptor");
3177 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3180 cast<CompileUnitDesc>(DD)));
3185 case Intrinsic::dbg_region_start: {
3186 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3187 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3188 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3189 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3190 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3195 case Intrinsic::dbg_region_end: {
3196 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3197 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3198 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3199 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3200 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3205 case Intrinsic::dbg_func_start: {
3206 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3208 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3209 Value *SP = FSI.getSubprogram();
3210 if (SP && MMI->Verify(SP)) {
3211 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3212 // what (most?) gdb expects.
3213 DebugInfoDesc *DD = MMI->getDescFor(SP);
3214 assert(DD && "Not a debug information descriptor");
3215 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3216 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3217 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3218 // Record the source line but does create a label. It will be emitted
3219 // at asm emission time.
3220 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3225 case Intrinsic::dbg_declare: {
3226 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3227 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3228 Value *Variable = DI.getVariable();
3229 if (MMI && Variable && MMI->Verify(Variable))
3230 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3231 getValue(DI.getAddress()), getValue(Variable)));
3235 case Intrinsic::eh_exception: {
3236 if (!CurMBB->isLandingPad()) {
3237 // FIXME: Mark exception register as live in. Hack for PR1508.
3238 unsigned Reg = TLI.getExceptionAddressRegister();
3239 if (Reg) CurMBB->addLiveIn(Reg);
3241 // Insert the EXCEPTIONADDR instruction.
3242 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3244 Ops[0] = DAG.getRoot();
3245 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3247 DAG.setRoot(Op.getValue(1));
3251 case Intrinsic::eh_selector_i32:
3252 case Intrinsic::eh_selector_i64: {
3253 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3254 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3255 MVT::i32 : MVT::i64);
3258 if (CurMBB->isLandingPad())
3259 addCatchInfo(I, MMI, CurMBB);
3262 FuncInfo.CatchInfoLost.insert(&I);
3264 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3265 unsigned Reg = TLI.getExceptionSelectorRegister();
3266 if (Reg) CurMBB->addLiveIn(Reg);
3269 // Insert the EHSELECTION instruction.
3270 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3272 Ops[0] = getValue(I.getOperand(1));
3274 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3276 DAG.setRoot(Op.getValue(1));
3278 setValue(&I, DAG.getConstant(0, VT));
3284 case Intrinsic::eh_typeid_for_i32:
3285 case Intrinsic::eh_typeid_for_i64: {
3286 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3287 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3288 MVT::i32 : MVT::i64);
3291 // Find the type id for the given typeinfo.
3292 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3294 unsigned TypeID = MMI->getTypeIDFor(GV);
3295 setValue(&I, DAG.getConstant(TypeID, VT));
3297 // Return something different to eh_selector.
3298 setValue(&I, DAG.getConstant(1, VT));
3304 case Intrinsic::eh_return: {
3305 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3308 MMI->setCallsEHReturn(true);
3309 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3312 getValue(I.getOperand(1)),
3313 getValue(I.getOperand(2))));
3315 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3321 case Intrinsic::eh_unwind_init: {
3322 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3323 MMI->setCallsUnwindInit(true);
3329 case Intrinsic::eh_dwarf_cfa: {
3330 MVT VT = getValue(I.getOperand(1)).getValueType();
3332 if (VT.bitsGT(TLI.getPointerTy()))
3333 CfaArg = DAG.getNode(ISD::TRUNCATE,
3334 TLI.getPointerTy(), getValue(I.getOperand(1)));
3336 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3337 TLI.getPointerTy(), getValue(I.getOperand(1)));
3339 SDValue Offset = DAG.getNode(ISD::ADD,
3341 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3342 TLI.getPointerTy()),
3344 setValue(&I, DAG.getNode(ISD::ADD,
3346 DAG.getNode(ISD::FRAMEADDR,
3349 TLI.getPointerTy())),
3354 case Intrinsic::sqrt:
3355 setValue(&I, DAG.getNode(ISD::FSQRT,
3356 getValue(I.getOperand(1)).getValueType(),
3357 getValue(I.getOperand(1))));
3359 case Intrinsic::powi:
3360 setValue(&I, DAG.getNode(ISD::FPOWI,
3361 getValue(I.getOperand(1)).getValueType(),
3362 getValue(I.getOperand(1)),
3363 getValue(I.getOperand(2))));
3365 case Intrinsic::sin:
3366 setValue(&I, DAG.getNode(ISD::FSIN,
3367 getValue(I.getOperand(1)).getValueType(),
3368 getValue(I.getOperand(1))));
3370 case Intrinsic::cos:
3371 setValue(&I, DAG.getNode(ISD::FCOS,
3372 getValue(I.getOperand(1)).getValueType(),
3373 getValue(I.getOperand(1))));
3375 case Intrinsic::pow:
3376 setValue(&I, DAG.getNode(ISD::FPOW,
3377 getValue(I.getOperand(1)).getValueType(),
3378 getValue(I.getOperand(1)),
3379 getValue(I.getOperand(2))));
3381 case Intrinsic::pcmarker: {
3382 SDValue Tmp = getValue(I.getOperand(1));
3383 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3386 case Intrinsic::readcyclecounter: {
3387 SDValue Op = getRoot();
3388 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3389 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3392 DAG.setRoot(Tmp.getValue(1));
3395 case Intrinsic::part_select: {
3396 // Currently not implemented: just abort
3397 assert(0 && "part_select intrinsic not implemented");
3400 case Intrinsic::part_set: {
3401 // Currently not implemented: just abort
3402 assert(0 && "part_set intrinsic not implemented");
3405 case Intrinsic::bswap:
3406 setValue(&I, DAG.getNode(ISD::BSWAP,
3407 getValue(I.getOperand(1)).getValueType(),
3408 getValue(I.getOperand(1))));
3410 case Intrinsic::cttz: {
3411 SDValue Arg = getValue(I.getOperand(1));
3412 MVT Ty = Arg.getValueType();
3413 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3414 setValue(&I, result);
3417 case Intrinsic::ctlz: {
3418 SDValue Arg = getValue(I.getOperand(1));
3419 MVT Ty = Arg.getValueType();
3420 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3421 setValue(&I, result);
3424 case Intrinsic::ctpop: {
3425 SDValue Arg = getValue(I.getOperand(1));
3426 MVT Ty = Arg.getValueType();
3427 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3428 setValue(&I, result);
3431 case Intrinsic::stacksave: {
3432 SDValue Op = getRoot();
3433 SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
3434 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3436 DAG.setRoot(Tmp.getValue(1));
3439 case Intrinsic::stackrestore: {
3440 SDValue Tmp = getValue(I.getOperand(1));
3441 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3444 case Intrinsic::var_annotation:
3445 // Discard annotate attributes
3448 case Intrinsic::init_trampoline: {
3449 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3453 Ops[1] = getValue(I.getOperand(1));
3454 Ops[2] = getValue(I.getOperand(2));
3455 Ops[3] = getValue(I.getOperand(3));
3456 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3457 Ops[5] = DAG.getSrcValue(F);
3459 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
3460 DAG.getNodeValueTypes(TLI.getPointerTy(),
3465 DAG.setRoot(Tmp.getValue(1));
3469 case Intrinsic::gcroot:
3471 Value *Alloca = I.getOperand(1);
3472 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3474 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3475 GCI->addStackRoot(FI->getIndex(), TypeMap);
3479 case Intrinsic::gcread:
3480 case Intrinsic::gcwrite:
3481 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3484 case Intrinsic::flt_rounds: {
3485 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3489 case Intrinsic::trap: {
3490 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3493 case Intrinsic::prefetch: {
3496 Ops[1] = getValue(I.getOperand(1));
3497 Ops[2] = getValue(I.getOperand(2));
3498 Ops[3] = getValue(I.getOperand(3));
3499 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3503 case Intrinsic::memory_barrier: {
3506 for (int x = 1; x < 6; ++x)
3507 Ops[x] = getValue(I.getOperand(x));
3509 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3512 case Intrinsic::atomic_cmp_swap: {
3513 SDValue Root = getRoot();
3514 SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
3515 getValue(I.getOperand(1)),
3516 getValue(I.getOperand(2)),
3517 getValue(I.getOperand(3)),
3520 DAG.setRoot(L.getValue(1));
3523 case Intrinsic::atomic_load_add:
3524 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
3525 case Intrinsic::atomic_load_sub:
3526 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
3527 case Intrinsic::atomic_load_and:
3528 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3529 case Intrinsic::atomic_load_or:
3530 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3531 case Intrinsic::atomic_load_xor:
3532 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
3533 case Intrinsic::atomic_load_nand:
3534 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
3535 case Intrinsic::atomic_load_min:
3536 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3537 case Intrinsic::atomic_load_max:
3538 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3539 case Intrinsic::atomic_load_umin:
3540 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3541 case Intrinsic::atomic_load_umax:
3542 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3543 case Intrinsic::atomic_swap:
3544 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
3549 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
3551 MachineBasicBlock *LandingPad) {
3552 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3553 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3554 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3555 unsigned BeginLabel = 0, EndLabel = 0;
3557 TargetLowering::ArgListTy Args;
3558 TargetLowering::ArgListEntry Entry;
3559 Args.reserve(CS.arg_size());
3560 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3562 SDValue ArgNode = getValue(*i);
3563 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3565 unsigned attrInd = i - CS.arg_begin() + 1;
3566 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3567 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3568 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3569 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3570 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3571 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3572 Entry.Alignment = CS.getParamAlignment(attrInd);
3573 Args.push_back(Entry);
3576 if (LandingPad && MMI) {
3577 // Insert a label before the invoke call to mark the try range. This can be
3578 // used to detect deletion of the invoke via the MachineModuleInfo.
3579 BeginLabel = MMI->NextLabelID();
3580 // Both PendingLoads and PendingExports must be flushed here;
3581 // this call might not return.
3583 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
3586 std::pair<SDValue,SDValue> Result =
3587 TLI.LowerCallTo(getRoot(), CS.getType(),
3588 CS.paramHasAttr(0, ParamAttr::SExt),
3589 CS.paramHasAttr(0, ParamAttr::ZExt),
3590 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3592 if (CS.getType() != Type::VoidTy)
3593 setValue(CS.getInstruction(), Result.first);
3594 DAG.setRoot(Result.second);
3596 if (LandingPad && MMI) {
3597 // Insert a label at the end of the invoke call to mark the try range. This
3598 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3599 EndLabel = MMI->NextLabelID();
3600 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
3602 // Inform MachineModuleInfo of range.
3603 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3608 void SelectionDAGLowering::visitCall(CallInst &I) {
3609 const char *RenameFn = 0;
3610 if (Function *F = I.getCalledFunction()) {
3611 if (F->isDeclaration()) {
3612 if (unsigned IID = F->getIntrinsicID()) {
3613 RenameFn = visitIntrinsicCall(I, IID);
3619 // Check for well-known libc/libm calls. If the function is internal, it
3620 // can't be a library call.
3621 unsigned NameLen = F->getNameLen();
3622 if (!F->hasInternalLinkage() && NameLen) {
3623 const char *NameStr = F->getNameStart();
3624 if (NameStr[0] == 'c' &&
3625 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3626 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3627 if (I.getNumOperands() == 3 && // Basic sanity checks.
3628 I.getOperand(1)->getType()->isFloatingPoint() &&
3629 I.getType() == I.getOperand(1)->getType() &&
3630 I.getType() == I.getOperand(2)->getType()) {
3631 SDValue LHS = getValue(I.getOperand(1));
3632 SDValue RHS = getValue(I.getOperand(2));
3633 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3637 } else if (NameStr[0] == 'f' &&
3638 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3639 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3640 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3641 if (I.getNumOperands() == 2 && // Basic sanity checks.
3642 I.getOperand(1)->getType()->isFloatingPoint() &&
3643 I.getType() == I.getOperand(1)->getType()) {
3644 SDValue Tmp = getValue(I.getOperand(1));
3645 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3648 } else if (NameStr[0] == 's' &&
3649 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3650 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3651 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3652 if (I.getNumOperands() == 2 && // Basic sanity checks.
3653 I.getOperand(1)->getType()->isFloatingPoint() &&
3654 I.getType() == I.getOperand(1)->getType()) {
3655 SDValue Tmp = getValue(I.getOperand(1));
3656 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3659 } else if (NameStr[0] == 'c' &&
3660 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3661 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3662 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3663 if (I.getNumOperands() == 2 && // Basic sanity checks.
3664 I.getOperand(1)->getType()->isFloatingPoint() &&
3665 I.getType() == I.getOperand(1)->getType()) {
3666 SDValue Tmp = getValue(I.getOperand(1));
3667 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3672 } else if (isa<InlineAsm>(I.getOperand(0))) {
3679 Callee = getValue(I.getOperand(0));
3681 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3683 LowerCallTo(&I, Callee, I.isTailCall());
3687 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3688 /// this value and returns the result as a ValueVT value. This uses
3689 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3690 /// If the Flag pointer is NULL, no flag is used.
3691 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3693 SDValue *Flag) const {
3694 // Assemble the legal parts into the final values.
3695 SmallVector<SDValue, 4> Values(ValueVTs.size());
3696 SmallVector<SDValue, 8> Parts;
3697 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3698 // Copy the legal parts from the registers.
3699 MVT ValueVT = ValueVTs[Value];
3700 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3701 MVT RegisterVT = RegVTs[Value];
3703 Parts.resize(NumRegs);
3704 for (unsigned i = 0; i != NumRegs; ++i) {
3707 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3709 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3710 *Flag = P.getValue(2);
3712 Chain = P.getValue(1);
3714 // If the source register was virtual and if we know something about it,
3715 // add an assert node.
3716 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
3717 RegisterVT.isInteger() && !RegisterVT.isVector()) {
3718 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
3719 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
3720 if (FLI.LiveOutRegInfo.size() > SlotNo) {
3721 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
3723 unsigned RegSize = RegisterVT.getSizeInBits();
3724 unsigned NumSignBits = LOI.NumSignBits;
3725 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
3727 // FIXME: We capture more information than the dag can represent. For
3728 // now, just use the tightest assertzext/assertsext possible.
3730 MVT FromVT(MVT::Other);
3731 if (NumSignBits == RegSize)
3732 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
3733 else if (NumZeroBits >= RegSize-1)
3734 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
3735 else if (NumSignBits > RegSize-8)
3736 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
3737 else if (NumZeroBits >= RegSize-9)
3738 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
3739 else if (NumSignBits > RegSize-16)
3740 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
3741 else if (NumZeroBits >= RegSize-17)
3742 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
3743 else if (NumSignBits > RegSize-32)
3744 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
3745 else if (NumZeroBits >= RegSize-33)
3746 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
3748 if (FromVT != MVT::Other) {
3749 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
3750 RegisterVT, P, DAG.getValueType(FromVT));
3759 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3764 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3765 &Values[0], ValueVTs.size());
3768 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3769 /// specified value into the registers specified by this object. This uses
3770 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3771 /// If the Flag pointer is NULL, no flag is used.
3772 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
3773 SDValue &Chain, SDValue *Flag) const {
3774 // Get the list of the values's legal parts.
3775 unsigned NumRegs = Regs.size();
3776 SmallVector<SDValue, 8> Parts(NumRegs);
3777 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3778 MVT ValueVT = ValueVTs[Value];
3779 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3780 MVT RegisterVT = RegVTs[Value];
3782 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3783 &Parts[Part], NumParts, RegisterVT);
3787 // Copy the parts into the registers.
3788 SmallVector<SDValue, 8> Chains(NumRegs);
3789 for (unsigned i = 0; i != NumRegs; ++i) {
3792 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3794 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3795 *Flag = Part.getValue(1);
3797 Chains[i] = Part.getValue(0);
3800 if (NumRegs == 1 || Flag)
3801 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3802 // flagged to it. That is the CopyToReg nodes and the user are considered
3803 // a single scheduling unit. If we create a TokenFactor and return it as
3804 // chain, then the TokenFactor is both a predecessor (operand) of the
3805 // user as well as a successor (the TF operands are flagged to the user).
3806 // c1, f1 = CopyToReg
3807 // c2, f2 = CopyToReg
3808 // c3 = TokenFactor c1, c2
3811 Chain = Chains[NumRegs-1];
3813 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3816 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3817 /// operand list. This adds the code marker and includes the number of
3818 /// values added into it.
3819 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3820 std::vector<SDValue> &Ops) const {
3821 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3822 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3823 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3824 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3825 MVT RegisterVT = RegVTs[Value];
3826 for (unsigned i = 0; i != NumRegs; ++i)
3827 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3831 /// isAllocatableRegister - If the specified register is safe to allocate,
3832 /// i.e. it isn't a stack pointer or some other special register, return the
3833 /// register class for the register. Otherwise, return null.
3834 static const TargetRegisterClass *
3835 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3836 const TargetLowering &TLI,
3837 const TargetRegisterInfo *TRI) {
3838 MVT FoundVT = MVT::Other;
3839 const TargetRegisterClass *FoundRC = 0;
3840 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3841 E = TRI->regclass_end(); RCI != E; ++RCI) {
3842 MVT ThisVT = MVT::Other;
3844 const TargetRegisterClass *RC = *RCI;
3845 // If none of the the value types for this register class are valid, we
3846 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3847 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3849 if (TLI.isTypeLegal(*I)) {
3850 // If we have already found this register in a different register class,
3851 // choose the one with the largest VT specified. For example, on
3852 // PowerPC, we favor f64 register classes over f32.
3853 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
3860 if (ThisVT == MVT::Other) continue;
3862 // NOTE: This isn't ideal. In particular, this might allocate the
3863 // frame pointer in functions that need it (due to them not being taken
3864 // out of allocation, because a variable sized allocation hasn't been seen
3865 // yet). This is a slight code pessimization, but should still work.
3866 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3867 E = RC->allocation_order_end(MF); I != E; ++I)
3869 // We found a matching register class. Keep looking at others in case
3870 // we find one with larger registers that this physreg is also in.
3881 /// AsmOperandInfo - This contains information for each constraint that we are
3883 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3884 /// CallOperand - If this is the result output operand or a clobber
3885 /// this is null, otherwise it is the incoming operand to the CallInst.
3886 /// This gets modified as the asm is processed.
3887 SDValue CallOperand;
3889 /// AssignedRegs - If this is a register or register class operand, this
3890 /// contains the set of register corresponding to the operand.
3891 RegsForValue AssignedRegs;
3893 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3894 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3897 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3898 /// busy in OutputRegs/InputRegs.
3899 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3900 std::set<unsigned> &OutputRegs,
3901 std::set<unsigned> &InputRegs,
3902 const TargetRegisterInfo &TRI) const {
3904 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3905 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3908 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3909 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3914 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3916 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3917 const TargetRegisterInfo &TRI) {
3918 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3920 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3921 for (; *Aliases; ++Aliases)
3922 Regs.insert(*Aliases);
3925 } // end anon namespace.
3928 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3929 /// specified operand. We prefer to assign virtual registers, to allow the
3930 /// register allocator handle the assignment process. However, if the asm uses
3931 /// features that we can't model on machineinstrs, we have SDISel do the
3932 /// allocation. This produces generally horrible, but correct, code.
3934 /// OpInfo describes the operand.
3935 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3936 /// or any explicitly clobbered registers.
3937 /// Input and OutputRegs are the set of already allocated physical registers.
3939 void SelectionDAGLowering::
3940 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3941 std::set<unsigned> &OutputRegs,
3942 std::set<unsigned> &InputRegs) {
3943 // Compute whether this value requires an input register, an output register,
3945 bool isOutReg = false;
3946 bool isInReg = false;
3947 switch (OpInfo.Type) {
3948 case InlineAsm::isOutput:
3951 // If this is an early-clobber output, or if there is an input
3952 // constraint that matches this, we need to reserve the input register
3953 // so no other inputs allocate to it.
3954 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3956 case InlineAsm::isInput:
3960 case InlineAsm::isClobber:
3967 MachineFunction &MF = DAG.getMachineFunction();
3968 SmallVector<unsigned, 4> Regs;
3970 // If this is a constraint for a single physreg, or a constraint for a
3971 // register class, find it.
3972 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3973 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3974 OpInfo.ConstraintVT);
3976 unsigned NumRegs = 1;
3977 if (OpInfo.ConstraintVT != MVT::Other)
3978 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3980 MVT ValueVT = OpInfo.ConstraintVT;
3983 // If this is a constraint for a specific physical register, like {r17},
3985 if (PhysReg.first) {
3986 if (OpInfo.ConstraintVT == MVT::Other)
3987 ValueVT = *PhysReg.second->vt_begin();
3989 // Get the actual register value type. This is important, because the user
3990 // may have asked for (e.g.) the AX register in i32 type. We need to
3991 // remember that AX is actually i16 to get the right extension.
3992 RegVT = *PhysReg.second->vt_begin();
3994 // This is a explicit reference to a physical register.
3995 Regs.push_back(PhysReg.first);
3997 // If this is an expanded reference, add the rest of the regs to Regs.
3999 TargetRegisterClass::iterator I = PhysReg.second->begin();
4000 for (; *I != PhysReg.first; ++I)
4001 assert(I != PhysReg.second->end() && "Didn't find reg!");
4003 // Already added the first reg.
4005 for (; NumRegs; --NumRegs, ++I) {
4006 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4010 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4011 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4012 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4016 // Otherwise, if this was a reference to an LLVM register class, create vregs
4017 // for this reference.
4018 std::vector<unsigned> RegClassRegs;
4019 const TargetRegisterClass *RC = PhysReg.second;
4021 // If this is an early clobber or tied register, our regalloc doesn't know
4022 // how to maintain the constraint. If it isn't, go ahead and create vreg
4023 // and let the regalloc do the right thing.
4024 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4025 // If there is some other early clobber and this is an input register,
4026 // then we are forced to pre-allocate the input reg so it doesn't
4027 // conflict with the earlyclobber.
4028 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
4029 RegVT = *PhysReg.second->vt_begin();
4031 if (OpInfo.ConstraintVT == MVT::Other)
4034 // Create the appropriate number of virtual registers.
4035 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4036 for (; NumRegs; --NumRegs)
4037 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4039 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4043 // Otherwise, we can't allocate it. Let the code below figure out how to
4044 // maintain these constraints.
4045 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4048 // This is a reference to a register class that doesn't directly correspond
4049 // to an LLVM register class. Allocate NumRegs consecutive, available,
4050 // registers from the class.
4051 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4052 OpInfo.ConstraintVT);
4055 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4056 unsigned NumAllocated = 0;
4057 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4058 unsigned Reg = RegClassRegs[i];
4059 // See if this register is available.
4060 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4061 (isInReg && InputRegs.count(Reg))) { // Already used.
4062 // Make sure we find consecutive registers.
4067 // Check to see if this register is allocatable (i.e. don't give out the
4070 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4071 if (!RC) { // Couldn't allocate this register.
4072 // Reset NumAllocated to make sure we return consecutive registers.
4078 // Okay, this register is good, we can use it.
4081 // If we allocated enough consecutive registers, succeed.
4082 if (NumAllocated == NumRegs) {
4083 unsigned RegStart = (i-NumAllocated)+1;
4084 unsigned RegEnd = i+1;
4085 // Mark all of the allocated registers used.
4086 for (unsigned i = RegStart; i != RegEnd; ++i)
4087 Regs.push_back(RegClassRegs[i]);
4089 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4090 OpInfo.ConstraintVT);
4091 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4096 // Otherwise, we couldn't allocate enough registers for this.
4100 /// visitInlineAsm - Handle a call to an InlineAsm object.
4102 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4103 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4105 /// ConstraintOperands - Information about all of the constraints.
4106 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4108 SDValue Chain = getRoot();
4111 std::set<unsigned> OutputRegs, InputRegs;
4113 // Do a prepass over the constraints, canonicalizing them, and building up the
4114 // ConstraintOperands list.
4115 std::vector<InlineAsm::ConstraintInfo>
4116 ConstraintInfos = IA->ParseConstraints();
4118 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4119 // constraint. If so, we can't let the register allocator allocate any input
4120 // registers, because it will not know to avoid the earlyclobbered output reg.
4121 bool SawEarlyClobber = false;
4123 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4124 unsigned ResNo = 0; // ResNo - The result number of the next output.
4125 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4126 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4127 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4129 MVT OpVT = MVT::Other;
4131 // Compute the value type for each operand.
4132 switch (OpInfo.Type) {
4133 case InlineAsm::isOutput:
4134 // Indirect outputs just consume an argument.
4135 if (OpInfo.isIndirect) {
4136 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4139 // The return value of the call is this value. As such, there is no
4140 // corresponding argument.
4141 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4142 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4143 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4145 assert(ResNo == 0 && "Asm only has one result!");
4146 OpVT = TLI.getValueType(CS.getType());
4150 case InlineAsm::isInput:
4151 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4153 case InlineAsm::isClobber:
4158 // If this is an input or an indirect output, process the call argument.
4159 // BasicBlocks are labels, currently appearing only in asm's.
4160 if (OpInfo.CallOperandVal) {
4161 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4162 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4164 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4165 const Type *OpTy = OpInfo.CallOperandVal->getType();
4166 // If this is an indirect operand, the operand is a pointer to the
4168 if (OpInfo.isIndirect)
4169 OpTy = cast<PointerType>(OpTy)->getElementType();
4171 // If OpTy is not a single value, it may be a struct/union that we
4172 // can tile with integers.
4173 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4174 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4182 OpTy = IntegerType::get(BitSize);
4187 OpVT = TLI.getValueType(OpTy, true);
4191 OpInfo.ConstraintVT = OpVT;
4193 // Compute the constraint code and ConstraintType to use.
4194 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
4196 // Keep track of whether we see an earlyclobber.
4197 SawEarlyClobber |= OpInfo.isEarlyClobber;
4199 // If we see a clobber of a register, it is an early clobber.
4200 if (!SawEarlyClobber &&
4201 OpInfo.Type == InlineAsm::isClobber &&
4202 OpInfo.ConstraintType == TargetLowering::C_Register) {
4203 // Note that we want to ignore things that we don't trick here, like
4204 // dirflag, fpsr, flags, etc.
4205 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4206 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4207 OpInfo.ConstraintVT);
4208 if (PhysReg.first || PhysReg.second) {
4209 // This is a register we know of.
4210 SawEarlyClobber = true;
4214 // If this is a memory input, and if the operand is not indirect, do what we
4215 // need to to provide an address for the memory input.
4216 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4217 !OpInfo.isIndirect) {
4218 assert(OpInfo.Type == InlineAsm::isInput &&
4219 "Can only indirectify direct input operands!");
4221 // Memory operands really want the address of the value. If we don't have
4222 // an indirect input, put it in the constpool if we can, otherwise spill
4223 // it to a stack slot.
4225 // If the operand is a float, integer, or vector constant, spill to a
4226 // constant pool entry to get its address.
4227 Value *OpVal = OpInfo.CallOperandVal;
4228 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4229 isa<ConstantVector>(OpVal)) {
4230 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4231 TLI.getPointerTy());
4233 // Otherwise, create a stack slot and emit a store to it before the
4235 const Type *Ty = OpVal->getType();
4236 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4237 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4238 MachineFunction &MF = DAG.getMachineFunction();
4239 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4240 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4241 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4242 OpInfo.CallOperand = StackSlot;
4245 // There is no longer a Value* corresponding to this operand.
4246 OpInfo.CallOperandVal = 0;
4247 // It is now an indirect operand.
4248 OpInfo.isIndirect = true;
4251 // If this constraint is for a specific register, allocate it before
4253 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4254 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4256 ConstraintInfos.clear();
4259 // Second pass - Loop over all of the operands, assigning virtual or physregs
4260 // to registerclass operands.
4261 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4262 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4264 // C_Register operands have already been allocated, Other/Memory don't need
4266 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4267 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4270 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4271 std::vector<SDValue> AsmNodeOperands;
4272 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
4273 AsmNodeOperands.push_back(
4274 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4277 // Loop over all of the inputs, copying the operand values into the
4278 // appropriate registers and processing the output regs.
4279 RegsForValue RetValRegs;
4281 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4282 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4284 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4285 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4287 switch (OpInfo.Type) {
4288 case InlineAsm::isOutput: {
4289 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4290 OpInfo.ConstraintType != TargetLowering::C_Register) {
4291 // Memory output, or 'other' output (e.g. 'X' constraint).
4292 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4294 // Add information to the INLINEASM node to know about this output.
4295 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4296 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4297 TLI.getPointerTy()));
4298 AsmNodeOperands.push_back(OpInfo.CallOperand);
4302 // Otherwise, this is a register or register class output.
4304 // Copy the output from the appropriate register. Find a register that
4306 if (OpInfo.AssignedRegs.Regs.empty()) {
4307 cerr << "Couldn't allocate output reg for constraint '"
4308 << OpInfo.ConstraintCode << "'!\n";
4312 // If this is an indirect operand, store through the pointer after the
4314 if (OpInfo.isIndirect) {
4315 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4316 OpInfo.CallOperandVal));
4318 // This is the result value of the call.
4319 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4320 // Concatenate this output onto the outputs list.
4321 RetValRegs.append(OpInfo.AssignedRegs);
4324 // Add information to the INLINEASM node to know that this register is
4326 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4330 case InlineAsm::isInput: {
4331 SDValue InOperandVal = OpInfo.CallOperand;
4333 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4334 // If this is required to match an output register we have already set,
4335 // just use its register.
4336 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4338 // Scan until we find the definition we already emitted of this operand.
4339 // When we find it, create a RegsForValue operand.
4340 unsigned CurOp = 2; // The first operand.
4341 for (; OperandNo; --OperandNo) {
4342 // Advance to the next operand.
4344 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4345 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4346 (NumOps & 7) == 4 /*MEM*/) &&
4347 "Skipped past definitions?");
4348 CurOp += (NumOps>>3)+1;
4352 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4353 if ((NumOps & 7) == 2 /*REGDEF*/) {
4354 // Add NumOps>>3 registers to MatchedRegs.
4355 RegsForValue MatchedRegs;
4356 MatchedRegs.TLI = &TLI;
4357 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4358 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4359 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4361 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4362 MatchedRegs.Regs.push_back(Reg);
4365 // Use the produced MatchedRegs object to
4366 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4367 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4370 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4371 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4372 // Add information to the INLINEASM node to know about this input.
4373 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4374 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4375 TLI.getPointerTy()));
4376 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4381 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4382 assert(!OpInfo.isIndirect &&
4383 "Don't know how to handle indirect other inputs yet!");
4385 std::vector<SDValue> Ops;
4386 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4389 cerr << "Invalid operand for inline asm constraint '"
4390 << OpInfo.ConstraintCode << "'!\n";
4394 // Add information to the INLINEASM node to know about this input.
4395 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4396 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4397 TLI.getPointerTy()));
4398 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4400 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4401 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4402 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4403 "Memory operands expect pointer values");
4405 // Add information to the INLINEASM node to know about this input.
4406 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4407 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4408 TLI.getPointerTy()));
4409 AsmNodeOperands.push_back(InOperandVal);
4413 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4414 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4415 "Unknown constraint type!");
4416 assert(!OpInfo.isIndirect &&
4417 "Don't know how to handle indirect register inputs yet!");
4419 // Copy the input into the appropriate registers.
4420 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4421 "Couldn't allocate input reg!");
4423 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4425 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4429 case InlineAsm::isClobber: {
4430 // Add the clobbered value to the operand list, so that the register
4431 // allocator is aware that the physreg got clobbered.
4432 if (!OpInfo.AssignedRegs.Regs.empty())
4433 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4440 // Finish up input operands.
4441 AsmNodeOperands[0] = Chain;
4442 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4444 Chain = DAG.getNode(ISD::INLINEASM,
4445 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4446 &AsmNodeOperands[0], AsmNodeOperands.size());
4447 Flag = Chain.getValue(1);
4449 // If this asm returns a register value, copy the result from that register
4450 // and set it as the value of the call.
4451 if (!RetValRegs.Regs.empty()) {
4452 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4454 // If any of the results of the inline asm is a vector, it may have the
4455 // wrong width/num elts. This can happen for register classes that can
4456 // contain multiple different value types. The preg or vreg allocated may
4457 // not have the same VT as was expected. Convert it to the right type with
4459 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4460 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4461 if (Val.Val->getValueType(i).isVector())
4462 Val = DAG.getNode(ISD::BIT_CONVERT,
4463 TLI.getValueType(ResSTy->getElementType(i)), Val);
4466 if (Val.getValueType().isVector())
4467 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4471 setValue(CS.getInstruction(), Val);
4474 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
4476 // Process indirect outputs, first output all of the flagged copies out of
4478 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4479 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4480 Value *Ptr = IndirectStoresToEmit[i].second;
4481 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4482 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4485 // Emit the non-flagged stores from the physregs.
4486 SmallVector<SDValue, 8> OutChains;
4487 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4488 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4489 getValue(StoresToEmit[i].second),
4490 StoresToEmit[i].second, 0));
4491 if (!OutChains.empty())
4492 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4493 &OutChains[0], OutChains.size());
4498 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4499 SDValue Src = getValue(I.getOperand(0));
4501 MVT IntPtr = TLI.getPointerTy();
4503 if (IntPtr.bitsLT(Src.getValueType()))
4504 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4505 else if (IntPtr.bitsGT(Src.getValueType()))
4506 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4508 // Scale the source by the type size.
4509 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4510 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4511 Src, DAG.getIntPtrConstant(ElementSize));
4513 TargetLowering::ArgListTy Args;
4514 TargetLowering::ArgListEntry Entry;
4516 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4517 Args.push_back(Entry);
4519 std::pair<SDValue,SDValue> Result =
4520 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4521 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4522 setValue(&I, Result.first); // Pointers always fit in registers
4523 DAG.setRoot(Result.second);
4526 void SelectionDAGLowering::visitFree(FreeInst &I) {
4527 TargetLowering::ArgListTy Args;
4528 TargetLowering::ArgListEntry Entry;
4529 Entry.Node = getValue(I.getOperand(0));
4530 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4531 Args.push_back(Entry);
4532 MVT IntPtr = TLI.getPointerTy();
4533 std::pair<SDValue,SDValue> Result =
4534 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4535 CallingConv::C, true,
4536 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4537 DAG.setRoot(Result.second);
4540 // EmitInstrWithCustomInserter - This method should be implemented by targets
4541 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4542 // instructions are special in various ways, which require special support to
4543 // insert. The specified MachineInstr is created but not inserted into any
4544 // basic blocks, and the scheduler passes ownership of it to this method.
4545 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4546 MachineBasicBlock *MBB) {
4547 cerr << "If a target marks an instruction with "
4548 << "'usesCustomDAGSchedInserter', it must implement "
4549 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4554 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4555 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4556 getValue(I.getOperand(1)),
4557 DAG.getSrcValue(I.getOperand(1))));
4560 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4561 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4562 getValue(I.getOperand(0)),
4563 DAG.getSrcValue(I.getOperand(0)));
4565 DAG.setRoot(V.getValue(1));
4568 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4569 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4570 getValue(I.getOperand(1)),
4571 DAG.getSrcValue(I.getOperand(1))));
4574 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4575 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4576 getValue(I.getOperand(1)),
4577 getValue(I.getOperand(2)),
4578 DAG.getSrcValue(I.getOperand(1)),
4579 DAG.getSrcValue(I.getOperand(2))));
4582 /// TargetLowering::LowerArguments - This is the default LowerArguments
4583 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4584 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4585 /// integrated into SDISel.
4586 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
4587 SmallVectorImpl<SDValue> &ArgValues) {
4588 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4589 SmallVector<SDValue, 3+16> Ops;
4590 Ops.push_back(DAG.getRoot());
4591 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4592 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4594 // Add one result value for each formal argument.
4595 SmallVector<MVT, 16> RetVals;
4597 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4599 SmallVector<MVT, 4> ValueVTs;
4600 ComputeValueVTs(*this, I->getType(), ValueVTs);
4601 for (unsigned Value = 0, NumValues = ValueVTs.size();
4602 Value != NumValues; ++Value) {
4603 MVT VT = ValueVTs[Value];
4604 const Type *ArgTy = VT.getTypeForMVT();
4605 ISD::ArgFlagsTy Flags;
4606 unsigned OriginalAlignment =
4607 getTargetData()->getABITypeAlignment(ArgTy);
4609 if (F.paramHasAttr(j, ParamAttr::ZExt))
4611 if (F.paramHasAttr(j, ParamAttr::SExt))
4613 if (F.paramHasAttr(j, ParamAttr::InReg))
4615 if (F.paramHasAttr(j, ParamAttr::StructRet))
4617 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4619 const PointerType *Ty = cast<PointerType>(I->getType());
4620 const Type *ElementTy = Ty->getElementType();
4621 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4622 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4623 // For ByVal, alignment should be passed from FE. BE will guess if
4624 // this info is not there but there are cases it cannot get right.
4625 if (F.getParamAlignment(j))
4626 FrameAlign = F.getParamAlignment(j);
4627 Flags.setByValAlign(FrameAlign);
4628 Flags.setByValSize(FrameSize);
4630 if (F.paramHasAttr(j, ParamAttr::Nest))
4632 Flags.setOrigAlign(OriginalAlignment);
4634 MVT RegisterVT = getRegisterType(VT);
4635 unsigned NumRegs = getNumRegisters(VT);
4636 for (unsigned i = 0; i != NumRegs; ++i) {
4637 RetVals.push_back(RegisterVT);
4638 ISD::ArgFlagsTy MyFlags = Flags;
4639 if (NumRegs > 1 && i == 0)
4641 // if it isn't first piece, alignment must be 1
4643 MyFlags.setOrigAlign(1);
4644 Ops.push_back(DAG.getArgFlags(MyFlags));
4649 RetVals.push_back(MVT::Other);
4652 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4653 DAG.getVTList(&RetVals[0], RetVals.size()),
4654 &Ops[0], Ops.size()).Val;
4656 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4657 // allows exposing the loads that may be part of the argument access to the
4658 // first DAGCombiner pass.
4659 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
4661 // The number of results should match up, except that the lowered one may have
4662 // an extra flag result.
4663 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4664 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4665 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4666 && "Lowering produced unexpected number of results!");
4668 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
4669 if (Result != TmpRes.Val && Result->use_empty()) {
4670 HandleSDNode Dummy(DAG.getRoot());
4671 DAG.RemoveDeadNode(Result);
4674 Result = TmpRes.Val;
4676 unsigned NumArgRegs = Result->getNumValues() - 1;
4677 DAG.setRoot(SDValue(Result, NumArgRegs));
4679 // Set up the return result vector.
4682 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4684 SmallVector<MVT, 4> ValueVTs;
4685 ComputeValueVTs(*this, I->getType(), ValueVTs);
4686 for (unsigned Value = 0, NumValues = ValueVTs.size();
4687 Value != NumValues; ++Value) {
4688 MVT VT = ValueVTs[Value];
4689 MVT PartVT = getRegisterType(VT);
4691 unsigned NumParts = getNumRegisters(VT);
4692 SmallVector<SDValue, 4> Parts(NumParts);
4693 for (unsigned j = 0; j != NumParts; ++j)
4694 Parts[j] = SDValue(Result, i++);
4696 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4697 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4698 AssertOp = ISD::AssertSext;
4699 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4700 AssertOp = ISD::AssertZext;
4702 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4706 assert(i == NumArgRegs && "Argument register count mismatch!");
4710 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4711 /// implementation, which just inserts an ISD::CALL node, which is later custom
4712 /// lowered by the target to something concrete. FIXME: When all targets are
4713 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4714 std::pair<SDValue, SDValue>
4715 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
4716 bool RetSExt, bool RetZExt, bool isVarArg,
4717 unsigned CallingConv, bool isTailCall,
4719 ArgListTy &Args, SelectionDAG &DAG) {
4720 SmallVector<SDValue, 32> Ops;
4721 Ops.push_back(Chain); // Op#0 - Chain
4722 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4723 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4724 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4725 Ops.push_back(Callee);
4727 // Handle all of the outgoing arguments.
4728 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4729 SmallVector<MVT, 4> ValueVTs;
4730 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
4731 for (unsigned Value = 0, NumValues = ValueVTs.size();
4732 Value != NumValues; ++Value) {
4733 MVT VT = ValueVTs[Value];
4734 const Type *ArgTy = VT.getTypeForMVT();
4735 SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value);
4736 ISD::ArgFlagsTy Flags;
4737 unsigned OriginalAlignment =
4738 getTargetData()->getABITypeAlignment(ArgTy);
4744 if (Args[i].isInReg)
4748 if (Args[i].isByVal) {
4750 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4751 const Type *ElementTy = Ty->getElementType();
4752 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4753 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4754 // For ByVal, alignment should come from FE. BE will guess if this
4755 // info is not there but there are cases it cannot get right.
4756 if (Args[i].Alignment)
4757 FrameAlign = Args[i].Alignment;
4758 Flags.setByValAlign(FrameAlign);
4759 Flags.setByValSize(FrameSize);
4763 Flags.setOrigAlign(OriginalAlignment);
4765 MVT PartVT = getRegisterType(VT);
4766 unsigned NumParts = getNumRegisters(VT);
4767 SmallVector<SDValue, 4> Parts(NumParts);
4768 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4771 ExtendKind = ISD::SIGN_EXTEND;
4772 else if (Args[i].isZExt)
4773 ExtendKind = ISD::ZERO_EXTEND;
4775 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4777 for (unsigned i = 0; i != NumParts; ++i) {
4778 // if it isn't first piece, alignment must be 1
4779 ISD::ArgFlagsTy MyFlags = Flags;
4780 if (NumParts > 1 && i == 0)
4783 MyFlags.setOrigAlign(1);
4785 Ops.push_back(Parts[i]);
4786 Ops.push_back(DAG.getArgFlags(MyFlags));
4791 // Figure out the result value types. We start by making a list of
4792 // the potentially illegal return value types.
4793 SmallVector<MVT, 4> LoweredRetTys;
4794 SmallVector<MVT, 4> RetTys;
4795 ComputeValueVTs(*this, RetTy, RetTys);
4797 // Then we translate that to a list of legal types.
4798 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4800 MVT RegisterVT = getRegisterType(VT);
4801 unsigned NumRegs = getNumRegisters(VT);
4802 for (unsigned i = 0; i != NumRegs; ++i)
4803 LoweredRetTys.push_back(RegisterVT);
4806 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4808 // Create the CALL node.
4809 SDValue Res = DAG.getNode(ISD::CALL,
4810 DAG.getVTList(&LoweredRetTys[0],
4811 LoweredRetTys.size()),
4812 &Ops[0], Ops.size());
4813 Chain = Res.getValue(LoweredRetTys.size() - 1);
4815 // Gather up the call result into a single value.
4816 if (RetTy != Type::VoidTy) {
4817 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4820 AssertOp = ISD::AssertSext;
4822 AssertOp = ISD::AssertZext;
4824 SmallVector<SDValue, 4> ReturnValues;
4826 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4828 MVT RegisterVT = getRegisterType(VT);
4829 unsigned NumRegs = getNumRegisters(VT);
4830 unsigned RegNoEnd = NumRegs + RegNo;
4831 SmallVector<SDValue, 4> Results;
4832 for (; RegNo != RegNoEnd; ++RegNo)
4833 Results.push_back(Res.getValue(RegNo));
4834 SDValue ReturnValue =
4835 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4837 ReturnValues.push_back(ReturnValue);
4839 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
4840 &ReturnValues[0], ReturnValues.size());
4843 return std::make_pair(Res, Chain);
4846 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4847 assert(0 && "LowerOperation not implemented for this target!");
4853 //===----------------------------------------------------------------------===//
4854 // SelectionDAGISel code
4855 //===----------------------------------------------------------------------===//
4857 unsigned SelectionDAGISel::MakeReg(MVT VT) {
4858 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4861 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4862 AU.addRequired<AliasAnalysis>();
4863 AU.addRequired<CollectorModuleMetadata>();
4864 AU.setPreservesAll();
4867 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4868 // Get alias analysis for load/store combining.
4869 AA = &getAnalysis<AliasAnalysis>();
4871 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4872 if (MF.getFunction()->hasCollector())
4873 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4876 RegInfo = &MF.getRegInfo();
4877 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4879 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4881 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4882 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4883 // Mark landing pad.
4884 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4886 SelectAllBasicBlocks(Fn, MF, FuncInfo);
4888 // Add function live-ins to entry block live-in set.
4889 BasicBlock *EntryBB = &Fn.getEntryBlock();
4890 BB = FuncInfo.MBBMap[EntryBB];
4891 if (!RegInfo->livein_empty())
4892 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4893 E = RegInfo->livein_end(); I != E; ++I)
4894 BB->addLiveIn(I->first);
4897 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4898 "Not all catch info was assigned to a landing pad!");
4904 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4905 SDValue Op = getValue(V);
4906 assert((Op.getOpcode() != ISD::CopyFromReg ||
4907 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4908 "Copy from a reg to the same reg!");
4909 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4911 RegsForValue RFV(TLI, Reg, V->getType());
4912 SDValue Chain = DAG.getEntryNode();
4913 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4914 PendingExports.push_back(Chain);
4917 void SelectionDAGISel::
4918 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4919 // If this is the entry block, emit arguments.
4920 Function &F = *LLVMBB->getParent();
4921 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4922 SDValue OldRoot = SDL.DAG.getRoot();
4923 SmallVector<SDValue, 16> Args;
4924 TLI.LowerArguments(F, SDL.DAG, Args);
4927 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4929 SmallVector<MVT, 4> ValueVTs;
4930 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
4931 unsigned NumValues = ValueVTs.size();
4932 if (!AI->use_empty()) {
4933 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues));
4934 // If this argument is live outside of the entry block, insert a copy from
4935 // whereever we got it to the vreg that other BB's will reference it as.
4936 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4937 if (VMI != FuncInfo.ValueMap.end()) {
4938 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4944 // Finally, if the target has anything special to do, allow it to do so.
4945 // FIXME: this should insert code into the DAG!
4946 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4949 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4950 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4951 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4952 if (isSelector(I)) {
4953 // Apply the catch info to DestBB.
4954 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4956 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4957 FLI.CatchInfoFound.insert(I);
4962 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4963 /// whether object offset >= 0.
4965 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
4966 if (!isa<FrameIndexSDNode>(Op)) return false;
4968 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
4969 int FrameIdx = FrameIdxNode->getIndex();
4970 return MFI->isFixedObjectIndex(FrameIdx) &&
4971 MFI->getObjectOffset(FrameIdx) >= 0;
4974 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
4975 /// possibly be overwritten when lowering the outgoing arguments in a tail
4976 /// call. Currently the implementation of this call is very conservative and
4977 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
4978 /// virtual registers would be overwritten by direct lowering.
4979 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
4980 MachineFrameInfo * MFI) {
4981 RegisterSDNode * OpReg = NULL;
4982 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
4983 (Op.getOpcode()== ISD::CopyFromReg &&
4984 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
4985 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
4986 (Op.getOpcode() == ISD::LOAD &&
4987 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
4988 (Op.getOpcode() == ISD::MERGE_VALUES &&
4989 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
4990 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
4996 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4997 /// DAG and fixes their tailcall attribute operand.
4998 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4999 TargetLowering& TLI) {
5000 SDNode * Ret = NULL;
5001 SDValue Terminator = DAG.getRoot();
5004 if (Terminator.getOpcode() == ISD::RET) {
5005 Ret = Terminator.Val;
5008 // Fix tail call attribute of CALL nodes.
5009 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
5010 BI = DAG.allnodes_end(); BI != BE; ) {
5012 if (BI->getOpcode() == ISD::CALL) {
5013 SDValue OpRet(Ret, 0);
5014 SDValue OpCall(BI, 0);
5015 bool isMarkedTailCall =
5016 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5017 // If CALL node has tail call attribute set to true and the call is not
5018 // eligible (no RET or the target rejects) the attribute is fixed to
5019 // false. The TargetLowering::IsEligibleForTailCallOptimization function
5020 // must correctly identify tail call optimizable calls.
5021 if (!isMarkedTailCall) continue;
5023 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5024 // Not eligible. Mark CALL node as non tail call.
5025 SmallVector<SDValue, 32> Ops;
5027 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5028 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5032 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5034 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5036 // Look for tail call clobbered arguments. Emit a series of
5037 // copyto/copyfrom virtual register nodes to protect them.
5038 SmallVector<SDValue, 32> Ops;
5039 SDValue Chain = OpCall.getOperand(0), InFlag;
5041 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5042 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5044 if (idx > 4 && (idx % 2)) {
5045 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5046 getArgFlags().isByVal();
5047 MachineFunction &MF = DAG.getMachineFunction();
5048 MachineFrameInfo *MFI = MF.getFrameInfo();
5050 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
5051 MVT VT = Arg.getValueType();
5052 unsigned VReg = MF.getRegInfo().
5053 createVirtualRegister(TLI.getRegClassFor(VT));
5054 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5055 InFlag = Chain.getValue(1);
5056 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5057 Chain = Arg.getValue(1);
5058 InFlag = Arg.getValue(2);
5063 // Link in chain of CopyTo/CopyFromReg.
5065 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5071 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
5072 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5073 FunctionLoweringInfo &FuncInfo) {
5074 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
5076 // Lower any arguments needed in this block if this is the entry block.
5077 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
5078 LowerArguments(LLVMBB, SDL);
5080 BB = FuncInfo.MBBMap[LLVMBB];
5081 SDL.setCurrentBasicBlock(BB);
5083 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
5085 if (MMI && BB->isLandingPad()) {
5086 // Add a label to mark the beginning of the landing pad. Deletion of the
5087 // landing pad can thus be detected via the MachineModuleInfo.
5088 unsigned LabelID = MMI->addLandingPad(BB);
5089 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID));
5091 // Mark exception register as live in.
5092 unsigned Reg = TLI.getExceptionAddressRegister();
5093 if (Reg) BB->addLiveIn(Reg);
5095 // Mark exception selector register as live in.
5096 Reg = TLI.getExceptionSelectorRegister();
5097 if (Reg) BB->addLiveIn(Reg);
5099 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5100 // function and list of typeids logically belong to the invoke (or, if you
5101 // like, the basic block containing the invoke), and need to be associated
5102 // with it in the dwarf exception handling tables. Currently however the
5103 // information is provided by an intrinsic (eh.selector) that can be moved
5104 // to unexpected places by the optimizers: if the unwind edge is critical,
5105 // then breaking it can result in the intrinsics being in the successor of
5106 // the landing pad, not the landing pad itself. This results in exceptions
5107 // not being caught because no typeids are associated with the invoke.
5108 // This may not be the only way things can go wrong, but it is the only way
5109 // we try to work around for the moment.
5110 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5112 if (Br && Br->isUnconditional()) { // Critical edge?
5113 BasicBlock::iterator I, E;
5114 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5119 // No catch info found - try to extract some from the successor.
5120 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5124 // Lower all of the non-terminator instructions.
5125 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
5129 // Ensure that all instructions which are used outside of their defining
5130 // blocks are available as virtual registers. Invoke is handled elsewhere.
5131 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
5132 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
5133 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
5134 if (VMI != FuncInfo.ValueMap.end())
5135 SDL.CopyValueToVirtualRegister(I, VMI->second);
5138 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5139 // ensure constants are generated when needed. Remember the virtual registers
5140 // that need to be added to the Machine PHI nodes as input. We cannot just
5141 // directly add them, because expansion might result in multiple MBB's for one
5142 // BB. As such, the start of the BB might correspond to a different MBB than
5145 TerminatorInst *TI = LLVMBB->getTerminator();
5147 // Emit constants only once even if used by multiple PHI nodes.
5148 std::map<Constant*, unsigned> ConstantsOut;
5150 // Vector bool would be better, but vector<bool> is really slow.
5151 std::vector<unsigned char> SuccsHandled;
5152 if (TI->getNumSuccessors())
5153 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
5155 // Check successor nodes' PHI nodes that expect a constant to be available
5157 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5158 BasicBlock *SuccBB = TI->getSuccessor(succ);
5159 if (!isa<PHINode>(SuccBB->begin())) continue;
5160 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
5162 // If this terminator has multiple identical successors (common for
5163 // switches), only handle each succ once.
5164 unsigned SuccMBBNo = SuccMBB->getNumber();
5165 if (SuccsHandled[SuccMBBNo]) continue;
5166 SuccsHandled[SuccMBBNo] = true;
5168 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5171 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5172 // nodes and Machine PHI nodes, but the incoming operands have not been
5174 for (BasicBlock::iterator I = SuccBB->begin();
5175 (PN = dyn_cast<PHINode>(I)); ++I) {
5176 // Ignore dead phi's.
5177 if (PN->use_empty()) continue;
5180 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5182 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5183 unsigned &RegOut = ConstantsOut[C];
5185 RegOut = FuncInfo.CreateRegForValue(C);
5186 SDL.CopyValueToVirtualRegister(C, RegOut);
5190 Reg = FuncInfo.ValueMap[PHIOp];
5192 assert(isa<AllocaInst>(PHIOp) &&
5193 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5194 "Didn't codegen value into a register!??");
5195 Reg = FuncInfo.CreateRegForValue(PHIOp);
5196 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
5200 // Remember that this register needs to added to the machine PHI node as
5201 // the input for this MBB.
5202 MVT VT = TLI.getValueType(PN->getType());
5203 unsigned NumRegisters = TLI.getNumRegisters(VT);
5204 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5205 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5208 ConstantsOut.clear();
5210 // Lower the terminator after the copies are emitted.
5211 SDL.visit(*LLVMBB->getTerminator());
5213 // Copy over any CaseBlock records that may now exist due to SwitchInst
5214 // lowering, as well as any jump table information.
5215 SwitchCases.clear();
5216 SwitchCases = SDL.SwitchCases;
5218 JTCases = SDL.JTCases;
5219 BitTestCases.clear();
5220 BitTestCases = SDL.BitTestCases;
5222 // Make sure the root of the DAG is up-to-date.
5223 DAG.setRoot(SDL.getControlRoot());
5225 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5226 // with correct tailcall attribute so that the target can rely on the tailcall
5227 // attribute indicating whether the call is really eligible for tail call
5229 CheckDAGForTailCallsAndFixThem(DAG, TLI);
5232 void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
5233 SmallPtrSet<SDNode*, 128> VisitedNodes;
5234 SmallVector<SDNode*, 128> Worklist;
5236 Worklist.push_back(DAG.getRoot().Val);
5242 while (!Worklist.empty()) {
5243 SDNode *N = Worklist.back();
5244 Worklist.pop_back();
5246 // If we've already seen this node, ignore it.
5247 if (!VisitedNodes.insert(N))
5250 // Otherwise, add all chain operands to the worklist.
5251 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5252 if (N->getOperand(i).getValueType() == MVT::Other)
5253 Worklist.push_back(N->getOperand(i).Val);
5255 // If this is a CopyToReg with a vreg dest, process it.
5256 if (N->getOpcode() != ISD::CopyToReg)
5259 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5260 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5263 // Ignore non-scalar or non-integer values.
5264 SDValue Src = N->getOperand(2);
5265 MVT SrcVT = Src.getValueType();
5266 if (!SrcVT.isInteger() || SrcVT.isVector())
5269 unsigned NumSignBits = DAG.ComputeNumSignBits(Src);
5270 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5271 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5273 // Only install this information if it tells us something.
5274 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5275 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5276 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5277 if (DestReg >= FLI.LiveOutRegInfo.size())
5278 FLI.LiveOutRegInfo.resize(DestReg+1);
5279 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5280 LOI.NumSignBits = NumSignBits;
5281 LOI.KnownOne = NumSignBits;
5282 LOI.KnownZero = NumSignBits;
5287 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
5288 std::string GroupName;
5289 if (TimePassesIsEnabled)
5290 GroupName = "Instruction Selection and Scheduling";
5291 std::string BlockName;
5292 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
5293 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
5294 BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' +
5295 BB->getBasicBlock()->getName();
5297 DOUT << "Initial selection DAG:\n";
5300 if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName);
5302 // Run the DAG combiner in pre-legalize mode.
5303 if (TimePassesIsEnabled) {
5304 NamedRegionTimer T("DAG Combining 1", GroupName);
5305 DAG.Combine(false, *AA);
5307 DAG.Combine(false, *AA);
5310 DOUT << "Optimized lowered selection DAG:\n";
5313 // Second step, hack on the DAG until it only uses operations and types that
5314 // the target supports.
5315 if (EnableLegalizeTypes) {// Enable this some day.
5316 if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " +
5319 if (TimePassesIsEnabled) {
5320 NamedRegionTimer T("Type Legalization", GroupName);
5321 DAG.LegalizeTypes();
5323 DAG.LegalizeTypes();
5326 DOUT << "Type-legalized selection DAG:\n";
5329 // TODO: enable a dag combine pass here.
5332 if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName);
5334 if (TimePassesIsEnabled) {
5335 NamedRegionTimer T("DAG Legalization", GroupName);
5341 DOUT << "Legalized selection DAG:\n";
5344 if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName);
5346 // Run the DAG combiner in post-legalize mode.
5347 if (TimePassesIsEnabled) {
5348 NamedRegionTimer T("DAG Combining 2", GroupName);
5349 DAG.Combine(true, *AA);
5351 DAG.Combine(true, *AA);
5354 DOUT << "Optimized legalized selection DAG:\n";
5357 if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
5359 if (!FastISel && EnableValueProp)
5360 ComputeLiveOutVRegInfo(DAG);
5362 // Third, instruction select all of the operations to machine code, adding the
5363 // code to the MachineBasicBlock.
5364 if (TimePassesIsEnabled) {
5365 NamedRegionTimer T("Instruction Selection", GroupName);
5366 InstructionSelect(DAG);
5368 InstructionSelect(DAG);
5371 DOUT << "Selected selection DAG:\n";
5374 if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName);
5376 // Schedule machine code.
5377 ScheduleDAG *Scheduler;
5378 if (TimePassesIsEnabled) {
5379 NamedRegionTimer T("Instruction Scheduling", GroupName);
5380 Scheduler = Schedule(DAG);
5382 Scheduler = Schedule(DAG);
5385 if (ViewSUnitDAGs) Scheduler->viewGraph();
5387 // Emit machine code to BB. This can change 'BB' to the last block being
5389 if (TimePassesIsEnabled) {
5390 NamedRegionTimer T("Instruction Creation", GroupName);
5391 BB = Scheduler->EmitSchedule();
5393 BB = Scheduler->EmitSchedule();
5396 // Free the scheduler state.
5397 if (TimePassesIsEnabled) {
5398 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
5404 // Perform target specific isel post processing.
5405 if (TimePassesIsEnabled) {
5406 NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
5407 InstructionSelectPostProcessing();
5409 InstructionSelectPostProcessing();
5412 DOUT << "Selected machine code:\n";
5416 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
5417 FunctionLoweringInfo &FuncInfo) {
5418 // Define NodeAllocator here so that memory allocation is reused for
5419 // each basic block.
5420 NodeAllocatorType NodeAllocator;
5422 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
5423 SelectBasicBlock(I, MF, FuncInfo, NodeAllocator);
5427 SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5428 FunctionLoweringInfo &FuncInfo,
5429 NodeAllocatorType &NodeAllocator) {
5430 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5432 SelectionDAG DAG(TLI, MF, FuncInfo,
5433 getAnalysisToUpdate<MachineModuleInfo>(),
5437 // First step, lower LLVM code to some DAG. This DAG may use operations and
5438 // types that are not supported by the target.
5439 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5441 // Second step, emit the lowered DAG as machine code.
5442 CodeGenAndEmitDAG(DAG);
5445 DOUT << "Total amount of phi nodes to update: "
5446 << PHINodesToUpdate.size() << "\n";
5447 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5448 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5449 << ", " << PHINodesToUpdate[i].second << ")\n";);
5451 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5452 // PHI nodes in successors.
5453 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
5454 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5455 MachineInstr *PHI = PHINodesToUpdate[i].first;
5456 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5457 "This is not a machine PHI node that we are updating!");
5458 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5460 PHI->addOperand(MachineOperand::CreateMBB(BB));
5465 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5466 // Lower header first, if it wasn't already lowered
5467 if (!BitTestCases[i].Emitted) {
5468 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5469 getAnalysisToUpdate<MachineModuleInfo>(),
5472 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5473 // Set the current basic block to the mbb we wish to insert the code into
5474 BB = BitTestCases[i].Parent;
5475 HSDL.setCurrentBasicBlock(BB);
5477 HSDL.visitBitTestHeader(BitTestCases[i]);
5478 HSDAG.setRoot(HSDL.getRoot());
5479 CodeGenAndEmitDAG(HSDAG);
5482 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5483 SelectionDAG BSDAG(TLI, MF, FuncInfo,
5484 getAnalysisToUpdate<MachineModuleInfo>(),
5487 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
5488 // Set the current basic block to the mbb we wish to insert the code into
5489 BB = BitTestCases[i].Cases[j].ThisBB;
5490 BSDL.setCurrentBasicBlock(BB);
5493 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5494 BitTestCases[i].Reg,
5495 BitTestCases[i].Cases[j]);
5497 BSDL.visitBitTestCase(BitTestCases[i].Default,
5498 BitTestCases[i].Reg,
5499 BitTestCases[i].Cases[j]);
5502 BSDAG.setRoot(BSDL.getRoot());
5503 CodeGenAndEmitDAG(BSDAG);
5507 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5508 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5509 MachineBasicBlock *PHIBB = PHI->getParent();
5510 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5511 "This is not a machine PHI node that we are updating!");
5512 // This is "default" BB. We have two jumps to it. From "header" BB and
5513 // from last "case" BB.
5514 if (PHIBB == BitTestCases[i].Default) {
5515 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5517 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5518 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5520 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5523 // One of "cases" BB.
5524 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5525 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5526 if (cBB->succ_end() !=
5527 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5528 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5530 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5536 // If the JumpTable record is filled in, then we need to emit a jump table.
5537 // Updating the PHI nodes is tricky in this case, since we need to determine
5538 // whether the PHI is a successor of the range check MBB or the jump table MBB
5539 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5540 // Lower header first, if it wasn't already lowered
5541 if (!JTCases[i].first.Emitted) {
5542 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5543 getAnalysisToUpdate<MachineModuleInfo>(),
5546 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5547 // Set the current basic block to the mbb we wish to insert the code into
5548 BB = JTCases[i].first.HeaderBB;
5549 HSDL.setCurrentBasicBlock(BB);
5551 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5552 HSDAG.setRoot(HSDL.getRoot());
5553 CodeGenAndEmitDAG(HSDAG);
5556 SelectionDAG JSDAG(TLI, MF, FuncInfo,
5557 getAnalysisToUpdate<MachineModuleInfo>(),
5560 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5561 // Set the current basic block to the mbb we wish to insert the code into
5562 BB = JTCases[i].second.MBB;
5563 JSDL.setCurrentBasicBlock(BB);
5565 JSDL.visitJumpTable(JTCases[i].second);
5566 JSDAG.setRoot(JSDL.getRoot());
5567 CodeGenAndEmitDAG(JSDAG);
5570 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5571 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5572 MachineBasicBlock *PHIBB = PHI->getParent();
5573 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5574 "This is not a machine PHI node that we are updating!");
5575 // "default" BB. We can go there only from header BB.
5576 if (PHIBB == JTCases[i].second.Default) {
5577 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5579 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5581 // JT BB. Just iterate over successors here
5582 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5583 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5585 PHI->addOperand(MachineOperand::CreateMBB(BB));
5590 // If the switch block involved a branch to one of the actual successors, we
5591 // need to update PHI nodes in that block.
5592 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5593 MachineInstr *PHI = PHINodesToUpdate[i].first;
5594 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5595 "This is not a machine PHI node that we are updating!");
5596 if (BB->isSuccessor(PHI->getParent())) {
5597 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5599 PHI->addOperand(MachineOperand::CreateMBB(BB));
5603 // If we generated any switch lowering information, build and codegen any
5604 // additional DAGs necessary.
5605 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5606 SelectionDAG SDAG(TLI, MF, FuncInfo,
5607 getAnalysisToUpdate<MachineModuleInfo>(),
5610 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5612 // Set the current basic block to the mbb we wish to insert the code into
5613 BB = SwitchCases[i].ThisBB;
5614 SDL.setCurrentBasicBlock(BB);
5617 SDL.visitSwitchCase(SwitchCases[i]);
5618 SDAG.setRoot(SDL.getRoot());
5619 CodeGenAndEmitDAG(SDAG);
5621 // Handle any PHI nodes in successors of this chunk, as if we were coming
5622 // from the original BB before switch expansion. Note that PHI nodes can
5623 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5624 // handle them the right number of times.
5625 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5626 for (MachineBasicBlock::iterator Phi = BB->begin();
5627 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5628 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5629 for (unsigned pn = 0; ; ++pn) {
5630 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5631 if (PHINodesToUpdate[pn].first == Phi) {
5632 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5634 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5640 // Don't process RHS if same block as LHS.
5641 if (BB == SwitchCases[i].FalseBB)
5642 SwitchCases[i].FalseBB = 0;
5644 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5645 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5646 SwitchCases[i].FalseBB = 0;
5648 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5653 /// Schedule - Pick a safe ordering for instructions for each
5654 /// target node in the graph.
5656 ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
5657 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5661 RegisterScheduler::setDefault(Ctor);
5664 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
5671 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5672 return new HazardRecognizer();
5675 //===----------------------------------------------------------------------===//
5676 // Helper functions used by the generated instruction selector.
5677 //===----------------------------------------------------------------------===//
5678 // Calls to these methods are generated by tblgen.
5680 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5681 /// the dag combiner simplified the 255, we still want to match. RHS is the
5682 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5683 /// specified in the .td file (e.g. 255).
5684 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
5685 int64_t DesiredMaskS) const {
5686 const APInt &ActualMask = RHS->getAPIntValue();
5687 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5689 // If the actual mask exactly matches, success!
5690 if (ActualMask == DesiredMask)
5693 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5694 if (ActualMask.intersects(~DesiredMask))
5697 // Otherwise, the DAG Combiner may have proven that the value coming in is
5698 // either already zero or is not demanded. Check for known zero input bits.
5699 APInt NeededMask = DesiredMask & ~ActualMask;
5700 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5703 // TODO: check to see if missing bits are just not demanded.
5705 // Otherwise, this pattern doesn't match.
5709 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5710 /// the dag combiner simplified the 255, we still want to match. RHS is the
5711 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5712 /// specified in the .td file (e.g. 255).
5713 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
5714 int64_t DesiredMaskS) const {
5715 const APInt &ActualMask = RHS->getAPIntValue();
5716 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5718 // If the actual mask exactly matches, success!
5719 if (ActualMask == DesiredMask)
5722 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5723 if (ActualMask.intersects(~DesiredMask))
5726 // Otherwise, the DAG Combiner may have proven that the value coming in is
5727 // either already zero or is not demanded. Check for known zero input bits.
5728 APInt NeededMask = DesiredMask & ~ActualMask;
5730 APInt KnownZero, KnownOne;
5731 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5733 // If all the missing bits in the or are already known to be set, match!
5734 if ((NeededMask & KnownOne) == NeededMask)
5737 // TODO: check to see if missing bits are just not demanded.
5739 // Otherwise, this pattern doesn't match.
5744 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5745 /// by tblgen. Others should not call it.
5746 void SelectionDAGISel::
5747 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SelectionDAG &DAG) {
5748 std::vector<SDValue> InOps;
5749 std::swap(InOps, Ops);
5751 Ops.push_back(InOps[0]); // input chain.
5752 Ops.push_back(InOps[1]); // input asm string.
5754 unsigned i = 2, e = InOps.size();
5755 if (InOps[e-1].getValueType() == MVT::Flag)
5756 --e; // Don't process a flag operand if it is here.
5759 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5760 if ((Flags & 7) != 4 /*MEM*/) {
5761 // Just skip over this operand, copying the operands verbatim.
5762 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5763 i += (Flags >> 3) + 1;
5765 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5766 // Otherwise, this is a memory operand. Ask the target to select it.
5767 std::vector<SDValue> SelOps;
5768 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5769 cerr << "Could not match memory address. Inline asm failure!\n";
5773 // Add this to the output node.
5774 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5775 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5777 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5782 // Add the flag input back if present.
5783 if (e != InOps.size())
5784 Ops.push_back(InOps.back());
5787 char SelectionDAGISel::ID = 0;