1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/TargetLibraryInfo.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SelectionDAGISel.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugInfo.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/IntrinsicInst.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/LLVMContext.h"
45 #include "llvm/IR/Module.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetIntrinsicInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "llvm/Target/TargetOptions.h"
57 #include "llvm/Target/TargetRegisterInfo.h"
58 #include "llvm/Target/TargetSubtargetInfo.h"
59 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
63 #define DEBUG_TYPE "isel"
65 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
66 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
67 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
68 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
69 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
70 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
71 STATISTIC(NumFastIselFailLowerArguments,
72 "Number of entry blocks where fast isel failed to lower arguments");
76 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
77 cl::desc("Enable extra verbose messages in the \"fast\" "
78 "instruction selector"));
81 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
82 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
83 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
84 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
85 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
86 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
87 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
89 // Standard binary operators...
90 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
91 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
92 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
93 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
94 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
95 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
96 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
97 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
98 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
99 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
100 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
101 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
103 // Logical operators...
104 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
105 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
106 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
108 // Memory instructions...
109 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
110 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
111 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
112 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
113 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
114 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
115 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
117 // Convert instructions...
118 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
119 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
120 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
121 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
122 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
123 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
124 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
125 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
126 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
127 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
128 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
129 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
131 // Other instructions...
132 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
133 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
134 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
135 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
136 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
137 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
138 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
139 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
140 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
141 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
142 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
143 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
144 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
145 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
146 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
148 // Intrinsic instructions...
149 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
150 STATISTIC(NumFastIselFailSAddWithOverflow,
151 "Fast isel fails on sadd.with.overflow");
152 STATISTIC(NumFastIselFailUAddWithOverflow,
153 "Fast isel fails on uadd.with.overflow");
154 STATISTIC(NumFastIselFailSSubWithOverflow,
155 "Fast isel fails on ssub.with.overflow");
156 STATISTIC(NumFastIselFailUSubWithOverflow,
157 "Fast isel fails on usub.with.overflow");
158 STATISTIC(NumFastIselFailSMulWithOverflow,
159 "Fast isel fails on smul.with.overflow");
160 STATISTIC(NumFastIselFailUMulWithOverflow,
161 "Fast isel fails on umul.with.overflow");
162 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
163 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
164 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
165 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
169 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
170 cl::desc("Enable verbose messages in the \"fast\" "
171 "instruction selector"));
172 static cl::opt<int> EnableFastISelAbort(
173 "fast-isel-abort", cl::Hidden,
174 cl::desc("Enable abort calls when \"fast\" instruction selection "
175 "fails to lower an instruction: 0 disable the abort, 1 will "
176 "abort but for args, calls and terminators, 2 will also "
177 "abort for argument lowering, and 3 will never fallback "
178 "to SelectionDAG."));
182 cl::desc("use Machine Branch Probability Info"),
183 cl::init(true), cl::Hidden);
186 static cl::opt<std::string>
187 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
188 cl::desc("Only display the basic block whose name "
189 "matches this for all view-*-dags options"));
191 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
192 cl::desc("Pop up a window to show dags before the first "
193 "dag combine pass"));
195 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before legalize types"));
198 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
199 cl::desc("Pop up a window to show dags before legalize"));
201 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
202 cl::desc("Pop up a window to show dags before the second "
203 "dag combine pass"));
205 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
206 cl::desc("Pop up a window to show dags before the post legalize types"
207 " dag combine pass"));
209 ViewISelDAGs("view-isel-dags", cl::Hidden,
210 cl::desc("Pop up a window to show isel dags as they are selected"));
212 ViewSchedDAGs("view-sched-dags", cl::Hidden,
213 cl::desc("Pop up a window to show sched dags as they are processed"));
215 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
216 cl::desc("Pop up a window to show SUnit dags after they are processed"));
218 static const bool ViewDAGCombine1 = false,
219 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
220 ViewDAGCombine2 = false,
221 ViewDAGCombineLT = false,
222 ViewISelDAGs = false, ViewSchedDAGs = false,
223 ViewSUnitDAGs = false;
226 //===---------------------------------------------------------------------===//
228 /// RegisterScheduler class - Track the registration of instruction schedulers.
230 //===---------------------------------------------------------------------===//
231 MachinePassRegistry RegisterScheduler::Registry;
233 //===---------------------------------------------------------------------===//
235 /// ISHeuristic command line option for instruction schedulers.
237 //===---------------------------------------------------------------------===//
238 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
239 RegisterPassParser<RegisterScheduler> >
240 ISHeuristic("pre-RA-sched",
241 cl::init(&createDefaultScheduler), cl::Hidden,
242 cl::desc("Instruction schedulers available (before register"
245 static RegisterScheduler
246 defaultListDAGScheduler("default", "Best scheduler for the target",
247 createDefaultScheduler);
250 //===--------------------------------------------------------------------===//
251 /// \brief This class is used by SelectionDAGISel to temporarily override
252 /// the optimization level on a per-function basis.
253 class OptLevelChanger {
254 SelectionDAGISel &IS;
255 CodeGenOpt::Level SavedOptLevel;
259 OptLevelChanger(SelectionDAGISel &ISel,
260 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
261 SavedOptLevel = IS.OptLevel;
262 if (NewOptLevel == SavedOptLevel)
264 IS.OptLevel = NewOptLevel;
265 IS.TM.setOptLevel(NewOptLevel);
266 SavedFastISel = IS.TM.Options.EnableFastISel;
267 if (NewOptLevel == CodeGenOpt::None)
268 IS.TM.setFastISel(true);
269 DEBUG(dbgs() << "\nChanging optimization level for Function "
270 << IS.MF->getFunction()->getName() << "\n");
271 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
272 << " ; After: -O" << NewOptLevel << "\n");
276 if (IS.OptLevel == SavedOptLevel)
278 DEBUG(dbgs() << "\nRestoring optimization level for Function "
279 << IS.MF->getFunction()->getName() << "\n");
280 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
281 << " ; After: -O" << SavedOptLevel << "\n");
282 IS.OptLevel = SavedOptLevel;
283 IS.TM.setOptLevel(SavedOptLevel);
284 IS.TM.setFastISel(SavedFastISel);
288 //===--------------------------------------------------------------------===//
289 /// createDefaultScheduler - This creates an instruction scheduler appropriate
291 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
292 CodeGenOpt::Level OptLevel) {
293 const TargetLowering *TLI = IS->TLI;
294 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
296 if (OptLevel == CodeGenOpt::None ||
297 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
298 TLI->getSchedulingPreference() == Sched::Source)
299 return createSourceListDAGScheduler(IS, OptLevel);
300 if (TLI->getSchedulingPreference() == Sched::RegPressure)
301 return createBURRListDAGScheduler(IS, OptLevel);
302 if (TLI->getSchedulingPreference() == Sched::Hybrid)
303 return createHybridListDAGScheduler(IS, OptLevel);
304 if (TLI->getSchedulingPreference() == Sched::VLIW)
305 return createVLIWDAGScheduler(IS, OptLevel);
306 assert(TLI->getSchedulingPreference() == Sched::ILP &&
307 "Unknown sched type!");
308 return createILPListDAGScheduler(IS, OptLevel);
312 // EmitInstrWithCustomInserter - This method should be implemented by targets
313 // that mark instructions with the 'usesCustomInserter' flag. These
314 // instructions are special in various ways, which require special support to
315 // insert. The specified MachineInstr is created but not inserted into any
316 // basic blocks, and this method is called to expand it into a sequence of
317 // instructions, potentially also creating new basic blocks and control flow.
318 // When new basic blocks are inserted and the edges from MBB to its successors
319 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
322 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
323 MachineBasicBlock *MBB) const {
325 dbgs() << "If a target marks an instruction with "
326 "'usesCustomInserter', it must implement "
327 "TargetLowering::EmitInstrWithCustomInserter!";
329 llvm_unreachable(nullptr);
332 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
333 SDNode *Node) const {
334 assert(!MI->hasPostISelHook() &&
335 "If a target marks an instruction with 'hasPostISelHook', "
336 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
339 //===----------------------------------------------------------------------===//
340 // SelectionDAGISel code
341 //===----------------------------------------------------------------------===//
343 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
344 CodeGenOpt::Level OL) :
345 MachineFunctionPass(ID), TM(tm),
346 FuncInfo(new FunctionLoweringInfo()),
347 CurDAG(new SelectionDAG(tm, OL)),
348 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
352 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
353 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
354 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
355 initializeTargetLibraryInfoWrapperPassPass(
356 *PassRegistry::getPassRegistry());
359 SelectionDAGISel::~SelectionDAGISel() {
365 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
366 AU.addRequired<AliasAnalysis>();
367 AU.addPreserved<AliasAnalysis>();
368 AU.addRequired<GCModuleInfo>();
369 AU.addPreserved<GCModuleInfo>();
370 AU.addRequired<TargetLibraryInfoWrapperPass>();
371 if (UseMBPI && OptLevel != CodeGenOpt::None)
372 AU.addRequired<BranchProbabilityInfo>();
373 MachineFunctionPass::getAnalysisUsage(AU);
376 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
377 /// may trap on it. In this case we have to split the edge so that the path
378 /// through the predecessor block that doesn't go to the phi block doesn't
379 /// execute the possibly trapping instruction.
381 /// This is required for correctness, so it must be done at -O0.
383 static void SplitCriticalSideEffectEdges(Function &Fn, AliasAnalysis *AA) {
384 // Loop for blocks with phi nodes.
385 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
386 PHINode *PN = dyn_cast<PHINode>(BB->begin());
390 // For each block with a PHI node, check to see if any of the input values
391 // are potentially trapping constant expressions. Constant expressions are
392 // the only potentially trapping value that can occur as the argument to a
394 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
395 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
396 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
397 if (!CE || !CE->canTrap()) continue;
399 // The only case we have to worry about is when the edge is critical.
400 // Since this block has a PHI Node, we assume it has multiple input
401 // edges: check to see if the pred has multiple successors.
402 BasicBlock *Pred = PN->getIncomingBlock(i);
403 if (Pred->getTerminator()->getNumSuccessors() == 1)
406 // Okay, we have to split this edge.
408 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
409 CriticalEdgeSplittingOptions(AA).setMergeIdenticalEdges());
415 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
416 // Do some sanity-checking on the command-line options.
417 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
418 "-fast-isel-verbose requires -fast-isel");
419 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
420 "-fast-isel-abort > 0 requires -fast-isel");
422 const Function &Fn = *mf.getFunction();
425 // Reset the target options before resetting the optimization
427 // FIXME: This is a horrible hack and should be processed via
428 // codegen looking at the optimization level explicitly when
429 // it wants to look at it.
430 TM.resetTargetOptions(Fn);
431 // Reset OptLevel to None for optnone functions.
432 CodeGenOpt::Level NewOptLevel = OptLevel;
433 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
434 NewOptLevel = CodeGenOpt::None;
435 OptLevelChanger OLC(*this, NewOptLevel);
437 TII = MF->getSubtarget().getInstrInfo();
438 TLI = MF->getSubtarget().getTargetLowering();
439 RegInfo = &MF->getRegInfo();
440 AA = &getAnalysis<AliasAnalysis>();
441 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
442 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
444 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
446 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), AA);
449 FuncInfo->set(Fn, *MF, CurDAG);
451 if (UseMBPI && OptLevel != CodeGenOpt::None)
452 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
454 FuncInfo->BPI = nullptr;
456 SDB->init(GFI, *AA, LibInfo);
458 MF->setHasInlineAsm(false);
460 SelectAllBasicBlocks(Fn);
462 // If the first basic block in the function has live ins that need to be
463 // copied into vregs, emit the copies into the top of the block before
464 // emitting the code for the block.
465 MachineBasicBlock *EntryMBB = MF->begin();
466 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
467 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
469 DenseMap<unsigned, unsigned> LiveInMap;
470 if (!FuncInfo->ArgDbgValues.empty())
471 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
472 E = RegInfo->livein_end(); LI != E; ++LI)
474 LiveInMap.insert(std::make_pair(LI->first, LI->second));
476 // Insert DBG_VALUE instructions for function arguments to the entry block.
477 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
478 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
479 bool hasFI = MI->getOperand(0).isFI();
481 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
482 if (TargetRegisterInfo::isPhysicalRegister(Reg))
483 EntryMBB->insert(EntryMBB->begin(), MI);
485 MachineInstr *Def = RegInfo->getVRegDef(Reg);
487 MachineBasicBlock::iterator InsertPos = Def;
488 // FIXME: VR def may not be in entry block.
489 Def->getParent()->insert(std::next(InsertPos), MI);
491 DEBUG(dbgs() << "Dropping debug info for dead vreg"
492 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
495 // If Reg is live-in then update debug info to track its copy in a vreg.
496 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
497 if (LDI != LiveInMap.end()) {
498 assert(!hasFI && "There's no handling of frame pointer updating here yet "
500 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
501 MachineBasicBlock::iterator InsertPos = Def;
502 const MDNode *Variable = MI->getDebugVariable();
503 const MDNode *Expr = MI->getDebugExpression();
504 DebugLoc DL = MI->getDebugLoc();
505 bool IsIndirect = MI->isIndirectDebugValue();
506 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
507 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
508 "Expected inlined-at fields to agree");
509 // Def is never a terminator here, so it is ok to increment InsertPos.
510 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
511 IsIndirect, LDI->second, Offset, Variable, Expr);
513 // If this vreg is directly copied into an exported register then
514 // that COPY instructions also need DBG_VALUE, if it is the only
515 // user of LDI->second.
516 MachineInstr *CopyUseMI = nullptr;
517 for (MachineRegisterInfo::use_instr_iterator
518 UI = RegInfo->use_instr_begin(LDI->second),
519 E = RegInfo->use_instr_end(); UI != E; ) {
520 MachineInstr *UseMI = &*(UI++);
521 if (UseMI->isDebugValue()) continue;
522 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
523 CopyUseMI = UseMI; continue;
525 // Otherwise this is another use or second copy use.
526 CopyUseMI = nullptr; break;
529 // Use MI's debug location, which describes where Variable was
530 // declared, rather than whatever is attached to CopyUseMI.
531 MachineInstr *NewMI =
532 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
533 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
534 MachineBasicBlock::iterator Pos = CopyUseMI;
535 EntryMBB->insertAfter(Pos, NewMI);
540 // Determine if there are any calls in this machine function.
541 MachineFrameInfo *MFI = MF->getFrameInfo();
542 for (const auto &MBB : *MF) {
543 if (MFI->hasCalls() && MF->hasInlineAsm())
546 for (const auto &MI : MBB) {
547 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
548 if ((MCID.isCall() && !MCID.isReturn()) ||
549 MI.isStackAligningInlineAsm()) {
550 MFI->setHasCalls(true);
552 if (MI.isInlineAsm()) {
553 MF->setHasInlineAsm(true);
558 // Determine if there is a call to setjmp in the machine function.
559 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
561 // Replace forward-declared registers with the registers containing
562 // the desired value.
563 MachineRegisterInfo &MRI = MF->getRegInfo();
564 for (DenseMap<unsigned, unsigned>::iterator
565 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
567 unsigned From = I->first;
568 unsigned To = I->second;
569 // If To is also scheduled to be replaced, find what its ultimate
572 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
576 // Make sure the new register has a sufficiently constrained register class.
577 if (TargetRegisterInfo::isVirtualRegister(From) &&
578 TargetRegisterInfo::isVirtualRegister(To))
579 MRI.constrainRegClass(To, MRI.getRegClass(From));
583 // Replacing one register with another won't touch the kill flags.
584 // We need to conservatively clear the kill flags as a kill on the old
585 // register might dominate existing uses of the new register.
586 if (!MRI.use_empty(To))
587 MRI.clearKillFlags(From);
588 MRI.replaceRegWith(From, To);
591 // Freeze the set of reserved registers now that MachineFrameInfo has been
592 // set up. All the information required by getReservedRegs() should be
594 MRI.freezeReservedRegs(*MF);
596 // Release function-specific state. SDB and CurDAG are already cleared
600 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
601 DEBUG(MF->print(dbgs()));
606 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
607 BasicBlock::const_iterator End,
609 // Lower the instructions. If a call is emitted as a tail call, cease emitting
610 // nodes for this block.
611 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
614 // Make sure the root of the DAG is up-to-date.
615 CurDAG->setRoot(SDB->getControlRoot());
616 HadTailCall = SDB->HasTailCall;
619 // Final step, emit the lowered DAG as machine code.
623 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
624 SmallPtrSet<SDNode*, 128> VisitedNodes;
625 SmallVector<SDNode*, 128> Worklist;
627 Worklist.push_back(CurDAG->getRoot().getNode());
633 SDNode *N = Worklist.pop_back_val();
635 // If we've already seen this node, ignore it.
636 if (!VisitedNodes.insert(N).second)
639 // Otherwise, add all chain operands to the worklist.
640 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
641 if (N->getOperand(i).getValueType() == MVT::Other)
642 Worklist.push_back(N->getOperand(i).getNode());
644 // If this is a CopyToReg with a vreg dest, process it.
645 if (N->getOpcode() != ISD::CopyToReg)
648 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
649 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
652 // Ignore non-scalar or non-integer values.
653 SDValue Src = N->getOperand(2);
654 EVT SrcVT = Src.getValueType();
655 if (!SrcVT.isInteger() || SrcVT.isVector())
658 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
659 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
660 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
661 } while (!Worklist.empty());
664 void SelectionDAGISel::CodeGenAndEmitDAG() {
665 std::string GroupName;
666 if (TimePassesIsEnabled)
667 GroupName = "Instruction Selection and Scheduling";
668 std::string BlockName;
669 int BlockNumber = -1;
671 bool MatchFilterBB = false; (void)MatchFilterBB;
673 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
674 FilterDAGBasicBlockName ==
675 FuncInfo->MBB->getBasicBlock()->getName().str());
678 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
679 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
683 BlockNumber = FuncInfo->MBB->getNumber();
685 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
687 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
688 << " '" << BlockName << "'\n"; CurDAG->dump());
690 if (ViewDAGCombine1 && MatchFilterBB)
691 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
693 // Run the DAG combiner in pre-legalize mode.
695 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
696 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
699 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
700 << " '" << BlockName << "'\n"; CurDAG->dump());
702 // Second step, hack on the DAG until it only uses operations and types that
703 // the target supports.
704 if (ViewLegalizeTypesDAGs && MatchFilterBB)
705 CurDAG->viewGraph("legalize-types input for " + BlockName);
709 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
710 Changed = CurDAG->LegalizeTypes();
713 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
714 << " '" << BlockName << "'\n"; CurDAG->dump());
716 CurDAG->NewNodesMustHaveLegalTypes = true;
719 if (ViewDAGCombineLT && MatchFilterBB)
720 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
722 // Run the DAG combiner in post-type-legalize mode.
724 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
725 TimePassesIsEnabled);
726 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
729 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
730 << " '" << BlockName << "'\n"; CurDAG->dump());
735 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
736 Changed = CurDAG->LegalizeVectors();
741 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
742 CurDAG->LegalizeTypes();
745 if (ViewDAGCombineLT && MatchFilterBB)
746 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
748 // Run the DAG combiner in post-type-legalize mode.
750 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
751 TimePassesIsEnabled);
752 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
755 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
756 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
759 if (ViewLegalizeDAGs && MatchFilterBB)
760 CurDAG->viewGraph("legalize input for " + BlockName);
763 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
767 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
768 << " '" << BlockName << "'\n"; CurDAG->dump());
770 if (ViewDAGCombine2 && MatchFilterBB)
771 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
773 // Run the DAG combiner in post-legalize mode.
775 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
776 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
779 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
780 << " '" << BlockName << "'\n"; CurDAG->dump());
782 if (OptLevel != CodeGenOpt::None)
783 ComputeLiveOutVRegInfo();
785 if (ViewISelDAGs && MatchFilterBB)
786 CurDAG->viewGraph("isel input for " + BlockName);
788 // Third, instruction select all of the operations to machine code, adding the
789 // code to the MachineBasicBlock.
791 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
792 DoInstructionSelection();
795 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
796 << " '" << BlockName << "'\n"; CurDAG->dump());
798 if (ViewSchedDAGs && MatchFilterBB)
799 CurDAG->viewGraph("scheduler input for " + BlockName);
801 // Schedule machine code.
802 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
804 NamedRegionTimer T("Instruction Scheduling", GroupName,
805 TimePassesIsEnabled);
806 Scheduler->Run(CurDAG, FuncInfo->MBB);
809 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
811 // Emit machine code to BB. This can change 'BB' to the last block being
813 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
815 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
817 // FuncInfo->InsertPt is passed by reference and set to the end of the
818 // scheduled instructions.
819 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
822 // If the block was split, make sure we update any references that are used to
823 // update PHI nodes later on.
824 if (FirstMBB != LastMBB)
825 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
827 // Free the scheduler state.
829 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
830 TimePassesIsEnabled);
834 // Free the SelectionDAG state, now that we're finished with it.
839 /// ISelUpdater - helper class to handle updates of the instruction selection
841 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
842 SelectionDAG::allnodes_iterator &ISelPosition;
844 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
845 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
847 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
848 /// deleted is the current ISelPosition node, update ISelPosition.
850 void NodeDeleted(SDNode *N, SDNode *E) override {
851 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
855 } // end anonymous namespace
857 void SelectionDAGISel::DoInstructionSelection() {
858 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
859 << FuncInfo->MBB->getNumber()
860 << " '" << FuncInfo->MBB->getName() << "'\n");
864 // Select target instructions for the DAG.
866 // Number all nodes with a topological order and set DAGSize.
867 DAGSize = CurDAG->AssignTopologicalOrder();
869 // Create a dummy node (which is not added to allnodes), that adds
870 // a reference to the root node, preventing it from being deleted,
871 // and tracking any changes of the root.
872 HandleSDNode Dummy(CurDAG->getRoot());
873 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
876 // Make sure that ISelPosition gets properly updated when nodes are deleted
877 // in calls made from this function.
878 ISelUpdater ISU(*CurDAG, ISelPosition);
880 // The AllNodes list is now topological-sorted. Visit the
881 // nodes by starting at the end of the list (the root of the
882 // graph) and preceding back toward the beginning (the entry
884 while (ISelPosition != CurDAG->allnodes_begin()) {
885 SDNode *Node = --ISelPosition;
886 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
887 // but there are currently some corner cases that it misses. Also, this
888 // makes it theoretically possible to disable the DAGCombiner.
889 if (Node->use_empty())
892 SDNode *ResNode = Select(Node);
894 // FIXME: This is pretty gross. 'Select' should be changed to not return
895 // anything at all and this code should be nuked with a tactical strike.
897 // If node should not be replaced, continue with the next one.
898 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
902 ReplaceUses(Node, ResNode);
905 // If after the replacement this node is not used any more,
906 // remove this dead node.
907 if (Node->use_empty()) // Don't delete EntryToken, etc.
908 CurDAG->RemoveDeadNode(Node);
911 CurDAG->setRoot(Dummy.getValue());
914 DEBUG(dbgs() << "===== Instruction selection ends:\n");
916 PostprocessISelDAG();
919 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
920 /// do other setup for EH landing-pad blocks.
921 bool SelectionDAGISel::PrepareEHLandingPad() {
922 MachineBasicBlock *MBB = FuncInfo->MBB;
924 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
926 // Add a label to mark the beginning of the landing pad. Deletion of the
927 // landing pad can thus be detected via the MachineModuleInfo.
928 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
930 // Assign the call site to the landing pad's begin label.
931 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
933 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
934 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
937 // If this is an MSVC-style personality function, we need to split the landing
938 // pad into several BBs.
939 const BasicBlock *LLVMBB = MBB->getBasicBlock();
940 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
941 MF->getMMI().addPersonality(
942 MBB, cast<Function>(LPadInst->getPersonalityFn()->stripPointerCasts()));
943 EHPersonality Personality = MF->getMMI().getPersonalityType();
945 if (isMSVCEHPersonality(Personality)) {
946 SmallVector<MachineBasicBlock *, 4> ClauseBBs;
947 const IntrinsicInst *ActionsCall =
948 dyn_cast<IntrinsicInst>(LLVMBB->getFirstInsertionPt());
949 // Get all invoke BBs that unwind to this landingpad.
950 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
952 if (ActionsCall && ActionsCall->getIntrinsicID() == Intrinsic::eh_actions) {
953 // If this is a call to llvm.eh.actions followed by indirectbr, then we've
954 // run WinEHPrepare, and we should remove this block from the machine CFG.
955 // Mark the targets of the indirectbr as landingpads instead.
956 for (const BasicBlock *LLVMSucc : successors(LLVMBB)) {
957 MachineBasicBlock *ClauseBB = FuncInfo->MBBMap[LLVMSucc];
958 // Add the edge from the invoke to the clause.
959 for (MachineBasicBlock *InvokeBB : InvokeBBs)
960 InvokeBB->addSuccessor(ClauseBB);
962 // Mark the clause as a landing pad or MI passes will delete it.
963 ClauseBB->setIsLandingPad();
967 // Remove the edge from the invoke to the lpad.
968 for (MachineBasicBlock *InvokeBB : InvokeBBs)
969 InvokeBB->removeSuccessor(MBB);
971 // Don't select instructions for the landingpad.
975 // Mark exception register as live in.
976 if (unsigned Reg = TLI->getExceptionPointerRegister())
977 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
979 // Mark exception selector register as live in.
980 if (unsigned Reg = TLI->getExceptionSelectorRegister())
981 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
986 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
987 /// side-effect free and is either dead or folded into a generated instruction.
988 /// Return false if it needs to be emitted.
989 static bool isFoldedOrDeadInstruction(const Instruction *I,
990 FunctionLoweringInfo *FuncInfo) {
991 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
992 !isa<TerminatorInst>(I) && // Terminators aren't folded.
993 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
994 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
995 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
999 // Collect per Instruction statistics for fast-isel misses. Only those
1000 // instructions that cause the bail are accounted for. It does not account for
1001 // instructions higher in the block. Thus, summing the per instructions stats
1002 // will not add up to what is reported by NumFastIselFailures.
1003 static void collectFailStats(const Instruction *I) {
1004 switch (I->getOpcode()) {
1005 default: assert (0 && "<Invalid operator> ");
1008 case Instruction::Ret: NumFastIselFailRet++; return;
1009 case Instruction::Br: NumFastIselFailBr++; return;
1010 case Instruction::Switch: NumFastIselFailSwitch++; return;
1011 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1012 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1013 case Instruction::Resume: NumFastIselFailResume++; return;
1014 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1016 // Standard binary operators...
1017 case Instruction::Add: NumFastIselFailAdd++; return;
1018 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1019 case Instruction::Sub: NumFastIselFailSub++; return;
1020 case Instruction::FSub: NumFastIselFailFSub++; return;
1021 case Instruction::Mul: NumFastIselFailMul++; return;
1022 case Instruction::FMul: NumFastIselFailFMul++; return;
1023 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1024 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1025 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1026 case Instruction::URem: NumFastIselFailURem++; return;
1027 case Instruction::SRem: NumFastIselFailSRem++; return;
1028 case Instruction::FRem: NumFastIselFailFRem++; return;
1030 // Logical operators...
1031 case Instruction::And: NumFastIselFailAnd++; return;
1032 case Instruction::Or: NumFastIselFailOr++; return;
1033 case Instruction::Xor: NumFastIselFailXor++; return;
1035 // Memory instructions...
1036 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1037 case Instruction::Load: NumFastIselFailLoad++; return;
1038 case Instruction::Store: NumFastIselFailStore++; return;
1039 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1040 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1041 case Instruction::Fence: NumFastIselFailFence++; return;
1042 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1044 // Convert instructions...
1045 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1046 case Instruction::ZExt: NumFastIselFailZExt++; return;
1047 case Instruction::SExt: NumFastIselFailSExt++; return;
1048 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1049 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1050 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1051 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1052 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1053 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1054 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1055 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1056 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1058 // Other instructions...
1059 case Instruction::ICmp: NumFastIselFailICmp++; return;
1060 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1061 case Instruction::PHI: NumFastIselFailPHI++; return;
1062 case Instruction::Select: NumFastIselFailSelect++; return;
1063 case Instruction::Call: {
1064 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1065 switch (Intrinsic->getIntrinsicID()) {
1067 NumFastIselFailIntrinsicCall++; return;
1068 case Intrinsic::sadd_with_overflow:
1069 NumFastIselFailSAddWithOverflow++; return;
1070 case Intrinsic::uadd_with_overflow:
1071 NumFastIselFailUAddWithOverflow++; return;
1072 case Intrinsic::ssub_with_overflow:
1073 NumFastIselFailSSubWithOverflow++; return;
1074 case Intrinsic::usub_with_overflow:
1075 NumFastIselFailUSubWithOverflow++; return;
1076 case Intrinsic::smul_with_overflow:
1077 NumFastIselFailSMulWithOverflow++; return;
1078 case Intrinsic::umul_with_overflow:
1079 NumFastIselFailUMulWithOverflow++; return;
1080 case Intrinsic::frameaddress:
1081 NumFastIselFailFrameaddress++; return;
1082 case Intrinsic::sqrt:
1083 NumFastIselFailSqrt++; return;
1084 case Intrinsic::experimental_stackmap:
1085 NumFastIselFailStackMap++; return;
1086 case Intrinsic::experimental_patchpoint_void: // fall-through
1087 case Intrinsic::experimental_patchpoint_i64:
1088 NumFastIselFailPatchPoint++; return;
1091 NumFastIselFailCall++;
1094 case Instruction::Shl: NumFastIselFailShl++; return;
1095 case Instruction::LShr: NumFastIselFailLShr++; return;
1096 case Instruction::AShr: NumFastIselFailAShr++; return;
1097 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1098 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1099 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1100 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1101 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1102 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1103 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1108 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1109 // Initialize the Fast-ISel state, if needed.
1110 FastISel *FastIS = nullptr;
1111 if (TM.Options.EnableFastISel)
1112 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1114 // Iterate over all basic blocks in the function.
1115 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1116 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1117 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1118 const BasicBlock *LLVMBB = *I;
1120 if (OptLevel != CodeGenOpt::None) {
1121 bool AllPredsVisited = true;
1122 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1124 if (!FuncInfo->VisitedBBs.count(*PI)) {
1125 AllPredsVisited = false;
1130 if (AllPredsVisited) {
1131 for (BasicBlock::const_iterator I = LLVMBB->begin();
1132 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1133 FuncInfo->ComputePHILiveOutRegInfo(PN);
1135 for (BasicBlock::const_iterator I = LLVMBB->begin();
1136 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1137 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1140 FuncInfo->VisitedBBs.insert(LLVMBB);
1143 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1144 BasicBlock::const_iterator const End = LLVMBB->end();
1145 BasicBlock::const_iterator BI = End;
1147 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1148 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1150 // Setup an EH landing-pad block.
1151 FuncInfo->ExceptionPointerVirtReg = 0;
1152 FuncInfo->ExceptionSelectorVirtReg = 0;
1153 if (LLVMBB->isLandingPad())
1154 if (!PrepareEHLandingPad())
1157 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1159 FastIS->startNewBlock();
1161 // Emit code for any incoming arguments. This must happen before
1162 // beginning FastISel on the entry block.
1163 if (LLVMBB == &Fn.getEntryBlock()) {
1166 // Lower any arguments needed in this block if this is the entry block.
1167 if (!FastIS->lowerArguments()) {
1168 // Fast isel failed to lower these arguments
1169 ++NumFastIselFailLowerArguments;
1170 if (EnableFastISelAbort > 1)
1171 report_fatal_error("FastISel didn't lower all arguments");
1173 // Use SelectionDAG argument lowering
1175 CurDAG->setRoot(SDB->getControlRoot());
1177 CodeGenAndEmitDAG();
1180 // If we inserted any instructions at the beginning, make a note of
1181 // where they are, so we can be sure to emit subsequent instructions
1183 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1184 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1186 FastIS->setLastLocalValue(nullptr);
1189 unsigned NumFastIselRemaining = std::distance(Begin, End);
1190 // Do FastISel on as many instructions as possible.
1191 for (; BI != Begin; --BI) {
1192 const Instruction *Inst = std::prev(BI);
1194 // If we no longer require this instruction, skip it.
1195 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1196 --NumFastIselRemaining;
1200 // Bottom-up: reset the insert pos at the top, after any local-value
1202 FastIS->recomputeInsertPt();
1204 // Try to select the instruction with FastISel.
1205 if (FastIS->selectInstruction(Inst)) {
1206 --NumFastIselRemaining;
1207 ++NumFastIselSuccess;
1208 // If fast isel succeeded, skip over all the folded instructions, and
1209 // then see if there is a load right before the selected instructions.
1210 // Try to fold the load if so.
1211 const Instruction *BeforeInst = Inst;
1212 while (BeforeInst != Begin) {
1213 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1214 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1217 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1218 BeforeInst->hasOneUse() &&
1219 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1220 // If we succeeded, don't re-select the load.
1221 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1222 --NumFastIselRemaining;
1223 ++NumFastIselSuccess;
1229 if (EnableFastISelVerbose2)
1230 collectFailStats(Inst);
1233 // Then handle certain instructions as single-LLVM-Instruction blocks.
1234 if (isa<CallInst>(Inst)) {
1236 if (EnableFastISelVerbose || EnableFastISelAbort) {
1237 dbgs() << "FastISel missed call: ";
1240 if (EnableFastISelAbort > 2)
1241 // FastISel selector couldn't handle something and bailed.
1242 // For the purpose of debugging, just abort.
1243 report_fatal_error("FastISel didn't select the entire block");
1245 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1246 unsigned &R = FuncInfo->ValueMap[Inst];
1248 R = FuncInfo->CreateRegs(Inst->getType());
1251 bool HadTailCall = false;
1252 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1253 SelectBasicBlock(Inst, BI, HadTailCall);
1255 // If the call was emitted as a tail call, we're done with the block.
1256 // We also need to delete any previously emitted instructions.
1258 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1263 // Recompute NumFastIselRemaining as Selection DAG instruction
1264 // selection may have handled the call, input args, etc.
1265 unsigned RemainingNow = std::distance(Begin, BI);
1266 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1267 NumFastIselRemaining = RemainingNow;
1271 bool ShouldAbort = EnableFastISelAbort;
1272 if (EnableFastISelVerbose || EnableFastISelAbort) {
1273 if (isa<TerminatorInst>(Inst)) {
1274 // Use a different message for terminator misses.
1275 dbgs() << "FastISel missed terminator: ";
1276 // Don't abort unless for terminator unless the level is really high
1277 ShouldAbort = (EnableFastISelAbort > 2);
1279 dbgs() << "FastISel miss: ";
1284 // FastISel selector couldn't handle something and bailed.
1285 // For the purpose of debugging, just abort.
1286 report_fatal_error("FastISel didn't select the entire block");
1288 NumFastIselFailures += NumFastIselRemaining;
1292 FastIS->recomputeInsertPt();
1294 // Lower any arguments needed in this block if this is the entry block.
1295 if (LLVMBB == &Fn.getEntryBlock()) {
1304 ++NumFastIselBlocks;
1307 // Run SelectionDAG instruction selection on the remainder of the block
1308 // not handled by FastISel. If FastISel is not run, this is the entire
1311 SelectBasicBlock(Begin, BI, HadTailCall);
1315 FuncInfo->PHINodesToUpdate.clear();
1319 SDB->clearDanglingDebugInfo();
1320 SDB->SPDescriptor.resetPerFunctionState();
1323 /// Given that the input MI is before a partial terminator sequence TSeq, return
1324 /// true if M + TSeq also a partial terminator sequence.
1326 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1327 /// lowering copy vregs into physical registers, which are then passed into
1328 /// terminator instructors so we can satisfy ABI constraints. A partial
1329 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1330 /// may be the whole terminator sequence).
1331 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1332 // If we do not have a copy or an implicit def, we return true if and only if
1333 // MI is a debug value.
1334 if (!MI->isCopy() && !MI->isImplicitDef())
1335 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1336 // physical registers if there is debug info associated with the terminator
1337 // of our mbb. We want to include said debug info in our terminator
1338 // sequence, so we return true in that case.
1339 return MI->isDebugValue();
1341 // We have left the terminator sequence if we are not doing one of the
1344 // 1. Copying a vreg into a physical register.
1345 // 2. Copying a vreg into a vreg.
1346 // 3. Defining a register via an implicit def.
1348 // OPI should always be a register definition...
1349 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1350 if (!OPI->isReg() || !OPI->isDef())
1353 // Defining any register via an implicit def is always ok.
1354 if (MI->isImplicitDef())
1357 // Grab the copy source...
1358 MachineInstr::const_mop_iterator OPI2 = OPI;
1360 assert(OPI2 != MI->operands_end()
1361 && "Should have a copy implying we should have 2 arguments.");
1363 // Make sure that the copy dest is not a vreg when the copy source is a
1364 // physical register.
1365 if (!OPI2->isReg() ||
1366 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1367 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1373 /// Find the split point at which to splice the end of BB into its success stack
1374 /// protector check machine basic block.
1376 /// On many platforms, due to ABI constraints, terminators, even before register
1377 /// allocation, use physical registers. This creates an issue for us since
1378 /// physical registers at this point can not travel across basic
1379 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1380 /// when they enter functions and moves them through a sequence of copies back
1381 /// into the physical registers right before the terminator creating a
1382 /// ``Terminator Sequence''. This function is searching for the beginning of the
1383 /// terminator sequence so that we can ensure that we splice off not just the
1384 /// terminator, but additionally the copies that move the vregs into the
1385 /// physical registers.
1386 static MachineBasicBlock::iterator
1387 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1388 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1390 if (SplitPoint == BB->begin())
1393 MachineBasicBlock::iterator Start = BB->begin();
1394 MachineBasicBlock::iterator Previous = SplitPoint;
1397 while (MIIsInTerminatorSequence(Previous)) {
1398 SplitPoint = Previous;
1399 if (Previous == Start)
1408 SelectionDAGISel::FinishBasicBlock() {
1410 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1411 << FuncInfo->PHINodesToUpdate.size() << "\n";
1412 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1413 dbgs() << "Node " << i << " : ("
1414 << FuncInfo->PHINodesToUpdate[i].first
1415 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1417 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1418 // PHI nodes in successors.
1419 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1420 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1421 assert(PHI->isPHI() &&
1422 "This is not a machine PHI node that we are updating!");
1423 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1425 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1428 // Handle stack protector.
1429 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1430 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1431 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1433 // Find the split point to split the parent mbb. At the same time copy all
1434 // physical registers used in the tail of parent mbb into virtual registers
1435 // before the split point and back into physical registers after the split
1436 // point. This prevents us needing to deal with Live-ins and many other
1437 // register allocation issues caused by us splitting the parent mbb. The
1438 // register allocator will clean up said virtual copies later on.
1439 MachineBasicBlock::iterator SplitPoint =
1440 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1442 // Splice the terminator of ParentMBB into SuccessMBB.
1443 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1447 // Add compare/jump on neq/jump to the parent BB.
1448 FuncInfo->MBB = ParentMBB;
1449 FuncInfo->InsertPt = ParentMBB->end();
1450 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1451 CurDAG->setRoot(SDB->getRoot());
1453 CodeGenAndEmitDAG();
1455 // CodeGen Failure MBB if we have not codegened it yet.
1456 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1457 if (!FailureMBB->size()) {
1458 FuncInfo->MBB = FailureMBB;
1459 FuncInfo->InsertPt = FailureMBB->end();
1460 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1461 CurDAG->setRoot(SDB->getRoot());
1463 CodeGenAndEmitDAG();
1466 // Clear the Per-BB State.
1467 SDB->SPDescriptor.resetPerBBState();
1470 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1471 // Lower header first, if it wasn't already lowered
1472 if (!SDB->BitTestCases[i].Emitted) {
1473 // Set the current basic block to the mbb we wish to insert the code into
1474 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1475 FuncInfo->InsertPt = FuncInfo->MBB->end();
1477 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1478 CurDAG->setRoot(SDB->getRoot());
1480 CodeGenAndEmitDAG();
1483 uint32_t UnhandledWeight = 0;
1484 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1485 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1487 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1488 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1489 // Set the current basic block to the mbb we wish to insert the code into
1490 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1491 FuncInfo->InsertPt = FuncInfo->MBB->end();
1494 SDB->visitBitTestCase(SDB->BitTestCases[i],
1495 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1497 SDB->BitTestCases[i].Reg,
1498 SDB->BitTestCases[i].Cases[j],
1501 SDB->visitBitTestCase(SDB->BitTestCases[i],
1502 SDB->BitTestCases[i].Default,
1504 SDB->BitTestCases[i].Reg,
1505 SDB->BitTestCases[i].Cases[j],
1509 CurDAG->setRoot(SDB->getRoot());
1511 CodeGenAndEmitDAG();
1515 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1517 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1518 MachineBasicBlock *PHIBB = PHI->getParent();
1519 assert(PHI->isPHI() &&
1520 "This is not a machine PHI node that we are updating!");
1521 // This is "default" BB. We have two jumps to it. From "header" BB and
1522 // from last "case" BB.
1523 if (PHIBB == SDB->BitTestCases[i].Default)
1524 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1525 .addMBB(SDB->BitTestCases[i].Parent)
1526 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1527 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1528 // One of "cases" BB.
1529 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1531 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1532 if (cBB->isSuccessor(PHIBB))
1533 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1537 SDB->BitTestCases.clear();
1539 // If the JumpTable record is filled in, then we need to emit a jump table.
1540 // Updating the PHI nodes is tricky in this case, since we need to determine
1541 // whether the PHI is a successor of the range check MBB or the jump table MBB
1542 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1543 // Lower header first, if it wasn't already lowered
1544 if (!SDB->JTCases[i].first.Emitted) {
1545 // Set the current basic block to the mbb we wish to insert the code into
1546 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1547 FuncInfo->InsertPt = FuncInfo->MBB->end();
1549 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1551 CurDAG->setRoot(SDB->getRoot());
1553 CodeGenAndEmitDAG();
1556 // Set the current basic block to the mbb we wish to insert the code into
1557 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1558 FuncInfo->InsertPt = FuncInfo->MBB->end();
1560 SDB->visitJumpTable(SDB->JTCases[i].second);
1561 CurDAG->setRoot(SDB->getRoot());
1563 CodeGenAndEmitDAG();
1566 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1568 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1569 MachineBasicBlock *PHIBB = PHI->getParent();
1570 assert(PHI->isPHI() &&
1571 "This is not a machine PHI node that we are updating!");
1572 // "default" BB. We can go there only from header BB.
1573 if (PHIBB == SDB->JTCases[i].second.Default)
1574 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1575 .addMBB(SDB->JTCases[i].first.HeaderBB);
1576 // JT BB. Just iterate over successors here
1577 if (FuncInfo->MBB->isSuccessor(PHIBB))
1578 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1581 SDB->JTCases.clear();
1583 // If we generated any switch lowering information, build and codegen any
1584 // additional DAGs necessary.
1585 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1586 // Set the current basic block to the mbb we wish to insert the code into
1587 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1588 FuncInfo->InsertPt = FuncInfo->MBB->end();
1590 // Determine the unique successors.
1591 SmallVector<MachineBasicBlock *, 2> Succs;
1592 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1593 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1594 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1596 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1597 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1598 CurDAG->setRoot(SDB->getRoot());
1600 CodeGenAndEmitDAG();
1602 // Remember the last block, now that any splitting is done, for use in
1603 // populating PHI nodes in successors.
1604 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1606 // Handle any PHI nodes in successors of this chunk, as if we were coming
1607 // from the original BB before switch expansion. Note that PHI nodes can
1608 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1609 // handle them the right number of times.
1610 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1611 FuncInfo->MBB = Succs[i];
1612 FuncInfo->InsertPt = FuncInfo->MBB->end();
1613 // FuncInfo->MBB may have been removed from the CFG if a branch was
1615 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1616 for (MachineBasicBlock::iterator
1617 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1618 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1619 MachineInstrBuilder PHI(*MF, MBBI);
1620 // This value for this PHI node is recorded in PHINodesToUpdate.
1621 for (unsigned pn = 0; ; ++pn) {
1622 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1623 "Didn't find PHI entry!");
1624 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1625 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1633 SDB->SwitchCases.clear();
1637 /// Create the scheduler. If a specific scheduler was specified
1638 /// via the SchedulerRegistry, use it, otherwise select the
1639 /// one preferred by the target.
1641 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1642 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1646 RegisterScheduler::setDefault(Ctor);
1649 return Ctor(this, OptLevel);
1652 //===----------------------------------------------------------------------===//
1653 // Helper functions used by the generated instruction selector.
1654 //===----------------------------------------------------------------------===//
1655 // Calls to these methods are generated by tblgen.
1657 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1658 /// the dag combiner simplified the 255, we still want to match. RHS is the
1659 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1660 /// specified in the .td file (e.g. 255).
1661 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1662 int64_t DesiredMaskS) const {
1663 const APInt &ActualMask = RHS->getAPIntValue();
1664 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1666 // If the actual mask exactly matches, success!
1667 if (ActualMask == DesiredMask)
1670 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1671 if (ActualMask.intersects(~DesiredMask))
1674 // Otherwise, the DAG Combiner may have proven that the value coming in is
1675 // either already zero or is not demanded. Check for known zero input bits.
1676 APInt NeededMask = DesiredMask & ~ActualMask;
1677 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1680 // TODO: check to see if missing bits are just not demanded.
1682 // Otherwise, this pattern doesn't match.
1686 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1687 /// the dag combiner simplified the 255, we still want to match. RHS is the
1688 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1689 /// specified in the .td file (e.g. 255).
1690 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1691 int64_t DesiredMaskS) const {
1692 const APInt &ActualMask = RHS->getAPIntValue();
1693 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1695 // If the actual mask exactly matches, success!
1696 if (ActualMask == DesiredMask)
1699 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1700 if (ActualMask.intersects(~DesiredMask))
1703 // Otherwise, the DAG Combiner may have proven that the value coming in is
1704 // either already zero or is not demanded. Check for known zero input bits.
1705 APInt NeededMask = DesiredMask & ~ActualMask;
1707 APInt KnownZero, KnownOne;
1708 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1710 // If all the missing bits in the or are already known to be set, match!
1711 if ((NeededMask & KnownOne) == NeededMask)
1714 // TODO: check to see if missing bits are just not demanded.
1716 // Otherwise, this pattern doesn't match.
1720 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1721 /// by tblgen. Others should not call it.
1722 void SelectionDAGISel::
1723 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL) {
1724 std::vector<SDValue> InOps;
1725 std::swap(InOps, Ops);
1727 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1728 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1729 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1730 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1732 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1733 if (InOps[e-1].getValueType() == MVT::Glue)
1734 --e; // Don't process a glue operand if it is here.
1737 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1738 if (!InlineAsm::isMemKind(Flags)) {
1739 // Just skip over this operand, copying the operands verbatim.
1740 Ops.insert(Ops.end(), InOps.begin()+i,
1741 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1742 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1744 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1745 "Memory operand with multiple values?");
1747 unsigned TiedToOperand;
1748 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1749 // We need the constraint ID from the operand this is tied to.
1750 unsigned CurOp = InlineAsm::Op_FirstOperand;
1751 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1752 for (; TiedToOperand; --TiedToOperand) {
1753 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1754 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1758 // Otherwise, this is a memory operand. Ask the target to select it.
1759 std::vector<SDValue> SelOps;
1760 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1761 InlineAsm::getMemoryConstraintID(Flags),
1763 report_fatal_error("Could not match memory address. Inline asm"
1766 // Add this to the output node.
1768 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1769 Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
1770 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1775 // Add the glue input back if present.
1776 if (e != InOps.size())
1777 Ops.push_back(InOps.back());
1780 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1783 static SDNode *findGlueUse(SDNode *N) {
1784 unsigned FlagResNo = N->getNumValues()-1;
1785 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1786 SDUse &Use = I.getUse();
1787 if (Use.getResNo() == FlagResNo)
1788 return Use.getUser();
1793 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1794 /// This function recursively traverses up the operand chain, ignoring
1796 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1797 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1798 bool IgnoreChains) {
1799 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1800 // greater than all of its (recursive) operands. If we scan to a point where
1801 // 'use' is smaller than the node we're scanning for, then we know we will
1804 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1805 // happen because we scan down to newly selected nodes in the case of glue
1807 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1810 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1811 // won't fail if we scan it again.
1812 if (!Visited.insert(Use).second)
1815 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1816 // Ignore chain uses, they are validated by HandleMergeInputChains.
1817 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1820 SDNode *N = Use->getOperand(i).getNode();
1822 if (Use == ImmedUse || Use == Root)
1823 continue; // We are not looking for immediate use.
1828 // Traverse up the operand chain.
1829 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1835 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1836 /// operand node N of U during instruction selection that starts at Root.
1837 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1838 SDNode *Root) const {
1839 if (OptLevel == CodeGenOpt::None) return false;
1840 return N.hasOneUse();
1843 /// IsLegalToFold - Returns true if the specific operand node N of
1844 /// U can be folded during instruction selection that starts at Root.
1845 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1846 CodeGenOpt::Level OptLevel,
1847 bool IgnoreChains) {
1848 if (OptLevel == CodeGenOpt::None) return false;
1850 // If Root use can somehow reach N through a path that that doesn't contain
1851 // U then folding N would create a cycle. e.g. In the following
1852 // diagram, Root can reach N through X. If N is folded into into Root, then
1853 // X is both a predecessor and a successor of U.
1864 // * indicates nodes to be folded together.
1866 // If Root produces glue, then it gets (even more) interesting. Since it
1867 // will be "glued" together with its glue use in the scheduler, we need to
1868 // check if it might reach N.
1887 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1888 // (call it Fold), then X is a predecessor of GU and a successor of
1889 // Fold. But since Fold and GU are glued together, this will create
1890 // a cycle in the scheduling graph.
1892 // If the node has glue, walk down the graph to the "lowest" node in the
1894 EVT VT = Root->getValueType(Root->getNumValues()-1);
1895 while (VT == MVT::Glue) {
1896 SDNode *GU = findGlueUse(Root);
1900 VT = Root->getValueType(Root->getNumValues()-1);
1902 // If our query node has a glue result with a use, we've walked up it. If
1903 // the user (which has already been selected) has a chain or indirectly uses
1904 // the chain, our WalkChainUsers predicate will not consider it. Because of
1905 // this, we cannot ignore chains in this predicate.
1906 IgnoreChains = false;
1910 SmallPtrSet<SDNode*, 16> Visited;
1911 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1914 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1917 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1918 SelectInlineAsmMemoryOperands(Ops, DL);
1920 const EVT VTs[] = {MVT::Other, MVT::Glue};
1921 SDValue New = CurDAG->getNode(ISD::INLINEASM, DL, VTs, Ops);
1923 return New.getNode();
1927 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1929 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1930 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1932 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
1933 SDValue New = CurDAG->getCopyFromReg(
1934 Op->getOperand(0), dl, Reg, Op->getValueType(0));
1936 return New.getNode();
1940 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1942 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1943 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1944 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1945 Op->getOperand(2).getValueType());
1946 SDValue New = CurDAG->getCopyToReg(
1947 Op->getOperand(0), dl, Reg, Op->getOperand(2));
1949 return New.getNode();
1954 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1955 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1958 /// GetVBR - decode a vbr encoding whose top bit is set.
1959 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1960 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1961 assert(Val >= 128 && "Not a VBR");
1962 Val &= 127; // Remove first vbr bit.
1967 NextBits = MatcherTable[Idx++];
1968 Val |= (NextBits&127) << Shift;
1970 } while (NextBits & 128);
1976 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1977 /// interior glue and chain results to use the new glue and chain results.
1978 void SelectionDAGISel::
1979 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1980 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1982 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1983 bool isMorphNodeTo) {
1984 SmallVector<SDNode*, 4> NowDeadNodes;
1986 // Now that all the normal results are replaced, we replace the chain and
1987 // glue results if present.
1988 if (!ChainNodesMatched.empty()) {
1989 assert(InputChain.getNode() &&
1990 "Matched input chains but didn't produce a chain");
1991 // Loop over all of the nodes we matched that produced a chain result.
1992 // Replace all the chain results with the final chain we ended up with.
1993 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1994 SDNode *ChainNode = ChainNodesMatched[i];
1996 // If this node was already deleted, don't look at it.
1997 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2000 // Don't replace the results of the root node if we're doing a
2002 if (ChainNode == NodeToMatch && isMorphNodeTo)
2005 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2006 if (ChainVal.getValueType() == MVT::Glue)
2007 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2008 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2009 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2011 // If the node became dead and we haven't already seen it, delete it.
2012 if (ChainNode->use_empty() &&
2013 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2014 NowDeadNodes.push_back(ChainNode);
2018 // If the result produces glue, update any glue results in the matched
2019 // pattern with the glue result.
2020 if (InputGlue.getNode()) {
2021 // Handle any interior nodes explicitly marked.
2022 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2023 SDNode *FRN = GlueResultNodesMatched[i];
2025 // If this node was already deleted, don't look at it.
2026 if (FRN->getOpcode() == ISD::DELETED_NODE)
2029 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2030 "Doesn't have a glue result");
2031 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2034 // If the node became dead and we haven't already seen it, delete it.
2035 if (FRN->use_empty() &&
2036 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2037 NowDeadNodes.push_back(FRN);
2041 if (!NowDeadNodes.empty())
2042 CurDAG->RemoveDeadNodes(NowDeadNodes);
2044 DEBUG(dbgs() << "ISEL: Match complete!\n");
2050 CR_LeadsToInteriorNode
2053 /// WalkChainUsers - Walk down the users of the specified chained node that is
2054 /// part of the pattern we're matching, looking at all of the users we find.
2055 /// This determines whether something is an interior node, whether we have a
2056 /// non-pattern node in between two pattern nodes (which prevent folding because
2057 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2058 /// between pattern nodes (in which case the TF becomes part of the pattern).
2060 /// The walk we do here is guaranteed to be small because we quickly get down to
2061 /// already selected nodes "below" us.
2063 WalkChainUsers(const SDNode *ChainedNode,
2064 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2065 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2066 ChainResult Result = CR_Simple;
2068 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2069 E = ChainedNode->use_end(); UI != E; ++UI) {
2070 // Make sure the use is of the chain, not some other value we produce.
2071 if (UI.getUse().getValueType() != MVT::Other) continue;
2075 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2078 // If we see an already-selected machine node, then we've gone beyond the
2079 // pattern that we're selecting down into the already selected chunk of the
2081 unsigned UserOpcode = User->getOpcode();
2082 if (User->isMachineOpcode() ||
2083 UserOpcode == ISD::CopyToReg ||
2084 UserOpcode == ISD::CopyFromReg ||
2085 UserOpcode == ISD::INLINEASM ||
2086 UserOpcode == ISD::EH_LABEL ||
2087 UserOpcode == ISD::LIFETIME_START ||
2088 UserOpcode == ISD::LIFETIME_END) {
2089 // If their node ID got reset to -1 then they've already been selected.
2090 // Treat them like a MachineOpcode.
2091 if (User->getNodeId() == -1)
2095 // If we have a TokenFactor, we handle it specially.
2096 if (User->getOpcode() != ISD::TokenFactor) {
2097 // If the node isn't a token factor and isn't part of our pattern, then it
2098 // must be a random chained node in between two nodes we're selecting.
2099 // This happens when we have something like:
2104 // Because we structurally match the load/store as a read/modify/write,
2105 // but the call is chained between them. We cannot fold in this case
2106 // because it would induce a cycle in the graph.
2107 if (!std::count(ChainedNodesInPattern.begin(),
2108 ChainedNodesInPattern.end(), User))
2109 return CR_InducesCycle;
2111 // Otherwise we found a node that is part of our pattern. For example in:
2115 // This would happen when we're scanning down from the load and see the
2116 // store as a user. Record that there is a use of ChainedNode that is
2117 // part of the pattern and keep scanning uses.
2118 Result = CR_LeadsToInteriorNode;
2119 InteriorChainedNodes.push_back(User);
2123 // If we found a TokenFactor, there are two cases to consider: first if the
2124 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2125 // uses of the TF are in our pattern) we just want to ignore it. Second,
2126 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2132 // | \ DAG's like cheese
2135 // [TokenFactor] [Op]
2142 // In this case, the TokenFactor becomes part of our match and we rewrite it
2143 // as a new TokenFactor.
2145 // To distinguish these two cases, do a recursive walk down the uses.
2146 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2148 // If the uses of the TokenFactor are just already-selected nodes, ignore
2149 // it, it is "below" our pattern.
2151 case CR_InducesCycle:
2152 // If the uses of the TokenFactor lead to nodes that are not part of our
2153 // pattern that are not selected, folding would turn this into a cycle,
2155 return CR_InducesCycle;
2156 case CR_LeadsToInteriorNode:
2157 break; // Otherwise, keep processing.
2160 // Okay, we know we're in the interesting interior case. The TokenFactor
2161 // is now going to be considered part of the pattern so that we rewrite its
2162 // uses (it may have uses that are not part of the pattern) with the
2163 // ultimate chain result of the generated code. We will also add its chain
2164 // inputs as inputs to the ultimate TokenFactor we create.
2165 Result = CR_LeadsToInteriorNode;
2166 ChainedNodesInPattern.push_back(User);
2167 InteriorChainedNodes.push_back(User);
2174 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2175 /// operation for when the pattern matched at least one node with a chains. The
2176 /// input vector contains a list of all of the chained nodes that we match. We
2177 /// must determine if this is a valid thing to cover (i.e. matching it won't
2178 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2179 /// be used as the input node chain for the generated nodes.
2181 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2182 SelectionDAG *CurDAG) {
2183 // Walk all of the chained nodes we've matched, recursively scanning down the
2184 // users of the chain result. This adds any TokenFactor nodes that are caught
2185 // in between chained nodes to the chained and interior nodes list.
2186 SmallVector<SDNode*, 3> InteriorChainedNodes;
2187 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2188 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2189 InteriorChainedNodes) == CR_InducesCycle)
2190 return SDValue(); // Would induce a cycle.
2193 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2194 // that we are interested in. Form our input TokenFactor node.
2195 SmallVector<SDValue, 3> InputChains;
2196 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2197 // Add the input chain of this node to the InputChains list (which will be
2198 // the operands of the generated TokenFactor) if it's not an interior node.
2199 SDNode *N = ChainNodesMatched[i];
2200 if (N->getOpcode() != ISD::TokenFactor) {
2201 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2204 // Otherwise, add the input chain.
2205 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2206 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2207 InputChains.push_back(InChain);
2211 // If we have a token factor, we want to add all inputs of the token factor
2212 // that are not part of the pattern we're matching.
2213 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2214 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2215 N->getOperand(op).getNode()))
2216 InputChains.push_back(N->getOperand(op));
2220 if (InputChains.size() == 1)
2221 return InputChains[0];
2222 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2223 MVT::Other, InputChains);
2226 /// MorphNode - Handle morphing a node in place for the selector.
2227 SDNode *SelectionDAGISel::
2228 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2229 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2230 // It is possible we're using MorphNodeTo to replace a node with no
2231 // normal results with one that has a normal result (or we could be
2232 // adding a chain) and the input could have glue and chains as well.
2233 // In this case we need to shift the operands down.
2234 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2235 // than the old isel though.
2236 int OldGlueResultNo = -1, OldChainResultNo = -1;
2238 unsigned NTMNumResults = Node->getNumValues();
2239 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2240 OldGlueResultNo = NTMNumResults-1;
2241 if (NTMNumResults != 1 &&
2242 Node->getValueType(NTMNumResults-2) == MVT::Other)
2243 OldChainResultNo = NTMNumResults-2;
2244 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2245 OldChainResultNo = NTMNumResults-1;
2247 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2248 // that this deletes operands of the old node that become dead.
2249 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2251 // MorphNodeTo can operate in two ways: if an existing node with the
2252 // specified operands exists, it can just return it. Otherwise, it
2253 // updates the node in place to have the requested operands.
2255 // If we updated the node in place, reset the node ID. To the isel,
2256 // this should be just like a newly allocated machine node.
2260 unsigned ResNumResults = Res->getNumValues();
2261 // Move the glue if needed.
2262 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2263 (unsigned)OldGlueResultNo != ResNumResults-1)
2264 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2265 SDValue(Res, ResNumResults-1));
2267 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2270 // Move the chain reference if needed.
2271 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2272 (unsigned)OldChainResultNo != ResNumResults-1)
2273 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2274 SDValue(Res, ResNumResults-1));
2276 // Otherwise, no replacement happened because the node already exists. Replace
2277 // Uses of the old node with the new one.
2279 CurDAG->ReplaceAllUsesWith(Node, Res);
2284 /// CheckSame - Implements OP_CheckSame.
2285 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2286 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2288 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2289 // Accept if it is exactly the same as a previously recorded node.
2290 unsigned RecNo = MatcherTable[MatcherIndex++];
2291 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2292 return N == RecordedNodes[RecNo].first;
2295 /// CheckChildSame - Implements OP_CheckChildXSame.
2296 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2297 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2299 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2301 if (ChildNo >= N.getNumOperands())
2302 return false; // Match fails if out of range child #.
2303 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2307 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2308 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2309 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2310 const SelectionDAGISel &SDISel) {
2311 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2314 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2315 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2316 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2317 const SelectionDAGISel &SDISel, SDNode *N) {
2318 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2321 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2322 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2324 uint16_t Opc = MatcherTable[MatcherIndex++];
2325 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2326 return N->getOpcode() == Opc;
2329 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2330 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2331 SDValue N, const TargetLowering *TLI) {
2332 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2333 if (N.getValueType() == VT) return true;
2335 // Handle the case when VT is iPTR.
2336 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2339 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2340 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2341 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2342 if (ChildNo >= N.getNumOperands())
2343 return false; // Match fails if out of range child #.
2344 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2347 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2348 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2350 return cast<CondCodeSDNode>(N)->get() ==
2351 (ISD::CondCode)MatcherTable[MatcherIndex++];
2354 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2355 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2356 SDValue N, const TargetLowering *TLI) {
2357 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2358 if (cast<VTSDNode>(N)->getVT() == VT)
2361 // Handle the case when VT is iPTR.
2362 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2365 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2366 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2368 int64_t Val = MatcherTable[MatcherIndex++];
2370 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2372 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2373 return C && C->getSExtValue() == Val;
2376 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2377 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2378 SDValue N, unsigned ChildNo) {
2379 if (ChildNo >= N.getNumOperands())
2380 return false; // Match fails if out of range child #.
2381 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2384 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2385 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2386 SDValue N, const SelectionDAGISel &SDISel) {
2387 int64_t Val = MatcherTable[MatcherIndex++];
2389 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2391 if (N->getOpcode() != ISD::AND) return false;
2393 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2394 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2397 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2398 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2399 SDValue N, const SelectionDAGISel &SDISel) {
2400 int64_t Val = MatcherTable[MatcherIndex++];
2402 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2404 if (N->getOpcode() != ISD::OR) return false;
2406 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2407 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2410 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2411 /// scope, evaluate the current node. If the current predicate is known to
2412 /// fail, set Result=true and return anything. If the current predicate is
2413 /// known to pass, set Result=false and return the MatcherIndex to continue
2414 /// with. If the current predicate is unknown, set Result=false and return the
2415 /// MatcherIndex to continue with.
2416 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2417 unsigned Index, SDValue N,
2419 const SelectionDAGISel &SDISel,
2420 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2421 switch (Table[Index++]) {
2424 return Index-1; // Could not evaluate this predicate.
2425 case SelectionDAGISel::OPC_CheckSame:
2426 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2428 case SelectionDAGISel::OPC_CheckChild0Same:
2429 case SelectionDAGISel::OPC_CheckChild1Same:
2430 case SelectionDAGISel::OPC_CheckChild2Same:
2431 case SelectionDAGISel::OPC_CheckChild3Same:
2432 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2433 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2435 case SelectionDAGISel::OPC_CheckPatternPredicate:
2436 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2438 case SelectionDAGISel::OPC_CheckPredicate:
2439 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2441 case SelectionDAGISel::OPC_CheckOpcode:
2442 Result = !::CheckOpcode(Table, Index, N.getNode());
2444 case SelectionDAGISel::OPC_CheckType:
2445 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2447 case SelectionDAGISel::OPC_CheckChild0Type:
2448 case SelectionDAGISel::OPC_CheckChild1Type:
2449 case SelectionDAGISel::OPC_CheckChild2Type:
2450 case SelectionDAGISel::OPC_CheckChild3Type:
2451 case SelectionDAGISel::OPC_CheckChild4Type:
2452 case SelectionDAGISel::OPC_CheckChild5Type:
2453 case SelectionDAGISel::OPC_CheckChild6Type:
2454 case SelectionDAGISel::OPC_CheckChild7Type:
2455 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2457 SelectionDAGISel::OPC_CheckChild0Type);
2459 case SelectionDAGISel::OPC_CheckCondCode:
2460 Result = !::CheckCondCode(Table, Index, N);
2462 case SelectionDAGISel::OPC_CheckValueType:
2463 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2465 case SelectionDAGISel::OPC_CheckInteger:
2466 Result = !::CheckInteger(Table, Index, N);
2468 case SelectionDAGISel::OPC_CheckChild0Integer:
2469 case SelectionDAGISel::OPC_CheckChild1Integer:
2470 case SelectionDAGISel::OPC_CheckChild2Integer:
2471 case SelectionDAGISel::OPC_CheckChild3Integer:
2472 case SelectionDAGISel::OPC_CheckChild4Integer:
2473 Result = !::CheckChildInteger(Table, Index, N,
2474 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2476 case SelectionDAGISel::OPC_CheckAndImm:
2477 Result = !::CheckAndImm(Table, Index, N, SDISel);
2479 case SelectionDAGISel::OPC_CheckOrImm:
2480 Result = !::CheckOrImm(Table, Index, N, SDISel);
2488 /// FailIndex - If this match fails, this is the index to continue with.
2491 /// NodeStack - The node stack when the scope was formed.
2492 SmallVector<SDValue, 4> NodeStack;
2494 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2495 unsigned NumRecordedNodes;
2497 /// NumMatchedMemRefs - The number of matched memref entries.
2498 unsigned NumMatchedMemRefs;
2500 /// InputChain/InputGlue - The current chain/glue
2501 SDValue InputChain, InputGlue;
2503 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2504 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2507 /// \\brief A DAG update listener to keep the matching state
2508 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2509 /// change the DAG while matching. X86 addressing mode matcher is an example
2511 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2513 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2514 SmallVectorImpl<MatchScope> &MatchScopes;
2516 MatchStateUpdater(SelectionDAG &DAG,
2517 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2518 SmallVectorImpl<MatchScope> &MS) :
2519 SelectionDAG::DAGUpdateListener(DAG),
2520 RecordedNodes(RN), MatchScopes(MS) { }
2522 void NodeDeleted(SDNode *N, SDNode *E) override {
2523 // Some early-returns here to avoid the search if we deleted the node or
2524 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2525 // do, so it's unnecessary to update matching state at that point).
2526 // Neither of these can occur currently because we only install this
2527 // update listener during matching a complex patterns.
2528 if (!E || E->isMachineOpcode())
2530 // Performing linear search here does not matter because we almost never
2531 // run this code. You'd have to have a CSE during complex pattern
2533 for (auto &I : RecordedNodes)
2534 if (I.first.getNode() == N)
2537 for (auto &I : MatchScopes)
2538 for (auto &J : I.NodeStack)
2539 if (J.getNode() == N)
2545 SDNode *SelectionDAGISel::
2546 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2547 unsigned TableSize) {
2548 // FIXME: Should these even be selected? Handle these cases in the caller?
2549 switch (NodeToMatch->getOpcode()) {
2552 case ISD::EntryToken: // These nodes remain the same.
2553 case ISD::BasicBlock:
2555 case ISD::RegisterMask:
2556 case ISD::HANDLENODE:
2557 case ISD::MDNODE_SDNODE:
2558 case ISD::TargetConstant:
2559 case ISD::TargetConstantFP:
2560 case ISD::TargetConstantPool:
2561 case ISD::TargetFrameIndex:
2562 case ISD::TargetExternalSymbol:
2563 case ISD::TargetBlockAddress:
2564 case ISD::TargetJumpTable:
2565 case ISD::TargetGlobalTLSAddress:
2566 case ISD::TargetGlobalAddress:
2567 case ISD::TokenFactor:
2568 case ISD::CopyFromReg:
2569 case ISD::CopyToReg:
2571 case ISD::LIFETIME_START:
2572 case ISD::LIFETIME_END:
2573 NodeToMatch->setNodeId(-1); // Mark selected.
2575 case ISD::AssertSext:
2576 case ISD::AssertZext:
2577 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2578 NodeToMatch->getOperand(0));
2580 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2581 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2582 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2583 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2586 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2588 // Set up the node stack with NodeToMatch as the only node on the stack.
2589 SmallVector<SDValue, 8> NodeStack;
2590 SDValue N = SDValue(NodeToMatch, 0);
2591 NodeStack.push_back(N);
2593 // MatchScopes - Scopes used when matching, if a match failure happens, this
2594 // indicates where to continue checking.
2595 SmallVector<MatchScope, 8> MatchScopes;
2597 // RecordedNodes - This is the set of nodes that have been recorded by the
2598 // state machine. The second value is the parent of the node, or null if the
2599 // root is recorded.
2600 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2602 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2604 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2606 // These are the current input chain and glue for use when generating nodes.
2607 // Various Emit operations change these. For example, emitting a copytoreg
2608 // uses and updates these.
2609 SDValue InputChain, InputGlue;
2611 // ChainNodesMatched - If a pattern matches nodes that have input/output
2612 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2613 // which ones they are. The result is captured into this list so that we can
2614 // update the chain results when the pattern is complete.
2615 SmallVector<SDNode*, 3> ChainNodesMatched;
2616 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2618 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2619 NodeToMatch->dump(CurDAG);
2622 // Determine where to start the interpreter. Normally we start at opcode #0,
2623 // but if the state machine starts with an OPC_SwitchOpcode, then we
2624 // accelerate the first lookup (which is guaranteed to be hot) with the
2625 // OpcodeOffset table.
2626 unsigned MatcherIndex = 0;
2628 if (!OpcodeOffset.empty()) {
2629 // Already computed the OpcodeOffset table, just index into it.
2630 if (N.getOpcode() < OpcodeOffset.size())
2631 MatcherIndex = OpcodeOffset[N.getOpcode()];
2632 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2634 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2635 // Otherwise, the table isn't computed, but the state machine does start
2636 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2637 // is the first time we're selecting an instruction.
2640 // Get the size of this case.
2641 unsigned CaseSize = MatcherTable[Idx++];
2643 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2644 if (CaseSize == 0) break;
2646 // Get the opcode, add the index to the table.
2647 uint16_t Opc = MatcherTable[Idx++];
2648 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2649 if (Opc >= OpcodeOffset.size())
2650 OpcodeOffset.resize((Opc+1)*2);
2651 OpcodeOffset[Opc] = Idx;
2655 // Okay, do the lookup for the first opcode.
2656 if (N.getOpcode() < OpcodeOffset.size())
2657 MatcherIndex = OpcodeOffset[N.getOpcode()];
2661 assert(MatcherIndex < TableSize && "Invalid index");
2663 unsigned CurrentOpcodeIndex = MatcherIndex;
2665 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2668 // Okay, the semantics of this operation are that we should push a scope
2669 // then evaluate the first child. However, pushing a scope only to have
2670 // the first check fail (which then pops it) is inefficient. If we can
2671 // determine immediately that the first check (or first several) will
2672 // immediately fail, don't even bother pushing a scope for them.
2676 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2677 if (NumToSkip & 128)
2678 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2679 // Found the end of the scope with no match.
2680 if (NumToSkip == 0) {
2685 FailIndex = MatcherIndex+NumToSkip;
2687 unsigned MatcherIndexOfPredicate = MatcherIndex;
2688 (void)MatcherIndexOfPredicate; // silence warning.
2690 // If we can't evaluate this predicate without pushing a scope (e.g. if
2691 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2692 // push the scope and evaluate the full predicate chain.
2694 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2695 Result, *this, RecordedNodes);
2699 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2700 << "index " << MatcherIndexOfPredicate
2701 << ", continuing at " << FailIndex << "\n");
2702 ++NumDAGIselRetries;
2704 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2705 // move to the next case.
2706 MatcherIndex = FailIndex;
2709 // If the whole scope failed to match, bail.
2710 if (FailIndex == 0) break;
2712 // Push a MatchScope which indicates where to go if the first child fails
2714 MatchScope NewEntry;
2715 NewEntry.FailIndex = FailIndex;
2716 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2717 NewEntry.NumRecordedNodes = RecordedNodes.size();
2718 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2719 NewEntry.InputChain = InputChain;
2720 NewEntry.InputGlue = InputGlue;
2721 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2722 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2723 MatchScopes.push_back(NewEntry);
2726 case OPC_RecordNode: {
2727 // Remember this node, it may end up being an operand in the pattern.
2728 SDNode *Parent = nullptr;
2729 if (NodeStack.size() > 1)
2730 Parent = NodeStack[NodeStack.size()-2].getNode();
2731 RecordedNodes.push_back(std::make_pair(N, Parent));
2735 case OPC_RecordChild0: case OPC_RecordChild1:
2736 case OPC_RecordChild2: case OPC_RecordChild3:
2737 case OPC_RecordChild4: case OPC_RecordChild5:
2738 case OPC_RecordChild6: case OPC_RecordChild7: {
2739 unsigned ChildNo = Opcode-OPC_RecordChild0;
2740 if (ChildNo >= N.getNumOperands())
2741 break; // Match fails if out of range child #.
2743 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2747 case OPC_RecordMemRef:
2748 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2751 case OPC_CaptureGlueInput:
2752 // If the current node has an input glue, capture it in InputGlue.
2753 if (N->getNumOperands() != 0 &&
2754 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2755 InputGlue = N->getOperand(N->getNumOperands()-1);
2758 case OPC_MoveChild: {
2759 unsigned ChildNo = MatcherTable[MatcherIndex++];
2760 if (ChildNo >= N.getNumOperands())
2761 break; // Match fails if out of range child #.
2762 N = N.getOperand(ChildNo);
2763 NodeStack.push_back(N);
2767 case OPC_MoveParent:
2768 // Pop the current node off the NodeStack.
2769 NodeStack.pop_back();
2770 assert(!NodeStack.empty() && "Node stack imbalance!");
2771 N = NodeStack.back();
2775 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2778 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2779 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2780 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2781 Opcode-OPC_CheckChild0Same))
2785 case OPC_CheckPatternPredicate:
2786 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2788 case OPC_CheckPredicate:
2789 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2793 case OPC_CheckComplexPat: {
2794 unsigned CPNum = MatcherTable[MatcherIndex++];
2795 unsigned RecNo = MatcherTable[MatcherIndex++];
2796 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2798 // If target can modify DAG during matching, keep the matching state
2800 std::unique_ptr<MatchStateUpdater> MSU;
2801 if (ComplexPatternFuncMutatesDAG())
2802 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2805 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2806 RecordedNodes[RecNo].first, CPNum,
2811 case OPC_CheckOpcode:
2812 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2816 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2820 case OPC_SwitchOpcode: {
2821 unsigned CurNodeOpcode = N.getOpcode();
2822 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2825 // Get the size of this case.
2826 CaseSize = MatcherTable[MatcherIndex++];
2828 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2829 if (CaseSize == 0) break;
2831 uint16_t Opc = MatcherTable[MatcherIndex++];
2832 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2834 // If the opcode matches, then we will execute this case.
2835 if (CurNodeOpcode == Opc)
2838 // Otherwise, skip over this case.
2839 MatcherIndex += CaseSize;
2842 // If no cases matched, bail out.
2843 if (CaseSize == 0) break;
2845 // Otherwise, execute the case we found.
2846 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2847 << " to " << MatcherIndex << "\n");
2851 case OPC_SwitchType: {
2852 MVT CurNodeVT = N.getSimpleValueType();
2853 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2856 // Get the size of this case.
2857 CaseSize = MatcherTable[MatcherIndex++];
2859 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2860 if (CaseSize == 0) break;
2862 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2863 if (CaseVT == MVT::iPTR)
2864 CaseVT = TLI->getPointerTy();
2866 // If the VT matches, then we will execute this case.
2867 if (CurNodeVT == CaseVT)
2870 // Otherwise, skip over this case.
2871 MatcherIndex += CaseSize;
2874 // If no cases matched, bail out.
2875 if (CaseSize == 0) break;
2877 // Otherwise, execute the case we found.
2878 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2879 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2882 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2883 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2884 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2885 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2886 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2887 Opcode-OPC_CheckChild0Type))
2890 case OPC_CheckCondCode:
2891 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2893 case OPC_CheckValueType:
2894 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2897 case OPC_CheckInteger:
2898 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2900 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2901 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2902 case OPC_CheckChild4Integer:
2903 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2904 Opcode-OPC_CheckChild0Integer)) break;
2906 case OPC_CheckAndImm:
2907 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2909 case OPC_CheckOrImm:
2910 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2913 case OPC_CheckFoldableChainNode: {
2914 assert(NodeStack.size() != 1 && "No parent node");
2915 // Verify that all intermediate nodes between the root and this one have
2917 bool HasMultipleUses = false;
2918 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2919 if (!NodeStack[i].hasOneUse()) {
2920 HasMultipleUses = true;
2923 if (HasMultipleUses) break;
2925 // Check to see that the target thinks this is profitable to fold and that
2926 // we can fold it without inducing cycles in the graph.
2927 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2929 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2930 NodeToMatch, OptLevel,
2931 true/*We validate our own chains*/))
2936 case OPC_EmitInteger: {
2937 MVT::SimpleValueType VT =
2938 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2939 int64_t Val = MatcherTable[MatcherIndex++];
2941 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2942 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2943 CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch),
2947 case OPC_EmitRegister: {
2948 MVT::SimpleValueType VT =
2949 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2950 unsigned RegNo = MatcherTable[MatcherIndex++];
2951 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2952 CurDAG->getRegister(RegNo, VT), nullptr));
2955 case OPC_EmitRegister2: {
2956 // For targets w/ more than 256 register names, the register enum
2957 // values are stored in two bytes in the matcher table (just like
2959 MVT::SimpleValueType VT =
2960 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2961 unsigned RegNo = MatcherTable[MatcherIndex++];
2962 RegNo |= MatcherTable[MatcherIndex++] << 8;
2963 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2964 CurDAG->getRegister(RegNo, VT), nullptr));
2968 case OPC_EmitConvertToTarget: {
2969 // Convert from IMM/FPIMM to target version.
2970 unsigned RecNo = MatcherTable[MatcherIndex++];
2971 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2972 SDValue Imm = RecordedNodes[RecNo].first;
2974 if (Imm->getOpcode() == ISD::Constant) {
2975 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2976 Imm = CurDAG->getConstant(*Val, SDLoc(NodeToMatch), Imm.getValueType(),
2978 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2979 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2980 Imm = CurDAG->getConstantFP(*Val, SDLoc(NodeToMatch),
2981 Imm.getValueType(), true);
2984 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2988 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2989 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2990 // These are space-optimized forms of OPC_EmitMergeInputChains.
2991 assert(!InputChain.getNode() &&
2992 "EmitMergeInputChains should be the first chain producing node");
2993 assert(ChainNodesMatched.empty() &&
2994 "Should only have one EmitMergeInputChains per match");
2996 // Read all of the chained nodes.
2997 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2998 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2999 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3001 // FIXME: What if other value results of the node have uses not matched
3003 if (ChainNodesMatched.back() != NodeToMatch &&
3004 !RecordedNodes[RecNo].first.hasOneUse()) {
3005 ChainNodesMatched.clear();
3009 // Merge the input chains if they are not intra-pattern references.
3010 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3012 if (!InputChain.getNode())
3013 break; // Failed to merge.
3017 case OPC_EmitMergeInputChains: {
3018 assert(!InputChain.getNode() &&
3019 "EmitMergeInputChains should be the first chain producing node");
3020 // This node gets a list of nodes we matched in the input that have
3021 // chains. We want to token factor all of the input chains to these nodes
3022 // together. However, if any of the input chains is actually one of the
3023 // nodes matched in this pattern, then we have an intra-match reference.
3024 // Ignore these because the newly token factored chain should not refer to
3026 unsigned NumChains = MatcherTable[MatcherIndex++];
3027 assert(NumChains != 0 && "Can't TF zero chains");
3029 assert(ChainNodesMatched.empty() &&
3030 "Should only have one EmitMergeInputChains per match");
3032 // Read all of the chained nodes.
3033 for (unsigned i = 0; i != NumChains; ++i) {
3034 unsigned RecNo = MatcherTable[MatcherIndex++];
3035 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3036 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3038 // FIXME: What if other value results of the node have uses not matched
3040 if (ChainNodesMatched.back() != NodeToMatch &&
3041 !RecordedNodes[RecNo].first.hasOneUse()) {
3042 ChainNodesMatched.clear();
3047 // If the inner loop broke out, the match fails.
3048 if (ChainNodesMatched.empty())
3051 // Merge the input chains if they are not intra-pattern references.
3052 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3054 if (!InputChain.getNode())
3055 break; // Failed to merge.
3060 case OPC_EmitCopyToReg: {
3061 unsigned RecNo = MatcherTable[MatcherIndex++];
3062 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3063 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3065 if (!InputChain.getNode())
3066 InputChain = CurDAG->getEntryNode();
3068 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3069 DestPhysReg, RecordedNodes[RecNo].first,
3072 InputGlue = InputChain.getValue(1);
3076 case OPC_EmitNodeXForm: {
3077 unsigned XFormNo = MatcherTable[MatcherIndex++];
3078 unsigned RecNo = MatcherTable[MatcherIndex++];
3079 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3080 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3081 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3086 case OPC_MorphNodeTo: {
3087 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3088 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3089 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3090 // Get the result VT list.
3091 unsigned NumVTs = MatcherTable[MatcherIndex++];
3092 SmallVector<EVT, 4> VTs;
3093 for (unsigned i = 0; i != NumVTs; ++i) {
3094 MVT::SimpleValueType VT =
3095 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3096 if (VT == MVT::iPTR)
3097 VT = TLI->getPointerTy().SimpleTy;
3101 if (EmitNodeInfo & OPFL_Chain)
3102 VTs.push_back(MVT::Other);
3103 if (EmitNodeInfo & OPFL_GlueOutput)
3104 VTs.push_back(MVT::Glue);
3106 // This is hot code, so optimize the two most common cases of 1 and 2
3109 if (VTs.size() == 1)
3110 VTList = CurDAG->getVTList(VTs[0]);
3111 else if (VTs.size() == 2)
3112 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3114 VTList = CurDAG->getVTList(VTs);
3116 // Get the operand list.
3117 unsigned NumOps = MatcherTable[MatcherIndex++];
3118 SmallVector<SDValue, 8> Ops;
3119 for (unsigned i = 0; i != NumOps; ++i) {
3120 unsigned RecNo = MatcherTable[MatcherIndex++];
3122 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3124 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3125 Ops.push_back(RecordedNodes[RecNo].first);
3128 // If there are variadic operands to add, handle them now.
3129 if (EmitNodeInfo & OPFL_VariadicInfo) {
3130 // Determine the start index to copy from.
3131 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3132 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3133 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3134 "Invalid variadic node");
3135 // Copy all of the variadic operands, not including a potential glue
3137 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3139 SDValue V = NodeToMatch->getOperand(i);
3140 if (V.getValueType() == MVT::Glue) break;
3145 // If this has chain/glue inputs, add them.
3146 if (EmitNodeInfo & OPFL_Chain)
3147 Ops.push_back(InputChain);
3148 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3149 Ops.push_back(InputGlue);
3152 SDNode *Res = nullptr;
3153 if (Opcode != OPC_MorphNodeTo) {
3154 // If this is a normal EmitNode command, just create the new node and
3155 // add the results to the RecordedNodes list.
3156 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3159 // Add all the non-glue/non-chain results to the RecordedNodes list.
3160 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3161 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3162 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3166 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3167 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3169 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3170 // We will visit the equivalent node later.
3171 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3175 // If the node had chain/glue results, update our notion of the current
3177 if (EmitNodeInfo & OPFL_GlueOutput) {
3178 InputGlue = SDValue(Res, VTs.size()-1);
3179 if (EmitNodeInfo & OPFL_Chain)
3180 InputChain = SDValue(Res, VTs.size()-2);
3181 } else if (EmitNodeInfo & OPFL_Chain)
3182 InputChain = SDValue(Res, VTs.size()-1);
3184 // If the OPFL_MemRefs glue is set on this node, slap all of the
3185 // accumulated memrefs onto it.
3187 // FIXME: This is vastly incorrect for patterns with multiple outputs
3188 // instructions that access memory and for ComplexPatterns that match
3190 if (EmitNodeInfo & OPFL_MemRefs) {
3191 // Only attach load or store memory operands if the generated
3192 // instruction may load or store.
3193 const MCInstrDesc &MCID = TII->get(TargetOpc);
3194 bool mayLoad = MCID.mayLoad();
3195 bool mayStore = MCID.mayStore();
3197 unsigned NumMemRefs = 0;
3198 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3199 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3200 if ((*I)->isLoad()) {
3203 } else if ((*I)->isStore()) {
3211 MachineSDNode::mmo_iterator MemRefs =
3212 MF->allocateMemRefsArray(NumMemRefs);
3214 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3215 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3216 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3217 if ((*I)->isLoad()) {
3220 } else if ((*I)->isStore()) {
3228 cast<MachineSDNode>(Res)
3229 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3233 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3234 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3236 // If this was a MorphNodeTo then we're completely done!
3237 if (Opcode == OPC_MorphNodeTo) {
3238 // Update chain and glue uses.
3239 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3240 InputGlue, GlueResultNodesMatched, true);
3247 case OPC_MarkGlueResults: {
3248 unsigned NumNodes = MatcherTable[MatcherIndex++];
3250 // Read and remember all the glue-result nodes.
3251 for (unsigned i = 0; i != NumNodes; ++i) {
3252 unsigned RecNo = MatcherTable[MatcherIndex++];
3254 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3256 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3257 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3262 case OPC_CompleteMatch: {
3263 // The match has been completed, and any new nodes (if any) have been
3264 // created. Patch up references to the matched dag to use the newly
3266 unsigned NumResults = MatcherTable[MatcherIndex++];
3268 for (unsigned i = 0; i != NumResults; ++i) {
3269 unsigned ResSlot = MatcherTable[MatcherIndex++];
3271 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3273 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3274 SDValue Res = RecordedNodes[ResSlot].first;
3276 assert(i < NodeToMatch->getNumValues() &&
3277 NodeToMatch->getValueType(i) != MVT::Other &&
3278 NodeToMatch->getValueType(i) != MVT::Glue &&
3279 "Invalid number of results to complete!");
3280 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3281 NodeToMatch->getValueType(i) == MVT::iPTR ||
3282 Res.getValueType() == MVT::iPTR ||
3283 NodeToMatch->getValueType(i).getSizeInBits() ==
3284 Res.getValueType().getSizeInBits()) &&
3285 "invalid replacement");
3286 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3289 // If the root node defines glue, add it to the glue nodes to update list.
3290 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3291 GlueResultNodesMatched.push_back(NodeToMatch);
3293 // Update chain and glue uses.
3294 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3295 InputGlue, GlueResultNodesMatched, false);
3297 assert(NodeToMatch->use_empty() &&
3298 "Didn't replace all uses of the node?");
3300 // FIXME: We just return here, which interacts correctly with SelectRoot
3301 // above. We should fix this to not return an SDNode* anymore.
3306 // If the code reached this point, then the match failed. See if there is
3307 // another child to try in the current 'Scope', otherwise pop it until we
3308 // find a case to check.
3309 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3310 ++NumDAGIselRetries;
3312 if (MatchScopes.empty()) {
3313 CannotYetSelect(NodeToMatch);
3317 // Restore the interpreter state back to the point where the scope was
3319 MatchScope &LastScope = MatchScopes.back();
3320 RecordedNodes.resize(LastScope.NumRecordedNodes);
3322 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3323 N = NodeStack.back();
3325 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3326 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3327 MatcherIndex = LastScope.FailIndex;
3329 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3331 InputChain = LastScope.InputChain;
3332 InputGlue = LastScope.InputGlue;
3333 if (!LastScope.HasChainNodesMatched)
3334 ChainNodesMatched.clear();
3335 if (!LastScope.HasGlueResultNodesMatched)
3336 GlueResultNodesMatched.clear();
3338 // Check to see what the offset is at the new MatcherIndex. If it is zero
3339 // we have reached the end of this scope, otherwise we have another child
3340 // in the current scope to try.
3341 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3342 if (NumToSkip & 128)
3343 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3345 // If we have another child in this scope to match, update FailIndex and
3347 if (NumToSkip != 0) {
3348 LastScope.FailIndex = MatcherIndex+NumToSkip;
3352 // End of this scope, pop it and try the next child in the containing
3354 MatchScopes.pop_back();
3361 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3363 raw_string_ostream Msg(msg);
3364 Msg << "Cannot select: ";
3366 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3367 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3368 N->getOpcode() != ISD::INTRINSIC_VOID) {
3369 N->printrFull(Msg, CurDAG);
3370 Msg << "\nIn function: " << MF->getName();
3372 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3374 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3375 if (iid < Intrinsic::num_intrinsics)
3376 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3377 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3378 Msg << "target intrinsic %" << TII->getName(iid);
3380 Msg << "unknown intrinsic #" << iid;
3382 report_fatal_error(Msg.str());
3385 char SelectionDAGISel::ID = 0;