1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/CFG.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/DebugInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/LLVMContext.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/Timer.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLibraryInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Target/TargetRegisterInfo.h"
57 #include "llvm/Target/TargetSubtargetInfo.h"
58 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
64 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
65 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
66 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
68 STATISTIC(NumFastIselFailLowerArguments,
69 "Number of entry blocks where fast isel failed to lower arguments");
73 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
74 cl::desc("Enable extra verbose messages in the \"fast\" "
75 "instruction selector"));
78 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
79 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
80 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
81 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
82 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
83 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
84 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
86 // Standard binary operators...
87 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
88 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
89 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
90 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
91 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
92 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
93 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
94 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
95 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
96 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
97 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
98 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
100 // Logical operators...
101 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
102 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
103 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
105 // Memory instructions...
106 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
107 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
108 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
109 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
110 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
111 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
112 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
114 // Convert instructions...
115 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
116 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
117 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
118 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
119 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
120 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
121 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
122 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
123 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
124 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
125 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
126 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
128 // Other instructions...
129 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
130 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
131 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
132 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
133 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
134 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
135 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
136 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
137 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
138 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
139 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
140 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
141 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
142 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
143 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
148 cl::desc("Enable verbose messages in the \"fast\" "
149 "instruction selector"));
151 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
152 cl::desc("Enable abort calls when \"fast\" instruction selection "
153 "fails to lower an instruction"));
155 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
156 cl::desc("Enable abort calls when \"fast\" instruction selection "
157 "fails to lower a formal argument"));
161 cl::desc("use Machine Branch Probability Info"),
162 cl::init(true), cl::Hidden);
166 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
167 cl::desc("Pop up a window to show dags before the first "
168 "dag combine pass"));
170 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
171 cl::desc("Pop up a window to show dags before legalize types"));
173 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
174 cl::desc("Pop up a window to show dags before legalize"));
176 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
177 cl::desc("Pop up a window to show dags before the second "
178 "dag combine pass"));
180 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
181 cl::desc("Pop up a window to show dags before the post legalize types"
182 " dag combine pass"));
184 ViewISelDAGs("view-isel-dags", cl::Hidden,
185 cl::desc("Pop up a window to show isel dags as they are selected"));
187 ViewSchedDAGs("view-sched-dags", cl::Hidden,
188 cl::desc("Pop up a window to show sched dags as they are processed"));
190 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
191 cl::desc("Pop up a window to show SUnit dags after they are processed"));
193 static const bool ViewDAGCombine1 = false,
194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
195 ViewDAGCombine2 = false,
196 ViewDAGCombineLT = false,
197 ViewISelDAGs = false, ViewSchedDAGs = false,
198 ViewSUnitDAGs = false;
201 //===---------------------------------------------------------------------===//
203 /// RegisterScheduler class - Track the registration of instruction schedulers.
205 //===---------------------------------------------------------------------===//
206 MachinePassRegistry RegisterScheduler::Registry;
208 //===---------------------------------------------------------------------===//
210 /// ISHeuristic command line option for instruction schedulers.
212 //===---------------------------------------------------------------------===//
213 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
214 RegisterPassParser<RegisterScheduler> >
215 ISHeuristic("pre-RA-sched",
216 cl::init(&createDefaultScheduler),
217 cl::desc("Instruction schedulers available (before register"
220 static RegisterScheduler
221 defaultListDAGScheduler("default", "Best scheduler for the target",
222 createDefaultScheduler);
225 //===--------------------------------------------------------------------===//
226 /// \brief This class is used by SelectionDAGISel to temporarily override
227 /// the optimization level on a per-function basis.
228 class OptLevelChanger {
229 SelectionDAGISel &IS;
230 CodeGenOpt::Level SavedOptLevel;
234 OptLevelChanger(SelectionDAGISel &ISel,
235 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
236 SavedOptLevel = IS.OptLevel;
237 if (NewOptLevel == SavedOptLevel)
239 IS.OptLevel = NewOptLevel;
240 IS.TM.setOptLevel(NewOptLevel);
241 SavedFastISel = IS.TM.Options.EnableFastISel;
242 if (NewOptLevel == CodeGenOpt::None)
243 IS.TM.setFastISel(true);
244 DEBUG(dbgs() << "\nChanging optimization level for Function "
245 << IS.MF->getFunction()->getName() << "\n");
246 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
247 << " ; After: -O" << NewOptLevel << "\n");
251 if (IS.OptLevel == SavedOptLevel)
253 DEBUG(dbgs() << "\nRestoring optimization level for Function "
254 << IS.MF->getFunction()->getName() << "\n");
255 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
256 << " ; After: -O" << SavedOptLevel << "\n");
257 IS.OptLevel = SavedOptLevel;
258 IS.TM.setOptLevel(SavedOptLevel);
259 IS.TM.setFastISel(SavedFastISel);
263 //===--------------------------------------------------------------------===//
264 /// createDefaultScheduler - This creates an instruction scheduler appropriate
266 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
267 CodeGenOpt::Level OptLevel) {
268 const TargetLowering *TLI = IS->getTargetLowering();
269 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
271 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
272 TLI->getSchedulingPreference() == Sched::Source)
273 return createSourceListDAGScheduler(IS, OptLevel);
274 if (TLI->getSchedulingPreference() == Sched::RegPressure)
275 return createBURRListDAGScheduler(IS, OptLevel);
276 if (TLI->getSchedulingPreference() == Sched::Hybrid)
277 return createHybridListDAGScheduler(IS, OptLevel);
278 if (TLI->getSchedulingPreference() == Sched::VLIW)
279 return createVLIWDAGScheduler(IS, OptLevel);
280 assert(TLI->getSchedulingPreference() == Sched::ILP &&
281 "Unknown sched type!");
282 return createILPListDAGScheduler(IS, OptLevel);
286 // EmitInstrWithCustomInserter - This method should be implemented by targets
287 // that mark instructions with the 'usesCustomInserter' flag. These
288 // instructions are special in various ways, which require special support to
289 // insert. The specified MachineInstr is created but not inserted into any
290 // basic blocks, and this method is called to expand it into a sequence of
291 // instructions, potentially also creating new basic blocks and control flow.
292 // When new basic blocks are inserted and the edges from MBB to its successors
293 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
296 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
297 MachineBasicBlock *MBB) const {
299 dbgs() << "If a target marks an instruction with "
300 "'usesCustomInserter', it must implement "
301 "TargetLowering::EmitInstrWithCustomInserter!";
306 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
307 SDNode *Node) const {
308 assert(!MI->hasPostISelHook() &&
309 "If a target marks an instruction with 'hasPostISelHook', "
310 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
313 //===----------------------------------------------------------------------===//
314 // SelectionDAGISel code
315 //===----------------------------------------------------------------------===//
317 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
318 CodeGenOpt::Level OL) :
319 MachineFunctionPass(ID), TM(tm),
320 FuncInfo(new FunctionLoweringInfo(TM)),
321 CurDAG(new SelectionDAG(tm, OL)),
322 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
326 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
327 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
328 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
329 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
332 SelectionDAGISel::~SelectionDAGISel() {
338 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
339 AU.addRequired<AliasAnalysis>();
340 AU.addPreserved<AliasAnalysis>();
341 AU.addRequired<GCModuleInfo>();
342 AU.addPreserved<GCModuleInfo>();
343 AU.addRequired<TargetLibraryInfo>();
344 if (UseMBPI && OptLevel != CodeGenOpt::None)
345 AU.addRequired<BranchProbabilityInfo>();
346 MachineFunctionPass::getAnalysisUsage(AU);
349 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
350 /// may trap on it. In this case we have to split the edge so that the path
351 /// through the predecessor block that doesn't go to the phi block doesn't
352 /// execute the possibly trapping instruction.
354 /// This is required for correctness, so it must be done at -O0.
356 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
357 // Loop for blocks with phi nodes.
358 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
359 PHINode *PN = dyn_cast<PHINode>(BB->begin());
360 if (PN == 0) continue;
363 // For each block with a PHI node, check to see if any of the input values
364 // are potentially trapping constant expressions. Constant expressions are
365 // the only potentially trapping value that can occur as the argument to a
367 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
368 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
369 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
370 if (CE == 0 || !CE->canTrap()) continue;
372 // The only case we have to worry about is when the edge is critical.
373 // Since this block has a PHI Node, we assume it has multiple input
374 // edges: check to see if the pred has multiple successors.
375 BasicBlock *Pred = PN->getIncomingBlock(i);
376 if (Pred->getTerminator()->getNumSuccessors() == 1)
379 // Okay, we have to split this edge.
380 SplitCriticalEdge(Pred->getTerminator(),
381 GetSuccessorNumber(Pred, BB), SDISel, true);
387 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
388 // Do some sanity-checking on the command-line options.
389 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
390 "-fast-isel-verbose requires -fast-isel");
391 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
392 "-fast-isel-abort requires -fast-isel");
394 const Function &Fn = *mf.getFunction();
395 const TargetInstrInfo &TII = *TM.getInstrInfo();
396 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
397 const TargetLowering *TLI = TM.getTargetLowering();
400 RegInfo = &MF->getRegInfo();
401 AA = &getAnalysis<AliasAnalysis>();
402 LibInfo = &getAnalysis<TargetLibraryInfo>();
403 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
404 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
406 TargetSubtargetInfo &ST =
407 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
408 ST.resetSubtargetFeatures(MF);
409 TM.resetTargetOptions(MF);
411 // Reset OptLevel to None for optnone functions.
412 CodeGenOpt::Level NewOptLevel = OptLevel;
413 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
414 NewOptLevel = CodeGenOpt::None;
415 OptLevelChanger OLC(*this, NewOptLevel);
417 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
419 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
421 CurDAG->init(*MF, TTI, TLI);
422 FuncInfo->set(Fn, *MF);
424 if (UseMBPI && OptLevel != CodeGenOpt::None)
425 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
429 SDB->init(GFI, *AA, LibInfo);
431 MF->setHasInlineAsm(false);
432 MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(false);
434 SelectAllBasicBlocks(Fn);
436 // If the first basic block in the function has live ins that need to be
437 // copied into vregs, emit the copies into the top of the block before
438 // emitting the code for the block.
439 MachineBasicBlock *EntryMBB = MF->begin();
440 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
442 DenseMap<unsigned, unsigned> LiveInMap;
443 if (!FuncInfo->ArgDbgValues.empty())
444 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
445 E = RegInfo->livein_end(); LI != E; ++LI)
447 LiveInMap.insert(std::make_pair(LI->first, LI->second));
449 // Insert DBG_VALUE instructions for function arguments to the entry block.
450 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
451 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
452 bool hasFI = MI->getOperand(0).isFI();
454 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
455 if (TargetRegisterInfo::isPhysicalRegister(Reg))
456 EntryMBB->insert(EntryMBB->begin(), MI);
458 MachineInstr *Def = RegInfo->getVRegDef(Reg);
460 MachineBasicBlock::iterator InsertPos = Def;
461 // FIXME: VR def may not be in entry block.
462 Def->getParent()->insert(llvm::next(InsertPos), MI);
464 DEBUG(dbgs() << "Dropping debug info for dead vreg"
465 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
468 // If Reg is live-in then update debug info to track its copy in a vreg.
469 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
470 if (LDI != LiveInMap.end()) {
471 assert(!hasFI && "There's no handling of frame pointer updating here yet "
473 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
474 MachineBasicBlock::iterator InsertPos = Def;
475 const MDNode *Variable =
476 MI->getOperand(MI->getNumOperands()-1).getMetadata();
477 bool IsIndirect = MI->isIndirectDebugValue();
478 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
479 // Def is never a terminator here, so it is ok to increment InsertPos.
480 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
481 TII.get(TargetOpcode::DBG_VALUE),
483 LDI->second, Offset, Variable);
485 // If this vreg is directly copied into an exported register then
486 // that COPY instructions also need DBG_VALUE, if it is the only
487 // user of LDI->second.
488 MachineInstr *CopyUseMI = NULL;
489 for (MachineRegisterInfo::use_iterator
490 UI = RegInfo->use_begin(LDI->second);
491 MachineInstr *UseMI = UI.skipInstruction();) {
492 if (UseMI->isDebugValue()) continue;
493 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
494 CopyUseMI = UseMI; continue;
496 // Otherwise this is another use or second copy use.
497 CopyUseMI = NULL; break;
500 MachineInstr *NewMI =
501 BuildMI(*MF, CopyUseMI->getDebugLoc(),
502 TII.get(TargetOpcode::DBG_VALUE),
504 CopyUseMI->getOperand(0).getReg(),
506 MachineBasicBlock::iterator Pos = CopyUseMI;
507 EntryMBB->insertAfter(Pos, NewMI);
512 // Determine if there are any calls in this machine function.
513 MachineFrameInfo *MFI = MF->getFrameInfo();
514 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
517 if (MFI->hasCalls() && MF->hasInlineAsm())
520 const MachineBasicBlock *MBB = I;
521 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
523 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
524 if ((MCID.isCall() && !MCID.isReturn()) ||
525 II->isStackAligningInlineAsm()) {
526 MFI->setHasCalls(true);
528 if (II->isInlineAsm()) {
529 MF->setHasInlineAsm(true);
534 // Determine if there is a call to setjmp in the machine function.
535 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
537 // Replace forward-declared registers with the registers containing
538 // the desired value.
539 MachineRegisterInfo &MRI = MF->getRegInfo();
540 for (DenseMap<unsigned, unsigned>::iterator
541 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
543 unsigned From = I->first;
544 unsigned To = I->second;
545 // If To is also scheduled to be replaced, find what its ultimate
548 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
552 // Make sure the new register has a sufficiently constrained register class.
553 if (TargetRegisterInfo::isVirtualRegister(From) &&
554 TargetRegisterInfo::isVirtualRegister(To))
555 MRI.constrainRegClass(To, MRI.getRegClass(From));
557 MRI.replaceRegWith(From, To);
560 // Freeze the set of reserved registers now that MachineFrameInfo has been
561 // set up. All the information required by getReservedRegs() should be
563 MRI.freezeReservedRegs(*MF);
565 // Release function-specific state. SDB and CurDAG are already cleared
569 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
570 DEBUG(MF->print(dbgs()));
575 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
576 BasicBlock::const_iterator End,
578 // Lower all of the non-terminator instructions. If a call is emitted
579 // as a tail call, cease emitting nodes for this block. Terminators
580 // are handled below.
581 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
584 // Make sure the root of the DAG is up-to-date.
585 CurDAG->setRoot(SDB->getControlRoot());
586 HadTailCall = SDB->HasTailCall;
589 // Final step, emit the lowered DAG as machine code.
593 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
594 SmallPtrSet<SDNode*, 128> VisitedNodes;
595 SmallVector<SDNode*, 128> Worklist;
597 Worklist.push_back(CurDAG->getRoot().getNode());
603 SDNode *N = Worklist.pop_back_val();
605 // If we've already seen this node, ignore it.
606 if (!VisitedNodes.insert(N))
609 // Otherwise, add all chain operands to the worklist.
610 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
611 if (N->getOperand(i).getValueType() == MVT::Other)
612 Worklist.push_back(N->getOperand(i).getNode());
614 // If this is a CopyToReg with a vreg dest, process it.
615 if (N->getOpcode() != ISD::CopyToReg)
618 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
619 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
622 // Ignore non-scalar or non-integer values.
623 SDValue Src = N->getOperand(2);
624 EVT SrcVT = Src.getValueType();
625 if (!SrcVT.isInteger() || SrcVT.isVector())
628 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
629 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
630 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
631 } while (!Worklist.empty());
634 void SelectionDAGISel::CodeGenAndEmitDAG() {
635 std::string GroupName;
636 if (TimePassesIsEnabled)
637 GroupName = "Instruction Selection and Scheduling";
638 std::string BlockName;
639 int BlockNumber = -1;
642 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
643 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
647 BlockNumber = FuncInfo->MBB->getNumber();
648 BlockName = MF->getName().str() + ":" +
649 FuncInfo->MBB->getBasicBlock()->getName().str();
651 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
652 << " '" << BlockName << "'\n"; CurDAG->dump());
654 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
656 // Run the DAG combiner in pre-legalize mode.
658 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
659 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
662 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
663 << " '" << BlockName << "'\n"; CurDAG->dump());
665 // Second step, hack on the DAG until it only uses operations and types that
666 // the target supports.
667 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
672 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
673 Changed = CurDAG->LegalizeTypes();
676 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
677 << " '" << BlockName << "'\n"; CurDAG->dump());
679 CurDAG->NewNodesMustHaveLegalTypes = true;
682 if (ViewDAGCombineLT)
683 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
685 // Run the DAG combiner in post-type-legalize mode.
687 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
688 TimePassesIsEnabled);
689 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
692 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
693 << " '" << BlockName << "'\n"; CurDAG->dump());
698 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
699 Changed = CurDAG->LegalizeVectors();
704 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
705 CurDAG->LegalizeTypes();
708 if (ViewDAGCombineLT)
709 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
711 // Run the DAG combiner in post-type-legalize mode.
713 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
714 TimePassesIsEnabled);
715 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
718 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
719 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
722 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
725 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
729 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
730 << " '" << BlockName << "'\n"; CurDAG->dump());
732 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
734 // Run the DAG combiner in post-legalize mode.
736 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
737 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
740 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
741 << " '" << BlockName << "'\n"; CurDAG->dump());
743 if (OptLevel != CodeGenOpt::None)
744 ComputeLiveOutVRegInfo();
746 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
748 // Third, instruction select all of the operations to machine code, adding the
749 // code to the MachineBasicBlock.
751 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
752 DoInstructionSelection();
755 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
756 << " '" << BlockName << "'\n"; CurDAG->dump());
758 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
760 // Schedule machine code.
761 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
763 NamedRegionTimer T("Instruction Scheduling", GroupName,
764 TimePassesIsEnabled);
765 Scheduler->Run(CurDAG, FuncInfo->MBB);
768 if (ViewSUnitDAGs) Scheduler->viewGraph();
770 // Emit machine code to BB. This can change 'BB' to the last block being
772 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
774 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
776 // FuncInfo->InsertPt is passed by reference and set to the end of the
777 // scheduled instructions.
778 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
781 // If the block was split, make sure we update any references that are used to
782 // update PHI nodes later on.
783 if (FirstMBB != LastMBB)
784 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
786 // Free the scheduler state.
788 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
789 TimePassesIsEnabled);
793 // Free the SelectionDAG state, now that we're finished with it.
798 /// ISelUpdater - helper class to handle updates of the instruction selection
800 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
801 SelectionDAG::allnodes_iterator &ISelPosition;
803 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
804 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
806 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
807 /// deleted is the current ISelPosition node, update ISelPosition.
809 virtual void NodeDeleted(SDNode *N, SDNode *E) {
810 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
814 } // end anonymous namespace
816 void SelectionDAGISel::DoInstructionSelection() {
817 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
818 << FuncInfo->MBB->getNumber()
819 << " '" << FuncInfo->MBB->getName() << "'\n");
823 // Select target instructions for the DAG.
825 // Number all nodes with a topological order and set DAGSize.
826 DAGSize = CurDAG->AssignTopologicalOrder();
828 // Create a dummy node (which is not added to allnodes), that adds
829 // a reference to the root node, preventing it from being deleted,
830 // and tracking any changes of the root.
831 HandleSDNode Dummy(CurDAG->getRoot());
832 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
835 // Make sure that ISelPosition gets properly updated when nodes are deleted
836 // in calls made from this function.
837 ISelUpdater ISU(*CurDAG, ISelPosition);
839 // The AllNodes list is now topological-sorted. Visit the
840 // nodes by starting at the end of the list (the root of the
841 // graph) and preceding back toward the beginning (the entry
843 while (ISelPosition != CurDAG->allnodes_begin()) {
844 SDNode *Node = --ISelPosition;
845 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
846 // but there are currently some corner cases that it misses. Also, this
847 // makes it theoretically possible to disable the DAGCombiner.
848 if (Node->use_empty())
851 SDNode *ResNode = Select(Node);
853 // FIXME: This is pretty gross. 'Select' should be changed to not return
854 // anything at all and this code should be nuked with a tactical strike.
856 // If node should not be replaced, continue with the next one.
857 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
861 ReplaceUses(Node, ResNode);
864 // If after the replacement this node is not used any more,
865 // remove this dead node.
866 if (Node->use_empty()) // Don't delete EntryToken, etc.
867 CurDAG->RemoveDeadNode(Node);
870 CurDAG->setRoot(Dummy.getValue());
873 DEBUG(dbgs() << "===== Instruction selection ends:\n");
875 PostprocessISelDAG();
878 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
879 /// do other setup for EH landing-pad blocks.
880 void SelectionDAGISel::PrepareEHLandingPad() {
881 MachineBasicBlock *MBB = FuncInfo->MBB;
883 // Add a label to mark the beginning of the landing pad. Deletion of the
884 // landing pad can thus be detected via the MachineModuleInfo.
885 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
887 // Assign the call site to the landing pad's begin label.
888 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
890 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
891 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
894 // Mark exception register as live in.
895 const TargetLowering *TLI = getTargetLowering();
896 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
897 if (unsigned Reg = TLI->getExceptionPointerRegister())
898 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
900 // Mark exception selector register as live in.
901 if (unsigned Reg = TLI->getExceptionSelectorRegister())
902 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
905 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
906 /// side-effect free and is either dead or folded into a generated instruction.
907 /// Return false if it needs to be emitted.
908 static bool isFoldedOrDeadInstruction(const Instruction *I,
909 FunctionLoweringInfo *FuncInfo) {
910 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
911 !isa<TerminatorInst>(I) && // Terminators aren't folded.
912 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
913 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
914 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
918 // Collect per Instruction statistics for fast-isel misses. Only those
919 // instructions that cause the bail are accounted for. It does not account for
920 // instructions higher in the block. Thus, summing the per instructions stats
921 // will not add up to what is reported by NumFastIselFailures.
922 static void collectFailStats(const Instruction *I) {
923 switch (I->getOpcode()) {
924 default: assert (0 && "<Invalid operator> ");
927 case Instruction::Ret: NumFastIselFailRet++; return;
928 case Instruction::Br: NumFastIselFailBr++; return;
929 case Instruction::Switch: NumFastIselFailSwitch++; return;
930 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
931 case Instruction::Invoke: NumFastIselFailInvoke++; return;
932 case Instruction::Resume: NumFastIselFailResume++; return;
933 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
935 // Standard binary operators...
936 case Instruction::Add: NumFastIselFailAdd++; return;
937 case Instruction::FAdd: NumFastIselFailFAdd++; return;
938 case Instruction::Sub: NumFastIselFailSub++; return;
939 case Instruction::FSub: NumFastIselFailFSub++; return;
940 case Instruction::Mul: NumFastIselFailMul++; return;
941 case Instruction::FMul: NumFastIselFailFMul++; return;
942 case Instruction::UDiv: NumFastIselFailUDiv++; return;
943 case Instruction::SDiv: NumFastIselFailSDiv++; return;
944 case Instruction::FDiv: NumFastIselFailFDiv++; return;
945 case Instruction::URem: NumFastIselFailURem++; return;
946 case Instruction::SRem: NumFastIselFailSRem++; return;
947 case Instruction::FRem: NumFastIselFailFRem++; return;
949 // Logical operators...
950 case Instruction::And: NumFastIselFailAnd++; return;
951 case Instruction::Or: NumFastIselFailOr++; return;
952 case Instruction::Xor: NumFastIselFailXor++; return;
954 // Memory instructions...
955 case Instruction::Alloca: NumFastIselFailAlloca++; return;
956 case Instruction::Load: NumFastIselFailLoad++; return;
957 case Instruction::Store: NumFastIselFailStore++; return;
958 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
959 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
960 case Instruction::Fence: NumFastIselFailFence++; return;
961 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
963 // Convert instructions...
964 case Instruction::Trunc: NumFastIselFailTrunc++; return;
965 case Instruction::ZExt: NumFastIselFailZExt++; return;
966 case Instruction::SExt: NumFastIselFailSExt++; return;
967 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
968 case Instruction::FPExt: NumFastIselFailFPExt++; return;
969 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
970 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
971 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
972 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
973 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
974 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
975 case Instruction::BitCast: NumFastIselFailBitCast++; return;
977 // Other instructions...
978 case Instruction::ICmp: NumFastIselFailICmp++; return;
979 case Instruction::FCmp: NumFastIselFailFCmp++; return;
980 case Instruction::PHI: NumFastIselFailPHI++; return;
981 case Instruction::Select: NumFastIselFailSelect++; return;
982 case Instruction::Call: NumFastIselFailCall++; return;
983 case Instruction::Shl: NumFastIselFailShl++; return;
984 case Instruction::LShr: NumFastIselFailLShr++; return;
985 case Instruction::AShr: NumFastIselFailAShr++; return;
986 case Instruction::VAArg: NumFastIselFailVAArg++; return;
987 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
988 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
989 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
990 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
991 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
992 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
997 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
998 // Initialize the Fast-ISel state, if needed.
999 FastISel *FastIS = 0;
1000 if (TM.Options.EnableFastISel)
1001 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo);
1003 // Iterate over all basic blocks in the function.
1004 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1005 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1006 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1007 const BasicBlock *LLVMBB = *I;
1009 if (OptLevel != CodeGenOpt::None) {
1010 bool AllPredsVisited = true;
1011 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1013 if (!FuncInfo->VisitedBBs.count(*PI)) {
1014 AllPredsVisited = false;
1019 if (AllPredsVisited) {
1020 for (BasicBlock::const_iterator I = LLVMBB->begin();
1021 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1022 FuncInfo->ComputePHILiveOutRegInfo(PN);
1024 for (BasicBlock::const_iterator I = LLVMBB->begin();
1025 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1026 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1029 FuncInfo->VisitedBBs.insert(LLVMBB);
1032 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1033 BasicBlock::const_iterator const End = LLVMBB->end();
1034 BasicBlock::const_iterator BI = End;
1036 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1037 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1039 // Setup an EH landing-pad block.
1040 FuncInfo->ExceptionPointerVirtReg = 0;
1041 FuncInfo->ExceptionSelectorVirtReg = 0;
1042 if (FuncInfo->MBB->isLandingPad())
1043 PrepareEHLandingPad();
1045 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1047 FastIS->startNewBlock();
1049 // Emit code for any incoming arguments. This must happen before
1050 // beginning FastISel on the entry block.
1051 if (LLVMBB == &Fn.getEntryBlock()) {
1054 // Lower any arguments needed in this block if this is the entry block.
1055 if (!FastIS->LowerArguments()) {
1056 // Fast isel failed to lower these arguments
1057 ++NumFastIselFailLowerArguments;
1058 if (EnableFastISelAbortArgs)
1059 llvm_unreachable("FastISel didn't lower all arguments");
1061 // Use SelectionDAG argument lowering
1063 CurDAG->setRoot(SDB->getControlRoot());
1065 CodeGenAndEmitDAG();
1068 // If we inserted any instructions at the beginning, make a note of
1069 // where they are, so we can be sure to emit subsequent instructions
1071 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1072 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1074 FastIS->setLastLocalValue(0);
1077 unsigned NumFastIselRemaining = std::distance(Begin, End);
1078 // Do FastISel on as many instructions as possible.
1079 for (; BI != Begin; --BI) {
1080 const Instruction *Inst = llvm::prior(BI);
1082 // If we no longer require this instruction, skip it.
1083 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1084 --NumFastIselRemaining;
1088 // Bottom-up: reset the insert pos at the top, after any local-value
1090 FastIS->recomputeInsertPt();
1092 // Try to select the instruction with FastISel.
1093 if (FastIS->SelectInstruction(Inst)) {
1094 --NumFastIselRemaining;
1095 ++NumFastIselSuccess;
1096 // If fast isel succeeded, skip over all the folded instructions, and
1097 // then see if there is a load right before the selected instructions.
1098 // Try to fold the load if so.
1099 const Instruction *BeforeInst = Inst;
1100 while (BeforeInst != Begin) {
1101 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1102 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1105 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1106 BeforeInst->hasOneUse() &&
1107 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1108 // If we succeeded, don't re-select the load.
1109 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1110 --NumFastIselRemaining;
1111 ++NumFastIselSuccess;
1117 if (EnableFastISelVerbose2)
1118 collectFailStats(Inst);
1121 // Then handle certain instructions as single-LLVM-Instruction blocks.
1122 if (isa<CallInst>(Inst)) {
1124 if (EnableFastISelVerbose || EnableFastISelAbort) {
1125 dbgs() << "FastISel missed call: ";
1129 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1130 unsigned &R = FuncInfo->ValueMap[Inst];
1132 R = FuncInfo->CreateRegs(Inst->getType());
1135 bool HadTailCall = false;
1136 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1137 SelectBasicBlock(Inst, BI, HadTailCall);
1139 // If the call was emitted as a tail call, we're done with the block.
1140 // We also need to delete any previously emitted instructions.
1142 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1147 // Recompute NumFastIselRemaining as Selection DAG instruction
1148 // selection may have handled the call, input args, etc.
1149 unsigned RemainingNow = std::distance(Begin, BI);
1150 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1151 NumFastIselRemaining = RemainingNow;
1155 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1156 // Don't abort, and use a different message for terminator misses.
1157 NumFastIselFailures += NumFastIselRemaining;
1158 if (EnableFastISelVerbose || EnableFastISelAbort) {
1159 dbgs() << "FastISel missed terminator: ";
1163 NumFastIselFailures += NumFastIselRemaining;
1164 if (EnableFastISelVerbose || EnableFastISelAbort) {
1165 dbgs() << "FastISel miss: ";
1168 if (EnableFastISelAbort)
1169 // The "fast" selector couldn't handle something and bailed.
1170 // For the purpose of debugging, just abort.
1171 llvm_unreachable("FastISel didn't select the entire block");
1176 FastIS->recomputeInsertPt();
1178 // Lower any arguments needed in this block if this is the entry block.
1179 if (LLVMBB == &Fn.getEntryBlock()) {
1188 ++NumFastIselBlocks;
1191 // Run SelectionDAG instruction selection on the remainder of the block
1192 // not handled by FastISel. If FastISel is not run, this is the entire
1195 SelectBasicBlock(Begin, BI, HadTailCall);
1199 FuncInfo->PHINodesToUpdate.clear();
1203 SDB->clearDanglingDebugInfo();
1204 SDB->SPDescriptor.resetPerFunctionState();
1207 /// Given that the input MI is before a partial terminator sequence TSeq, return
1208 /// true if M + TSeq also a partial terminator sequence.
1210 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1211 /// lowering copy vregs into physical registers, which are then passed into
1212 /// terminator instructors so we can satisfy ABI constraints. A partial
1213 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1214 /// may be the whole terminator sequence).
1215 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1216 // If we do not have a copy or an implicit def, we return true if and only if
1217 // MI is a debug value.
1218 if (!MI->isCopy() && !MI->isImplicitDef())
1219 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1220 // physical registers if there is debug info associated with the terminator
1221 // of our mbb. We want to include said debug info in our terminator
1222 // sequence, so we return true in that case.
1223 return MI->isDebugValue();
1225 // We have left the terminator sequence if we are not doing one of the
1228 // 1. Copying a vreg into a physical register.
1229 // 2. Copying a vreg into a vreg.
1230 // 3. Defining a register via an implicit def.
1232 // OPI should always be a register definition...
1233 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1234 if (!OPI->isReg() || !OPI->isDef())
1237 // Defining any register via an implicit def is always ok.
1238 if (MI->isImplicitDef())
1241 // Grab the copy source...
1242 MachineInstr::const_mop_iterator OPI2 = OPI;
1244 assert(OPI2 != MI->operands_end()
1245 && "Should have a copy implying we should have 2 arguments.");
1247 // Make sure that the copy dest is not a vreg when the copy source is a
1248 // physical register.
1249 if (!OPI2->isReg() ||
1250 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1251 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1257 /// Find the split point at which to splice the end of BB into its success stack
1258 /// protector check machine basic block.
1260 /// On many platforms, due to ABI constraints, terminators, even before register
1261 /// allocation, use physical registers. This creates an issue for us since
1262 /// physical registers at this point can not travel across basic
1263 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1264 /// when they enter functions and moves them through a sequence of copies back
1265 /// into the physical registers right before the terminator creating a
1266 /// ``Terminator Sequence''. This function is searching for the beginning of the
1267 /// terminator sequence so that we can ensure that we splice off not just the
1268 /// terminator, but additionally the copies that move the vregs into the
1269 /// physical registers.
1270 static MachineBasicBlock::iterator
1271 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1272 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1274 if (SplitPoint == BB->begin())
1277 MachineBasicBlock::iterator Start = BB->begin();
1278 MachineBasicBlock::iterator Previous = SplitPoint;
1281 while (MIIsInTerminatorSequence(Previous)) {
1282 SplitPoint = Previous;
1283 if (Previous == Start)
1292 SelectionDAGISel::FinishBasicBlock() {
1294 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1295 << FuncInfo->PHINodesToUpdate.size() << "\n";
1296 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1297 dbgs() << "Node " << i << " : ("
1298 << FuncInfo->PHINodesToUpdate[i].first
1299 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1301 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1302 SDB->JTCases.empty() &&
1303 SDB->BitTestCases.empty();
1305 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1306 // PHI nodes in successors.
1307 if (MustUpdatePHINodes) {
1308 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1309 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1310 assert(PHI->isPHI() &&
1311 "This is not a machine PHI node that we are updating!");
1312 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1314 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1318 // Handle stack protector.
1319 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1320 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1321 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1323 // Find the split point to split the parent mbb. At the same time copy all
1324 // physical registers used in the tail of parent mbb into virtual registers
1325 // before the split point and back into physical registers after the split
1326 // point. This prevents us needing to deal with Live-ins and many other
1327 // register allocation issues caused by us splitting the parent mbb. The
1328 // register allocator will clean up said virtual copies later on.
1329 MachineBasicBlock::iterator SplitPoint =
1330 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1332 // Splice the terminator of ParentMBB into SuccessMBB.
1333 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1337 // Add compare/jump on neq/jump to the parent BB.
1338 FuncInfo->MBB = ParentMBB;
1339 FuncInfo->InsertPt = ParentMBB->end();
1340 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1341 CurDAG->setRoot(SDB->getRoot());
1343 CodeGenAndEmitDAG();
1345 // CodeGen Failure MBB if we have not codegened it yet.
1346 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1347 if (!FailureMBB->size()) {
1348 FuncInfo->MBB = FailureMBB;
1349 FuncInfo->InsertPt = FailureMBB->end();
1350 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1351 CurDAG->setRoot(SDB->getRoot());
1353 CodeGenAndEmitDAG();
1356 // Clear the Per-BB State.
1357 SDB->SPDescriptor.resetPerBBState();
1360 // If we updated PHI Nodes, return early.
1361 if (MustUpdatePHINodes)
1364 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1365 // Lower header first, if it wasn't already lowered
1366 if (!SDB->BitTestCases[i].Emitted) {
1367 // Set the current basic block to the mbb we wish to insert the code into
1368 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1369 FuncInfo->InsertPt = FuncInfo->MBB->end();
1371 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1372 CurDAG->setRoot(SDB->getRoot());
1374 CodeGenAndEmitDAG();
1377 uint32_t UnhandledWeight = 0;
1378 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1379 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1381 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1382 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1383 // Set the current basic block to the mbb we wish to insert the code into
1384 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1385 FuncInfo->InsertPt = FuncInfo->MBB->end();
1388 SDB->visitBitTestCase(SDB->BitTestCases[i],
1389 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1391 SDB->BitTestCases[i].Reg,
1392 SDB->BitTestCases[i].Cases[j],
1395 SDB->visitBitTestCase(SDB->BitTestCases[i],
1396 SDB->BitTestCases[i].Default,
1398 SDB->BitTestCases[i].Reg,
1399 SDB->BitTestCases[i].Cases[j],
1403 CurDAG->setRoot(SDB->getRoot());
1405 CodeGenAndEmitDAG();
1409 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1411 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1412 MachineBasicBlock *PHIBB = PHI->getParent();
1413 assert(PHI->isPHI() &&
1414 "This is not a machine PHI node that we are updating!");
1415 // This is "default" BB. We have two jumps to it. From "header" BB and
1416 // from last "case" BB.
1417 if (PHIBB == SDB->BitTestCases[i].Default)
1418 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1419 .addMBB(SDB->BitTestCases[i].Parent)
1420 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1421 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1422 // One of "cases" BB.
1423 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1425 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1426 if (cBB->isSuccessor(PHIBB))
1427 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1431 SDB->BitTestCases.clear();
1433 // If the JumpTable record is filled in, then we need to emit a jump table.
1434 // Updating the PHI nodes is tricky in this case, since we need to determine
1435 // whether the PHI is a successor of the range check MBB or the jump table MBB
1436 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1437 // Lower header first, if it wasn't already lowered
1438 if (!SDB->JTCases[i].first.Emitted) {
1439 // Set the current basic block to the mbb we wish to insert the code into
1440 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1441 FuncInfo->InsertPt = FuncInfo->MBB->end();
1443 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1445 CurDAG->setRoot(SDB->getRoot());
1447 CodeGenAndEmitDAG();
1450 // Set the current basic block to the mbb we wish to insert the code into
1451 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1452 FuncInfo->InsertPt = FuncInfo->MBB->end();
1454 SDB->visitJumpTable(SDB->JTCases[i].second);
1455 CurDAG->setRoot(SDB->getRoot());
1457 CodeGenAndEmitDAG();
1460 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1462 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1463 MachineBasicBlock *PHIBB = PHI->getParent();
1464 assert(PHI->isPHI() &&
1465 "This is not a machine PHI node that we are updating!");
1466 // "default" BB. We can go there only from header BB.
1467 if (PHIBB == SDB->JTCases[i].second.Default)
1468 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1469 .addMBB(SDB->JTCases[i].first.HeaderBB);
1470 // JT BB. Just iterate over successors here
1471 if (FuncInfo->MBB->isSuccessor(PHIBB))
1472 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1475 SDB->JTCases.clear();
1477 // If the switch block involved a branch to one of the actual successors, we
1478 // need to update PHI nodes in that block.
1479 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1480 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1481 assert(PHI->isPHI() &&
1482 "This is not a machine PHI node that we are updating!");
1483 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1484 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1487 // If we generated any switch lowering information, build and codegen any
1488 // additional DAGs necessary.
1489 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1490 // Set the current basic block to the mbb we wish to insert the code into
1491 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1492 FuncInfo->InsertPt = FuncInfo->MBB->end();
1494 // Determine the unique successors.
1495 SmallVector<MachineBasicBlock *, 2> Succs;
1496 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1497 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1498 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1500 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1501 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1502 CurDAG->setRoot(SDB->getRoot());
1504 CodeGenAndEmitDAG();
1506 // Remember the last block, now that any splitting is done, for use in
1507 // populating PHI nodes in successors.
1508 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1510 // Handle any PHI nodes in successors of this chunk, as if we were coming
1511 // from the original BB before switch expansion. Note that PHI nodes can
1512 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1513 // handle them the right number of times.
1514 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1515 FuncInfo->MBB = Succs[i];
1516 FuncInfo->InsertPt = FuncInfo->MBB->end();
1517 // FuncInfo->MBB may have been removed from the CFG if a branch was
1519 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1520 for (MachineBasicBlock::iterator
1521 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1522 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1523 MachineInstrBuilder PHI(*MF, MBBI);
1524 // This value for this PHI node is recorded in PHINodesToUpdate.
1525 for (unsigned pn = 0; ; ++pn) {
1526 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1527 "Didn't find PHI entry!");
1528 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1529 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1537 SDB->SwitchCases.clear();
1541 /// Create the scheduler. If a specific scheduler was specified
1542 /// via the SchedulerRegistry, use it, otherwise select the
1543 /// one preferred by the target.
1545 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1546 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1550 RegisterScheduler::setDefault(Ctor);
1553 return Ctor(this, OptLevel);
1556 //===----------------------------------------------------------------------===//
1557 // Helper functions used by the generated instruction selector.
1558 //===----------------------------------------------------------------------===//
1559 // Calls to these methods are generated by tblgen.
1561 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1562 /// the dag combiner simplified the 255, we still want to match. RHS is the
1563 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1564 /// specified in the .td file (e.g. 255).
1565 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1566 int64_t DesiredMaskS) const {
1567 const APInt &ActualMask = RHS->getAPIntValue();
1568 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1570 // If the actual mask exactly matches, success!
1571 if (ActualMask == DesiredMask)
1574 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1575 if (ActualMask.intersects(~DesiredMask))
1578 // Otherwise, the DAG Combiner may have proven that the value coming in is
1579 // either already zero or is not demanded. Check for known zero input bits.
1580 APInt NeededMask = DesiredMask & ~ActualMask;
1581 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1584 // TODO: check to see if missing bits are just not demanded.
1586 // Otherwise, this pattern doesn't match.
1590 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1591 /// the dag combiner simplified the 255, we still want to match. RHS is the
1592 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1593 /// specified in the .td file (e.g. 255).
1594 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1595 int64_t DesiredMaskS) const {
1596 const APInt &ActualMask = RHS->getAPIntValue();
1597 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1599 // If the actual mask exactly matches, success!
1600 if (ActualMask == DesiredMask)
1603 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1604 if (ActualMask.intersects(~DesiredMask))
1607 // Otherwise, the DAG Combiner may have proven that the value coming in is
1608 // either already zero or is not demanded. Check for known zero input bits.
1609 APInt NeededMask = DesiredMask & ~ActualMask;
1611 APInt KnownZero, KnownOne;
1612 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1614 // If all the missing bits in the or are already known to be set, match!
1615 if ((NeededMask & KnownOne) == NeededMask)
1618 // TODO: check to see if missing bits are just not demanded.
1620 // Otherwise, this pattern doesn't match.
1625 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1626 /// by tblgen. Others should not call it.
1627 void SelectionDAGISel::
1628 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1629 std::vector<SDValue> InOps;
1630 std::swap(InOps, Ops);
1632 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1633 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1634 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1635 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1637 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1638 if (InOps[e-1].getValueType() == MVT::Glue)
1639 --e; // Don't process a glue operand if it is here.
1642 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1643 if (!InlineAsm::isMemKind(Flags)) {
1644 // Just skip over this operand, copying the operands verbatim.
1645 Ops.insert(Ops.end(), InOps.begin()+i,
1646 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1647 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1649 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1650 "Memory operand with multiple values?");
1651 // Otherwise, this is a memory operand. Ask the target to select it.
1652 std::vector<SDValue> SelOps;
1653 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1654 report_fatal_error("Could not match memory address. Inline asm"
1657 // Add this to the output node.
1659 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1660 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1661 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1666 // Add the glue input back if present.
1667 if (e != InOps.size())
1668 Ops.push_back(InOps.back());
1671 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1674 static SDNode *findGlueUse(SDNode *N) {
1675 unsigned FlagResNo = N->getNumValues()-1;
1676 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1677 SDUse &Use = I.getUse();
1678 if (Use.getResNo() == FlagResNo)
1679 return Use.getUser();
1684 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1685 /// This function recursively traverses up the operand chain, ignoring
1687 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1688 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1689 bool IgnoreChains) {
1690 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1691 // greater than all of its (recursive) operands. If we scan to a point where
1692 // 'use' is smaller than the node we're scanning for, then we know we will
1695 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1696 // happen because we scan down to newly selected nodes in the case of glue
1698 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1701 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1702 // won't fail if we scan it again.
1703 if (!Visited.insert(Use))
1706 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1707 // Ignore chain uses, they are validated by HandleMergeInputChains.
1708 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1711 SDNode *N = Use->getOperand(i).getNode();
1713 if (Use == ImmedUse || Use == Root)
1714 continue; // We are not looking for immediate use.
1719 // Traverse up the operand chain.
1720 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1726 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1727 /// operand node N of U during instruction selection that starts at Root.
1728 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1729 SDNode *Root) const {
1730 if (OptLevel == CodeGenOpt::None) return false;
1731 return N.hasOneUse();
1734 /// IsLegalToFold - Returns true if the specific operand node N of
1735 /// U can be folded during instruction selection that starts at Root.
1736 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1737 CodeGenOpt::Level OptLevel,
1738 bool IgnoreChains) {
1739 if (OptLevel == CodeGenOpt::None) return false;
1741 // If Root use can somehow reach N through a path that that doesn't contain
1742 // U then folding N would create a cycle. e.g. In the following
1743 // diagram, Root can reach N through X. If N is folded into into Root, then
1744 // X is both a predecessor and a successor of U.
1755 // * indicates nodes to be folded together.
1757 // If Root produces glue, then it gets (even more) interesting. Since it
1758 // will be "glued" together with its glue use in the scheduler, we need to
1759 // check if it might reach N.
1778 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1779 // (call it Fold), then X is a predecessor of GU and a successor of
1780 // Fold. But since Fold and GU are glued together, this will create
1781 // a cycle in the scheduling graph.
1783 // If the node has glue, walk down the graph to the "lowest" node in the
1785 EVT VT = Root->getValueType(Root->getNumValues()-1);
1786 while (VT == MVT::Glue) {
1787 SDNode *GU = findGlueUse(Root);
1791 VT = Root->getValueType(Root->getNumValues()-1);
1793 // If our query node has a glue result with a use, we've walked up it. If
1794 // the user (which has already been selected) has a chain or indirectly uses
1795 // the chain, our WalkChainUsers predicate will not consider it. Because of
1796 // this, we cannot ignore chains in this predicate.
1797 IgnoreChains = false;
1801 SmallPtrSet<SDNode*, 16> Visited;
1802 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1805 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1806 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1807 SelectInlineAsmMemoryOperands(Ops);
1809 EVT VTs[] = { MVT::Other, MVT::Glue };
1810 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
1811 VTs, &Ops[0], Ops.size());
1813 return New.getNode();
1816 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1817 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1820 /// GetVBR - decode a vbr encoding whose top bit is set.
1821 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1822 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1823 assert(Val >= 128 && "Not a VBR");
1824 Val &= 127; // Remove first vbr bit.
1829 NextBits = MatcherTable[Idx++];
1830 Val |= (NextBits&127) << Shift;
1832 } while (NextBits & 128);
1838 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1839 /// interior glue and chain results to use the new glue and chain results.
1840 void SelectionDAGISel::
1841 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1842 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1844 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1845 bool isMorphNodeTo) {
1846 SmallVector<SDNode*, 4> NowDeadNodes;
1848 // Now that all the normal results are replaced, we replace the chain and
1849 // glue results if present.
1850 if (!ChainNodesMatched.empty()) {
1851 assert(InputChain.getNode() != 0 &&
1852 "Matched input chains but didn't produce a chain");
1853 // Loop over all of the nodes we matched that produced a chain result.
1854 // Replace all the chain results with the final chain we ended up with.
1855 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1856 SDNode *ChainNode = ChainNodesMatched[i];
1858 // If this node was already deleted, don't look at it.
1859 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1862 // Don't replace the results of the root node if we're doing a
1864 if (ChainNode == NodeToMatch && isMorphNodeTo)
1867 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1868 if (ChainVal.getValueType() == MVT::Glue)
1869 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1870 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1871 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1873 // If the node became dead and we haven't already seen it, delete it.
1874 if (ChainNode->use_empty() &&
1875 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1876 NowDeadNodes.push_back(ChainNode);
1880 // If the result produces glue, update any glue results in the matched
1881 // pattern with the glue result.
1882 if (InputGlue.getNode() != 0) {
1883 // Handle any interior nodes explicitly marked.
1884 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1885 SDNode *FRN = GlueResultNodesMatched[i];
1887 // If this node was already deleted, don't look at it.
1888 if (FRN->getOpcode() == ISD::DELETED_NODE)
1891 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1892 "Doesn't have a glue result");
1893 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1896 // If the node became dead and we haven't already seen it, delete it.
1897 if (FRN->use_empty() &&
1898 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1899 NowDeadNodes.push_back(FRN);
1903 if (!NowDeadNodes.empty())
1904 CurDAG->RemoveDeadNodes(NowDeadNodes);
1906 DEBUG(dbgs() << "ISEL: Match complete!\n");
1912 CR_LeadsToInteriorNode
1915 /// WalkChainUsers - Walk down the users of the specified chained node that is
1916 /// part of the pattern we're matching, looking at all of the users we find.
1917 /// This determines whether something is an interior node, whether we have a
1918 /// non-pattern node in between two pattern nodes (which prevent folding because
1919 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1920 /// between pattern nodes (in which case the TF becomes part of the pattern).
1922 /// The walk we do here is guaranteed to be small because we quickly get down to
1923 /// already selected nodes "below" us.
1925 WalkChainUsers(const SDNode *ChainedNode,
1926 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1927 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1928 ChainResult Result = CR_Simple;
1930 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1931 E = ChainedNode->use_end(); UI != E; ++UI) {
1932 // Make sure the use is of the chain, not some other value we produce.
1933 if (UI.getUse().getValueType() != MVT::Other) continue;
1937 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1940 // If we see an already-selected machine node, then we've gone beyond the
1941 // pattern that we're selecting down into the already selected chunk of the
1943 unsigned UserOpcode = User->getOpcode();
1944 if (User->isMachineOpcode() ||
1945 UserOpcode == ISD::CopyToReg ||
1946 UserOpcode == ISD::CopyFromReg ||
1947 UserOpcode == ISD::INLINEASM ||
1948 UserOpcode == ISD::EH_LABEL ||
1949 UserOpcode == ISD::LIFETIME_START ||
1950 UserOpcode == ISD::LIFETIME_END) {
1951 // If their node ID got reset to -1 then they've already been selected.
1952 // Treat them like a MachineOpcode.
1953 if (User->getNodeId() == -1)
1957 // If we have a TokenFactor, we handle it specially.
1958 if (User->getOpcode() != ISD::TokenFactor) {
1959 // If the node isn't a token factor and isn't part of our pattern, then it
1960 // must be a random chained node in between two nodes we're selecting.
1961 // This happens when we have something like:
1966 // Because we structurally match the load/store as a read/modify/write,
1967 // but the call is chained between them. We cannot fold in this case
1968 // because it would induce a cycle in the graph.
1969 if (!std::count(ChainedNodesInPattern.begin(),
1970 ChainedNodesInPattern.end(), User))
1971 return CR_InducesCycle;
1973 // Otherwise we found a node that is part of our pattern. For example in:
1977 // This would happen when we're scanning down from the load and see the
1978 // store as a user. Record that there is a use of ChainedNode that is
1979 // part of the pattern and keep scanning uses.
1980 Result = CR_LeadsToInteriorNode;
1981 InteriorChainedNodes.push_back(User);
1985 // If we found a TokenFactor, there are two cases to consider: first if the
1986 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1987 // uses of the TF are in our pattern) we just want to ignore it. Second,
1988 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1994 // | \ DAG's like cheese
1997 // [TokenFactor] [Op]
2004 // In this case, the TokenFactor becomes part of our match and we rewrite it
2005 // as a new TokenFactor.
2007 // To distinguish these two cases, do a recursive walk down the uses.
2008 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2010 // If the uses of the TokenFactor are just already-selected nodes, ignore
2011 // it, it is "below" our pattern.
2013 case CR_InducesCycle:
2014 // If the uses of the TokenFactor lead to nodes that are not part of our
2015 // pattern that are not selected, folding would turn this into a cycle,
2017 return CR_InducesCycle;
2018 case CR_LeadsToInteriorNode:
2019 break; // Otherwise, keep processing.
2022 // Okay, we know we're in the interesting interior case. The TokenFactor
2023 // is now going to be considered part of the pattern so that we rewrite its
2024 // uses (it may have uses that are not part of the pattern) with the
2025 // ultimate chain result of the generated code. We will also add its chain
2026 // inputs as inputs to the ultimate TokenFactor we create.
2027 Result = CR_LeadsToInteriorNode;
2028 ChainedNodesInPattern.push_back(User);
2029 InteriorChainedNodes.push_back(User);
2036 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2037 /// operation for when the pattern matched at least one node with a chains. The
2038 /// input vector contains a list of all of the chained nodes that we match. We
2039 /// must determine if this is a valid thing to cover (i.e. matching it won't
2040 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2041 /// be used as the input node chain for the generated nodes.
2043 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2044 SelectionDAG *CurDAG) {
2045 // Walk all of the chained nodes we've matched, recursively scanning down the
2046 // users of the chain result. This adds any TokenFactor nodes that are caught
2047 // in between chained nodes to the chained and interior nodes list.
2048 SmallVector<SDNode*, 3> InteriorChainedNodes;
2049 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2050 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2051 InteriorChainedNodes) == CR_InducesCycle)
2052 return SDValue(); // Would induce a cycle.
2055 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2056 // that we are interested in. Form our input TokenFactor node.
2057 SmallVector<SDValue, 3> InputChains;
2058 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2059 // Add the input chain of this node to the InputChains list (which will be
2060 // the operands of the generated TokenFactor) if it's not an interior node.
2061 SDNode *N = ChainNodesMatched[i];
2062 if (N->getOpcode() != ISD::TokenFactor) {
2063 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2066 // Otherwise, add the input chain.
2067 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2068 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2069 InputChains.push_back(InChain);
2073 // If we have a token factor, we want to add all inputs of the token factor
2074 // that are not part of the pattern we're matching.
2075 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2076 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2077 N->getOperand(op).getNode()))
2078 InputChains.push_back(N->getOperand(op));
2082 if (InputChains.size() == 1)
2083 return InputChains[0];
2084 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2085 MVT::Other, &InputChains[0], InputChains.size());
2088 /// MorphNode - Handle morphing a node in place for the selector.
2089 SDNode *SelectionDAGISel::
2090 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2091 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
2092 // It is possible we're using MorphNodeTo to replace a node with no
2093 // normal results with one that has a normal result (or we could be
2094 // adding a chain) and the input could have glue and chains as well.
2095 // In this case we need to shift the operands down.
2096 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2097 // than the old isel though.
2098 int OldGlueResultNo = -1, OldChainResultNo = -1;
2100 unsigned NTMNumResults = Node->getNumValues();
2101 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2102 OldGlueResultNo = NTMNumResults-1;
2103 if (NTMNumResults != 1 &&
2104 Node->getValueType(NTMNumResults-2) == MVT::Other)
2105 OldChainResultNo = NTMNumResults-2;
2106 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2107 OldChainResultNo = NTMNumResults-1;
2109 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2110 // that this deletes operands of the old node that become dead.
2111 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
2113 // MorphNodeTo can operate in two ways: if an existing node with the
2114 // specified operands exists, it can just return it. Otherwise, it
2115 // updates the node in place to have the requested operands.
2117 // If we updated the node in place, reset the node ID. To the isel,
2118 // this should be just like a newly allocated machine node.
2122 unsigned ResNumResults = Res->getNumValues();
2123 // Move the glue if needed.
2124 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2125 (unsigned)OldGlueResultNo != ResNumResults-1)
2126 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2127 SDValue(Res, ResNumResults-1));
2129 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2132 // Move the chain reference if needed.
2133 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2134 (unsigned)OldChainResultNo != ResNumResults-1)
2135 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2136 SDValue(Res, ResNumResults-1));
2138 // Otherwise, no replacement happened because the node already exists. Replace
2139 // Uses of the old node with the new one.
2141 CurDAG->ReplaceAllUsesWith(Node, Res);
2146 /// CheckSame - Implements OP_CheckSame.
2147 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2148 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2150 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2151 // Accept if it is exactly the same as a previously recorded node.
2152 unsigned RecNo = MatcherTable[MatcherIndex++];
2153 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2154 return N == RecordedNodes[RecNo].first;
2157 /// CheckChildSame - Implements OP_CheckChildXSame.
2158 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2159 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2161 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2163 if (ChildNo >= N.getNumOperands())
2164 return false; // Match fails if out of range child #.
2165 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2169 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2170 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2171 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2172 const SelectionDAGISel &SDISel) {
2173 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2176 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2177 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2178 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2179 const SelectionDAGISel &SDISel, SDNode *N) {
2180 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2183 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2184 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2186 uint16_t Opc = MatcherTable[MatcherIndex++];
2187 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2188 return N->getOpcode() == Opc;
2191 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2192 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2193 SDValue N, const TargetLowering *TLI) {
2194 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2195 if (N.getValueType() == VT) return true;
2197 // Handle the case when VT is iPTR.
2198 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2201 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2202 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2203 SDValue N, const TargetLowering *TLI,
2205 if (ChildNo >= N.getNumOperands())
2206 return false; // Match fails if out of range child #.
2207 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2210 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2211 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2213 return cast<CondCodeSDNode>(N)->get() ==
2214 (ISD::CondCode)MatcherTable[MatcherIndex++];
2217 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2218 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2219 SDValue N, const TargetLowering *TLI) {
2220 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2221 if (cast<VTSDNode>(N)->getVT() == VT)
2224 // Handle the case when VT is iPTR.
2225 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2228 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2229 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2231 int64_t Val = MatcherTable[MatcherIndex++];
2233 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2235 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2236 return C != 0 && C->getSExtValue() == Val;
2239 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2240 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2241 SDValue N, const SelectionDAGISel &SDISel) {
2242 int64_t Val = MatcherTable[MatcherIndex++];
2244 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2246 if (N->getOpcode() != ISD::AND) return false;
2248 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2249 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2252 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2253 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2254 SDValue N, const SelectionDAGISel &SDISel) {
2255 int64_t Val = MatcherTable[MatcherIndex++];
2257 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2259 if (N->getOpcode() != ISD::OR) return false;
2261 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2262 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2265 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2266 /// scope, evaluate the current node. If the current predicate is known to
2267 /// fail, set Result=true and return anything. If the current predicate is
2268 /// known to pass, set Result=false and return the MatcherIndex to continue
2269 /// with. If the current predicate is unknown, set Result=false and return the
2270 /// MatcherIndex to continue with.
2271 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2272 unsigned Index, SDValue N,
2274 const SelectionDAGISel &SDISel,
2275 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2276 switch (Table[Index++]) {
2279 return Index-1; // Could not evaluate this predicate.
2280 case SelectionDAGISel::OPC_CheckSame:
2281 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2283 case SelectionDAGISel::OPC_CheckChild0Same:
2284 case SelectionDAGISel::OPC_CheckChild1Same:
2285 case SelectionDAGISel::OPC_CheckChild2Same:
2286 case SelectionDAGISel::OPC_CheckChild3Same:
2287 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2288 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2290 case SelectionDAGISel::OPC_CheckPatternPredicate:
2291 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2293 case SelectionDAGISel::OPC_CheckPredicate:
2294 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2296 case SelectionDAGISel::OPC_CheckOpcode:
2297 Result = !::CheckOpcode(Table, Index, N.getNode());
2299 case SelectionDAGISel::OPC_CheckType:
2300 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering());
2302 case SelectionDAGISel::OPC_CheckChild0Type:
2303 case SelectionDAGISel::OPC_CheckChild1Type:
2304 case SelectionDAGISel::OPC_CheckChild2Type:
2305 case SelectionDAGISel::OPC_CheckChild3Type:
2306 case SelectionDAGISel::OPC_CheckChild4Type:
2307 case SelectionDAGISel::OPC_CheckChild5Type:
2308 case SelectionDAGISel::OPC_CheckChild6Type:
2309 case SelectionDAGISel::OPC_CheckChild7Type:
2310 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(),
2311 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2313 case SelectionDAGISel::OPC_CheckCondCode:
2314 Result = !::CheckCondCode(Table, Index, N);
2316 case SelectionDAGISel::OPC_CheckValueType:
2317 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering());
2319 case SelectionDAGISel::OPC_CheckInteger:
2320 Result = !::CheckInteger(Table, Index, N);
2322 case SelectionDAGISel::OPC_CheckAndImm:
2323 Result = !::CheckAndImm(Table, Index, N, SDISel);
2325 case SelectionDAGISel::OPC_CheckOrImm:
2326 Result = !::CheckOrImm(Table, Index, N, SDISel);
2334 /// FailIndex - If this match fails, this is the index to continue with.
2337 /// NodeStack - The node stack when the scope was formed.
2338 SmallVector<SDValue, 4> NodeStack;
2340 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2341 unsigned NumRecordedNodes;
2343 /// NumMatchedMemRefs - The number of matched memref entries.
2344 unsigned NumMatchedMemRefs;
2346 /// InputChain/InputGlue - The current chain/glue
2347 SDValue InputChain, InputGlue;
2349 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2350 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2355 SDNode *SelectionDAGISel::
2356 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2357 unsigned TableSize) {
2358 // FIXME: Should these even be selected? Handle these cases in the caller?
2359 switch (NodeToMatch->getOpcode()) {
2362 case ISD::EntryToken: // These nodes remain the same.
2363 case ISD::BasicBlock:
2365 case ISD::RegisterMask:
2366 //case ISD::VALUETYPE:
2367 //case ISD::CONDCODE:
2368 case ISD::HANDLENODE:
2369 case ISD::MDNODE_SDNODE:
2370 case ISD::TargetConstant:
2371 case ISD::TargetConstantFP:
2372 case ISD::TargetConstantPool:
2373 case ISD::TargetFrameIndex:
2374 case ISD::TargetExternalSymbol:
2375 case ISD::TargetBlockAddress:
2376 case ISD::TargetJumpTable:
2377 case ISD::TargetGlobalTLSAddress:
2378 case ISD::TargetGlobalAddress:
2379 case ISD::TokenFactor:
2380 case ISD::CopyFromReg:
2381 case ISD::CopyToReg:
2383 case ISD::LIFETIME_START:
2384 case ISD::LIFETIME_END:
2385 NodeToMatch->setNodeId(-1); // Mark selected.
2387 case ISD::AssertSext:
2388 case ISD::AssertZext:
2389 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2390 NodeToMatch->getOperand(0));
2392 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2393 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2396 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2398 // Set up the node stack with NodeToMatch as the only node on the stack.
2399 SmallVector<SDValue, 8> NodeStack;
2400 SDValue N = SDValue(NodeToMatch, 0);
2401 NodeStack.push_back(N);
2403 // MatchScopes - Scopes used when matching, if a match failure happens, this
2404 // indicates where to continue checking.
2405 SmallVector<MatchScope, 8> MatchScopes;
2407 // RecordedNodes - This is the set of nodes that have been recorded by the
2408 // state machine. The second value is the parent of the node, or null if the
2409 // root is recorded.
2410 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2412 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2414 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2416 // These are the current input chain and glue for use when generating nodes.
2417 // Various Emit operations change these. For example, emitting a copytoreg
2418 // uses and updates these.
2419 SDValue InputChain, InputGlue;
2421 // ChainNodesMatched - If a pattern matches nodes that have input/output
2422 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2423 // which ones they are. The result is captured into this list so that we can
2424 // update the chain results when the pattern is complete.
2425 SmallVector<SDNode*, 3> ChainNodesMatched;
2426 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2428 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2429 NodeToMatch->dump(CurDAG);
2432 // Determine where to start the interpreter. Normally we start at opcode #0,
2433 // but if the state machine starts with an OPC_SwitchOpcode, then we
2434 // accelerate the first lookup (which is guaranteed to be hot) with the
2435 // OpcodeOffset table.
2436 unsigned MatcherIndex = 0;
2438 if (!OpcodeOffset.empty()) {
2439 // Already computed the OpcodeOffset table, just index into it.
2440 if (N.getOpcode() < OpcodeOffset.size())
2441 MatcherIndex = OpcodeOffset[N.getOpcode()];
2442 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2444 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2445 // Otherwise, the table isn't computed, but the state machine does start
2446 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2447 // is the first time we're selecting an instruction.
2450 // Get the size of this case.
2451 unsigned CaseSize = MatcherTable[Idx++];
2453 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2454 if (CaseSize == 0) break;
2456 // Get the opcode, add the index to the table.
2457 uint16_t Opc = MatcherTable[Idx++];
2458 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2459 if (Opc >= OpcodeOffset.size())
2460 OpcodeOffset.resize((Opc+1)*2);
2461 OpcodeOffset[Opc] = Idx;
2465 // Okay, do the lookup for the first opcode.
2466 if (N.getOpcode() < OpcodeOffset.size())
2467 MatcherIndex = OpcodeOffset[N.getOpcode()];
2471 assert(MatcherIndex < TableSize && "Invalid index");
2473 unsigned CurrentOpcodeIndex = MatcherIndex;
2475 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2478 // Okay, the semantics of this operation are that we should push a scope
2479 // then evaluate the first child. However, pushing a scope only to have
2480 // the first check fail (which then pops it) is inefficient. If we can
2481 // determine immediately that the first check (or first several) will
2482 // immediately fail, don't even bother pushing a scope for them.
2486 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2487 if (NumToSkip & 128)
2488 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2489 // Found the end of the scope with no match.
2490 if (NumToSkip == 0) {
2495 FailIndex = MatcherIndex+NumToSkip;
2497 unsigned MatcherIndexOfPredicate = MatcherIndex;
2498 (void)MatcherIndexOfPredicate; // silence warning.
2500 // If we can't evaluate this predicate without pushing a scope (e.g. if
2501 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2502 // push the scope and evaluate the full predicate chain.
2504 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2505 Result, *this, RecordedNodes);
2509 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2510 << "index " << MatcherIndexOfPredicate
2511 << ", continuing at " << FailIndex << "\n");
2512 ++NumDAGIselRetries;
2514 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2515 // move to the next case.
2516 MatcherIndex = FailIndex;
2519 // If the whole scope failed to match, bail.
2520 if (FailIndex == 0) break;
2522 // Push a MatchScope which indicates where to go if the first child fails
2524 MatchScope NewEntry;
2525 NewEntry.FailIndex = FailIndex;
2526 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2527 NewEntry.NumRecordedNodes = RecordedNodes.size();
2528 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2529 NewEntry.InputChain = InputChain;
2530 NewEntry.InputGlue = InputGlue;
2531 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2532 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2533 MatchScopes.push_back(NewEntry);
2536 case OPC_RecordNode: {
2537 // Remember this node, it may end up being an operand in the pattern.
2539 if (NodeStack.size() > 1)
2540 Parent = NodeStack[NodeStack.size()-2].getNode();
2541 RecordedNodes.push_back(std::make_pair(N, Parent));
2545 case OPC_RecordChild0: case OPC_RecordChild1:
2546 case OPC_RecordChild2: case OPC_RecordChild3:
2547 case OPC_RecordChild4: case OPC_RecordChild5:
2548 case OPC_RecordChild6: case OPC_RecordChild7: {
2549 unsigned ChildNo = Opcode-OPC_RecordChild0;
2550 if (ChildNo >= N.getNumOperands())
2551 break; // Match fails if out of range child #.
2553 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2557 case OPC_RecordMemRef:
2558 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2561 case OPC_CaptureGlueInput:
2562 // If the current node has an input glue, capture it in InputGlue.
2563 if (N->getNumOperands() != 0 &&
2564 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2565 InputGlue = N->getOperand(N->getNumOperands()-1);
2568 case OPC_MoveChild: {
2569 unsigned ChildNo = MatcherTable[MatcherIndex++];
2570 if (ChildNo >= N.getNumOperands())
2571 break; // Match fails if out of range child #.
2572 N = N.getOperand(ChildNo);
2573 NodeStack.push_back(N);
2577 case OPC_MoveParent:
2578 // Pop the current node off the NodeStack.
2579 NodeStack.pop_back();
2580 assert(!NodeStack.empty() && "Node stack imbalance!");
2581 N = NodeStack.back();
2585 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2588 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2589 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2590 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2591 Opcode-OPC_CheckChild0Same))
2595 case OPC_CheckPatternPredicate:
2596 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2598 case OPC_CheckPredicate:
2599 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2603 case OPC_CheckComplexPat: {
2604 unsigned CPNum = MatcherTable[MatcherIndex++];
2605 unsigned RecNo = MatcherTable[MatcherIndex++];
2606 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2607 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2608 RecordedNodes[RecNo].first, CPNum,
2613 case OPC_CheckOpcode:
2614 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2618 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2622 case OPC_SwitchOpcode: {
2623 unsigned CurNodeOpcode = N.getOpcode();
2624 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2627 // Get the size of this case.
2628 CaseSize = MatcherTable[MatcherIndex++];
2630 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2631 if (CaseSize == 0) break;
2633 uint16_t Opc = MatcherTable[MatcherIndex++];
2634 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2636 // If the opcode matches, then we will execute this case.
2637 if (CurNodeOpcode == Opc)
2640 // Otherwise, skip over this case.
2641 MatcherIndex += CaseSize;
2644 // If no cases matched, bail out.
2645 if (CaseSize == 0) break;
2647 // Otherwise, execute the case we found.
2648 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2649 << " to " << MatcherIndex << "\n");
2653 case OPC_SwitchType: {
2654 MVT CurNodeVT = N.getSimpleValueType();
2655 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2658 // Get the size of this case.
2659 CaseSize = MatcherTable[MatcherIndex++];
2661 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2662 if (CaseSize == 0) break;
2664 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2665 if (CaseVT == MVT::iPTR)
2666 CaseVT = getTargetLowering()->getPointerTy();
2668 // If the VT matches, then we will execute this case.
2669 if (CurNodeVT == CaseVT)
2672 // Otherwise, skip over this case.
2673 MatcherIndex += CaseSize;
2676 // If no cases matched, bail out.
2677 if (CaseSize == 0) break;
2679 // Otherwise, execute the case we found.
2680 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2681 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2684 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2685 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2686 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2687 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2688 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(),
2689 Opcode-OPC_CheckChild0Type))
2692 case OPC_CheckCondCode:
2693 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2695 case OPC_CheckValueType:
2696 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2699 case OPC_CheckInteger:
2700 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2702 case OPC_CheckAndImm:
2703 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2705 case OPC_CheckOrImm:
2706 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2709 case OPC_CheckFoldableChainNode: {
2710 assert(NodeStack.size() != 1 && "No parent node");
2711 // Verify that all intermediate nodes between the root and this one have
2713 bool HasMultipleUses = false;
2714 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2715 if (!NodeStack[i].hasOneUse()) {
2716 HasMultipleUses = true;
2719 if (HasMultipleUses) break;
2721 // Check to see that the target thinks this is profitable to fold and that
2722 // we can fold it without inducing cycles in the graph.
2723 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2725 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2726 NodeToMatch, OptLevel,
2727 true/*We validate our own chains*/))
2732 case OPC_EmitInteger: {
2733 MVT::SimpleValueType VT =
2734 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2735 int64_t Val = MatcherTable[MatcherIndex++];
2737 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2738 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2739 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2742 case OPC_EmitRegister: {
2743 MVT::SimpleValueType VT =
2744 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2745 unsigned RegNo = MatcherTable[MatcherIndex++];
2746 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2747 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2750 case OPC_EmitRegister2: {
2751 // For targets w/ more than 256 register names, the register enum
2752 // values are stored in two bytes in the matcher table (just like
2754 MVT::SimpleValueType VT =
2755 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2756 unsigned RegNo = MatcherTable[MatcherIndex++];
2757 RegNo |= MatcherTable[MatcherIndex++] << 8;
2758 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2759 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2763 case OPC_EmitConvertToTarget: {
2764 // Convert from IMM/FPIMM to target version.
2765 unsigned RecNo = MatcherTable[MatcherIndex++];
2766 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2767 SDValue Imm = RecordedNodes[RecNo].first;
2769 if (Imm->getOpcode() == ISD::Constant) {
2770 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2771 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2772 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2773 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2774 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2777 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2781 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2782 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2783 // These are space-optimized forms of OPC_EmitMergeInputChains.
2784 assert(InputChain.getNode() == 0 &&
2785 "EmitMergeInputChains should be the first chain producing node");
2786 assert(ChainNodesMatched.empty() &&
2787 "Should only have one EmitMergeInputChains per match");
2789 // Read all of the chained nodes.
2790 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2791 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2792 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2794 // FIXME: What if other value results of the node have uses not matched
2796 if (ChainNodesMatched.back() != NodeToMatch &&
2797 !RecordedNodes[RecNo].first.hasOneUse()) {
2798 ChainNodesMatched.clear();
2802 // Merge the input chains if they are not intra-pattern references.
2803 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2805 if (InputChain.getNode() == 0)
2806 break; // Failed to merge.
2810 case OPC_EmitMergeInputChains: {
2811 assert(InputChain.getNode() == 0 &&
2812 "EmitMergeInputChains should be the first chain producing node");
2813 // This node gets a list of nodes we matched in the input that have
2814 // chains. We want to token factor all of the input chains to these nodes
2815 // together. However, if any of the input chains is actually one of the
2816 // nodes matched in this pattern, then we have an intra-match reference.
2817 // Ignore these because the newly token factored chain should not refer to
2819 unsigned NumChains = MatcherTable[MatcherIndex++];
2820 assert(NumChains != 0 && "Can't TF zero chains");
2822 assert(ChainNodesMatched.empty() &&
2823 "Should only have one EmitMergeInputChains per match");
2825 // Read all of the chained nodes.
2826 for (unsigned i = 0; i != NumChains; ++i) {
2827 unsigned RecNo = MatcherTable[MatcherIndex++];
2828 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2829 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2831 // FIXME: What if other value results of the node have uses not matched
2833 if (ChainNodesMatched.back() != NodeToMatch &&
2834 !RecordedNodes[RecNo].first.hasOneUse()) {
2835 ChainNodesMatched.clear();
2840 // If the inner loop broke out, the match fails.
2841 if (ChainNodesMatched.empty())
2844 // Merge the input chains if they are not intra-pattern references.
2845 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2847 if (InputChain.getNode() == 0)
2848 break; // Failed to merge.
2853 case OPC_EmitCopyToReg: {
2854 unsigned RecNo = MatcherTable[MatcherIndex++];
2855 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
2856 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2858 if (InputChain.getNode() == 0)
2859 InputChain = CurDAG->getEntryNode();
2861 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2862 DestPhysReg, RecordedNodes[RecNo].first,
2865 InputGlue = InputChain.getValue(1);
2869 case OPC_EmitNodeXForm: {
2870 unsigned XFormNo = MatcherTable[MatcherIndex++];
2871 unsigned RecNo = MatcherTable[MatcherIndex++];
2872 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
2873 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2874 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2879 case OPC_MorphNodeTo: {
2880 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2881 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2882 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2883 // Get the result VT list.
2884 unsigned NumVTs = MatcherTable[MatcherIndex++];
2885 SmallVector<EVT, 4> VTs;
2886 for (unsigned i = 0; i != NumVTs; ++i) {
2887 MVT::SimpleValueType VT =
2888 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2889 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy;
2893 if (EmitNodeInfo & OPFL_Chain)
2894 VTs.push_back(MVT::Other);
2895 if (EmitNodeInfo & OPFL_GlueOutput)
2896 VTs.push_back(MVT::Glue);
2898 // This is hot code, so optimize the two most common cases of 1 and 2
2901 if (VTs.size() == 1)
2902 VTList = CurDAG->getVTList(VTs[0]);
2903 else if (VTs.size() == 2)
2904 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2906 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2908 // Get the operand list.
2909 unsigned NumOps = MatcherTable[MatcherIndex++];
2910 SmallVector<SDValue, 8> Ops;
2911 for (unsigned i = 0; i != NumOps; ++i) {
2912 unsigned RecNo = MatcherTable[MatcherIndex++];
2914 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2916 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2917 Ops.push_back(RecordedNodes[RecNo].first);
2920 // If there are variadic operands to add, handle them now.
2921 if (EmitNodeInfo & OPFL_VariadicInfo) {
2922 // Determine the start index to copy from.
2923 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2924 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2925 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2926 "Invalid variadic node");
2927 // Copy all of the variadic operands, not including a potential glue
2929 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2931 SDValue V = NodeToMatch->getOperand(i);
2932 if (V.getValueType() == MVT::Glue) break;
2937 // If this has chain/glue inputs, add them.
2938 if (EmitNodeInfo & OPFL_Chain)
2939 Ops.push_back(InputChain);
2940 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2941 Ops.push_back(InputGlue);
2945 if (Opcode != OPC_MorphNodeTo) {
2946 // If this is a normal EmitNode command, just create the new node and
2947 // add the results to the RecordedNodes list.
2948 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
2951 // Add all the non-glue/non-chain results to the RecordedNodes list.
2952 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2953 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2954 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2958 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2959 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2962 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2963 // We will visit the equivalent node later.
2964 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2968 // If the node had chain/glue results, update our notion of the current
2970 if (EmitNodeInfo & OPFL_GlueOutput) {
2971 InputGlue = SDValue(Res, VTs.size()-1);
2972 if (EmitNodeInfo & OPFL_Chain)
2973 InputChain = SDValue(Res, VTs.size()-2);
2974 } else if (EmitNodeInfo & OPFL_Chain)
2975 InputChain = SDValue(Res, VTs.size()-1);
2977 // If the OPFL_MemRefs glue is set on this node, slap all of the
2978 // accumulated memrefs onto it.
2980 // FIXME: This is vastly incorrect for patterns with multiple outputs
2981 // instructions that access memory and for ComplexPatterns that match
2983 if (EmitNodeInfo & OPFL_MemRefs) {
2984 // Only attach load or store memory operands if the generated
2985 // instruction may load or store.
2986 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2987 bool mayLoad = MCID.mayLoad();
2988 bool mayStore = MCID.mayStore();
2990 unsigned NumMemRefs = 0;
2991 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2992 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2993 if ((*I)->isLoad()) {
2996 } else if ((*I)->isStore()) {
3004 MachineSDNode::mmo_iterator MemRefs =
3005 MF->allocateMemRefsArray(NumMemRefs);
3007 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3008 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3009 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3010 if ((*I)->isLoad()) {
3013 } else if ((*I)->isStore()) {
3021 cast<MachineSDNode>(Res)
3022 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3026 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3027 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3029 // If this was a MorphNodeTo then we're completely done!
3030 if (Opcode == OPC_MorphNodeTo) {
3031 // Update chain and glue uses.
3032 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3033 InputGlue, GlueResultNodesMatched, true);
3040 case OPC_MarkGlueResults: {
3041 unsigned NumNodes = MatcherTable[MatcherIndex++];
3043 // Read and remember all the glue-result nodes.
3044 for (unsigned i = 0; i != NumNodes; ++i) {
3045 unsigned RecNo = MatcherTable[MatcherIndex++];
3047 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3049 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3050 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3055 case OPC_CompleteMatch: {
3056 // The match has been completed, and any new nodes (if any) have been
3057 // created. Patch up references to the matched dag to use the newly
3059 unsigned NumResults = MatcherTable[MatcherIndex++];
3061 for (unsigned i = 0; i != NumResults; ++i) {
3062 unsigned ResSlot = MatcherTable[MatcherIndex++];
3064 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3066 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3067 SDValue Res = RecordedNodes[ResSlot].first;
3069 assert(i < NodeToMatch->getNumValues() &&
3070 NodeToMatch->getValueType(i) != MVT::Other &&
3071 NodeToMatch->getValueType(i) != MVT::Glue &&
3072 "Invalid number of results to complete!");
3073 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3074 NodeToMatch->getValueType(i) == MVT::iPTR ||
3075 Res.getValueType() == MVT::iPTR ||
3076 NodeToMatch->getValueType(i).getSizeInBits() ==
3077 Res.getValueType().getSizeInBits()) &&
3078 "invalid replacement");
3079 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3082 // If the root node defines glue, add it to the glue nodes to update list.
3083 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3084 GlueResultNodesMatched.push_back(NodeToMatch);
3086 // Update chain and glue uses.
3087 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3088 InputGlue, GlueResultNodesMatched, false);
3090 assert(NodeToMatch->use_empty() &&
3091 "Didn't replace all uses of the node?");
3093 // FIXME: We just return here, which interacts correctly with SelectRoot
3094 // above. We should fix this to not return an SDNode* anymore.
3099 // If the code reached this point, then the match failed. See if there is
3100 // another child to try in the current 'Scope', otherwise pop it until we
3101 // find a case to check.
3102 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3103 ++NumDAGIselRetries;
3105 if (MatchScopes.empty()) {
3106 CannotYetSelect(NodeToMatch);
3110 // Restore the interpreter state back to the point where the scope was
3112 MatchScope &LastScope = MatchScopes.back();
3113 RecordedNodes.resize(LastScope.NumRecordedNodes);
3115 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3116 N = NodeStack.back();
3118 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3119 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3120 MatcherIndex = LastScope.FailIndex;
3122 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3124 InputChain = LastScope.InputChain;
3125 InputGlue = LastScope.InputGlue;
3126 if (!LastScope.HasChainNodesMatched)
3127 ChainNodesMatched.clear();
3128 if (!LastScope.HasGlueResultNodesMatched)
3129 GlueResultNodesMatched.clear();
3131 // Check to see what the offset is at the new MatcherIndex. If it is zero
3132 // we have reached the end of this scope, otherwise we have another child
3133 // in the current scope to try.
3134 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3135 if (NumToSkip & 128)
3136 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3138 // If we have another child in this scope to match, update FailIndex and
3140 if (NumToSkip != 0) {
3141 LastScope.FailIndex = MatcherIndex+NumToSkip;
3145 // End of this scope, pop it and try the next child in the containing
3147 MatchScopes.pop_back();
3154 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3156 raw_string_ostream Msg(msg);
3157 Msg << "Cannot select: ";
3159 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3160 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3161 N->getOpcode() != ISD::INTRINSIC_VOID) {
3162 N->printrFull(Msg, CurDAG);
3163 Msg << "\nIn function: " << MF->getName();
3165 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3167 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3168 if (iid < Intrinsic::num_intrinsics)
3169 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3170 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3171 Msg << "target intrinsic %" << TII->getName(iid);
3173 Msg << "unknown intrinsic #" << iid;
3175 report_fatal_error(Msg.str());
3178 char SelectionDAGISel::ID = 0;