1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/ADT/Statistic.h"
56 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
57 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
58 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
59 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
62 STATISTIC(NumBBWithOutOfOrderLineInfo,
63 "Number of blocks with out of order line number info");
64 STATISTIC(NumMBBWithOutOfOrderLineInfo,
65 "Number of machine blocks with out of order line number info");
69 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
70 cl::desc("Enable verbose messages in the \"fast\" "
71 "instruction selector"));
73 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
74 cl::desc("Enable abort calls when \"fast\" instruction fails"));
78 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the first "
82 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before legalize types"));
85 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
86 cl::desc("Pop up a window to show dags before legalize"));
88 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
89 cl::desc("Pop up a window to show dags before the second "
92 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
93 cl::desc("Pop up a window to show dags before the post legalize types"
94 " dag combine pass"));
96 ViewISelDAGs("view-isel-dags", cl::Hidden,
97 cl::desc("Pop up a window to show isel dags as they are selected"));
99 ViewSchedDAGs("view-sched-dags", cl::Hidden,
100 cl::desc("Pop up a window to show sched dags as they are processed"));
102 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
103 cl::desc("Pop up a window to show SUnit dags after they are processed"));
105 static const bool ViewDAGCombine1 = false,
106 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
107 ViewDAGCombine2 = false,
108 ViewDAGCombineLT = false,
109 ViewISelDAGs = false, ViewSchedDAGs = false,
110 ViewSUnitDAGs = false;
113 //===---------------------------------------------------------------------===//
115 /// RegisterScheduler class - Track the registration of instruction schedulers.
117 //===---------------------------------------------------------------------===//
118 MachinePassRegistry RegisterScheduler::Registry;
120 //===---------------------------------------------------------------------===//
122 /// ISHeuristic command line option for instruction schedulers.
124 //===---------------------------------------------------------------------===//
125 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
126 RegisterPassParser<RegisterScheduler> >
127 ISHeuristic("pre-RA-sched",
128 cl::init(&createDefaultScheduler),
129 cl::desc("Instruction schedulers available (before register"
132 static RegisterScheduler
133 defaultListDAGScheduler("default", "Best scheduler for the target",
134 createDefaultScheduler);
137 //===--------------------------------------------------------------------===//
138 /// createDefaultScheduler - This creates an instruction scheduler appropriate
140 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
141 CodeGenOpt::Level OptLevel) {
142 const TargetLowering &TLI = IS->getTargetLowering();
144 if (OptLevel == CodeGenOpt::None)
145 return createSourceListDAGScheduler(IS, OptLevel);
146 if (TLI.getSchedulingPreference() == Sched::Latency)
147 return createTDListDAGScheduler(IS, OptLevel);
148 if (TLI.getSchedulingPreference() == Sched::RegPressure)
149 return createBURRListDAGScheduler(IS, OptLevel);
150 if (TLI.getSchedulingPreference() == Sched::Hybrid)
151 return createHybridListDAGScheduler(IS, OptLevel);
152 assert(TLI.getSchedulingPreference() == Sched::ILP &&
153 "Unknown sched type!");
154 return createILPListDAGScheduler(IS, OptLevel);
158 // EmitInstrWithCustomInserter - This method should be implemented by targets
159 // that mark instructions with the 'usesCustomInserter' flag. These
160 // instructions are special in various ways, which require special support to
161 // insert. The specified MachineInstr is created but not inserted into any
162 // basic blocks, and this method is called to expand it into a sequence of
163 // instructions, potentially also creating new basic blocks and control flow.
164 // When new basic blocks are inserted and the edges from MBB to its successors
165 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
168 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
169 MachineBasicBlock *MBB) const {
171 dbgs() << "If a target marks an instruction with "
172 "'usesCustomInserter', it must implement "
173 "TargetLowering::EmitInstrWithCustomInserter!";
179 //===----------------------------------------------------------------------===//
180 // SelectionDAGISel code
181 //===----------------------------------------------------------------------===//
183 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
184 CodeGenOpt::Level OL) :
185 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
186 FuncInfo(new FunctionLoweringInfo(TLI)),
187 CurDAG(new SelectionDAG(tm)),
188 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
192 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
193 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
196 SelectionDAGISel::~SelectionDAGISel() {
202 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
203 AU.addRequired<AliasAnalysis>();
204 AU.addPreserved<AliasAnalysis>();
205 AU.addRequired<GCModuleInfo>();
206 AU.addPreserved<GCModuleInfo>();
207 MachineFunctionPass::getAnalysisUsage(AU);
210 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
211 /// other function that gcc recognizes as "returning twice". This is used to
212 /// limit code-gen optimizations on the machine function.
214 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
215 static bool FunctionCallsSetJmp(const Function *F) {
216 const Module *M = F->getParent();
217 static const char *ReturnsTwiceFns[] = {
227 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
229 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
230 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
231 if (!Callee->use_empty())
232 for (Value::const_use_iterator
233 I = Callee->use_begin(), E = Callee->use_end();
235 if (const CallInst *CI = dyn_cast<CallInst>(*I))
236 if (CI->getParent()->getParent() == F)
241 #undef NUM_RETURNS_TWICE_FNS
244 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
245 /// may trap on it. In this case we have to split the edge so that the path
246 /// through the predecessor block that doesn't go to the phi block doesn't
247 /// execute the possibly trapping instruction.
249 /// This is required for correctness, so it must be done at -O0.
251 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
252 // Loop for blocks with phi nodes.
253 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
254 PHINode *PN = dyn_cast<PHINode>(BB->begin());
255 if (PN == 0) continue;
258 // For each block with a PHI node, check to see if any of the input values
259 // are potentially trapping constant expressions. Constant expressions are
260 // the only potentially trapping value that can occur as the argument to a
262 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
263 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
264 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
265 if (CE == 0 || !CE->canTrap()) continue;
267 // The only case we have to worry about is when the edge is critical.
268 // Since this block has a PHI Node, we assume it has multiple input
269 // edges: check to see if the pred has multiple successors.
270 BasicBlock *Pred = PN->getIncomingBlock(i);
271 if (Pred->getTerminator()->getNumSuccessors() == 1)
274 // Okay, we have to split this edge.
275 SplitCriticalEdge(Pred->getTerminator(),
276 GetSuccessorNumber(Pred, BB), SDISel, true);
282 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
283 // Do some sanity-checking on the command-line options.
284 assert((!EnableFastISelVerbose || EnableFastISel) &&
285 "-fast-isel-verbose requires -fast-isel");
286 assert((!EnableFastISelAbort || EnableFastISel) &&
287 "-fast-isel-abort requires -fast-isel");
289 const Function &Fn = *mf.getFunction();
290 const TargetInstrInfo &TII = *TM.getInstrInfo();
291 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
294 RegInfo = &MF->getRegInfo();
295 AA = &getAnalysis<AliasAnalysis>();
296 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
298 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
300 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
303 FuncInfo->set(Fn, *MF);
306 SelectAllBasicBlocks(Fn);
308 // If the first basic block in the function has live ins that need to be
309 // copied into vregs, emit the copies into the top of the block before
310 // emitting the code for the block.
311 MachineBasicBlock *EntryMBB = MF->begin();
312 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
314 DenseMap<unsigned, unsigned> LiveInMap;
315 if (!FuncInfo->ArgDbgValues.empty())
316 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
317 E = RegInfo->livein_end(); LI != E; ++LI)
319 LiveInMap.insert(std::make_pair(LI->first, LI->second));
321 // Insert DBG_VALUE instructions for function arguments to the entry block.
322 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
323 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
324 unsigned Reg = MI->getOperand(0).getReg();
325 if (TargetRegisterInfo::isPhysicalRegister(Reg))
326 EntryMBB->insert(EntryMBB->begin(), MI);
328 MachineInstr *Def = RegInfo->getVRegDef(Reg);
329 MachineBasicBlock::iterator InsertPos = Def;
330 // FIXME: VR def may not be in entry block.
331 Def->getParent()->insert(llvm::next(InsertPos), MI);
334 // If Reg is live-in then update debug info to track its copy in a vreg.
335 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
336 if (LDI != LiveInMap.end()) {
337 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
338 MachineBasicBlock::iterator InsertPos = Def;
339 const MDNode *Variable =
340 MI->getOperand(MI->getNumOperands()-1).getMetadata();
341 unsigned Offset = MI->getOperand(1).getImm();
342 // Def is never a terminator here, so it is ok to increment InsertPos.
343 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
344 TII.get(TargetOpcode::DBG_VALUE))
345 .addReg(LDI->second, RegState::Debug)
346 .addImm(Offset).addMetadata(Variable);
348 // If this vreg is directly copied into an exported register then
349 // that COPY instructions also need DBG_VALUE, if it is the only
350 // user of LDI->second.
351 MachineInstr *CopyUseMI = NULL;
352 for (MachineRegisterInfo::use_iterator
353 UI = RegInfo->use_begin(LDI->second);
354 MachineInstr *UseMI = UI.skipInstruction();) {
355 if (UseMI->isDebugValue()) continue;
356 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
357 CopyUseMI = UseMI; continue;
359 // Otherwise this is another use or second copy use.
360 CopyUseMI = NULL; break;
363 MachineInstr *NewMI =
364 BuildMI(*MF, CopyUseMI->getDebugLoc(),
365 TII.get(TargetOpcode::DBG_VALUE))
366 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
367 .addImm(Offset).addMetadata(Variable);
368 EntryMBB->insertAfter(CopyUseMI, NewMI);
373 // Determine if there are any calls in this machine function.
374 MachineFrameInfo *MFI = MF->getFrameInfo();
375 if (!MFI->hasCalls()) {
376 for (MachineFunction::const_iterator
377 I = MF->begin(), E = MF->end(); I != E; ++I) {
378 const MachineBasicBlock *MBB = I;
379 for (MachineBasicBlock::const_iterator
380 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
381 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
383 if ((TID.isCall() && !TID.isReturn()) ||
384 II->isStackAligningInlineAsm()) {
385 MFI->setHasCalls(true);
393 // Determine if there is a call to setjmp in the machine function.
394 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
396 // Replace forward-declared registers with the registers containing
397 // the desired value.
398 MachineRegisterInfo &MRI = MF->getRegInfo();
399 for (DenseMap<unsigned, unsigned>::iterator
400 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
402 unsigned From = I->first;
403 unsigned To = I->second;
404 // If To is also scheduled to be replaced, find what its ultimate
407 DenseMap<unsigned, unsigned>::iterator J =
408 FuncInfo->RegFixups.find(To);
413 MRI.replaceRegWith(From, To);
416 // Release function-specific state. SDB and CurDAG are already cleared
424 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
425 BasicBlock::const_iterator End,
427 // Lower all of the non-terminator instructions. If a call is emitted
428 // as a tail call, cease emitting nodes for this block. Terminators
429 // are handled below.
430 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
433 // Make sure the root of the DAG is up-to-date.
434 CurDAG->setRoot(SDB->getControlRoot());
435 HadTailCall = SDB->HasTailCall;
438 // Final step, emit the lowered DAG as machine code.
443 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
444 SmallPtrSet<SDNode*, 128> VisitedNodes;
445 SmallVector<SDNode*, 128> Worklist;
447 Worklist.push_back(CurDAG->getRoot().getNode());
454 SDNode *N = Worklist.pop_back_val();
456 // If we've already seen this node, ignore it.
457 if (!VisitedNodes.insert(N))
460 // Otherwise, add all chain operands to the worklist.
461 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
462 if (N->getOperand(i).getValueType() == MVT::Other)
463 Worklist.push_back(N->getOperand(i).getNode());
465 // If this is a CopyToReg with a vreg dest, process it.
466 if (N->getOpcode() != ISD::CopyToReg)
469 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
470 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
473 // Ignore non-scalar or non-integer values.
474 SDValue Src = N->getOperand(2);
475 EVT SrcVT = Src.getValueType();
476 if (!SrcVT.isInteger() || SrcVT.isVector())
479 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
480 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
481 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
483 // Only install this information if it tells us something.
484 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
485 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
486 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
487 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
488 FunctionLoweringInfo::LiveOutInfo &LOI =
489 FuncInfo->LiveOutRegInfo[DestReg];
490 LOI.NumSignBits = NumSignBits;
491 LOI.KnownOne = KnownOne;
492 LOI.KnownZero = KnownZero;
494 } while (!Worklist.empty());
497 void SelectionDAGISel::CodeGenAndEmitDAG() {
498 std::string GroupName;
499 if (TimePassesIsEnabled)
500 GroupName = "Instruction Selection and Scheduling";
501 std::string BlockName;
502 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
503 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
505 BlockName = MF->getFunction()->getNameStr() + ":" +
506 FuncInfo->MBB->getBasicBlock()->getNameStr();
508 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
510 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
512 // Run the DAG combiner in pre-legalize mode.
514 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
515 CurDAG->Combine(Unrestricted, *AA, OptLevel);
518 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
520 // Second step, hack on the DAG until it only uses operations and types that
521 // the target supports.
522 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
527 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
528 Changed = CurDAG->LegalizeTypes();
531 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
534 if (ViewDAGCombineLT)
535 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
537 // Run the DAG combiner in post-type-legalize mode.
539 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
540 TimePassesIsEnabled);
541 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
544 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
549 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
550 Changed = CurDAG->LegalizeVectors();
555 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
556 CurDAG->LegalizeTypes();
559 if (ViewDAGCombineLT)
560 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
562 // Run the DAG combiner in post-type-legalize mode.
564 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
565 TimePassesIsEnabled);
566 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
569 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
573 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
576 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
577 CurDAG->Legalize(OptLevel);
580 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
582 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
584 // Run the DAG combiner in post-legalize mode.
586 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
587 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
590 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
592 if (OptLevel != CodeGenOpt::None)
593 ComputeLiveOutVRegInfo();
595 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
597 // Third, instruction select all of the operations to machine code, adding the
598 // code to the MachineBasicBlock.
600 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
601 DoInstructionSelection();
604 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
606 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
608 // Schedule machine code.
609 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
611 NamedRegionTimer T("Instruction Scheduling", GroupName,
612 TimePassesIsEnabled);
613 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
616 if (ViewSUnitDAGs) Scheduler->viewGraph();
618 // Emit machine code to BB. This can change 'BB' to the last block being
620 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
622 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
624 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
625 FuncInfo->InsertPt = Scheduler->InsertPos;
628 // If the block was split, make sure we update any references that are used to
629 // update PHI nodes later on.
630 if (FirstMBB != LastMBB)
631 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
633 // Free the scheduler state.
635 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
636 TimePassesIsEnabled);
640 // Free the SelectionDAG state, now that we're finished with it.
644 void SelectionDAGISel::DoInstructionSelection() {
645 DEBUG(errs() << "===== Instruction selection begins:\n");
649 // Select target instructions for the DAG.
651 // Number all nodes with a topological order and set DAGSize.
652 DAGSize = CurDAG->AssignTopologicalOrder();
654 // Create a dummy node (which is not added to allnodes), that adds
655 // a reference to the root node, preventing it from being deleted,
656 // and tracking any changes of the root.
657 HandleSDNode Dummy(CurDAG->getRoot());
658 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
661 // The AllNodes list is now topological-sorted. Visit the
662 // nodes by starting at the end of the list (the root of the
663 // graph) and preceding back toward the beginning (the entry
665 while (ISelPosition != CurDAG->allnodes_begin()) {
666 SDNode *Node = --ISelPosition;
667 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
668 // but there are currently some corner cases that it misses. Also, this
669 // makes it theoretically possible to disable the DAGCombiner.
670 if (Node->use_empty())
673 SDNode *ResNode = Select(Node);
675 // FIXME: This is pretty gross. 'Select' should be changed to not return
676 // anything at all and this code should be nuked with a tactical strike.
678 // If node should not be replaced, continue with the next one.
679 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
683 ReplaceUses(Node, ResNode);
685 // If after the replacement this node is not used any more,
686 // remove this dead node.
687 if (Node->use_empty()) { // Don't delete EntryToken, etc.
688 ISelUpdater ISU(ISelPosition);
689 CurDAG->RemoveDeadNode(Node, &ISU);
693 CurDAG->setRoot(Dummy.getValue());
696 DEBUG(errs() << "===== Instruction selection ends:\n");
698 PostprocessISelDAG();
701 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
702 /// do other setup for EH landing-pad blocks.
703 void SelectionDAGISel::PrepareEHLandingPad() {
704 // Add a label to mark the beginning of the landing pad. Deletion of the
705 // landing pad can thus be detected via the MachineModuleInfo.
706 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
708 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
709 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
712 // Mark exception register as live in.
713 unsigned Reg = TLI.getExceptionAddressRegister();
714 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
716 // Mark exception selector register as live in.
717 Reg = TLI.getExceptionSelectorRegister();
718 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
720 // FIXME: Hack around an exception handling flaw (PR1508): the personality
721 // function and list of typeids logically belong to the invoke (or, if you
722 // like, the basic block containing the invoke), and need to be associated
723 // with it in the dwarf exception handling tables. Currently however the
724 // information is provided by an intrinsic (eh.selector) that can be moved
725 // to unexpected places by the optimizers: if the unwind edge is critical,
726 // then breaking it can result in the intrinsics being in the successor of
727 // the landing pad, not the landing pad itself. This results
728 // in exceptions not being caught because no typeids are associated with
729 // the invoke. This may not be the only way things can go wrong, but it
730 // is the only way we try to work around for the moment.
731 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
732 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
734 if (Br && Br->isUnconditional()) { // Critical edge?
735 BasicBlock::const_iterator I, E;
736 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
737 if (isa<EHSelectorInst>(I))
741 // No catch info found - try to extract some from the successor.
742 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
749 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
751 // Don't try to fold volatile loads. Target has to deal with alignment
753 if (LI->isVolatile()) return false;
755 // Figure out which vreg this is going into.
756 unsigned LoadReg = FastIS->getRegForValue(LI);
757 assert(LoadReg && "Load isn't already assigned a vreg? ");
759 // Check to see what the uses of this vreg are. If it has no uses, or more
760 // than one use (at the machine instr level) then we can't fold it.
761 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
762 if (RI == RegInfo->reg_end())
765 // See if there is exactly one use of the vreg. If there are multiple uses,
766 // then the instruction got lowered to multiple machine instructions or the
767 // use of the loaded value ended up being multiple operands of the result, in
768 // either case, we can't fold this.
769 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
770 if (PostRI != RegInfo->reg_end())
773 assert(RI.getOperand().isUse() &&
774 "The only use of the vreg must be a use, we haven't emitted the def!");
776 // Ask the target to try folding the load.
777 return FastIS->TryToFoldLoad(&*RI, RI.getOperandNo(), LI);
781 /// CheckLineNumbers - Check if basic block instructions follow source order
783 static void CheckLineNumbers(const BasicBlock *BB) {
786 for (BasicBlock::const_iterator BI = BB->begin(),
787 BE = BB->end(); BI != BE; ++BI) {
788 const DebugLoc DL = BI->getDebugLoc();
789 if (DL.isUnknown()) continue;
790 unsigned L = DL.getLine();
791 unsigned C = DL.getCol();
792 if (L < Line || (L == Line && C < Col)) {
793 ++NumBBWithOutOfOrderLineInfo;
801 /// CheckLineNumbers - Check if machine basic block instructions follow source
803 static void CheckLineNumbers(const MachineBasicBlock *MBB) {
806 for (MachineBasicBlock::const_iterator MBI = MBB->begin(),
807 MBE = MBB->end(); MBI != MBE; ++MBI) {
808 const DebugLoc DL = MBI->getDebugLoc();
809 if (DL.isUnknown()) continue;
810 unsigned L = DL.getLine();
811 unsigned C = DL.getCol();
812 if (L < Line || (L == Line && C < Col)) {
813 ++NumMBBWithOutOfOrderLineInfo;
822 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
823 // Initialize the Fast-ISel state, if needed.
824 FastISel *FastIS = 0;
826 FastIS = TLI.createFastISel(*FuncInfo);
828 // Iterate over all basic blocks in the function.
829 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
830 const BasicBlock *LLVMBB = &*I;
832 CheckLineNumbers(LLVMBB);
834 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
835 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
837 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
838 BasicBlock::const_iterator const End = LLVMBB->end();
839 BasicBlock::const_iterator BI = End;
841 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
843 // Setup an EH landing-pad block.
844 if (FuncInfo->MBB->isLandingPad())
845 PrepareEHLandingPad();
847 // Lower any arguments needed in this block if this is the entry block.
848 if (LLVMBB == &Fn.getEntryBlock())
849 LowerArguments(LLVMBB);
851 // Before doing SelectionDAG ISel, see if FastISel has been requested.
853 FastIS->startNewBlock();
855 // Emit code for any incoming arguments. This must happen before
856 // beginning FastISel on the entry block.
857 if (LLVMBB == &Fn.getEntryBlock()) {
858 CurDAG->setRoot(SDB->getControlRoot());
862 // If we inserted any instructions at the beginning, make a note of
863 // where they are, so we can be sure to emit subsequent instructions
865 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
866 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
868 FastIS->setLastLocalValue(0);
871 // Do FastISel on as many instructions as possible.
872 for (; BI != Begin; --BI) {
873 const Instruction *Inst = llvm::prior(BI);
875 // If we no longer require this instruction, skip it.
876 if (!Inst->mayWriteToMemory() &&
877 !isa<TerminatorInst>(Inst) &&
878 !isa<DbgInfoIntrinsic>(Inst) &&
879 !FuncInfo->isExportedInst(Inst))
882 // Bottom-up: reset the insert pos at the top, after any local-value
884 FastIS->recomputeInsertPt();
886 // Try to select the instruction with FastISel.
887 if (FastIS->SelectInstruction(Inst)) {
888 // If fast isel succeeded, check to see if there is a single-use
889 // non-volatile load right before the selected instruction, and see if
890 // the load is used by the instruction. If so, try to fold it.
891 const Instruction *BeforeInst = 0;
893 BeforeInst = llvm::prior(llvm::prior(BI));
894 if (BeforeInst && isa<LoadInst>(BeforeInst) &&
895 BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst &&
896 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), FastIS)) {
897 // If we succeeded, don't re-select the load.
903 // Then handle certain instructions as single-LLVM-Instruction blocks.
904 if (isa<CallInst>(Inst)) {
905 ++NumFastIselFailures;
906 if (EnableFastISelVerbose || EnableFastISelAbort) {
907 dbgs() << "FastISel missed call: ";
911 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
912 unsigned &R = FuncInfo->ValueMap[Inst];
914 R = FuncInfo->CreateRegs(Inst->getType());
917 bool HadTailCall = false;
918 SelectBasicBlock(Inst, BI, HadTailCall);
920 // If the call was emitted as a tail call, we're done with the block.
929 // Otherwise, give up on FastISel for the rest of the block.
930 // For now, be a little lenient about non-branch terminators.
931 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
932 ++NumFastIselFailures;
933 if (EnableFastISelVerbose || EnableFastISelAbort) {
934 dbgs() << "FastISel miss: ";
937 if (EnableFastISelAbort)
938 // The "fast" selector couldn't handle something and bailed.
939 // For the purpose of debugging, just abort.
940 llvm_unreachable("FastISel didn't select the entire block");
945 FastIS->recomputeInsertPt();
953 // Run SelectionDAG instruction selection on the remainder of the block
954 // not handled by FastISel. If FastISel is not run, this is the entire
957 SelectBasicBlock(Begin, BI, HadTailCall);
960 FuncInfo->PHINodesToUpdate.clear();
965 for (MachineFunction::const_iterator MBI = MF->begin(), MBE = MF->end();
967 CheckLineNumbers(MBI);
972 SelectionDAGISel::FinishBasicBlock() {
974 DEBUG(dbgs() << "Total amount of phi nodes to update: "
975 << FuncInfo->PHINodesToUpdate.size() << "\n";
976 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
977 dbgs() << "Node " << i << " : ("
978 << FuncInfo->PHINodesToUpdate[i].first
979 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
981 // Next, now that we know what the last MBB the LLVM BB expanded is, update
982 // PHI nodes in successors.
983 if (SDB->SwitchCases.empty() &&
984 SDB->JTCases.empty() &&
985 SDB->BitTestCases.empty()) {
986 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
987 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
988 assert(PHI->isPHI() &&
989 "This is not a machine PHI node that we are updating!");
990 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
993 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
994 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
999 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1000 // Lower header first, if it wasn't already lowered
1001 if (!SDB->BitTestCases[i].Emitted) {
1002 // Set the current basic block to the mbb we wish to insert the code into
1003 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1004 FuncInfo->InsertPt = FuncInfo->MBB->end();
1006 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1007 CurDAG->setRoot(SDB->getRoot());
1009 CodeGenAndEmitDAG();
1012 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1013 // Set the current basic block to the mbb we wish to insert the code into
1014 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1015 FuncInfo->InsertPt = FuncInfo->MBB->end();
1018 SDB->visitBitTestCase(SDB->BitTestCases[i],
1019 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1020 SDB->BitTestCases[i].Reg,
1021 SDB->BitTestCases[i].Cases[j],
1024 SDB->visitBitTestCase(SDB->BitTestCases[i],
1025 SDB->BitTestCases[i].Default,
1026 SDB->BitTestCases[i].Reg,
1027 SDB->BitTestCases[i].Cases[j],
1031 CurDAG->setRoot(SDB->getRoot());
1033 CodeGenAndEmitDAG();
1037 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1039 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1040 MachineBasicBlock *PHIBB = PHI->getParent();
1041 assert(PHI->isPHI() &&
1042 "This is not a machine PHI node that we are updating!");
1043 // This is "default" BB. We have two jumps to it. From "header" BB and
1044 // from last "case" BB.
1045 if (PHIBB == SDB->BitTestCases[i].Default) {
1046 PHI->addOperand(MachineOperand::
1047 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1049 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1050 PHI->addOperand(MachineOperand::
1051 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1053 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1056 // One of "cases" BB.
1057 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1059 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1060 if (cBB->isSuccessor(PHIBB)) {
1061 PHI->addOperand(MachineOperand::
1062 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1064 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1069 SDB->BitTestCases.clear();
1071 // If the JumpTable record is filled in, then we need to emit a jump table.
1072 // Updating the PHI nodes is tricky in this case, since we need to determine
1073 // whether the PHI is a successor of the range check MBB or the jump table MBB
1074 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1075 // Lower header first, if it wasn't already lowered
1076 if (!SDB->JTCases[i].first.Emitted) {
1077 // Set the current basic block to the mbb we wish to insert the code into
1078 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1079 FuncInfo->InsertPt = FuncInfo->MBB->end();
1081 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1083 CurDAG->setRoot(SDB->getRoot());
1085 CodeGenAndEmitDAG();
1088 // Set the current basic block to the mbb we wish to insert the code into
1089 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1090 FuncInfo->InsertPt = FuncInfo->MBB->end();
1092 SDB->visitJumpTable(SDB->JTCases[i].second);
1093 CurDAG->setRoot(SDB->getRoot());
1095 CodeGenAndEmitDAG();
1098 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1100 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1101 MachineBasicBlock *PHIBB = PHI->getParent();
1102 assert(PHI->isPHI() &&
1103 "This is not a machine PHI node that we are updating!");
1104 // "default" BB. We can go there only from header BB.
1105 if (PHIBB == SDB->JTCases[i].second.Default) {
1107 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1110 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1112 // JT BB. Just iterate over successors here
1113 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1115 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1117 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1121 SDB->JTCases.clear();
1123 // If the switch block involved a branch to one of the actual successors, we
1124 // need to update PHI nodes in that block.
1125 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1126 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1127 assert(PHI->isPHI() &&
1128 "This is not a machine PHI node that we are updating!");
1129 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1131 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1132 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1136 // If we generated any switch lowering information, build and codegen any
1137 // additional DAGs necessary.
1138 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1139 // Set the current basic block to the mbb we wish to insert the code into
1140 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1141 FuncInfo->InsertPt = FuncInfo->MBB->end();
1143 // Determine the unique successors.
1144 SmallVector<MachineBasicBlock *, 2> Succs;
1145 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1146 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1147 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1149 // Emit the code. Note that this could result in ThisBB being split, so
1150 // we need to check for updates.
1151 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1152 CurDAG->setRoot(SDB->getRoot());
1154 CodeGenAndEmitDAG();
1155 ThisBB = FuncInfo->MBB;
1157 // Handle any PHI nodes in successors of this chunk, as if we were coming
1158 // from the original BB before switch expansion. Note that PHI nodes can
1159 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1160 // handle them the right number of times.
1161 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1162 FuncInfo->MBB = Succs[i];
1163 FuncInfo->InsertPt = FuncInfo->MBB->end();
1164 // FuncInfo->MBB may have been removed from the CFG if a branch was
1166 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1167 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1168 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1170 // This value for this PHI node is recorded in PHINodesToUpdate.
1171 for (unsigned pn = 0; ; ++pn) {
1172 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1173 "Didn't find PHI entry!");
1174 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1175 Phi->addOperand(MachineOperand::
1176 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1178 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1186 SDB->SwitchCases.clear();
1190 /// Create the scheduler. If a specific scheduler was specified
1191 /// via the SchedulerRegistry, use it, otherwise select the
1192 /// one preferred by the target.
1194 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1195 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1199 RegisterScheduler::setDefault(Ctor);
1202 return Ctor(this, OptLevel);
1205 //===----------------------------------------------------------------------===//
1206 // Helper functions used by the generated instruction selector.
1207 //===----------------------------------------------------------------------===//
1208 // Calls to these methods are generated by tblgen.
1210 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1211 /// the dag combiner simplified the 255, we still want to match. RHS is the
1212 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1213 /// specified in the .td file (e.g. 255).
1214 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1215 int64_t DesiredMaskS) const {
1216 const APInt &ActualMask = RHS->getAPIntValue();
1217 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1219 // If the actual mask exactly matches, success!
1220 if (ActualMask == DesiredMask)
1223 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1224 if (ActualMask.intersects(~DesiredMask))
1227 // Otherwise, the DAG Combiner may have proven that the value coming in is
1228 // either already zero or is not demanded. Check for known zero input bits.
1229 APInt NeededMask = DesiredMask & ~ActualMask;
1230 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1233 // TODO: check to see if missing bits are just not demanded.
1235 // Otherwise, this pattern doesn't match.
1239 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1240 /// the dag combiner simplified the 255, we still want to match. RHS is the
1241 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1242 /// specified in the .td file (e.g. 255).
1243 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1244 int64_t DesiredMaskS) const {
1245 const APInt &ActualMask = RHS->getAPIntValue();
1246 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1248 // If the actual mask exactly matches, success!
1249 if (ActualMask == DesiredMask)
1252 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1253 if (ActualMask.intersects(~DesiredMask))
1256 // Otherwise, the DAG Combiner may have proven that the value coming in is
1257 // either already zero or is not demanded. Check for known zero input bits.
1258 APInt NeededMask = DesiredMask & ~ActualMask;
1260 APInt KnownZero, KnownOne;
1261 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1263 // If all the missing bits in the or are already known to be set, match!
1264 if ((NeededMask & KnownOne) == NeededMask)
1267 // TODO: check to see if missing bits are just not demanded.
1269 // Otherwise, this pattern doesn't match.
1274 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1275 /// by tblgen. Others should not call it.
1276 void SelectionDAGISel::
1277 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1278 std::vector<SDValue> InOps;
1279 std::swap(InOps, Ops);
1281 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1282 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1283 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1284 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1286 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1287 if (InOps[e-1].getValueType() == MVT::Glue)
1288 --e; // Don't process a glue operand if it is here.
1291 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1292 if (!InlineAsm::isMemKind(Flags)) {
1293 // Just skip over this operand, copying the operands verbatim.
1294 Ops.insert(Ops.end(), InOps.begin()+i,
1295 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1296 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1298 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1299 "Memory operand with multiple values?");
1300 // Otherwise, this is a memory operand. Ask the target to select it.
1301 std::vector<SDValue> SelOps;
1302 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1303 report_fatal_error("Could not match memory address. Inline asm"
1306 // Add this to the output node.
1308 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1309 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1310 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1315 // Add the glue input back if present.
1316 if (e != InOps.size())
1317 Ops.push_back(InOps.back());
1320 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1323 static SDNode *findGlueUse(SDNode *N) {
1324 unsigned FlagResNo = N->getNumValues()-1;
1325 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1326 SDUse &Use = I.getUse();
1327 if (Use.getResNo() == FlagResNo)
1328 return Use.getUser();
1333 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1334 /// This function recursively traverses up the operand chain, ignoring
1336 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1337 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1338 bool IgnoreChains) {
1339 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1340 // greater than all of its (recursive) operands. If we scan to a point where
1341 // 'use' is smaller than the node we're scanning for, then we know we will
1344 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1345 // happen because we scan down to newly selected nodes in the case of glue
1347 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1350 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1351 // won't fail if we scan it again.
1352 if (!Visited.insert(Use))
1355 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1356 // Ignore chain uses, they are validated by HandleMergeInputChains.
1357 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1360 SDNode *N = Use->getOperand(i).getNode();
1362 if (Use == ImmedUse || Use == Root)
1363 continue; // We are not looking for immediate use.
1368 // Traverse up the operand chain.
1369 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1375 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1376 /// operand node N of U during instruction selection that starts at Root.
1377 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1378 SDNode *Root) const {
1379 if (OptLevel == CodeGenOpt::None) return false;
1380 return N.hasOneUse();
1383 /// IsLegalToFold - Returns true if the specific operand node N of
1384 /// U can be folded during instruction selection that starts at Root.
1385 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1386 CodeGenOpt::Level OptLevel,
1387 bool IgnoreChains) {
1388 if (OptLevel == CodeGenOpt::None) return false;
1390 // If Root use can somehow reach N through a path that that doesn't contain
1391 // U then folding N would create a cycle. e.g. In the following
1392 // diagram, Root can reach N through X. If N is folded into into Root, then
1393 // X is both a predecessor and a successor of U.
1404 // * indicates nodes to be folded together.
1406 // If Root produces glue, then it gets (even more) interesting. Since it
1407 // will be "glued" together with its glue use in the scheduler, we need to
1408 // check if it might reach N.
1427 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1428 // (call it Fold), then X is a predecessor of GU and a successor of
1429 // Fold. But since Fold and GU are glued together, this will create
1430 // a cycle in the scheduling graph.
1432 // If the node has glue, walk down the graph to the "lowest" node in the
1434 EVT VT = Root->getValueType(Root->getNumValues()-1);
1435 while (VT == MVT::Glue) {
1436 SDNode *GU = findGlueUse(Root);
1440 VT = Root->getValueType(Root->getNumValues()-1);
1442 // If our query node has a glue result with a use, we've walked up it. If
1443 // the user (which has already been selected) has a chain or indirectly uses
1444 // the chain, our WalkChainUsers predicate will not consider it. Because of
1445 // this, we cannot ignore chains in this predicate.
1446 IgnoreChains = false;
1450 SmallPtrSet<SDNode*, 16> Visited;
1451 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1454 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1455 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1456 SelectInlineAsmMemoryOperands(Ops);
1458 std::vector<EVT> VTs;
1459 VTs.push_back(MVT::Other);
1460 VTs.push_back(MVT::Glue);
1461 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1462 VTs, &Ops[0], Ops.size());
1464 return New.getNode();
1467 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1468 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1471 /// GetVBR - decode a vbr encoding whose top bit is set.
1472 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1473 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1474 assert(Val >= 128 && "Not a VBR");
1475 Val &= 127; // Remove first vbr bit.
1480 NextBits = MatcherTable[Idx++];
1481 Val |= (NextBits&127) << Shift;
1483 } while (NextBits & 128);
1489 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1490 /// interior glue and chain results to use the new glue and chain results.
1491 void SelectionDAGISel::
1492 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1493 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1495 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1496 bool isMorphNodeTo) {
1497 SmallVector<SDNode*, 4> NowDeadNodes;
1499 ISelUpdater ISU(ISelPosition);
1501 // Now that all the normal results are replaced, we replace the chain and
1502 // glue results if present.
1503 if (!ChainNodesMatched.empty()) {
1504 assert(InputChain.getNode() != 0 &&
1505 "Matched input chains but didn't produce a chain");
1506 // Loop over all of the nodes we matched that produced a chain result.
1507 // Replace all the chain results with the final chain we ended up with.
1508 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1509 SDNode *ChainNode = ChainNodesMatched[i];
1511 // If this node was already deleted, don't look at it.
1512 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1515 // Don't replace the results of the root node if we're doing a
1517 if (ChainNode == NodeToMatch && isMorphNodeTo)
1520 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1521 if (ChainVal.getValueType() == MVT::Glue)
1522 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1523 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1524 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1526 // If the node became dead and we haven't already seen it, delete it.
1527 if (ChainNode->use_empty() &&
1528 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1529 NowDeadNodes.push_back(ChainNode);
1533 // If the result produces glue, update any glue results in the matched
1534 // pattern with the glue result.
1535 if (InputGlue.getNode() != 0) {
1536 // Handle any interior nodes explicitly marked.
1537 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1538 SDNode *FRN = GlueResultNodesMatched[i];
1540 // If this node was already deleted, don't look at it.
1541 if (FRN->getOpcode() == ISD::DELETED_NODE)
1544 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1545 "Doesn't have a glue result");
1546 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1549 // If the node became dead and we haven't already seen it, delete it.
1550 if (FRN->use_empty() &&
1551 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1552 NowDeadNodes.push_back(FRN);
1556 if (!NowDeadNodes.empty())
1557 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1559 DEBUG(errs() << "ISEL: Match complete!\n");
1565 CR_LeadsToInteriorNode
1568 /// WalkChainUsers - Walk down the users of the specified chained node that is
1569 /// part of the pattern we're matching, looking at all of the users we find.
1570 /// This determines whether something is an interior node, whether we have a
1571 /// non-pattern node in between two pattern nodes (which prevent folding because
1572 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1573 /// between pattern nodes (in which case the TF becomes part of the pattern).
1575 /// The walk we do here is guaranteed to be small because we quickly get down to
1576 /// already selected nodes "below" us.
1578 WalkChainUsers(SDNode *ChainedNode,
1579 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1580 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1581 ChainResult Result = CR_Simple;
1583 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1584 E = ChainedNode->use_end(); UI != E; ++UI) {
1585 // Make sure the use is of the chain, not some other value we produce.
1586 if (UI.getUse().getValueType() != MVT::Other) continue;
1590 // If we see an already-selected machine node, then we've gone beyond the
1591 // pattern that we're selecting down into the already selected chunk of the
1593 if (User->isMachineOpcode() ||
1594 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1597 if (User->getOpcode() == ISD::CopyToReg ||
1598 User->getOpcode() == ISD::CopyFromReg ||
1599 User->getOpcode() == ISD::INLINEASM ||
1600 User->getOpcode() == ISD::EH_LABEL) {
1601 // If their node ID got reset to -1 then they've already been selected.
1602 // Treat them like a MachineOpcode.
1603 if (User->getNodeId() == -1)
1607 // If we have a TokenFactor, we handle it specially.
1608 if (User->getOpcode() != ISD::TokenFactor) {
1609 // If the node isn't a token factor and isn't part of our pattern, then it
1610 // must be a random chained node in between two nodes we're selecting.
1611 // This happens when we have something like:
1616 // Because we structurally match the load/store as a read/modify/write,
1617 // but the call is chained between them. We cannot fold in this case
1618 // because it would induce a cycle in the graph.
1619 if (!std::count(ChainedNodesInPattern.begin(),
1620 ChainedNodesInPattern.end(), User))
1621 return CR_InducesCycle;
1623 // Otherwise we found a node that is part of our pattern. For example in:
1627 // This would happen when we're scanning down from the load and see the
1628 // store as a user. Record that there is a use of ChainedNode that is
1629 // part of the pattern and keep scanning uses.
1630 Result = CR_LeadsToInteriorNode;
1631 InteriorChainedNodes.push_back(User);
1635 // If we found a TokenFactor, there are two cases to consider: first if the
1636 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1637 // uses of the TF are in our pattern) we just want to ignore it. Second,
1638 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1644 // | \ DAG's like cheese
1647 // [TokenFactor] [Op]
1654 // In this case, the TokenFactor becomes part of our match and we rewrite it
1655 // as a new TokenFactor.
1657 // To distinguish these two cases, do a recursive walk down the uses.
1658 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1660 // If the uses of the TokenFactor are just already-selected nodes, ignore
1661 // it, it is "below" our pattern.
1663 case CR_InducesCycle:
1664 // If the uses of the TokenFactor lead to nodes that are not part of our
1665 // pattern that are not selected, folding would turn this into a cycle,
1667 return CR_InducesCycle;
1668 case CR_LeadsToInteriorNode:
1669 break; // Otherwise, keep processing.
1672 // Okay, we know we're in the interesting interior case. The TokenFactor
1673 // is now going to be considered part of the pattern so that we rewrite its
1674 // uses (it may have uses that are not part of the pattern) with the
1675 // ultimate chain result of the generated code. We will also add its chain
1676 // inputs as inputs to the ultimate TokenFactor we create.
1677 Result = CR_LeadsToInteriorNode;
1678 ChainedNodesInPattern.push_back(User);
1679 InteriorChainedNodes.push_back(User);
1686 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1687 /// operation for when the pattern matched at least one node with a chains. The
1688 /// input vector contains a list of all of the chained nodes that we match. We
1689 /// must determine if this is a valid thing to cover (i.e. matching it won't
1690 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1691 /// be used as the input node chain for the generated nodes.
1693 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1694 SelectionDAG *CurDAG) {
1695 // Walk all of the chained nodes we've matched, recursively scanning down the
1696 // users of the chain result. This adds any TokenFactor nodes that are caught
1697 // in between chained nodes to the chained and interior nodes list.
1698 SmallVector<SDNode*, 3> InteriorChainedNodes;
1699 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1700 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1701 InteriorChainedNodes) == CR_InducesCycle)
1702 return SDValue(); // Would induce a cycle.
1705 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1706 // that we are interested in. Form our input TokenFactor node.
1707 SmallVector<SDValue, 3> InputChains;
1708 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1709 // Add the input chain of this node to the InputChains list (which will be
1710 // the operands of the generated TokenFactor) if it's not an interior node.
1711 SDNode *N = ChainNodesMatched[i];
1712 if (N->getOpcode() != ISD::TokenFactor) {
1713 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1716 // Otherwise, add the input chain.
1717 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1718 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1719 InputChains.push_back(InChain);
1723 // If we have a token factor, we want to add all inputs of the token factor
1724 // that are not part of the pattern we're matching.
1725 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1726 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1727 N->getOperand(op).getNode()))
1728 InputChains.push_back(N->getOperand(op));
1733 if (InputChains.size() == 1)
1734 return InputChains[0];
1735 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1736 MVT::Other, &InputChains[0], InputChains.size());
1739 /// MorphNode - Handle morphing a node in place for the selector.
1740 SDNode *SelectionDAGISel::
1741 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1742 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1743 // It is possible we're using MorphNodeTo to replace a node with no
1744 // normal results with one that has a normal result (or we could be
1745 // adding a chain) and the input could have glue and chains as well.
1746 // In this case we need to shift the operands down.
1747 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1748 // than the old isel though.
1749 int OldGlueResultNo = -1, OldChainResultNo = -1;
1751 unsigned NTMNumResults = Node->getNumValues();
1752 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1753 OldGlueResultNo = NTMNumResults-1;
1754 if (NTMNumResults != 1 &&
1755 Node->getValueType(NTMNumResults-2) == MVT::Other)
1756 OldChainResultNo = NTMNumResults-2;
1757 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1758 OldChainResultNo = NTMNumResults-1;
1760 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1761 // that this deletes operands of the old node that become dead.
1762 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1764 // MorphNodeTo can operate in two ways: if an existing node with the
1765 // specified operands exists, it can just return it. Otherwise, it
1766 // updates the node in place to have the requested operands.
1768 // If we updated the node in place, reset the node ID. To the isel,
1769 // this should be just like a newly allocated machine node.
1773 unsigned ResNumResults = Res->getNumValues();
1774 // Move the glue if needed.
1775 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1776 (unsigned)OldGlueResultNo != ResNumResults-1)
1777 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1778 SDValue(Res, ResNumResults-1));
1780 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1783 // Move the chain reference if needed.
1784 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1785 (unsigned)OldChainResultNo != ResNumResults-1)
1786 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1787 SDValue(Res, ResNumResults-1));
1789 // Otherwise, no replacement happened because the node already exists. Replace
1790 // Uses of the old node with the new one.
1792 CurDAG->ReplaceAllUsesWith(Node, Res);
1797 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1798 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1799 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1801 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1802 // Accept if it is exactly the same as a previously recorded node.
1803 unsigned RecNo = MatcherTable[MatcherIndex++];
1804 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1805 return N == RecordedNodes[RecNo].first;
1808 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1809 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1810 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1811 SelectionDAGISel &SDISel) {
1812 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1815 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1816 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1817 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1818 SelectionDAGISel &SDISel, SDNode *N) {
1819 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1822 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1823 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1825 uint16_t Opc = MatcherTable[MatcherIndex++];
1826 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1827 return N->getOpcode() == Opc;
1830 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1831 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1832 SDValue N, const TargetLowering &TLI) {
1833 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1834 if (N.getValueType() == VT) return true;
1836 // Handle the case when VT is iPTR.
1837 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1840 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1841 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1842 SDValue N, const TargetLowering &TLI,
1844 if (ChildNo >= N.getNumOperands())
1845 return false; // Match fails if out of range child #.
1846 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1850 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1851 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1853 return cast<CondCodeSDNode>(N)->get() ==
1854 (ISD::CondCode)MatcherTable[MatcherIndex++];
1857 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1858 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1859 SDValue N, const TargetLowering &TLI) {
1860 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1861 if (cast<VTSDNode>(N)->getVT() == VT)
1864 // Handle the case when VT is iPTR.
1865 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1868 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1869 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1871 int64_t Val = MatcherTable[MatcherIndex++];
1873 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1875 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1876 return C != 0 && C->getSExtValue() == Val;
1879 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1880 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1881 SDValue N, SelectionDAGISel &SDISel) {
1882 int64_t Val = MatcherTable[MatcherIndex++];
1884 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1886 if (N->getOpcode() != ISD::AND) return false;
1888 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1889 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1892 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1893 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1894 SDValue N, SelectionDAGISel &SDISel) {
1895 int64_t Val = MatcherTable[MatcherIndex++];
1897 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1899 if (N->getOpcode() != ISD::OR) return false;
1901 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1902 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1905 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1906 /// scope, evaluate the current node. If the current predicate is known to
1907 /// fail, set Result=true and return anything. If the current predicate is
1908 /// known to pass, set Result=false and return the MatcherIndex to continue
1909 /// with. If the current predicate is unknown, set Result=false and return the
1910 /// MatcherIndex to continue with.
1911 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1912 unsigned Index, SDValue N,
1913 bool &Result, SelectionDAGISel &SDISel,
1914 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1915 switch (Table[Index++]) {
1918 return Index-1; // Could not evaluate this predicate.
1919 case SelectionDAGISel::OPC_CheckSame:
1920 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1922 case SelectionDAGISel::OPC_CheckPatternPredicate:
1923 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1925 case SelectionDAGISel::OPC_CheckPredicate:
1926 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1928 case SelectionDAGISel::OPC_CheckOpcode:
1929 Result = !::CheckOpcode(Table, Index, N.getNode());
1931 case SelectionDAGISel::OPC_CheckType:
1932 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1934 case SelectionDAGISel::OPC_CheckChild0Type:
1935 case SelectionDAGISel::OPC_CheckChild1Type:
1936 case SelectionDAGISel::OPC_CheckChild2Type:
1937 case SelectionDAGISel::OPC_CheckChild3Type:
1938 case SelectionDAGISel::OPC_CheckChild4Type:
1939 case SelectionDAGISel::OPC_CheckChild5Type:
1940 case SelectionDAGISel::OPC_CheckChild6Type:
1941 case SelectionDAGISel::OPC_CheckChild7Type:
1942 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1943 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1945 case SelectionDAGISel::OPC_CheckCondCode:
1946 Result = !::CheckCondCode(Table, Index, N);
1948 case SelectionDAGISel::OPC_CheckValueType:
1949 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1951 case SelectionDAGISel::OPC_CheckInteger:
1952 Result = !::CheckInteger(Table, Index, N);
1954 case SelectionDAGISel::OPC_CheckAndImm:
1955 Result = !::CheckAndImm(Table, Index, N, SDISel);
1957 case SelectionDAGISel::OPC_CheckOrImm:
1958 Result = !::CheckOrImm(Table, Index, N, SDISel);
1966 /// FailIndex - If this match fails, this is the index to continue with.
1969 /// NodeStack - The node stack when the scope was formed.
1970 SmallVector<SDValue, 4> NodeStack;
1972 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1973 unsigned NumRecordedNodes;
1975 /// NumMatchedMemRefs - The number of matched memref entries.
1976 unsigned NumMatchedMemRefs;
1978 /// InputChain/InputGlue - The current chain/glue
1979 SDValue InputChain, InputGlue;
1981 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1982 bool HasChainNodesMatched, HasGlueResultNodesMatched;
1987 SDNode *SelectionDAGISel::
1988 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1989 unsigned TableSize) {
1990 // FIXME: Should these even be selected? Handle these cases in the caller?
1991 switch (NodeToMatch->getOpcode()) {
1994 case ISD::EntryToken: // These nodes remain the same.
1995 case ISD::BasicBlock:
1997 //case ISD::VALUETYPE:
1998 //case ISD::CONDCODE:
1999 case ISD::HANDLENODE:
2000 case ISD::MDNODE_SDNODE:
2001 case ISD::TargetConstant:
2002 case ISD::TargetConstantFP:
2003 case ISD::TargetConstantPool:
2004 case ISD::TargetFrameIndex:
2005 case ISD::TargetExternalSymbol:
2006 case ISD::TargetBlockAddress:
2007 case ISD::TargetJumpTable:
2008 case ISD::TargetGlobalTLSAddress:
2009 case ISD::TargetGlobalAddress:
2010 case ISD::TokenFactor:
2011 case ISD::CopyFromReg:
2012 case ISD::CopyToReg:
2014 NodeToMatch->setNodeId(-1); // Mark selected.
2016 case ISD::AssertSext:
2017 case ISD::AssertZext:
2018 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2019 NodeToMatch->getOperand(0));
2021 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2022 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2025 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2027 // Set up the node stack with NodeToMatch as the only node on the stack.
2028 SmallVector<SDValue, 8> NodeStack;
2029 SDValue N = SDValue(NodeToMatch, 0);
2030 NodeStack.push_back(N);
2032 // MatchScopes - Scopes used when matching, if a match failure happens, this
2033 // indicates where to continue checking.
2034 SmallVector<MatchScope, 8> MatchScopes;
2036 // RecordedNodes - This is the set of nodes that have been recorded by the
2037 // state machine. The second value is the parent of the node, or null if the
2038 // root is recorded.
2039 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2041 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2043 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2045 // These are the current input chain and glue for use when generating nodes.
2046 // Various Emit operations change these. For example, emitting a copytoreg
2047 // uses and updates these.
2048 SDValue InputChain, InputGlue;
2050 // ChainNodesMatched - If a pattern matches nodes that have input/output
2051 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2052 // which ones they are. The result is captured into this list so that we can
2053 // update the chain results when the pattern is complete.
2054 SmallVector<SDNode*, 3> ChainNodesMatched;
2055 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2057 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2058 NodeToMatch->dump(CurDAG);
2061 // Determine where to start the interpreter. Normally we start at opcode #0,
2062 // but if the state machine starts with an OPC_SwitchOpcode, then we
2063 // accelerate the first lookup (which is guaranteed to be hot) with the
2064 // OpcodeOffset table.
2065 unsigned MatcherIndex = 0;
2067 if (!OpcodeOffset.empty()) {
2068 // Already computed the OpcodeOffset table, just index into it.
2069 if (N.getOpcode() < OpcodeOffset.size())
2070 MatcherIndex = OpcodeOffset[N.getOpcode()];
2071 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2073 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2074 // Otherwise, the table isn't computed, but the state machine does start
2075 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2076 // is the first time we're selecting an instruction.
2079 // Get the size of this case.
2080 unsigned CaseSize = MatcherTable[Idx++];
2082 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2083 if (CaseSize == 0) break;
2085 // Get the opcode, add the index to the table.
2086 uint16_t Opc = MatcherTable[Idx++];
2087 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2088 if (Opc >= OpcodeOffset.size())
2089 OpcodeOffset.resize((Opc+1)*2);
2090 OpcodeOffset[Opc] = Idx;
2094 // Okay, do the lookup for the first opcode.
2095 if (N.getOpcode() < OpcodeOffset.size())
2096 MatcherIndex = OpcodeOffset[N.getOpcode()];
2100 assert(MatcherIndex < TableSize && "Invalid index");
2102 unsigned CurrentOpcodeIndex = MatcherIndex;
2104 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2107 // Okay, the semantics of this operation are that we should push a scope
2108 // then evaluate the first child. However, pushing a scope only to have
2109 // the first check fail (which then pops it) is inefficient. If we can
2110 // determine immediately that the first check (or first several) will
2111 // immediately fail, don't even bother pushing a scope for them.
2115 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2116 if (NumToSkip & 128)
2117 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2118 // Found the end of the scope with no match.
2119 if (NumToSkip == 0) {
2124 FailIndex = MatcherIndex+NumToSkip;
2126 unsigned MatcherIndexOfPredicate = MatcherIndex;
2127 (void)MatcherIndexOfPredicate; // silence warning.
2129 // If we can't evaluate this predicate without pushing a scope (e.g. if
2130 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2131 // push the scope and evaluate the full predicate chain.
2133 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2134 Result, *this, RecordedNodes);
2138 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2139 << "index " << MatcherIndexOfPredicate
2140 << ", continuing at " << FailIndex << "\n");
2141 ++NumDAGIselRetries;
2143 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2144 // move to the next case.
2145 MatcherIndex = FailIndex;
2148 // If the whole scope failed to match, bail.
2149 if (FailIndex == 0) break;
2151 // Push a MatchScope which indicates where to go if the first child fails
2153 MatchScope NewEntry;
2154 NewEntry.FailIndex = FailIndex;
2155 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2156 NewEntry.NumRecordedNodes = RecordedNodes.size();
2157 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2158 NewEntry.InputChain = InputChain;
2159 NewEntry.InputGlue = InputGlue;
2160 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2161 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2162 MatchScopes.push_back(NewEntry);
2165 case OPC_RecordNode: {
2166 // Remember this node, it may end up being an operand in the pattern.
2168 if (NodeStack.size() > 1)
2169 Parent = NodeStack[NodeStack.size()-2].getNode();
2170 RecordedNodes.push_back(std::make_pair(N, Parent));
2174 case OPC_RecordChild0: case OPC_RecordChild1:
2175 case OPC_RecordChild2: case OPC_RecordChild3:
2176 case OPC_RecordChild4: case OPC_RecordChild5:
2177 case OPC_RecordChild6: case OPC_RecordChild7: {
2178 unsigned ChildNo = Opcode-OPC_RecordChild0;
2179 if (ChildNo >= N.getNumOperands())
2180 break; // Match fails if out of range child #.
2182 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2186 case OPC_RecordMemRef:
2187 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2190 case OPC_CaptureGlueInput:
2191 // If the current node has an input glue, capture it in InputGlue.
2192 if (N->getNumOperands() != 0 &&
2193 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2194 InputGlue = N->getOperand(N->getNumOperands()-1);
2197 case OPC_MoveChild: {
2198 unsigned ChildNo = MatcherTable[MatcherIndex++];
2199 if (ChildNo >= N.getNumOperands())
2200 break; // Match fails if out of range child #.
2201 N = N.getOperand(ChildNo);
2202 NodeStack.push_back(N);
2206 case OPC_MoveParent:
2207 // Pop the current node off the NodeStack.
2208 NodeStack.pop_back();
2209 assert(!NodeStack.empty() && "Node stack imbalance!");
2210 N = NodeStack.back();
2214 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2216 case OPC_CheckPatternPredicate:
2217 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2219 case OPC_CheckPredicate:
2220 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2224 case OPC_CheckComplexPat: {
2225 unsigned CPNum = MatcherTable[MatcherIndex++];
2226 unsigned RecNo = MatcherTable[MatcherIndex++];
2227 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2228 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2229 RecordedNodes[RecNo].first, CPNum,
2234 case OPC_CheckOpcode:
2235 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2239 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2242 case OPC_SwitchOpcode: {
2243 unsigned CurNodeOpcode = N.getOpcode();
2244 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2247 // Get the size of this case.
2248 CaseSize = MatcherTable[MatcherIndex++];
2250 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2251 if (CaseSize == 0) break;
2253 uint16_t Opc = MatcherTable[MatcherIndex++];
2254 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2256 // If the opcode matches, then we will execute this case.
2257 if (CurNodeOpcode == Opc)
2260 // Otherwise, skip over this case.
2261 MatcherIndex += CaseSize;
2264 // If no cases matched, bail out.
2265 if (CaseSize == 0) break;
2267 // Otherwise, execute the case we found.
2268 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2269 << " to " << MatcherIndex << "\n");
2273 case OPC_SwitchType: {
2274 MVT CurNodeVT = N.getValueType().getSimpleVT();
2275 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2278 // Get the size of this case.
2279 CaseSize = MatcherTable[MatcherIndex++];
2281 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2282 if (CaseSize == 0) break;
2284 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2285 if (CaseVT == MVT::iPTR)
2286 CaseVT = TLI.getPointerTy();
2288 // If the VT matches, then we will execute this case.
2289 if (CurNodeVT == CaseVT)
2292 // Otherwise, skip over this case.
2293 MatcherIndex += CaseSize;
2296 // If no cases matched, bail out.
2297 if (CaseSize == 0) break;
2299 // Otherwise, execute the case we found.
2300 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2301 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2304 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2305 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2306 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2307 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2308 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2309 Opcode-OPC_CheckChild0Type))
2312 case OPC_CheckCondCode:
2313 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2315 case OPC_CheckValueType:
2316 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2318 case OPC_CheckInteger:
2319 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2321 case OPC_CheckAndImm:
2322 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2324 case OPC_CheckOrImm:
2325 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2328 case OPC_CheckFoldableChainNode: {
2329 assert(NodeStack.size() != 1 && "No parent node");
2330 // Verify that all intermediate nodes between the root and this one have
2332 bool HasMultipleUses = false;
2333 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2334 if (!NodeStack[i].hasOneUse()) {
2335 HasMultipleUses = true;
2338 if (HasMultipleUses) break;
2340 // Check to see that the target thinks this is profitable to fold and that
2341 // we can fold it without inducing cycles in the graph.
2342 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2344 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2345 NodeToMatch, OptLevel,
2346 true/*We validate our own chains*/))
2351 case OPC_EmitInteger: {
2352 MVT::SimpleValueType VT =
2353 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2354 int64_t Val = MatcherTable[MatcherIndex++];
2356 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2357 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2358 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2361 case OPC_EmitRegister: {
2362 MVT::SimpleValueType VT =
2363 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2364 unsigned RegNo = MatcherTable[MatcherIndex++];
2365 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2366 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2370 case OPC_EmitConvertToTarget: {
2371 // Convert from IMM/FPIMM to target version.
2372 unsigned RecNo = MatcherTable[MatcherIndex++];
2373 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2374 SDValue Imm = RecordedNodes[RecNo].first;
2376 if (Imm->getOpcode() == ISD::Constant) {
2377 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2378 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2379 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2380 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2381 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2384 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2388 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2389 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2390 // These are space-optimized forms of OPC_EmitMergeInputChains.
2391 assert(InputChain.getNode() == 0 &&
2392 "EmitMergeInputChains should be the first chain producing node");
2393 assert(ChainNodesMatched.empty() &&
2394 "Should only have one EmitMergeInputChains per match");
2396 // Read all of the chained nodes.
2397 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2398 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2399 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2401 // FIXME: What if other value results of the node have uses not matched
2403 if (ChainNodesMatched.back() != NodeToMatch &&
2404 !RecordedNodes[RecNo].first.hasOneUse()) {
2405 ChainNodesMatched.clear();
2409 // Merge the input chains if they are not intra-pattern references.
2410 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2412 if (InputChain.getNode() == 0)
2413 break; // Failed to merge.
2417 case OPC_EmitMergeInputChains: {
2418 assert(InputChain.getNode() == 0 &&
2419 "EmitMergeInputChains should be the first chain producing node");
2420 // This node gets a list of nodes we matched in the input that have
2421 // chains. We want to token factor all of the input chains to these nodes
2422 // together. However, if any of the input chains is actually one of the
2423 // nodes matched in this pattern, then we have an intra-match reference.
2424 // Ignore these because the newly token factored chain should not refer to
2426 unsigned NumChains = MatcherTable[MatcherIndex++];
2427 assert(NumChains != 0 && "Can't TF zero chains");
2429 assert(ChainNodesMatched.empty() &&
2430 "Should only have one EmitMergeInputChains per match");
2432 // Read all of the chained nodes.
2433 for (unsigned i = 0; i != NumChains; ++i) {
2434 unsigned RecNo = MatcherTable[MatcherIndex++];
2435 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2436 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2438 // FIXME: What if other value results of the node have uses not matched
2440 if (ChainNodesMatched.back() != NodeToMatch &&
2441 !RecordedNodes[RecNo].first.hasOneUse()) {
2442 ChainNodesMatched.clear();
2447 // If the inner loop broke out, the match fails.
2448 if (ChainNodesMatched.empty())
2451 // Merge the input chains if they are not intra-pattern references.
2452 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2454 if (InputChain.getNode() == 0)
2455 break; // Failed to merge.
2460 case OPC_EmitCopyToReg: {
2461 unsigned RecNo = MatcherTable[MatcherIndex++];
2462 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2463 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2465 if (InputChain.getNode() == 0)
2466 InputChain = CurDAG->getEntryNode();
2468 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2469 DestPhysReg, RecordedNodes[RecNo].first,
2472 InputGlue = InputChain.getValue(1);
2476 case OPC_EmitNodeXForm: {
2477 unsigned XFormNo = MatcherTable[MatcherIndex++];
2478 unsigned RecNo = MatcherTable[MatcherIndex++];
2479 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2480 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2481 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2486 case OPC_MorphNodeTo: {
2487 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2488 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2489 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2490 // Get the result VT list.
2491 unsigned NumVTs = MatcherTable[MatcherIndex++];
2492 SmallVector<EVT, 4> VTs;
2493 for (unsigned i = 0; i != NumVTs; ++i) {
2494 MVT::SimpleValueType VT =
2495 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2496 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2500 if (EmitNodeInfo & OPFL_Chain)
2501 VTs.push_back(MVT::Other);
2502 if (EmitNodeInfo & OPFL_GlueOutput)
2503 VTs.push_back(MVT::Glue);
2505 // This is hot code, so optimize the two most common cases of 1 and 2
2508 if (VTs.size() == 1)
2509 VTList = CurDAG->getVTList(VTs[0]);
2510 else if (VTs.size() == 2)
2511 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2513 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2515 // Get the operand list.
2516 unsigned NumOps = MatcherTable[MatcherIndex++];
2517 SmallVector<SDValue, 8> Ops;
2518 for (unsigned i = 0; i != NumOps; ++i) {
2519 unsigned RecNo = MatcherTable[MatcherIndex++];
2521 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2523 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2524 Ops.push_back(RecordedNodes[RecNo].first);
2527 // If there are variadic operands to add, handle them now.
2528 if (EmitNodeInfo & OPFL_VariadicInfo) {
2529 // Determine the start index to copy from.
2530 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2531 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2532 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2533 "Invalid variadic node");
2534 // Copy all of the variadic operands, not including a potential glue
2536 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2538 SDValue V = NodeToMatch->getOperand(i);
2539 if (V.getValueType() == MVT::Glue) break;
2544 // If this has chain/glue inputs, add them.
2545 if (EmitNodeInfo & OPFL_Chain)
2546 Ops.push_back(InputChain);
2547 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2548 Ops.push_back(InputGlue);
2552 if (Opcode != OPC_MorphNodeTo) {
2553 // If this is a normal EmitNode command, just create the new node and
2554 // add the results to the RecordedNodes list.
2555 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2556 VTList, Ops.data(), Ops.size());
2558 // Add all the non-glue/non-chain results to the RecordedNodes list.
2559 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2560 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2561 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2566 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2570 // If the node had chain/glue results, update our notion of the current
2572 if (EmitNodeInfo & OPFL_GlueOutput) {
2573 InputGlue = SDValue(Res, VTs.size()-1);
2574 if (EmitNodeInfo & OPFL_Chain)
2575 InputChain = SDValue(Res, VTs.size()-2);
2576 } else if (EmitNodeInfo & OPFL_Chain)
2577 InputChain = SDValue(Res, VTs.size()-1);
2579 // If the OPFL_MemRefs glue is set on this node, slap all of the
2580 // accumulated memrefs onto it.
2582 // FIXME: This is vastly incorrect for patterns with multiple outputs
2583 // instructions that access memory and for ComplexPatterns that match
2585 if (EmitNodeInfo & OPFL_MemRefs) {
2586 MachineSDNode::mmo_iterator MemRefs =
2587 MF->allocateMemRefsArray(MatchedMemRefs.size());
2588 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2589 cast<MachineSDNode>(Res)
2590 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2594 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2595 << " node: "; Res->dump(CurDAG); errs() << "\n");
2597 // If this was a MorphNodeTo then we're completely done!
2598 if (Opcode == OPC_MorphNodeTo) {
2599 // Update chain and glue uses.
2600 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2601 InputGlue, GlueResultNodesMatched, true);
2608 case OPC_MarkGlueResults: {
2609 unsigned NumNodes = MatcherTable[MatcherIndex++];
2611 // Read and remember all the glue-result nodes.
2612 for (unsigned i = 0; i != NumNodes; ++i) {
2613 unsigned RecNo = MatcherTable[MatcherIndex++];
2615 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2617 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2618 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2623 case OPC_CompleteMatch: {
2624 // The match has been completed, and any new nodes (if any) have been
2625 // created. Patch up references to the matched dag to use the newly
2627 unsigned NumResults = MatcherTable[MatcherIndex++];
2629 for (unsigned i = 0; i != NumResults; ++i) {
2630 unsigned ResSlot = MatcherTable[MatcherIndex++];
2632 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2634 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2635 SDValue Res = RecordedNodes[ResSlot].first;
2637 assert(i < NodeToMatch->getNumValues() &&
2638 NodeToMatch->getValueType(i) != MVT::Other &&
2639 NodeToMatch->getValueType(i) != MVT::Glue &&
2640 "Invalid number of results to complete!");
2641 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2642 NodeToMatch->getValueType(i) == MVT::iPTR ||
2643 Res.getValueType() == MVT::iPTR ||
2644 NodeToMatch->getValueType(i).getSizeInBits() ==
2645 Res.getValueType().getSizeInBits()) &&
2646 "invalid replacement");
2647 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2650 // If the root node defines glue, add it to the glue nodes to update list.
2651 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2652 GlueResultNodesMatched.push_back(NodeToMatch);
2654 // Update chain and glue uses.
2655 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2656 InputGlue, GlueResultNodesMatched, false);
2658 assert(NodeToMatch->use_empty() &&
2659 "Didn't replace all uses of the node?");
2661 // FIXME: We just return here, which interacts correctly with SelectRoot
2662 // above. We should fix this to not return an SDNode* anymore.
2667 // If the code reached this point, then the match failed. See if there is
2668 // another child to try in the current 'Scope', otherwise pop it until we
2669 // find a case to check.
2670 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2671 ++NumDAGIselRetries;
2673 if (MatchScopes.empty()) {
2674 CannotYetSelect(NodeToMatch);
2678 // Restore the interpreter state back to the point where the scope was
2680 MatchScope &LastScope = MatchScopes.back();
2681 RecordedNodes.resize(LastScope.NumRecordedNodes);
2683 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2684 N = NodeStack.back();
2686 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2687 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2688 MatcherIndex = LastScope.FailIndex;
2690 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2692 InputChain = LastScope.InputChain;
2693 InputGlue = LastScope.InputGlue;
2694 if (!LastScope.HasChainNodesMatched)
2695 ChainNodesMatched.clear();
2696 if (!LastScope.HasGlueResultNodesMatched)
2697 GlueResultNodesMatched.clear();
2699 // Check to see what the offset is at the new MatcherIndex. If it is zero
2700 // we have reached the end of this scope, otherwise we have another child
2701 // in the current scope to try.
2702 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2703 if (NumToSkip & 128)
2704 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2706 // If we have another child in this scope to match, update FailIndex and
2708 if (NumToSkip != 0) {
2709 LastScope.FailIndex = MatcherIndex+NumToSkip;
2713 // End of this scope, pop it and try the next child in the containing
2715 MatchScopes.pop_back();
2722 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2724 raw_string_ostream Msg(msg);
2725 Msg << "Cannot select: ";
2727 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2728 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2729 N->getOpcode() != ISD::INTRINSIC_VOID) {
2730 N->printrFull(Msg, CurDAG);
2732 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2734 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2735 if (iid < Intrinsic::num_intrinsics)
2736 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2737 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2738 Msg << "target intrinsic %" << TII->getName(iid);
2740 Msg << "unknown intrinsic #" << iid;
2742 report_fatal_error(Msg.str());
2745 char SelectionDAGISel::ID = 0;