1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/TargetLibraryInfo.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SelectionDAGISel.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugInfo.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/IntrinsicInst.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/LLVMContext.h"
45 #include "llvm/IR/Module.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetIntrinsicInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "llvm/Target/TargetOptions.h"
57 #include "llvm/Target/TargetRegisterInfo.h"
58 #include "llvm/Target/TargetSubtargetInfo.h"
59 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
63 #define DEBUG_TYPE "isel"
65 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
66 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
67 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
68 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
69 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
70 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
71 STATISTIC(NumFastIselFailLowerArguments,
72 "Number of entry blocks where fast isel failed to lower arguments");
76 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
77 cl::desc("Enable extra verbose messages in the \"fast\" "
78 "instruction selector"));
81 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
82 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
83 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
84 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
85 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
86 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
87 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
89 // Standard binary operators...
90 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
91 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
92 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
93 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
94 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
95 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
96 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
97 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
98 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
99 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
100 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
101 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
103 // Logical operators...
104 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
105 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
106 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
108 // Memory instructions...
109 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
110 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
111 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
112 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
113 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
114 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
115 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
117 // Convert instructions...
118 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
119 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
120 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
121 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
122 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
123 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
124 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
125 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
126 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
127 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
128 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
129 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
131 // Other instructions...
132 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
133 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
134 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
135 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
136 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
137 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
138 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
139 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
140 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
141 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
142 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
143 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
144 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
145 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
146 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
148 // Intrinsic instructions...
149 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
150 STATISTIC(NumFastIselFailSAddWithOverflow,
151 "Fast isel fails on sadd.with.overflow");
152 STATISTIC(NumFastIselFailUAddWithOverflow,
153 "Fast isel fails on uadd.with.overflow");
154 STATISTIC(NumFastIselFailSSubWithOverflow,
155 "Fast isel fails on ssub.with.overflow");
156 STATISTIC(NumFastIselFailUSubWithOverflow,
157 "Fast isel fails on usub.with.overflow");
158 STATISTIC(NumFastIselFailSMulWithOverflow,
159 "Fast isel fails on smul.with.overflow");
160 STATISTIC(NumFastIselFailUMulWithOverflow,
161 "Fast isel fails on umul.with.overflow");
162 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
163 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
164 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
165 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
169 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
170 cl::desc("Enable verbose messages in the \"fast\" "
171 "instruction selector"));
172 static cl::opt<int> EnableFastISelAbort(
173 "fast-isel-abort", cl::Hidden,
174 cl::desc("Enable abort calls when \"fast\" instruction selection "
175 "fails to lower an instruction: 0 disable the abort, 1 will "
176 "abort but for args, calls and terminators, 2 will also "
177 "abort for argument lowering, and 3 will never fallback "
178 "to SelectionDAG."));
182 cl::desc("use Machine Branch Probability Info"),
183 cl::init(true), cl::Hidden);
186 static cl::opt<std::string>
187 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
188 cl::desc("Only display the basic block whose name "
189 "matches this for all view-*-dags options"));
191 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
192 cl::desc("Pop up a window to show dags before the first "
193 "dag combine pass"));
195 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before legalize types"));
198 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
199 cl::desc("Pop up a window to show dags before legalize"));
201 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
202 cl::desc("Pop up a window to show dags before the second "
203 "dag combine pass"));
205 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
206 cl::desc("Pop up a window to show dags before the post legalize types"
207 " dag combine pass"));
209 ViewISelDAGs("view-isel-dags", cl::Hidden,
210 cl::desc("Pop up a window to show isel dags as they are selected"));
212 ViewSchedDAGs("view-sched-dags", cl::Hidden,
213 cl::desc("Pop up a window to show sched dags as they are processed"));
215 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
216 cl::desc("Pop up a window to show SUnit dags after they are processed"));
218 static const bool ViewDAGCombine1 = false,
219 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
220 ViewDAGCombine2 = false,
221 ViewDAGCombineLT = false,
222 ViewISelDAGs = false, ViewSchedDAGs = false,
223 ViewSUnitDAGs = false;
226 //===---------------------------------------------------------------------===//
228 /// RegisterScheduler class - Track the registration of instruction schedulers.
230 //===---------------------------------------------------------------------===//
231 MachinePassRegistry RegisterScheduler::Registry;
233 //===---------------------------------------------------------------------===//
235 /// ISHeuristic command line option for instruction schedulers.
237 //===---------------------------------------------------------------------===//
238 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
239 RegisterPassParser<RegisterScheduler> >
240 ISHeuristic("pre-RA-sched",
241 cl::init(&createDefaultScheduler), cl::Hidden,
242 cl::desc("Instruction schedulers available (before register"
245 static RegisterScheduler
246 defaultListDAGScheduler("default", "Best scheduler for the target",
247 createDefaultScheduler);
250 //===--------------------------------------------------------------------===//
251 /// \brief This class is used by SelectionDAGISel to temporarily override
252 /// the optimization level on a per-function basis.
253 class OptLevelChanger {
254 SelectionDAGISel &IS;
255 CodeGenOpt::Level SavedOptLevel;
259 OptLevelChanger(SelectionDAGISel &ISel,
260 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
261 SavedOptLevel = IS.OptLevel;
262 if (NewOptLevel == SavedOptLevel)
264 IS.OptLevel = NewOptLevel;
265 IS.TM.setOptLevel(NewOptLevel);
266 SavedFastISel = IS.TM.Options.EnableFastISel;
267 if (NewOptLevel == CodeGenOpt::None)
268 IS.TM.setFastISel(true);
269 DEBUG(dbgs() << "\nChanging optimization level for Function "
270 << IS.MF->getFunction()->getName() << "\n");
271 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
272 << " ; After: -O" << NewOptLevel << "\n");
276 if (IS.OptLevel == SavedOptLevel)
278 DEBUG(dbgs() << "\nRestoring optimization level for Function "
279 << IS.MF->getFunction()->getName() << "\n");
280 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
281 << " ; After: -O" << SavedOptLevel << "\n");
282 IS.OptLevel = SavedOptLevel;
283 IS.TM.setOptLevel(SavedOptLevel);
284 IS.TM.setFastISel(SavedFastISel);
288 //===--------------------------------------------------------------------===//
289 /// createDefaultScheduler - This creates an instruction scheduler appropriate
291 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
292 CodeGenOpt::Level OptLevel) {
293 const TargetLowering *TLI = IS->TLI;
294 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
296 if (OptLevel == CodeGenOpt::None ||
297 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
298 TLI->getSchedulingPreference() == Sched::Source)
299 return createSourceListDAGScheduler(IS, OptLevel);
300 if (TLI->getSchedulingPreference() == Sched::RegPressure)
301 return createBURRListDAGScheduler(IS, OptLevel);
302 if (TLI->getSchedulingPreference() == Sched::Hybrid)
303 return createHybridListDAGScheduler(IS, OptLevel);
304 if (TLI->getSchedulingPreference() == Sched::VLIW)
305 return createVLIWDAGScheduler(IS, OptLevel);
306 assert(TLI->getSchedulingPreference() == Sched::ILP &&
307 "Unknown sched type!");
308 return createILPListDAGScheduler(IS, OptLevel);
312 // EmitInstrWithCustomInserter - This method should be implemented by targets
313 // that mark instructions with the 'usesCustomInserter' flag. These
314 // instructions are special in various ways, which require special support to
315 // insert. The specified MachineInstr is created but not inserted into any
316 // basic blocks, and this method is called to expand it into a sequence of
317 // instructions, potentially also creating new basic blocks and control flow.
318 // When new basic blocks are inserted and the edges from MBB to its successors
319 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
322 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
323 MachineBasicBlock *MBB) const {
325 dbgs() << "If a target marks an instruction with "
326 "'usesCustomInserter', it must implement "
327 "TargetLowering::EmitInstrWithCustomInserter!";
329 llvm_unreachable(nullptr);
332 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
333 SDNode *Node) const {
334 assert(!MI->hasPostISelHook() &&
335 "If a target marks an instruction with 'hasPostISelHook', "
336 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
339 //===----------------------------------------------------------------------===//
340 // SelectionDAGISel code
341 //===----------------------------------------------------------------------===//
343 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
344 CodeGenOpt::Level OL) :
345 MachineFunctionPass(ID), TM(tm),
346 FuncInfo(new FunctionLoweringInfo()),
347 CurDAG(new SelectionDAG(tm, OL)),
348 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
352 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
353 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
354 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
355 initializeTargetLibraryInfoWrapperPassPass(
356 *PassRegistry::getPassRegistry());
359 SelectionDAGISel::~SelectionDAGISel() {
365 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
366 AU.addRequired<AliasAnalysis>();
367 AU.addPreserved<AliasAnalysis>();
368 AU.addRequired<GCModuleInfo>();
369 AU.addPreserved<GCModuleInfo>();
370 AU.addRequired<TargetLibraryInfoWrapperPass>();
371 if (UseMBPI && OptLevel != CodeGenOpt::None)
372 AU.addRequired<BranchProbabilityInfo>();
373 MachineFunctionPass::getAnalysisUsage(AU);
376 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
377 /// may trap on it. In this case we have to split the edge so that the path
378 /// through the predecessor block that doesn't go to the phi block doesn't
379 /// execute the possibly trapping instruction.
381 /// This is required for correctness, so it must be done at -O0.
383 static void SplitCriticalSideEffectEdges(Function &Fn, AliasAnalysis *AA) {
384 // Loop for blocks with phi nodes.
385 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
386 PHINode *PN = dyn_cast<PHINode>(BB->begin());
390 // For each block with a PHI node, check to see if any of the input values
391 // are potentially trapping constant expressions. Constant expressions are
392 // the only potentially trapping value that can occur as the argument to a
394 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
395 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
396 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
397 if (!CE || !CE->canTrap()) continue;
399 // The only case we have to worry about is when the edge is critical.
400 // Since this block has a PHI Node, we assume it has multiple input
401 // edges: check to see if the pred has multiple successors.
402 BasicBlock *Pred = PN->getIncomingBlock(i);
403 if (Pred->getTerminator()->getNumSuccessors() == 1)
406 // Okay, we have to split this edge.
408 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
409 CriticalEdgeSplittingOptions(AA).setMergeIdenticalEdges());
415 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
416 // Do some sanity-checking on the command-line options.
417 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
418 "-fast-isel-verbose requires -fast-isel");
419 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
420 "-fast-isel-abort > 0 requires -fast-isel");
422 const Function &Fn = *mf.getFunction();
425 // Reset the target options before resetting the optimization
427 // FIXME: This is a horrible hack and should be processed via
428 // codegen looking at the optimization level explicitly when
429 // it wants to look at it.
430 TM.resetTargetOptions(Fn);
431 // Reset OptLevel to None for optnone functions.
432 CodeGenOpt::Level NewOptLevel = OptLevel;
433 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
434 NewOptLevel = CodeGenOpt::None;
435 OptLevelChanger OLC(*this, NewOptLevel);
437 TII = MF->getSubtarget().getInstrInfo();
438 TLI = MF->getSubtarget().getTargetLowering();
439 RegInfo = &MF->getRegInfo();
440 AA = &getAnalysis<AliasAnalysis>();
441 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
442 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
444 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
446 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), AA);
449 FuncInfo->set(Fn, *MF, CurDAG);
451 if (UseMBPI && OptLevel != CodeGenOpt::None)
452 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
454 FuncInfo->BPI = nullptr;
456 SDB->init(GFI, *AA, LibInfo);
458 MF->setHasInlineAsm(false);
460 SelectAllBasicBlocks(Fn);
462 // If the first basic block in the function has live ins that need to be
463 // copied into vregs, emit the copies into the top of the block before
464 // emitting the code for the block.
465 MachineBasicBlock *EntryMBB = MF->begin();
466 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
467 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
469 DenseMap<unsigned, unsigned> LiveInMap;
470 if (!FuncInfo->ArgDbgValues.empty())
471 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
472 E = RegInfo->livein_end(); LI != E; ++LI)
474 LiveInMap.insert(std::make_pair(LI->first, LI->second));
476 // Insert DBG_VALUE instructions for function arguments to the entry block.
477 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
478 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
479 bool hasFI = MI->getOperand(0).isFI();
481 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
482 if (TargetRegisterInfo::isPhysicalRegister(Reg))
483 EntryMBB->insert(EntryMBB->begin(), MI);
485 MachineInstr *Def = RegInfo->getVRegDef(Reg);
487 MachineBasicBlock::iterator InsertPos = Def;
488 // FIXME: VR def may not be in entry block.
489 Def->getParent()->insert(std::next(InsertPos), MI);
491 DEBUG(dbgs() << "Dropping debug info for dead vreg"
492 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
495 // If Reg is live-in then update debug info to track its copy in a vreg.
496 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
497 if (LDI != LiveInMap.end()) {
498 assert(!hasFI && "There's no handling of frame pointer updating here yet "
500 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
501 MachineBasicBlock::iterator InsertPos = Def;
502 const MDNode *Variable = MI->getDebugVariable();
503 const MDNode *Expr = MI->getDebugExpression();
504 DebugLoc DL = MI->getDebugLoc();
505 bool IsIndirect = MI->isIndirectDebugValue();
506 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
507 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
508 "Expected inlined-at fields to agree");
509 // Def is never a terminator here, so it is ok to increment InsertPos.
510 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
511 IsIndirect, LDI->second, Offset, Variable, Expr);
513 // If this vreg is directly copied into an exported register then
514 // that COPY instructions also need DBG_VALUE, if it is the only
515 // user of LDI->second.
516 MachineInstr *CopyUseMI = nullptr;
517 for (MachineRegisterInfo::use_instr_iterator
518 UI = RegInfo->use_instr_begin(LDI->second),
519 E = RegInfo->use_instr_end(); UI != E; ) {
520 MachineInstr *UseMI = &*(UI++);
521 if (UseMI->isDebugValue()) continue;
522 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
523 CopyUseMI = UseMI; continue;
525 // Otherwise this is another use or second copy use.
526 CopyUseMI = nullptr; break;
529 // Use MI's debug location, which describes where Variable was
530 // declared, rather than whatever is attached to CopyUseMI.
531 MachineInstr *NewMI =
532 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
533 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
534 MachineBasicBlock::iterator Pos = CopyUseMI;
535 EntryMBB->insertAfter(Pos, NewMI);
540 // Determine if there are any calls in this machine function.
541 MachineFrameInfo *MFI = MF->getFrameInfo();
542 for (const auto &MBB : *MF) {
543 if (MFI->hasCalls() && MF->hasInlineAsm())
546 for (const auto &MI : MBB) {
547 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
548 if ((MCID.isCall() && !MCID.isReturn()) ||
549 MI.isStackAligningInlineAsm()) {
550 MFI->setHasCalls(true);
552 if (MI.isInlineAsm()) {
553 MF->setHasInlineAsm(true);
558 // Determine if there is a call to setjmp in the machine function.
559 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
561 // Replace forward-declared registers with the registers containing
562 // the desired value.
563 MachineRegisterInfo &MRI = MF->getRegInfo();
564 for (DenseMap<unsigned, unsigned>::iterator
565 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
567 unsigned From = I->first;
568 unsigned To = I->second;
569 // If To is also scheduled to be replaced, find what its ultimate
572 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
576 // Make sure the new register has a sufficiently constrained register class.
577 if (TargetRegisterInfo::isVirtualRegister(From) &&
578 TargetRegisterInfo::isVirtualRegister(To))
579 MRI.constrainRegClass(To, MRI.getRegClass(From));
583 // Replacing one register with another won't touch the kill flags.
584 // We need to conservatively clear the kill flags as a kill on the old
585 // register might dominate existing uses of the new register.
586 if (!MRI.use_empty(To))
587 MRI.clearKillFlags(From);
588 MRI.replaceRegWith(From, To);
591 // Freeze the set of reserved registers now that MachineFrameInfo has been
592 // set up. All the information required by getReservedRegs() should be
594 MRI.freezeReservedRegs(*MF);
596 // Release function-specific state. SDB and CurDAG are already cleared
600 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
601 DEBUG(MF->print(dbgs()));
606 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
607 BasicBlock::const_iterator End,
609 // Lower the instructions. If a call is emitted as a tail call, cease emitting
610 // nodes for this block.
611 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
614 // Make sure the root of the DAG is up-to-date.
615 CurDAG->setRoot(SDB->getControlRoot());
616 HadTailCall = SDB->HasTailCall;
619 // Final step, emit the lowered DAG as machine code.
623 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
624 SmallPtrSet<SDNode*, 128> VisitedNodes;
625 SmallVector<SDNode*, 128> Worklist;
627 Worklist.push_back(CurDAG->getRoot().getNode());
633 SDNode *N = Worklist.pop_back_val();
635 // If we've already seen this node, ignore it.
636 if (!VisitedNodes.insert(N).second)
639 // Otherwise, add all chain operands to the worklist.
640 for (const SDValue &Op : N->op_values())
641 if (Op.getValueType() == MVT::Other)
642 Worklist.push_back(Op.getNode());
644 // If this is a CopyToReg with a vreg dest, process it.
645 if (N->getOpcode() != ISD::CopyToReg)
648 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
649 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
652 // Ignore non-scalar or non-integer values.
653 SDValue Src = N->getOperand(2);
654 EVT SrcVT = Src.getValueType();
655 if (!SrcVT.isInteger() || SrcVT.isVector())
658 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
659 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
660 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
661 } while (!Worklist.empty());
664 void SelectionDAGISel::CodeGenAndEmitDAG() {
665 std::string GroupName;
666 if (TimePassesIsEnabled)
667 GroupName = "Instruction Selection and Scheduling";
668 std::string BlockName;
669 int BlockNumber = -1;
671 bool MatchFilterBB = false; (void)MatchFilterBB;
673 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
674 FilterDAGBasicBlockName ==
675 FuncInfo->MBB->getBasicBlock()->getName().str());
678 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
679 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
683 BlockNumber = FuncInfo->MBB->getNumber();
685 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
687 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
688 << " '" << BlockName << "'\n"; CurDAG->dump());
690 if (ViewDAGCombine1 && MatchFilterBB)
691 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
693 // Run the DAG combiner in pre-legalize mode.
695 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
696 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
699 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
700 << " '" << BlockName << "'\n"; CurDAG->dump());
702 // Second step, hack on the DAG until it only uses operations and types that
703 // the target supports.
704 if (ViewLegalizeTypesDAGs && MatchFilterBB)
705 CurDAG->viewGraph("legalize-types input for " + BlockName);
709 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
710 Changed = CurDAG->LegalizeTypes();
713 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
714 << " '" << BlockName << "'\n"; CurDAG->dump());
716 CurDAG->NewNodesMustHaveLegalTypes = true;
719 if (ViewDAGCombineLT && MatchFilterBB)
720 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
722 // Run the DAG combiner in post-type-legalize mode.
724 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
725 TimePassesIsEnabled);
726 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
729 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
730 << " '" << BlockName << "'\n"; CurDAG->dump());
735 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
736 Changed = CurDAG->LegalizeVectors();
741 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
742 CurDAG->LegalizeTypes();
745 if (ViewDAGCombineLT && MatchFilterBB)
746 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
748 // Run the DAG combiner in post-type-legalize mode.
750 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
751 TimePassesIsEnabled);
752 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
755 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
756 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
759 if (ViewLegalizeDAGs && MatchFilterBB)
760 CurDAG->viewGraph("legalize input for " + BlockName);
763 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
767 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
768 << " '" << BlockName << "'\n"; CurDAG->dump());
770 if (ViewDAGCombine2 && MatchFilterBB)
771 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
773 // Run the DAG combiner in post-legalize mode.
775 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
776 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
779 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
780 << " '" << BlockName << "'\n"; CurDAG->dump());
782 if (OptLevel != CodeGenOpt::None)
783 ComputeLiveOutVRegInfo();
785 if (ViewISelDAGs && MatchFilterBB)
786 CurDAG->viewGraph("isel input for " + BlockName);
788 // Third, instruction select all of the operations to machine code, adding the
789 // code to the MachineBasicBlock.
791 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
792 DoInstructionSelection();
795 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
796 << " '" << BlockName << "'\n"; CurDAG->dump());
798 if (ViewSchedDAGs && MatchFilterBB)
799 CurDAG->viewGraph("scheduler input for " + BlockName);
801 // Schedule machine code.
802 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
804 NamedRegionTimer T("Instruction Scheduling", GroupName,
805 TimePassesIsEnabled);
806 Scheduler->Run(CurDAG, FuncInfo->MBB);
809 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
811 // Emit machine code to BB. This can change 'BB' to the last block being
813 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
815 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
817 // FuncInfo->InsertPt is passed by reference and set to the end of the
818 // scheduled instructions.
819 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
822 // If the block was split, make sure we update any references that are used to
823 // update PHI nodes later on.
824 if (FirstMBB != LastMBB)
825 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
827 // Free the scheduler state.
829 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
830 TimePassesIsEnabled);
834 // Free the SelectionDAG state, now that we're finished with it.
839 /// ISelUpdater - helper class to handle updates of the instruction selection
841 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
842 SelectionDAG::allnodes_iterator &ISelPosition;
844 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
845 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
847 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
848 /// deleted is the current ISelPosition node, update ISelPosition.
850 void NodeDeleted(SDNode *N, SDNode *E) override {
851 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
855 } // end anonymous namespace
857 void SelectionDAGISel::DoInstructionSelection() {
858 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
859 << FuncInfo->MBB->getNumber()
860 << " '" << FuncInfo->MBB->getName() << "'\n");
864 // Select target instructions for the DAG.
866 // Number all nodes with a topological order and set DAGSize.
867 DAGSize = CurDAG->AssignTopologicalOrder();
869 // Create a dummy node (which is not added to allnodes), that adds
870 // a reference to the root node, preventing it from being deleted,
871 // and tracking any changes of the root.
872 HandleSDNode Dummy(CurDAG->getRoot());
873 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
876 // Make sure that ISelPosition gets properly updated when nodes are deleted
877 // in calls made from this function.
878 ISelUpdater ISU(*CurDAG, ISelPosition);
880 // The AllNodes list is now topological-sorted. Visit the
881 // nodes by starting at the end of the list (the root of the
882 // graph) and preceding back toward the beginning (the entry
884 while (ISelPosition != CurDAG->allnodes_begin()) {
885 SDNode *Node = --ISelPosition;
886 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
887 // but there are currently some corner cases that it misses. Also, this
888 // makes it theoretically possible to disable the DAGCombiner.
889 if (Node->use_empty())
892 SDNode *ResNode = Select(Node);
894 // FIXME: This is pretty gross. 'Select' should be changed to not return
895 // anything at all and this code should be nuked with a tactical strike.
897 // If node should not be replaced, continue with the next one.
898 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
902 ReplaceUses(Node, ResNode);
905 // If after the replacement this node is not used any more,
906 // remove this dead node.
907 if (Node->use_empty()) // Don't delete EntryToken, etc.
908 CurDAG->RemoveDeadNode(Node);
911 CurDAG->setRoot(Dummy.getValue());
914 DEBUG(dbgs() << "===== Instruction selection ends:\n");
916 PostprocessISelDAG();
919 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
920 /// do other setup for EH landing-pad blocks.
921 bool SelectionDAGISel::PrepareEHLandingPad() {
922 MachineBasicBlock *MBB = FuncInfo->MBB;
924 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
926 // Add a label to mark the beginning of the landing pad. Deletion of the
927 // landing pad can thus be detected via the MachineModuleInfo.
928 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
930 // Assign the call site to the landing pad's begin label.
931 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
933 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
934 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
937 // If this is an MSVC-style personality function, we need to split the landing
938 // pad into several BBs.
939 const BasicBlock *LLVMBB = MBB->getBasicBlock();
940 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
941 MF->getMMI().addPersonality(MBB, cast<Function>(LPadInst->getParent()
944 ->stripPointerCasts()));
945 EHPersonality Personality = MF->getMMI().getPersonalityType();
947 if (isMSVCEHPersonality(Personality)) {
948 SmallVector<MachineBasicBlock *, 4> ClauseBBs;
949 const IntrinsicInst *ActionsCall =
950 dyn_cast<IntrinsicInst>(LLVMBB->getFirstInsertionPt());
951 // Get all invoke BBs that unwind to this landingpad.
952 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
954 if (ActionsCall && ActionsCall->getIntrinsicID() == Intrinsic::eh_actions) {
955 // If this is a call to llvm.eh.actions followed by indirectbr, then we've
956 // run WinEHPrepare, and we should remove this block from the machine CFG.
957 // Mark the targets of the indirectbr as landingpads instead.
958 for (const BasicBlock *LLVMSucc : successors(LLVMBB)) {
959 MachineBasicBlock *ClauseBB = FuncInfo->MBBMap[LLVMSucc];
960 // Add the edge from the invoke to the clause.
961 for (MachineBasicBlock *InvokeBB : InvokeBBs)
962 InvokeBB->addSuccessor(ClauseBB);
964 // Mark the clause as a landing pad or MI passes will delete it.
965 ClauseBB->setIsLandingPad();
969 // Remove the edge from the invoke to the lpad.
970 for (MachineBasicBlock *InvokeBB : InvokeBBs)
971 InvokeBB->removeSuccessor(MBB);
973 // Don't select instructions for the landingpad.
977 // Mark exception register as live in.
978 if (unsigned Reg = TLI->getExceptionPointerRegister())
979 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
981 // Mark exception selector register as live in.
982 if (unsigned Reg = TLI->getExceptionSelectorRegister())
983 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
988 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
989 /// side-effect free and is either dead or folded into a generated instruction.
990 /// Return false if it needs to be emitted.
991 static bool isFoldedOrDeadInstruction(const Instruction *I,
992 FunctionLoweringInfo *FuncInfo) {
993 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
994 !isa<TerminatorInst>(I) && // Terminators aren't folded.
995 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
996 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
997 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1001 // Collect per Instruction statistics for fast-isel misses. Only those
1002 // instructions that cause the bail are accounted for. It does not account for
1003 // instructions higher in the block. Thus, summing the per instructions stats
1004 // will not add up to what is reported by NumFastIselFailures.
1005 static void collectFailStats(const Instruction *I) {
1006 switch (I->getOpcode()) {
1007 default: assert (0 && "<Invalid operator> ");
1010 case Instruction::Ret: NumFastIselFailRet++; return;
1011 case Instruction::Br: NumFastIselFailBr++; return;
1012 case Instruction::Switch: NumFastIselFailSwitch++; return;
1013 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1014 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1015 case Instruction::Resume: NumFastIselFailResume++; return;
1016 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1018 // Standard binary operators...
1019 case Instruction::Add: NumFastIselFailAdd++; return;
1020 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1021 case Instruction::Sub: NumFastIselFailSub++; return;
1022 case Instruction::FSub: NumFastIselFailFSub++; return;
1023 case Instruction::Mul: NumFastIselFailMul++; return;
1024 case Instruction::FMul: NumFastIselFailFMul++; return;
1025 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1026 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1027 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1028 case Instruction::URem: NumFastIselFailURem++; return;
1029 case Instruction::SRem: NumFastIselFailSRem++; return;
1030 case Instruction::FRem: NumFastIselFailFRem++; return;
1032 // Logical operators...
1033 case Instruction::And: NumFastIselFailAnd++; return;
1034 case Instruction::Or: NumFastIselFailOr++; return;
1035 case Instruction::Xor: NumFastIselFailXor++; return;
1037 // Memory instructions...
1038 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1039 case Instruction::Load: NumFastIselFailLoad++; return;
1040 case Instruction::Store: NumFastIselFailStore++; return;
1041 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1042 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1043 case Instruction::Fence: NumFastIselFailFence++; return;
1044 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1046 // Convert instructions...
1047 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1048 case Instruction::ZExt: NumFastIselFailZExt++; return;
1049 case Instruction::SExt: NumFastIselFailSExt++; return;
1050 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1051 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1052 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1053 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1054 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1055 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1056 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1057 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1058 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1060 // Other instructions...
1061 case Instruction::ICmp: NumFastIselFailICmp++; return;
1062 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1063 case Instruction::PHI: NumFastIselFailPHI++; return;
1064 case Instruction::Select: NumFastIselFailSelect++; return;
1065 case Instruction::Call: {
1066 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1067 switch (Intrinsic->getIntrinsicID()) {
1069 NumFastIselFailIntrinsicCall++; return;
1070 case Intrinsic::sadd_with_overflow:
1071 NumFastIselFailSAddWithOverflow++; return;
1072 case Intrinsic::uadd_with_overflow:
1073 NumFastIselFailUAddWithOverflow++; return;
1074 case Intrinsic::ssub_with_overflow:
1075 NumFastIselFailSSubWithOverflow++; return;
1076 case Intrinsic::usub_with_overflow:
1077 NumFastIselFailUSubWithOverflow++; return;
1078 case Intrinsic::smul_with_overflow:
1079 NumFastIselFailSMulWithOverflow++; return;
1080 case Intrinsic::umul_with_overflow:
1081 NumFastIselFailUMulWithOverflow++; return;
1082 case Intrinsic::frameaddress:
1083 NumFastIselFailFrameaddress++; return;
1084 case Intrinsic::sqrt:
1085 NumFastIselFailSqrt++; return;
1086 case Intrinsic::experimental_stackmap:
1087 NumFastIselFailStackMap++; return;
1088 case Intrinsic::experimental_patchpoint_void: // fall-through
1089 case Intrinsic::experimental_patchpoint_i64:
1090 NumFastIselFailPatchPoint++; return;
1093 NumFastIselFailCall++;
1096 case Instruction::Shl: NumFastIselFailShl++; return;
1097 case Instruction::LShr: NumFastIselFailLShr++; return;
1098 case Instruction::AShr: NumFastIselFailAShr++; return;
1099 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1100 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1101 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1102 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1103 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1104 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1105 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1110 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1111 // Initialize the Fast-ISel state, if needed.
1112 FastISel *FastIS = nullptr;
1113 if (TM.Options.EnableFastISel)
1114 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1116 // Iterate over all basic blocks in the function.
1117 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1118 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1119 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1120 const BasicBlock *LLVMBB = *I;
1122 if (OptLevel != CodeGenOpt::None) {
1123 bool AllPredsVisited = true;
1124 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1126 if (!FuncInfo->VisitedBBs.count(*PI)) {
1127 AllPredsVisited = false;
1132 if (AllPredsVisited) {
1133 for (BasicBlock::const_iterator I = LLVMBB->begin();
1134 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1135 FuncInfo->ComputePHILiveOutRegInfo(PN);
1137 for (BasicBlock::const_iterator I = LLVMBB->begin();
1138 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1139 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1142 FuncInfo->VisitedBBs.insert(LLVMBB);
1145 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1146 BasicBlock::const_iterator const End = LLVMBB->end();
1147 BasicBlock::const_iterator BI = End;
1149 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1150 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1152 // Setup an EH landing-pad block.
1153 FuncInfo->ExceptionPointerVirtReg = 0;
1154 FuncInfo->ExceptionSelectorVirtReg = 0;
1155 if (LLVMBB->isLandingPad())
1156 if (!PrepareEHLandingPad())
1159 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1161 FastIS->startNewBlock();
1163 // Emit code for any incoming arguments. This must happen before
1164 // beginning FastISel on the entry block.
1165 if (LLVMBB == &Fn.getEntryBlock()) {
1168 // Lower any arguments needed in this block if this is the entry block.
1169 if (!FastIS->lowerArguments()) {
1170 // Fast isel failed to lower these arguments
1171 ++NumFastIselFailLowerArguments;
1172 if (EnableFastISelAbort > 1)
1173 report_fatal_error("FastISel didn't lower all arguments");
1175 // Use SelectionDAG argument lowering
1177 CurDAG->setRoot(SDB->getControlRoot());
1179 CodeGenAndEmitDAG();
1182 // If we inserted any instructions at the beginning, make a note of
1183 // where they are, so we can be sure to emit subsequent instructions
1185 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1186 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1188 FastIS->setLastLocalValue(nullptr);
1191 unsigned NumFastIselRemaining = std::distance(Begin, End);
1192 // Do FastISel on as many instructions as possible.
1193 for (; BI != Begin; --BI) {
1194 const Instruction *Inst = std::prev(BI);
1196 // If we no longer require this instruction, skip it.
1197 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1198 --NumFastIselRemaining;
1202 // Bottom-up: reset the insert pos at the top, after any local-value
1204 FastIS->recomputeInsertPt();
1206 // Try to select the instruction with FastISel.
1207 if (FastIS->selectInstruction(Inst)) {
1208 --NumFastIselRemaining;
1209 ++NumFastIselSuccess;
1210 // If fast isel succeeded, skip over all the folded instructions, and
1211 // then see if there is a load right before the selected instructions.
1212 // Try to fold the load if so.
1213 const Instruction *BeforeInst = Inst;
1214 while (BeforeInst != Begin) {
1215 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1216 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1219 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1220 BeforeInst->hasOneUse() &&
1221 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1222 // If we succeeded, don't re-select the load.
1223 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1224 --NumFastIselRemaining;
1225 ++NumFastIselSuccess;
1231 if (EnableFastISelVerbose2)
1232 collectFailStats(Inst);
1235 // Then handle certain instructions as single-LLVM-Instruction blocks.
1236 if (isa<CallInst>(Inst)) {
1238 if (EnableFastISelVerbose || EnableFastISelAbort) {
1239 dbgs() << "FastISel missed call: ";
1242 if (EnableFastISelAbort > 2)
1243 // FastISel selector couldn't handle something and bailed.
1244 // For the purpose of debugging, just abort.
1245 report_fatal_error("FastISel didn't select the entire block");
1247 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1248 unsigned &R = FuncInfo->ValueMap[Inst];
1250 R = FuncInfo->CreateRegs(Inst->getType());
1253 bool HadTailCall = false;
1254 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1255 SelectBasicBlock(Inst, BI, HadTailCall);
1257 // If the call was emitted as a tail call, we're done with the block.
1258 // We also need to delete any previously emitted instructions.
1260 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1265 // Recompute NumFastIselRemaining as Selection DAG instruction
1266 // selection may have handled the call, input args, etc.
1267 unsigned RemainingNow = std::distance(Begin, BI);
1268 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1269 NumFastIselRemaining = RemainingNow;
1273 bool ShouldAbort = EnableFastISelAbort;
1274 if (EnableFastISelVerbose || EnableFastISelAbort) {
1275 if (isa<TerminatorInst>(Inst)) {
1276 // Use a different message for terminator misses.
1277 dbgs() << "FastISel missed terminator: ";
1278 // Don't abort unless for terminator unless the level is really high
1279 ShouldAbort = (EnableFastISelAbort > 2);
1281 dbgs() << "FastISel miss: ";
1286 // FastISel selector couldn't handle something and bailed.
1287 // For the purpose of debugging, just abort.
1288 report_fatal_error("FastISel didn't select the entire block");
1290 NumFastIselFailures += NumFastIselRemaining;
1294 FastIS->recomputeInsertPt();
1296 // Lower any arguments needed in this block if this is the entry block.
1297 if (LLVMBB == &Fn.getEntryBlock()) {
1306 ++NumFastIselBlocks;
1309 // Run SelectionDAG instruction selection on the remainder of the block
1310 // not handled by FastISel. If FastISel is not run, this is the entire
1313 SelectBasicBlock(Begin, BI, HadTailCall);
1317 FuncInfo->PHINodesToUpdate.clear();
1321 SDB->clearDanglingDebugInfo();
1322 SDB->SPDescriptor.resetPerFunctionState();
1325 /// Given that the input MI is before a partial terminator sequence TSeq, return
1326 /// true if M + TSeq also a partial terminator sequence.
1328 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1329 /// lowering copy vregs into physical registers, which are then passed into
1330 /// terminator instructors so we can satisfy ABI constraints. A partial
1331 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1332 /// may be the whole terminator sequence).
1333 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1334 // If we do not have a copy or an implicit def, we return true if and only if
1335 // MI is a debug value.
1336 if (!MI->isCopy() && !MI->isImplicitDef())
1337 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1338 // physical registers if there is debug info associated with the terminator
1339 // of our mbb. We want to include said debug info in our terminator
1340 // sequence, so we return true in that case.
1341 return MI->isDebugValue();
1343 // We have left the terminator sequence if we are not doing one of the
1346 // 1. Copying a vreg into a physical register.
1347 // 2. Copying a vreg into a vreg.
1348 // 3. Defining a register via an implicit def.
1350 // OPI should always be a register definition...
1351 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1352 if (!OPI->isReg() || !OPI->isDef())
1355 // Defining any register via an implicit def is always ok.
1356 if (MI->isImplicitDef())
1359 // Grab the copy source...
1360 MachineInstr::const_mop_iterator OPI2 = OPI;
1362 assert(OPI2 != MI->operands_end()
1363 && "Should have a copy implying we should have 2 arguments.");
1365 // Make sure that the copy dest is not a vreg when the copy source is a
1366 // physical register.
1367 if (!OPI2->isReg() ||
1368 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1369 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1375 /// Find the split point at which to splice the end of BB into its success stack
1376 /// protector check machine basic block.
1378 /// On many platforms, due to ABI constraints, terminators, even before register
1379 /// allocation, use physical registers. This creates an issue for us since
1380 /// physical registers at this point can not travel across basic
1381 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1382 /// when they enter functions and moves them through a sequence of copies back
1383 /// into the physical registers right before the terminator creating a
1384 /// ``Terminator Sequence''. This function is searching for the beginning of the
1385 /// terminator sequence so that we can ensure that we splice off not just the
1386 /// terminator, but additionally the copies that move the vregs into the
1387 /// physical registers.
1388 static MachineBasicBlock::iterator
1389 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1390 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1392 if (SplitPoint == BB->begin())
1395 MachineBasicBlock::iterator Start = BB->begin();
1396 MachineBasicBlock::iterator Previous = SplitPoint;
1399 while (MIIsInTerminatorSequence(Previous)) {
1400 SplitPoint = Previous;
1401 if (Previous == Start)
1410 SelectionDAGISel::FinishBasicBlock() {
1412 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1413 << FuncInfo->PHINodesToUpdate.size() << "\n";
1414 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1415 dbgs() << "Node " << i << " : ("
1416 << FuncInfo->PHINodesToUpdate[i].first
1417 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1419 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1420 // PHI nodes in successors.
1421 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1422 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1423 assert(PHI->isPHI() &&
1424 "This is not a machine PHI node that we are updating!");
1425 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1427 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1430 // Handle stack protector.
1431 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1432 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1433 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1435 // Find the split point to split the parent mbb. At the same time copy all
1436 // physical registers used in the tail of parent mbb into virtual registers
1437 // before the split point and back into physical registers after the split
1438 // point. This prevents us needing to deal with Live-ins and many other
1439 // register allocation issues caused by us splitting the parent mbb. The
1440 // register allocator will clean up said virtual copies later on.
1441 MachineBasicBlock::iterator SplitPoint =
1442 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1444 // Splice the terminator of ParentMBB into SuccessMBB.
1445 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1449 // Add compare/jump on neq/jump to the parent BB.
1450 FuncInfo->MBB = ParentMBB;
1451 FuncInfo->InsertPt = ParentMBB->end();
1452 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1453 CurDAG->setRoot(SDB->getRoot());
1455 CodeGenAndEmitDAG();
1457 // CodeGen Failure MBB if we have not codegened it yet.
1458 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1459 if (!FailureMBB->size()) {
1460 FuncInfo->MBB = FailureMBB;
1461 FuncInfo->InsertPt = FailureMBB->end();
1462 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1463 CurDAG->setRoot(SDB->getRoot());
1465 CodeGenAndEmitDAG();
1468 // Clear the Per-BB State.
1469 SDB->SPDescriptor.resetPerBBState();
1472 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1473 // Lower header first, if it wasn't already lowered
1474 if (!SDB->BitTestCases[i].Emitted) {
1475 // Set the current basic block to the mbb we wish to insert the code into
1476 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1477 FuncInfo->InsertPt = FuncInfo->MBB->end();
1479 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1480 CurDAG->setRoot(SDB->getRoot());
1482 CodeGenAndEmitDAG();
1485 uint32_t UnhandledWeight = 0;
1486 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1487 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1489 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1490 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1491 // Set the current basic block to the mbb we wish to insert the code into
1492 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1493 FuncInfo->InsertPt = FuncInfo->MBB->end();
1496 SDB->visitBitTestCase(SDB->BitTestCases[i],
1497 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1499 SDB->BitTestCases[i].Reg,
1500 SDB->BitTestCases[i].Cases[j],
1503 SDB->visitBitTestCase(SDB->BitTestCases[i],
1504 SDB->BitTestCases[i].Default,
1506 SDB->BitTestCases[i].Reg,
1507 SDB->BitTestCases[i].Cases[j],
1511 CurDAG->setRoot(SDB->getRoot());
1513 CodeGenAndEmitDAG();
1517 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1519 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1520 MachineBasicBlock *PHIBB = PHI->getParent();
1521 assert(PHI->isPHI() &&
1522 "This is not a machine PHI node that we are updating!");
1523 // This is "default" BB. We have two jumps to it. From "header" BB and
1524 // from last "case" BB.
1525 if (PHIBB == SDB->BitTestCases[i].Default)
1526 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1527 .addMBB(SDB->BitTestCases[i].Parent)
1528 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1529 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1530 // One of "cases" BB.
1531 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1533 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1534 if (cBB->isSuccessor(PHIBB))
1535 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1539 SDB->BitTestCases.clear();
1541 // If the JumpTable record is filled in, then we need to emit a jump table.
1542 // Updating the PHI nodes is tricky in this case, since we need to determine
1543 // whether the PHI is a successor of the range check MBB or the jump table MBB
1544 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1545 // Lower header first, if it wasn't already lowered
1546 if (!SDB->JTCases[i].first.Emitted) {
1547 // Set the current basic block to the mbb we wish to insert the code into
1548 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1549 FuncInfo->InsertPt = FuncInfo->MBB->end();
1551 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1553 CurDAG->setRoot(SDB->getRoot());
1555 CodeGenAndEmitDAG();
1558 // Set the current basic block to the mbb we wish to insert the code into
1559 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1560 FuncInfo->InsertPt = FuncInfo->MBB->end();
1562 SDB->visitJumpTable(SDB->JTCases[i].second);
1563 CurDAG->setRoot(SDB->getRoot());
1565 CodeGenAndEmitDAG();
1568 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1570 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1571 MachineBasicBlock *PHIBB = PHI->getParent();
1572 assert(PHI->isPHI() &&
1573 "This is not a machine PHI node that we are updating!");
1574 // "default" BB. We can go there only from header BB.
1575 if (PHIBB == SDB->JTCases[i].second.Default)
1576 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1577 .addMBB(SDB->JTCases[i].first.HeaderBB);
1578 // JT BB. Just iterate over successors here
1579 if (FuncInfo->MBB->isSuccessor(PHIBB))
1580 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1583 SDB->JTCases.clear();
1585 // If we generated any switch lowering information, build and codegen any
1586 // additional DAGs necessary.
1587 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1588 // Set the current basic block to the mbb we wish to insert the code into
1589 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1590 FuncInfo->InsertPt = FuncInfo->MBB->end();
1592 // Determine the unique successors.
1593 SmallVector<MachineBasicBlock *, 2> Succs;
1594 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1595 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1596 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1598 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1599 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1600 CurDAG->setRoot(SDB->getRoot());
1602 CodeGenAndEmitDAG();
1604 // Remember the last block, now that any splitting is done, for use in
1605 // populating PHI nodes in successors.
1606 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1608 // Handle any PHI nodes in successors of this chunk, as if we were coming
1609 // from the original BB before switch expansion. Note that PHI nodes can
1610 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1611 // handle them the right number of times.
1612 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1613 FuncInfo->MBB = Succs[i];
1614 FuncInfo->InsertPt = FuncInfo->MBB->end();
1615 // FuncInfo->MBB may have been removed from the CFG if a branch was
1617 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1618 for (MachineBasicBlock::iterator
1619 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1620 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1621 MachineInstrBuilder PHI(*MF, MBBI);
1622 // This value for this PHI node is recorded in PHINodesToUpdate.
1623 for (unsigned pn = 0; ; ++pn) {
1624 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1625 "Didn't find PHI entry!");
1626 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1627 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1635 SDB->SwitchCases.clear();
1639 /// Create the scheduler. If a specific scheduler was specified
1640 /// via the SchedulerRegistry, use it, otherwise select the
1641 /// one preferred by the target.
1643 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1644 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1648 RegisterScheduler::setDefault(Ctor);
1651 return Ctor(this, OptLevel);
1654 //===----------------------------------------------------------------------===//
1655 // Helper functions used by the generated instruction selector.
1656 //===----------------------------------------------------------------------===//
1657 // Calls to these methods are generated by tblgen.
1659 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1660 /// the dag combiner simplified the 255, we still want to match. RHS is the
1661 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1662 /// specified in the .td file (e.g. 255).
1663 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1664 int64_t DesiredMaskS) const {
1665 const APInt &ActualMask = RHS->getAPIntValue();
1666 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1668 // If the actual mask exactly matches, success!
1669 if (ActualMask == DesiredMask)
1672 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1673 if (ActualMask.intersects(~DesiredMask))
1676 // Otherwise, the DAG Combiner may have proven that the value coming in is
1677 // either already zero or is not demanded. Check for known zero input bits.
1678 APInt NeededMask = DesiredMask & ~ActualMask;
1679 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1682 // TODO: check to see if missing bits are just not demanded.
1684 // Otherwise, this pattern doesn't match.
1688 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1689 /// the dag combiner simplified the 255, we still want to match. RHS is the
1690 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1691 /// specified in the .td file (e.g. 255).
1692 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1693 int64_t DesiredMaskS) const {
1694 const APInt &ActualMask = RHS->getAPIntValue();
1695 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1697 // If the actual mask exactly matches, success!
1698 if (ActualMask == DesiredMask)
1701 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1702 if (ActualMask.intersects(~DesiredMask))
1705 // Otherwise, the DAG Combiner may have proven that the value coming in is
1706 // either already zero or is not demanded. Check for known zero input bits.
1707 APInt NeededMask = DesiredMask & ~ActualMask;
1709 APInt KnownZero, KnownOne;
1710 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1712 // If all the missing bits in the or are already known to be set, match!
1713 if ((NeededMask & KnownOne) == NeededMask)
1716 // TODO: check to see if missing bits are just not demanded.
1718 // Otherwise, this pattern doesn't match.
1722 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1723 /// by tblgen. Others should not call it.
1724 void SelectionDAGISel::
1725 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL) {
1726 std::vector<SDValue> InOps;
1727 std::swap(InOps, Ops);
1729 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1730 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1731 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1732 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1734 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1735 if (InOps[e-1].getValueType() == MVT::Glue)
1736 --e; // Don't process a glue operand if it is here.
1739 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1740 if (!InlineAsm::isMemKind(Flags)) {
1741 // Just skip over this operand, copying the operands verbatim.
1742 Ops.insert(Ops.end(), InOps.begin()+i,
1743 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1744 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1746 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1747 "Memory operand with multiple values?");
1749 unsigned TiedToOperand;
1750 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1751 // We need the constraint ID from the operand this is tied to.
1752 unsigned CurOp = InlineAsm::Op_FirstOperand;
1753 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1754 for (; TiedToOperand; --TiedToOperand) {
1755 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1756 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1760 // Otherwise, this is a memory operand. Ask the target to select it.
1761 std::vector<SDValue> SelOps;
1762 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1763 InlineAsm::getMemoryConstraintID(Flags),
1765 report_fatal_error("Could not match memory address. Inline asm"
1768 // Add this to the output node.
1770 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1771 Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
1772 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1777 // Add the glue input back if present.
1778 if (e != InOps.size())
1779 Ops.push_back(InOps.back());
1782 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1785 static SDNode *findGlueUse(SDNode *N) {
1786 unsigned FlagResNo = N->getNumValues()-1;
1787 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1788 SDUse &Use = I.getUse();
1789 if (Use.getResNo() == FlagResNo)
1790 return Use.getUser();
1795 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1796 /// This function recursively traverses up the operand chain, ignoring
1798 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1799 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1800 bool IgnoreChains) {
1801 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1802 // greater than all of its (recursive) operands. If we scan to a point where
1803 // 'use' is smaller than the node we're scanning for, then we know we will
1806 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1807 // happen because we scan down to newly selected nodes in the case of glue
1809 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1812 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1813 // won't fail if we scan it again.
1814 if (!Visited.insert(Use).second)
1817 for (const SDValue &Op : Use->op_values()) {
1818 // Ignore chain uses, they are validated by HandleMergeInputChains.
1819 if (Op.getValueType() == MVT::Other && IgnoreChains)
1822 SDNode *N = Op.getNode();
1824 if (Use == ImmedUse || Use == Root)
1825 continue; // We are not looking for immediate use.
1830 // Traverse up the operand chain.
1831 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1837 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1838 /// operand node N of U during instruction selection that starts at Root.
1839 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1840 SDNode *Root) const {
1841 if (OptLevel == CodeGenOpt::None) return false;
1842 return N.hasOneUse();
1845 /// IsLegalToFold - Returns true if the specific operand node N of
1846 /// U can be folded during instruction selection that starts at Root.
1847 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1848 CodeGenOpt::Level OptLevel,
1849 bool IgnoreChains) {
1850 if (OptLevel == CodeGenOpt::None) return false;
1852 // If Root use can somehow reach N through a path that that doesn't contain
1853 // U then folding N would create a cycle. e.g. In the following
1854 // diagram, Root can reach N through X. If N is folded into into Root, then
1855 // X is both a predecessor and a successor of U.
1866 // * indicates nodes to be folded together.
1868 // If Root produces glue, then it gets (even more) interesting. Since it
1869 // will be "glued" together with its glue use in the scheduler, we need to
1870 // check if it might reach N.
1889 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1890 // (call it Fold), then X is a predecessor of GU and a successor of
1891 // Fold. But since Fold and GU are glued together, this will create
1892 // a cycle in the scheduling graph.
1894 // If the node has glue, walk down the graph to the "lowest" node in the
1896 EVT VT = Root->getValueType(Root->getNumValues()-1);
1897 while (VT == MVT::Glue) {
1898 SDNode *GU = findGlueUse(Root);
1902 VT = Root->getValueType(Root->getNumValues()-1);
1904 // If our query node has a glue result with a use, we've walked up it. If
1905 // the user (which has already been selected) has a chain or indirectly uses
1906 // the chain, our WalkChainUsers predicate will not consider it. Because of
1907 // this, we cannot ignore chains in this predicate.
1908 IgnoreChains = false;
1912 SmallPtrSet<SDNode*, 16> Visited;
1913 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1916 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1919 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1920 SelectInlineAsmMemoryOperands(Ops, DL);
1922 const EVT VTs[] = {MVT::Other, MVT::Glue};
1923 SDValue New = CurDAG->getNode(ISD::INLINEASM, DL, VTs, Ops);
1925 return New.getNode();
1929 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1931 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1932 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1934 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
1935 SDValue New = CurDAG->getCopyFromReg(
1936 Op->getOperand(0), dl, Reg, Op->getValueType(0));
1938 return New.getNode();
1942 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1944 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1945 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1946 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1947 Op->getOperand(2).getValueType());
1948 SDValue New = CurDAG->getCopyToReg(
1949 Op->getOperand(0), dl, Reg, Op->getOperand(2));
1951 return New.getNode();
1956 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1957 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1960 /// GetVBR - decode a vbr encoding whose top bit is set.
1961 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1962 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1963 assert(Val >= 128 && "Not a VBR");
1964 Val &= 127; // Remove first vbr bit.
1969 NextBits = MatcherTable[Idx++];
1970 Val |= (NextBits&127) << Shift;
1972 } while (NextBits & 128);
1978 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1979 /// interior glue and chain results to use the new glue and chain results.
1980 void SelectionDAGISel::
1981 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1982 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1984 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1985 bool isMorphNodeTo) {
1986 SmallVector<SDNode*, 4> NowDeadNodes;
1988 // Now that all the normal results are replaced, we replace the chain and
1989 // glue results if present.
1990 if (!ChainNodesMatched.empty()) {
1991 assert(InputChain.getNode() &&
1992 "Matched input chains but didn't produce a chain");
1993 // Loop over all of the nodes we matched that produced a chain result.
1994 // Replace all the chain results with the final chain we ended up with.
1995 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1996 SDNode *ChainNode = ChainNodesMatched[i];
1998 // If this node was already deleted, don't look at it.
1999 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2002 // Don't replace the results of the root node if we're doing a
2004 if (ChainNode == NodeToMatch && isMorphNodeTo)
2007 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2008 if (ChainVal.getValueType() == MVT::Glue)
2009 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2010 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2011 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2013 // If the node became dead and we haven't already seen it, delete it.
2014 if (ChainNode->use_empty() &&
2015 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2016 NowDeadNodes.push_back(ChainNode);
2020 // If the result produces glue, update any glue results in the matched
2021 // pattern with the glue result.
2022 if (InputGlue.getNode()) {
2023 // Handle any interior nodes explicitly marked.
2024 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2025 SDNode *FRN = GlueResultNodesMatched[i];
2027 // If this node was already deleted, don't look at it.
2028 if (FRN->getOpcode() == ISD::DELETED_NODE)
2031 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2032 "Doesn't have a glue result");
2033 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2036 // If the node became dead and we haven't already seen it, delete it.
2037 if (FRN->use_empty() &&
2038 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2039 NowDeadNodes.push_back(FRN);
2043 if (!NowDeadNodes.empty())
2044 CurDAG->RemoveDeadNodes(NowDeadNodes);
2046 DEBUG(dbgs() << "ISEL: Match complete!\n");
2052 CR_LeadsToInteriorNode
2055 /// WalkChainUsers - Walk down the users of the specified chained node that is
2056 /// part of the pattern we're matching, looking at all of the users we find.
2057 /// This determines whether something is an interior node, whether we have a
2058 /// non-pattern node in between two pattern nodes (which prevent folding because
2059 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2060 /// between pattern nodes (in which case the TF becomes part of the pattern).
2062 /// The walk we do here is guaranteed to be small because we quickly get down to
2063 /// already selected nodes "below" us.
2065 WalkChainUsers(const SDNode *ChainedNode,
2066 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2067 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2068 ChainResult Result = CR_Simple;
2070 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2071 E = ChainedNode->use_end(); UI != E; ++UI) {
2072 // Make sure the use is of the chain, not some other value we produce.
2073 if (UI.getUse().getValueType() != MVT::Other) continue;
2077 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2080 // If we see an already-selected machine node, then we've gone beyond the
2081 // pattern that we're selecting down into the already selected chunk of the
2083 unsigned UserOpcode = User->getOpcode();
2084 if (User->isMachineOpcode() ||
2085 UserOpcode == ISD::CopyToReg ||
2086 UserOpcode == ISD::CopyFromReg ||
2087 UserOpcode == ISD::INLINEASM ||
2088 UserOpcode == ISD::EH_LABEL ||
2089 UserOpcode == ISD::LIFETIME_START ||
2090 UserOpcode == ISD::LIFETIME_END) {
2091 // If their node ID got reset to -1 then they've already been selected.
2092 // Treat them like a MachineOpcode.
2093 if (User->getNodeId() == -1)
2097 // If we have a TokenFactor, we handle it specially.
2098 if (User->getOpcode() != ISD::TokenFactor) {
2099 // If the node isn't a token factor and isn't part of our pattern, then it
2100 // must be a random chained node in between two nodes we're selecting.
2101 // This happens when we have something like:
2106 // Because we structurally match the load/store as a read/modify/write,
2107 // but the call is chained between them. We cannot fold in this case
2108 // because it would induce a cycle in the graph.
2109 if (!std::count(ChainedNodesInPattern.begin(),
2110 ChainedNodesInPattern.end(), User))
2111 return CR_InducesCycle;
2113 // Otherwise we found a node that is part of our pattern. For example in:
2117 // This would happen when we're scanning down from the load and see the
2118 // store as a user. Record that there is a use of ChainedNode that is
2119 // part of the pattern and keep scanning uses.
2120 Result = CR_LeadsToInteriorNode;
2121 InteriorChainedNodes.push_back(User);
2125 // If we found a TokenFactor, there are two cases to consider: first if the
2126 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2127 // uses of the TF are in our pattern) we just want to ignore it. Second,
2128 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2134 // | \ DAG's like cheese
2137 // [TokenFactor] [Op]
2144 // In this case, the TokenFactor becomes part of our match and we rewrite it
2145 // as a new TokenFactor.
2147 // To distinguish these two cases, do a recursive walk down the uses.
2148 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2150 // If the uses of the TokenFactor are just already-selected nodes, ignore
2151 // it, it is "below" our pattern.
2153 case CR_InducesCycle:
2154 // If the uses of the TokenFactor lead to nodes that are not part of our
2155 // pattern that are not selected, folding would turn this into a cycle,
2157 return CR_InducesCycle;
2158 case CR_LeadsToInteriorNode:
2159 break; // Otherwise, keep processing.
2162 // Okay, we know we're in the interesting interior case. The TokenFactor
2163 // is now going to be considered part of the pattern so that we rewrite its
2164 // uses (it may have uses that are not part of the pattern) with the
2165 // ultimate chain result of the generated code. We will also add its chain
2166 // inputs as inputs to the ultimate TokenFactor we create.
2167 Result = CR_LeadsToInteriorNode;
2168 ChainedNodesInPattern.push_back(User);
2169 InteriorChainedNodes.push_back(User);
2176 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2177 /// operation for when the pattern matched at least one node with a chains. The
2178 /// input vector contains a list of all of the chained nodes that we match. We
2179 /// must determine if this is a valid thing to cover (i.e. matching it won't
2180 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2181 /// be used as the input node chain for the generated nodes.
2183 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2184 SelectionDAG *CurDAG) {
2185 // Walk all of the chained nodes we've matched, recursively scanning down the
2186 // users of the chain result. This adds any TokenFactor nodes that are caught
2187 // in between chained nodes to the chained and interior nodes list.
2188 SmallVector<SDNode*, 3> InteriorChainedNodes;
2189 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2190 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2191 InteriorChainedNodes) == CR_InducesCycle)
2192 return SDValue(); // Would induce a cycle.
2195 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2196 // that we are interested in. Form our input TokenFactor node.
2197 SmallVector<SDValue, 3> InputChains;
2198 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2199 // Add the input chain of this node to the InputChains list (which will be
2200 // the operands of the generated TokenFactor) if it's not an interior node.
2201 SDNode *N = ChainNodesMatched[i];
2202 if (N->getOpcode() != ISD::TokenFactor) {
2203 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2206 // Otherwise, add the input chain.
2207 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2208 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2209 InputChains.push_back(InChain);
2213 // If we have a token factor, we want to add all inputs of the token factor
2214 // that are not part of the pattern we're matching.
2215 for (const SDValue &Op : N->op_values()) {
2216 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2218 InputChains.push_back(Op);
2222 if (InputChains.size() == 1)
2223 return InputChains[0];
2224 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2225 MVT::Other, InputChains);
2228 /// MorphNode - Handle morphing a node in place for the selector.
2229 SDNode *SelectionDAGISel::
2230 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2231 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2232 // It is possible we're using MorphNodeTo to replace a node with no
2233 // normal results with one that has a normal result (or we could be
2234 // adding a chain) and the input could have glue and chains as well.
2235 // In this case we need to shift the operands down.
2236 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2237 // than the old isel though.
2238 int OldGlueResultNo = -1, OldChainResultNo = -1;
2240 unsigned NTMNumResults = Node->getNumValues();
2241 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2242 OldGlueResultNo = NTMNumResults-1;
2243 if (NTMNumResults != 1 &&
2244 Node->getValueType(NTMNumResults-2) == MVT::Other)
2245 OldChainResultNo = NTMNumResults-2;
2246 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2247 OldChainResultNo = NTMNumResults-1;
2249 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2250 // that this deletes operands of the old node that become dead.
2251 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2253 // MorphNodeTo can operate in two ways: if an existing node with the
2254 // specified operands exists, it can just return it. Otherwise, it
2255 // updates the node in place to have the requested operands.
2257 // If we updated the node in place, reset the node ID. To the isel,
2258 // this should be just like a newly allocated machine node.
2262 unsigned ResNumResults = Res->getNumValues();
2263 // Move the glue if needed.
2264 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2265 (unsigned)OldGlueResultNo != ResNumResults-1)
2266 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2267 SDValue(Res, ResNumResults-1));
2269 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2272 // Move the chain reference if needed.
2273 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2274 (unsigned)OldChainResultNo != ResNumResults-1)
2275 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2276 SDValue(Res, ResNumResults-1));
2278 // Otherwise, no replacement happened because the node already exists. Replace
2279 // Uses of the old node with the new one.
2281 CurDAG->ReplaceAllUsesWith(Node, Res);
2286 /// CheckSame - Implements OP_CheckSame.
2287 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2288 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2290 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2291 // Accept if it is exactly the same as a previously recorded node.
2292 unsigned RecNo = MatcherTable[MatcherIndex++];
2293 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2294 return N == RecordedNodes[RecNo].first;
2297 /// CheckChildSame - Implements OP_CheckChildXSame.
2298 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2299 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2301 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2303 if (ChildNo >= N.getNumOperands())
2304 return false; // Match fails if out of range child #.
2305 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2309 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2310 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2311 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2312 const SelectionDAGISel &SDISel) {
2313 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2316 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2317 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2318 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2319 const SelectionDAGISel &SDISel, SDNode *N) {
2320 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2323 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2324 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2326 uint16_t Opc = MatcherTable[MatcherIndex++];
2327 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2328 return N->getOpcode() == Opc;
2331 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2332 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2333 SDValue N, const TargetLowering *TLI) {
2334 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2335 if (N.getValueType() == VT) return true;
2337 // Handle the case when VT is iPTR.
2338 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2341 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2342 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2343 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2344 if (ChildNo >= N.getNumOperands())
2345 return false; // Match fails if out of range child #.
2346 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2349 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2350 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2352 return cast<CondCodeSDNode>(N)->get() ==
2353 (ISD::CondCode)MatcherTable[MatcherIndex++];
2356 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2357 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2358 SDValue N, const TargetLowering *TLI) {
2359 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2360 if (cast<VTSDNode>(N)->getVT() == VT)
2363 // Handle the case when VT is iPTR.
2364 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2367 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2368 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2370 int64_t Val = MatcherTable[MatcherIndex++];
2372 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2374 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2375 return C && C->getSExtValue() == Val;
2378 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2379 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2380 SDValue N, unsigned ChildNo) {
2381 if (ChildNo >= N.getNumOperands())
2382 return false; // Match fails if out of range child #.
2383 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2386 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2387 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2388 SDValue N, const SelectionDAGISel &SDISel) {
2389 int64_t Val = MatcherTable[MatcherIndex++];
2391 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2393 if (N->getOpcode() != ISD::AND) return false;
2395 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2396 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2399 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2400 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2401 SDValue N, const SelectionDAGISel &SDISel) {
2402 int64_t Val = MatcherTable[MatcherIndex++];
2404 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2406 if (N->getOpcode() != ISD::OR) return false;
2408 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2409 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2412 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2413 /// scope, evaluate the current node. If the current predicate is known to
2414 /// fail, set Result=true and return anything. If the current predicate is
2415 /// known to pass, set Result=false and return the MatcherIndex to continue
2416 /// with. If the current predicate is unknown, set Result=false and return the
2417 /// MatcherIndex to continue with.
2418 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2419 unsigned Index, SDValue N,
2421 const SelectionDAGISel &SDISel,
2422 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2423 switch (Table[Index++]) {
2426 return Index-1; // Could not evaluate this predicate.
2427 case SelectionDAGISel::OPC_CheckSame:
2428 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2430 case SelectionDAGISel::OPC_CheckChild0Same:
2431 case SelectionDAGISel::OPC_CheckChild1Same:
2432 case SelectionDAGISel::OPC_CheckChild2Same:
2433 case SelectionDAGISel::OPC_CheckChild3Same:
2434 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2435 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2437 case SelectionDAGISel::OPC_CheckPatternPredicate:
2438 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2440 case SelectionDAGISel::OPC_CheckPredicate:
2441 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2443 case SelectionDAGISel::OPC_CheckOpcode:
2444 Result = !::CheckOpcode(Table, Index, N.getNode());
2446 case SelectionDAGISel::OPC_CheckType:
2447 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2449 case SelectionDAGISel::OPC_CheckChild0Type:
2450 case SelectionDAGISel::OPC_CheckChild1Type:
2451 case SelectionDAGISel::OPC_CheckChild2Type:
2452 case SelectionDAGISel::OPC_CheckChild3Type:
2453 case SelectionDAGISel::OPC_CheckChild4Type:
2454 case SelectionDAGISel::OPC_CheckChild5Type:
2455 case SelectionDAGISel::OPC_CheckChild6Type:
2456 case SelectionDAGISel::OPC_CheckChild7Type:
2457 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2459 SelectionDAGISel::OPC_CheckChild0Type);
2461 case SelectionDAGISel::OPC_CheckCondCode:
2462 Result = !::CheckCondCode(Table, Index, N);
2464 case SelectionDAGISel::OPC_CheckValueType:
2465 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2467 case SelectionDAGISel::OPC_CheckInteger:
2468 Result = !::CheckInteger(Table, Index, N);
2470 case SelectionDAGISel::OPC_CheckChild0Integer:
2471 case SelectionDAGISel::OPC_CheckChild1Integer:
2472 case SelectionDAGISel::OPC_CheckChild2Integer:
2473 case SelectionDAGISel::OPC_CheckChild3Integer:
2474 case SelectionDAGISel::OPC_CheckChild4Integer:
2475 Result = !::CheckChildInteger(Table, Index, N,
2476 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2478 case SelectionDAGISel::OPC_CheckAndImm:
2479 Result = !::CheckAndImm(Table, Index, N, SDISel);
2481 case SelectionDAGISel::OPC_CheckOrImm:
2482 Result = !::CheckOrImm(Table, Index, N, SDISel);
2490 /// FailIndex - If this match fails, this is the index to continue with.
2493 /// NodeStack - The node stack when the scope was formed.
2494 SmallVector<SDValue, 4> NodeStack;
2496 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2497 unsigned NumRecordedNodes;
2499 /// NumMatchedMemRefs - The number of matched memref entries.
2500 unsigned NumMatchedMemRefs;
2502 /// InputChain/InputGlue - The current chain/glue
2503 SDValue InputChain, InputGlue;
2505 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2506 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2509 /// \\brief A DAG update listener to keep the matching state
2510 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2511 /// change the DAG while matching. X86 addressing mode matcher is an example
2513 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2515 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2516 SmallVectorImpl<MatchScope> &MatchScopes;
2518 MatchStateUpdater(SelectionDAG &DAG,
2519 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2520 SmallVectorImpl<MatchScope> &MS) :
2521 SelectionDAG::DAGUpdateListener(DAG),
2522 RecordedNodes(RN), MatchScopes(MS) { }
2524 void NodeDeleted(SDNode *N, SDNode *E) override {
2525 // Some early-returns here to avoid the search if we deleted the node or
2526 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2527 // do, so it's unnecessary to update matching state at that point).
2528 // Neither of these can occur currently because we only install this
2529 // update listener during matching a complex patterns.
2530 if (!E || E->isMachineOpcode())
2532 // Performing linear search here does not matter because we almost never
2533 // run this code. You'd have to have a CSE during complex pattern
2535 for (auto &I : RecordedNodes)
2536 if (I.first.getNode() == N)
2539 for (auto &I : MatchScopes)
2540 for (auto &J : I.NodeStack)
2541 if (J.getNode() == N)
2547 SDNode *SelectionDAGISel::
2548 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2549 unsigned TableSize) {
2550 // FIXME: Should these even be selected? Handle these cases in the caller?
2551 switch (NodeToMatch->getOpcode()) {
2554 case ISD::EntryToken: // These nodes remain the same.
2555 case ISD::BasicBlock:
2557 case ISD::RegisterMask:
2558 case ISD::HANDLENODE:
2559 case ISD::MDNODE_SDNODE:
2560 case ISD::TargetConstant:
2561 case ISD::TargetConstantFP:
2562 case ISD::TargetConstantPool:
2563 case ISD::TargetFrameIndex:
2564 case ISD::TargetExternalSymbol:
2566 case ISD::TargetBlockAddress:
2567 case ISD::TargetJumpTable:
2568 case ISD::TargetGlobalTLSAddress:
2569 case ISD::TargetGlobalAddress:
2570 case ISD::TokenFactor:
2571 case ISD::CopyFromReg:
2572 case ISD::CopyToReg:
2574 case ISD::LIFETIME_START:
2575 case ISD::LIFETIME_END:
2576 NodeToMatch->setNodeId(-1); // Mark selected.
2578 case ISD::AssertSext:
2579 case ISD::AssertZext:
2580 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2581 NodeToMatch->getOperand(0));
2583 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2584 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2585 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2586 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2589 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2591 // Set up the node stack with NodeToMatch as the only node on the stack.
2592 SmallVector<SDValue, 8> NodeStack;
2593 SDValue N = SDValue(NodeToMatch, 0);
2594 NodeStack.push_back(N);
2596 // MatchScopes - Scopes used when matching, if a match failure happens, this
2597 // indicates where to continue checking.
2598 SmallVector<MatchScope, 8> MatchScopes;
2600 // RecordedNodes - This is the set of nodes that have been recorded by the
2601 // state machine. The second value is the parent of the node, or null if the
2602 // root is recorded.
2603 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2605 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2607 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2609 // These are the current input chain and glue for use when generating nodes.
2610 // Various Emit operations change these. For example, emitting a copytoreg
2611 // uses and updates these.
2612 SDValue InputChain, InputGlue;
2614 // ChainNodesMatched - If a pattern matches nodes that have input/output
2615 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2616 // which ones they are. The result is captured into this list so that we can
2617 // update the chain results when the pattern is complete.
2618 SmallVector<SDNode*, 3> ChainNodesMatched;
2619 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2621 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2622 NodeToMatch->dump(CurDAG);
2625 // Determine where to start the interpreter. Normally we start at opcode #0,
2626 // but if the state machine starts with an OPC_SwitchOpcode, then we
2627 // accelerate the first lookup (which is guaranteed to be hot) with the
2628 // OpcodeOffset table.
2629 unsigned MatcherIndex = 0;
2631 if (!OpcodeOffset.empty()) {
2632 // Already computed the OpcodeOffset table, just index into it.
2633 if (N.getOpcode() < OpcodeOffset.size())
2634 MatcherIndex = OpcodeOffset[N.getOpcode()];
2635 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2637 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2638 // Otherwise, the table isn't computed, but the state machine does start
2639 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2640 // is the first time we're selecting an instruction.
2643 // Get the size of this case.
2644 unsigned CaseSize = MatcherTable[Idx++];
2646 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2647 if (CaseSize == 0) break;
2649 // Get the opcode, add the index to the table.
2650 uint16_t Opc = MatcherTable[Idx++];
2651 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2652 if (Opc >= OpcodeOffset.size())
2653 OpcodeOffset.resize((Opc+1)*2);
2654 OpcodeOffset[Opc] = Idx;
2658 // Okay, do the lookup for the first opcode.
2659 if (N.getOpcode() < OpcodeOffset.size())
2660 MatcherIndex = OpcodeOffset[N.getOpcode()];
2664 assert(MatcherIndex < TableSize && "Invalid index");
2666 unsigned CurrentOpcodeIndex = MatcherIndex;
2668 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2671 // Okay, the semantics of this operation are that we should push a scope
2672 // then evaluate the first child. However, pushing a scope only to have
2673 // the first check fail (which then pops it) is inefficient. If we can
2674 // determine immediately that the first check (or first several) will
2675 // immediately fail, don't even bother pushing a scope for them.
2679 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2680 if (NumToSkip & 128)
2681 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2682 // Found the end of the scope with no match.
2683 if (NumToSkip == 0) {
2688 FailIndex = MatcherIndex+NumToSkip;
2690 unsigned MatcherIndexOfPredicate = MatcherIndex;
2691 (void)MatcherIndexOfPredicate; // silence warning.
2693 // If we can't evaluate this predicate without pushing a scope (e.g. if
2694 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2695 // push the scope and evaluate the full predicate chain.
2697 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2698 Result, *this, RecordedNodes);
2702 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2703 << "index " << MatcherIndexOfPredicate
2704 << ", continuing at " << FailIndex << "\n");
2705 ++NumDAGIselRetries;
2707 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2708 // move to the next case.
2709 MatcherIndex = FailIndex;
2712 // If the whole scope failed to match, bail.
2713 if (FailIndex == 0) break;
2715 // Push a MatchScope which indicates where to go if the first child fails
2717 MatchScope NewEntry;
2718 NewEntry.FailIndex = FailIndex;
2719 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2720 NewEntry.NumRecordedNodes = RecordedNodes.size();
2721 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2722 NewEntry.InputChain = InputChain;
2723 NewEntry.InputGlue = InputGlue;
2724 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2725 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2726 MatchScopes.push_back(NewEntry);
2729 case OPC_RecordNode: {
2730 // Remember this node, it may end up being an operand in the pattern.
2731 SDNode *Parent = nullptr;
2732 if (NodeStack.size() > 1)
2733 Parent = NodeStack[NodeStack.size()-2].getNode();
2734 RecordedNodes.push_back(std::make_pair(N, Parent));
2738 case OPC_RecordChild0: case OPC_RecordChild1:
2739 case OPC_RecordChild2: case OPC_RecordChild3:
2740 case OPC_RecordChild4: case OPC_RecordChild5:
2741 case OPC_RecordChild6: case OPC_RecordChild7: {
2742 unsigned ChildNo = Opcode-OPC_RecordChild0;
2743 if (ChildNo >= N.getNumOperands())
2744 break; // Match fails if out of range child #.
2746 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2750 case OPC_RecordMemRef:
2751 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2754 case OPC_CaptureGlueInput:
2755 // If the current node has an input glue, capture it in InputGlue.
2756 if (N->getNumOperands() != 0 &&
2757 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2758 InputGlue = N->getOperand(N->getNumOperands()-1);
2761 case OPC_MoveChild: {
2762 unsigned ChildNo = MatcherTable[MatcherIndex++];
2763 if (ChildNo >= N.getNumOperands())
2764 break; // Match fails if out of range child #.
2765 N = N.getOperand(ChildNo);
2766 NodeStack.push_back(N);
2770 case OPC_MoveParent:
2771 // Pop the current node off the NodeStack.
2772 NodeStack.pop_back();
2773 assert(!NodeStack.empty() && "Node stack imbalance!");
2774 N = NodeStack.back();
2778 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2781 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2782 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2783 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2784 Opcode-OPC_CheckChild0Same))
2788 case OPC_CheckPatternPredicate:
2789 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2791 case OPC_CheckPredicate:
2792 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2796 case OPC_CheckComplexPat: {
2797 unsigned CPNum = MatcherTable[MatcherIndex++];
2798 unsigned RecNo = MatcherTable[MatcherIndex++];
2799 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2801 // If target can modify DAG during matching, keep the matching state
2803 std::unique_ptr<MatchStateUpdater> MSU;
2804 if (ComplexPatternFuncMutatesDAG())
2805 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2808 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2809 RecordedNodes[RecNo].first, CPNum,
2814 case OPC_CheckOpcode:
2815 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2819 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2823 case OPC_SwitchOpcode: {
2824 unsigned CurNodeOpcode = N.getOpcode();
2825 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2828 // Get the size of this case.
2829 CaseSize = MatcherTable[MatcherIndex++];
2831 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2832 if (CaseSize == 0) break;
2834 uint16_t Opc = MatcherTable[MatcherIndex++];
2835 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2837 // If the opcode matches, then we will execute this case.
2838 if (CurNodeOpcode == Opc)
2841 // Otherwise, skip over this case.
2842 MatcherIndex += CaseSize;
2845 // If no cases matched, bail out.
2846 if (CaseSize == 0) break;
2848 // Otherwise, execute the case we found.
2849 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2850 << " to " << MatcherIndex << "\n");
2854 case OPC_SwitchType: {
2855 MVT CurNodeVT = N.getSimpleValueType();
2856 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2859 // Get the size of this case.
2860 CaseSize = MatcherTable[MatcherIndex++];
2862 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2863 if (CaseSize == 0) break;
2865 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2866 if (CaseVT == MVT::iPTR)
2867 CaseVT = TLI->getPointerTy();
2869 // If the VT matches, then we will execute this case.
2870 if (CurNodeVT == CaseVT)
2873 // Otherwise, skip over this case.
2874 MatcherIndex += CaseSize;
2877 // If no cases matched, bail out.
2878 if (CaseSize == 0) break;
2880 // Otherwise, execute the case we found.
2881 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2882 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2885 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2886 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2887 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2888 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2889 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2890 Opcode-OPC_CheckChild0Type))
2893 case OPC_CheckCondCode:
2894 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2896 case OPC_CheckValueType:
2897 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2900 case OPC_CheckInteger:
2901 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2903 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2904 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2905 case OPC_CheckChild4Integer:
2906 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2907 Opcode-OPC_CheckChild0Integer)) break;
2909 case OPC_CheckAndImm:
2910 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2912 case OPC_CheckOrImm:
2913 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2916 case OPC_CheckFoldableChainNode: {
2917 assert(NodeStack.size() != 1 && "No parent node");
2918 // Verify that all intermediate nodes between the root and this one have
2920 bool HasMultipleUses = false;
2921 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2922 if (!NodeStack[i].hasOneUse()) {
2923 HasMultipleUses = true;
2926 if (HasMultipleUses) break;
2928 // Check to see that the target thinks this is profitable to fold and that
2929 // we can fold it without inducing cycles in the graph.
2930 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2932 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2933 NodeToMatch, OptLevel,
2934 true/*We validate our own chains*/))
2939 case OPC_EmitInteger: {
2940 MVT::SimpleValueType VT =
2941 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2942 int64_t Val = MatcherTable[MatcherIndex++];
2944 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2945 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2946 CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch),
2950 case OPC_EmitRegister: {
2951 MVT::SimpleValueType VT =
2952 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2953 unsigned RegNo = MatcherTable[MatcherIndex++];
2954 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2955 CurDAG->getRegister(RegNo, VT), nullptr));
2958 case OPC_EmitRegister2: {
2959 // For targets w/ more than 256 register names, the register enum
2960 // values are stored in two bytes in the matcher table (just like
2962 MVT::SimpleValueType VT =
2963 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2964 unsigned RegNo = MatcherTable[MatcherIndex++];
2965 RegNo |= MatcherTable[MatcherIndex++] << 8;
2966 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2967 CurDAG->getRegister(RegNo, VT), nullptr));
2971 case OPC_EmitConvertToTarget: {
2972 // Convert from IMM/FPIMM to target version.
2973 unsigned RecNo = MatcherTable[MatcherIndex++];
2974 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2975 SDValue Imm = RecordedNodes[RecNo].first;
2977 if (Imm->getOpcode() == ISD::Constant) {
2978 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2979 Imm = CurDAG->getConstant(*Val, SDLoc(NodeToMatch), Imm.getValueType(),
2981 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2982 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2983 Imm = CurDAG->getConstantFP(*Val, SDLoc(NodeToMatch),
2984 Imm.getValueType(), true);
2987 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2991 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2992 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2993 // These are space-optimized forms of OPC_EmitMergeInputChains.
2994 assert(!InputChain.getNode() &&
2995 "EmitMergeInputChains should be the first chain producing node");
2996 assert(ChainNodesMatched.empty() &&
2997 "Should only have one EmitMergeInputChains per match");
2999 // Read all of the chained nodes.
3000 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3001 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3002 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3004 // FIXME: What if other value results of the node have uses not matched
3006 if (ChainNodesMatched.back() != NodeToMatch &&
3007 !RecordedNodes[RecNo].first.hasOneUse()) {
3008 ChainNodesMatched.clear();
3012 // Merge the input chains if they are not intra-pattern references.
3013 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3015 if (!InputChain.getNode())
3016 break; // Failed to merge.
3020 case OPC_EmitMergeInputChains: {
3021 assert(!InputChain.getNode() &&
3022 "EmitMergeInputChains should be the first chain producing node");
3023 // This node gets a list of nodes we matched in the input that have
3024 // chains. We want to token factor all of the input chains to these nodes
3025 // together. However, if any of the input chains is actually one of the
3026 // nodes matched in this pattern, then we have an intra-match reference.
3027 // Ignore these because the newly token factored chain should not refer to
3029 unsigned NumChains = MatcherTable[MatcherIndex++];
3030 assert(NumChains != 0 && "Can't TF zero chains");
3032 assert(ChainNodesMatched.empty() &&
3033 "Should only have one EmitMergeInputChains per match");
3035 // Read all of the chained nodes.
3036 for (unsigned i = 0; i != NumChains; ++i) {
3037 unsigned RecNo = MatcherTable[MatcherIndex++];
3038 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3039 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3041 // FIXME: What if other value results of the node have uses not matched
3043 if (ChainNodesMatched.back() != NodeToMatch &&
3044 !RecordedNodes[RecNo].first.hasOneUse()) {
3045 ChainNodesMatched.clear();
3050 // If the inner loop broke out, the match fails.
3051 if (ChainNodesMatched.empty())
3054 // Merge the input chains if they are not intra-pattern references.
3055 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3057 if (!InputChain.getNode())
3058 break; // Failed to merge.
3063 case OPC_EmitCopyToReg: {
3064 unsigned RecNo = MatcherTable[MatcherIndex++];
3065 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3066 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3068 if (!InputChain.getNode())
3069 InputChain = CurDAG->getEntryNode();
3071 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3072 DestPhysReg, RecordedNodes[RecNo].first,
3075 InputGlue = InputChain.getValue(1);
3079 case OPC_EmitNodeXForm: {
3080 unsigned XFormNo = MatcherTable[MatcherIndex++];
3081 unsigned RecNo = MatcherTable[MatcherIndex++];
3082 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3083 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3084 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3089 case OPC_MorphNodeTo: {
3090 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3091 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3092 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3093 // Get the result VT list.
3094 unsigned NumVTs = MatcherTable[MatcherIndex++];
3095 SmallVector<EVT, 4> VTs;
3096 for (unsigned i = 0; i != NumVTs; ++i) {
3097 MVT::SimpleValueType VT =
3098 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3099 if (VT == MVT::iPTR)
3100 VT = TLI->getPointerTy().SimpleTy;
3104 if (EmitNodeInfo & OPFL_Chain)
3105 VTs.push_back(MVT::Other);
3106 if (EmitNodeInfo & OPFL_GlueOutput)
3107 VTs.push_back(MVT::Glue);
3109 // This is hot code, so optimize the two most common cases of 1 and 2
3112 if (VTs.size() == 1)
3113 VTList = CurDAG->getVTList(VTs[0]);
3114 else if (VTs.size() == 2)
3115 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3117 VTList = CurDAG->getVTList(VTs);
3119 // Get the operand list.
3120 unsigned NumOps = MatcherTable[MatcherIndex++];
3121 SmallVector<SDValue, 8> Ops;
3122 for (unsigned i = 0; i != NumOps; ++i) {
3123 unsigned RecNo = MatcherTable[MatcherIndex++];
3125 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3127 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3128 Ops.push_back(RecordedNodes[RecNo].first);
3131 // If there are variadic operands to add, handle them now.
3132 if (EmitNodeInfo & OPFL_VariadicInfo) {
3133 // Determine the start index to copy from.
3134 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3135 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3136 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3137 "Invalid variadic node");
3138 // Copy all of the variadic operands, not including a potential glue
3140 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3142 SDValue V = NodeToMatch->getOperand(i);
3143 if (V.getValueType() == MVT::Glue) break;
3148 // If this has chain/glue inputs, add them.
3149 if (EmitNodeInfo & OPFL_Chain)
3150 Ops.push_back(InputChain);
3151 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3152 Ops.push_back(InputGlue);
3155 SDNode *Res = nullptr;
3156 if (Opcode != OPC_MorphNodeTo) {
3157 // If this is a normal EmitNode command, just create the new node and
3158 // add the results to the RecordedNodes list.
3159 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3162 // Add all the non-glue/non-chain results to the RecordedNodes list.
3163 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3164 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3165 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3169 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3170 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3172 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3173 // We will visit the equivalent node later.
3174 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3178 // If the node had chain/glue results, update our notion of the current
3180 if (EmitNodeInfo & OPFL_GlueOutput) {
3181 InputGlue = SDValue(Res, VTs.size()-1);
3182 if (EmitNodeInfo & OPFL_Chain)
3183 InputChain = SDValue(Res, VTs.size()-2);
3184 } else if (EmitNodeInfo & OPFL_Chain)
3185 InputChain = SDValue(Res, VTs.size()-1);
3187 // If the OPFL_MemRefs glue is set on this node, slap all of the
3188 // accumulated memrefs onto it.
3190 // FIXME: This is vastly incorrect for patterns with multiple outputs
3191 // instructions that access memory and for ComplexPatterns that match
3193 if (EmitNodeInfo & OPFL_MemRefs) {
3194 // Only attach load or store memory operands if the generated
3195 // instruction may load or store.
3196 const MCInstrDesc &MCID = TII->get(TargetOpc);
3197 bool mayLoad = MCID.mayLoad();
3198 bool mayStore = MCID.mayStore();
3200 unsigned NumMemRefs = 0;
3201 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3202 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3203 if ((*I)->isLoad()) {
3206 } else if ((*I)->isStore()) {
3214 MachineSDNode::mmo_iterator MemRefs =
3215 MF->allocateMemRefsArray(NumMemRefs);
3217 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3218 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3219 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3220 if ((*I)->isLoad()) {
3223 } else if ((*I)->isStore()) {
3231 cast<MachineSDNode>(Res)
3232 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3236 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3237 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3239 // If this was a MorphNodeTo then we're completely done!
3240 if (Opcode == OPC_MorphNodeTo) {
3241 // Update chain and glue uses.
3242 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3243 InputGlue, GlueResultNodesMatched, true);
3250 case OPC_MarkGlueResults: {
3251 unsigned NumNodes = MatcherTable[MatcherIndex++];
3253 // Read and remember all the glue-result nodes.
3254 for (unsigned i = 0; i != NumNodes; ++i) {
3255 unsigned RecNo = MatcherTable[MatcherIndex++];
3257 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3259 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3260 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3265 case OPC_CompleteMatch: {
3266 // The match has been completed, and any new nodes (if any) have been
3267 // created. Patch up references to the matched dag to use the newly
3269 unsigned NumResults = MatcherTable[MatcherIndex++];
3271 for (unsigned i = 0; i != NumResults; ++i) {
3272 unsigned ResSlot = MatcherTable[MatcherIndex++];
3274 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3276 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3277 SDValue Res = RecordedNodes[ResSlot].first;
3279 assert(i < NodeToMatch->getNumValues() &&
3280 NodeToMatch->getValueType(i) != MVT::Other &&
3281 NodeToMatch->getValueType(i) != MVT::Glue &&
3282 "Invalid number of results to complete!");
3283 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3284 NodeToMatch->getValueType(i) == MVT::iPTR ||
3285 Res.getValueType() == MVT::iPTR ||
3286 NodeToMatch->getValueType(i).getSizeInBits() ==
3287 Res.getValueType().getSizeInBits()) &&
3288 "invalid replacement");
3289 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3292 // If the root node defines glue, add it to the glue nodes to update list.
3293 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3294 GlueResultNodesMatched.push_back(NodeToMatch);
3296 // Update chain and glue uses.
3297 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3298 InputGlue, GlueResultNodesMatched, false);
3300 assert(NodeToMatch->use_empty() &&
3301 "Didn't replace all uses of the node?");
3303 // FIXME: We just return here, which interacts correctly with SelectRoot
3304 // above. We should fix this to not return an SDNode* anymore.
3309 // If the code reached this point, then the match failed. See if there is
3310 // another child to try in the current 'Scope', otherwise pop it until we
3311 // find a case to check.
3312 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3313 ++NumDAGIselRetries;
3315 if (MatchScopes.empty()) {
3316 CannotYetSelect(NodeToMatch);
3320 // Restore the interpreter state back to the point where the scope was
3322 MatchScope &LastScope = MatchScopes.back();
3323 RecordedNodes.resize(LastScope.NumRecordedNodes);
3325 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3326 N = NodeStack.back();
3328 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3329 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3330 MatcherIndex = LastScope.FailIndex;
3332 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3334 InputChain = LastScope.InputChain;
3335 InputGlue = LastScope.InputGlue;
3336 if (!LastScope.HasChainNodesMatched)
3337 ChainNodesMatched.clear();
3338 if (!LastScope.HasGlueResultNodesMatched)
3339 GlueResultNodesMatched.clear();
3341 // Check to see what the offset is at the new MatcherIndex. If it is zero
3342 // we have reached the end of this scope, otherwise we have another child
3343 // in the current scope to try.
3344 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3345 if (NumToSkip & 128)
3346 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3348 // If we have another child in this scope to match, update FailIndex and
3350 if (NumToSkip != 0) {
3351 LastScope.FailIndex = MatcherIndex+NumToSkip;
3355 // End of this scope, pop it and try the next child in the containing
3357 MatchScopes.pop_back();
3364 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3366 raw_string_ostream Msg(msg);
3367 Msg << "Cannot select: ";
3369 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3370 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3371 N->getOpcode() != ISD::INTRINSIC_VOID) {
3372 N->printrFull(Msg, CurDAG);
3373 Msg << "\nIn function: " << MF->getName();
3375 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3377 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3378 if (iid < Intrinsic::num_intrinsics)
3379 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3380 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3381 Msg << "target intrinsic %" << TII->getName(iid);
3383 Msg << "unknown intrinsic #" << iid;
3385 report_fatal_error(Msg.str());
3388 char SelectionDAGISel::ID = 0;