1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLibraryInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
61 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
62 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
63 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
64 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
66 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
67 STATISTIC(NumFastIselFailLowerArguments,
68 "Number of entry blocks where fast isel failed to lower arguments");
72 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
73 cl::desc("Enable extra verbose messages in the \"fast\" "
74 "instruction selector"));
77 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
78 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
79 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
80 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
81 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
82 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
83 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
85 // Standard binary operators...
86 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
87 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
88 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
89 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
90 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
91 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
92 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
93 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
94 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
95 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
96 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
97 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
99 // Logical operators...
100 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
101 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
102 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
104 // Memory instructions...
105 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
106 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
107 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
108 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
109 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
110 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
111 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
113 // Convert instructions...
114 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
115 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
116 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
117 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
118 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
119 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
120 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
121 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
122 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
123 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
124 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
125 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
127 // Other instructions...
128 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
129 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
130 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
131 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
132 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
133 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
134 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
135 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
136 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
137 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
138 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
139 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
140 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
141 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
142 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
146 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
147 cl::desc("Enable verbose messages in the \"fast\" "
148 "instruction selector"));
150 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
151 cl::desc("Enable abort calls when \"fast\" instruction selection "
152 "fails to lower an instruction"));
154 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
155 cl::desc("Enable abort calls when \"fast\" instruction selection "
156 "fails to lower a formal argument"));
160 cl::desc("use Machine Branch Probability Info"),
161 cl::init(true), cl::Hidden);
165 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
166 cl::desc("Pop up a window to show dags before the first "
167 "dag combine pass"));
169 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
170 cl::desc("Pop up a window to show dags before legalize types"));
172 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
173 cl::desc("Pop up a window to show dags before legalize"));
175 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
176 cl::desc("Pop up a window to show dags before the second "
177 "dag combine pass"));
179 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
180 cl::desc("Pop up a window to show dags before the post legalize types"
181 " dag combine pass"));
183 ViewISelDAGs("view-isel-dags", cl::Hidden,
184 cl::desc("Pop up a window to show isel dags as they are selected"));
186 ViewSchedDAGs("view-sched-dags", cl::Hidden,
187 cl::desc("Pop up a window to show sched dags as they are processed"));
189 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
190 cl::desc("Pop up a window to show SUnit dags after they are processed"));
192 static const bool ViewDAGCombine1 = false,
193 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
194 ViewDAGCombine2 = false,
195 ViewDAGCombineLT = false,
196 ViewISelDAGs = false, ViewSchedDAGs = false,
197 ViewSUnitDAGs = false;
200 //===---------------------------------------------------------------------===//
202 /// RegisterScheduler class - Track the registration of instruction schedulers.
204 //===---------------------------------------------------------------------===//
205 MachinePassRegistry RegisterScheduler::Registry;
207 //===---------------------------------------------------------------------===//
209 /// ISHeuristic command line option for instruction schedulers.
211 //===---------------------------------------------------------------------===//
212 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
213 RegisterPassParser<RegisterScheduler> >
214 ISHeuristic("pre-RA-sched",
215 cl::init(&createDefaultScheduler),
216 cl::desc("Instruction schedulers available (before register"
219 static RegisterScheduler
220 defaultListDAGScheduler("default", "Best scheduler for the target",
221 createDefaultScheduler);
224 //===--------------------------------------------------------------------===//
225 /// createDefaultScheduler - This creates an instruction scheduler appropriate
227 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
228 CodeGenOpt::Level OptLevel) {
229 const TargetLowering *TLI = IS->getTargetLowering();
230 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
232 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
233 TLI->getSchedulingPreference() == Sched::Source)
234 return createSourceListDAGScheduler(IS, OptLevel);
235 if (TLI->getSchedulingPreference() == Sched::RegPressure)
236 return createBURRListDAGScheduler(IS, OptLevel);
237 if (TLI->getSchedulingPreference() == Sched::Hybrid)
238 return createHybridListDAGScheduler(IS, OptLevel);
239 if (TLI->getSchedulingPreference() == Sched::VLIW)
240 return createVLIWDAGScheduler(IS, OptLevel);
241 assert(TLI->getSchedulingPreference() == Sched::ILP &&
242 "Unknown sched type!");
243 return createILPListDAGScheduler(IS, OptLevel);
247 // EmitInstrWithCustomInserter - This method should be implemented by targets
248 // that mark instructions with the 'usesCustomInserter' flag. These
249 // instructions are special in various ways, which require special support to
250 // insert. The specified MachineInstr is created but not inserted into any
251 // basic blocks, and this method is called to expand it into a sequence of
252 // instructions, potentially also creating new basic blocks and control flow.
253 // When new basic blocks are inserted and the edges from MBB to its successors
254 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
257 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
258 MachineBasicBlock *MBB) const {
260 dbgs() << "If a target marks an instruction with "
261 "'usesCustomInserter', it must implement "
262 "TargetLowering::EmitInstrWithCustomInserter!";
267 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
268 SDNode *Node) const {
269 assert(!MI->hasPostISelHook() &&
270 "If a target marks an instruction with 'hasPostISelHook', "
271 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
274 //===----------------------------------------------------------------------===//
275 // SelectionDAGISel code
276 //===----------------------------------------------------------------------===//
278 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
279 CodeGenOpt::Level OL) :
280 MachineFunctionPass(ID), TM(tm),
281 FuncInfo(new FunctionLoweringInfo(TM)),
282 CurDAG(new SelectionDAG(tm, OL)),
283 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
287 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
288 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
289 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
290 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
293 SelectionDAGISel::~SelectionDAGISel() {
299 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
300 AU.addRequired<AliasAnalysis>();
301 AU.addPreserved<AliasAnalysis>();
302 AU.addRequired<GCModuleInfo>();
303 AU.addPreserved<GCModuleInfo>();
304 AU.addRequired<TargetLibraryInfo>();
305 if (UseMBPI && OptLevel != CodeGenOpt::None)
306 AU.addRequired<BranchProbabilityInfo>();
307 MachineFunctionPass::getAnalysisUsage(AU);
310 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
311 /// may trap on it. In this case we have to split the edge so that the path
312 /// through the predecessor block that doesn't go to the phi block doesn't
313 /// execute the possibly trapping instruction.
315 /// This is required for correctness, so it must be done at -O0.
317 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
318 // Loop for blocks with phi nodes.
319 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
320 PHINode *PN = dyn_cast<PHINode>(BB->begin());
321 if (PN == 0) continue;
324 // For each block with a PHI node, check to see if any of the input values
325 // are potentially trapping constant expressions. Constant expressions are
326 // the only potentially trapping value that can occur as the argument to a
328 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
329 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
330 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
331 if (CE == 0 || !CE->canTrap()) continue;
333 // The only case we have to worry about is when the edge is critical.
334 // Since this block has a PHI Node, we assume it has multiple input
335 // edges: check to see if the pred has multiple successors.
336 BasicBlock *Pred = PN->getIncomingBlock(i);
337 if (Pred->getTerminator()->getNumSuccessors() == 1)
340 // Okay, we have to split this edge.
341 SplitCriticalEdge(Pred->getTerminator(),
342 GetSuccessorNumber(Pred, BB), SDISel, true);
348 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
349 // Do some sanity-checking on the command-line options.
350 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
351 "-fast-isel-verbose requires -fast-isel");
352 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
353 "-fast-isel-abort requires -fast-isel");
355 const Function &Fn = *mf.getFunction();
356 const TargetInstrInfo &TII = *TM.getInstrInfo();
357 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
360 RegInfo = &MF->getRegInfo();
361 AA = &getAnalysis<AliasAnalysis>();
362 LibInfo = &getAnalysis<TargetLibraryInfo>();
363 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
364 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
366 TargetSubtargetInfo &ST =
367 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
368 ST.resetSubtargetFeatures(MF);
369 TM.resetTargetOptions(MF);
371 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
373 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
375 CurDAG->init(*MF, TTI);
376 FuncInfo->set(Fn, *MF);
378 if (UseMBPI && OptLevel != CodeGenOpt::None)
379 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
383 SDB->init(GFI, *AA, LibInfo);
385 MF->setHasMSInlineAsm(false);
386 SelectAllBasicBlocks(Fn);
388 // If the first basic block in the function has live ins that need to be
389 // copied into vregs, emit the copies into the top of the block before
390 // emitting the code for the block.
391 MachineBasicBlock *EntryMBB = MF->begin();
392 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
394 DenseMap<unsigned, unsigned> LiveInMap;
395 if (!FuncInfo->ArgDbgValues.empty())
396 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
397 E = RegInfo->livein_end(); LI != E; ++LI)
399 LiveInMap.insert(std::make_pair(LI->first, LI->second));
401 // Insert DBG_VALUE instructions for function arguments to the entry block.
402 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
403 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
404 bool hasFI = MI->getOperand(0).isFI();
405 unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
406 if (TargetRegisterInfo::isPhysicalRegister(Reg))
407 EntryMBB->insert(EntryMBB->begin(), MI);
409 MachineInstr *Def = RegInfo->getVRegDef(Reg);
410 MachineBasicBlock::iterator InsertPos = Def;
411 // FIXME: VR def may not be in entry block.
412 Def->getParent()->insert(llvm::next(InsertPos), MI);
415 // If Reg is live-in then update debug info to track its copy in a vreg.
416 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
417 if (LDI != LiveInMap.end()) {
418 assert(!hasFI && "There's no handling of frame pointer updating here yet "
420 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
421 MachineBasicBlock::iterator InsertPos = Def;
422 const MDNode *Variable =
423 MI->getOperand(MI->getNumOperands()-1).getMetadata();
424 unsigned Offset = MI->getOperand(1).getImm();
425 // Def is never a terminator here, so it is ok to increment InsertPos.
426 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
427 TII.get(TargetOpcode::DBG_VALUE))
428 .addReg(LDI->second, RegState::Debug)
429 .addImm(Offset).addMetadata(Variable);
431 // If this vreg is directly copied into an exported register then
432 // that COPY instructions also need DBG_VALUE, if it is the only
433 // user of LDI->second.
434 MachineInstr *CopyUseMI = NULL;
435 for (MachineRegisterInfo::use_iterator
436 UI = RegInfo->use_begin(LDI->second);
437 MachineInstr *UseMI = UI.skipInstruction();) {
438 if (UseMI->isDebugValue()) continue;
439 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
440 CopyUseMI = UseMI; continue;
442 // Otherwise this is another use or second copy use.
443 CopyUseMI = NULL; break;
446 MachineInstr *NewMI =
447 BuildMI(*MF, CopyUseMI->getDebugLoc(),
448 TII.get(TargetOpcode::DBG_VALUE))
449 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
450 .addImm(Offset).addMetadata(Variable);
451 MachineBasicBlock::iterator Pos = CopyUseMI;
452 EntryMBB->insertAfter(Pos, NewMI);
457 // Determine if there are any calls in this machine function.
458 MachineFrameInfo *MFI = MF->getFrameInfo();
459 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
462 if (MFI->hasCalls() && MF->hasMSInlineAsm())
465 const MachineBasicBlock *MBB = I;
466 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
468 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
469 if ((MCID.isCall() && !MCID.isReturn()) ||
470 II->isStackAligningInlineAsm()) {
471 MFI->setHasCalls(true);
473 if (II->isMSInlineAsm()) {
474 MF->setHasMSInlineAsm(true);
479 // Determine if there is a call to setjmp in the machine function.
480 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
482 // Replace forward-declared registers with the registers containing
483 // the desired value.
484 MachineRegisterInfo &MRI = MF->getRegInfo();
485 for (DenseMap<unsigned, unsigned>::iterator
486 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
488 unsigned From = I->first;
489 unsigned To = I->second;
490 // If To is also scheduled to be replaced, find what its ultimate
493 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
498 MRI.replaceRegWith(From, To);
501 // Freeze the set of reserved registers now that MachineFrameInfo has been
502 // set up. All the information required by getReservedRegs() should be
504 MRI.freezeReservedRegs(*MF);
506 // Release function-specific state. SDB and CurDAG are already cleared
513 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
514 BasicBlock::const_iterator End,
516 // Lower all of the non-terminator instructions. If a call is emitted
517 // as a tail call, cease emitting nodes for this block. Terminators
518 // are handled below.
519 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
522 // Make sure the root of the DAG is up-to-date.
523 CurDAG->setRoot(SDB->getControlRoot());
524 HadTailCall = SDB->HasTailCall;
527 // Final step, emit the lowered DAG as machine code.
531 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
532 SmallPtrSet<SDNode*, 128> VisitedNodes;
533 SmallVector<SDNode*, 128> Worklist;
535 Worklist.push_back(CurDAG->getRoot().getNode());
541 SDNode *N = Worklist.pop_back_val();
543 // If we've already seen this node, ignore it.
544 if (!VisitedNodes.insert(N))
547 // Otherwise, add all chain operands to the worklist.
548 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
549 if (N->getOperand(i).getValueType() == MVT::Other)
550 Worklist.push_back(N->getOperand(i).getNode());
552 // If this is a CopyToReg with a vreg dest, process it.
553 if (N->getOpcode() != ISD::CopyToReg)
556 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
557 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
560 // Ignore non-scalar or non-integer values.
561 SDValue Src = N->getOperand(2);
562 EVT SrcVT = Src.getValueType();
563 if (!SrcVT.isInteger() || SrcVT.isVector())
566 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
567 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
568 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
569 } while (!Worklist.empty());
572 void SelectionDAGISel::CodeGenAndEmitDAG() {
573 std::string GroupName;
574 if (TimePassesIsEnabled)
575 GroupName = "Instruction Selection and Scheduling";
576 std::string BlockName;
577 int BlockNumber = -1;
580 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
581 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
585 BlockNumber = FuncInfo->MBB->getNumber();
586 BlockName = MF->getName().str() + ":" +
587 FuncInfo->MBB->getBasicBlock()->getName().str();
589 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
590 << " '" << BlockName << "'\n"; CurDAG->dump());
592 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
594 // Run the DAG combiner in pre-legalize mode.
596 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
597 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
600 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
601 << " '" << BlockName << "'\n"; CurDAG->dump());
603 // Second step, hack on the DAG until it only uses operations and types that
604 // the target supports.
605 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
610 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
611 Changed = CurDAG->LegalizeTypes();
614 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
615 << " '" << BlockName << "'\n"; CurDAG->dump());
618 if (ViewDAGCombineLT)
619 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
621 // Run the DAG combiner in post-type-legalize mode.
623 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
624 TimePassesIsEnabled);
625 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
628 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
629 << " '" << BlockName << "'\n"; CurDAG->dump());
634 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
635 Changed = CurDAG->LegalizeVectors();
640 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
641 CurDAG->LegalizeTypes();
644 if (ViewDAGCombineLT)
645 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
647 // Run the DAG combiner in post-type-legalize mode.
649 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
650 TimePassesIsEnabled);
651 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
654 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
655 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
658 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
661 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
665 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
666 << " '" << BlockName << "'\n"; CurDAG->dump());
668 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
670 // Run the DAG combiner in post-legalize mode.
672 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
673 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
676 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
677 << " '" << BlockName << "'\n"; CurDAG->dump());
679 if (OptLevel != CodeGenOpt::None)
680 ComputeLiveOutVRegInfo();
682 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
684 // Third, instruction select all of the operations to machine code, adding the
685 // code to the MachineBasicBlock.
687 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
688 DoInstructionSelection();
691 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
692 << " '" << BlockName << "'\n"; CurDAG->dump());
694 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
696 // Schedule machine code.
697 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
699 NamedRegionTimer T("Instruction Scheduling", GroupName,
700 TimePassesIsEnabled);
701 Scheduler->Run(CurDAG, FuncInfo->MBB);
704 if (ViewSUnitDAGs) Scheduler->viewGraph();
706 // Emit machine code to BB. This can change 'BB' to the last block being
708 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
710 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
712 // FuncInfo->InsertPt is passed by reference and set to the end of the
713 // scheduled instructions.
714 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
717 // If the block was split, make sure we update any references that are used to
718 // update PHI nodes later on.
719 if (FirstMBB != LastMBB)
720 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
722 // Free the scheduler state.
724 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
725 TimePassesIsEnabled);
729 // Free the SelectionDAG state, now that we're finished with it.
734 /// ISelUpdater - helper class to handle updates of the instruction selection
736 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
737 SelectionDAG::allnodes_iterator &ISelPosition;
739 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
740 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
742 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
743 /// deleted is the current ISelPosition node, update ISelPosition.
745 virtual void NodeDeleted(SDNode *N, SDNode *E) {
746 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
750 } // end anonymous namespace
752 void SelectionDAGISel::DoInstructionSelection() {
753 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
754 << FuncInfo->MBB->getNumber()
755 << " '" << FuncInfo->MBB->getName() << "'\n");
759 // Select target instructions for the DAG.
761 // Number all nodes with a topological order and set DAGSize.
762 DAGSize = CurDAG->AssignTopologicalOrder();
764 // Create a dummy node (which is not added to allnodes), that adds
765 // a reference to the root node, preventing it from being deleted,
766 // and tracking any changes of the root.
767 HandleSDNode Dummy(CurDAG->getRoot());
768 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
771 // Make sure that ISelPosition gets properly updated when nodes are deleted
772 // in calls made from this function.
773 ISelUpdater ISU(*CurDAG, ISelPosition);
775 // The AllNodes list is now topological-sorted. Visit the
776 // nodes by starting at the end of the list (the root of the
777 // graph) and preceding back toward the beginning (the entry
779 while (ISelPosition != CurDAG->allnodes_begin()) {
780 SDNode *Node = --ISelPosition;
781 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
782 // but there are currently some corner cases that it misses. Also, this
783 // makes it theoretically possible to disable the DAGCombiner.
784 if (Node->use_empty())
787 SDNode *ResNode = Select(Node);
789 // FIXME: This is pretty gross. 'Select' should be changed to not return
790 // anything at all and this code should be nuked with a tactical strike.
792 // If node should not be replaced, continue with the next one.
793 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
797 ReplaceUses(Node, ResNode);
800 // If after the replacement this node is not used any more,
801 // remove this dead node.
802 if (Node->use_empty()) // Don't delete EntryToken, etc.
803 CurDAG->RemoveDeadNode(Node);
806 CurDAG->setRoot(Dummy.getValue());
809 DEBUG(dbgs() << "===== Instruction selection ends:\n");
811 PostprocessISelDAG();
814 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
815 /// do other setup for EH landing-pad blocks.
816 void SelectionDAGISel::PrepareEHLandingPad() {
817 MachineBasicBlock *MBB = FuncInfo->MBB;
819 // Add a label to mark the beginning of the landing pad. Deletion of the
820 // landing pad can thus be detected via the MachineModuleInfo.
821 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
823 // Assign the call site to the landing pad's begin label.
824 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
826 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
827 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
830 // Mark exception register as live in.
831 const TargetLowering *TLI = getTargetLowering();
832 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
833 if (unsigned Reg = TLI->getExceptionPointerRegister())
834 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
836 // Mark exception selector register as live in.
837 if (unsigned Reg = TLI->getExceptionSelectorRegister())
838 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
841 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
842 /// side-effect free and is either dead or folded into a generated instruction.
843 /// Return false if it needs to be emitted.
844 static bool isFoldedOrDeadInstruction(const Instruction *I,
845 FunctionLoweringInfo *FuncInfo) {
846 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
847 !isa<TerminatorInst>(I) && // Terminators aren't folded.
848 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
849 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
850 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
854 // Collect per Instruction statistics for fast-isel misses. Only those
855 // instructions that cause the bail are accounted for. It does not account for
856 // instructions higher in the block. Thus, summing the per instructions stats
857 // will not add up to what is reported by NumFastIselFailures.
858 static void collectFailStats(const Instruction *I) {
859 switch (I->getOpcode()) {
860 default: assert (0 && "<Invalid operator> ");
863 case Instruction::Ret: NumFastIselFailRet++; return;
864 case Instruction::Br: NumFastIselFailBr++; return;
865 case Instruction::Switch: NumFastIselFailSwitch++; return;
866 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
867 case Instruction::Invoke: NumFastIselFailInvoke++; return;
868 case Instruction::Resume: NumFastIselFailResume++; return;
869 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
871 // Standard binary operators...
872 case Instruction::Add: NumFastIselFailAdd++; return;
873 case Instruction::FAdd: NumFastIselFailFAdd++; return;
874 case Instruction::Sub: NumFastIselFailSub++; return;
875 case Instruction::FSub: NumFastIselFailFSub++; return;
876 case Instruction::Mul: NumFastIselFailMul++; return;
877 case Instruction::FMul: NumFastIselFailFMul++; return;
878 case Instruction::UDiv: NumFastIselFailUDiv++; return;
879 case Instruction::SDiv: NumFastIselFailSDiv++; return;
880 case Instruction::FDiv: NumFastIselFailFDiv++; return;
881 case Instruction::URem: NumFastIselFailURem++; return;
882 case Instruction::SRem: NumFastIselFailSRem++; return;
883 case Instruction::FRem: NumFastIselFailFRem++; return;
885 // Logical operators...
886 case Instruction::And: NumFastIselFailAnd++; return;
887 case Instruction::Or: NumFastIselFailOr++; return;
888 case Instruction::Xor: NumFastIselFailXor++; return;
890 // Memory instructions...
891 case Instruction::Alloca: NumFastIselFailAlloca++; return;
892 case Instruction::Load: NumFastIselFailLoad++; return;
893 case Instruction::Store: NumFastIselFailStore++; return;
894 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
895 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
896 case Instruction::Fence: NumFastIselFailFence++; return;
897 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
899 // Convert instructions...
900 case Instruction::Trunc: NumFastIselFailTrunc++; return;
901 case Instruction::ZExt: NumFastIselFailZExt++; return;
902 case Instruction::SExt: NumFastIselFailSExt++; return;
903 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
904 case Instruction::FPExt: NumFastIselFailFPExt++; return;
905 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
906 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
907 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
908 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
909 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
910 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
911 case Instruction::BitCast: NumFastIselFailBitCast++; return;
913 // Other instructions...
914 case Instruction::ICmp: NumFastIselFailICmp++; return;
915 case Instruction::FCmp: NumFastIselFailFCmp++; return;
916 case Instruction::PHI: NumFastIselFailPHI++; return;
917 case Instruction::Select: NumFastIselFailSelect++; return;
918 case Instruction::Call: NumFastIselFailCall++; return;
919 case Instruction::Shl: NumFastIselFailShl++; return;
920 case Instruction::LShr: NumFastIselFailLShr++; return;
921 case Instruction::AShr: NumFastIselFailAShr++; return;
922 case Instruction::VAArg: NumFastIselFailVAArg++; return;
923 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
924 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
925 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
926 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
927 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
928 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
933 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
934 // Initialize the Fast-ISel state, if needed.
935 FastISel *FastIS = 0;
936 if (TM.Options.EnableFastISel)
937 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo);
939 // Iterate over all basic blocks in the function.
940 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
941 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
942 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
943 const BasicBlock *LLVMBB = *I;
945 if (OptLevel != CodeGenOpt::None) {
946 bool AllPredsVisited = true;
947 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
949 if (!FuncInfo->VisitedBBs.count(*PI)) {
950 AllPredsVisited = false;
955 if (AllPredsVisited) {
956 for (BasicBlock::const_iterator I = LLVMBB->begin();
957 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
958 FuncInfo->ComputePHILiveOutRegInfo(PN);
960 for (BasicBlock::const_iterator I = LLVMBB->begin();
961 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
962 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
965 FuncInfo->VisitedBBs.insert(LLVMBB);
968 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
969 BasicBlock::const_iterator const End = LLVMBB->end();
970 BasicBlock::const_iterator BI = End;
972 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
973 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
975 // Setup an EH landing-pad block.
976 FuncInfo->ExceptionPointerVirtReg = 0;
977 FuncInfo->ExceptionSelectorVirtReg = 0;
978 if (FuncInfo->MBB->isLandingPad())
979 PrepareEHLandingPad();
981 // Before doing SelectionDAG ISel, see if FastISel has been requested.
983 FastIS->startNewBlock();
985 // Emit code for any incoming arguments. This must happen before
986 // beginning FastISel on the entry block.
987 if (LLVMBB == &Fn.getEntryBlock()) {
990 // Lower any arguments needed in this block if this is the entry block.
991 if (!FastIS->LowerArguments()) {
992 // Fast isel failed to lower these arguments
993 ++NumFastIselFailLowerArguments;
994 if (EnableFastISelAbortArgs)
995 llvm_unreachable("FastISel didn't lower all arguments");
997 // Use SelectionDAG argument lowering
999 CurDAG->setRoot(SDB->getControlRoot());
1001 CodeGenAndEmitDAG();
1004 // If we inserted any instructions at the beginning, make a note of
1005 // where they are, so we can be sure to emit subsequent instructions
1007 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1008 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1010 FastIS->setLastLocalValue(0);
1013 unsigned NumFastIselRemaining = std::distance(Begin, End);
1014 // Do FastISel on as many instructions as possible.
1015 for (; BI != Begin; --BI) {
1016 const Instruction *Inst = llvm::prior(BI);
1018 // If we no longer require this instruction, skip it.
1019 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1020 --NumFastIselRemaining;
1024 // Bottom-up: reset the insert pos at the top, after any local-value
1026 FastIS->recomputeInsertPt();
1028 // Try to select the instruction with FastISel.
1029 if (FastIS->SelectInstruction(Inst)) {
1030 --NumFastIselRemaining;
1031 ++NumFastIselSuccess;
1032 // If fast isel succeeded, skip over all the folded instructions, and
1033 // then see if there is a load right before the selected instructions.
1034 // Try to fold the load if so.
1035 const Instruction *BeforeInst = Inst;
1036 while (BeforeInst != Begin) {
1037 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1038 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1041 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1042 BeforeInst->hasOneUse() &&
1043 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1044 // If we succeeded, don't re-select the load.
1045 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1046 --NumFastIselRemaining;
1047 ++NumFastIselSuccess;
1053 if (EnableFastISelVerbose2)
1054 collectFailStats(Inst);
1057 // Then handle certain instructions as single-LLVM-Instruction blocks.
1058 if (isa<CallInst>(Inst)) {
1060 if (EnableFastISelVerbose || EnableFastISelAbort) {
1061 dbgs() << "FastISel missed call: ";
1065 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1066 unsigned &R = FuncInfo->ValueMap[Inst];
1068 R = FuncInfo->CreateRegs(Inst->getType());
1071 bool HadTailCall = false;
1072 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1073 SelectBasicBlock(Inst, BI, HadTailCall);
1075 // If the call was emitted as a tail call, we're done with the block.
1076 // We also need to delete any previously emitted instructions.
1078 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1083 // Recompute NumFastIselRemaining as Selection DAG instruction
1084 // selection may have handled the call, input args, etc.
1085 unsigned RemainingNow = std::distance(Begin, BI);
1086 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1087 NumFastIselRemaining = RemainingNow;
1091 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1092 // Don't abort, and use a different message for terminator misses.
1093 NumFastIselFailures += NumFastIselRemaining;
1094 if (EnableFastISelVerbose || EnableFastISelAbort) {
1095 dbgs() << "FastISel missed terminator: ";
1099 NumFastIselFailures += NumFastIselRemaining;
1100 if (EnableFastISelVerbose || EnableFastISelAbort) {
1101 dbgs() << "FastISel miss: ";
1104 if (EnableFastISelAbort)
1105 // The "fast" selector couldn't handle something and bailed.
1106 // For the purpose of debugging, just abort.
1107 llvm_unreachable("FastISel didn't select the entire block");
1112 FastIS->recomputeInsertPt();
1114 // Lower any arguments needed in this block if this is the entry block.
1115 if (LLVMBB == &Fn.getEntryBlock()) {
1124 ++NumFastIselBlocks;
1127 // Run SelectionDAG instruction selection on the remainder of the block
1128 // not handled by FastISel. If FastISel is not run, this is the entire
1131 SelectBasicBlock(Begin, BI, HadTailCall);
1135 FuncInfo->PHINodesToUpdate.clear();
1139 SDB->clearDanglingDebugInfo();
1143 SelectionDAGISel::FinishBasicBlock() {
1145 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1146 << FuncInfo->PHINodesToUpdate.size() << "\n";
1147 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1148 dbgs() << "Node " << i << " : ("
1149 << FuncInfo->PHINodesToUpdate[i].first
1150 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1152 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1153 // PHI nodes in successors.
1154 if (SDB->SwitchCases.empty() &&
1155 SDB->JTCases.empty() &&
1156 SDB->BitTestCases.empty()) {
1157 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1158 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1159 assert(PHI->isPHI() &&
1160 "This is not a machine PHI node that we are updating!");
1161 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1163 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1168 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1169 // Lower header first, if it wasn't already lowered
1170 if (!SDB->BitTestCases[i].Emitted) {
1171 // Set the current basic block to the mbb we wish to insert the code into
1172 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1173 FuncInfo->InsertPt = FuncInfo->MBB->end();
1175 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1176 CurDAG->setRoot(SDB->getRoot());
1178 CodeGenAndEmitDAG();
1181 uint32_t UnhandledWeight = 0;
1182 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1183 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1185 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1186 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1187 // Set the current basic block to the mbb we wish to insert the code into
1188 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1189 FuncInfo->InsertPt = FuncInfo->MBB->end();
1192 SDB->visitBitTestCase(SDB->BitTestCases[i],
1193 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1195 SDB->BitTestCases[i].Reg,
1196 SDB->BitTestCases[i].Cases[j],
1199 SDB->visitBitTestCase(SDB->BitTestCases[i],
1200 SDB->BitTestCases[i].Default,
1202 SDB->BitTestCases[i].Reg,
1203 SDB->BitTestCases[i].Cases[j],
1207 CurDAG->setRoot(SDB->getRoot());
1209 CodeGenAndEmitDAG();
1213 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1215 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1216 MachineBasicBlock *PHIBB = PHI->getParent();
1217 assert(PHI->isPHI() &&
1218 "This is not a machine PHI node that we are updating!");
1219 // This is "default" BB. We have two jumps to it. From "header" BB and
1220 // from last "case" BB.
1221 if (PHIBB == SDB->BitTestCases[i].Default)
1222 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1223 .addMBB(SDB->BitTestCases[i].Parent)
1224 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1225 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1226 // One of "cases" BB.
1227 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1229 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1230 if (cBB->isSuccessor(PHIBB))
1231 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1235 SDB->BitTestCases.clear();
1237 // If the JumpTable record is filled in, then we need to emit a jump table.
1238 // Updating the PHI nodes is tricky in this case, since we need to determine
1239 // whether the PHI is a successor of the range check MBB or the jump table MBB
1240 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1241 // Lower header first, if it wasn't already lowered
1242 if (!SDB->JTCases[i].first.Emitted) {
1243 // Set the current basic block to the mbb we wish to insert the code into
1244 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1245 FuncInfo->InsertPt = FuncInfo->MBB->end();
1247 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1249 CurDAG->setRoot(SDB->getRoot());
1251 CodeGenAndEmitDAG();
1254 // Set the current basic block to the mbb we wish to insert the code into
1255 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1256 FuncInfo->InsertPt = FuncInfo->MBB->end();
1258 SDB->visitJumpTable(SDB->JTCases[i].second);
1259 CurDAG->setRoot(SDB->getRoot());
1261 CodeGenAndEmitDAG();
1264 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1266 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1267 MachineBasicBlock *PHIBB = PHI->getParent();
1268 assert(PHI->isPHI() &&
1269 "This is not a machine PHI node that we are updating!");
1270 // "default" BB. We can go there only from header BB.
1271 if (PHIBB == SDB->JTCases[i].second.Default)
1272 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1273 .addMBB(SDB->JTCases[i].first.HeaderBB);
1274 // JT BB. Just iterate over successors here
1275 if (FuncInfo->MBB->isSuccessor(PHIBB))
1276 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1279 SDB->JTCases.clear();
1281 // If the switch block involved a branch to one of the actual successors, we
1282 // need to update PHI nodes in that block.
1283 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1284 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1285 assert(PHI->isPHI() &&
1286 "This is not a machine PHI node that we are updating!");
1287 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1288 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1291 // If we generated any switch lowering information, build and codegen any
1292 // additional DAGs necessary.
1293 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1294 // Set the current basic block to the mbb we wish to insert the code into
1295 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1296 FuncInfo->InsertPt = FuncInfo->MBB->end();
1298 // Determine the unique successors.
1299 SmallVector<MachineBasicBlock *, 2> Succs;
1300 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1301 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1302 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1304 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1305 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1306 CurDAG->setRoot(SDB->getRoot());
1308 CodeGenAndEmitDAG();
1310 // Remember the last block, now that any splitting is done, for use in
1311 // populating PHI nodes in successors.
1312 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1314 // Handle any PHI nodes in successors of this chunk, as if we were coming
1315 // from the original BB before switch expansion. Note that PHI nodes can
1316 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1317 // handle them the right number of times.
1318 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1319 FuncInfo->MBB = Succs[i];
1320 FuncInfo->InsertPt = FuncInfo->MBB->end();
1321 // FuncInfo->MBB may have been removed from the CFG if a branch was
1323 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1324 for (MachineBasicBlock::iterator
1325 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1326 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1327 MachineInstrBuilder PHI(*MF, MBBI);
1328 // This value for this PHI node is recorded in PHINodesToUpdate.
1329 for (unsigned pn = 0; ; ++pn) {
1330 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1331 "Didn't find PHI entry!");
1332 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1333 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1341 SDB->SwitchCases.clear();
1345 /// Create the scheduler. If a specific scheduler was specified
1346 /// via the SchedulerRegistry, use it, otherwise select the
1347 /// one preferred by the target.
1349 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1350 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1354 RegisterScheduler::setDefault(Ctor);
1357 return Ctor(this, OptLevel);
1360 //===----------------------------------------------------------------------===//
1361 // Helper functions used by the generated instruction selector.
1362 //===----------------------------------------------------------------------===//
1363 // Calls to these methods are generated by tblgen.
1365 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1366 /// the dag combiner simplified the 255, we still want to match. RHS is the
1367 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1368 /// specified in the .td file (e.g. 255).
1369 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1370 int64_t DesiredMaskS) const {
1371 const APInt &ActualMask = RHS->getAPIntValue();
1372 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1374 // If the actual mask exactly matches, success!
1375 if (ActualMask == DesiredMask)
1378 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1379 if (ActualMask.intersects(~DesiredMask))
1382 // Otherwise, the DAG Combiner may have proven that the value coming in is
1383 // either already zero or is not demanded. Check for known zero input bits.
1384 APInt NeededMask = DesiredMask & ~ActualMask;
1385 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1388 // TODO: check to see if missing bits are just not demanded.
1390 // Otherwise, this pattern doesn't match.
1394 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1395 /// the dag combiner simplified the 255, we still want to match. RHS is the
1396 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1397 /// specified in the .td file (e.g. 255).
1398 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1399 int64_t DesiredMaskS) const {
1400 const APInt &ActualMask = RHS->getAPIntValue();
1401 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1403 // If the actual mask exactly matches, success!
1404 if (ActualMask == DesiredMask)
1407 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1408 if (ActualMask.intersects(~DesiredMask))
1411 // Otherwise, the DAG Combiner may have proven that the value coming in is
1412 // either already zero or is not demanded. Check for known zero input bits.
1413 APInt NeededMask = DesiredMask & ~ActualMask;
1415 APInt KnownZero, KnownOne;
1416 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1418 // If all the missing bits in the or are already known to be set, match!
1419 if ((NeededMask & KnownOne) == NeededMask)
1422 // TODO: check to see if missing bits are just not demanded.
1424 // Otherwise, this pattern doesn't match.
1429 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1430 /// by tblgen. Others should not call it.
1431 void SelectionDAGISel::
1432 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1433 std::vector<SDValue> InOps;
1434 std::swap(InOps, Ops);
1436 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1437 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1438 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1439 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1441 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1442 if (InOps[e-1].getValueType() == MVT::Glue)
1443 --e; // Don't process a glue operand if it is here.
1446 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1447 if (!InlineAsm::isMemKind(Flags)) {
1448 // Just skip over this operand, copying the operands verbatim.
1449 Ops.insert(Ops.end(), InOps.begin()+i,
1450 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1451 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1453 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1454 "Memory operand with multiple values?");
1455 // Otherwise, this is a memory operand. Ask the target to select it.
1456 std::vector<SDValue> SelOps;
1457 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1458 report_fatal_error("Could not match memory address. Inline asm"
1461 // Add this to the output node.
1463 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1464 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1465 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1470 // Add the glue input back if present.
1471 if (e != InOps.size())
1472 Ops.push_back(InOps.back());
1475 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1478 static SDNode *findGlueUse(SDNode *N) {
1479 unsigned FlagResNo = N->getNumValues()-1;
1480 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1481 SDUse &Use = I.getUse();
1482 if (Use.getResNo() == FlagResNo)
1483 return Use.getUser();
1488 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1489 /// This function recursively traverses up the operand chain, ignoring
1491 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1492 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1493 bool IgnoreChains) {
1494 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1495 // greater than all of its (recursive) operands. If we scan to a point where
1496 // 'use' is smaller than the node we're scanning for, then we know we will
1499 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1500 // happen because we scan down to newly selected nodes in the case of glue
1502 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1505 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1506 // won't fail if we scan it again.
1507 if (!Visited.insert(Use))
1510 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1511 // Ignore chain uses, they are validated by HandleMergeInputChains.
1512 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1515 SDNode *N = Use->getOperand(i).getNode();
1517 if (Use == ImmedUse || Use == Root)
1518 continue; // We are not looking for immediate use.
1523 // Traverse up the operand chain.
1524 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1530 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1531 /// operand node N of U during instruction selection that starts at Root.
1532 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1533 SDNode *Root) const {
1534 if (OptLevel == CodeGenOpt::None) return false;
1535 return N.hasOneUse();
1538 /// IsLegalToFold - Returns true if the specific operand node N of
1539 /// U can be folded during instruction selection that starts at Root.
1540 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1541 CodeGenOpt::Level OptLevel,
1542 bool IgnoreChains) {
1543 if (OptLevel == CodeGenOpt::None) return false;
1545 // If Root use can somehow reach N through a path that that doesn't contain
1546 // U then folding N would create a cycle. e.g. In the following
1547 // diagram, Root can reach N through X. If N is folded into into Root, then
1548 // X is both a predecessor and a successor of U.
1559 // * indicates nodes to be folded together.
1561 // If Root produces glue, then it gets (even more) interesting. Since it
1562 // will be "glued" together with its glue use in the scheduler, we need to
1563 // check if it might reach N.
1582 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1583 // (call it Fold), then X is a predecessor of GU and a successor of
1584 // Fold. But since Fold and GU are glued together, this will create
1585 // a cycle in the scheduling graph.
1587 // If the node has glue, walk down the graph to the "lowest" node in the
1589 EVT VT = Root->getValueType(Root->getNumValues()-1);
1590 while (VT == MVT::Glue) {
1591 SDNode *GU = findGlueUse(Root);
1595 VT = Root->getValueType(Root->getNumValues()-1);
1597 // If our query node has a glue result with a use, we've walked up it. If
1598 // the user (which has already been selected) has a chain or indirectly uses
1599 // the chain, our WalkChainUsers predicate will not consider it. Because of
1600 // this, we cannot ignore chains in this predicate.
1601 IgnoreChains = false;
1605 SmallPtrSet<SDNode*, 16> Visited;
1606 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1609 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1610 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1611 SelectInlineAsmMemoryOperands(Ops);
1613 EVT VTs[] = { MVT::Other, MVT::Glue };
1614 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
1615 VTs, &Ops[0], Ops.size());
1617 return New.getNode();
1620 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1621 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1624 /// GetVBR - decode a vbr encoding whose top bit is set.
1625 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1626 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1627 assert(Val >= 128 && "Not a VBR");
1628 Val &= 127; // Remove first vbr bit.
1633 NextBits = MatcherTable[Idx++];
1634 Val |= (NextBits&127) << Shift;
1636 } while (NextBits & 128);
1642 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1643 /// interior glue and chain results to use the new glue and chain results.
1644 void SelectionDAGISel::
1645 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1646 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1648 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1649 bool isMorphNodeTo) {
1650 SmallVector<SDNode*, 4> NowDeadNodes;
1652 // Now that all the normal results are replaced, we replace the chain and
1653 // glue results if present.
1654 if (!ChainNodesMatched.empty()) {
1655 assert(InputChain.getNode() != 0 &&
1656 "Matched input chains but didn't produce a chain");
1657 // Loop over all of the nodes we matched that produced a chain result.
1658 // Replace all the chain results with the final chain we ended up with.
1659 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1660 SDNode *ChainNode = ChainNodesMatched[i];
1662 // If this node was already deleted, don't look at it.
1663 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1666 // Don't replace the results of the root node if we're doing a
1668 if (ChainNode == NodeToMatch && isMorphNodeTo)
1671 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1672 if (ChainVal.getValueType() == MVT::Glue)
1673 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1674 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1675 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1677 // If the node became dead and we haven't already seen it, delete it.
1678 if (ChainNode->use_empty() &&
1679 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1680 NowDeadNodes.push_back(ChainNode);
1684 // If the result produces glue, update any glue results in the matched
1685 // pattern with the glue result.
1686 if (InputGlue.getNode() != 0) {
1687 // Handle any interior nodes explicitly marked.
1688 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1689 SDNode *FRN = GlueResultNodesMatched[i];
1691 // If this node was already deleted, don't look at it.
1692 if (FRN->getOpcode() == ISD::DELETED_NODE)
1695 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1696 "Doesn't have a glue result");
1697 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1700 // If the node became dead and we haven't already seen it, delete it.
1701 if (FRN->use_empty() &&
1702 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1703 NowDeadNodes.push_back(FRN);
1707 if (!NowDeadNodes.empty())
1708 CurDAG->RemoveDeadNodes(NowDeadNodes);
1710 DEBUG(dbgs() << "ISEL: Match complete!\n");
1716 CR_LeadsToInteriorNode
1719 /// WalkChainUsers - Walk down the users of the specified chained node that is
1720 /// part of the pattern we're matching, looking at all of the users we find.
1721 /// This determines whether something is an interior node, whether we have a
1722 /// non-pattern node in between two pattern nodes (which prevent folding because
1723 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1724 /// between pattern nodes (in which case the TF becomes part of the pattern).
1726 /// The walk we do here is guaranteed to be small because we quickly get down to
1727 /// already selected nodes "below" us.
1729 WalkChainUsers(const SDNode *ChainedNode,
1730 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1731 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1732 ChainResult Result = CR_Simple;
1734 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1735 E = ChainedNode->use_end(); UI != E; ++UI) {
1736 // Make sure the use is of the chain, not some other value we produce.
1737 if (UI.getUse().getValueType() != MVT::Other) continue;
1741 // If we see an already-selected machine node, then we've gone beyond the
1742 // pattern that we're selecting down into the already selected chunk of the
1744 if (User->isMachineOpcode() ||
1745 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1748 unsigned UserOpcode = User->getOpcode();
1749 if (UserOpcode == ISD::CopyToReg ||
1750 UserOpcode == ISD::CopyFromReg ||
1751 UserOpcode == ISD::INLINEASM ||
1752 UserOpcode == ISD::EH_LABEL ||
1753 UserOpcode == ISD::LIFETIME_START ||
1754 UserOpcode == ISD::LIFETIME_END) {
1755 // If their node ID got reset to -1 then they've already been selected.
1756 // Treat them like a MachineOpcode.
1757 if (User->getNodeId() == -1)
1761 // If we have a TokenFactor, we handle it specially.
1762 if (User->getOpcode() != ISD::TokenFactor) {
1763 // If the node isn't a token factor and isn't part of our pattern, then it
1764 // must be a random chained node in between two nodes we're selecting.
1765 // This happens when we have something like:
1770 // Because we structurally match the load/store as a read/modify/write,
1771 // but the call is chained between them. We cannot fold in this case
1772 // because it would induce a cycle in the graph.
1773 if (!std::count(ChainedNodesInPattern.begin(),
1774 ChainedNodesInPattern.end(), User))
1775 return CR_InducesCycle;
1777 // Otherwise we found a node that is part of our pattern. For example in:
1781 // This would happen when we're scanning down from the load and see the
1782 // store as a user. Record that there is a use of ChainedNode that is
1783 // part of the pattern and keep scanning uses.
1784 Result = CR_LeadsToInteriorNode;
1785 InteriorChainedNodes.push_back(User);
1789 // If we found a TokenFactor, there are two cases to consider: first if the
1790 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1791 // uses of the TF are in our pattern) we just want to ignore it. Second,
1792 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1798 // | \ DAG's like cheese
1801 // [TokenFactor] [Op]
1808 // In this case, the TokenFactor becomes part of our match and we rewrite it
1809 // as a new TokenFactor.
1811 // To distinguish these two cases, do a recursive walk down the uses.
1812 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1814 // If the uses of the TokenFactor are just already-selected nodes, ignore
1815 // it, it is "below" our pattern.
1817 case CR_InducesCycle:
1818 // If the uses of the TokenFactor lead to nodes that are not part of our
1819 // pattern that are not selected, folding would turn this into a cycle,
1821 return CR_InducesCycle;
1822 case CR_LeadsToInteriorNode:
1823 break; // Otherwise, keep processing.
1826 // Okay, we know we're in the interesting interior case. The TokenFactor
1827 // is now going to be considered part of the pattern so that we rewrite its
1828 // uses (it may have uses that are not part of the pattern) with the
1829 // ultimate chain result of the generated code. We will also add its chain
1830 // inputs as inputs to the ultimate TokenFactor we create.
1831 Result = CR_LeadsToInteriorNode;
1832 ChainedNodesInPattern.push_back(User);
1833 InteriorChainedNodes.push_back(User);
1840 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1841 /// operation for when the pattern matched at least one node with a chains. The
1842 /// input vector contains a list of all of the chained nodes that we match. We
1843 /// must determine if this is a valid thing to cover (i.e. matching it won't
1844 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1845 /// be used as the input node chain for the generated nodes.
1847 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1848 SelectionDAG *CurDAG) {
1849 // Walk all of the chained nodes we've matched, recursively scanning down the
1850 // users of the chain result. This adds any TokenFactor nodes that are caught
1851 // in between chained nodes to the chained and interior nodes list.
1852 SmallVector<SDNode*, 3> InteriorChainedNodes;
1853 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1854 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1855 InteriorChainedNodes) == CR_InducesCycle)
1856 return SDValue(); // Would induce a cycle.
1859 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1860 // that we are interested in. Form our input TokenFactor node.
1861 SmallVector<SDValue, 3> InputChains;
1862 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1863 // Add the input chain of this node to the InputChains list (which will be
1864 // the operands of the generated TokenFactor) if it's not an interior node.
1865 SDNode *N = ChainNodesMatched[i];
1866 if (N->getOpcode() != ISD::TokenFactor) {
1867 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1870 // Otherwise, add the input chain.
1871 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1872 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1873 InputChains.push_back(InChain);
1877 // If we have a token factor, we want to add all inputs of the token factor
1878 // that are not part of the pattern we're matching.
1879 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1880 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1881 N->getOperand(op).getNode()))
1882 InputChains.push_back(N->getOperand(op));
1887 if (InputChains.size() == 1)
1888 return InputChains[0];
1889 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
1890 MVT::Other, &InputChains[0], InputChains.size());
1893 /// MorphNode - Handle morphing a node in place for the selector.
1894 SDNode *SelectionDAGISel::
1895 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1896 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1897 // It is possible we're using MorphNodeTo to replace a node with no
1898 // normal results with one that has a normal result (or we could be
1899 // adding a chain) and the input could have glue and chains as well.
1900 // In this case we need to shift the operands down.
1901 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1902 // than the old isel though.
1903 int OldGlueResultNo = -1, OldChainResultNo = -1;
1905 unsigned NTMNumResults = Node->getNumValues();
1906 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1907 OldGlueResultNo = NTMNumResults-1;
1908 if (NTMNumResults != 1 &&
1909 Node->getValueType(NTMNumResults-2) == MVT::Other)
1910 OldChainResultNo = NTMNumResults-2;
1911 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1912 OldChainResultNo = NTMNumResults-1;
1914 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1915 // that this deletes operands of the old node that become dead.
1916 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1918 // MorphNodeTo can operate in two ways: if an existing node with the
1919 // specified operands exists, it can just return it. Otherwise, it
1920 // updates the node in place to have the requested operands.
1922 // If we updated the node in place, reset the node ID. To the isel,
1923 // this should be just like a newly allocated machine node.
1927 unsigned ResNumResults = Res->getNumValues();
1928 // Move the glue if needed.
1929 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1930 (unsigned)OldGlueResultNo != ResNumResults-1)
1931 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1932 SDValue(Res, ResNumResults-1));
1934 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1937 // Move the chain reference if needed.
1938 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1939 (unsigned)OldChainResultNo != ResNumResults-1)
1940 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1941 SDValue(Res, ResNumResults-1));
1943 // Otherwise, no replacement happened because the node already exists. Replace
1944 // Uses of the old node with the new one.
1946 CurDAG->ReplaceAllUsesWith(Node, Res);
1951 /// CheckSame - Implements OP_CheckSame.
1952 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1953 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1955 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1956 // Accept if it is exactly the same as a previously recorded node.
1957 unsigned RecNo = MatcherTable[MatcherIndex++];
1958 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1959 return N == RecordedNodes[RecNo].first;
1962 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1963 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1964 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1965 const SelectionDAGISel &SDISel) {
1966 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1969 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1970 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1971 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1972 const SelectionDAGISel &SDISel, SDNode *N) {
1973 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1976 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1977 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1979 uint16_t Opc = MatcherTable[MatcherIndex++];
1980 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1981 return N->getOpcode() == Opc;
1984 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1985 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1986 SDValue N, const TargetLowering *TLI) {
1987 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1988 if (N.getValueType() == VT) return true;
1990 // Handle the case when VT is iPTR.
1991 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
1994 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1995 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1996 SDValue N, const TargetLowering *TLI,
1998 if (ChildNo >= N.getNumOperands())
1999 return false; // Match fails if out of range child #.
2000 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2003 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2004 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2006 return cast<CondCodeSDNode>(N)->get() ==
2007 (ISD::CondCode)MatcherTable[MatcherIndex++];
2010 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2011 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2012 SDValue N, const TargetLowering *TLI) {
2013 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2014 if (cast<VTSDNode>(N)->getVT() == VT)
2017 // Handle the case when VT is iPTR.
2018 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2021 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2022 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2024 int64_t Val = MatcherTable[MatcherIndex++];
2026 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2028 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2029 return C != 0 && C->getSExtValue() == Val;
2032 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2033 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2034 SDValue N, const SelectionDAGISel &SDISel) {
2035 int64_t Val = MatcherTable[MatcherIndex++];
2037 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2039 if (N->getOpcode() != ISD::AND) return false;
2041 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2042 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2045 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2046 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2047 SDValue N, const SelectionDAGISel &SDISel) {
2048 int64_t Val = MatcherTable[MatcherIndex++];
2050 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2052 if (N->getOpcode() != ISD::OR) return false;
2054 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2055 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2058 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2059 /// scope, evaluate the current node. If the current predicate is known to
2060 /// fail, set Result=true and return anything. If the current predicate is
2061 /// known to pass, set Result=false and return the MatcherIndex to continue
2062 /// with. If the current predicate is unknown, set Result=false and return the
2063 /// MatcherIndex to continue with.
2064 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2065 unsigned Index, SDValue N,
2067 const SelectionDAGISel &SDISel,
2068 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2069 switch (Table[Index++]) {
2072 return Index-1; // Could not evaluate this predicate.
2073 case SelectionDAGISel::OPC_CheckSame:
2074 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2076 case SelectionDAGISel::OPC_CheckPatternPredicate:
2077 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2079 case SelectionDAGISel::OPC_CheckPredicate:
2080 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2082 case SelectionDAGISel::OPC_CheckOpcode:
2083 Result = !::CheckOpcode(Table, Index, N.getNode());
2085 case SelectionDAGISel::OPC_CheckType:
2086 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering());
2088 case SelectionDAGISel::OPC_CheckChild0Type:
2089 case SelectionDAGISel::OPC_CheckChild1Type:
2090 case SelectionDAGISel::OPC_CheckChild2Type:
2091 case SelectionDAGISel::OPC_CheckChild3Type:
2092 case SelectionDAGISel::OPC_CheckChild4Type:
2093 case SelectionDAGISel::OPC_CheckChild5Type:
2094 case SelectionDAGISel::OPC_CheckChild6Type:
2095 case SelectionDAGISel::OPC_CheckChild7Type:
2096 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(),
2097 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2099 case SelectionDAGISel::OPC_CheckCondCode:
2100 Result = !::CheckCondCode(Table, Index, N);
2102 case SelectionDAGISel::OPC_CheckValueType:
2103 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering());
2105 case SelectionDAGISel::OPC_CheckInteger:
2106 Result = !::CheckInteger(Table, Index, N);
2108 case SelectionDAGISel::OPC_CheckAndImm:
2109 Result = !::CheckAndImm(Table, Index, N, SDISel);
2111 case SelectionDAGISel::OPC_CheckOrImm:
2112 Result = !::CheckOrImm(Table, Index, N, SDISel);
2120 /// FailIndex - If this match fails, this is the index to continue with.
2123 /// NodeStack - The node stack when the scope was formed.
2124 SmallVector<SDValue, 4> NodeStack;
2126 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2127 unsigned NumRecordedNodes;
2129 /// NumMatchedMemRefs - The number of matched memref entries.
2130 unsigned NumMatchedMemRefs;
2132 /// InputChain/InputGlue - The current chain/glue
2133 SDValue InputChain, InputGlue;
2135 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2136 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2141 SDNode *SelectionDAGISel::
2142 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2143 unsigned TableSize) {
2144 // FIXME: Should these even be selected? Handle these cases in the caller?
2145 switch (NodeToMatch->getOpcode()) {
2148 case ISD::EntryToken: // These nodes remain the same.
2149 case ISD::BasicBlock:
2151 case ISD::RegisterMask:
2152 //case ISD::VALUETYPE:
2153 //case ISD::CONDCODE:
2154 case ISD::HANDLENODE:
2155 case ISD::MDNODE_SDNODE:
2156 case ISD::TargetConstant:
2157 case ISD::TargetConstantFP:
2158 case ISD::TargetConstantPool:
2159 case ISD::TargetFrameIndex:
2160 case ISD::TargetExternalSymbol:
2161 case ISD::TargetBlockAddress:
2162 case ISD::TargetJumpTable:
2163 case ISD::TargetGlobalTLSAddress:
2164 case ISD::TargetGlobalAddress:
2165 case ISD::TokenFactor:
2166 case ISD::CopyFromReg:
2167 case ISD::CopyToReg:
2169 case ISD::LIFETIME_START:
2170 case ISD::LIFETIME_END:
2171 NodeToMatch->setNodeId(-1); // Mark selected.
2173 case ISD::AssertSext:
2174 case ISD::AssertZext:
2175 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2176 NodeToMatch->getOperand(0));
2178 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2179 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2182 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2184 // Set up the node stack with NodeToMatch as the only node on the stack.
2185 SmallVector<SDValue, 8> NodeStack;
2186 SDValue N = SDValue(NodeToMatch, 0);
2187 NodeStack.push_back(N);
2189 // MatchScopes - Scopes used when matching, if a match failure happens, this
2190 // indicates where to continue checking.
2191 SmallVector<MatchScope, 8> MatchScopes;
2193 // RecordedNodes - This is the set of nodes that have been recorded by the
2194 // state machine. The second value is the parent of the node, or null if the
2195 // root is recorded.
2196 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2198 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2200 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2202 // These are the current input chain and glue for use when generating nodes.
2203 // Various Emit operations change these. For example, emitting a copytoreg
2204 // uses and updates these.
2205 SDValue InputChain, InputGlue;
2207 // ChainNodesMatched - If a pattern matches nodes that have input/output
2208 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2209 // which ones they are. The result is captured into this list so that we can
2210 // update the chain results when the pattern is complete.
2211 SmallVector<SDNode*, 3> ChainNodesMatched;
2212 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2214 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2215 NodeToMatch->dump(CurDAG);
2218 // Determine where to start the interpreter. Normally we start at opcode #0,
2219 // but if the state machine starts with an OPC_SwitchOpcode, then we
2220 // accelerate the first lookup (which is guaranteed to be hot) with the
2221 // OpcodeOffset table.
2222 unsigned MatcherIndex = 0;
2224 if (!OpcodeOffset.empty()) {
2225 // Already computed the OpcodeOffset table, just index into it.
2226 if (N.getOpcode() < OpcodeOffset.size())
2227 MatcherIndex = OpcodeOffset[N.getOpcode()];
2228 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2230 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2231 // Otherwise, the table isn't computed, but the state machine does start
2232 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2233 // is the first time we're selecting an instruction.
2236 // Get the size of this case.
2237 unsigned CaseSize = MatcherTable[Idx++];
2239 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2240 if (CaseSize == 0) break;
2242 // Get the opcode, add the index to the table.
2243 uint16_t Opc = MatcherTable[Idx++];
2244 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2245 if (Opc >= OpcodeOffset.size())
2246 OpcodeOffset.resize((Opc+1)*2);
2247 OpcodeOffset[Opc] = Idx;
2251 // Okay, do the lookup for the first opcode.
2252 if (N.getOpcode() < OpcodeOffset.size())
2253 MatcherIndex = OpcodeOffset[N.getOpcode()];
2257 assert(MatcherIndex < TableSize && "Invalid index");
2259 unsigned CurrentOpcodeIndex = MatcherIndex;
2261 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2264 // Okay, the semantics of this operation are that we should push a scope
2265 // then evaluate the first child. However, pushing a scope only to have
2266 // the first check fail (which then pops it) is inefficient. If we can
2267 // determine immediately that the first check (or first several) will
2268 // immediately fail, don't even bother pushing a scope for them.
2272 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2273 if (NumToSkip & 128)
2274 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2275 // Found the end of the scope with no match.
2276 if (NumToSkip == 0) {
2281 FailIndex = MatcherIndex+NumToSkip;
2283 unsigned MatcherIndexOfPredicate = MatcherIndex;
2284 (void)MatcherIndexOfPredicate; // silence warning.
2286 // If we can't evaluate this predicate without pushing a scope (e.g. if
2287 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2288 // push the scope and evaluate the full predicate chain.
2290 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2291 Result, *this, RecordedNodes);
2295 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2296 << "index " << MatcherIndexOfPredicate
2297 << ", continuing at " << FailIndex << "\n");
2298 ++NumDAGIselRetries;
2300 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2301 // move to the next case.
2302 MatcherIndex = FailIndex;
2305 // If the whole scope failed to match, bail.
2306 if (FailIndex == 0) break;
2308 // Push a MatchScope which indicates where to go if the first child fails
2310 MatchScope NewEntry;
2311 NewEntry.FailIndex = FailIndex;
2312 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2313 NewEntry.NumRecordedNodes = RecordedNodes.size();
2314 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2315 NewEntry.InputChain = InputChain;
2316 NewEntry.InputGlue = InputGlue;
2317 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2318 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2319 MatchScopes.push_back(NewEntry);
2322 case OPC_RecordNode: {
2323 // Remember this node, it may end up being an operand in the pattern.
2325 if (NodeStack.size() > 1)
2326 Parent = NodeStack[NodeStack.size()-2].getNode();
2327 RecordedNodes.push_back(std::make_pair(N, Parent));
2331 case OPC_RecordChild0: case OPC_RecordChild1:
2332 case OPC_RecordChild2: case OPC_RecordChild3:
2333 case OPC_RecordChild4: case OPC_RecordChild5:
2334 case OPC_RecordChild6: case OPC_RecordChild7: {
2335 unsigned ChildNo = Opcode-OPC_RecordChild0;
2336 if (ChildNo >= N.getNumOperands())
2337 break; // Match fails if out of range child #.
2339 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2343 case OPC_RecordMemRef:
2344 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2347 case OPC_CaptureGlueInput:
2348 // If the current node has an input glue, capture it in InputGlue.
2349 if (N->getNumOperands() != 0 &&
2350 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2351 InputGlue = N->getOperand(N->getNumOperands()-1);
2354 case OPC_MoveChild: {
2355 unsigned ChildNo = MatcherTable[MatcherIndex++];
2356 if (ChildNo >= N.getNumOperands())
2357 break; // Match fails if out of range child #.
2358 N = N.getOperand(ChildNo);
2359 NodeStack.push_back(N);
2363 case OPC_MoveParent:
2364 // Pop the current node off the NodeStack.
2365 NodeStack.pop_back();
2366 assert(!NodeStack.empty() && "Node stack imbalance!");
2367 N = NodeStack.back();
2371 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2373 case OPC_CheckPatternPredicate:
2374 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2376 case OPC_CheckPredicate:
2377 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2381 case OPC_CheckComplexPat: {
2382 unsigned CPNum = MatcherTable[MatcherIndex++];
2383 unsigned RecNo = MatcherTable[MatcherIndex++];
2384 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2385 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2386 RecordedNodes[RecNo].first, CPNum,
2391 case OPC_CheckOpcode:
2392 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2396 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2400 case OPC_SwitchOpcode: {
2401 unsigned CurNodeOpcode = N.getOpcode();
2402 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2405 // Get the size of this case.
2406 CaseSize = MatcherTable[MatcherIndex++];
2408 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2409 if (CaseSize == 0) break;
2411 uint16_t Opc = MatcherTable[MatcherIndex++];
2412 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2414 // If the opcode matches, then we will execute this case.
2415 if (CurNodeOpcode == Opc)
2418 // Otherwise, skip over this case.
2419 MatcherIndex += CaseSize;
2422 // If no cases matched, bail out.
2423 if (CaseSize == 0) break;
2425 // Otherwise, execute the case we found.
2426 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2427 << " to " << MatcherIndex << "\n");
2431 case OPC_SwitchType: {
2432 MVT CurNodeVT = N.getValueType().getSimpleVT();
2433 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2436 // Get the size of this case.
2437 CaseSize = MatcherTable[MatcherIndex++];
2439 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2440 if (CaseSize == 0) break;
2442 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2443 if (CaseVT == MVT::iPTR)
2444 CaseVT = getTargetLowering()->getPointerTy();
2446 // If the VT matches, then we will execute this case.
2447 if (CurNodeVT == CaseVT)
2450 // Otherwise, skip over this case.
2451 MatcherIndex += CaseSize;
2454 // If no cases matched, bail out.
2455 if (CaseSize == 0) break;
2457 // Otherwise, execute the case we found.
2458 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2459 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2462 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2463 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2464 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2465 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2466 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(),
2467 Opcode-OPC_CheckChild0Type))
2470 case OPC_CheckCondCode:
2471 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2473 case OPC_CheckValueType:
2474 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2477 case OPC_CheckInteger:
2478 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2480 case OPC_CheckAndImm:
2481 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2483 case OPC_CheckOrImm:
2484 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2487 case OPC_CheckFoldableChainNode: {
2488 assert(NodeStack.size() != 1 && "No parent node");
2489 // Verify that all intermediate nodes between the root and this one have
2491 bool HasMultipleUses = false;
2492 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2493 if (!NodeStack[i].hasOneUse()) {
2494 HasMultipleUses = true;
2497 if (HasMultipleUses) break;
2499 // Check to see that the target thinks this is profitable to fold and that
2500 // we can fold it without inducing cycles in the graph.
2501 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2503 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2504 NodeToMatch, OptLevel,
2505 true/*We validate our own chains*/))
2510 case OPC_EmitInteger: {
2511 MVT::SimpleValueType VT =
2512 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2513 int64_t Val = MatcherTable[MatcherIndex++];
2515 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2516 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2517 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2520 case OPC_EmitRegister: {
2521 MVT::SimpleValueType VT =
2522 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2523 unsigned RegNo = MatcherTable[MatcherIndex++];
2524 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2525 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2528 case OPC_EmitRegister2: {
2529 // For targets w/ more than 256 register names, the register enum
2530 // values are stored in two bytes in the matcher table (just like
2532 MVT::SimpleValueType VT =
2533 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2534 unsigned RegNo = MatcherTable[MatcherIndex++];
2535 RegNo |= MatcherTable[MatcherIndex++] << 8;
2536 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2537 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2541 case OPC_EmitConvertToTarget: {
2542 // Convert from IMM/FPIMM to target version.
2543 unsigned RecNo = MatcherTable[MatcherIndex++];
2544 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2545 SDValue Imm = RecordedNodes[RecNo].first;
2547 if (Imm->getOpcode() == ISD::Constant) {
2548 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2549 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2550 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2551 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2552 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2555 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2559 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2560 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2561 // These are space-optimized forms of OPC_EmitMergeInputChains.
2562 assert(InputChain.getNode() == 0 &&
2563 "EmitMergeInputChains should be the first chain producing node");
2564 assert(ChainNodesMatched.empty() &&
2565 "Should only have one EmitMergeInputChains per match");
2567 // Read all of the chained nodes.
2568 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2569 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2570 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2572 // FIXME: What if other value results of the node have uses not matched
2574 if (ChainNodesMatched.back() != NodeToMatch &&
2575 !RecordedNodes[RecNo].first.hasOneUse()) {
2576 ChainNodesMatched.clear();
2580 // Merge the input chains if they are not intra-pattern references.
2581 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2583 if (InputChain.getNode() == 0)
2584 break; // Failed to merge.
2588 case OPC_EmitMergeInputChains: {
2589 assert(InputChain.getNode() == 0 &&
2590 "EmitMergeInputChains should be the first chain producing node");
2591 // This node gets a list of nodes we matched in the input that have
2592 // chains. We want to token factor all of the input chains to these nodes
2593 // together. However, if any of the input chains is actually one of the
2594 // nodes matched in this pattern, then we have an intra-match reference.
2595 // Ignore these because the newly token factored chain should not refer to
2597 unsigned NumChains = MatcherTable[MatcherIndex++];
2598 assert(NumChains != 0 && "Can't TF zero chains");
2600 assert(ChainNodesMatched.empty() &&
2601 "Should only have one EmitMergeInputChains per match");
2603 // Read all of the chained nodes.
2604 for (unsigned i = 0; i != NumChains; ++i) {
2605 unsigned RecNo = MatcherTable[MatcherIndex++];
2606 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2607 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2609 // FIXME: What if other value results of the node have uses not matched
2611 if (ChainNodesMatched.back() != NodeToMatch &&
2612 !RecordedNodes[RecNo].first.hasOneUse()) {
2613 ChainNodesMatched.clear();
2618 // If the inner loop broke out, the match fails.
2619 if (ChainNodesMatched.empty())
2622 // Merge the input chains if they are not intra-pattern references.
2623 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2625 if (InputChain.getNode() == 0)
2626 break; // Failed to merge.
2631 case OPC_EmitCopyToReg: {
2632 unsigned RecNo = MatcherTable[MatcherIndex++];
2633 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2634 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2636 if (InputChain.getNode() == 0)
2637 InputChain = CurDAG->getEntryNode();
2639 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2640 DestPhysReg, RecordedNodes[RecNo].first,
2643 InputGlue = InputChain.getValue(1);
2647 case OPC_EmitNodeXForm: {
2648 unsigned XFormNo = MatcherTable[MatcherIndex++];
2649 unsigned RecNo = MatcherTable[MatcherIndex++];
2650 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2651 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2652 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2657 case OPC_MorphNodeTo: {
2658 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2659 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2660 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2661 // Get the result VT list.
2662 unsigned NumVTs = MatcherTable[MatcherIndex++];
2663 SmallVector<EVT, 4> VTs;
2664 for (unsigned i = 0; i != NumVTs; ++i) {
2665 MVT::SimpleValueType VT =
2666 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2667 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy;
2671 if (EmitNodeInfo & OPFL_Chain)
2672 VTs.push_back(MVT::Other);
2673 if (EmitNodeInfo & OPFL_GlueOutput)
2674 VTs.push_back(MVT::Glue);
2676 // This is hot code, so optimize the two most common cases of 1 and 2
2679 if (VTs.size() == 1)
2680 VTList = CurDAG->getVTList(VTs[0]);
2681 else if (VTs.size() == 2)
2682 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2684 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2686 // Get the operand list.
2687 unsigned NumOps = MatcherTable[MatcherIndex++];
2688 SmallVector<SDValue, 8> Ops;
2689 for (unsigned i = 0; i != NumOps; ++i) {
2690 unsigned RecNo = MatcherTable[MatcherIndex++];
2692 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2694 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2695 Ops.push_back(RecordedNodes[RecNo].first);
2698 // If there are variadic operands to add, handle them now.
2699 if (EmitNodeInfo & OPFL_VariadicInfo) {
2700 // Determine the start index to copy from.
2701 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2702 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2703 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2704 "Invalid variadic node");
2705 // Copy all of the variadic operands, not including a potential glue
2707 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2709 SDValue V = NodeToMatch->getOperand(i);
2710 if (V.getValueType() == MVT::Glue) break;
2715 // If this has chain/glue inputs, add them.
2716 if (EmitNodeInfo & OPFL_Chain)
2717 Ops.push_back(InputChain);
2718 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2719 Ops.push_back(InputGlue);
2723 if (Opcode != OPC_MorphNodeTo) {
2724 // If this is a normal EmitNode command, just create the new node and
2725 // add the results to the RecordedNodes list.
2726 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
2729 // Add all the non-glue/non-chain results to the RecordedNodes list.
2730 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2731 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2732 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2736 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2737 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2740 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2741 // We will visit the equivalent node later.
2742 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2746 // If the node had chain/glue results, update our notion of the current
2748 if (EmitNodeInfo & OPFL_GlueOutput) {
2749 InputGlue = SDValue(Res, VTs.size()-1);
2750 if (EmitNodeInfo & OPFL_Chain)
2751 InputChain = SDValue(Res, VTs.size()-2);
2752 } else if (EmitNodeInfo & OPFL_Chain)
2753 InputChain = SDValue(Res, VTs.size()-1);
2755 // If the OPFL_MemRefs glue is set on this node, slap all of the
2756 // accumulated memrefs onto it.
2758 // FIXME: This is vastly incorrect for patterns with multiple outputs
2759 // instructions that access memory and for ComplexPatterns that match
2761 if (EmitNodeInfo & OPFL_MemRefs) {
2762 // Only attach load or store memory operands if the generated
2763 // instruction may load or store.
2764 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2765 bool mayLoad = MCID.mayLoad();
2766 bool mayStore = MCID.mayStore();
2768 unsigned NumMemRefs = 0;
2769 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2770 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2771 if ((*I)->isLoad()) {
2774 } else if ((*I)->isStore()) {
2782 MachineSDNode::mmo_iterator MemRefs =
2783 MF->allocateMemRefsArray(NumMemRefs);
2785 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2786 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2787 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2788 if ((*I)->isLoad()) {
2791 } else if ((*I)->isStore()) {
2799 cast<MachineSDNode>(Res)
2800 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2804 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2805 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
2807 // If this was a MorphNodeTo then we're completely done!
2808 if (Opcode == OPC_MorphNodeTo) {
2809 // Update chain and glue uses.
2810 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2811 InputGlue, GlueResultNodesMatched, true);
2818 case OPC_MarkGlueResults: {
2819 unsigned NumNodes = MatcherTable[MatcherIndex++];
2821 // Read and remember all the glue-result nodes.
2822 for (unsigned i = 0; i != NumNodes; ++i) {
2823 unsigned RecNo = MatcherTable[MatcherIndex++];
2825 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2827 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2828 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2833 case OPC_CompleteMatch: {
2834 // The match has been completed, and any new nodes (if any) have been
2835 // created. Patch up references to the matched dag to use the newly
2837 unsigned NumResults = MatcherTable[MatcherIndex++];
2839 for (unsigned i = 0; i != NumResults; ++i) {
2840 unsigned ResSlot = MatcherTable[MatcherIndex++];
2842 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2844 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2845 SDValue Res = RecordedNodes[ResSlot].first;
2847 assert(i < NodeToMatch->getNumValues() &&
2848 NodeToMatch->getValueType(i) != MVT::Other &&
2849 NodeToMatch->getValueType(i) != MVT::Glue &&
2850 "Invalid number of results to complete!");
2851 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2852 NodeToMatch->getValueType(i) == MVT::iPTR ||
2853 Res.getValueType() == MVT::iPTR ||
2854 NodeToMatch->getValueType(i).getSizeInBits() ==
2855 Res.getValueType().getSizeInBits()) &&
2856 "invalid replacement");
2857 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2860 // If the root node defines glue, add it to the glue nodes to update list.
2861 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2862 GlueResultNodesMatched.push_back(NodeToMatch);
2864 // Update chain and glue uses.
2865 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2866 InputGlue, GlueResultNodesMatched, false);
2868 assert(NodeToMatch->use_empty() &&
2869 "Didn't replace all uses of the node?");
2871 // FIXME: We just return here, which interacts correctly with SelectRoot
2872 // above. We should fix this to not return an SDNode* anymore.
2877 // If the code reached this point, then the match failed. See if there is
2878 // another child to try in the current 'Scope', otherwise pop it until we
2879 // find a case to check.
2880 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2881 ++NumDAGIselRetries;
2883 if (MatchScopes.empty()) {
2884 CannotYetSelect(NodeToMatch);
2888 // Restore the interpreter state back to the point where the scope was
2890 MatchScope &LastScope = MatchScopes.back();
2891 RecordedNodes.resize(LastScope.NumRecordedNodes);
2893 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2894 N = NodeStack.back();
2896 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2897 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2898 MatcherIndex = LastScope.FailIndex;
2900 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
2902 InputChain = LastScope.InputChain;
2903 InputGlue = LastScope.InputGlue;
2904 if (!LastScope.HasChainNodesMatched)
2905 ChainNodesMatched.clear();
2906 if (!LastScope.HasGlueResultNodesMatched)
2907 GlueResultNodesMatched.clear();
2909 // Check to see what the offset is at the new MatcherIndex. If it is zero
2910 // we have reached the end of this scope, otherwise we have another child
2911 // in the current scope to try.
2912 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2913 if (NumToSkip & 128)
2914 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2916 // If we have another child in this scope to match, update FailIndex and
2918 if (NumToSkip != 0) {
2919 LastScope.FailIndex = MatcherIndex+NumToSkip;
2923 // End of this scope, pop it and try the next child in the containing
2925 MatchScopes.pop_back();
2932 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2934 raw_string_ostream Msg(msg);
2935 Msg << "Cannot select: ";
2937 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2938 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2939 N->getOpcode() != ISD::INTRINSIC_VOID) {
2940 N->printrFull(Msg, CurDAG);
2941 Msg << "\nIn function: " << MF->getName();
2943 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2945 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2946 if (iid < Intrinsic::num_intrinsics)
2947 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2948 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2949 Msg << "target intrinsic %" << TII->getName(iid);
2951 Msg << "unknown intrinsic #" << iid;
2953 report_fatal_error(Msg.str());
2956 char SelectionDAGISel::ID = 0;