1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/TargetLibraryInfo.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SelectionDAGISel.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugInfo.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/IntrinsicInst.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/LLVMContext.h"
45 #include "llvm/IR/Module.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetIntrinsicInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "llvm/Target/TargetOptions.h"
57 #include "llvm/Target/TargetRegisterInfo.h"
58 #include "llvm/Target/TargetSubtargetInfo.h"
59 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
63 #define DEBUG_TYPE "isel"
65 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
66 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
67 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
68 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
69 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
70 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
71 STATISTIC(NumFastIselFailLowerArguments,
72 "Number of entry blocks where fast isel failed to lower arguments");
76 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
77 cl::desc("Enable extra verbose messages in the \"fast\" "
78 "instruction selector"));
81 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
82 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
83 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
84 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
85 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
86 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
87 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
89 // Standard binary operators...
90 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
91 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
92 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
93 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
94 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
95 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
96 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
97 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
98 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
99 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
100 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
101 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
103 // Logical operators...
104 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
105 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
106 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
108 // Memory instructions...
109 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
110 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
111 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
112 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
113 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
114 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
115 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
117 // Convert instructions...
118 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
119 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
120 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
121 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
122 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
123 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
124 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
125 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
126 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
127 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
128 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
129 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
131 // Other instructions...
132 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
133 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
134 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
135 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
136 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
137 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
138 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
139 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
140 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
141 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
142 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
143 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
144 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
145 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
146 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
148 // Intrinsic instructions...
149 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
150 STATISTIC(NumFastIselFailSAddWithOverflow,
151 "Fast isel fails on sadd.with.overflow");
152 STATISTIC(NumFastIselFailUAddWithOverflow,
153 "Fast isel fails on uadd.with.overflow");
154 STATISTIC(NumFastIselFailSSubWithOverflow,
155 "Fast isel fails on ssub.with.overflow");
156 STATISTIC(NumFastIselFailUSubWithOverflow,
157 "Fast isel fails on usub.with.overflow");
158 STATISTIC(NumFastIselFailSMulWithOverflow,
159 "Fast isel fails on smul.with.overflow");
160 STATISTIC(NumFastIselFailUMulWithOverflow,
161 "Fast isel fails on umul.with.overflow");
162 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
163 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
164 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
165 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
169 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
170 cl::desc("Enable verbose messages in the \"fast\" "
171 "instruction selector"));
172 static cl::opt<int> EnableFastISelAbort(
173 "fast-isel-abort", cl::Hidden,
174 cl::desc("Enable abort calls when \"fast\" instruction selection "
175 "fails to lower an instruction: 0 disable the abort, 1 will "
176 "abort but for args, calls and terminators, 2 will also "
177 "abort for argument lowering, and 3 will never fallback "
178 "to SelectionDAG."));
182 cl::desc("use Machine Branch Probability Info"),
183 cl::init(true), cl::Hidden);
186 static cl::opt<std::string>
187 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
188 cl::desc("Only display the basic block whose name "
189 "matches this for all view-*-dags options"));
191 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
192 cl::desc("Pop up a window to show dags before the first "
193 "dag combine pass"));
195 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before legalize types"));
198 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
199 cl::desc("Pop up a window to show dags before legalize"));
201 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
202 cl::desc("Pop up a window to show dags before the second "
203 "dag combine pass"));
205 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
206 cl::desc("Pop up a window to show dags before the post legalize types"
207 " dag combine pass"));
209 ViewISelDAGs("view-isel-dags", cl::Hidden,
210 cl::desc("Pop up a window to show isel dags as they are selected"));
212 ViewSchedDAGs("view-sched-dags", cl::Hidden,
213 cl::desc("Pop up a window to show sched dags as they are processed"));
215 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
216 cl::desc("Pop up a window to show SUnit dags after they are processed"));
218 static const bool ViewDAGCombine1 = false,
219 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
220 ViewDAGCombine2 = false,
221 ViewDAGCombineLT = false,
222 ViewISelDAGs = false, ViewSchedDAGs = false,
223 ViewSUnitDAGs = false;
226 //===---------------------------------------------------------------------===//
228 /// RegisterScheduler class - Track the registration of instruction schedulers.
230 //===---------------------------------------------------------------------===//
231 MachinePassRegistry RegisterScheduler::Registry;
233 //===---------------------------------------------------------------------===//
235 /// ISHeuristic command line option for instruction schedulers.
237 //===---------------------------------------------------------------------===//
238 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
239 RegisterPassParser<RegisterScheduler> >
240 ISHeuristic("pre-RA-sched",
241 cl::init(&createDefaultScheduler), cl::Hidden,
242 cl::desc("Instruction schedulers available (before register"
245 static RegisterScheduler
246 defaultListDAGScheduler("default", "Best scheduler for the target",
247 createDefaultScheduler);
250 //===--------------------------------------------------------------------===//
251 /// \brief This class is used by SelectionDAGISel to temporarily override
252 /// the optimization level on a per-function basis.
253 class OptLevelChanger {
254 SelectionDAGISel &IS;
255 CodeGenOpt::Level SavedOptLevel;
259 OptLevelChanger(SelectionDAGISel &ISel,
260 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
261 SavedOptLevel = IS.OptLevel;
262 if (NewOptLevel == SavedOptLevel)
264 IS.OptLevel = NewOptLevel;
265 IS.TM.setOptLevel(NewOptLevel);
266 SavedFastISel = IS.TM.Options.EnableFastISel;
267 if (NewOptLevel == CodeGenOpt::None)
268 IS.TM.setFastISel(true);
269 DEBUG(dbgs() << "\nChanging optimization level for Function "
270 << IS.MF->getFunction()->getName() << "\n");
271 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
272 << " ; After: -O" << NewOptLevel << "\n");
276 if (IS.OptLevel == SavedOptLevel)
278 DEBUG(dbgs() << "\nRestoring optimization level for Function "
279 << IS.MF->getFunction()->getName() << "\n");
280 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
281 << " ; After: -O" << SavedOptLevel << "\n");
282 IS.OptLevel = SavedOptLevel;
283 IS.TM.setOptLevel(SavedOptLevel);
284 IS.TM.setFastISel(SavedFastISel);
288 //===--------------------------------------------------------------------===//
289 /// createDefaultScheduler - This creates an instruction scheduler appropriate
291 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
292 CodeGenOpt::Level OptLevel) {
293 const TargetLowering *TLI = IS->TLI;
294 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
296 if (OptLevel == CodeGenOpt::None ||
297 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
298 TLI->getSchedulingPreference() == Sched::Source)
299 return createSourceListDAGScheduler(IS, OptLevel);
300 if (TLI->getSchedulingPreference() == Sched::RegPressure)
301 return createBURRListDAGScheduler(IS, OptLevel);
302 if (TLI->getSchedulingPreference() == Sched::Hybrid)
303 return createHybridListDAGScheduler(IS, OptLevel);
304 if (TLI->getSchedulingPreference() == Sched::VLIW)
305 return createVLIWDAGScheduler(IS, OptLevel);
306 assert(TLI->getSchedulingPreference() == Sched::ILP &&
307 "Unknown sched type!");
308 return createILPListDAGScheduler(IS, OptLevel);
312 // EmitInstrWithCustomInserter - This method should be implemented by targets
313 // that mark instructions with the 'usesCustomInserter' flag. These
314 // instructions are special in various ways, which require special support to
315 // insert. The specified MachineInstr is created but not inserted into any
316 // basic blocks, and this method is called to expand it into a sequence of
317 // instructions, potentially also creating new basic blocks and control flow.
318 // When new basic blocks are inserted and the edges from MBB to its successors
319 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
322 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
323 MachineBasicBlock *MBB) const {
325 dbgs() << "If a target marks an instruction with "
326 "'usesCustomInserter', it must implement "
327 "TargetLowering::EmitInstrWithCustomInserter!";
329 llvm_unreachable(nullptr);
332 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
333 SDNode *Node) const {
334 assert(!MI->hasPostISelHook() &&
335 "If a target marks an instruction with 'hasPostISelHook', "
336 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
339 //===----------------------------------------------------------------------===//
340 // SelectionDAGISel code
341 //===----------------------------------------------------------------------===//
343 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
344 CodeGenOpt::Level OL) :
345 MachineFunctionPass(ID), TM(tm),
346 FuncInfo(new FunctionLoweringInfo()),
347 CurDAG(new SelectionDAG(tm, OL)),
348 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
352 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
353 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
354 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
355 initializeTargetLibraryInfoWrapperPassPass(
356 *PassRegistry::getPassRegistry());
359 SelectionDAGISel::~SelectionDAGISel() {
365 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
366 AU.addRequired<AliasAnalysis>();
367 AU.addPreserved<AliasAnalysis>();
368 AU.addRequired<GCModuleInfo>();
369 AU.addPreserved<GCModuleInfo>();
370 AU.addRequired<TargetLibraryInfoWrapperPass>();
371 if (UseMBPI && OptLevel != CodeGenOpt::None)
372 AU.addRequired<BranchProbabilityInfo>();
373 MachineFunctionPass::getAnalysisUsage(AU);
376 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
377 /// may trap on it. In this case we have to split the edge so that the path
378 /// through the predecessor block that doesn't go to the phi block doesn't
379 /// execute the possibly trapping instruction.
381 /// This is required for correctness, so it must be done at -O0.
383 static void SplitCriticalSideEffectEdges(Function &Fn, AliasAnalysis *AA) {
384 // Loop for blocks with phi nodes.
385 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
386 PHINode *PN = dyn_cast<PHINode>(BB->begin());
390 // For each block with a PHI node, check to see if any of the input values
391 // are potentially trapping constant expressions. Constant expressions are
392 // the only potentially trapping value that can occur as the argument to a
394 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
395 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
396 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
397 if (!CE || !CE->canTrap()) continue;
399 // The only case we have to worry about is when the edge is critical.
400 // Since this block has a PHI Node, we assume it has multiple input
401 // edges: check to see if the pred has multiple successors.
402 BasicBlock *Pred = PN->getIncomingBlock(i);
403 if (Pred->getTerminator()->getNumSuccessors() == 1)
406 // Okay, we have to split this edge.
408 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
409 CriticalEdgeSplittingOptions(AA).setMergeIdenticalEdges());
415 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
416 // Do some sanity-checking on the command-line options.
417 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
418 "-fast-isel-verbose requires -fast-isel");
419 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
420 "-fast-isel-abort > 0 requires -fast-isel");
422 const Function &Fn = *mf.getFunction();
425 // Reset the target options before resetting the optimization
427 // FIXME: This is a horrible hack and should be processed via
428 // codegen looking at the optimization level explicitly when
429 // it wants to look at it.
430 TM.resetTargetOptions(Fn);
431 // Reset OptLevel to None for optnone functions.
432 CodeGenOpt::Level NewOptLevel = OptLevel;
433 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
434 NewOptLevel = CodeGenOpt::None;
435 OptLevelChanger OLC(*this, NewOptLevel);
437 TII = MF->getSubtarget().getInstrInfo();
438 TLI = MF->getSubtarget().getTargetLowering();
439 RegInfo = &MF->getRegInfo();
440 AA = &getAnalysis<AliasAnalysis>();
441 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
442 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
444 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
446 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), AA);
449 FuncInfo->set(Fn, *MF, CurDAG);
451 if (UseMBPI && OptLevel != CodeGenOpt::None)
452 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
454 FuncInfo->BPI = nullptr;
456 SDB->init(GFI, *AA, LibInfo);
458 MF->setHasInlineAsm(false);
460 SelectAllBasicBlocks(Fn);
462 // If the first basic block in the function has live ins that need to be
463 // copied into vregs, emit the copies into the top of the block before
464 // emitting the code for the block.
465 MachineBasicBlock *EntryMBB = MF->begin();
466 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
467 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
469 DenseMap<unsigned, unsigned> LiveInMap;
470 if (!FuncInfo->ArgDbgValues.empty())
471 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
472 E = RegInfo->livein_end(); LI != E; ++LI)
474 LiveInMap.insert(std::make_pair(LI->first, LI->second));
476 // Insert DBG_VALUE instructions for function arguments to the entry block.
477 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
478 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
479 bool hasFI = MI->getOperand(0).isFI();
481 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
482 if (TargetRegisterInfo::isPhysicalRegister(Reg))
483 EntryMBB->insert(EntryMBB->begin(), MI);
485 MachineInstr *Def = RegInfo->getVRegDef(Reg);
487 MachineBasicBlock::iterator InsertPos = Def;
488 // FIXME: VR def may not be in entry block.
489 Def->getParent()->insert(std::next(InsertPos), MI);
491 DEBUG(dbgs() << "Dropping debug info for dead vreg"
492 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
495 // If Reg is live-in then update debug info to track its copy in a vreg.
496 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
497 if (LDI != LiveInMap.end()) {
498 assert(!hasFI && "There's no handling of frame pointer updating here yet "
500 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
501 MachineBasicBlock::iterator InsertPos = Def;
502 const MDNode *Variable = MI->getDebugVariable();
503 const MDNode *Expr = MI->getDebugExpression();
504 DebugLoc DL = MI->getDebugLoc();
505 bool IsIndirect = MI->isIndirectDebugValue();
506 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
507 assert(cast<MDLocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
508 "Expected inlined-at fields to agree");
509 // Def is never a terminator here, so it is ok to increment InsertPos.
510 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
511 IsIndirect, LDI->second, Offset, Variable, Expr);
513 // If this vreg is directly copied into an exported register then
514 // that COPY instructions also need DBG_VALUE, if it is the only
515 // user of LDI->second.
516 MachineInstr *CopyUseMI = nullptr;
517 for (MachineRegisterInfo::use_instr_iterator
518 UI = RegInfo->use_instr_begin(LDI->second),
519 E = RegInfo->use_instr_end(); UI != E; ) {
520 MachineInstr *UseMI = &*(UI++);
521 if (UseMI->isDebugValue()) continue;
522 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
523 CopyUseMI = UseMI; continue;
525 // Otherwise this is another use or second copy use.
526 CopyUseMI = nullptr; break;
529 // Use MI's debug location, which describes where Variable was
530 // declared, rather than whatever is attached to CopyUseMI.
531 MachineInstr *NewMI =
532 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
533 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
534 MachineBasicBlock::iterator Pos = CopyUseMI;
535 EntryMBB->insertAfter(Pos, NewMI);
540 // Determine if there are any calls in this machine function.
541 MachineFrameInfo *MFI = MF->getFrameInfo();
542 for (const auto &MBB : *MF) {
543 if (MFI->hasCalls() && MF->hasInlineAsm())
546 for (const auto &MI : MBB) {
547 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
548 if ((MCID.isCall() && !MCID.isReturn()) ||
549 MI.isStackAligningInlineAsm()) {
550 MFI->setHasCalls(true);
552 if (MI.isInlineAsm()) {
553 MF->setHasInlineAsm(true);
558 // Determine if there is a call to setjmp in the machine function.
559 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
561 // Replace forward-declared registers with the registers containing
562 // the desired value.
563 MachineRegisterInfo &MRI = MF->getRegInfo();
564 for (DenseMap<unsigned, unsigned>::iterator
565 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
567 unsigned From = I->first;
568 unsigned To = I->second;
569 // If To is also scheduled to be replaced, find what its ultimate
572 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
576 // Make sure the new register has a sufficiently constrained register class.
577 if (TargetRegisterInfo::isVirtualRegister(From) &&
578 TargetRegisterInfo::isVirtualRegister(To))
579 MRI.constrainRegClass(To, MRI.getRegClass(From));
581 MRI.replaceRegWith(From, To);
584 // Freeze the set of reserved registers now that MachineFrameInfo has been
585 // set up. All the information required by getReservedRegs() should be
587 MRI.freezeReservedRegs(*MF);
589 // Release function-specific state. SDB and CurDAG are already cleared
593 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
594 DEBUG(MF->print(dbgs()));
599 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
600 BasicBlock::const_iterator End,
602 // Lower the instructions. If a call is emitted as a tail call, cease emitting
603 // nodes for this block.
604 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
607 // Make sure the root of the DAG is up-to-date.
608 CurDAG->setRoot(SDB->getControlRoot());
609 HadTailCall = SDB->HasTailCall;
612 // Final step, emit the lowered DAG as machine code.
616 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
617 SmallPtrSet<SDNode*, 128> VisitedNodes;
618 SmallVector<SDNode*, 128> Worklist;
620 Worklist.push_back(CurDAG->getRoot().getNode());
626 SDNode *N = Worklist.pop_back_val();
628 // If we've already seen this node, ignore it.
629 if (!VisitedNodes.insert(N).second)
632 // Otherwise, add all chain operands to the worklist.
633 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
634 if (N->getOperand(i).getValueType() == MVT::Other)
635 Worklist.push_back(N->getOperand(i).getNode());
637 // If this is a CopyToReg with a vreg dest, process it.
638 if (N->getOpcode() != ISD::CopyToReg)
641 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
642 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
645 // Ignore non-scalar or non-integer values.
646 SDValue Src = N->getOperand(2);
647 EVT SrcVT = Src.getValueType();
648 if (!SrcVT.isInteger() || SrcVT.isVector())
651 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
652 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
653 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
654 } while (!Worklist.empty());
657 void SelectionDAGISel::CodeGenAndEmitDAG() {
658 std::string GroupName;
659 if (TimePassesIsEnabled)
660 GroupName = "Instruction Selection and Scheduling";
661 std::string BlockName;
662 int BlockNumber = -1;
664 bool MatchFilterBB = false; (void)MatchFilterBB;
666 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
667 FilterDAGBasicBlockName ==
668 FuncInfo->MBB->getBasicBlock()->getName().str());
671 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
672 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
676 BlockNumber = FuncInfo->MBB->getNumber();
678 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
680 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
681 << " '" << BlockName << "'\n"; CurDAG->dump());
683 if (ViewDAGCombine1 && MatchFilterBB)
684 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
686 // Run the DAG combiner in pre-legalize mode.
688 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
689 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
692 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
693 << " '" << BlockName << "'\n"; CurDAG->dump());
695 // Second step, hack on the DAG until it only uses operations and types that
696 // the target supports.
697 if (ViewLegalizeTypesDAGs && MatchFilterBB)
698 CurDAG->viewGraph("legalize-types input for " + BlockName);
702 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
703 Changed = CurDAG->LegalizeTypes();
706 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
707 << " '" << BlockName << "'\n"; CurDAG->dump());
709 CurDAG->NewNodesMustHaveLegalTypes = true;
712 if (ViewDAGCombineLT && MatchFilterBB)
713 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
715 // Run the DAG combiner in post-type-legalize mode.
717 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
718 TimePassesIsEnabled);
719 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
722 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
723 << " '" << BlockName << "'\n"; CurDAG->dump());
728 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
729 Changed = CurDAG->LegalizeVectors();
734 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
735 CurDAG->LegalizeTypes();
738 if (ViewDAGCombineLT && MatchFilterBB)
739 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
741 // Run the DAG combiner in post-type-legalize mode.
743 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
744 TimePassesIsEnabled);
745 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
748 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
749 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
752 if (ViewLegalizeDAGs && MatchFilterBB)
753 CurDAG->viewGraph("legalize input for " + BlockName);
756 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
760 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
761 << " '" << BlockName << "'\n"; CurDAG->dump());
763 if (ViewDAGCombine2 && MatchFilterBB)
764 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
766 // Run the DAG combiner in post-legalize mode.
768 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
769 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
772 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
773 << " '" << BlockName << "'\n"; CurDAG->dump());
775 if (OptLevel != CodeGenOpt::None)
776 ComputeLiveOutVRegInfo();
778 if (ViewISelDAGs && MatchFilterBB)
779 CurDAG->viewGraph("isel input for " + BlockName);
781 // Third, instruction select all of the operations to machine code, adding the
782 // code to the MachineBasicBlock.
784 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
785 DoInstructionSelection();
788 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
789 << " '" << BlockName << "'\n"; CurDAG->dump());
791 if (ViewSchedDAGs && MatchFilterBB)
792 CurDAG->viewGraph("scheduler input for " + BlockName);
794 // Schedule machine code.
795 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
797 NamedRegionTimer T("Instruction Scheduling", GroupName,
798 TimePassesIsEnabled);
799 Scheduler->Run(CurDAG, FuncInfo->MBB);
802 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
804 // Emit machine code to BB. This can change 'BB' to the last block being
806 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
808 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
810 // FuncInfo->InsertPt is passed by reference and set to the end of the
811 // scheduled instructions.
812 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
815 // If the block was split, make sure we update any references that are used to
816 // update PHI nodes later on.
817 if (FirstMBB != LastMBB)
818 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
820 // Free the scheduler state.
822 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
823 TimePassesIsEnabled);
827 // Free the SelectionDAG state, now that we're finished with it.
832 /// ISelUpdater - helper class to handle updates of the instruction selection
834 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
835 SelectionDAG::allnodes_iterator &ISelPosition;
837 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
838 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
840 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
841 /// deleted is the current ISelPosition node, update ISelPosition.
843 void NodeDeleted(SDNode *N, SDNode *E) override {
844 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
848 } // end anonymous namespace
850 void SelectionDAGISel::DoInstructionSelection() {
851 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
852 << FuncInfo->MBB->getNumber()
853 << " '" << FuncInfo->MBB->getName() << "'\n");
857 // Select target instructions for the DAG.
859 // Number all nodes with a topological order and set DAGSize.
860 DAGSize = CurDAG->AssignTopologicalOrder();
862 // Create a dummy node (which is not added to allnodes), that adds
863 // a reference to the root node, preventing it from being deleted,
864 // and tracking any changes of the root.
865 HandleSDNode Dummy(CurDAG->getRoot());
866 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
869 // Make sure that ISelPosition gets properly updated when nodes are deleted
870 // in calls made from this function.
871 ISelUpdater ISU(*CurDAG, ISelPosition);
873 // The AllNodes list is now topological-sorted. Visit the
874 // nodes by starting at the end of the list (the root of the
875 // graph) and preceding back toward the beginning (the entry
877 while (ISelPosition != CurDAG->allnodes_begin()) {
878 SDNode *Node = --ISelPosition;
879 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
880 // but there are currently some corner cases that it misses. Also, this
881 // makes it theoretically possible to disable the DAGCombiner.
882 if (Node->use_empty())
885 SDNode *ResNode = Select(Node);
887 // FIXME: This is pretty gross. 'Select' should be changed to not return
888 // anything at all and this code should be nuked with a tactical strike.
890 // If node should not be replaced, continue with the next one.
891 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
895 ReplaceUses(Node, ResNode);
898 // If after the replacement this node is not used any more,
899 // remove this dead node.
900 if (Node->use_empty()) // Don't delete EntryToken, etc.
901 CurDAG->RemoveDeadNode(Node);
904 CurDAG->setRoot(Dummy.getValue());
907 DEBUG(dbgs() << "===== Instruction selection ends:\n");
909 PostprocessISelDAG();
912 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
913 /// do other setup for EH landing-pad blocks.
914 void SelectionDAGISel::PrepareEHLandingPad() {
915 MachineBasicBlock *MBB = FuncInfo->MBB;
917 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
919 // Add a label to mark the beginning of the landing pad. Deletion of the
920 // landing pad can thus be detected via the MachineModuleInfo.
921 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
923 // Assign the call site to the landing pad's begin label.
924 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
926 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
927 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
930 // If this is an MSVC-style personality function, we need to split the landing
931 // pad into several BBs.
932 const BasicBlock *LLVMBB = MBB->getBasicBlock();
933 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
934 MF->getMMI().addPersonality(
935 MBB, cast<Function>(LPadInst->getPersonalityFn()->stripPointerCasts()));
936 if (MF->getMMI().getPersonalityType() == EHPersonality::MSVC_Win64SEH) {
937 // Make virtual registers and a series of labels that fill in values for the
939 auto &RI = MF->getRegInfo();
940 FuncInfo->ExceptionSelectorVirtReg = RI.createVirtualRegister(PtrRC);
942 // Get all invoke BBs that will unwind into the clause BBs.
943 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
946 // Emit separate machine basic blocks with separate labels for each clause
947 // before the main landing pad block.
948 MachineInstrBuilder SelectorPHI = BuildMI(
949 *MBB, MBB->begin(), SDB->getCurDebugLoc(), TII->get(TargetOpcode::PHI),
950 FuncInfo->ExceptionSelectorVirtReg);
951 for (unsigned I = 0, E = LPadInst->getNumClauses(); I != E; ++I) {
952 // Skip filter clauses, we can't implement them yet.
953 if (LPadInst->isFilter(I))
956 MachineBasicBlock *ClauseBB = MF->CreateMachineBasicBlock(LLVMBB);
957 MF->insert(MBB, ClauseBB);
959 // Add the edge from the invoke to the clause.
960 for (MachineBasicBlock *InvokeBB : InvokeBBs)
961 InvokeBB->addSuccessor(ClauseBB);
963 // Mark the clause as a landing pad or MI passes will delete it.
964 ClauseBB->setIsLandingPad();
966 GlobalValue *ClauseGV = ExtractTypeInfo(LPadInst->getClause(I));
968 // Start the BB with a label.
969 MCSymbol *ClauseLabel = MF->getMMI().addClauseForLandingPad(MBB);
970 BuildMI(*ClauseBB, ClauseBB->begin(), SDB->getCurDebugLoc(), II)
971 .addSym(ClauseLabel);
973 // Construct a simple BB that defines a register with the typeid constant.
974 FuncInfo->MBB = ClauseBB;
975 FuncInfo->InsertPt = ClauseBB->end();
976 unsigned VReg = SDB->visitLandingPadClauseBB(ClauseGV, MBB);
977 CurDAG->setRoot(SDB->getRoot());
981 // Add the typeid virtual register to the phi in the main landing pad.
982 SelectorPHI.addReg(VReg).addMBB(ClauseBB);
985 // Remove the edge from the invoke to the lpad.
986 for (MachineBasicBlock *InvokeBB : InvokeBBs)
987 InvokeBB->removeSuccessor(MBB);
989 // Restore FuncInfo back to its previous state and select the main landing
992 FuncInfo->InsertPt = MBB->end();
995 if (MF->getMMI().getPersonalityType() == EHPersonality::MSVC_CXX) {
996 WinEHFuncInfo &FuncInfo = MF->getMMI().getWinEHFuncInfo(MF->getFunction());
997 MF->getMMI().addWinEHState(MBB, FuncInfo.LandingPadStateMap[LPadInst]);
1000 // Mark exception register as live in.
1001 if (unsigned Reg = TLI->getExceptionPointerRegister())
1002 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
1004 // Mark exception selector register as live in.
1005 if (unsigned Reg = TLI->getExceptionSelectorRegister())
1006 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
1009 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
1010 /// side-effect free and is either dead or folded into a generated instruction.
1011 /// Return false if it needs to be emitted.
1012 static bool isFoldedOrDeadInstruction(const Instruction *I,
1013 FunctionLoweringInfo *FuncInfo) {
1014 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
1015 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1016 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1017 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
1018 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1022 // Collect per Instruction statistics for fast-isel misses. Only those
1023 // instructions that cause the bail are accounted for. It does not account for
1024 // instructions higher in the block. Thus, summing the per instructions stats
1025 // will not add up to what is reported by NumFastIselFailures.
1026 static void collectFailStats(const Instruction *I) {
1027 switch (I->getOpcode()) {
1028 default: assert (0 && "<Invalid operator> ");
1031 case Instruction::Ret: NumFastIselFailRet++; return;
1032 case Instruction::Br: NumFastIselFailBr++; return;
1033 case Instruction::Switch: NumFastIselFailSwitch++; return;
1034 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1035 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1036 case Instruction::Resume: NumFastIselFailResume++; return;
1037 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1039 // Standard binary operators...
1040 case Instruction::Add: NumFastIselFailAdd++; return;
1041 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1042 case Instruction::Sub: NumFastIselFailSub++; return;
1043 case Instruction::FSub: NumFastIselFailFSub++; return;
1044 case Instruction::Mul: NumFastIselFailMul++; return;
1045 case Instruction::FMul: NumFastIselFailFMul++; return;
1046 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1047 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1048 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1049 case Instruction::URem: NumFastIselFailURem++; return;
1050 case Instruction::SRem: NumFastIselFailSRem++; return;
1051 case Instruction::FRem: NumFastIselFailFRem++; return;
1053 // Logical operators...
1054 case Instruction::And: NumFastIselFailAnd++; return;
1055 case Instruction::Or: NumFastIselFailOr++; return;
1056 case Instruction::Xor: NumFastIselFailXor++; return;
1058 // Memory instructions...
1059 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1060 case Instruction::Load: NumFastIselFailLoad++; return;
1061 case Instruction::Store: NumFastIselFailStore++; return;
1062 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1063 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1064 case Instruction::Fence: NumFastIselFailFence++; return;
1065 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1067 // Convert instructions...
1068 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1069 case Instruction::ZExt: NumFastIselFailZExt++; return;
1070 case Instruction::SExt: NumFastIselFailSExt++; return;
1071 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1072 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1073 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1074 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1075 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1076 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1077 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1078 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1079 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1081 // Other instructions...
1082 case Instruction::ICmp: NumFastIselFailICmp++; return;
1083 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1084 case Instruction::PHI: NumFastIselFailPHI++; return;
1085 case Instruction::Select: NumFastIselFailSelect++; return;
1086 case Instruction::Call: {
1087 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1088 switch (Intrinsic->getIntrinsicID()) {
1090 NumFastIselFailIntrinsicCall++; return;
1091 case Intrinsic::sadd_with_overflow:
1092 NumFastIselFailSAddWithOverflow++; return;
1093 case Intrinsic::uadd_with_overflow:
1094 NumFastIselFailUAddWithOverflow++; return;
1095 case Intrinsic::ssub_with_overflow:
1096 NumFastIselFailSSubWithOverflow++; return;
1097 case Intrinsic::usub_with_overflow:
1098 NumFastIselFailUSubWithOverflow++; return;
1099 case Intrinsic::smul_with_overflow:
1100 NumFastIselFailSMulWithOverflow++; return;
1101 case Intrinsic::umul_with_overflow:
1102 NumFastIselFailUMulWithOverflow++; return;
1103 case Intrinsic::frameaddress:
1104 NumFastIselFailFrameaddress++; return;
1105 case Intrinsic::sqrt:
1106 NumFastIselFailSqrt++; return;
1107 case Intrinsic::experimental_stackmap:
1108 NumFastIselFailStackMap++; return;
1109 case Intrinsic::experimental_patchpoint_void: // fall-through
1110 case Intrinsic::experimental_patchpoint_i64:
1111 NumFastIselFailPatchPoint++; return;
1114 NumFastIselFailCall++;
1117 case Instruction::Shl: NumFastIselFailShl++; return;
1118 case Instruction::LShr: NumFastIselFailLShr++; return;
1119 case Instruction::AShr: NumFastIselFailAShr++; return;
1120 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1121 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1122 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1123 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1124 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1125 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1126 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1131 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1132 // Initialize the Fast-ISel state, if needed.
1133 FastISel *FastIS = nullptr;
1134 if (TM.Options.EnableFastISel)
1135 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1137 // Iterate over all basic blocks in the function.
1138 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1139 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1140 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1141 const BasicBlock *LLVMBB = *I;
1143 if (OptLevel != CodeGenOpt::None) {
1144 bool AllPredsVisited = true;
1145 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1147 if (!FuncInfo->VisitedBBs.count(*PI)) {
1148 AllPredsVisited = false;
1153 if (AllPredsVisited) {
1154 for (BasicBlock::const_iterator I = LLVMBB->begin();
1155 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1156 FuncInfo->ComputePHILiveOutRegInfo(PN);
1158 for (BasicBlock::const_iterator I = LLVMBB->begin();
1159 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1160 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1163 FuncInfo->VisitedBBs.insert(LLVMBB);
1166 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1167 BasicBlock::const_iterator const End = LLVMBB->end();
1168 BasicBlock::const_iterator BI = End;
1170 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1171 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1173 // Setup an EH landing-pad block.
1174 FuncInfo->ExceptionPointerVirtReg = 0;
1175 FuncInfo->ExceptionSelectorVirtReg = 0;
1176 if (FuncInfo->MBB->isLandingPad())
1177 PrepareEHLandingPad();
1179 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1181 FastIS->startNewBlock();
1183 // Emit code for any incoming arguments. This must happen before
1184 // beginning FastISel on the entry block.
1185 if (LLVMBB == &Fn.getEntryBlock()) {
1188 // Lower any arguments needed in this block if this is the entry block.
1189 if (!FastIS->lowerArguments()) {
1190 // Fast isel failed to lower these arguments
1191 ++NumFastIselFailLowerArguments;
1192 if (EnableFastISelAbort > 1)
1193 report_fatal_error("FastISel didn't lower all arguments");
1195 // Use SelectionDAG argument lowering
1197 CurDAG->setRoot(SDB->getControlRoot());
1199 CodeGenAndEmitDAG();
1202 // If we inserted any instructions at the beginning, make a note of
1203 // where they are, so we can be sure to emit subsequent instructions
1205 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1206 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1208 FastIS->setLastLocalValue(nullptr);
1211 unsigned NumFastIselRemaining = std::distance(Begin, End);
1212 // Do FastISel on as many instructions as possible.
1213 for (; BI != Begin; --BI) {
1214 const Instruction *Inst = std::prev(BI);
1216 // If we no longer require this instruction, skip it.
1217 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1218 --NumFastIselRemaining;
1222 // Bottom-up: reset the insert pos at the top, after any local-value
1224 FastIS->recomputeInsertPt();
1226 // Try to select the instruction with FastISel.
1227 if (FastIS->selectInstruction(Inst)) {
1228 --NumFastIselRemaining;
1229 ++NumFastIselSuccess;
1230 // If fast isel succeeded, skip over all the folded instructions, and
1231 // then see if there is a load right before the selected instructions.
1232 // Try to fold the load if so.
1233 const Instruction *BeforeInst = Inst;
1234 while (BeforeInst != Begin) {
1235 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1236 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1239 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1240 BeforeInst->hasOneUse() &&
1241 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1242 // If we succeeded, don't re-select the load.
1243 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1244 --NumFastIselRemaining;
1245 ++NumFastIselSuccess;
1251 if (EnableFastISelVerbose2)
1252 collectFailStats(Inst);
1255 // Then handle certain instructions as single-LLVM-Instruction blocks.
1256 if (isa<CallInst>(Inst)) {
1258 if (EnableFastISelVerbose || EnableFastISelAbort) {
1259 dbgs() << "FastISel missed call: ";
1262 if (EnableFastISelAbort > 2)
1263 // FastISel selector couldn't handle something and bailed.
1264 // For the purpose of debugging, just abort.
1265 report_fatal_error("FastISel didn't select the entire block");
1267 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1268 unsigned &R = FuncInfo->ValueMap[Inst];
1270 R = FuncInfo->CreateRegs(Inst->getType());
1273 bool HadTailCall = false;
1274 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1275 SelectBasicBlock(Inst, BI, HadTailCall);
1277 // If the call was emitted as a tail call, we're done with the block.
1278 // We also need to delete any previously emitted instructions.
1280 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1285 // Recompute NumFastIselRemaining as Selection DAG instruction
1286 // selection may have handled the call, input args, etc.
1287 unsigned RemainingNow = std::distance(Begin, BI);
1288 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1289 NumFastIselRemaining = RemainingNow;
1293 bool ShouldAbort = EnableFastISelAbort;
1294 if (EnableFastISelVerbose || EnableFastISelAbort) {
1295 if (isa<TerminatorInst>(Inst)) {
1296 // Use a different message for terminator misses.
1297 dbgs() << "FastISel missed terminator: ";
1298 // Don't abort unless for terminator unless the level is really high
1299 ShouldAbort = (EnableFastISelAbort > 2);
1301 dbgs() << "FastISel miss: ";
1306 // FastISel selector couldn't handle something and bailed.
1307 // For the purpose of debugging, just abort.
1308 report_fatal_error("FastISel didn't select the entire block");
1310 NumFastIselFailures += NumFastIselRemaining;
1314 FastIS->recomputeInsertPt();
1316 // Lower any arguments needed in this block if this is the entry block.
1317 if (LLVMBB == &Fn.getEntryBlock()) {
1326 ++NumFastIselBlocks;
1329 // Run SelectionDAG instruction selection on the remainder of the block
1330 // not handled by FastISel. If FastISel is not run, this is the entire
1333 SelectBasicBlock(Begin, BI, HadTailCall);
1337 FuncInfo->PHINodesToUpdate.clear();
1341 SDB->clearDanglingDebugInfo();
1342 SDB->SPDescriptor.resetPerFunctionState();
1345 /// Given that the input MI is before a partial terminator sequence TSeq, return
1346 /// true if M + TSeq also a partial terminator sequence.
1348 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1349 /// lowering copy vregs into physical registers, which are then passed into
1350 /// terminator instructors so we can satisfy ABI constraints. A partial
1351 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1352 /// may be the whole terminator sequence).
1353 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1354 // If we do not have a copy or an implicit def, we return true if and only if
1355 // MI is a debug value.
1356 if (!MI->isCopy() && !MI->isImplicitDef())
1357 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1358 // physical registers if there is debug info associated with the terminator
1359 // of our mbb. We want to include said debug info in our terminator
1360 // sequence, so we return true in that case.
1361 return MI->isDebugValue();
1363 // We have left the terminator sequence if we are not doing one of the
1366 // 1. Copying a vreg into a physical register.
1367 // 2. Copying a vreg into a vreg.
1368 // 3. Defining a register via an implicit def.
1370 // OPI should always be a register definition...
1371 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1372 if (!OPI->isReg() || !OPI->isDef())
1375 // Defining any register via an implicit def is always ok.
1376 if (MI->isImplicitDef())
1379 // Grab the copy source...
1380 MachineInstr::const_mop_iterator OPI2 = OPI;
1382 assert(OPI2 != MI->operands_end()
1383 && "Should have a copy implying we should have 2 arguments.");
1385 // Make sure that the copy dest is not a vreg when the copy source is a
1386 // physical register.
1387 if (!OPI2->isReg() ||
1388 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1389 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1395 /// Find the split point at which to splice the end of BB into its success stack
1396 /// protector check machine basic block.
1398 /// On many platforms, due to ABI constraints, terminators, even before register
1399 /// allocation, use physical registers. This creates an issue for us since
1400 /// physical registers at this point can not travel across basic
1401 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1402 /// when they enter functions and moves them through a sequence of copies back
1403 /// into the physical registers right before the terminator creating a
1404 /// ``Terminator Sequence''. This function is searching for the beginning of the
1405 /// terminator sequence so that we can ensure that we splice off not just the
1406 /// terminator, but additionally the copies that move the vregs into the
1407 /// physical registers.
1408 static MachineBasicBlock::iterator
1409 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1410 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1412 if (SplitPoint == BB->begin())
1415 MachineBasicBlock::iterator Start = BB->begin();
1416 MachineBasicBlock::iterator Previous = SplitPoint;
1419 while (MIIsInTerminatorSequence(Previous)) {
1420 SplitPoint = Previous;
1421 if (Previous == Start)
1430 SelectionDAGISel::FinishBasicBlock() {
1432 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1433 << FuncInfo->PHINodesToUpdate.size() << "\n";
1434 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1435 dbgs() << "Node " << i << " : ("
1436 << FuncInfo->PHINodesToUpdate[i].first
1437 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1439 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1440 SDB->JTCases.empty() &&
1441 SDB->BitTestCases.empty();
1443 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1444 // PHI nodes in successors.
1445 if (MustUpdatePHINodes) {
1446 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1447 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1448 assert(PHI->isPHI() &&
1449 "This is not a machine PHI node that we are updating!");
1450 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1452 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1456 // Handle stack protector.
1457 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1458 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1459 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1461 // Find the split point to split the parent mbb. At the same time copy all
1462 // physical registers used in the tail of parent mbb into virtual registers
1463 // before the split point and back into physical registers after the split
1464 // point. This prevents us needing to deal with Live-ins and many other
1465 // register allocation issues caused by us splitting the parent mbb. The
1466 // register allocator will clean up said virtual copies later on.
1467 MachineBasicBlock::iterator SplitPoint =
1468 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1470 // Splice the terminator of ParentMBB into SuccessMBB.
1471 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1475 // Add compare/jump on neq/jump to the parent BB.
1476 FuncInfo->MBB = ParentMBB;
1477 FuncInfo->InsertPt = ParentMBB->end();
1478 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1479 CurDAG->setRoot(SDB->getRoot());
1481 CodeGenAndEmitDAG();
1483 // CodeGen Failure MBB if we have not codegened it yet.
1484 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1485 if (!FailureMBB->size()) {
1486 FuncInfo->MBB = FailureMBB;
1487 FuncInfo->InsertPt = FailureMBB->end();
1488 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1489 CurDAG->setRoot(SDB->getRoot());
1491 CodeGenAndEmitDAG();
1494 // Clear the Per-BB State.
1495 SDB->SPDescriptor.resetPerBBState();
1498 // If we updated PHI Nodes, return early.
1499 if (MustUpdatePHINodes)
1502 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1503 // Lower header first, if it wasn't already lowered
1504 if (!SDB->BitTestCases[i].Emitted) {
1505 // Set the current basic block to the mbb we wish to insert the code into
1506 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1507 FuncInfo->InsertPt = FuncInfo->MBB->end();
1509 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1510 CurDAG->setRoot(SDB->getRoot());
1512 CodeGenAndEmitDAG();
1515 uint32_t UnhandledWeight = 0;
1516 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1517 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1519 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1520 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1521 // Set the current basic block to the mbb we wish to insert the code into
1522 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1523 FuncInfo->InsertPt = FuncInfo->MBB->end();
1526 SDB->visitBitTestCase(SDB->BitTestCases[i],
1527 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1529 SDB->BitTestCases[i].Reg,
1530 SDB->BitTestCases[i].Cases[j],
1533 SDB->visitBitTestCase(SDB->BitTestCases[i],
1534 SDB->BitTestCases[i].Default,
1536 SDB->BitTestCases[i].Reg,
1537 SDB->BitTestCases[i].Cases[j],
1541 CurDAG->setRoot(SDB->getRoot());
1543 CodeGenAndEmitDAG();
1547 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1549 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1550 MachineBasicBlock *PHIBB = PHI->getParent();
1551 assert(PHI->isPHI() &&
1552 "This is not a machine PHI node that we are updating!");
1553 // This is "default" BB. We have two jumps to it. From "header" BB and
1554 // from last "case" BB.
1555 if (PHIBB == SDB->BitTestCases[i].Default)
1556 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1557 .addMBB(SDB->BitTestCases[i].Parent)
1558 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1559 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1560 // One of "cases" BB.
1561 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1563 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1564 if (cBB->isSuccessor(PHIBB))
1565 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1569 SDB->BitTestCases.clear();
1571 // If the JumpTable record is filled in, then we need to emit a jump table.
1572 // Updating the PHI nodes is tricky in this case, since we need to determine
1573 // whether the PHI is a successor of the range check MBB or the jump table MBB
1574 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1575 // Lower header first, if it wasn't already lowered
1576 if (!SDB->JTCases[i].first.Emitted) {
1577 // Set the current basic block to the mbb we wish to insert the code into
1578 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1579 FuncInfo->InsertPt = FuncInfo->MBB->end();
1581 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1583 CurDAG->setRoot(SDB->getRoot());
1585 CodeGenAndEmitDAG();
1588 // Set the current basic block to the mbb we wish to insert the code into
1589 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1590 FuncInfo->InsertPt = FuncInfo->MBB->end();
1592 SDB->visitJumpTable(SDB->JTCases[i].second);
1593 CurDAG->setRoot(SDB->getRoot());
1595 CodeGenAndEmitDAG();
1598 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1600 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1601 MachineBasicBlock *PHIBB = PHI->getParent();
1602 assert(PHI->isPHI() &&
1603 "This is not a machine PHI node that we are updating!");
1604 // "default" BB. We can go there only from header BB.
1605 if (PHIBB == SDB->JTCases[i].second.Default)
1606 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1607 .addMBB(SDB->JTCases[i].first.HeaderBB);
1608 // JT BB. Just iterate over successors here
1609 if (FuncInfo->MBB->isSuccessor(PHIBB))
1610 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1613 SDB->JTCases.clear();
1615 // If the switch block involved a branch to one of the actual successors, we
1616 // need to update PHI nodes in that block.
1617 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1618 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1619 assert(PHI->isPHI() &&
1620 "This is not a machine PHI node that we are updating!");
1621 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1622 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1625 // If we generated any switch lowering information, build and codegen any
1626 // additional DAGs necessary.
1627 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1628 // Set the current basic block to the mbb we wish to insert the code into
1629 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1630 FuncInfo->InsertPt = FuncInfo->MBB->end();
1632 // Determine the unique successors.
1633 SmallVector<MachineBasicBlock *, 2> Succs;
1634 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1635 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1636 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1638 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1639 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1640 CurDAG->setRoot(SDB->getRoot());
1642 CodeGenAndEmitDAG();
1644 // Remember the last block, now that any splitting is done, for use in
1645 // populating PHI nodes in successors.
1646 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1648 // Handle any PHI nodes in successors of this chunk, as if we were coming
1649 // from the original BB before switch expansion. Note that PHI nodes can
1650 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1651 // handle them the right number of times.
1652 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1653 FuncInfo->MBB = Succs[i];
1654 FuncInfo->InsertPt = FuncInfo->MBB->end();
1655 // FuncInfo->MBB may have been removed from the CFG if a branch was
1657 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1658 for (MachineBasicBlock::iterator
1659 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1660 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1661 MachineInstrBuilder PHI(*MF, MBBI);
1662 // This value for this PHI node is recorded in PHINodesToUpdate.
1663 for (unsigned pn = 0; ; ++pn) {
1664 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1665 "Didn't find PHI entry!");
1666 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1667 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1675 SDB->SwitchCases.clear();
1679 /// Create the scheduler. If a specific scheduler was specified
1680 /// via the SchedulerRegistry, use it, otherwise select the
1681 /// one preferred by the target.
1683 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1684 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1688 RegisterScheduler::setDefault(Ctor);
1691 return Ctor(this, OptLevel);
1694 //===----------------------------------------------------------------------===//
1695 // Helper functions used by the generated instruction selector.
1696 //===----------------------------------------------------------------------===//
1697 // Calls to these methods are generated by tblgen.
1699 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1700 /// the dag combiner simplified the 255, we still want to match. RHS is the
1701 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1702 /// specified in the .td file (e.g. 255).
1703 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1704 int64_t DesiredMaskS) const {
1705 const APInt &ActualMask = RHS->getAPIntValue();
1706 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1708 // If the actual mask exactly matches, success!
1709 if (ActualMask == DesiredMask)
1712 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1713 if (ActualMask.intersects(~DesiredMask))
1716 // Otherwise, the DAG Combiner may have proven that the value coming in is
1717 // either already zero or is not demanded. Check for known zero input bits.
1718 APInt NeededMask = DesiredMask & ~ActualMask;
1719 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1722 // TODO: check to see if missing bits are just not demanded.
1724 // Otherwise, this pattern doesn't match.
1728 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1729 /// the dag combiner simplified the 255, we still want to match. RHS is the
1730 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1731 /// specified in the .td file (e.g. 255).
1732 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1733 int64_t DesiredMaskS) const {
1734 const APInt &ActualMask = RHS->getAPIntValue();
1735 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1737 // If the actual mask exactly matches, success!
1738 if (ActualMask == DesiredMask)
1741 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1742 if (ActualMask.intersects(~DesiredMask))
1745 // Otherwise, the DAG Combiner may have proven that the value coming in is
1746 // either already zero or is not demanded. Check for known zero input bits.
1747 APInt NeededMask = DesiredMask & ~ActualMask;
1749 APInt KnownZero, KnownOne;
1750 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1752 // If all the missing bits in the or are already known to be set, match!
1753 if ((NeededMask & KnownOne) == NeededMask)
1756 // TODO: check to see if missing bits are just not demanded.
1758 // Otherwise, this pattern doesn't match.
1763 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1764 /// by tblgen. Others should not call it.
1765 void SelectionDAGISel::
1766 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1767 std::vector<SDValue> InOps;
1768 std::swap(InOps, Ops);
1770 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1771 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1772 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1773 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1775 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1776 if (InOps[e-1].getValueType() == MVT::Glue)
1777 --e; // Don't process a glue operand if it is here.
1780 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1781 if (!InlineAsm::isMemKind(Flags)) {
1782 // Just skip over this operand, copying the operands verbatim.
1783 Ops.insert(Ops.end(), InOps.begin()+i,
1784 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1785 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1787 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1788 "Memory operand with multiple values?");
1790 unsigned TiedToOperand;
1791 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1792 // We need the constraint ID from the operand this is tied to.
1793 unsigned CurOp = InlineAsm::Op_FirstOperand;
1794 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1795 for (; TiedToOperand; --TiedToOperand) {
1796 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1797 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1801 // Otherwise, this is a memory operand. Ask the target to select it.
1802 std::vector<SDValue> SelOps;
1803 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1804 InlineAsm::getMemoryConstraintID(Flags),
1806 report_fatal_error("Could not match memory address. Inline asm"
1809 // Add this to the output node.
1811 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1812 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1813 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1818 // Add the glue input back if present.
1819 if (e != InOps.size())
1820 Ops.push_back(InOps.back());
1823 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1826 static SDNode *findGlueUse(SDNode *N) {
1827 unsigned FlagResNo = N->getNumValues()-1;
1828 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1829 SDUse &Use = I.getUse();
1830 if (Use.getResNo() == FlagResNo)
1831 return Use.getUser();
1836 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1837 /// This function recursively traverses up the operand chain, ignoring
1839 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1840 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1841 bool IgnoreChains) {
1842 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1843 // greater than all of its (recursive) operands. If we scan to a point where
1844 // 'use' is smaller than the node we're scanning for, then we know we will
1847 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1848 // happen because we scan down to newly selected nodes in the case of glue
1850 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1853 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1854 // won't fail if we scan it again.
1855 if (!Visited.insert(Use).second)
1858 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1859 // Ignore chain uses, they are validated by HandleMergeInputChains.
1860 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1863 SDNode *N = Use->getOperand(i).getNode();
1865 if (Use == ImmedUse || Use == Root)
1866 continue; // We are not looking for immediate use.
1871 // Traverse up the operand chain.
1872 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1878 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1879 /// operand node N of U during instruction selection that starts at Root.
1880 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1881 SDNode *Root) const {
1882 if (OptLevel == CodeGenOpt::None) return false;
1883 return N.hasOneUse();
1886 /// IsLegalToFold - Returns true if the specific operand node N of
1887 /// U can be folded during instruction selection that starts at Root.
1888 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1889 CodeGenOpt::Level OptLevel,
1890 bool IgnoreChains) {
1891 if (OptLevel == CodeGenOpt::None) return false;
1893 // If Root use can somehow reach N through a path that that doesn't contain
1894 // U then folding N would create a cycle. e.g. In the following
1895 // diagram, Root can reach N through X. If N is folded into into Root, then
1896 // X is both a predecessor and a successor of U.
1907 // * indicates nodes to be folded together.
1909 // If Root produces glue, then it gets (even more) interesting. Since it
1910 // will be "glued" together with its glue use in the scheduler, we need to
1911 // check if it might reach N.
1930 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1931 // (call it Fold), then X is a predecessor of GU and a successor of
1932 // Fold. But since Fold and GU are glued together, this will create
1933 // a cycle in the scheduling graph.
1935 // If the node has glue, walk down the graph to the "lowest" node in the
1937 EVT VT = Root->getValueType(Root->getNumValues()-1);
1938 while (VT == MVT::Glue) {
1939 SDNode *GU = findGlueUse(Root);
1943 VT = Root->getValueType(Root->getNumValues()-1);
1945 // If our query node has a glue result with a use, we've walked up it. If
1946 // the user (which has already been selected) has a chain or indirectly uses
1947 // the chain, our WalkChainUsers predicate will not consider it. Because of
1948 // this, we cannot ignore chains in this predicate.
1949 IgnoreChains = false;
1953 SmallPtrSet<SDNode*, 16> Visited;
1954 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1957 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1958 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1959 SelectInlineAsmMemoryOperands(Ops);
1961 const EVT VTs[] = {MVT::Other, MVT::Glue};
1962 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
1964 return New.getNode();
1968 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1970 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
1971 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1973 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
1974 SDValue New = CurDAG->getCopyFromReg(
1975 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
1977 return New.getNode();
1981 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1983 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1984 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1985 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1986 Op->getOperand(2).getValueType());
1987 SDValue New = CurDAG->getCopyToReg(
1988 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
1990 return New.getNode();
1995 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1996 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1999 /// GetVBR - decode a vbr encoding whose top bit is set.
2000 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
2001 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
2002 assert(Val >= 128 && "Not a VBR");
2003 Val &= 127; // Remove first vbr bit.
2008 NextBits = MatcherTable[Idx++];
2009 Val |= (NextBits&127) << Shift;
2011 } while (NextBits & 128);
2017 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
2018 /// interior glue and chain results to use the new glue and chain results.
2019 void SelectionDAGISel::
2020 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
2021 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
2023 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
2024 bool isMorphNodeTo) {
2025 SmallVector<SDNode*, 4> NowDeadNodes;
2027 // Now that all the normal results are replaced, we replace the chain and
2028 // glue results if present.
2029 if (!ChainNodesMatched.empty()) {
2030 assert(InputChain.getNode() &&
2031 "Matched input chains but didn't produce a chain");
2032 // Loop over all of the nodes we matched that produced a chain result.
2033 // Replace all the chain results with the final chain we ended up with.
2034 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2035 SDNode *ChainNode = ChainNodesMatched[i];
2037 // If this node was already deleted, don't look at it.
2038 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2041 // Don't replace the results of the root node if we're doing a
2043 if (ChainNode == NodeToMatch && isMorphNodeTo)
2046 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2047 if (ChainVal.getValueType() == MVT::Glue)
2048 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2049 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2050 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2052 // If the node became dead and we haven't already seen it, delete it.
2053 if (ChainNode->use_empty() &&
2054 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2055 NowDeadNodes.push_back(ChainNode);
2059 // If the result produces glue, update any glue results in the matched
2060 // pattern with the glue result.
2061 if (InputGlue.getNode()) {
2062 // Handle any interior nodes explicitly marked.
2063 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2064 SDNode *FRN = GlueResultNodesMatched[i];
2066 // If this node was already deleted, don't look at it.
2067 if (FRN->getOpcode() == ISD::DELETED_NODE)
2070 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2071 "Doesn't have a glue result");
2072 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2075 // If the node became dead and we haven't already seen it, delete it.
2076 if (FRN->use_empty() &&
2077 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2078 NowDeadNodes.push_back(FRN);
2082 if (!NowDeadNodes.empty())
2083 CurDAG->RemoveDeadNodes(NowDeadNodes);
2085 DEBUG(dbgs() << "ISEL: Match complete!\n");
2091 CR_LeadsToInteriorNode
2094 /// WalkChainUsers - Walk down the users of the specified chained node that is
2095 /// part of the pattern we're matching, looking at all of the users we find.
2096 /// This determines whether something is an interior node, whether we have a
2097 /// non-pattern node in between two pattern nodes (which prevent folding because
2098 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2099 /// between pattern nodes (in which case the TF becomes part of the pattern).
2101 /// The walk we do here is guaranteed to be small because we quickly get down to
2102 /// already selected nodes "below" us.
2104 WalkChainUsers(const SDNode *ChainedNode,
2105 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2106 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2107 ChainResult Result = CR_Simple;
2109 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2110 E = ChainedNode->use_end(); UI != E; ++UI) {
2111 // Make sure the use is of the chain, not some other value we produce.
2112 if (UI.getUse().getValueType() != MVT::Other) continue;
2116 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2119 // If we see an already-selected machine node, then we've gone beyond the
2120 // pattern that we're selecting down into the already selected chunk of the
2122 unsigned UserOpcode = User->getOpcode();
2123 if (User->isMachineOpcode() ||
2124 UserOpcode == ISD::CopyToReg ||
2125 UserOpcode == ISD::CopyFromReg ||
2126 UserOpcode == ISD::INLINEASM ||
2127 UserOpcode == ISD::EH_LABEL ||
2128 UserOpcode == ISD::LIFETIME_START ||
2129 UserOpcode == ISD::LIFETIME_END) {
2130 // If their node ID got reset to -1 then they've already been selected.
2131 // Treat them like a MachineOpcode.
2132 if (User->getNodeId() == -1)
2136 // If we have a TokenFactor, we handle it specially.
2137 if (User->getOpcode() != ISD::TokenFactor) {
2138 // If the node isn't a token factor and isn't part of our pattern, then it
2139 // must be a random chained node in between two nodes we're selecting.
2140 // This happens when we have something like:
2145 // Because we structurally match the load/store as a read/modify/write,
2146 // but the call is chained between them. We cannot fold in this case
2147 // because it would induce a cycle in the graph.
2148 if (!std::count(ChainedNodesInPattern.begin(),
2149 ChainedNodesInPattern.end(), User))
2150 return CR_InducesCycle;
2152 // Otherwise we found a node that is part of our pattern. For example in:
2156 // This would happen when we're scanning down from the load and see the
2157 // store as a user. Record that there is a use of ChainedNode that is
2158 // part of the pattern and keep scanning uses.
2159 Result = CR_LeadsToInteriorNode;
2160 InteriorChainedNodes.push_back(User);
2164 // If we found a TokenFactor, there are two cases to consider: first if the
2165 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2166 // uses of the TF are in our pattern) we just want to ignore it. Second,
2167 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2173 // | \ DAG's like cheese
2176 // [TokenFactor] [Op]
2183 // In this case, the TokenFactor becomes part of our match and we rewrite it
2184 // as a new TokenFactor.
2186 // To distinguish these two cases, do a recursive walk down the uses.
2187 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2189 // If the uses of the TokenFactor are just already-selected nodes, ignore
2190 // it, it is "below" our pattern.
2192 case CR_InducesCycle:
2193 // If the uses of the TokenFactor lead to nodes that are not part of our
2194 // pattern that are not selected, folding would turn this into a cycle,
2196 return CR_InducesCycle;
2197 case CR_LeadsToInteriorNode:
2198 break; // Otherwise, keep processing.
2201 // Okay, we know we're in the interesting interior case. The TokenFactor
2202 // is now going to be considered part of the pattern so that we rewrite its
2203 // uses (it may have uses that are not part of the pattern) with the
2204 // ultimate chain result of the generated code. We will also add its chain
2205 // inputs as inputs to the ultimate TokenFactor we create.
2206 Result = CR_LeadsToInteriorNode;
2207 ChainedNodesInPattern.push_back(User);
2208 InteriorChainedNodes.push_back(User);
2215 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2216 /// operation for when the pattern matched at least one node with a chains. The
2217 /// input vector contains a list of all of the chained nodes that we match. We
2218 /// must determine if this is a valid thing to cover (i.e. matching it won't
2219 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2220 /// be used as the input node chain for the generated nodes.
2222 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2223 SelectionDAG *CurDAG) {
2224 // Walk all of the chained nodes we've matched, recursively scanning down the
2225 // users of the chain result. This adds any TokenFactor nodes that are caught
2226 // in between chained nodes to the chained and interior nodes list.
2227 SmallVector<SDNode*, 3> InteriorChainedNodes;
2228 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2229 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2230 InteriorChainedNodes) == CR_InducesCycle)
2231 return SDValue(); // Would induce a cycle.
2234 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2235 // that we are interested in. Form our input TokenFactor node.
2236 SmallVector<SDValue, 3> InputChains;
2237 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2238 // Add the input chain of this node to the InputChains list (which will be
2239 // the operands of the generated TokenFactor) if it's not an interior node.
2240 SDNode *N = ChainNodesMatched[i];
2241 if (N->getOpcode() != ISD::TokenFactor) {
2242 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2245 // Otherwise, add the input chain.
2246 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2247 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2248 InputChains.push_back(InChain);
2252 // If we have a token factor, we want to add all inputs of the token factor
2253 // that are not part of the pattern we're matching.
2254 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2255 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2256 N->getOperand(op).getNode()))
2257 InputChains.push_back(N->getOperand(op));
2261 if (InputChains.size() == 1)
2262 return InputChains[0];
2263 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2264 MVT::Other, InputChains);
2267 /// MorphNode - Handle morphing a node in place for the selector.
2268 SDNode *SelectionDAGISel::
2269 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2270 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2271 // It is possible we're using MorphNodeTo to replace a node with no
2272 // normal results with one that has a normal result (or we could be
2273 // adding a chain) and the input could have glue and chains as well.
2274 // In this case we need to shift the operands down.
2275 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2276 // than the old isel though.
2277 int OldGlueResultNo = -1, OldChainResultNo = -1;
2279 unsigned NTMNumResults = Node->getNumValues();
2280 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2281 OldGlueResultNo = NTMNumResults-1;
2282 if (NTMNumResults != 1 &&
2283 Node->getValueType(NTMNumResults-2) == MVT::Other)
2284 OldChainResultNo = NTMNumResults-2;
2285 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2286 OldChainResultNo = NTMNumResults-1;
2288 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2289 // that this deletes operands of the old node that become dead.
2290 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2292 // MorphNodeTo can operate in two ways: if an existing node with the
2293 // specified operands exists, it can just return it. Otherwise, it
2294 // updates the node in place to have the requested operands.
2296 // If we updated the node in place, reset the node ID. To the isel,
2297 // this should be just like a newly allocated machine node.
2301 unsigned ResNumResults = Res->getNumValues();
2302 // Move the glue if needed.
2303 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2304 (unsigned)OldGlueResultNo != ResNumResults-1)
2305 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2306 SDValue(Res, ResNumResults-1));
2308 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2311 // Move the chain reference if needed.
2312 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2313 (unsigned)OldChainResultNo != ResNumResults-1)
2314 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2315 SDValue(Res, ResNumResults-1));
2317 // Otherwise, no replacement happened because the node already exists. Replace
2318 // Uses of the old node with the new one.
2320 CurDAG->ReplaceAllUsesWith(Node, Res);
2325 /// CheckSame - Implements OP_CheckSame.
2326 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2327 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2329 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2330 // Accept if it is exactly the same as a previously recorded node.
2331 unsigned RecNo = MatcherTable[MatcherIndex++];
2332 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2333 return N == RecordedNodes[RecNo].first;
2336 /// CheckChildSame - Implements OP_CheckChildXSame.
2337 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2338 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2340 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2342 if (ChildNo >= N.getNumOperands())
2343 return false; // Match fails if out of range child #.
2344 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2348 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2349 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2350 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2351 const SelectionDAGISel &SDISel) {
2352 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2355 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2356 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2357 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2358 const SelectionDAGISel &SDISel, SDNode *N) {
2359 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2362 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2363 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2365 uint16_t Opc = MatcherTable[MatcherIndex++];
2366 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2367 return N->getOpcode() == Opc;
2370 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2371 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2372 SDValue N, const TargetLowering *TLI) {
2373 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2374 if (N.getValueType() == VT) return true;
2376 // Handle the case when VT is iPTR.
2377 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2380 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2381 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2382 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2383 if (ChildNo >= N.getNumOperands())
2384 return false; // Match fails if out of range child #.
2385 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2388 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2389 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2391 return cast<CondCodeSDNode>(N)->get() ==
2392 (ISD::CondCode)MatcherTable[MatcherIndex++];
2395 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2396 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2397 SDValue N, const TargetLowering *TLI) {
2398 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2399 if (cast<VTSDNode>(N)->getVT() == VT)
2402 // Handle the case when VT is iPTR.
2403 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2406 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2407 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2409 int64_t Val = MatcherTable[MatcherIndex++];
2411 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2413 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2414 return C && C->getSExtValue() == Val;
2417 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2418 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2419 SDValue N, unsigned ChildNo) {
2420 if (ChildNo >= N.getNumOperands())
2421 return false; // Match fails if out of range child #.
2422 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2425 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2426 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2427 SDValue N, const SelectionDAGISel &SDISel) {
2428 int64_t Val = MatcherTable[MatcherIndex++];
2430 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2432 if (N->getOpcode() != ISD::AND) return false;
2434 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2435 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2438 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2439 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2440 SDValue N, const SelectionDAGISel &SDISel) {
2441 int64_t Val = MatcherTable[MatcherIndex++];
2443 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2445 if (N->getOpcode() != ISD::OR) return false;
2447 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2448 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2451 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2452 /// scope, evaluate the current node. If the current predicate is known to
2453 /// fail, set Result=true and return anything. If the current predicate is
2454 /// known to pass, set Result=false and return the MatcherIndex to continue
2455 /// with. If the current predicate is unknown, set Result=false and return the
2456 /// MatcherIndex to continue with.
2457 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2458 unsigned Index, SDValue N,
2460 const SelectionDAGISel &SDISel,
2461 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2462 switch (Table[Index++]) {
2465 return Index-1; // Could not evaluate this predicate.
2466 case SelectionDAGISel::OPC_CheckSame:
2467 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2469 case SelectionDAGISel::OPC_CheckChild0Same:
2470 case SelectionDAGISel::OPC_CheckChild1Same:
2471 case SelectionDAGISel::OPC_CheckChild2Same:
2472 case SelectionDAGISel::OPC_CheckChild3Same:
2473 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2474 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2476 case SelectionDAGISel::OPC_CheckPatternPredicate:
2477 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2479 case SelectionDAGISel::OPC_CheckPredicate:
2480 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2482 case SelectionDAGISel::OPC_CheckOpcode:
2483 Result = !::CheckOpcode(Table, Index, N.getNode());
2485 case SelectionDAGISel::OPC_CheckType:
2486 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2488 case SelectionDAGISel::OPC_CheckChild0Type:
2489 case SelectionDAGISel::OPC_CheckChild1Type:
2490 case SelectionDAGISel::OPC_CheckChild2Type:
2491 case SelectionDAGISel::OPC_CheckChild3Type:
2492 case SelectionDAGISel::OPC_CheckChild4Type:
2493 case SelectionDAGISel::OPC_CheckChild5Type:
2494 case SelectionDAGISel::OPC_CheckChild6Type:
2495 case SelectionDAGISel::OPC_CheckChild7Type:
2496 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2498 SelectionDAGISel::OPC_CheckChild0Type);
2500 case SelectionDAGISel::OPC_CheckCondCode:
2501 Result = !::CheckCondCode(Table, Index, N);
2503 case SelectionDAGISel::OPC_CheckValueType:
2504 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2506 case SelectionDAGISel::OPC_CheckInteger:
2507 Result = !::CheckInteger(Table, Index, N);
2509 case SelectionDAGISel::OPC_CheckChild0Integer:
2510 case SelectionDAGISel::OPC_CheckChild1Integer:
2511 case SelectionDAGISel::OPC_CheckChild2Integer:
2512 case SelectionDAGISel::OPC_CheckChild3Integer:
2513 case SelectionDAGISel::OPC_CheckChild4Integer:
2514 Result = !::CheckChildInteger(Table, Index, N,
2515 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2517 case SelectionDAGISel::OPC_CheckAndImm:
2518 Result = !::CheckAndImm(Table, Index, N, SDISel);
2520 case SelectionDAGISel::OPC_CheckOrImm:
2521 Result = !::CheckOrImm(Table, Index, N, SDISel);
2529 /// FailIndex - If this match fails, this is the index to continue with.
2532 /// NodeStack - The node stack when the scope was formed.
2533 SmallVector<SDValue, 4> NodeStack;
2535 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2536 unsigned NumRecordedNodes;
2538 /// NumMatchedMemRefs - The number of matched memref entries.
2539 unsigned NumMatchedMemRefs;
2541 /// InputChain/InputGlue - The current chain/glue
2542 SDValue InputChain, InputGlue;
2544 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2545 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2548 /// \\brief A DAG update listener to keep the matching state
2549 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2550 /// change the DAG while matching. X86 addressing mode matcher is an example
2552 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2554 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2555 SmallVectorImpl<MatchScope> &MatchScopes;
2557 MatchStateUpdater(SelectionDAG &DAG,
2558 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2559 SmallVectorImpl<MatchScope> &MS) :
2560 SelectionDAG::DAGUpdateListener(DAG),
2561 RecordedNodes(RN), MatchScopes(MS) { }
2563 void NodeDeleted(SDNode *N, SDNode *E) {
2564 // Some early-returns here to avoid the search if we deleted the node or
2565 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2566 // do, so it's unnecessary to update matching state at that point).
2567 // Neither of these can occur currently because we only install this
2568 // update listener during matching a complex patterns.
2569 if (!E || E->isMachineOpcode())
2571 // Performing linear search here does not matter because we almost never
2572 // run this code. You'd have to have a CSE during complex pattern
2574 for (auto &I : RecordedNodes)
2575 if (I.first.getNode() == N)
2578 for (auto &I : MatchScopes)
2579 for (auto &J : I.NodeStack)
2580 if (J.getNode() == N)
2586 SDNode *SelectionDAGISel::
2587 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2588 unsigned TableSize) {
2589 // FIXME: Should these even be selected? Handle these cases in the caller?
2590 switch (NodeToMatch->getOpcode()) {
2593 case ISD::EntryToken: // These nodes remain the same.
2594 case ISD::BasicBlock:
2596 case ISD::RegisterMask:
2597 case ISD::HANDLENODE:
2598 case ISD::MDNODE_SDNODE:
2599 case ISD::TargetConstant:
2600 case ISD::TargetConstantFP:
2601 case ISD::TargetConstantPool:
2602 case ISD::TargetFrameIndex:
2603 case ISD::TargetExternalSymbol:
2604 case ISD::TargetBlockAddress:
2605 case ISD::TargetJumpTable:
2606 case ISD::TargetGlobalTLSAddress:
2607 case ISD::TargetGlobalAddress:
2608 case ISD::TokenFactor:
2609 case ISD::CopyFromReg:
2610 case ISD::CopyToReg:
2612 case ISD::LIFETIME_START:
2613 case ISD::LIFETIME_END:
2614 NodeToMatch->setNodeId(-1); // Mark selected.
2616 case ISD::AssertSext:
2617 case ISD::AssertZext:
2618 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2619 NodeToMatch->getOperand(0));
2621 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2622 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2623 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2624 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2627 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2629 // Set up the node stack with NodeToMatch as the only node on the stack.
2630 SmallVector<SDValue, 8> NodeStack;
2631 SDValue N = SDValue(NodeToMatch, 0);
2632 NodeStack.push_back(N);
2634 // MatchScopes - Scopes used when matching, if a match failure happens, this
2635 // indicates where to continue checking.
2636 SmallVector<MatchScope, 8> MatchScopes;
2638 // RecordedNodes - This is the set of nodes that have been recorded by the
2639 // state machine. The second value is the parent of the node, or null if the
2640 // root is recorded.
2641 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2643 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2645 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2647 // These are the current input chain and glue for use when generating nodes.
2648 // Various Emit operations change these. For example, emitting a copytoreg
2649 // uses and updates these.
2650 SDValue InputChain, InputGlue;
2652 // ChainNodesMatched - If a pattern matches nodes that have input/output
2653 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2654 // which ones they are. The result is captured into this list so that we can
2655 // update the chain results when the pattern is complete.
2656 SmallVector<SDNode*, 3> ChainNodesMatched;
2657 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2659 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2660 NodeToMatch->dump(CurDAG);
2663 // Determine where to start the interpreter. Normally we start at opcode #0,
2664 // but if the state machine starts with an OPC_SwitchOpcode, then we
2665 // accelerate the first lookup (which is guaranteed to be hot) with the
2666 // OpcodeOffset table.
2667 unsigned MatcherIndex = 0;
2669 if (!OpcodeOffset.empty()) {
2670 // Already computed the OpcodeOffset table, just index into it.
2671 if (N.getOpcode() < OpcodeOffset.size())
2672 MatcherIndex = OpcodeOffset[N.getOpcode()];
2673 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2675 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2676 // Otherwise, the table isn't computed, but the state machine does start
2677 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2678 // is the first time we're selecting an instruction.
2681 // Get the size of this case.
2682 unsigned CaseSize = MatcherTable[Idx++];
2684 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2685 if (CaseSize == 0) break;
2687 // Get the opcode, add the index to the table.
2688 uint16_t Opc = MatcherTable[Idx++];
2689 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2690 if (Opc >= OpcodeOffset.size())
2691 OpcodeOffset.resize((Opc+1)*2);
2692 OpcodeOffset[Opc] = Idx;
2696 // Okay, do the lookup for the first opcode.
2697 if (N.getOpcode() < OpcodeOffset.size())
2698 MatcherIndex = OpcodeOffset[N.getOpcode()];
2702 assert(MatcherIndex < TableSize && "Invalid index");
2704 unsigned CurrentOpcodeIndex = MatcherIndex;
2706 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2709 // Okay, the semantics of this operation are that we should push a scope
2710 // then evaluate the first child. However, pushing a scope only to have
2711 // the first check fail (which then pops it) is inefficient. If we can
2712 // determine immediately that the first check (or first several) will
2713 // immediately fail, don't even bother pushing a scope for them.
2717 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2718 if (NumToSkip & 128)
2719 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2720 // Found the end of the scope with no match.
2721 if (NumToSkip == 0) {
2726 FailIndex = MatcherIndex+NumToSkip;
2728 unsigned MatcherIndexOfPredicate = MatcherIndex;
2729 (void)MatcherIndexOfPredicate; // silence warning.
2731 // If we can't evaluate this predicate without pushing a scope (e.g. if
2732 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2733 // push the scope and evaluate the full predicate chain.
2735 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2736 Result, *this, RecordedNodes);
2740 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2741 << "index " << MatcherIndexOfPredicate
2742 << ", continuing at " << FailIndex << "\n");
2743 ++NumDAGIselRetries;
2745 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2746 // move to the next case.
2747 MatcherIndex = FailIndex;
2750 // If the whole scope failed to match, bail.
2751 if (FailIndex == 0) break;
2753 // Push a MatchScope which indicates where to go if the first child fails
2755 MatchScope NewEntry;
2756 NewEntry.FailIndex = FailIndex;
2757 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2758 NewEntry.NumRecordedNodes = RecordedNodes.size();
2759 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2760 NewEntry.InputChain = InputChain;
2761 NewEntry.InputGlue = InputGlue;
2762 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2763 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2764 MatchScopes.push_back(NewEntry);
2767 case OPC_RecordNode: {
2768 // Remember this node, it may end up being an operand in the pattern.
2769 SDNode *Parent = nullptr;
2770 if (NodeStack.size() > 1)
2771 Parent = NodeStack[NodeStack.size()-2].getNode();
2772 RecordedNodes.push_back(std::make_pair(N, Parent));
2776 case OPC_RecordChild0: case OPC_RecordChild1:
2777 case OPC_RecordChild2: case OPC_RecordChild3:
2778 case OPC_RecordChild4: case OPC_RecordChild5:
2779 case OPC_RecordChild6: case OPC_RecordChild7: {
2780 unsigned ChildNo = Opcode-OPC_RecordChild0;
2781 if (ChildNo >= N.getNumOperands())
2782 break; // Match fails if out of range child #.
2784 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2788 case OPC_RecordMemRef:
2789 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2792 case OPC_CaptureGlueInput:
2793 // If the current node has an input glue, capture it in InputGlue.
2794 if (N->getNumOperands() != 0 &&
2795 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2796 InputGlue = N->getOperand(N->getNumOperands()-1);
2799 case OPC_MoveChild: {
2800 unsigned ChildNo = MatcherTable[MatcherIndex++];
2801 if (ChildNo >= N.getNumOperands())
2802 break; // Match fails if out of range child #.
2803 N = N.getOperand(ChildNo);
2804 NodeStack.push_back(N);
2808 case OPC_MoveParent:
2809 // Pop the current node off the NodeStack.
2810 NodeStack.pop_back();
2811 assert(!NodeStack.empty() && "Node stack imbalance!");
2812 N = NodeStack.back();
2816 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2819 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2820 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2821 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2822 Opcode-OPC_CheckChild0Same))
2826 case OPC_CheckPatternPredicate:
2827 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2829 case OPC_CheckPredicate:
2830 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2834 case OPC_CheckComplexPat: {
2835 unsigned CPNum = MatcherTable[MatcherIndex++];
2836 unsigned RecNo = MatcherTable[MatcherIndex++];
2837 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2839 // If target can modify DAG during matching, keep the matching state
2841 std::unique_ptr<MatchStateUpdater> MSU;
2842 if (ComplexPatternFuncMutatesDAG())
2843 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2846 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2847 RecordedNodes[RecNo].first, CPNum,
2852 case OPC_CheckOpcode:
2853 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2857 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2861 case OPC_SwitchOpcode: {
2862 unsigned CurNodeOpcode = N.getOpcode();
2863 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2866 // Get the size of this case.
2867 CaseSize = MatcherTable[MatcherIndex++];
2869 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2870 if (CaseSize == 0) break;
2872 uint16_t Opc = MatcherTable[MatcherIndex++];
2873 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2875 // If the opcode matches, then we will execute this case.
2876 if (CurNodeOpcode == Opc)
2879 // Otherwise, skip over this case.
2880 MatcherIndex += CaseSize;
2883 // If no cases matched, bail out.
2884 if (CaseSize == 0) break;
2886 // Otherwise, execute the case we found.
2887 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2888 << " to " << MatcherIndex << "\n");
2892 case OPC_SwitchType: {
2893 MVT CurNodeVT = N.getSimpleValueType();
2894 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2897 // Get the size of this case.
2898 CaseSize = MatcherTable[MatcherIndex++];
2900 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2901 if (CaseSize == 0) break;
2903 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2904 if (CaseVT == MVT::iPTR)
2905 CaseVT = TLI->getPointerTy();
2907 // If the VT matches, then we will execute this case.
2908 if (CurNodeVT == CaseVT)
2911 // Otherwise, skip over this case.
2912 MatcherIndex += CaseSize;
2915 // If no cases matched, bail out.
2916 if (CaseSize == 0) break;
2918 // Otherwise, execute the case we found.
2919 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2920 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2923 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2924 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2925 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2926 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2927 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2928 Opcode-OPC_CheckChild0Type))
2931 case OPC_CheckCondCode:
2932 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2934 case OPC_CheckValueType:
2935 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2938 case OPC_CheckInteger:
2939 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2941 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2942 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2943 case OPC_CheckChild4Integer:
2944 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2945 Opcode-OPC_CheckChild0Integer)) break;
2947 case OPC_CheckAndImm:
2948 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2950 case OPC_CheckOrImm:
2951 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2954 case OPC_CheckFoldableChainNode: {
2955 assert(NodeStack.size() != 1 && "No parent node");
2956 // Verify that all intermediate nodes between the root and this one have
2958 bool HasMultipleUses = false;
2959 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2960 if (!NodeStack[i].hasOneUse()) {
2961 HasMultipleUses = true;
2964 if (HasMultipleUses) break;
2966 // Check to see that the target thinks this is profitable to fold and that
2967 // we can fold it without inducing cycles in the graph.
2968 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2970 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2971 NodeToMatch, OptLevel,
2972 true/*We validate our own chains*/))
2977 case OPC_EmitInteger: {
2978 MVT::SimpleValueType VT =
2979 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2980 int64_t Val = MatcherTable[MatcherIndex++];
2982 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2983 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2984 CurDAG->getTargetConstant(Val, VT), nullptr));
2987 case OPC_EmitRegister: {
2988 MVT::SimpleValueType VT =
2989 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2990 unsigned RegNo = MatcherTable[MatcherIndex++];
2991 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2992 CurDAG->getRegister(RegNo, VT), nullptr));
2995 case OPC_EmitRegister2: {
2996 // For targets w/ more than 256 register names, the register enum
2997 // values are stored in two bytes in the matcher table (just like
2999 MVT::SimpleValueType VT =
3000 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3001 unsigned RegNo = MatcherTable[MatcherIndex++];
3002 RegNo |= MatcherTable[MatcherIndex++] << 8;
3003 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3004 CurDAG->getRegister(RegNo, VT), nullptr));
3008 case OPC_EmitConvertToTarget: {
3009 // Convert from IMM/FPIMM to target version.
3010 unsigned RecNo = MatcherTable[MatcherIndex++];
3011 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
3012 SDValue Imm = RecordedNodes[RecNo].first;
3014 if (Imm->getOpcode() == ISD::Constant) {
3015 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
3016 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
3017 } else if (Imm->getOpcode() == ISD::ConstantFP) {
3018 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
3019 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
3022 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3026 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
3027 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
3028 // These are space-optimized forms of OPC_EmitMergeInputChains.
3029 assert(!InputChain.getNode() &&
3030 "EmitMergeInputChains should be the first chain producing node");
3031 assert(ChainNodesMatched.empty() &&
3032 "Should only have one EmitMergeInputChains per match");
3034 // Read all of the chained nodes.
3035 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3036 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3037 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3039 // FIXME: What if other value results of the node have uses not matched
3041 if (ChainNodesMatched.back() != NodeToMatch &&
3042 !RecordedNodes[RecNo].first.hasOneUse()) {
3043 ChainNodesMatched.clear();
3047 // Merge the input chains if they are not intra-pattern references.
3048 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3050 if (!InputChain.getNode())
3051 break; // Failed to merge.
3055 case OPC_EmitMergeInputChains: {
3056 assert(!InputChain.getNode() &&
3057 "EmitMergeInputChains should be the first chain producing node");
3058 // This node gets a list of nodes we matched in the input that have
3059 // chains. We want to token factor all of the input chains to these nodes
3060 // together. However, if any of the input chains is actually one of the
3061 // nodes matched in this pattern, then we have an intra-match reference.
3062 // Ignore these because the newly token factored chain should not refer to
3064 unsigned NumChains = MatcherTable[MatcherIndex++];
3065 assert(NumChains != 0 && "Can't TF zero chains");
3067 assert(ChainNodesMatched.empty() &&
3068 "Should only have one EmitMergeInputChains per match");
3070 // Read all of the chained nodes.
3071 for (unsigned i = 0; i != NumChains; ++i) {
3072 unsigned RecNo = MatcherTable[MatcherIndex++];
3073 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3074 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3076 // FIXME: What if other value results of the node have uses not matched
3078 if (ChainNodesMatched.back() != NodeToMatch &&
3079 !RecordedNodes[RecNo].first.hasOneUse()) {
3080 ChainNodesMatched.clear();
3085 // If the inner loop broke out, the match fails.
3086 if (ChainNodesMatched.empty())
3089 // Merge the input chains if they are not intra-pattern references.
3090 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3092 if (!InputChain.getNode())
3093 break; // Failed to merge.
3098 case OPC_EmitCopyToReg: {
3099 unsigned RecNo = MatcherTable[MatcherIndex++];
3100 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3101 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3103 if (!InputChain.getNode())
3104 InputChain = CurDAG->getEntryNode();
3106 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3107 DestPhysReg, RecordedNodes[RecNo].first,
3110 InputGlue = InputChain.getValue(1);
3114 case OPC_EmitNodeXForm: {
3115 unsigned XFormNo = MatcherTable[MatcherIndex++];
3116 unsigned RecNo = MatcherTable[MatcherIndex++];
3117 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3118 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3119 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3124 case OPC_MorphNodeTo: {
3125 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3126 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3127 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3128 // Get the result VT list.
3129 unsigned NumVTs = MatcherTable[MatcherIndex++];
3130 SmallVector<EVT, 4> VTs;
3131 for (unsigned i = 0; i != NumVTs; ++i) {
3132 MVT::SimpleValueType VT =
3133 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3134 if (VT == MVT::iPTR)
3135 VT = TLI->getPointerTy().SimpleTy;
3139 if (EmitNodeInfo & OPFL_Chain)
3140 VTs.push_back(MVT::Other);
3141 if (EmitNodeInfo & OPFL_GlueOutput)
3142 VTs.push_back(MVT::Glue);
3144 // This is hot code, so optimize the two most common cases of 1 and 2
3147 if (VTs.size() == 1)
3148 VTList = CurDAG->getVTList(VTs[0]);
3149 else if (VTs.size() == 2)
3150 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3152 VTList = CurDAG->getVTList(VTs);
3154 // Get the operand list.
3155 unsigned NumOps = MatcherTable[MatcherIndex++];
3156 SmallVector<SDValue, 8> Ops;
3157 for (unsigned i = 0; i != NumOps; ++i) {
3158 unsigned RecNo = MatcherTable[MatcherIndex++];
3160 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3162 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3163 Ops.push_back(RecordedNodes[RecNo].first);
3166 // If there are variadic operands to add, handle them now.
3167 if (EmitNodeInfo & OPFL_VariadicInfo) {
3168 // Determine the start index to copy from.
3169 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3170 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3171 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3172 "Invalid variadic node");
3173 // Copy all of the variadic operands, not including a potential glue
3175 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3177 SDValue V = NodeToMatch->getOperand(i);
3178 if (V.getValueType() == MVT::Glue) break;
3183 // If this has chain/glue inputs, add them.
3184 if (EmitNodeInfo & OPFL_Chain)
3185 Ops.push_back(InputChain);
3186 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3187 Ops.push_back(InputGlue);
3190 SDNode *Res = nullptr;
3191 if (Opcode != OPC_MorphNodeTo) {
3192 // If this is a normal EmitNode command, just create the new node and
3193 // add the results to the RecordedNodes list.
3194 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3197 // Add all the non-glue/non-chain results to the RecordedNodes list.
3198 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3199 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3200 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3204 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3205 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3207 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3208 // We will visit the equivalent node later.
3209 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3213 // If the node had chain/glue results, update our notion of the current
3215 if (EmitNodeInfo & OPFL_GlueOutput) {
3216 InputGlue = SDValue(Res, VTs.size()-1);
3217 if (EmitNodeInfo & OPFL_Chain)
3218 InputChain = SDValue(Res, VTs.size()-2);
3219 } else if (EmitNodeInfo & OPFL_Chain)
3220 InputChain = SDValue(Res, VTs.size()-1);
3222 // If the OPFL_MemRefs glue is set on this node, slap all of the
3223 // accumulated memrefs onto it.
3225 // FIXME: This is vastly incorrect for patterns with multiple outputs
3226 // instructions that access memory and for ComplexPatterns that match
3228 if (EmitNodeInfo & OPFL_MemRefs) {
3229 // Only attach load or store memory operands if the generated
3230 // instruction may load or store.
3231 const MCInstrDesc &MCID = TII->get(TargetOpc);
3232 bool mayLoad = MCID.mayLoad();
3233 bool mayStore = MCID.mayStore();
3235 unsigned NumMemRefs = 0;
3236 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3237 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3238 if ((*I)->isLoad()) {
3241 } else if ((*I)->isStore()) {
3249 MachineSDNode::mmo_iterator MemRefs =
3250 MF->allocateMemRefsArray(NumMemRefs);
3252 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3253 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3254 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3255 if ((*I)->isLoad()) {
3258 } else if ((*I)->isStore()) {
3266 cast<MachineSDNode>(Res)
3267 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3271 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3272 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3274 // If this was a MorphNodeTo then we're completely done!
3275 if (Opcode == OPC_MorphNodeTo) {
3276 // Update chain and glue uses.
3277 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3278 InputGlue, GlueResultNodesMatched, true);
3285 case OPC_MarkGlueResults: {
3286 unsigned NumNodes = MatcherTable[MatcherIndex++];
3288 // Read and remember all the glue-result nodes.
3289 for (unsigned i = 0; i != NumNodes; ++i) {
3290 unsigned RecNo = MatcherTable[MatcherIndex++];
3292 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3294 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3295 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3300 case OPC_CompleteMatch: {
3301 // The match has been completed, and any new nodes (if any) have been
3302 // created. Patch up references to the matched dag to use the newly
3304 unsigned NumResults = MatcherTable[MatcherIndex++];
3306 for (unsigned i = 0; i != NumResults; ++i) {
3307 unsigned ResSlot = MatcherTable[MatcherIndex++];
3309 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3311 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3312 SDValue Res = RecordedNodes[ResSlot].first;
3314 assert(i < NodeToMatch->getNumValues() &&
3315 NodeToMatch->getValueType(i) != MVT::Other &&
3316 NodeToMatch->getValueType(i) != MVT::Glue &&
3317 "Invalid number of results to complete!");
3318 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3319 NodeToMatch->getValueType(i) == MVT::iPTR ||
3320 Res.getValueType() == MVT::iPTR ||
3321 NodeToMatch->getValueType(i).getSizeInBits() ==
3322 Res.getValueType().getSizeInBits()) &&
3323 "invalid replacement");
3324 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3327 // If the root node defines glue, add it to the glue nodes to update list.
3328 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3329 GlueResultNodesMatched.push_back(NodeToMatch);
3331 // Update chain and glue uses.
3332 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3333 InputGlue, GlueResultNodesMatched, false);
3335 assert(NodeToMatch->use_empty() &&
3336 "Didn't replace all uses of the node?");
3338 // FIXME: We just return here, which interacts correctly with SelectRoot
3339 // above. We should fix this to not return an SDNode* anymore.
3344 // If the code reached this point, then the match failed. See if there is
3345 // another child to try in the current 'Scope', otherwise pop it until we
3346 // find a case to check.
3347 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3348 ++NumDAGIselRetries;
3350 if (MatchScopes.empty()) {
3351 CannotYetSelect(NodeToMatch);
3355 // Restore the interpreter state back to the point where the scope was
3357 MatchScope &LastScope = MatchScopes.back();
3358 RecordedNodes.resize(LastScope.NumRecordedNodes);
3360 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3361 N = NodeStack.back();
3363 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3364 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3365 MatcherIndex = LastScope.FailIndex;
3367 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3369 InputChain = LastScope.InputChain;
3370 InputGlue = LastScope.InputGlue;
3371 if (!LastScope.HasChainNodesMatched)
3372 ChainNodesMatched.clear();
3373 if (!LastScope.HasGlueResultNodesMatched)
3374 GlueResultNodesMatched.clear();
3376 // Check to see what the offset is at the new MatcherIndex. If it is zero
3377 // we have reached the end of this scope, otherwise we have another child
3378 // in the current scope to try.
3379 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3380 if (NumToSkip & 128)
3381 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3383 // If we have another child in this scope to match, update FailIndex and
3385 if (NumToSkip != 0) {
3386 LastScope.FailIndex = MatcherIndex+NumToSkip;
3390 // End of this scope, pop it and try the next child in the containing
3392 MatchScopes.pop_back();
3399 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3401 raw_string_ostream Msg(msg);
3402 Msg << "Cannot select: ";
3404 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3405 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3406 N->getOpcode() != ISD::INTRINSIC_VOID) {
3407 N->printrFull(Msg, CurDAG);
3408 Msg << "\nIn function: " << MF->getName();
3410 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3412 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3413 if (iid < Intrinsic::num_intrinsics)
3414 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3415 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3416 Msg << "target intrinsic %" << TII->getName(iid);
3418 Msg << "unknown intrinsic #" << iid;
3420 report_fatal_error(Msg.str());
3423 char SelectionDAGISel::ID = 0;