1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAGISel.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DebugInfo.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/Timer.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLibraryInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Target/TargetRegisterInfo.h"
57 #include "llvm/Target/TargetSubtargetInfo.h"
58 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
62 #define DEBUG_TYPE "isel"
64 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
65 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
66 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
67 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
68 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
69 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
70 STATISTIC(NumFastIselFailLowerArguments,
71 "Number of entry blocks where fast isel failed to lower arguments");
75 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
76 cl::desc("Enable extra verbose messages in the \"fast\" "
77 "instruction selector"));
80 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
81 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
82 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
83 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
84 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
85 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
86 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
88 // Standard binary operators...
89 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
90 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
91 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
92 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
93 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
94 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
95 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
96 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
97 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
98 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
99 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
100 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
102 // Logical operators...
103 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
104 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
105 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
107 // Memory instructions...
108 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
109 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
110 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
111 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
112 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
113 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
114 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
116 // Convert instructions...
117 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
118 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
119 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
120 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
121 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
122 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
123 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
124 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
125 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
126 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
127 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
128 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
130 // Other instructions...
131 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
132 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
133 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
134 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
135 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
136 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
137 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
138 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
139 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
140 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
141 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
142 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
143 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
144 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
145 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 // Intrinsic instructions...
148 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
149 STATISTIC(NumFastIselFailSAddWithOverflow,
150 "Fast isel fails on sadd.with.overflow");
151 STATISTIC(NumFastIselFailUAddWithOverflow,
152 "Fast isel fails on uadd.with.overflow");
153 STATISTIC(NumFastIselFailSSubWithOverflow,
154 "Fast isel fails on ssub.with.overflow");
155 STATISTIC(NumFastIselFailUSubWithOverflow,
156 "Fast isel fails on usub.with.overflow");
157 STATISTIC(NumFastIselFailSMulWithOverflow,
158 "Fast isel fails on smul.with.overflow");
159 STATISTIC(NumFastIselFailUMulWithOverflow,
160 "Fast isel fails on umul.with.overflow");
161 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
162 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
163 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
164 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
168 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
169 cl::desc("Enable verbose messages in the \"fast\" "
170 "instruction selector"));
172 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
173 cl::desc("Enable abort calls when \"fast\" instruction selection "
174 "fails to lower an instruction"));
176 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
177 cl::desc("Enable abort calls when \"fast\" instruction selection "
178 "fails to lower a formal argument"));
182 cl::desc("use Machine Branch Probability Info"),
183 cl::init(true), cl::Hidden);
186 static cl::opt<std::string>
187 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
188 cl::desc("Only display the basic block whose name "
189 "matches this for all view-*-dags options"));
191 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
192 cl::desc("Pop up a window to show dags before the first "
193 "dag combine pass"));
195 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before legalize types"));
198 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
199 cl::desc("Pop up a window to show dags before legalize"));
201 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
202 cl::desc("Pop up a window to show dags before the second "
203 "dag combine pass"));
205 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
206 cl::desc("Pop up a window to show dags before the post legalize types"
207 " dag combine pass"));
209 ViewISelDAGs("view-isel-dags", cl::Hidden,
210 cl::desc("Pop up a window to show isel dags as they are selected"));
212 ViewSchedDAGs("view-sched-dags", cl::Hidden,
213 cl::desc("Pop up a window to show sched dags as they are processed"));
215 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
216 cl::desc("Pop up a window to show SUnit dags after they are processed"));
218 static const bool ViewDAGCombine1 = false,
219 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
220 ViewDAGCombine2 = false,
221 ViewDAGCombineLT = false,
222 ViewISelDAGs = false, ViewSchedDAGs = false,
223 ViewSUnitDAGs = false;
226 //===---------------------------------------------------------------------===//
228 /// RegisterScheduler class - Track the registration of instruction schedulers.
230 //===---------------------------------------------------------------------===//
231 MachinePassRegistry RegisterScheduler::Registry;
233 //===---------------------------------------------------------------------===//
235 /// ISHeuristic command line option for instruction schedulers.
237 //===---------------------------------------------------------------------===//
238 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
239 RegisterPassParser<RegisterScheduler> >
240 ISHeuristic("pre-RA-sched",
241 cl::init(&createDefaultScheduler), cl::Hidden,
242 cl::desc("Instruction schedulers available (before register"
245 static RegisterScheduler
246 defaultListDAGScheduler("default", "Best scheduler for the target",
247 createDefaultScheduler);
250 //===--------------------------------------------------------------------===//
251 /// \brief This class is used by SelectionDAGISel to temporarily override
252 /// the optimization level on a per-function basis.
253 class OptLevelChanger {
254 SelectionDAGISel &IS;
255 CodeGenOpt::Level SavedOptLevel;
259 OptLevelChanger(SelectionDAGISel &ISel,
260 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
261 SavedOptLevel = IS.OptLevel;
262 if (NewOptLevel == SavedOptLevel)
264 IS.OptLevel = NewOptLevel;
265 IS.TM.setOptLevel(NewOptLevel);
266 SavedFastISel = IS.TM.Options.EnableFastISel;
267 if (NewOptLevel == CodeGenOpt::None)
268 IS.TM.setFastISel(true);
269 DEBUG(dbgs() << "\nChanging optimization level for Function "
270 << IS.MF->getFunction()->getName() << "\n");
271 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
272 << " ; After: -O" << NewOptLevel << "\n");
276 if (IS.OptLevel == SavedOptLevel)
278 DEBUG(dbgs() << "\nRestoring optimization level for Function "
279 << IS.MF->getFunction()->getName() << "\n");
280 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
281 << " ; After: -O" << SavedOptLevel << "\n");
282 IS.OptLevel = SavedOptLevel;
283 IS.TM.setOptLevel(SavedOptLevel);
284 IS.TM.setFastISel(SavedFastISel);
288 //===--------------------------------------------------------------------===//
289 /// createDefaultScheduler - This creates an instruction scheduler appropriate
291 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
292 CodeGenOpt::Level OptLevel) {
293 const TargetLowering *TLI = IS->TLI;
294 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
296 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
297 TLI->getSchedulingPreference() == Sched::Source)
298 return createSourceListDAGScheduler(IS, OptLevel);
299 if (TLI->getSchedulingPreference() == Sched::RegPressure)
300 return createBURRListDAGScheduler(IS, OptLevel);
301 if (TLI->getSchedulingPreference() == Sched::Hybrid)
302 return createHybridListDAGScheduler(IS, OptLevel);
303 if (TLI->getSchedulingPreference() == Sched::VLIW)
304 return createVLIWDAGScheduler(IS, OptLevel);
305 assert(TLI->getSchedulingPreference() == Sched::ILP &&
306 "Unknown sched type!");
307 return createILPListDAGScheduler(IS, OptLevel);
311 // EmitInstrWithCustomInserter - This method should be implemented by targets
312 // that mark instructions with the 'usesCustomInserter' flag. These
313 // instructions are special in various ways, which require special support to
314 // insert. The specified MachineInstr is created but not inserted into any
315 // basic blocks, and this method is called to expand it into a sequence of
316 // instructions, potentially also creating new basic blocks and control flow.
317 // When new basic blocks are inserted and the edges from MBB to its successors
318 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
321 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
322 MachineBasicBlock *MBB) const {
324 dbgs() << "If a target marks an instruction with "
325 "'usesCustomInserter', it must implement "
326 "TargetLowering::EmitInstrWithCustomInserter!";
328 llvm_unreachable(nullptr);
331 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
332 SDNode *Node) const {
333 assert(!MI->hasPostISelHook() &&
334 "If a target marks an instruction with 'hasPostISelHook', "
335 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
338 //===----------------------------------------------------------------------===//
339 // SelectionDAGISel code
340 //===----------------------------------------------------------------------===//
342 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
343 CodeGenOpt::Level OL) :
344 MachineFunctionPass(ID), TM(tm),
345 FuncInfo(new FunctionLoweringInfo()),
346 CurDAG(new SelectionDAG(tm, OL)),
347 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
351 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
352 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
353 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
354 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
357 SelectionDAGISel::~SelectionDAGISel() {
363 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
364 AU.addRequired<AliasAnalysis>();
365 AU.addPreserved<AliasAnalysis>();
366 AU.addRequired<GCModuleInfo>();
367 AU.addPreserved<GCModuleInfo>();
368 AU.addRequired<TargetLibraryInfo>();
369 if (UseMBPI && OptLevel != CodeGenOpt::None)
370 AU.addRequired<BranchProbabilityInfo>();
371 MachineFunctionPass::getAnalysisUsage(AU);
374 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
375 /// may trap on it. In this case we have to split the edge so that the path
376 /// through the predecessor block that doesn't go to the phi block doesn't
377 /// execute the possibly trapping instruction.
379 /// This is required for correctness, so it must be done at -O0.
381 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
382 // Loop for blocks with phi nodes.
383 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
384 PHINode *PN = dyn_cast<PHINode>(BB->begin());
388 // For each block with a PHI node, check to see if any of the input values
389 // are potentially trapping constant expressions. Constant expressions are
390 // the only potentially trapping value that can occur as the argument to a
392 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
393 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
394 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
395 if (!CE || !CE->canTrap()) continue;
397 // The only case we have to worry about is when the edge is critical.
398 // Since this block has a PHI Node, we assume it has multiple input
399 // edges: check to see if the pred has multiple successors.
400 BasicBlock *Pred = PN->getIncomingBlock(i);
401 if (Pred->getTerminator()->getNumSuccessors() == 1)
404 // Okay, we have to split this edge.
405 SplitCriticalEdge(Pred->getTerminator(),
406 GetSuccessorNumber(Pred, BB), SDISel, true);
412 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
413 // Do some sanity-checking on the command-line options.
414 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
415 "-fast-isel-verbose requires -fast-isel");
416 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
417 "-fast-isel-abort requires -fast-isel");
419 const Function &Fn = *mf.getFunction();
422 // Reset the target options before resetting the optimization
424 // FIXME: This is a horrible hack and should be processed via
425 // codegen looking at the optimization level explicitly when
426 // it wants to look at it.
427 TM.resetTargetOptions(Fn);
428 // Reset OptLevel to None for optnone functions.
429 CodeGenOpt::Level NewOptLevel = OptLevel;
430 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
431 NewOptLevel = CodeGenOpt::None;
432 OptLevelChanger OLC(*this, NewOptLevel);
434 TII = MF->getSubtarget().getInstrInfo();
435 TLI = MF->getSubtarget().getTargetLowering();
436 RegInfo = &MF->getRegInfo();
437 AA = &getAnalysis<AliasAnalysis>();
438 LibInfo = &getAnalysis<TargetLibraryInfo>();
439 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
441 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
443 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
446 FuncInfo->set(Fn, *MF, CurDAG);
448 if (UseMBPI && OptLevel != CodeGenOpt::None)
449 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
451 FuncInfo->BPI = nullptr;
453 SDB->init(GFI, *AA, LibInfo);
455 MF->setHasInlineAsm(false);
457 SelectAllBasicBlocks(Fn);
459 // If the first basic block in the function has live ins that need to be
460 // copied into vregs, emit the copies into the top of the block before
461 // emitting the code for the block.
462 MachineBasicBlock *EntryMBB = MF->begin();
463 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
464 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
466 DenseMap<unsigned, unsigned> LiveInMap;
467 if (!FuncInfo->ArgDbgValues.empty())
468 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
469 E = RegInfo->livein_end(); LI != E; ++LI)
471 LiveInMap.insert(std::make_pair(LI->first, LI->second));
473 // Insert DBG_VALUE instructions for function arguments to the entry block.
474 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
475 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
476 bool hasFI = MI->getOperand(0).isFI();
478 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
479 if (TargetRegisterInfo::isPhysicalRegister(Reg))
480 EntryMBB->insert(EntryMBB->begin(), MI);
482 MachineInstr *Def = RegInfo->getVRegDef(Reg);
484 MachineBasicBlock::iterator InsertPos = Def;
485 // FIXME: VR def may not be in entry block.
486 Def->getParent()->insert(std::next(InsertPos), MI);
488 DEBUG(dbgs() << "Dropping debug info for dead vreg"
489 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
492 // If Reg is live-in then update debug info to track its copy in a vreg.
493 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
494 if (LDI != LiveInMap.end()) {
495 assert(!hasFI && "There's no handling of frame pointer updating here yet "
497 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
498 MachineBasicBlock::iterator InsertPos = Def;
499 const MDNode *Variable = MI->getDebugVariable();
500 const MDNode *Expr = MI->getDebugExpression();
501 bool IsIndirect = MI->isIndirectDebugValue();
502 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
503 // Def is never a terminator here, so it is ok to increment InsertPos.
504 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
505 TII->get(TargetOpcode::DBG_VALUE), IsIndirect, LDI->second, Offset,
508 // If this vreg is directly copied into an exported register then
509 // that COPY instructions also need DBG_VALUE, if it is the only
510 // user of LDI->second.
511 MachineInstr *CopyUseMI = nullptr;
512 for (MachineRegisterInfo::use_instr_iterator
513 UI = RegInfo->use_instr_begin(LDI->second),
514 E = RegInfo->use_instr_end(); UI != E; ) {
515 MachineInstr *UseMI = &*(UI++);
516 if (UseMI->isDebugValue()) continue;
517 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
518 CopyUseMI = UseMI; continue;
520 // Otherwise this is another use or second copy use.
521 CopyUseMI = nullptr; break;
524 MachineInstr *NewMI =
525 BuildMI(*MF, CopyUseMI->getDebugLoc(),
526 TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
527 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
528 MachineBasicBlock::iterator Pos = CopyUseMI;
529 EntryMBB->insertAfter(Pos, NewMI);
534 // Determine if there are any calls in this machine function.
535 MachineFrameInfo *MFI = MF->getFrameInfo();
536 for (const auto &MBB : *MF) {
537 if (MFI->hasCalls() && MF->hasInlineAsm())
540 for (const auto &MI : MBB) {
541 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
542 if ((MCID.isCall() && !MCID.isReturn()) ||
543 MI.isStackAligningInlineAsm()) {
544 MFI->setHasCalls(true);
546 if (MI.isInlineAsm()) {
547 MF->setHasInlineAsm(true);
552 // Determine if there is a call to setjmp in the machine function.
553 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
555 // Replace forward-declared registers with the registers containing
556 // the desired value.
557 MachineRegisterInfo &MRI = MF->getRegInfo();
558 for (DenseMap<unsigned, unsigned>::iterator
559 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
561 unsigned From = I->first;
562 unsigned To = I->second;
563 // If To is also scheduled to be replaced, find what its ultimate
566 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
570 // Make sure the new register has a sufficiently constrained register class.
571 if (TargetRegisterInfo::isVirtualRegister(From) &&
572 TargetRegisterInfo::isVirtualRegister(To))
573 MRI.constrainRegClass(To, MRI.getRegClass(From));
575 MRI.replaceRegWith(From, To);
578 // Freeze the set of reserved registers now that MachineFrameInfo has been
579 // set up. All the information required by getReservedRegs() should be
581 MRI.freezeReservedRegs(*MF);
583 // Release function-specific state. SDB and CurDAG are already cleared
587 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
588 DEBUG(MF->print(dbgs()));
593 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
594 BasicBlock::const_iterator End,
596 // Lower all of the non-terminator instructions. If a call is emitted
597 // as a tail call, cease emitting nodes for this block. Terminators
598 // are handled below.
599 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
602 // Make sure the root of the DAG is up-to-date.
603 CurDAG->setRoot(SDB->getControlRoot());
604 HadTailCall = SDB->HasTailCall;
607 // Final step, emit the lowered DAG as machine code.
611 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
612 SmallPtrSet<SDNode*, 128> VisitedNodes;
613 SmallVector<SDNode*, 128> Worklist;
615 Worklist.push_back(CurDAG->getRoot().getNode());
621 SDNode *N = Worklist.pop_back_val();
623 // If we've already seen this node, ignore it.
624 if (!VisitedNodes.insert(N).second)
627 // Otherwise, add all chain operands to the worklist.
628 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
629 if (N->getOperand(i).getValueType() == MVT::Other)
630 Worklist.push_back(N->getOperand(i).getNode());
632 // If this is a CopyToReg with a vreg dest, process it.
633 if (N->getOpcode() != ISD::CopyToReg)
636 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
637 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
640 // Ignore non-scalar or non-integer values.
641 SDValue Src = N->getOperand(2);
642 EVT SrcVT = Src.getValueType();
643 if (!SrcVT.isInteger() || SrcVT.isVector())
646 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
647 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
648 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
649 } while (!Worklist.empty());
652 void SelectionDAGISel::CodeGenAndEmitDAG() {
653 std::string GroupName;
654 if (TimePassesIsEnabled)
655 GroupName = "Instruction Selection and Scheduling";
656 std::string BlockName;
657 int BlockNumber = -1;
659 bool MatchFilterBB = false; (void)MatchFilterBB;
661 MatchFilterBB = (!FilterDAGBasicBlockName.empty() &&
662 FilterDAGBasicBlockName ==
663 FuncInfo->MBB->getBasicBlock()->getName().str());
666 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
667 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
671 BlockNumber = FuncInfo->MBB->getNumber();
672 BlockName = MF->getName().str() + ":" +
673 FuncInfo->MBB->getBasicBlock()->getName().str();
675 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
676 << " '" << BlockName << "'\n"; CurDAG->dump());
678 if (ViewDAGCombine1 && MatchFilterBB)
679 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
681 // Run the DAG combiner in pre-legalize mode.
683 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
684 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
687 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
688 << " '" << BlockName << "'\n"; CurDAG->dump());
690 // Second step, hack on the DAG until it only uses operations and types that
691 // the target supports.
692 if (ViewLegalizeTypesDAGs && MatchFilterBB)
693 CurDAG->viewGraph("legalize-types input for " + BlockName);
697 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
698 Changed = CurDAG->LegalizeTypes();
701 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
702 << " '" << BlockName << "'\n"; CurDAG->dump());
704 CurDAG->NewNodesMustHaveLegalTypes = true;
707 if (ViewDAGCombineLT && MatchFilterBB)
708 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
710 // Run the DAG combiner in post-type-legalize mode.
712 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
713 TimePassesIsEnabled);
714 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
717 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
718 << " '" << BlockName << "'\n"; CurDAG->dump());
723 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
724 Changed = CurDAG->LegalizeVectors();
729 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
730 CurDAG->LegalizeTypes();
733 if (ViewDAGCombineLT && MatchFilterBB)
734 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
736 // Run the DAG combiner in post-type-legalize mode.
738 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
739 TimePassesIsEnabled);
740 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
743 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
744 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
747 if (ViewLegalizeDAGs && MatchFilterBB)
748 CurDAG->viewGraph("legalize input for " + BlockName);
751 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
755 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
756 << " '" << BlockName << "'\n"; CurDAG->dump());
758 if (ViewDAGCombine2 && MatchFilterBB)
759 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
761 // Run the DAG combiner in post-legalize mode.
763 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
764 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
767 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
768 << " '" << BlockName << "'\n"; CurDAG->dump());
770 if (OptLevel != CodeGenOpt::None)
771 ComputeLiveOutVRegInfo();
773 if (ViewISelDAGs && MatchFilterBB)
774 CurDAG->viewGraph("isel input for " + BlockName);
776 // Third, instruction select all of the operations to machine code, adding the
777 // code to the MachineBasicBlock.
779 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
780 DoInstructionSelection();
783 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
784 << " '" << BlockName << "'\n"; CurDAG->dump());
786 if (ViewSchedDAGs && MatchFilterBB)
787 CurDAG->viewGraph("scheduler input for " + BlockName);
789 // Schedule machine code.
790 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
792 NamedRegionTimer T("Instruction Scheduling", GroupName,
793 TimePassesIsEnabled);
794 Scheduler->Run(CurDAG, FuncInfo->MBB);
797 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
799 // Emit machine code to BB. This can change 'BB' to the last block being
801 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
803 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
805 // FuncInfo->InsertPt is passed by reference and set to the end of the
806 // scheduled instructions.
807 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
810 // If the block was split, make sure we update any references that are used to
811 // update PHI nodes later on.
812 if (FirstMBB != LastMBB)
813 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
815 // Free the scheduler state.
817 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
818 TimePassesIsEnabled);
822 // Free the SelectionDAG state, now that we're finished with it.
827 /// ISelUpdater - helper class to handle updates of the instruction selection
829 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
830 SelectionDAG::allnodes_iterator &ISelPosition;
832 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
833 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
835 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
836 /// deleted is the current ISelPosition node, update ISelPosition.
838 void NodeDeleted(SDNode *N, SDNode *E) override {
839 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
843 } // end anonymous namespace
845 void SelectionDAGISel::DoInstructionSelection() {
846 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
847 << FuncInfo->MBB->getNumber()
848 << " '" << FuncInfo->MBB->getName() << "'\n");
852 // Select target instructions for the DAG.
854 // Number all nodes with a topological order and set DAGSize.
855 DAGSize = CurDAG->AssignTopologicalOrder();
857 // Create a dummy node (which is not added to allnodes), that adds
858 // a reference to the root node, preventing it from being deleted,
859 // and tracking any changes of the root.
860 HandleSDNode Dummy(CurDAG->getRoot());
861 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
864 // Make sure that ISelPosition gets properly updated when nodes are deleted
865 // in calls made from this function.
866 ISelUpdater ISU(*CurDAG, ISelPosition);
868 // The AllNodes list is now topological-sorted. Visit the
869 // nodes by starting at the end of the list (the root of the
870 // graph) and preceding back toward the beginning (the entry
872 while (ISelPosition != CurDAG->allnodes_begin()) {
873 SDNode *Node = --ISelPosition;
874 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
875 // but there are currently some corner cases that it misses. Also, this
876 // makes it theoretically possible to disable the DAGCombiner.
877 if (Node->use_empty())
880 SDNode *ResNode = Select(Node);
882 // FIXME: This is pretty gross. 'Select' should be changed to not return
883 // anything at all and this code should be nuked with a tactical strike.
885 // If node should not be replaced, continue with the next one.
886 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
890 ReplaceUses(Node, ResNode);
893 // If after the replacement this node is not used any more,
894 // remove this dead node.
895 if (Node->use_empty()) // Don't delete EntryToken, etc.
896 CurDAG->RemoveDeadNode(Node);
899 CurDAG->setRoot(Dummy.getValue());
902 DEBUG(dbgs() << "===== Instruction selection ends:\n");
904 PostprocessISelDAG();
907 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
908 /// do other setup for EH landing-pad blocks.
909 void SelectionDAGISel::PrepareEHLandingPad() {
910 MachineBasicBlock *MBB = FuncInfo->MBB;
912 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
914 // Add a label to mark the beginning of the landing pad. Deletion of the
915 // landing pad can thus be detected via the MachineModuleInfo.
916 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
918 // Assign the call site to the landing pad's begin label.
919 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
921 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
922 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
925 if (TM.getMCAsmInfo()->getExceptionHandlingType() ==
926 ExceptionHandling::MSVC) {
927 // Make virtual registers and a series of labels that fill in values for the
929 auto &RI = MF->getRegInfo();
930 FuncInfo->ExceptionSelectorVirtReg = RI.createVirtualRegister(PtrRC);
932 // Get all invoke BBs that will unwind into the clause BBs.
933 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
936 // Emit separate machine basic blocks with separate labels for each clause
937 // before the main landing pad block.
938 const BasicBlock *LLVMBB = MBB->getBasicBlock();
939 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
940 MachineInstrBuilder SelectorPHI = BuildMI(
941 *MBB, MBB->begin(), SDB->getCurDebugLoc(), TII->get(TargetOpcode::PHI),
942 FuncInfo->ExceptionSelectorVirtReg);
943 for (unsigned I = 0, E = LPadInst->getNumClauses(); I != E; ++I) {
944 MachineBasicBlock *ClauseBB = MF->CreateMachineBasicBlock(LLVMBB);
945 MF->insert(MBB, ClauseBB);
947 // Add the edge from the invoke to the clause.
948 for (MachineBasicBlock *InvokeBB : InvokeBBs)
949 InvokeBB->addSuccessor(ClauseBB);
951 // Mark the clause as a landing pad or MI passes will delete it.
952 ClauseBB->setIsLandingPad();
954 GlobalValue *ClauseGV = ExtractTypeInfo(LPadInst->getClause(I));
956 // Start the BB with a label.
957 MCSymbol *ClauseLabel = MF->getMMI().addClauseForLandingPad(MBB);
958 BuildMI(*ClauseBB, ClauseBB->begin(), SDB->getCurDebugLoc(), II)
959 .addSym(ClauseLabel);
961 // Construct a simple BB that defines a register with the typeid constant.
962 FuncInfo->MBB = ClauseBB;
963 FuncInfo->InsertPt = ClauseBB->end();
964 unsigned VReg = SDB->visitLandingPadClauseBB(ClauseGV, MBB);
965 CurDAG->setRoot(SDB->getRoot());
969 // Add the typeid virtual register to the phi in the main landing pad.
970 SelectorPHI.addReg(VReg).addMBB(ClauseBB);
973 // Remove the edge from the invoke to the lpad.
974 for (MachineBasicBlock *InvokeBB : InvokeBBs)
975 InvokeBB->removeSuccessor(MBB);
977 // Restore FuncInfo back to its previous state and select the main landing
980 FuncInfo->InsertPt = MBB->end();
984 // Mark exception register as live in.
985 if (unsigned Reg = TLI->getExceptionPointerRegister())
986 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
988 // Mark exception selector register as live in.
989 if (unsigned Reg = TLI->getExceptionSelectorRegister())
990 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
993 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
994 /// side-effect free and is either dead or folded into a generated instruction.
995 /// Return false if it needs to be emitted.
996 static bool isFoldedOrDeadInstruction(const Instruction *I,
997 FunctionLoweringInfo *FuncInfo) {
998 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
999 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1000 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1001 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
1002 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1006 // Collect per Instruction statistics for fast-isel misses. Only those
1007 // instructions that cause the bail are accounted for. It does not account for
1008 // instructions higher in the block. Thus, summing the per instructions stats
1009 // will not add up to what is reported by NumFastIselFailures.
1010 static void collectFailStats(const Instruction *I) {
1011 switch (I->getOpcode()) {
1012 default: assert (0 && "<Invalid operator> ");
1015 case Instruction::Ret: NumFastIselFailRet++; return;
1016 case Instruction::Br: NumFastIselFailBr++; return;
1017 case Instruction::Switch: NumFastIselFailSwitch++; return;
1018 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1019 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1020 case Instruction::Resume: NumFastIselFailResume++; return;
1021 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1023 // Standard binary operators...
1024 case Instruction::Add: NumFastIselFailAdd++; return;
1025 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1026 case Instruction::Sub: NumFastIselFailSub++; return;
1027 case Instruction::FSub: NumFastIselFailFSub++; return;
1028 case Instruction::Mul: NumFastIselFailMul++; return;
1029 case Instruction::FMul: NumFastIselFailFMul++; return;
1030 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1031 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1032 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1033 case Instruction::URem: NumFastIselFailURem++; return;
1034 case Instruction::SRem: NumFastIselFailSRem++; return;
1035 case Instruction::FRem: NumFastIselFailFRem++; return;
1037 // Logical operators...
1038 case Instruction::And: NumFastIselFailAnd++; return;
1039 case Instruction::Or: NumFastIselFailOr++; return;
1040 case Instruction::Xor: NumFastIselFailXor++; return;
1042 // Memory instructions...
1043 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1044 case Instruction::Load: NumFastIselFailLoad++; return;
1045 case Instruction::Store: NumFastIselFailStore++; return;
1046 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1047 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1048 case Instruction::Fence: NumFastIselFailFence++; return;
1049 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1051 // Convert instructions...
1052 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1053 case Instruction::ZExt: NumFastIselFailZExt++; return;
1054 case Instruction::SExt: NumFastIselFailSExt++; return;
1055 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1056 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1057 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1058 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1059 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1060 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1061 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1062 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1063 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1065 // Other instructions...
1066 case Instruction::ICmp: NumFastIselFailICmp++; return;
1067 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1068 case Instruction::PHI: NumFastIselFailPHI++; return;
1069 case Instruction::Select: NumFastIselFailSelect++; return;
1070 case Instruction::Call: {
1071 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1072 switch (Intrinsic->getIntrinsicID()) {
1074 NumFastIselFailIntrinsicCall++; return;
1075 case Intrinsic::sadd_with_overflow:
1076 NumFastIselFailSAddWithOverflow++; return;
1077 case Intrinsic::uadd_with_overflow:
1078 NumFastIselFailUAddWithOverflow++; return;
1079 case Intrinsic::ssub_with_overflow:
1080 NumFastIselFailSSubWithOverflow++; return;
1081 case Intrinsic::usub_with_overflow:
1082 NumFastIselFailUSubWithOverflow++; return;
1083 case Intrinsic::smul_with_overflow:
1084 NumFastIselFailSMulWithOverflow++; return;
1085 case Intrinsic::umul_with_overflow:
1086 NumFastIselFailUMulWithOverflow++; return;
1087 case Intrinsic::frameaddress:
1088 NumFastIselFailFrameaddress++; return;
1089 case Intrinsic::sqrt:
1090 NumFastIselFailSqrt++; return;
1091 case Intrinsic::experimental_stackmap:
1092 NumFastIselFailStackMap++; return;
1093 case Intrinsic::experimental_patchpoint_void: // fall-through
1094 case Intrinsic::experimental_patchpoint_i64:
1095 NumFastIselFailPatchPoint++; return;
1098 NumFastIselFailCall++;
1101 case Instruction::Shl: NumFastIselFailShl++; return;
1102 case Instruction::LShr: NumFastIselFailLShr++; return;
1103 case Instruction::AShr: NumFastIselFailAShr++; return;
1104 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1105 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1106 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1107 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1108 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1109 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1110 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1115 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1116 // Initialize the Fast-ISel state, if needed.
1117 FastISel *FastIS = nullptr;
1118 if (TM.Options.EnableFastISel)
1119 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1121 // Iterate over all basic blocks in the function.
1122 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1123 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1124 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1125 const BasicBlock *LLVMBB = *I;
1127 if (OptLevel != CodeGenOpt::None) {
1128 bool AllPredsVisited = true;
1129 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1131 if (!FuncInfo->VisitedBBs.count(*PI)) {
1132 AllPredsVisited = false;
1137 if (AllPredsVisited) {
1138 for (BasicBlock::const_iterator I = LLVMBB->begin();
1139 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1140 FuncInfo->ComputePHILiveOutRegInfo(PN);
1142 for (BasicBlock::const_iterator I = LLVMBB->begin();
1143 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1144 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1147 FuncInfo->VisitedBBs.insert(LLVMBB);
1150 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1151 BasicBlock::const_iterator const End = LLVMBB->end();
1152 BasicBlock::const_iterator BI = End;
1154 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1155 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1157 // Setup an EH landing-pad block.
1158 FuncInfo->ExceptionPointerVirtReg = 0;
1159 FuncInfo->ExceptionSelectorVirtReg = 0;
1160 if (FuncInfo->MBB->isLandingPad())
1161 PrepareEHLandingPad();
1163 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1165 FastIS->startNewBlock();
1167 // Emit code for any incoming arguments. This must happen before
1168 // beginning FastISel on the entry block.
1169 if (LLVMBB == &Fn.getEntryBlock()) {
1172 // Lower any arguments needed in this block if this is the entry block.
1173 if (!FastIS->lowerArguments()) {
1174 // Fast isel failed to lower these arguments
1175 ++NumFastIselFailLowerArguments;
1176 if (EnableFastISelAbortArgs)
1177 llvm_unreachable("FastISel didn't lower all arguments");
1179 // Use SelectionDAG argument lowering
1181 CurDAG->setRoot(SDB->getControlRoot());
1183 CodeGenAndEmitDAG();
1186 // If we inserted any instructions at the beginning, make a note of
1187 // where they are, so we can be sure to emit subsequent instructions
1189 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1190 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1192 FastIS->setLastLocalValue(nullptr);
1195 unsigned NumFastIselRemaining = std::distance(Begin, End);
1196 // Do FastISel on as many instructions as possible.
1197 for (; BI != Begin; --BI) {
1198 const Instruction *Inst = std::prev(BI);
1200 // If we no longer require this instruction, skip it.
1201 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1202 --NumFastIselRemaining;
1206 // Bottom-up: reset the insert pos at the top, after any local-value
1208 FastIS->recomputeInsertPt();
1210 // Try to select the instruction with FastISel.
1211 if (FastIS->selectInstruction(Inst)) {
1212 --NumFastIselRemaining;
1213 ++NumFastIselSuccess;
1214 // If fast isel succeeded, skip over all the folded instructions, and
1215 // then see if there is a load right before the selected instructions.
1216 // Try to fold the load if so.
1217 const Instruction *BeforeInst = Inst;
1218 while (BeforeInst != Begin) {
1219 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1220 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1223 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1224 BeforeInst->hasOneUse() &&
1225 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1226 // If we succeeded, don't re-select the load.
1227 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1228 --NumFastIselRemaining;
1229 ++NumFastIselSuccess;
1235 if (EnableFastISelVerbose2)
1236 collectFailStats(Inst);
1239 // Then handle certain instructions as single-LLVM-Instruction blocks.
1240 if (isa<CallInst>(Inst)) {
1242 if (EnableFastISelVerbose || EnableFastISelAbort) {
1243 dbgs() << "FastISel missed call: ";
1247 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1248 unsigned &R = FuncInfo->ValueMap[Inst];
1250 R = FuncInfo->CreateRegs(Inst->getType());
1253 bool HadTailCall = false;
1254 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1255 SelectBasicBlock(Inst, BI, HadTailCall);
1257 // If the call was emitted as a tail call, we're done with the block.
1258 // We also need to delete any previously emitted instructions.
1260 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1265 // Recompute NumFastIselRemaining as Selection DAG instruction
1266 // selection may have handled the call, input args, etc.
1267 unsigned RemainingNow = std::distance(Begin, BI);
1268 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1269 NumFastIselRemaining = RemainingNow;
1273 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1274 // Don't abort, and use a different message for terminator misses.
1275 NumFastIselFailures += NumFastIselRemaining;
1276 if (EnableFastISelVerbose || EnableFastISelAbort) {
1277 dbgs() << "FastISel missed terminator: ";
1281 NumFastIselFailures += NumFastIselRemaining;
1282 if (EnableFastISelVerbose || EnableFastISelAbort) {
1283 dbgs() << "FastISel miss: ";
1286 if (EnableFastISelAbort)
1287 // The "fast" selector couldn't handle something and bailed.
1288 // For the purpose of debugging, just abort.
1289 llvm_unreachable("FastISel didn't select the entire block");
1294 FastIS->recomputeInsertPt();
1296 // Lower any arguments needed in this block if this is the entry block.
1297 if (LLVMBB == &Fn.getEntryBlock()) {
1306 ++NumFastIselBlocks;
1309 // Run SelectionDAG instruction selection on the remainder of the block
1310 // not handled by FastISel. If FastISel is not run, this is the entire
1313 SelectBasicBlock(Begin, BI, HadTailCall);
1317 FuncInfo->PHINodesToUpdate.clear();
1321 SDB->clearDanglingDebugInfo();
1322 SDB->SPDescriptor.resetPerFunctionState();
1325 /// Given that the input MI is before a partial terminator sequence TSeq, return
1326 /// true if M + TSeq also a partial terminator sequence.
1328 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1329 /// lowering copy vregs into physical registers, which are then passed into
1330 /// terminator instructors so we can satisfy ABI constraints. A partial
1331 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1332 /// may be the whole terminator sequence).
1333 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1334 // If we do not have a copy or an implicit def, we return true if and only if
1335 // MI is a debug value.
1336 if (!MI->isCopy() && !MI->isImplicitDef())
1337 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1338 // physical registers if there is debug info associated with the terminator
1339 // of our mbb. We want to include said debug info in our terminator
1340 // sequence, so we return true in that case.
1341 return MI->isDebugValue();
1343 // We have left the terminator sequence if we are not doing one of the
1346 // 1. Copying a vreg into a physical register.
1347 // 2. Copying a vreg into a vreg.
1348 // 3. Defining a register via an implicit def.
1350 // OPI should always be a register definition...
1351 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1352 if (!OPI->isReg() || !OPI->isDef())
1355 // Defining any register via an implicit def is always ok.
1356 if (MI->isImplicitDef())
1359 // Grab the copy source...
1360 MachineInstr::const_mop_iterator OPI2 = OPI;
1362 assert(OPI2 != MI->operands_end()
1363 && "Should have a copy implying we should have 2 arguments.");
1365 // Make sure that the copy dest is not a vreg when the copy source is a
1366 // physical register.
1367 if (!OPI2->isReg() ||
1368 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1369 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1375 /// Find the split point at which to splice the end of BB into its success stack
1376 /// protector check machine basic block.
1378 /// On many platforms, due to ABI constraints, terminators, even before register
1379 /// allocation, use physical registers. This creates an issue for us since
1380 /// physical registers at this point can not travel across basic
1381 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1382 /// when they enter functions and moves them through a sequence of copies back
1383 /// into the physical registers right before the terminator creating a
1384 /// ``Terminator Sequence''. This function is searching for the beginning of the
1385 /// terminator sequence so that we can ensure that we splice off not just the
1386 /// terminator, but additionally the copies that move the vregs into the
1387 /// physical registers.
1388 static MachineBasicBlock::iterator
1389 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1390 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1392 if (SplitPoint == BB->begin())
1395 MachineBasicBlock::iterator Start = BB->begin();
1396 MachineBasicBlock::iterator Previous = SplitPoint;
1399 while (MIIsInTerminatorSequence(Previous)) {
1400 SplitPoint = Previous;
1401 if (Previous == Start)
1410 SelectionDAGISel::FinishBasicBlock() {
1412 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1413 << FuncInfo->PHINodesToUpdate.size() << "\n";
1414 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1415 dbgs() << "Node " << i << " : ("
1416 << FuncInfo->PHINodesToUpdate[i].first
1417 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1419 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1420 SDB->JTCases.empty() &&
1421 SDB->BitTestCases.empty();
1423 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1424 // PHI nodes in successors.
1425 if (MustUpdatePHINodes) {
1426 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1427 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1428 assert(PHI->isPHI() &&
1429 "This is not a machine PHI node that we are updating!");
1430 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1432 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1436 // Handle stack protector.
1437 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1438 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1439 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1441 // Find the split point to split the parent mbb. At the same time copy all
1442 // physical registers used in the tail of parent mbb into virtual registers
1443 // before the split point and back into physical registers after the split
1444 // point. This prevents us needing to deal with Live-ins and many other
1445 // register allocation issues caused by us splitting the parent mbb. The
1446 // register allocator will clean up said virtual copies later on.
1447 MachineBasicBlock::iterator SplitPoint =
1448 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1450 // Splice the terminator of ParentMBB into SuccessMBB.
1451 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1455 // Add compare/jump on neq/jump to the parent BB.
1456 FuncInfo->MBB = ParentMBB;
1457 FuncInfo->InsertPt = ParentMBB->end();
1458 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1459 CurDAG->setRoot(SDB->getRoot());
1461 CodeGenAndEmitDAG();
1463 // CodeGen Failure MBB if we have not codegened it yet.
1464 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1465 if (!FailureMBB->size()) {
1466 FuncInfo->MBB = FailureMBB;
1467 FuncInfo->InsertPt = FailureMBB->end();
1468 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1469 CurDAG->setRoot(SDB->getRoot());
1471 CodeGenAndEmitDAG();
1474 // Clear the Per-BB State.
1475 SDB->SPDescriptor.resetPerBBState();
1478 // If we updated PHI Nodes, return early.
1479 if (MustUpdatePHINodes)
1482 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1483 // Lower header first, if it wasn't already lowered
1484 if (!SDB->BitTestCases[i].Emitted) {
1485 // Set the current basic block to the mbb we wish to insert the code into
1486 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1487 FuncInfo->InsertPt = FuncInfo->MBB->end();
1489 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1490 CurDAG->setRoot(SDB->getRoot());
1492 CodeGenAndEmitDAG();
1495 uint32_t UnhandledWeight = 0;
1496 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1497 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1499 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1500 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1501 // Set the current basic block to the mbb we wish to insert the code into
1502 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1503 FuncInfo->InsertPt = FuncInfo->MBB->end();
1506 SDB->visitBitTestCase(SDB->BitTestCases[i],
1507 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1509 SDB->BitTestCases[i].Reg,
1510 SDB->BitTestCases[i].Cases[j],
1513 SDB->visitBitTestCase(SDB->BitTestCases[i],
1514 SDB->BitTestCases[i].Default,
1516 SDB->BitTestCases[i].Reg,
1517 SDB->BitTestCases[i].Cases[j],
1521 CurDAG->setRoot(SDB->getRoot());
1523 CodeGenAndEmitDAG();
1527 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1529 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1530 MachineBasicBlock *PHIBB = PHI->getParent();
1531 assert(PHI->isPHI() &&
1532 "This is not a machine PHI node that we are updating!");
1533 // This is "default" BB. We have two jumps to it. From "header" BB and
1534 // from last "case" BB.
1535 if (PHIBB == SDB->BitTestCases[i].Default)
1536 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1537 .addMBB(SDB->BitTestCases[i].Parent)
1538 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1539 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1540 // One of "cases" BB.
1541 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1543 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1544 if (cBB->isSuccessor(PHIBB))
1545 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1549 SDB->BitTestCases.clear();
1551 // If the JumpTable record is filled in, then we need to emit a jump table.
1552 // Updating the PHI nodes is tricky in this case, since we need to determine
1553 // whether the PHI is a successor of the range check MBB or the jump table MBB
1554 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1555 // Lower header first, if it wasn't already lowered
1556 if (!SDB->JTCases[i].first.Emitted) {
1557 // Set the current basic block to the mbb we wish to insert the code into
1558 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1559 FuncInfo->InsertPt = FuncInfo->MBB->end();
1561 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1563 CurDAG->setRoot(SDB->getRoot());
1565 CodeGenAndEmitDAG();
1568 // Set the current basic block to the mbb we wish to insert the code into
1569 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1570 FuncInfo->InsertPt = FuncInfo->MBB->end();
1572 SDB->visitJumpTable(SDB->JTCases[i].second);
1573 CurDAG->setRoot(SDB->getRoot());
1575 CodeGenAndEmitDAG();
1578 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1580 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1581 MachineBasicBlock *PHIBB = PHI->getParent();
1582 assert(PHI->isPHI() &&
1583 "This is not a machine PHI node that we are updating!");
1584 // "default" BB. We can go there only from header BB.
1585 if (PHIBB == SDB->JTCases[i].second.Default)
1586 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1587 .addMBB(SDB->JTCases[i].first.HeaderBB);
1588 // JT BB. Just iterate over successors here
1589 if (FuncInfo->MBB->isSuccessor(PHIBB))
1590 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1593 SDB->JTCases.clear();
1595 // If the switch block involved a branch to one of the actual successors, we
1596 // need to update PHI nodes in that block.
1597 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1598 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1599 assert(PHI->isPHI() &&
1600 "This is not a machine PHI node that we are updating!");
1601 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1602 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1605 // If we generated any switch lowering information, build and codegen any
1606 // additional DAGs necessary.
1607 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1608 // Set the current basic block to the mbb we wish to insert the code into
1609 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1610 FuncInfo->InsertPt = FuncInfo->MBB->end();
1612 // Determine the unique successors.
1613 SmallVector<MachineBasicBlock *, 2> Succs;
1614 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1615 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1616 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1618 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1619 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1620 CurDAG->setRoot(SDB->getRoot());
1622 CodeGenAndEmitDAG();
1624 // Remember the last block, now that any splitting is done, for use in
1625 // populating PHI nodes in successors.
1626 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1628 // Handle any PHI nodes in successors of this chunk, as if we were coming
1629 // from the original BB before switch expansion. Note that PHI nodes can
1630 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1631 // handle them the right number of times.
1632 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1633 FuncInfo->MBB = Succs[i];
1634 FuncInfo->InsertPt = FuncInfo->MBB->end();
1635 // FuncInfo->MBB may have been removed from the CFG if a branch was
1637 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1638 for (MachineBasicBlock::iterator
1639 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1640 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1641 MachineInstrBuilder PHI(*MF, MBBI);
1642 // This value for this PHI node is recorded in PHINodesToUpdate.
1643 for (unsigned pn = 0; ; ++pn) {
1644 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1645 "Didn't find PHI entry!");
1646 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1647 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1655 SDB->SwitchCases.clear();
1659 /// Create the scheduler. If a specific scheduler was specified
1660 /// via the SchedulerRegistry, use it, otherwise select the
1661 /// one preferred by the target.
1663 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1664 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1668 RegisterScheduler::setDefault(Ctor);
1671 return Ctor(this, OptLevel);
1674 //===----------------------------------------------------------------------===//
1675 // Helper functions used by the generated instruction selector.
1676 //===----------------------------------------------------------------------===//
1677 // Calls to these methods are generated by tblgen.
1679 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1680 /// the dag combiner simplified the 255, we still want to match. RHS is the
1681 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1682 /// specified in the .td file (e.g. 255).
1683 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1684 int64_t DesiredMaskS) const {
1685 const APInt &ActualMask = RHS->getAPIntValue();
1686 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1688 // If the actual mask exactly matches, success!
1689 if (ActualMask == DesiredMask)
1692 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1693 if (ActualMask.intersects(~DesiredMask))
1696 // Otherwise, the DAG Combiner may have proven that the value coming in is
1697 // either already zero or is not demanded. Check for known zero input bits.
1698 APInt NeededMask = DesiredMask & ~ActualMask;
1699 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1702 // TODO: check to see if missing bits are just not demanded.
1704 // Otherwise, this pattern doesn't match.
1708 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1709 /// the dag combiner simplified the 255, we still want to match. RHS is the
1710 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1711 /// specified in the .td file (e.g. 255).
1712 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1713 int64_t DesiredMaskS) const {
1714 const APInt &ActualMask = RHS->getAPIntValue();
1715 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1717 // If the actual mask exactly matches, success!
1718 if (ActualMask == DesiredMask)
1721 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1722 if (ActualMask.intersects(~DesiredMask))
1725 // Otherwise, the DAG Combiner may have proven that the value coming in is
1726 // either already zero or is not demanded. Check for known zero input bits.
1727 APInt NeededMask = DesiredMask & ~ActualMask;
1729 APInt KnownZero, KnownOne;
1730 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1732 // If all the missing bits in the or are already known to be set, match!
1733 if ((NeededMask & KnownOne) == NeededMask)
1736 // TODO: check to see if missing bits are just not demanded.
1738 // Otherwise, this pattern doesn't match.
1743 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1744 /// by tblgen. Others should not call it.
1745 void SelectionDAGISel::
1746 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1747 std::vector<SDValue> InOps;
1748 std::swap(InOps, Ops);
1750 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1751 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1752 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1753 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1755 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1756 if (InOps[e-1].getValueType() == MVT::Glue)
1757 --e; // Don't process a glue operand if it is here.
1760 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1761 if (!InlineAsm::isMemKind(Flags)) {
1762 // Just skip over this operand, copying the operands verbatim.
1763 Ops.insert(Ops.end(), InOps.begin()+i,
1764 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1765 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1767 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1768 "Memory operand with multiple values?");
1769 // Otherwise, this is a memory operand. Ask the target to select it.
1770 std::vector<SDValue> SelOps;
1771 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1772 report_fatal_error("Could not match memory address. Inline asm"
1775 // Add this to the output node.
1777 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1778 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1779 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1784 // Add the glue input back if present.
1785 if (e != InOps.size())
1786 Ops.push_back(InOps.back());
1789 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1792 static SDNode *findGlueUse(SDNode *N) {
1793 unsigned FlagResNo = N->getNumValues()-1;
1794 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1795 SDUse &Use = I.getUse();
1796 if (Use.getResNo() == FlagResNo)
1797 return Use.getUser();
1802 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1803 /// This function recursively traverses up the operand chain, ignoring
1805 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1806 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1807 bool IgnoreChains) {
1808 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1809 // greater than all of its (recursive) operands. If we scan to a point where
1810 // 'use' is smaller than the node we're scanning for, then we know we will
1813 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1814 // happen because we scan down to newly selected nodes in the case of glue
1816 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1819 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1820 // won't fail if we scan it again.
1821 if (!Visited.insert(Use).second)
1824 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1825 // Ignore chain uses, they are validated by HandleMergeInputChains.
1826 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1829 SDNode *N = Use->getOperand(i).getNode();
1831 if (Use == ImmedUse || Use == Root)
1832 continue; // We are not looking for immediate use.
1837 // Traverse up the operand chain.
1838 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1844 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1845 /// operand node N of U during instruction selection that starts at Root.
1846 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1847 SDNode *Root) const {
1848 if (OptLevel == CodeGenOpt::None) return false;
1849 return N.hasOneUse();
1852 /// IsLegalToFold - Returns true if the specific operand node N of
1853 /// U can be folded during instruction selection that starts at Root.
1854 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1855 CodeGenOpt::Level OptLevel,
1856 bool IgnoreChains) {
1857 if (OptLevel == CodeGenOpt::None) return false;
1859 // If Root use can somehow reach N through a path that that doesn't contain
1860 // U then folding N would create a cycle. e.g. In the following
1861 // diagram, Root can reach N through X. If N is folded into into Root, then
1862 // X is both a predecessor and a successor of U.
1873 // * indicates nodes to be folded together.
1875 // If Root produces glue, then it gets (even more) interesting. Since it
1876 // will be "glued" together with its glue use in the scheduler, we need to
1877 // check if it might reach N.
1896 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1897 // (call it Fold), then X is a predecessor of GU and a successor of
1898 // Fold. But since Fold and GU are glued together, this will create
1899 // a cycle in the scheduling graph.
1901 // If the node has glue, walk down the graph to the "lowest" node in the
1903 EVT VT = Root->getValueType(Root->getNumValues()-1);
1904 while (VT == MVT::Glue) {
1905 SDNode *GU = findGlueUse(Root);
1909 VT = Root->getValueType(Root->getNumValues()-1);
1911 // If our query node has a glue result with a use, we've walked up it. If
1912 // the user (which has already been selected) has a chain or indirectly uses
1913 // the chain, our WalkChainUsers predicate will not consider it. Because of
1914 // this, we cannot ignore chains in this predicate.
1915 IgnoreChains = false;
1919 SmallPtrSet<SDNode*, 16> Visited;
1920 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1923 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1924 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1925 SelectInlineAsmMemoryOperands(Ops);
1927 EVT VTs[] = { MVT::Other, MVT::Glue };
1928 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
1930 return New.getNode();
1934 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1936 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
1937 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1939 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
1940 SDValue New = CurDAG->getCopyFromReg(
1941 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
1943 return New.getNode();
1947 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1949 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1950 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1951 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1952 Op->getOperand(2).getValueType());
1953 SDValue New = CurDAG->getCopyToReg(
1954 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
1956 return New.getNode();
1961 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1962 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1965 /// GetVBR - decode a vbr encoding whose top bit is set.
1966 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1967 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1968 assert(Val >= 128 && "Not a VBR");
1969 Val &= 127; // Remove first vbr bit.
1974 NextBits = MatcherTable[Idx++];
1975 Val |= (NextBits&127) << Shift;
1977 } while (NextBits & 128);
1983 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1984 /// interior glue and chain results to use the new glue and chain results.
1985 void SelectionDAGISel::
1986 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1987 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1989 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1990 bool isMorphNodeTo) {
1991 SmallVector<SDNode*, 4> NowDeadNodes;
1993 // Now that all the normal results are replaced, we replace the chain and
1994 // glue results if present.
1995 if (!ChainNodesMatched.empty()) {
1996 assert(InputChain.getNode() &&
1997 "Matched input chains but didn't produce a chain");
1998 // Loop over all of the nodes we matched that produced a chain result.
1999 // Replace all the chain results with the final chain we ended up with.
2000 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2001 SDNode *ChainNode = ChainNodesMatched[i];
2003 // If this node was already deleted, don't look at it.
2004 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2007 // Don't replace the results of the root node if we're doing a
2009 if (ChainNode == NodeToMatch && isMorphNodeTo)
2012 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2013 if (ChainVal.getValueType() == MVT::Glue)
2014 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2015 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2016 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2018 // If the node became dead and we haven't already seen it, delete it.
2019 if (ChainNode->use_empty() &&
2020 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2021 NowDeadNodes.push_back(ChainNode);
2025 // If the result produces glue, update any glue results in the matched
2026 // pattern with the glue result.
2027 if (InputGlue.getNode()) {
2028 // Handle any interior nodes explicitly marked.
2029 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2030 SDNode *FRN = GlueResultNodesMatched[i];
2032 // If this node was already deleted, don't look at it.
2033 if (FRN->getOpcode() == ISD::DELETED_NODE)
2036 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2037 "Doesn't have a glue result");
2038 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2041 // If the node became dead and we haven't already seen it, delete it.
2042 if (FRN->use_empty() &&
2043 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2044 NowDeadNodes.push_back(FRN);
2048 if (!NowDeadNodes.empty())
2049 CurDAG->RemoveDeadNodes(NowDeadNodes);
2051 DEBUG(dbgs() << "ISEL: Match complete!\n");
2057 CR_LeadsToInteriorNode
2060 /// WalkChainUsers - Walk down the users of the specified chained node that is
2061 /// part of the pattern we're matching, looking at all of the users we find.
2062 /// This determines whether something is an interior node, whether we have a
2063 /// non-pattern node in between two pattern nodes (which prevent folding because
2064 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2065 /// between pattern nodes (in which case the TF becomes part of the pattern).
2067 /// The walk we do here is guaranteed to be small because we quickly get down to
2068 /// already selected nodes "below" us.
2070 WalkChainUsers(const SDNode *ChainedNode,
2071 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2072 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2073 ChainResult Result = CR_Simple;
2075 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2076 E = ChainedNode->use_end(); UI != E; ++UI) {
2077 // Make sure the use is of the chain, not some other value we produce.
2078 if (UI.getUse().getValueType() != MVT::Other) continue;
2082 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2085 // If we see an already-selected machine node, then we've gone beyond the
2086 // pattern that we're selecting down into the already selected chunk of the
2088 unsigned UserOpcode = User->getOpcode();
2089 if (User->isMachineOpcode() ||
2090 UserOpcode == ISD::CopyToReg ||
2091 UserOpcode == ISD::CopyFromReg ||
2092 UserOpcode == ISD::INLINEASM ||
2093 UserOpcode == ISD::EH_LABEL ||
2094 UserOpcode == ISD::LIFETIME_START ||
2095 UserOpcode == ISD::LIFETIME_END) {
2096 // If their node ID got reset to -1 then they've already been selected.
2097 // Treat them like a MachineOpcode.
2098 if (User->getNodeId() == -1)
2102 // If we have a TokenFactor, we handle it specially.
2103 if (User->getOpcode() != ISD::TokenFactor) {
2104 // If the node isn't a token factor and isn't part of our pattern, then it
2105 // must be a random chained node in between two nodes we're selecting.
2106 // This happens when we have something like:
2111 // Because we structurally match the load/store as a read/modify/write,
2112 // but the call is chained between them. We cannot fold in this case
2113 // because it would induce a cycle in the graph.
2114 if (!std::count(ChainedNodesInPattern.begin(),
2115 ChainedNodesInPattern.end(), User))
2116 return CR_InducesCycle;
2118 // Otherwise we found a node that is part of our pattern. For example in:
2122 // This would happen when we're scanning down from the load and see the
2123 // store as a user. Record that there is a use of ChainedNode that is
2124 // part of the pattern and keep scanning uses.
2125 Result = CR_LeadsToInteriorNode;
2126 InteriorChainedNodes.push_back(User);
2130 // If we found a TokenFactor, there are two cases to consider: first if the
2131 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2132 // uses of the TF are in our pattern) we just want to ignore it. Second,
2133 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2139 // | \ DAG's like cheese
2142 // [TokenFactor] [Op]
2149 // In this case, the TokenFactor becomes part of our match and we rewrite it
2150 // as a new TokenFactor.
2152 // To distinguish these two cases, do a recursive walk down the uses.
2153 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2155 // If the uses of the TokenFactor are just already-selected nodes, ignore
2156 // it, it is "below" our pattern.
2158 case CR_InducesCycle:
2159 // If the uses of the TokenFactor lead to nodes that are not part of our
2160 // pattern that are not selected, folding would turn this into a cycle,
2162 return CR_InducesCycle;
2163 case CR_LeadsToInteriorNode:
2164 break; // Otherwise, keep processing.
2167 // Okay, we know we're in the interesting interior case. The TokenFactor
2168 // is now going to be considered part of the pattern so that we rewrite its
2169 // uses (it may have uses that are not part of the pattern) with the
2170 // ultimate chain result of the generated code. We will also add its chain
2171 // inputs as inputs to the ultimate TokenFactor we create.
2172 Result = CR_LeadsToInteriorNode;
2173 ChainedNodesInPattern.push_back(User);
2174 InteriorChainedNodes.push_back(User);
2181 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2182 /// operation for when the pattern matched at least one node with a chains. The
2183 /// input vector contains a list of all of the chained nodes that we match. We
2184 /// must determine if this is a valid thing to cover (i.e. matching it won't
2185 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2186 /// be used as the input node chain for the generated nodes.
2188 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2189 SelectionDAG *CurDAG) {
2190 // Walk all of the chained nodes we've matched, recursively scanning down the
2191 // users of the chain result. This adds any TokenFactor nodes that are caught
2192 // in between chained nodes to the chained and interior nodes list.
2193 SmallVector<SDNode*, 3> InteriorChainedNodes;
2194 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2195 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2196 InteriorChainedNodes) == CR_InducesCycle)
2197 return SDValue(); // Would induce a cycle.
2200 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2201 // that we are interested in. Form our input TokenFactor node.
2202 SmallVector<SDValue, 3> InputChains;
2203 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2204 // Add the input chain of this node to the InputChains list (which will be
2205 // the operands of the generated TokenFactor) if it's not an interior node.
2206 SDNode *N = ChainNodesMatched[i];
2207 if (N->getOpcode() != ISD::TokenFactor) {
2208 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2211 // Otherwise, add the input chain.
2212 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2213 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2214 InputChains.push_back(InChain);
2218 // If we have a token factor, we want to add all inputs of the token factor
2219 // that are not part of the pattern we're matching.
2220 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2221 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2222 N->getOperand(op).getNode()))
2223 InputChains.push_back(N->getOperand(op));
2227 if (InputChains.size() == 1)
2228 return InputChains[0];
2229 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2230 MVT::Other, InputChains);
2233 /// MorphNode - Handle morphing a node in place for the selector.
2234 SDNode *SelectionDAGISel::
2235 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2236 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2237 // It is possible we're using MorphNodeTo to replace a node with no
2238 // normal results with one that has a normal result (or we could be
2239 // adding a chain) and the input could have glue and chains as well.
2240 // In this case we need to shift the operands down.
2241 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2242 // than the old isel though.
2243 int OldGlueResultNo = -1, OldChainResultNo = -1;
2245 unsigned NTMNumResults = Node->getNumValues();
2246 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2247 OldGlueResultNo = NTMNumResults-1;
2248 if (NTMNumResults != 1 &&
2249 Node->getValueType(NTMNumResults-2) == MVT::Other)
2250 OldChainResultNo = NTMNumResults-2;
2251 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2252 OldChainResultNo = NTMNumResults-1;
2254 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2255 // that this deletes operands of the old node that become dead.
2256 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2258 // MorphNodeTo can operate in two ways: if an existing node with the
2259 // specified operands exists, it can just return it. Otherwise, it
2260 // updates the node in place to have the requested operands.
2262 // If we updated the node in place, reset the node ID. To the isel,
2263 // this should be just like a newly allocated machine node.
2267 unsigned ResNumResults = Res->getNumValues();
2268 // Move the glue if needed.
2269 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2270 (unsigned)OldGlueResultNo != ResNumResults-1)
2271 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2272 SDValue(Res, ResNumResults-1));
2274 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2277 // Move the chain reference if needed.
2278 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2279 (unsigned)OldChainResultNo != ResNumResults-1)
2280 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2281 SDValue(Res, ResNumResults-1));
2283 // Otherwise, no replacement happened because the node already exists. Replace
2284 // Uses of the old node with the new one.
2286 CurDAG->ReplaceAllUsesWith(Node, Res);
2291 /// CheckSame - Implements OP_CheckSame.
2292 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2293 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2295 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2296 // Accept if it is exactly the same as a previously recorded node.
2297 unsigned RecNo = MatcherTable[MatcherIndex++];
2298 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2299 return N == RecordedNodes[RecNo].first;
2302 /// CheckChildSame - Implements OP_CheckChildXSame.
2303 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2304 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2306 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2308 if (ChildNo >= N.getNumOperands())
2309 return false; // Match fails if out of range child #.
2310 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2314 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2315 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2316 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2317 const SelectionDAGISel &SDISel) {
2318 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2321 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2322 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2323 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2324 const SelectionDAGISel &SDISel, SDNode *N) {
2325 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2328 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2329 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2331 uint16_t Opc = MatcherTable[MatcherIndex++];
2332 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2333 return N->getOpcode() == Opc;
2336 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2337 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2338 SDValue N, const TargetLowering *TLI) {
2339 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2340 if (N.getValueType() == VT) return true;
2342 // Handle the case when VT is iPTR.
2343 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2346 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2347 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2348 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2349 if (ChildNo >= N.getNumOperands())
2350 return false; // Match fails if out of range child #.
2351 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2354 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2355 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2357 return cast<CondCodeSDNode>(N)->get() ==
2358 (ISD::CondCode)MatcherTable[MatcherIndex++];
2361 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2362 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2363 SDValue N, const TargetLowering *TLI) {
2364 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2365 if (cast<VTSDNode>(N)->getVT() == VT)
2368 // Handle the case when VT is iPTR.
2369 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2372 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2373 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2375 int64_t Val = MatcherTable[MatcherIndex++];
2377 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2379 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2380 return C && C->getSExtValue() == Val;
2383 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2384 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2385 SDValue N, unsigned ChildNo) {
2386 if (ChildNo >= N.getNumOperands())
2387 return false; // Match fails if out of range child #.
2388 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2391 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2392 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2393 SDValue N, const SelectionDAGISel &SDISel) {
2394 int64_t Val = MatcherTable[MatcherIndex++];
2396 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2398 if (N->getOpcode() != ISD::AND) return false;
2400 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2401 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2404 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2405 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2406 SDValue N, const SelectionDAGISel &SDISel) {
2407 int64_t Val = MatcherTable[MatcherIndex++];
2409 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2411 if (N->getOpcode() != ISD::OR) return false;
2413 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2414 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2417 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2418 /// scope, evaluate the current node. If the current predicate is known to
2419 /// fail, set Result=true and return anything. If the current predicate is
2420 /// known to pass, set Result=false and return the MatcherIndex to continue
2421 /// with. If the current predicate is unknown, set Result=false and return the
2422 /// MatcherIndex to continue with.
2423 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2424 unsigned Index, SDValue N,
2426 const SelectionDAGISel &SDISel,
2427 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2428 switch (Table[Index++]) {
2431 return Index-1; // Could not evaluate this predicate.
2432 case SelectionDAGISel::OPC_CheckSame:
2433 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2435 case SelectionDAGISel::OPC_CheckChild0Same:
2436 case SelectionDAGISel::OPC_CheckChild1Same:
2437 case SelectionDAGISel::OPC_CheckChild2Same:
2438 case SelectionDAGISel::OPC_CheckChild3Same:
2439 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2440 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2442 case SelectionDAGISel::OPC_CheckPatternPredicate:
2443 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2445 case SelectionDAGISel::OPC_CheckPredicate:
2446 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2448 case SelectionDAGISel::OPC_CheckOpcode:
2449 Result = !::CheckOpcode(Table, Index, N.getNode());
2451 case SelectionDAGISel::OPC_CheckType:
2452 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2454 case SelectionDAGISel::OPC_CheckChild0Type:
2455 case SelectionDAGISel::OPC_CheckChild1Type:
2456 case SelectionDAGISel::OPC_CheckChild2Type:
2457 case SelectionDAGISel::OPC_CheckChild3Type:
2458 case SelectionDAGISel::OPC_CheckChild4Type:
2459 case SelectionDAGISel::OPC_CheckChild5Type:
2460 case SelectionDAGISel::OPC_CheckChild6Type:
2461 case SelectionDAGISel::OPC_CheckChild7Type:
2462 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2464 SelectionDAGISel::OPC_CheckChild0Type);
2466 case SelectionDAGISel::OPC_CheckCondCode:
2467 Result = !::CheckCondCode(Table, Index, N);
2469 case SelectionDAGISel::OPC_CheckValueType:
2470 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2472 case SelectionDAGISel::OPC_CheckInteger:
2473 Result = !::CheckInteger(Table, Index, N);
2475 case SelectionDAGISel::OPC_CheckChild0Integer:
2476 case SelectionDAGISel::OPC_CheckChild1Integer:
2477 case SelectionDAGISel::OPC_CheckChild2Integer:
2478 case SelectionDAGISel::OPC_CheckChild3Integer:
2479 case SelectionDAGISel::OPC_CheckChild4Integer:
2480 Result = !::CheckChildInteger(Table, Index, N,
2481 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2483 case SelectionDAGISel::OPC_CheckAndImm:
2484 Result = !::CheckAndImm(Table, Index, N, SDISel);
2486 case SelectionDAGISel::OPC_CheckOrImm:
2487 Result = !::CheckOrImm(Table, Index, N, SDISel);
2495 /// FailIndex - If this match fails, this is the index to continue with.
2498 /// NodeStack - The node stack when the scope was formed.
2499 SmallVector<SDValue, 4> NodeStack;
2501 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2502 unsigned NumRecordedNodes;
2504 /// NumMatchedMemRefs - The number of matched memref entries.
2505 unsigned NumMatchedMemRefs;
2507 /// InputChain/InputGlue - The current chain/glue
2508 SDValue InputChain, InputGlue;
2510 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2511 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2514 /// \\brief A DAG update listener to keep the matching state
2515 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2516 /// change the DAG while matching. X86 addressing mode matcher is an example
2518 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2520 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2521 SmallVectorImpl<MatchScope> &MatchScopes;
2523 MatchStateUpdater(SelectionDAG &DAG,
2524 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2525 SmallVectorImpl<MatchScope> &MS) :
2526 SelectionDAG::DAGUpdateListener(DAG),
2527 RecordedNodes(RN), MatchScopes(MS) { }
2529 void NodeDeleted(SDNode *N, SDNode *E) {
2530 // Some early-returns here to avoid the search if we deleted the node or
2531 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2532 // do, so it's unnecessary to update matching state at that point).
2533 // Neither of these can occur currently because we only install this
2534 // update listener during matching a complex patterns.
2535 if (!E || E->isMachineOpcode())
2537 // Performing linear search here does not matter because we almost never
2538 // run this code. You'd have to have a CSE during complex pattern
2540 for (auto &I : RecordedNodes)
2541 if (I.first.getNode() == N)
2544 for (auto &I : MatchScopes)
2545 for (auto &J : I.NodeStack)
2546 if (J.getNode() == N)
2552 SDNode *SelectionDAGISel::
2553 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2554 unsigned TableSize) {
2555 // FIXME: Should these even be selected? Handle these cases in the caller?
2556 switch (NodeToMatch->getOpcode()) {
2559 case ISD::EntryToken: // These nodes remain the same.
2560 case ISD::BasicBlock:
2562 case ISD::RegisterMask:
2563 case ISD::HANDLENODE:
2564 case ISD::MDNODE_SDNODE:
2565 case ISD::TargetConstant:
2566 case ISD::TargetConstantFP:
2567 case ISD::TargetConstantPool:
2568 case ISD::TargetFrameIndex:
2569 case ISD::TargetExternalSymbol:
2570 case ISD::TargetBlockAddress:
2571 case ISD::TargetJumpTable:
2572 case ISD::TargetGlobalTLSAddress:
2573 case ISD::TargetGlobalAddress:
2574 case ISD::TokenFactor:
2575 case ISD::CopyFromReg:
2576 case ISD::CopyToReg:
2578 case ISD::LIFETIME_START:
2579 case ISD::LIFETIME_END:
2580 NodeToMatch->setNodeId(-1); // Mark selected.
2582 case ISD::AssertSext:
2583 case ISD::AssertZext:
2584 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2585 NodeToMatch->getOperand(0));
2587 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2588 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2589 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2590 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2593 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2595 // Set up the node stack with NodeToMatch as the only node on the stack.
2596 SmallVector<SDValue, 8> NodeStack;
2597 SDValue N = SDValue(NodeToMatch, 0);
2598 NodeStack.push_back(N);
2600 // MatchScopes - Scopes used when matching, if a match failure happens, this
2601 // indicates where to continue checking.
2602 SmallVector<MatchScope, 8> MatchScopes;
2604 // RecordedNodes - This is the set of nodes that have been recorded by the
2605 // state machine. The second value is the parent of the node, or null if the
2606 // root is recorded.
2607 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2609 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2611 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2613 // These are the current input chain and glue for use when generating nodes.
2614 // Various Emit operations change these. For example, emitting a copytoreg
2615 // uses and updates these.
2616 SDValue InputChain, InputGlue;
2618 // ChainNodesMatched - If a pattern matches nodes that have input/output
2619 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2620 // which ones they are. The result is captured into this list so that we can
2621 // update the chain results when the pattern is complete.
2622 SmallVector<SDNode*, 3> ChainNodesMatched;
2623 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2625 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2626 NodeToMatch->dump(CurDAG);
2629 // Determine where to start the interpreter. Normally we start at opcode #0,
2630 // but if the state machine starts with an OPC_SwitchOpcode, then we
2631 // accelerate the first lookup (which is guaranteed to be hot) with the
2632 // OpcodeOffset table.
2633 unsigned MatcherIndex = 0;
2635 if (!OpcodeOffset.empty()) {
2636 // Already computed the OpcodeOffset table, just index into it.
2637 if (N.getOpcode() < OpcodeOffset.size())
2638 MatcherIndex = OpcodeOffset[N.getOpcode()];
2639 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2641 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2642 // Otherwise, the table isn't computed, but the state machine does start
2643 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2644 // is the first time we're selecting an instruction.
2647 // Get the size of this case.
2648 unsigned CaseSize = MatcherTable[Idx++];
2650 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2651 if (CaseSize == 0) break;
2653 // Get the opcode, add the index to the table.
2654 uint16_t Opc = MatcherTable[Idx++];
2655 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2656 if (Opc >= OpcodeOffset.size())
2657 OpcodeOffset.resize((Opc+1)*2);
2658 OpcodeOffset[Opc] = Idx;
2662 // Okay, do the lookup for the first opcode.
2663 if (N.getOpcode() < OpcodeOffset.size())
2664 MatcherIndex = OpcodeOffset[N.getOpcode()];
2668 assert(MatcherIndex < TableSize && "Invalid index");
2670 unsigned CurrentOpcodeIndex = MatcherIndex;
2672 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2675 // Okay, the semantics of this operation are that we should push a scope
2676 // then evaluate the first child. However, pushing a scope only to have
2677 // the first check fail (which then pops it) is inefficient. If we can
2678 // determine immediately that the first check (or first several) will
2679 // immediately fail, don't even bother pushing a scope for them.
2683 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2684 if (NumToSkip & 128)
2685 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2686 // Found the end of the scope with no match.
2687 if (NumToSkip == 0) {
2692 FailIndex = MatcherIndex+NumToSkip;
2694 unsigned MatcherIndexOfPredicate = MatcherIndex;
2695 (void)MatcherIndexOfPredicate; // silence warning.
2697 // If we can't evaluate this predicate without pushing a scope (e.g. if
2698 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2699 // push the scope and evaluate the full predicate chain.
2701 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2702 Result, *this, RecordedNodes);
2706 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2707 << "index " << MatcherIndexOfPredicate
2708 << ", continuing at " << FailIndex << "\n");
2709 ++NumDAGIselRetries;
2711 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2712 // move to the next case.
2713 MatcherIndex = FailIndex;
2716 // If the whole scope failed to match, bail.
2717 if (FailIndex == 0) break;
2719 // Push a MatchScope which indicates where to go if the first child fails
2721 MatchScope NewEntry;
2722 NewEntry.FailIndex = FailIndex;
2723 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2724 NewEntry.NumRecordedNodes = RecordedNodes.size();
2725 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2726 NewEntry.InputChain = InputChain;
2727 NewEntry.InputGlue = InputGlue;
2728 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2729 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2730 MatchScopes.push_back(NewEntry);
2733 case OPC_RecordNode: {
2734 // Remember this node, it may end up being an operand in the pattern.
2735 SDNode *Parent = nullptr;
2736 if (NodeStack.size() > 1)
2737 Parent = NodeStack[NodeStack.size()-2].getNode();
2738 RecordedNodes.push_back(std::make_pair(N, Parent));
2742 case OPC_RecordChild0: case OPC_RecordChild1:
2743 case OPC_RecordChild2: case OPC_RecordChild3:
2744 case OPC_RecordChild4: case OPC_RecordChild5:
2745 case OPC_RecordChild6: case OPC_RecordChild7: {
2746 unsigned ChildNo = Opcode-OPC_RecordChild0;
2747 if (ChildNo >= N.getNumOperands())
2748 break; // Match fails if out of range child #.
2750 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2754 case OPC_RecordMemRef:
2755 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2758 case OPC_CaptureGlueInput:
2759 // If the current node has an input glue, capture it in InputGlue.
2760 if (N->getNumOperands() != 0 &&
2761 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2762 InputGlue = N->getOperand(N->getNumOperands()-1);
2765 case OPC_MoveChild: {
2766 unsigned ChildNo = MatcherTable[MatcherIndex++];
2767 if (ChildNo >= N.getNumOperands())
2768 break; // Match fails if out of range child #.
2769 N = N.getOperand(ChildNo);
2770 NodeStack.push_back(N);
2774 case OPC_MoveParent:
2775 // Pop the current node off the NodeStack.
2776 NodeStack.pop_back();
2777 assert(!NodeStack.empty() && "Node stack imbalance!");
2778 N = NodeStack.back();
2782 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2785 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2786 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2787 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2788 Opcode-OPC_CheckChild0Same))
2792 case OPC_CheckPatternPredicate:
2793 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2795 case OPC_CheckPredicate:
2796 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2800 case OPC_CheckComplexPat: {
2801 unsigned CPNum = MatcherTable[MatcherIndex++];
2802 unsigned RecNo = MatcherTable[MatcherIndex++];
2803 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2805 // If target can modify DAG during matching, keep the matching state
2807 std::unique_ptr<MatchStateUpdater> MSU;
2808 if (ComplexPatternFuncMutatesDAG())
2809 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2812 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2813 RecordedNodes[RecNo].first, CPNum,
2818 case OPC_CheckOpcode:
2819 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2823 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2827 case OPC_SwitchOpcode: {
2828 unsigned CurNodeOpcode = N.getOpcode();
2829 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2832 // Get the size of this case.
2833 CaseSize = MatcherTable[MatcherIndex++];
2835 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2836 if (CaseSize == 0) break;
2838 uint16_t Opc = MatcherTable[MatcherIndex++];
2839 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2841 // If the opcode matches, then we will execute this case.
2842 if (CurNodeOpcode == Opc)
2845 // Otherwise, skip over this case.
2846 MatcherIndex += CaseSize;
2849 // If no cases matched, bail out.
2850 if (CaseSize == 0) break;
2852 // Otherwise, execute the case we found.
2853 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2854 << " to " << MatcherIndex << "\n");
2858 case OPC_SwitchType: {
2859 MVT CurNodeVT = N.getSimpleValueType();
2860 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2863 // Get the size of this case.
2864 CaseSize = MatcherTable[MatcherIndex++];
2866 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2867 if (CaseSize == 0) break;
2869 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2870 if (CaseVT == MVT::iPTR)
2871 CaseVT = TLI->getPointerTy();
2873 // If the VT matches, then we will execute this case.
2874 if (CurNodeVT == CaseVT)
2877 // Otherwise, skip over this case.
2878 MatcherIndex += CaseSize;
2881 // If no cases matched, bail out.
2882 if (CaseSize == 0) break;
2884 // Otherwise, execute the case we found.
2885 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2886 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2889 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2890 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2891 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2892 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2893 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2894 Opcode-OPC_CheckChild0Type))
2897 case OPC_CheckCondCode:
2898 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2900 case OPC_CheckValueType:
2901 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2904 case OPC_CheckInteger:
2905 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2907 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2908 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2909 case OPC_CheckChild4Integer:
2910 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2911 Opcode-OPC_CheckChild0Integer)) break;
2913 case OPC_CheckAndImm:
2914 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2916 case OPC_CheckOrImm:
2917 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2920 case OPC_CheckFoldableChainNode: {
2921 assert(NodeStack.size() != 1 && "No parent node");
2922 // Verify that all intermediate nodes between the root and this one have
2924 bool HasMultipleUses = false;
2925 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2926 if (!NodeStack[i].hasOneUse()) {
2927 HasMultipleUses = true;
2930 if (HasMultipleUses) break;
2932 // Check to see that the target thinks this is profitable to fold and that
2933 // we can fold it without inducing cycles in the graph.
2934 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2936 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2937 NodeToMatch, OptLevel,
2938 true/*We validate our own chains*/))
2943 case OPC_EmitInteger: {
2944 MVT::SimpleValueType VT =
2945 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2946 int64_t Val = MatcherTable[MatcherIndex++];
2948 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2949 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2950 CurDAG->getTargetConstant(Val, VT), nullptr));
2953 case OPC_EmitRegister: {
2954 MVT::SimpleValueType VT =
2955 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2956 unsigned RegNo = MatcherTable[MatcherIndex++];
2957 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2958 CurDAG->getRegister(RegNo, VT), nullptr));
2961 case OPC_EmitRegister2: {
2962 // For targets w/ more than 256 register names, the register enum
2963 // values are stored in two bytes in the matcher table (just like
2965 MVT::SimpleValueType VT =
2966 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2967 unsigned RegNo = MatcherTable[MatcherIndex++];
2968 RegNo |= MatcherTable[MatcherIndex++] << 8;
2969 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2970 CurDAG->getRegister(RegNo, VT), nullptr));
2974 case OPC_EmitConvertToTarget: {
2975 // Convert from IMM/FPIMM to target version.
2976 unsigned RecNo = MatcherTable[MatcherIndex++];
2977 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2978 SDValue Imm = RecordedNodes[RecNo].first;
2980 if (Imm->getOpcode() == ISD::Constant) {
2981 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2982 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2983 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2984 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2985 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2988 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2992 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2993 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2994 // These are space-optimized forms of OPC_EmitMergeInputChains.
2995 assert(!InputChain.getNode() &&
2996 "EmitMergeInputChains should be the first chain producing node");
2997 assert(ChainNodesMatched.empty() &&
2998 "Should only have one EmitMergeInputChains per match");
3000 // Read all of the chained nodes.
3001 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3002 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3003 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3005 // FIXME: What if other value results of the node have uses not matched
3007 if (ChainNodesMatched.back() != NodeToMatch &&
3008 !RecordedNodes[RecNo].first.hasOneUse()) {
3009 ChainNodesMatched.clear();
3013 // Merge the input chains if they are not intra-pattern references.
3014 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3016 if (!InputChain.getNode())
3017 break; // Failed to merge.
3021 case OPC_EmitMergeInputChains: {
3022 assert(!InputChain.getNode() &&
3023 "EmitMergeInputChains should be the first chain producing node");
3024 // This node gets a list of nodes we matched in the input that have
3025 // chains. We want to token factor all of the input chains to these nodes
3026 // together. However, if any of the input chains is actually one of the
3027 // nodes matched in this pattern, then we have an intra-match reference.
3028 // Ignore these because the newly token factored chain should not refer to
3030 unsigned NumChains = MatcherTable[MatcherIndex++];
3031 assert(NumChains != 0 && "Can't TF zero chains");
3033 assert(ChainNodesMatched.empty() &&
3034 "Should only have one EmitMergeInputChains per match");
3036 // Read all of the chained nodes.
3037 for (unsigned i = 0; i != NumChains; ++i) {
3038 unsigned RecNo = MatcherTable[MatcherIndex++];
3039 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3040 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3042 // FIXME: What if other value results of the node have uses not matched
3044 if (ChainNodesMatched.back() != NodeToMatch &&
3045 !RecordedNodes[RecNo].first.hasOneUse()) {
3046 ChainNodesMatched.clear();
3051 // If the inner loop broke out, the match fails.
3052 if (ChainNodesMatched.empty())
3055 // Merge the input chains if they are not intra-pattern references.
3056 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3058 if (!InputChain.getNode())
3059 break; // Failed to merge.
3064 case OPC_EmitCopyToReg: {
3065 unsigned RecNo = MatcherTable[MatcherIndex++];
3066 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3067 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3069 if (!InputChain.getNode())
3070 InputChain = CurDAG->getEntryNode();
3072 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3073 DestPhysReg, RecordedNodes[RecNo].first,
3076 InputGlue = InputChain.getValue(1);
3080 case OPC_EmitNodeXForm: {
3081 unsigned XFormNo = MatcherTable[MatcherIndex++];
3082 unsigned RecNo = MatcherTable[MatcherIndex++];
3083 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3084 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3085 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3090 case OPC_MorphNodeTo: {
3091 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3092 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3093 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3094 // Get the result VT list.
3095 unsigned NumVTs = MatcherTable[MatcherIndex++];
3096 SmallVector<EVT, 4> VTs;
3097 for (unsigned i = 0; i != NumVTs; ++i) {
3098 MVT::SimpleValueType VT =
3099 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3100 if (VT == MVT::iPTR)
3101 VT = TLI->getPointerTy().SimpleTy;
3105 if (EmitNodeInfo & OPFL_Chain)
3106 VTs.push_back(MVT::Other);
3107 if (EmitNodeInfo & OPFL_GlueOutput)
3108 VTs.push_back(MVT::Glue);
3110 // This is hot code, so optimize the two most common cases of 1 and 2
3113 if (VTs.size() == 1)
3114 VTList = CurDAG->getVTList(VTs[0]);
3115 else if (VTs.size() == 2)
3116 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3118 VTList = CurDAG->getVTList(VTs);
3120 // Get the operand list.
3121 unsigned NumOps = MatcherTable[MatcherIndex++];
3122 SmallVector<SDValue, 8> Ops;
3123 for (unsigned i = 0; i != NumOps; ++i) {
3124 unsigned RecNo = MatcherTable[MatcherIndex++];
3126 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3128 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3129 Ops.push_back(RecordedNodes[RecNo].first);
3132 // If there are variadic operands to add, handle them now.
3133 if (EmitNodeInfo & OPFL_VariadicInfo) {
3134 // Determine the start index to copy from.
3135 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3136 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3137 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3138 "Invalid variadic node");
3139 // Copy all of the variadic operands, not including a potential glue
3141 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3143 SDValue V = NodeToMatch->getOperand(i);
3144 if (V.getValueType() == MVT::Glue) break;
3149 // If this has chain/glue inputs, add them.
3150 if (EmitNodeInfo & OPFL_Chain)
3151 Ops.push_back(InputChain);
3152 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3153 Ops.push_back(InputGlue);
3156 SDNode *Res = nullptr;
3157 if (Opcode != OPC_MorphNodeTo) {
3158 // If this is a normal EmitNode command, just create the new node and
3159 // add the results to the RecordedNodes list.
3160 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3163 // Add all the non-glue/non-chain results to the RecordedNodes list.
3164 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3165 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3166 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3170 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3171 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3173 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3174 // We will visit the equivalent node later.
3175 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3179 // If the node had chain/glue results, update our notion of the current
3181 if (EmitNodeInfo & OPFL_GlueOutput) {
3182 InputGlue = SDValue(Res, VTs.size()-1);
3183 if (EmitNodeInfo & OPFL_Chain)
3184 InputChain = SDValue(Res, VTs.size()-2);
3185 } else if (EmitNodeInfo & OPFL_Chain)
3186 InputChain = SDValue(Res, VTs.size()-1);
3188 // If the OPFL_MemRefs glue is set on this node, slap all of the
3189 // accumulated memrefs onto it.
3191 // FIXME: This is vastly incorrect for patterns with multiple outputs
3192 // instructions that access memory and for ComplexPatterns that match
3194 if (EmitNodeInfo & OPFL_MemRefs) {
3195 // Only attach load or store memory operands if the generated
3196 // instruction may load or store.
3197 const MCInstrDesc &MCID = TII->get(TargetOpc);
3198 bool mayLoad = MCID.mayLoad();
3199 bool mayStore = MCID.mayStore();
3201 unsigned NumMemRefs = 0;
3202 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3203 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3204 if ((*I)->isLoad()) {
3207 } else if ((*I)->isStore()) {
3215 MachineSDNode::mmo_iterator MemRefs =
3216 MF->allocateMemRefsArray(NumMemRefs);
3218 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3219 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3220 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3221 if ((*I)->isLoad()) {
3224 } else if ((*I)->isStore()) {
3232 cast<MachineSDNode>(Res)
3233 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3237 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3238 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3240 // If this was a MorphNodeTo then we're completely done!
3241 if (Opcode == OPC_MorphNodeTo) {
3242 // Update chain and glue uses.
3243 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3244 InputGlue, GlueResultNodesMatched, true);
3251 case OPC_MarkGlueResults: {
3252 unsigned NumNodes = MatcherTable[MatcherIndex++];
3254 // Read and remember all the glue-result nodes.
3255 for (unsigned i = 0; i != NumNodes; ++i) {
3256 unsigned RecNo = MatcherTable[MatcherIndex++];
3258 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3260 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3261 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3266 case OPC_CompleteMatch: {
3267 // The match has been completed, and any new nodes (if any) have been
3268 // created. Patch up references to the matched dag to use the newly
3270 unsigned NumResults = MatcherTable[MatcherIndex++];
3272 for (unsigned i = 0; i != NumResults; ++i) {
3273 unsigned ResSlot = MatcherTable[MatcherIndex++];
3275 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3277 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3278 SDValue Res = RecordedNodes[ResSlot].first;
3280 assert(i < NodeToMatch->getNumValues() &&
3281 NodeToMatch->getValueType(i) != MVT::Other &&
3282 NodeToMatch->getValueType(i) != MVT::Glue &&
3283 "Invalid number of results to complete!");
3284 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3285 NodeToMatch->getValueType(i) == MVT::iPTR ||
3286 Res.getValueType() == MVT::iPTR ||
3287 NodeToMatch->getValueType(i).getSizeInBits() ==
3288 Res.getValueType().getSizeInBits()) &&
3289 "invalid replacement");
3290 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3293 // If the root node defines glue, add it to the glue nodes to update list.
3294 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3295 GlueResultNodesMatched.push_back(NodeToMatch);
3297 // Update chain and glue uses.
3298 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3299 InputGlue, GlueResultNodesMatched, false);
3301 assert(NodeToMatch->use_empty() &&
3302 "Didn't replace all uses of the node?");
3304 // FIXME: We just return here, which interacts correctly with SelectRoot
3305 // above. We should fix this to not return an SDNode* anymore.
3310 // If the code reached this point, then the match failed. See if there is
3311 // another child to try in the current 'Scope', otherwise pop it until we
3312 // find a case to check.
3313 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3314 ++NumDAGIselRetries;
3316 if (MatchScopes.empty()) {
3317 CannotYetSelect(NodeToMatch);
3321 // Restore the interpreter state back to the point where the scope was
3323 MatchScope &LastScope = MatchScopes.back();
3324 RecordedNodes.resize(LastScope.NumRecordedNodes);
3326 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3327 N = NodeStack.back();
3329 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3330 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3331 MatcherIndex = LastScope.FailIndex;
3333 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3335 InputChain = LastScope.InputChain;
3336 InputGlue = LastScope.InputGlue;
3337 if (!LastScope.HasChainNodesMatched)
3338 ChainNodesMatched.clear();
3339 if (!LastScope.HasGlueResultNodesMatched)
3340 GlueResultNodesMatched.clear();
3342 // Check to see what the offset is at the new MatcherIndex. If it is zero
3343 // we have reached the end of this scope, otherwise we have another child
3344 // in the current scope to try.
3345 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3346 if (NumToSkip & 128)
3347 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3349 // If we have another child in this scope to match, update FailIndex and
3351 if (NumToSkip != 0) {
3352 LastScope.FailIndex = MatcherIndex+NumToSkip;
3356 // End of this scope, pop it and try the next child in the containing
3358 MatchScopes.pop_back();
3365 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3367 raw_string_ostream Msg(msg);
3368 Msg << "Cannot select: ";
3370 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3371 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3372 N->getOpcode() != ISD::INTRINSIC_VOID) {
3373 N->printrFull(Msg, CurDAG);
3374 Msg << "\nIn function: " << MF->getName();
3376 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3378 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3379 if (iid < Intrinsic::num_intrinsics)
3380 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3381 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3382 Msg << "target intrinsic %" << TII->getName(iid);
3384 Msg << "unknown intrinsic #" << iid;
3386 report_fatal_error(Msg.str());
3389 char SelectionDAGISel::ID = 0;