1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/ADT/Statistic.h"
55 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
56 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
57 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
58 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
61 STATISTIC(NumBBWithOutOfOrderLineInfo,
62 "Number of blocks with out of order line number info");
63 STATISTIC(NumMBBWithOutOfOrderLineInfo,
64 "Number of machine blocks with out of order line number info");
68 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
69 cl::desc("Enable verbose messages in the \"fast\" "
70 "instruction selector"));
72 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
73 cl::desc("Enable abort calls when \"fast\" instruction fails"));
77 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
78 cl::desc("Pop up a window to show dags before the first "
81 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
82 cl::desc("Pop up a window to show dags before legalize types"));
84 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
85 cl::desc("Pop up a window to show dags before legalize"));
87 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
88 cl::desc("Pop up a window to show dags before the second "
91 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
92 cl::desc("Pop up a window to show dags before the post legalize types"
93 " dag combine pass"));
95 ViewISelDAGs("view-isel-dags", cl::Hidden,
96 cl::desc("Pop up a window to show isel dags as they are selected"));
98 ViewSchedDAGs("view-sched-dags", cl::Hidden,
99 cl::desc("Pop up a window to show sched dags as they are processed"));
101 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
102 cl::desc("Pop up a window to show SUnit dags after they are processed"));
104 static const bool ViewDAGCombine1 = false,
105 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
106 ViewDAGCombine2 = false,
107 ViewDAGCombineLT = false,
108 ViewISelDAGs = false, ViewSchedDAGs = false,
109 ViewSUnitDAGs = false;
112 //===---------------------------------------------------------------------===//
114 /// RegisterScheduler class - Track the registration of instruction schedulers.
116 //===---------------------------------------------------------------------===//
117 MachinePassRegistry RegisterScheduler::Registry;
119 //===---------------------------------------------------------------------===//
121 /// ISHeuristic command line option for instruction schedulers.
123 //===---------------------------------------------------------------------===//
124 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
125 RegisterPassParser<RegisterScheduler> >
126 ISHeuristic("pre-RA-sched",
127 cl::init(&createDefaultScheduler),
128 cl::desc("Instruction schedulers available (before register"
131 static RegisterScheduler
132 defaultListDAGScheduler("default", "Best scheduler for the target",
133 createDefaultScheduler);
136 //===--------------------------------------------------------------------===//
137 /// createDefaultScheduler - This creates an instruction scheduler appropriate
139 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
140 CodeGenOpt::Level OptLevel) {
141 const TargetLowering &TLI = IS->getTargetLowering();
143 if (OptLevel == CodeGenOpt::None)
144 return createSourceListDAGScheduler(IS, OptLevel);
145 if (TLI.getSchedulingPreference() == Sched::Latency)
146 return createTDListDAGScheduler(IS, OptLevel);
147 if (TLI.getSchedulingPreference() == Sched::RegPressure)
148 return createBURRListDAGScheduler(IS, OptLevel);
149 if (TLI.getSchedulingPreference() == Sched::Hybrid)
150 return createHybridListDAGScheduler(IS, OptLevel);
151 assert(TLI.getSchedulingPreference() == Sched::ILP &&
152 "Unknown sched type!");
153 return createILPListDAGScheduler(IS, OptLevel);
157 // EmitInstrWithCustomInserter - This method should be implemented by targets
158 // that mark instructions with the 'usesCustomInserter' flag. These
159 // instructions are special in various ways, which require special support to
160 // insert. The specified MachineInstr is created but not inserted into any
161 // basic blocks, and this method is called to expand it into a sequence of
162 // instructions, potentially also creating new basic blocks and control flow.
163 // When new basic blocks are inserted and the edges from MBB to its successors
164 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
167 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
168 MachineBasicBlock *MBB) const {
170 dbgs() << "If a target marks an instruction with "
171 "'usesCustomInserter', it must implement "
172 "TargetLowering::EmitInstrWithCustomInserter!";
178 //===----------------------------------------------------------------------===//
179 // SelectionDAGISel code
180 //===----------------------------------------------------------------------===//
182 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
183 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
184 FuncInfo(new FunctionLoweringInfo(TLI)),
185 CurDAG(new SelectionDAG(tm)),
186 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
190 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
191 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
194 SelectionDAGISel::~SelectionDAGISel() {
200 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
201 AU.addRequired<AliasAnalysis>();
202 AU.addPreserved<AliasAnalysis>();
203 AU.addRequired<GCModuleInfo>();
204 AU.addPreserved<GCModuleInfo>();
205 MachineFunctionPass::getAnalysisUsage(AU);
208 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
209 /// other function that gcc recognizes as "returning twice". This is used to
210 /// limit code-gen optimizations on the machine function.
212 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
213 static bool FunctionCallsSetJmp(const Function *F) {
214 const Module *M = F->getParent();
215 static const char *ReturnsTwiceFns[] = {
225 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
227 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
228 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
229 if (!Callee->use_empty())
230 for (Value::const_use_iterator
231 I = Callee->use_begin(), E = Callee->use_end();
233 if (const CallInst *CI = dyn_cast<CallInst>(*I))
234 if (CI->getParent()->getParent() == F)
239 #undef NUM_RETURNS_TWICE_FNS
242 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
243 // Do some sanity-checking on the command-line options.
244 assert((!EnableFastISelVerbose || EnableFastISel) &&
245 "-fast-isel-verbose requires -fast-isel");
246 assert((!EnableFastISelAbort || EnableFastISel) &&
247 "-fast-isel-abort requires -fast-isel");
249 const Function &Fn = *mf.getFunction();
250 const TargetInstrInfo &TII = *TM.getInstrInfo();
251 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
254 RegInfo = &MF->getRegInfo();
255 AA = &getAnalysis<AliasAnalysis>();
256 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
258 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
261 FuncInfo->set(Fn, *MF);
264 SelectAllBasicBlocks(Fn);
266 // If the first basic block in the function has live ins that need to be
267 // copied into vregs, emit the copies into the top of the block before
268 // emitting the code for the block.
269 MachineBasicBlock *EntryMBB = MF->begin();
270 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
272 DenseMap<unsigned, unsigned> LiveInMap;
273 if (!FuncInfo->ArgDbgValues.empty())
274 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
275 E = RegInfo->livein_end(); LI != E; ++LI)
277 LiveInMap.insert(std::make_pair(LI->first, LI->second));
279 // Insert DBG_VALUE instructions for function arguments to the entry block.
280 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
281 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
282 unsigned Reg = MI->getOperand(0).getReg();
283 if (TargetRegisterInfo::isPhysicalRegister(Reg))
284 EntryMBB->insert(EntryMBB->begin(), MI);
286 MachineInstr *Def = RegInfo->getVRegDef(Reg);
287 MachineBasicBlock::iterator InsertPos = Def;
288 // FIXME: VR def may not be in entry block.
289 Def->getParent()->insert(llvm::next(InsertPos), MI);
292 // If Reg is live-in then update debug info to track its copy in a vreg.
293 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
294 if (LDI != LiveInMap.end()) {
295 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
296 MachineBasicBlock::iterator InsertPos = Def;
297 const MDNode *Variable =
298 MI->getOperand(MI->getNumOperands()-1).getMetadata();
299 unsigned Offset = MI->getOperand(1).getImm();
300 // Def is never a terminator here, so it is ok to increment InsertPos.
301 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
302 TII.get(TargetOpcode::DBG_VALUE))
303 .addReg(LDI->second, RegState::Debug)
304 .addImm(Offset).addMetadata(Variable);
306 // If this vreg is directly copied into an exported register then
307 // that COPY instructions also need DBG_VALUE, if it is the only
308 // user of LDI->second.
309 MachineInstr *CopyUseMI = NULL;
310 for (MachineRegisterInfo::use_iterator
311 UI = RegInfo->use_begin(LDI->second);
312 MachineInstr *UseMI = UI.skipInstruction();) {
313 if (UseMI->isDebugValue()) continue;
314 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
315 CopyUseMI = UseMI; continue;
317 // Otherwise this is another use or second copy use.
318 CopyUseMI = NULL; break;
321 MachineInstr *NewMI =
322 BuildMI(*MF, CopyUseMI->getDebugLoc(),
323 TII.get(TargetOpcode::DBG_VALUE))
324 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
325 .addImm(Offset).addMetadata(Variable);
326 EntryMBB->insertAfter(CopyUseMI, NewMI);
331 // Determine if there are any calls in this machine function.
332 MachineFrameInfo *MFI = MF->getFrameInfo();
333 if (!MFI->hasCalls()) {
334 for (MachineFunction::const_iterator
335 I = MF->begin(), E = MF->end(); I != E; ++I) {
336 const MachineBasicBlock *MBB = I;
337 for (MachineBasicBlock::const_iterator
338 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
339 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
341 // Operand 1 of an inline asm instruction indicates whether the asm
342 // needs stack or not.
343 if ((II->isInlineAsm() && II->getOperand(1).getImm()) ||
344 (TID.isCall() && !TID.isReturn())) {
345 MFI->setHasCalls(true);
353 // Determine if there is a call to setjmp in the machine function.
354 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
356 // Replace forward-declared registers with the registers containing
357 // the desired value.
358 MachineRegisterInfo &MRI = MF->getRegInfo();
359 for (DenseMap<unsigned, unsigned>::iterator
360 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
362 unsigned From = I->first;
363 unsigned To = I->second;
364 // If To is also scheduled to be replaced, find what its ultimate
367 DenseMap<unsigned, unsigned>::iterator J =
368 FuncInfo->RegFixups.find(To);
373 MRI.replaceRegWith(From, To);
376 // Release function-specific state. SDB and CurDAG are already cleared
384 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
385 BasicBlock::const_iterator End,
387 // Lower all of the non-terminator instructions. If a call is emitted
388 // as a tail call, cease emitting nodes for this block. Terminators
389 // are handled below.
390 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
393 // Make sure the root of the DAG is up-to-date.
394 CurDAG->setRoot(SDB->getControlRoot());
395 HadTailCall = SDB->HasTailCall;
398 // Final step, emit the lowered DAG as machine code.
403 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
404 SmallPtrSet<SDNode*, 128> VisitedNodes;
405 SmallVector<SDNode*, 128> Worklist;
407 Worklist.push_back(CurDAG->getRoot().getNode());
414 SDNode *N = Worklist.pop_back_val();
416 // If we've already seen this node, ignore it.
417 if (!VisitedNodes.insert(N))
420 // Otherwise, add all chain operands to the worklist.
421 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
422 if (N->getOperand(i).getValueType() == MVT::Other)
423 Worklist.push_back(N->getOperand(i).getNode());
425 // If this is a CopyToReg with a vreg dest, process it.
426 if (N->getOpcode() != ISD::CopyToReg)
429 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
430 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
433 // Ignore non-scalar or non-integer values.
434 SDValue Src = N->getOperand(2);
435 EVT SrcVT = Src.getValueType();
436 if (!SrcVT.isInteger() || SrcVT.isVector())
439 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
440 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
441 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
443 // Only install this information if it tells us something.
444 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
445 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
446 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
447 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
448 FunctionLoweringInfo::LiveOutInfo &LOI =
449 FuncInfo->LiveOutRegInfo[DestReg];
450 LOI.NumSignBits = NumSignBits;
451 LOI.KnownOne = KnownOne;
452 LOI.KnownZero = KnownZero;
454 } while (!Worklist.empty());
457 void SelectionDAGISel::CodeGenAndEmitDAG() {
458 std::string GroupName;
459 if (TimePassesIsEnabled)
460 GroupName = "Instruction Selection and Scheduling";
461 std::string BlockName;
462 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
463 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
465 BlockName = MF->getFunction()->getNameStr() + ":" +
466 FuncInfo->MBB->getBasicBlock()->getNameStr();
468 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
470 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
472 // Run the DAG combiner in pre-legalize mode.
474 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
475 CurDAG->Combine(Unrestricted, *AA, OptLevel);
478 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
480 // Second step, hack on the DAG until it only uses operations and types that
481 // the target supports.
482 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
487 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
488 Changed = CurDAG->LegalizeTypes();
491 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
494 if (ViewDAGCombineLT)
495 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
497 // Run the DAG combiner in post-type-legalize mode.
499 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
500 TimePassesIsEnabled);
501 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
504 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
509 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
510 Changed = CurDAG->LegalizeVectors();
515 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
516 CurDAG->LegalizeTypes();
519 if (ViewDAGCombineLT)
520 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
522 // Run the DAG combiner in post-type-legalize mode.
524 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
525 TimePassesIsEnabled);
526 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
529 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
533 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
536 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
537 CurDAG->Legalize(OptLevel);
540 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
542 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
544 // Run the DAG combiner in post-legalize mode.
546 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
547 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
550 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
552 if (OptLevel != CodeGenOpt::None)
553 ComputeLiveOutVRegInfo();
555 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
557 // Third, instruction select all of the operations to machine code, adding the
558 // code to the MachineBasicBlock.
560 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
561 DoInstructionSelection();
564 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
566 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
568 // Schedule machine code.
569 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
571 NamedRegionTimer T("Instruction Scheduling", GroupName,
572 TimePassesIsEnabled);
573 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
576 if (ViewSUnitDAGs) Scheduler->viewGraph();
578 // Emit machine code to BB. This can change 'BB' to the last block being
580 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
582 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
584 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
585 FuncInfo->InsertPt = Scheduler->InsertPos;
588 // If the block was split, make sure we update any references that are used to
589 // update PHI nodes later on.
590 if (FirstMBB != LastMBB)
591 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
593 // Free the scheduler state.
595 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
596 TimePassesIsEnabled);
600 // Free the SelectionDAG state, now that we're finished with it.
604 void SelectionDAGISel::DoInstructionSelection() {
605 DEBUG(errs() << "===== Instruction selection begins:\n");
609 // Select target instructions for the DAG.
611 // Number all nodes with a topological order and set DAGSize.
612 DAGSize = CurDAG->AssignTopologicalOrder();
614 // Create a dummy node (which is not added to allnodes), that adds
615 // a reference to the root node, preventing it from being deleted,
616 // and tracking any changes of the root.
617 HandleSDNode Dummy(CurDAG->getRoot());
618 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
621 // The AllNodes list is now topological-sorted. Visit the
622 // nodes by starting at the end of the list (the root of the
623 // graph) and preceding back toward the beginning (the entry
625 while (ISelPosition != CurDAG->allnodes_begin()) {
626 SDNode *Node = --ISelPosition;
627 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
628 // but there are currently some corner cases that it misses. Also, this
629 // makes it theoretically possible to disable the DAGCombiner.
630 if (Node->use_empty())
633 SDNode *ResNode = Select(Node);
635 // FIXME: This is pretty gross. 'Select' should be changed to not return
636 // anything at all and this code should be nuked with a tactical strike.
638 // If node should not be replaced, continue with the next one.
639 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
643 ReplaceUses(Node, ResNode);
645 // If after the replacement this node is not used any more,
646 // remove this dead node.
647 if (Node->use_empty()) { // Don't delete EntryToken, etc.
648 ISelUpdater ISU(ISelPosition);
649 CurDAG->RemoveDeadNode(Node, &ISU);
653 CurDAG->setRoot(Dummy.getValue());
656 DEBUG(errs() << "===== Instruction selection ends:\n");
658 PostprocessISelDAG();
661 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
662 /// do other setup for EH landing-pad blocks.
663 void SelectionDAGISel::PrepareEHLandingPad() {
664 // Add a label to mark the beginning of the landing pad. Deletion of the
665 // landing pad can thus be detected via the MachineModuleInfo.
666 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
668 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
669 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
672 // Mark exception register as live in.
673 unsigned Reg = TLI.getExceptionAddressRegister();
674 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
676 // Mark exception selector register as live in.
677 Reg = TLI.getExceptionSelectorRegister();
678 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
680 // FIXME: Hack around an exception handling flaw (PR1508): the personality
681 // function and list of typeids logically belong to the invoke (or, if you
682 // like, the basic block containing the invoke), and need to be associated
683 // with it in the dwarf exception handling tables. Currently however the
684 // information is provided by an intrinsic (eh.selector) that can be moved
685 // to unexpected places by the optimizers: if the unwind edge is critical,
686 // then breaking it can result in the intrinsics being in the successor of
687 // the landing pad, not the landing pad itself. This results
688 // in exceptions not being caught because no typeids are associated with
689 // the invoke. This may not be the only way things can go wrong, but it
690 // is the only way we try to work around for the moment.
691 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
692 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
694 if (Br && Br->isUnconditional()) { // Critical edge?
695 BasicBlock::const_iterator I, E;
696 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
697 if (isa<EHSelectorInst>(I))
701 // No catch info found - try to extract some from the successor.
702 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
709 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
711 // Don't try to fold volatile loads. Target has to deal with alignment
713 if (LI->isVolatile()) return false;
715 // Figure out which vreg this is going into.
716 unsigned LoadReg = FastIS->getRegForValue(LI);
717 assert(LoadReg && "Load isn't already assigned a vreg? ");
719 // Check to see what the uses of this vreg are. If it has no uses, or more
720 // than one use (at the machine instr level) then we can't fold it.
721 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
722 if (RI == RegInfo->reg_end())
725 // See if there is exactly one use of the vreg. If there are multiple uses,
726 // then the instruction got lowered to multiple machine instructions or the
727 // use of the loaded value ended up being multiple operands of the result, in
728 // either case, we can't fold this.
729 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
730 if (PostRI != RegInfo->reg_end())
733 assert(RI.getOperand().isUse() &&
734 "The only use of the vreg must be a use, we haven't emitted the def!");
736 // Ask the target to try folding the load.
737 return FastIS->TryToFoldLoad(&*RI, RI.getOperandNo(), LI);
741 /// CheckLineNumbers - Check if basic block instructions follow source order
743 static void CheckLineNumbers(const BasicBlock *BB) {
746 for (BasicBlock::const_iterator BI = BB->begin(),
747 BE = BB->end(); BI != BE; ++BI) {
748 const DebugLoc DL = BI->getDebugLoc();
749 if (DL.isUnknown()) continue;
750 unsigned L = DL.getLine();
751 unsigned C = DL.getCol();
752 if (L < Line || (L == Line && C < Col)) {
753 ++NumBBWithOutOfOrderLineInfo;
761 /// CheckLineNumbers - Check if machine basic block instructions follow source
763 static void CheckLineNumbers(const MachineBasicBlock *MBB) {
766 for (MachineBasicBlock::const_iterator MBI = MBB->begin(),
767 MBE = MBB->end(); MBI != MBE; ++MBI) {
768 const DebugLoc DL = MBI->getDebugLoc();
769 if (DL.isUnknown()) continue;
770 unsigned L = DL.getLine();
771 unsigned C = DL.getCol();
772 if (L < Line || (L == Line && C < Col)) {
773 ++NumMBBWithOutOfOrderLineInfo;
782 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
783 // Initialize the Fast-ISel state, if needed.
784 FastISel *FastIS = 0;
786 FastIS = TLI.createFastISel(*FuncInfo);
788 // Iterate over all basic blocks in the function.
789 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
790 const BasicBlock *LLVMBB = &*I;
792 CheckLineNumbers(LLVMBB);
794 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
795 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
797 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
798 BasicBlock::const_iterator const End = LLVMBB->end();
799 BasicBlock::const_iterator BI = End;
801 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
803 // Setup an EH landing-pad block.
804 if (FuncInfo->MBB->isLandingPad())
805 PrepareEHLandingPad();
807 // Lower any arguments needed in this block if this is the entry block.
808 if (LLVMBB == &Fn.getEntryBlock())
809 LowerArguments(LLVMBB);
811 // Before doing SelectionDAG ISel, see if FastISel has been requested.
813 FastIS->startNewBlock();
815 // Emit code for any incoming arguments. This must happen before
816 // beginning FastISel on the entry block.
817 if (LLVMBB == &Fn.getEntryBlock()) {
818 CurDAG->setRoot(SDB->getControlRoot());
822 // If we inserted any instructions at the beginning, make a note of
823 // where they are, so we can be sure to emit subsequent instructions
825 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
826 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
828 FastIS->setLastLocalValue(0);
831 // Do FastISel on as many instructions as possible.
832 for (; BI != Begin; --BI) {
833 const Instruction *Inst = llvm::prior(BI);
835 // If we no longer require this instruction, skip it.
836 if (!Inst->mayWriteToMemory() &&
837 !isa<TerminatorInst>(Inst) &&
838 !isa<DbgInfoIntrinsic>(Inst) &&
839 !FuncInfo->isExportedInst(Inst))
842 // Bottom-up: reset the insert pos at the top, after any local-value
844 FastIS->recomputeInsertPt();
846 // Try to select the instruction with FastISel.
847 if (FastIS->SelectInstruction(Inst)) {
848 // If fast isel succeeded, check to see if there is a single-use
849 // non-volatile load right before the selected instruction, and see if
850 // the load is used by the instruction. If so, try to fold it.
851 const Instruction *BeforeInst = 0;
853 BeforeInst = llvm::prior(llvm::prior(BI));
854 if (BeforeInst && isa<LoadInst>(BeforeInst) &&
855 BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst &&
856 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), FastIS)) {
857 // If we succeeded, don't re-select the load.
863 // Then handle certain instructions as single-LLVM-Instruction blocks.
864 if (isa<CallInst>(Inst)) {
865 ++NumFastIselFailures;
866 if (EnableFastISelVerbose || EnableFastISelAbort) {
867 dbgs() << "FastISel missed call: ";
871 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
872 unsigned &R = FuncInfo->ValueMap[Inst];
874 R = FuncInfo->CreateRegs(Inst->getType());
877 bool HadTailCall = false;
878 SelectBasicBlock(Inst, BI, HadTailCall);
880 // If the call was emitted as a tail call, we're done with the block.
889 // Otherwise, give up on FastISel for the rest of the block.
890 // For now, be a little lenient about non-branch terminators.
891 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
892 ++NumFastIselFailures;
893 if (EnableFastISelVerbose || EnableFastISelAbort) {
894 dbgs() << "FastISel miss: ";
897 if (EnableFastISelAbort)
898 // The "fast" selector couldn't handle something and bailed.
899 // For the purpose of debugging, just abort.
900 llvm_unreachable("FastISel didn't select the entire block");
905 FastIS->recomputeInsertPt();
913 // Run SelectionDAG instruction selection on the remainder of the block
914 // not handled by FastISel. If FastISel is not run, this is the entire
917 SelectBasicBlock(Begin, BI, HadTailCall);
920 FuncInfo->PHINodesToUpdate.clear();
925 for (MachineFunction::const_iterator MBI = MF->begin(), MBE = MF->end();
927 CheckLineNumbers(MBI);
932 SelectionDAGISel::FinishBasicBlock() {
934 DEBUG(dbgs() << "Total amount of phi nodes to update: "
935 << FuncInfo->PHINodesToUpdate.size() << "\n";
936 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
937 dbgs() << "Node " << i << " : ("
938 << FuncInfo->PHINodesToUpdate[i].first
939 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
941 // Next, now that we know what the last MBB the LLVM BB expanded is, update
942 // PHI nodes in successors.
943 if (SDB->SwitchCases.empty() &&
944 SDB->JTCases.empty() &&
945 SDB->BitTestCases.empty()) {
946 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
947 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
948 assert(PHI->isPHI() &&
949 "This is not a machine PHI node that we are updating!");
950 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
953 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
954 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
959 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
960 // Lower header first, if it wasn't already lowered
961 if (!SDB->BitTestCases[i].Emitted) {
962 // Set the current basic block to the mbb we wish to insert the code into
963 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
964 FuncInfo->InsertPt = FuncInfo->MBB->end();
966 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
967 CurDAG->setRoot(SDB->getRoot());
972 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
973 // Set the current basic block to the mbb we wish to insert the code into
974 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
975 FuncInfo->InsertPt = FuncInfo->MBB->end();
978 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
979 SDB->BitTestCases[i].Reg,
980 SDB->BitTestCases[i].Cases[j],
983 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
984 SDB->BitTestCases[i].Reg,
985 SDB->BitTestCases[i].Cases[j],
989 CurDAG->setRoot(SDB->getRoot());
995 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
997 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
998 MachineBasicBlock *PHIBB = PHI->getParent();
999 assert(PHI->isPHI() &&
1000 "This is not a machine PHI node that we are updating!");
1001 // This is "default" BB. We have two jumps to it. From "header" BB and
1002 // from last "case" BB.
1003 if (PHIBB == SDB->BitTestCases[i].Default) {
1004 PHI->addOperand(MachineOperand::
1005 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1007 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1008 PHI->addOperand(MachineOperand::
1009 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1011 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1014 // One of "cases" BB.
1015 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1017 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1018 if (cBB->isSuccessor(PHIBB)) {
1019 PHI->addOperand(MachineOperand::
1020 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1022 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1027 SDB->BitTestCases.clear();
1029 // If the JumpTable record is filled in, then we need to emit a jump table.
1030 // Updating the PHI nodes is tricky in this case, since we need to determine
1031 // whether the PHI is a successor of the range check MBB or the jump table MBB
1032 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1033 // Lower header first, if it wasn't already lowered
1034 if (!SDB->JTCases[i].first.Emitted) {
1035 // Set the current basic block to the mbb we wish to insert the code into
1036 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1037 FuncInfo->InsertPt = FuncInfo->MBB->end();
1039 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1041 CurDAG->setRoot(SDB->getRoot());
1043 CodeGenAndEmitDAG();
1046 // Set the current basic block to the mbb we wish to insert the code into
1047 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1048 FuncInfo->InsertPt = FuncInfo->MBB->end();
1050 SDB->visitJumpTable(SDB->JTCases[i].second);
1051 CurDAG->setRoot(SDB->getRoot());
1053 CodeGenAndEmitDAG();
1056 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1058 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1059 MachineBasicBlock *PHIBB = PHI->getParent();
1060 assert(PHI->isPHI() &&
1061 "This is not a machine PHI node that we are updating!");
1062 // "default" BB. We can go there only from header BB.
1063 if (PHIBB == SDB->JTCases[i].second.Default) {
1065 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1068 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1070 // JT BB. Just iterate over successors here
1071 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1073 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1075 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1079 SDB->JTCases.clear();
1081 // If the switch block involved a branch to one of the actual successors, we
1082 // need to update PHI nodes in that block.
1083 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1084 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1085 assert(PHI->isPHI() &&
1086 "This is not a machine PHI node that we are updating!");
1087 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1089 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1090 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1094 // If we generated any switch lowering information, build and codegen any
1095 // additional DAGs necessary.
1096 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1097 // Set the current basic block to the mbb we wish to insert the code into
1098 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1099 FuncInfo->InsertPt = FuncInfo->MBB->end();
1101 // Determine the unique successors.
1102 SmallVector<MachineBasicBlock *, 2> Succs;
1103 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1104 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1105 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1107 // Emit the code. Note that this could result in ThisBB being split, so
1108 // we need to check for updates.
1109 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1110 CurDAG->setRoot(SDB->getRoot());
1112 CodeGenAndEmitDAG();
1113 ThisBB = FuncInfo->MBB;
1115 // Handle any PHI nodes in successors of this chunk, as if we were coming
1116 // from the original BB before switch expansion. Note that PHI nodes can
1117 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1118 // handle them the right number of times.
1119 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1120 FuncInfo->MBB = Succs[i];
1121 FuncInfo->InsertPt = FuncInfo->MBB->end();
1122 // FuncInfo->MBB may have been removed from the CFG if a branch was
1124 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1125 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1126 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1128 // This value for this PHI node is recorded in PHINodesToUpdate.
1129 for (unsigned pn = 0; ; ++pn) {
1130 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1131 "Didn't find PHI entry!");
1132 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1133 Phi->addOperand(MachineOperand::
1134 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1136 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1144 SDB->SwitchCases.clear();
1148 /// Create the scheduler. If a specific scheduler was specified
1149 /// via the SchedulerRegistry, use it, otherwise select the
1150 /// one preferred by the target.
1152 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1153 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1157 RegisterScheduler::setDefault(Ctor);
1160 return Ctor(this, OptLevel);
1163 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1164 return new ScheduleHazardRecognizer();
1167 //===----------------------------------------------------------------------===//
1168 // Helper functions used by the generated instruction selector.
1169 //===----------------------------------------------------------------------===//
1170 // Calls to these methods are generated by tblgen.
1172 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1173 /// the dag combiner simplified the 255, we still want to match. RHS is the
1174 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1175 /// specified in the .td file (e.g. 255).
1176 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1177 int64_t DesiredMaskS) const {
1178 const APInt &ActualMask = RHS->getAPIntValue();
1179 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1181 // If the actual mask exactly matches, success!
1182 if (ActualMask == DesiredMask)
1185 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1186 if (ActualMask.intersects(~DesiredMask))
1189 // Otherwise, the DAG Combiner may have proven that the value coming in is
1190 // either already zero or is not demanded. Check for known zero input bits.
1191 APInt NeededMask = DesiredMask & ~ActualMask;
1192 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1195 // TODO: check to see if missing bits are just not demanded.
1197 // Otherwise, this pattern doesn't match.
1201 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1202 /// the dag combiner simplified the 255, we still want to match. RHS is the
1203 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1204 /// specified in the .td file (e.g. 255).
1205 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1206 int64_t DesiredMaskS) const {
1207 const APInt &ActualMask = RHS->getAPIntValue();
1208 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1210 // If the actual mask exactly matches, success!
1211 if (ActualMask == DesiredMask)
1214 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1215 if (ActualMask.intersects(~DesiredMask))
1218 // Otherwise, the DAG Combiner may have proven that the value coming in is
1219 // either already zero or is not demanded. Check for known zero input bits.
1220 APInt NeededMask = DesiredMask & ~ActualMask;
1222 APInt KnownZero, KnownOne;
1223 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1225 // If all the missing bits in the or are already known to be set, match!
1226 if ((NeededMask & KnownOne) == NeededMask)
1229 // TODO: check to see if missing bits are just not demanded.
1231 // Otherwise, this pattern doesn't match.
1236 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1237 /// by tblgen. Others should not call it.
1238 void SelectionDAGISel::
1239 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1240 std::vector<SDValue> InOps;
1241 std::swap(InOps, Ops);
1243 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1244 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1245 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1246 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
1248 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1249 if (InOps[e-1].getValueType() == MVT::Flag)
1250 --e; // Don't process a flag operand if it is here.
1253 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1254 if (!InlineAsm::isMemKind(Flags)) {
1255 // Just skip over this operand, copying the operands verbatim.
1256 Ops.insert(Ops.end(), InOps.begin()+i,
1257 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1258 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1260 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1261 "Memory operand with multiple values?");
1262 // Otherwise, this is a memory operand. Ask the target to select it.
1263 std::vector<SDValue> SelOps;
1264 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1265 report_fatal_error("Could not match memory address. Inline asm"
1268 // Add this to the output node.
1270 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1271 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1272 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1277 // Add the flag input back if present.
1278 if (e != InOps.size())
1279 Ops.push_back(InOps.back());
1282 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1285 static SDNode *findFlagUse(SDNode *N) {
1286 unsigned FlagResNo = N->getNumValues()-1;
1287 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1288 SDUse &Use = I.getUse();
1289 if (Use.getResNo() == FlagResNo)
1290 return Use.getUser();
1295 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1296 /// This function recursively traverses up the operand chain, ignoring
1298 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1299 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1300 bool IgnoreChains) {
1301 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1302 // greater than all of its (recursive) operands. If we scan to a point where
1303 // 'use' is smaller than the node we're scanning for, then we know we will
1306 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1307 // happen because we scan down to newly selected nodes in the case of flag
1309 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1312 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1313 // won't fail if we scan it again.
1314 if (!Visited.insert(Use))
1317 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1318 // Ignore chain uses, they are validated by HandleMergeInputChains.
1319 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1322 SDNode *N = Use->getOperand(i).getNode();
1324 if (Use == ImmedUse || Use == Root)
1325 continue; // We are not looking for immediate use.
1330 // Traverse up the operand chain.
1331 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1337 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1338 /// operand node N of U during instruction selection that starts at Root.
1339 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1340 SDNode *Root) const {
1341 if (OptLevel == CodeGenOpt::None) return false;
1342 return N.hasOneUse();
1345 /// IsLegalToFold - Returns true if the specific operand node N of
1346 /// U can be folded during instruction selection that starts at Root.
1347 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1348 CodeGenOpt::Level OptLevel,
1349 bool IgnoreChains) {
1350 if (OptLevel == CodeGenOpt::None) return false;
1352 // If Root use can somehow reach N through a path that that doesn't contain
1353 // U then folding N would create a cycle. e.g. In the following
1354 // diagram, Root can reach N through X. If N is folded into into Root, then
1355 // X is both a predecessor and a successor of U.
1366 // * indicates nodes to be folded together.
1368 // If Root produces a flag, then it gets (even more) interesting. Since it
1369 // will be "glued" together with its flag use in the scheduler, we need to
1370 // check if it might reach N.
1389 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1390 // (call it Fold), then X is a predecessor of FU and a successor of
1391 // Fold. But since Fold and FU are flagged together, this will create
1392 // a cycle in the scheduling graph.
1394 // If the node has flags, walk down the graph to the "lowest" node in the
1396 EVT VT = Root->getValueType(Root->getNumValues()-1);
1397 while (VT == MVT::Flag) {
1398 SDNode *FU = findFlagUse(Root);
1402 VT = Root->getValueType(Root->getNumValues()-1);
1404 // If our query node has a flag result with a use, we've walked up it. If
1405 // the user (which has already been selected) has a chain or indirectly uses
1406 // the chain, our WalkChainUsers predicate will not consider it. Because of
1407 // this, we cannot ignore chains in this predicate.
1408 IgnoreChains = false;
1412 SmallPtrSet<SDNode*, 16> Visited;
1413 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1416 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1417 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1418 SelectInlineAsmMemoryOperands(Ops);
1420 std::vector<EVT> VTs;
1421 VTs.push_back(MVT::Other);
1422 VTs.push_back(MVT::Flag);
1423 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1424 VTs, &Ops[0], Ops.size());
1426 return New.getNode();
1429 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1430 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1433 /// GetVBR - decode a vbr encoding whose top bit is set.
1434 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1435 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1436 assert(Val >= 128 && "Not a VBR");
1437 Val &= 127; // Remove first vbr bit.
1442 NextBits = MatcherTable[Idx++];
1443 Val |= (NextBits&127) << Shift;
1445 } while (NextBits & 128);
1451 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1452 /// interior flag and chain results to use the new flag and chain results.
1453 void SelectionDAGISel::
1454 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1455 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1457 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1458 bool isMorphNodeTo) {
1459 SmallVector<SDNode*, 4> NowDeadNodes;
1461 ISelUpdater ISU(ISelPosition);
1463 // Now that all the normal results are replaced, we replace the chain and
1464 // flag results if present.
1465 if (!ChainNodesMatched.empty()) {
1466 assert(InputChain.getNode() != 0 &&
1467 "Matched input chains but didn't produce a chain");
1468 // Loop over all of the nodes we matched that produced a chain result.
1469 // Replace all the chain results with the final chain we ended up with.
1470 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1471 SDNode *ChainNode = ChainNodesMatched[i];
1473 // If this node was already deleted, don't look at it.
1474 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1477 // Don't replace the results of the root node if we're doing a
1479 if (ChainNode == NodeToMatch && isMorphNodeTo)
1482 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1483 if (ChainVal.getValueType() == MVT::Flag)
1484 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1485 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1486 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1488 // If the node became dead and we haven't already seen it, delete it.
1489 if (ChainNode->use_empty() &&
1490 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1491 NowDeadNodes.push_back(ChainNode);
1495 // If the result produces a flag, update any flag results in the matched
1496 // pattern with the flag result.
1497 if (InputFlag.getNode() != 0) {
1498 // Handle any interior nodes explicitly marked.
1499 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1500 SDNode *FRN = FlagResultNodesMatched[i];
1502 // If this node was already deleted, don't look at it.
1503 if (FRN->getOpcode() == ISD::DELETED_NODE)
1506 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1507 "Doesn't have a flag result");
1508 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1511 // If the node became dead and we haven't already seen it, delete it.
1512 if (FRN->use_empty() &&
1513 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1514 NowDeadNodes.push_back(FRN);
1518 if (!NowDeadNodes.empty())
1519 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1521 DEBUG(errs() << "ISEL: Match complete!\n");
1527 CR_LeadsToInteriorNode
1530 /// WalkChainUsers - Walk down the users of the specified chained node that is
1531 /// part of the pattern we're matching, looking at all of the users we find.
1532 /// This determines whether something is an interior node, whether we have a
1533 /// non-pattern node in between two pattern nodes (which prevent folding because
1534 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1535 /// between pattern nodes (in which case the TF becomes part of the pattern).
1537 /// The walk we do here is guaranteed to be small because we quickly get down to
1538 /// already selected nodes "below" us.
1540 WalkChainUsers(SDNode *ChainedNode,
1541 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1542 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1543 ChainResult Result = CR_Simple;
1545 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1546 E = ChainedNode->use_end(); UI != E; ++UI) {
1547 // Make sure the use is of the chain, not some other value we produce.
1548 if (UI.getUse().getValueType() != MVT::Other) continue;
1552 // If we see an already-selected machine node, then we've gone beyond the
1553 // pattern that we're selecting down into the already selected chunk of the
1555 if (User->isMachineOpcode() ||
1556 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1559 if (User->getOpcode() == ISD::CopyToReg ||
1560 User->getOpcode() == ISD::CopyFromReg ||
1561 User->getOpcode() == ISD::INLINEASM ||
1562 User->getOpcode() == ISD::EH_LABEL) {
1563 // If their node ID got reset to -1 then they've already been selected.
1564 // Treat them like a MachineOpcode.
1565 if (User->getNodeId() == -1)
1569 // If we have a TokenFactor, we handle it specially.
1570 if (User->getOpcode() != ISD::TokenFactor) {
1571 // If the node isn't a token factor and isn't part of our pattern, then it
1572 // must be a random chained node in between two nodes we're selecting.
1573 // This happens when we have something like:
1578 // Because we structurally match the load/store as a read/modify/write,
1579 // but the call is chained between them. We cannot fold in this case
1580 // because it would induce a cycle in the graph.
1581 if (!std::count(ChainedNodesInPattern.begin(),
1582 ChainedNodesInPattern.end(), User))
1583 return CR_InducesCycle;
1585 // Otherwise we found a node that is part of our pattern. For example in:
1589 // This would happen when we're scanning down from the load and see the
1590 // store as a user. Record that there is a use of ChainedNode that is
1591 // part of the pattern and keep scanning uses.
1592 Result = CR_LeadsToInteriorNode;
1593 InteriorChainedNodes.push_back(User);
1597 // If we found a TokenFactor, there are two cases to consider: first if the
1598 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1599 // uses of the TF are in our pattern) we just want to ignore it. Second,
1600 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1606 // | \ DAG's like cheese
1609 // [TokenFactor] [Op]
1616 // In this case, the TokenFactor becomes part of our match and we rewrite it
1617 // as a new TokenFactor.
1619 // To distinguish these two cases, do a recursive walk down the uses.
1620 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1622 // If the uses of the TokenFactor are just already-selected nodes, ignore
1623 // it, it is "below" our pattern.
1625 case CR_InducesCycle:
1626 // If the uses of the TokenFactor lead to nodes that are not part of our
1627 // pattern that are not selected, folding would turn this into a cycle,
1629 return CR_InducesCycle;
1630 case CR_LeadsToInteriorNode:
1631 break; // Otherwise, keep processing.
1634 // Okay, we know we're in the interesting interior case. The TokenFactor
1635 // is now going to be considered part of the pattern so that we rewrite its
1636 // uses (it may have uses that are not part of the pattern) with the
1637 // ultimate chain result of the generated code. We will also add its chain
1638 // inputs as inputs to the ultimate TokenFactor we create.
1639 Result = CR_LeadsToInteriorNode;
1640 ChainedNodesInPattern.push_back(User);
1641 InteriorChainedNodes.push_back(User);
1648 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1649 /// operation for when the pattern matched at least one node with a chains. The
1650 /// input vector contains a list of all of the chained nodes that we match. We
1651 /// must determine if this is a valid thing to cover (i.e. matching it won't
1652 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1653 /// be used as the input node chain for the generated nodes.
1655 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1656 SelectionDAG *CurDAG) {
1657 // Walk all of the chained nodes we've matched, recursively scanning down the
1658 // users of the chain result. This adds any TokenFactor nodes that are caught
1659 // in between chained nodes to the chained and interior nodes list.
1660 SmallVector<SDNode*, 3> InteriorChainedNodes;
1661 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1662 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1663 InteriorChainedNodes) == CR_InducesCycle)
1664 return SDValue(); // Would induce a cycle.
1667 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1668 // that we are interested in. Form our input TokenFactor node.
1669 SmallVector<SDValue, 3> InputChains;
1670 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1671 // Add the input chain of this node to the InputChains list (which will be
1672 // the operands of the generated TokenFactor) if it's not an interior node.
1673 SDNode *N = ChainNodesMatched[i];
1674 if (N->getOpcode() != ISD::TokenFactor) {
1675 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1678 // Otherwise, add the input chain.
1679 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1680 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1681 InputChains.push_back(InChain);
1685 // If we have a token factor, we want to add all inputs of the token factor
1686 // that are not part of the pattern we're matching.
1687 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1688 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1689 N->getOperand(op).getNode()))
1690 InputChains.push_back(N->getOperand(op));
1695 if (InputChains.size() == 1)
1696 return InputChains[0];
1697 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1698 MVT::Other, &InputChains[0], InputChains.size());
1701 /// MorphNode - Handle morphing a node in place for the selector.
1702 SDNode *SelectionDAGISel::
1703 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1704 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1705 // It is possible we're using MorphNodeTo to replace a node with no
1706 // normal results with one that has a normal result (or we could be
1707 // adding a chain) and the input could have flags and chains as well.
1708 // In this case we need to shift the operands down.
1709 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1710 // than the old isel though.
1711 int OldFlagResultNo = -1, OldChainResultNo = -1;
1713 unsigned NTMNumResults = Node->getNumValues();
1714 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1715 OldFlagResultNo = NTMNumResults-1;
1716 if (NTMNumResults != 1 &&
1717 Node->getValueType(NTMNumResults-2) == MVT::Other)
1718 OldChainResultNo = NTMNumResults-2;
1719 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1720 OldChainResultNo = NTMNumResults-1;
1722 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1723 // that this deletes operands of the old node that become dead.
1724 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1726 // MorphNodeTo can operate in two ways: if an existing node with the
1727 // specified operands exists, it can just return it. Otherwise, it
1728 // updates the node in place to have the requested operands.
1730 // If we updated the node in place, reset the node ID. To the isel,
1731 // this should be just like a newly allocated machine node.
1735 unsigned ResNumResults = Res->getNumValues();
1736 // Move the flag if needed.
1737 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1738 (unsigned)OldFlagResultNo != ResNumResults-1)
1739 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1740 SDValue(Res, ResNumResults-1));
1742 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1745 // Move the chain reference if needed.
1746 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1747 (unsigned)OldChainResultNo != ResNumResults-1)
1748 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1749 SDValue(Res, ResNumResults-1));
1751 // Otherwise, no replacement happened because the node already exists. Replace
1752 // Uses of the old node with the new one.
1754 CurDAG->ReplaceAllUsesWith(Node, Res);
1759 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1760 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1761 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1763 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1764 // Accept if it is exactly the same as a previously recorded node.
1765 unsigned RecNo = MatcherTable[MatcherIndex++];
1766 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1767 return N == RecordedNodes[RecNo].first;
1770 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1771 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1772 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1773 SelectionDAGISel &SDISel) {
1774 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1777 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1778 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1779 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1780 SelectionDAGISel &SDISel, SDNode *N) {
1781 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1784 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1785 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1787 uint16_t Opc = MatcherTable[MatcherIndex++];
1788 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1789 return N->getOpcode() == Opc;
1792 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1793 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1794 SDValue N, const TargetLowering &TLI) {
1795 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1796 if (N.getValueType() == VT) return true;
1798 // Handle the case when VT is iPTR.
1799 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1802 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1803 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1804 SDValue N, const TargetLowering &TLI,
1806 if (ChildNo >= N.getNumOperands())
1807 return false; // Match fails if out of range child #.
1808 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1812 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1813 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1815 return cast<CondCodeSDNode>(N)->get() ==
1816 (ISD::CondCode)MatcherTable[MatcherIndex++];
1819 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1820 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1821 SDValue N, const TargetLowering &TLI) {
1822 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1823 if (cast<VTSDNode>(N)->getVT() == VT)
1826 // Handle the case when VT is iPTR.
1827 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1830 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1831 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1833 int64_t Val = MatcherTable[MatcherIndex++];
1835 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1837 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1838 return C != 0 && C->getSExtValue() == Val;
1841 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1842 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1843 SDValue N, SelectionDAGISel &SDISel) {
1844 int64_t Val = MatcherTable[MatcherIndex++];
1846 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1848 if (N->getOpcode() != ISD::AND) return false;
1850 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1851 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1854 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1855 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1856 SDValue N, SelectionDAGISel &SDISel) {
1857 int64_t Val = MatcherTable[MatcherIndex++];
1859 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1861 if (N->getOpcode() != ISD::OR) return false;
1863 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1864 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1867 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1868 /// scope, evaluate the current node. If the current predicate is known to
1869 /// fail, set Result=true and return anything. If the current predicate is
1870 /// known to pass, set Result=false and return the MatcherIndex to continue
1871 /// with. If the current predicate is unknown, set Result=false and return the
1872 /// MatcherIndex to continue with.
1873 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1874 unsigned Index, SDValue N,
1875 bool &Result, SelectionDAGISel &SDISel,
1876 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1877 switch (Table[Index++]) {
1880 return Index-1; // Could not evaluate this predicate.
1881 case SelectionDAGISel::OPC_CheckSame:
1882 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1884 case SelectionDAGISel::OPC_CheckPatternPredicate:
1885 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1887 case SelectionDAGISel::OPC_CheckPredicate:
1888 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1890 case SelectionDAGISel::OPC_CheckOpcode:
1891 Result = !::CheckOpcode(Table, Index, N.getNode());
1893 case SelectionDAGISel::OPC_CheckType:
1894 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1896 case SelectionDAGISel::OPC_CheckChild0Type:
1897 case SelectionDAGISel::OPC_CheckChild1Type:
1898 case SelectionDAGISel::OPC_CheckChild2Type:
1899 case SelectionDAGISel::OPC_CheckChild3Type:
1900 case SelectionDAGISel::OPC_CheckChild4Type:
1901 case SelectionDAGISel::OPC_CheckChild5Type:
1902 case SelectionDAGISel::OPC_CheckChild6Type:
1903 case SelectionDAGISel::OPC_CheckChild7Type:
1904 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1905 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1907 case SelectionDAGISel::OPC_CheckCondCode:
1908 Result = !::CheckCondCode(Table, Index, N);
1910 case SelectionDAGISel::OPC_CheckValueType:
1911 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1913 case SelectionDAGISel::OPC_CheckInteger:
1914 Result = !::CheckInteger(Table, Index, N);
1916 case SelectionDAGISel::OPC_CheckAndImm:
1917 Result = !::CheckAndImm(Table, Index, N, SDISel);
1919 case SelectionDAGISel::OPC_CheckOrImm:
1920 Result = !::CheckOrImm(Table, Index, N, SDISel);
1928 /// FailIndex - If this match fails, this is the index to continue with.
1931 /// NodeStack - The node stack when the scope was formed.
1932 SmallVector<SDValue, 4> NodeStack;
1934 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1935 unsigned NumRecordedNodes;
1937 /// NumMatchedMemRefs - The number of matched memref entries.
1938 unsigned NumMatchedMemRefs;
1940 /// InputChain/InputFlag - The current chain/flag
1941 SDValue InputChain, InputFlag;
1943 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1944 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1949 SDNode *SelectionDAGISel::
1950 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1951 unsigned TableSize) {
1952 // FIXME: Should these even be selected? Handle these cases in the caller?
1953 switch (NodeToMatch->getOpcode()) {
1956 case ISD::EntryToken: // These nodes remain the same.
1957 case ISD::BasicBlock:
1959 //case ISD::VALUETYPE:
1960 //case ISD::CONDCODE:
1961 case ISD::HANDLENODE:
1962 case ISD::MDNODE_SDNODE:
1963 case ISD::TargetConstant:
1964 case ISD::TargetConstantFP:
1965 case ISD::TargetConstantPool:
1966 case ISD::TargetFrameIndex:
1967 case ISD::TargetExternalSymbol:
1968 case ISD::TargetBlockAddress:
1969 case ISD::TargetJumpTable:
1970 case ISD::TargetGlobalTLSAddress:
1971 case ISD::TargetGlobalAddress:
1972 case ISD::TokenFactor:
1973 case ISD::CopyFromReg:
1974 case ISD::CopyToReg:
1976 NodeToMatch->setNodeId(-1); // Mark selected.
1978 case ISD::AssertSext:
1979 case ISD::AssertZext:
1980 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1981 NodeToMatch->getOperand(0));
1983 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1984 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1987 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1989 // Set up the node stack with NodeToMatch as the only node on the stack.
1990 SmallVector<SDValue, 8> NodeStack;
1991 SDValue N = SDValue(NodeToMatch, 0);
1992 NodeStack.push_back(N);
1994 // MatchScopes - Scopes used when matching, if a match failure happens, this
1995 // indicates where to continue checking.
1996 SmallVector<MatchScope, 8> MatchScopes;
1998 // RecordedNodes - This is the set of nodes that have been recorded by the
1999 // state machine. The second value is the parent of the node, or null if the
2000 // root is recorded.
2001 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2003 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2005 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2007 // These are the current input chain and flag for use when generating nodes.
2008 // Various Emit operations change these. For example, emitting a copytoreg
2009 // uses and updates these.
2010 SDValue InputChain, InputFlag;
2012 // ChainNodesMatched - If a pattern matches nodes that have input/output
2013 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2014 // which ones they are. The result is captured into this list so that we can
2015 // update the chain results when the pattern is complete.
2016 SmallVector<SDNode*, 3> ChainNodesMatched;
2017 SmallVector<SDNode*, 3> FlagResultNodesMatched;
2019 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2020 NodeToMatch->dump(CurDAG);
2023 // Determine where to start the interpreter. Normally we start at opcode #0,
2024 // but if the state machine starts with an OPC_SwitchOpcode, then we
2025 // accelerate the first lookup (which is guaranteed to be hot) with the
2026 // OpcodeOffset table.
2027 unsigned MatcherIndex = 0;
2029 if (!OpcodeOffset.empty()) {
2030 // Already computed the OpcodeOffset table, just index into it.
2031 if (N.getOpcode() < OpcodeOffset.size())
2032 MatcherIndex = OpcodeOffset[N.getOpcode()];
2033 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2035 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2036 // Otherwise, the table isn't computed, but the state machine does start
2037 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2038 // is the first time we're selecting an instruction.
2041 // Get the size of this case.
2042 unsigned CaseSize = MatcherTable[Idx++];
2044 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2045 if (CaseSize == 0) break;
2047 // Get the opcode, add the index to the table.
2048 uint16_t Opc = MatcherTable[Idx++];
2049 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2050 if (Opc >= OpcodeOffset.size())
2051 OpcodeOffset.resize((Opc+1)*2);
2052 OpcodeOffset[Opc] = Idx;
2056 // Okay, do the lookup for the first opcode.
2057 if (N.getOpcode() < OpcodeOffset.size())
2058 MatcherIndex = OpcodeOffset[N.getOpcode()];
2062 assert(MatcherIndex < TableSize && "Invalid index");
2064 unsigned CurrentOpcodeIndex = MatcherIndex;
2066 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2069 // Okay, the semantics of this operation are that we should push a scope
2070 // then evaluate the first child. However, pushing a scope only to have
2071 // the first check fail (which then pops it) is inefficient. If we can
2072 // determine immediately that the first check (or first several) will
2073 // immediately fail, don't even bother pushing a scope for them.
2077 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2078 if (NumToSkip & 128)
2079 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2080 // Found the end of the scope with no match.
2081 if (NumToSkip == 0) {
2086 FailIndex = MatcherIndex+NumToSkip;
2088 unsigned MatcherIndexOfPredicate = MatcherIndex;
2089 (void)MatcherIndexOfPredicate; // silence warning.
2091 // If we can't evaluate this predicate without pushing a scope (e.g. if
2092 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2093 // push the scope and evaluate the full predicate chain.
2095 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2096 Result, *this, RecordedNodes);
2100 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2101 << "index " << MatcherIndexOfPredicate
2102 << ", continuing at " << FailIndex << "\n");
2103 ++NumDAGIselRetries;
2105 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2106 // move to the next case.
2107 MatcherIndex = FailIndex;
2110 // If the whole scope failed to match, bail.
2111 if (FailIndex == 0) break;
2113 // Push a MatchScope which indicates where to go if the first child fails
2115 MatchScope NewEntry;
2116 NewEntry.FailIndex = FailIndex;
2117 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2118 NewEntry.NumRecordedNodes = RecordedNodes.size();
2119 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2120 NewEntry.InputChain = InputChain;
2121 NewEntry.InputFlag = InputFlag;
2122 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2123 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2124 MatchScopes.push_back(NewEntry);
2127 case OPC_RecordNode: {
2128 // Remember this node, it may end up being an operand in the pattern.
2130 if (NodeStack.size() > 1)
2131 Parent = NodeStack[NodeStack.size()-2].getNode();
2132 RecordedNodes.push_back(std::make_pair(N, Parent));
2136 case OPC_RecordChild0: case OPC_RecordChild1:
2137 case OPC_RecordChild2: case OPC_RecordChild3:
2138 case OPC_RecordChild4: case OPC_RecordChild5:
2139 case OPC_RecordChild6: case OPC_RecordChild7: {
2140 unsigned ChildNo = Opcode-OPC_RecordChild0;
2141 if (ChildNo >= N.getNumOperands())
2142 break; // Match fails if out of range child #.
2144 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2148 case OPC_RecordMemRef:
2149 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2152 case OPC_CaptureFlagInput:
2153 // If the current node has an input flag, capture it in InputFlag.
2154 if (N->getNumOperands() != 0 &&
2155 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2156 InputFlag = N->getOperand(N->getNumOperands()-1);
2159 case OPC_MoveChild: {
2160 unsigned ChildNo = MatcherTable[MatcherIndex++];
2161 if (ChildNo >= N.getNumOperands())
2162 break; // Match fails if out of range child #.
2163 N = N.getOperand(ChildNo);
2164 NodeStack.push_back(N);
2168 case OPC_MoveParent:
2169 // Pop the current node off the NodeStack.
2170 NodeStack.pop_back();
2171 assert(!NodeStack.empty() && "Node stack imbalance!");
2172 N = NodeStack.back();
2176 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2178 case OPC_CheckPatternPredicate:
2179 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2181 case OPC_CheckPredicate:
2182 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2186 case OPC_CheckComplexPat: {
2187 unsigned CPNum = MatcherTable[MatcherIndex++];
2188 unsigned RecNo = MatcherTable[MatcherIndex++];
2189 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2190 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2191 RecordedNodes[RecNo].first, CPNum,
2196 case OPC_CheckOpcode:
2197 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2201 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2204 case OPC_SwitchOpcode: {
2205 unsigned CurNodeOpcode = N.getOpcode();
2206 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2209 // Get the size of this case.
2210 CaseSize = MatcherTable[MatcherIndex++];
2212 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2213 if (CaseSize == 0) break;
2215 uint16_t Opc = MatcherTable[MatcherIndex++];
2216 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2218 // If the opcode matches, then we will execute this case.
2219 if (CurNodeOpcode == Opc)
2222 // Otherwise, skip over this case.
2223 MatcherIndex += CaseSize;
2226 // If no cases matched, bail out.
2227 if (CaseSize == 0) break;
2229 // Otherwise, execute the case we found.
2230 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2231 << " to " << MatcherIndex << "\n");
2235 case OPC_SwitchType: {
2236 MVT CurNodeVT = N.getValueType().getSimpleVT();
2237 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2240 // Get the size of this case.
2241 CaseSize = MatcherTable[MatcherIndex++];
2243 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2244 if (CaseSize == 0) break;
2246 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2247 if (CaseVT == MVT::iPTR)
2248 CaseVT = TLI.getPointerTy();
2250 // If the VT matches, then we will execute this case.
2251 if (CurNodeVT == CaseVT)
2254 // Otherwise, skip over this case.
2255 MatcherIndex += CaseSize;
2258 // If no cases matched, bail out.
2259 if (CaseSize == 0) break;
2261 // Otherwise, execute the case we found.
2262 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2263 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2266 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2267 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2268 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2269 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2270 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2271 Opcode-OPC_CheckChild0Type))
2274 case OPC_CheckCondCode:
2275 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2277 case OPC_CheckValueType:
2278 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2280 case OPC_CheckInteger:
2281 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2283 case OPC_CheckAndImm:
2284 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2286 case OPC_CheckOrImm:
2287 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2290 case OPC_CheckFoldableChainNode: {
2291 assert(NodeStack.size() != 1 && "No parent node");
2292 // Verify that all intermediate nodes between the root and this one have
2294 bool HasMultipleUses = false;
2295 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2296 if (!NodeStack[i].hasOneUse()) {
2297 HasMultipleUses = true;
2300 if (HasMultipleUses) break;
2302 // Check to see that the target thinks this is profitable to fold and that
2303 // we can fold it without inducing cycles in the graph.
2304 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2306 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2307 NodeToMatch, OptLevel,
2308 true/*We validate our own chains*/))
2313 case OPC_EmitInteger: {
2314 MVT::SimpleValueType VT =
2315 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2316 int64_t Val = MatcherTable[MatcherIndex++];
2318 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2319 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2320 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2323 case OPC_EmitRegister: {
2324 MVT::SimpleValueType VT =
2325 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2326 unsigned RegNo = MatcherTable[MatcherIndex++];
2327 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2328 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2332 case OPC_EmitConvertToTarget: {
2333 // Convert from IMM/FPIMM to target version.
2334 unsigned RecNo = MatcherTable[MatcherIndex++];
2335 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2336 SDValue Imm = RecordedNodes[RecNo].first;
2338 if (Imm->getOpcode() == ISD::Constant) {
2339 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2340 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2341 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2342 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2343 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2346 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2350 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2351 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2352 // These are space-optimized forms of OPC_EmitMergeInputChains.
2353 assert(InputChain.getNode() == 0 &&
2354 "EmitMergeInputChains should be the first chain producing node");
2355 assert(ChainNodesMatched.empty() &&
2356 "Should only have one EmitMergeInputChains per match");
2358 // Read all of the chained nodes.
2359 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2360 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2361 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2363 // FIXME: What if other value results of the node have uses not matched
2365 if (ChainNodesMatched.back() != NodeToMatch &&
2366 !RecordedNodes[RecNo].first.hasOneUse()) {
2367 ChainNodesMatched.clear();
2371 // Merge the input chains if they are not intra-pattern references.
2372 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2374 if (InputChain.getNode() == 0)
2375 break; // Failed to merge.
2379 case OPC_EmitMergeInputChains: {
2380 assert(InputChain.getNode() == 0 &&
2381 "EmitMergeInputChains should be the first chain producing node");
2382 // This node gets a list of nodes we matched in the input that have
2383 // chains. We want to token factor all of the input chains to these nodes
2384 // together. However, if any of the input chains is actually one of the
2385 // nodes matched in this pattern, then we have an intra-match reference.
2386 // Ignore these because the newly token factored chain should not refer to
2388 unsigned NumChains = MatcherTable[MatcherIndex++];
2389 assert(NumChains != 0 && "Can't TF zero chains");
2391 assert(ChainNodesMatched.empty() &&
2392 "Should only have one EmitMergeInputChains per match");
2394 // Read all of the chained nodes.
2395 for (unsigned i = 0; i != NumChains; ++i) {
2396 unsigned RecNo = MatcherTable[MatcherIndex++];
2397 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2398 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2400 // FIXME: What if other value results of the node have uses not matched
2402 if (ChainNodesMatched.back() != NodeToMatch &&
2403 !RecordedNodes[RecNo].first.hasOneUse()) {
2404 ChainNodesMatched.clear();
2409 // If the inner loop broke out, the match fails.
2410 if (ChainNodesMatched.empty())
2413 // Merge the input chains if they are not intra-pattern references.
2414 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2416 if (InputChain.getNode() == 0)
2417 break; // Failed to merge.
2422 case OPC_EmitCopyToReg: {
2423 unsigned RecNo = MatcherTable[MatcherIndex++];
2424 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2425 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2427 if (InputChain.getNode() == 0)
2428 InputChain = CurDAG->getEntryNode();
2430 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2431 DestPhysReg, RecordedNodes[RecNo].first,
2434 InputFlag = InputChain.getValue(1);
2438 case OPC_EmitNodeXForm: {
2439 unsigned XFormNo = MatcherTable[MatcherIndex++];
2440 unsigned RecNo = MatcherTable[MatcherIndex++];
2441 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2442 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2443 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2448 case OPC_MorphNodeTo: {
2449 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2450 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2451 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2452 // Get the result VT list.
2453 unsigned NumVTs = MatcherTable[MatcherIndex++];
2454 SmallVector<EVT, 4> VTs;
2455 for (unsigned i = 0; i != NumVTs; ++i) {
2456 MVT::SimpleValueType VT =
2457 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2458 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2462 if (EmitNodeInfo & OPFL_Chain)
2463 VTs.push_back(MVT::Other);
2464 if (EmitNodeInfo & OPFL_FlagOutput)
2465 VTs.push_back(MVT::Flag);
2467 // This is hot code, so optimize the two most common cases of 1 and 2
2470 if (VTs.size() == 1)
2471 VTList = CurDAG->getVTList(VTs[0]);
2472 else if (VTs.size() == 2)
2473 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2475 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2477 // Get the operand list.
2478 unsigned NumOps = MatcherTable[MatcherIndex++];
2479 SmallVector<SDValue, 8> Ops;
2480 for (unsigned i = 0; i != NumOps; ++i) {
2481 unsigned RecNo = MatcherTable[MatcherIndex++];
2483 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2485 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2486 Ops.push_back(RecordedNodes[RecNo].first);
2489 // If there are variadic operands to add, handle them now.
2490 if (EmitNodeInfo & OPFL_VariadicInfo) {
2491 // Determine the start index to copy from.
2492 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2493 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2494 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2495 "Invalid variadic node");
2496 // Copy all of the variadic operands, not including a potential flag
2498 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2500 SDValue V = NodeToMatch->getOperand(i);
2501 if (V.getValueType() == MVT::Flag) break;
2506 // If this has chain/flag inputs, add them.
2507 if (EmitNodeInfo & OPFL_Chain)
2508 Ops.push_back(InputChain);
2509 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2510 Ops.push_back(InputFlag);
2514 if (Opcode != OPC_MorphNodeTo) {
2515 // If this is a normal EmitNode command, just create the new node and
2516 // add the results to the RecordedNodes list.
2517 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2518 VTList, Ops.data(), Ops.size());
2520 // Add all the non-flag/non-chain results to the RecordedNodes list.
2521 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2522 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2523 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2528 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2532 // If the node had chain/flag results, update our notion of the current
2534 if (EmitNodeInfo & OPFL_FlagOutput) {
2535 InputFlag = SDValue(Res, VTs.size()-1);
2536 if (EmitNodeInfo & OPFL_Chain)
2537 InputChain = SDValue(Res, VTs.size()-2);
2538 } else if (EmitNodeInfo & OPFL_Chain)
2539 InputChain = SDValue(Res, VTs.size()-1);
2541 // If the OPFL_MemRefs flag is set on this node, slap all of the
2542 // accumulated memrefs onto it.
2544 // FIXME: This is vastly incorrect for patterns with multiple outputs
2545 // instructions that access memory and for ComplexPatterns that match
2547 if (EmitNodeInfo & OPFL_MemRefs) {
2548 MachineSDNode::mmo_iterator MemRefs =
2549 MF->allocateMemRefsArray(MatchedMemRefs.size());
2550 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2551 cast<MachineSDNode>(Res)
2552 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2556 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2557 << " node: "; Res->dump(CurDAG); errs() << "\n");
2559 // If this was a MorphNodeTo then we're completely done!
2560 if (Opcode == OPC_MorphNodeTo) {
2561 // Update chain and flag uses.
2562 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2563 InputFlag, FlagResultNodesMatched, true);
2570 case OPC_MarkFlagResults: {
2571 unsigned NumNodes = MatcherTable[MatcherIndex++];
2573 // Read and remember all the flag-result nodes.
2574 for (unsigned i = 0; i != NumNodes; ++i) {
2575 unsigned RecNo = MatcherTable[MatcherIndex++];
2577 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2579 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2580 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2585 case OPC_CompleteMatch: {
2586 // The match has been completed, and any new nodes (if any) have been
2587 // created. Patch up references to the matched dag to use the newly
2589 unsigned NumResults = MatcherTable[MatcherIndex++];
2591 for (unsigned i = 0; i != NumResults; ++i) {
2592 unsigned ResSlot = MatcherTable[MatcherIndex++];
2594 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2596 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2597 SDValue Res = RecordedNodes[ResSlot].first;
2599 assert(i < NodeToMatch->getNumValues() &&
2600 NodeToMatch->getValueType(i) != MVT::Other &&
2601 NodeToMatch->getValueType(i) != MVT::Flag &&
2602 "Invalid number of results to complete!");
2603 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2604 NodeToMatch->getValueType(i) == MVT::iPTR ||
2605 Res.getValueType() == MVT::iPTR ||
2606 NodeToMatch->getValueType(i).getSizeInBits() ==
2607 Res.getValueType().getSizeInBits()) &&
2608 "invalid replacement");
2609 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2612 // If the root node defines a flag, add it to the flag nodes to update
2614 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2615 FlagResultNodesMatched.push_back(NodeToMatch);
2617 // Update chain and flag uses.
2618 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2619 InputFlag, FlagResultNodesMatched, false);
2621 assert(NodeToMatch->use_empty() &&
2622 "Didn't replace all uses of the node?");
2624 // FIXME: We just return here, which interacts correctly with SelectRoot
2625 // above. We should fix this to not return an SDNode* anymore.
2630 // If the code reached this point, then the match failed. See if there is
2631 // another child to try in the current 'Scope', otherwise pop it until we
2632 // find a case to check.
2633 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2634 ++NumDAGIselRetries;
2636 if (MatchScopes.empty()) {
2637 CannotYetSelect(NodeToMatch);
2641 // Restore the interpreter state back to the point where the scope was
2643 MatchScope &LastScope = MatchScopes.back();
2644 RecordedNodes.resize(LastScope.NumRecordedNodes);
2646 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2647 N = NodeStack.back();
2649 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2650 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2651 MatcherIndex = LastScope.FailIndex;
2653 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2655 InputChain = LastScope.InputChain;
2656 InputFlag = LastScope.InputFlag;
2657 if (!LastScope.HasChainNodesMatched)
2658 ChainNodesMatched.clear();
2659 if (!LastScope.HasFlagResultNodesMatched)
2660 FlagResultNodesMatched.clear();
2662 // Check to see what the offset is at the new MatcherIndex. If it is zero
2663 // we have reached the end of this scope, otherwise we have another child
2664 // in the current scope to try.
2665 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2666 if (NumToSkip & 128)
2667 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2669 // If we have another child in this scope to match, update FailIndex and
2671 if (NumToSkip != 0) {
2672 LastScope.FailIndex = MatcherIndex+NumToSkip;
2676 // End of this scope, pop it and try the next child in the containing
2678 MatchScopes.pop_back();
2685 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2687 raw_string_ostream Msg(msg);
2688 Msg << "Cannot yet select: ";
2690 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2691 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2692 N->getOpcode() != ISD::INTRINSIC_VOID) {
2693 N->printrFull(Msg, CurDAG);
2695 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2697 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2698 if (iid < Intrinsic::num_intrinsics)
2699 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2700 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2701 Msg << "target intrinsic %" << TII->getName(iid);
2703 Msg << "unknown intrinsic #" << iid;
2705 report_fatal_error(Msg.str());
2708 char SelectionDAGISel::ID = 0;