1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/ADT/Statistic.h"
55 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
56 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
59 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
60 cl::desc("Enable verbose messages in the \"fast\" "
61 "instruction selector"));
63 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
64 cl::desc("Enable abort calls when \"fast\" instruction fails"));
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before the post legalize types"
84 " dag combine pass"));
86 ViewISelDAGs("view-isel-dags", cl::Hidden,
87 cl::desc("Pop up a window to show isel dags as they are selected"));
89 ViewSchedDAGs("view-sched-dags", cl::Hidden,
90 cl::desc("Pop up a window to show sched dags as they are processed"));
92 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
93 cl::desc("Pop up a window to show SUnit dags after they are processed"));
95 static const bool ViewDAGCombine1 = false,
96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
97 ViewDAGCombine2 = false,
98 ViewDAGCombineLT = false,
99 ViewISelDAGs = false, ViewSchedDAGs = false,
100 ViewSUnitDAGs = false;
103 //===---------------------------------------------------------------------===//
105 /// RegisterScheduler class - Track the registration of instruction schedulers.
107 //===---------------------------------------------------------------------===//
108 MachinePassRegistry RegisterScheduler::Registry;
110 //===---------------------------------------------------------------------===//
112 /// ISHeuristic command line option for instruction schedulers.
114 //===---------------------------------------------------------------------===//
115 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
116 RegisterPassParser<RegisterScheduler> >
117 ISHeuristic("pre-RA-sched",
118 cl::init(&createDefaultScheduler),
119 cl::desc("Instruction schedulers available (before register"
122 static RegisterScheduler
123 defaultListDAGScheduler("default", "Best scheduler for the target",
124 createDefaultScheduler);
127 //===--------------------------------------------------------------------===//
128 /// createDefaultScheduler - This creates an instruction scheduler appropriate
130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
131 CodeGenOpt::Level OptLevel) {
132 const TargetLowering &TLI = IS->getTargetLowering();
134 if (OptLevel == CodeGenOpt::None)
135 return createSourceListDAGScheduler(IS, OptLevel);
136 if (TLI.getSchedulingPreference() == Sched::Latency)
137 return createTDListDAGScheduler(IS, OptLevel);
138 if (TLI.getSchedulingPreference() == Sched::RegPressure)
139 return createBURRListDAGScheduler(IS, OptLevel);
140 if (TLI.getSchedulingPreference() == Sched::Hybrid)
141 return createHybridListDAGScheduler(IS, OptLevel);
142 assert(TLI.getSchedulingPreference() == Sched::ILP &&
143 "Unknown sched type!");
144 return createILPListDAGScheduler(IS, OptLevel);
148 // EmitInstrWithCustomInserter - This method should be implemented by targets
149 // that mark instructions with the 'usesCustomInserter' flag. These
150 // instructions are special in various ways, which require special support to
151 // insert. The specified MachineInstr is created but not inserted into any
152 // basic blocks, and this method is called to expand it into a sequence of
153 // instructions, potentially also creating new basic blocks and control flow.
154 // When new basic blocks are inserted and the edges from MBB to its successors
155 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
158 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
159 MachineBasicBlock *MBB) const {
161 dbgs() << "If a target marks an instruction with "
162 "'usesCustomInserter', it must implement "
163 "TargetLowering::EmitInstrWithCustomInserter!";
169 //===----------------------------------------------------------------------===//
170 // SelectionDAGISel code
171 //===----------------------------------------------------------------------===//
173 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
174 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
175 FuncInfo(new FunctionLoweringInfo(TLI)),
176 CurDAG(new SelectionDAG(tm)),
177 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
183 SelectionDAGISel::~SelectionDAGISel() {
189 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
190 AU.addRequired<AliasAnalysis>();
191 AU.addPreserved<AliasAnalysis>();
192 AU.addRequired<GCModuleInfo>();
193 AU.addPreserved<GCModuleInfo>();
194 MachineFunctionPass::getAnalysisUsage(AU);
197 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
198 /// other function that gcc recognizes as "returning twice". This is used to
199 /// limit code-gen optimizations on the machine function.
201 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
202 static bool FunctionCallsSetJmp(const Function *F) {
203 const Module *M = F->getParent();
204 static const char *ReturnsTwiceFns[] = {
213 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
215 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
216 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
217 if (!Callee->use_empty())
218 for (Value::const_use_iterator
219 I = Callee->use_begin(), E = Callee->use_end();
221 if (const CallInst *CI = dyn_cast<CallInst>(*I))
222 if (CI->getParent()->getParent() == F)
227 #undef NUM_RETURNS_TWICE_FNS
230 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
231 // Do some sanity-checking on the command-line options.
232 assert((!EnableFastISelVerbose || EnableFastISel) &&
233 "-fast-isel-verbose requires -fast-isel");
234 assert((!EnableFastISelAbort || EnableFastISel) &&
235 "-fast-isel-abort requires -fast-isel");
237 const Function &Fn = *mf.getFunction();
238 const TargetInstrInfo &TII = *TM.getInstrInfo();
239 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
242 RegInfo = &MF->getRegInfo();
243 AA = &getAnalysis<AliasAnalysis>();
244 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
246 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
249 FuncInfo->set(Fn, *MF);
252 SelectAllBasicBlocks(Fn);
254 // If the first basic block in the function has live ins that need to be
255 // copied into vregs, emit the copies into the top of the block before
256 // emitting the code for the block.
257 MachineBasicBlock *EntryMBB = MF->begin();
258 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
260 DenseMap<unsigned, unsigned> LiveInMap;
261 if (!FuncInfo->ArgDbgValues.empty())
262 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
263 E = RegInfo->livein_end(); LI != E; ++LI)
265 LiveInMap.insert(std::make_pair(LI->first, LI->second));
267 // Insert DBG_VALUE instructions for function arguments to the entry block.
268 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
269 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
270 unsigned Reg = MI->getOperand(0).getReg();
271 if (TargetRegisterInfo::isPhysicalRegister(Reg))
272 EntryMBB->insert(EntryMBB->begin(), MI);
274 MachineInstr *Def = RegInfo->getVRegDef(Reg);
275 MachineBasicBlock::iterator InsertPos = Def;
276 // FIXME: VR def may not be in entry block.
277 Def->getParent()->insert(llvm::next(InsertPos), MI);
280 // If Reg is live-in then update debug info to track its copy in a vreg.
281 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
282 if (LDI != LiveInMap.end()) {
283 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
284 MachineBasicBlock::iterator InsertPos = Def;
285 const MDNode *Variable =
286 MI->getOperand(MI->getNumOperands()-1).getMetadata();
287 unsigned Offset = MI->getOperand(1).getImm();
288 // Def is never a terminator here, so it is ok to increment InsertPos.
289 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
290 TII.get(TargetOpcode::DBG_VALUE))
291 .addReg(LDI->second, RegState::Debug)
292 .addImm(Offset).addMetadata(Variable);
294 // If this vreg is directly copied into an exported register then
295 // that COPY instructions also need DBG_VALUE, if it is the only
296 // user of LDI->second.
297 MachineInstr *CopyUseMI = NULL;
298 for (MachineRegisterInfo::use_iterator
299 UI = RegInfo->use_begin(LDI->second);
300 MachineInstr *UseMI = UI.skipInstruction();) {
301 if (UseMI->isDebugValue()) continue;
302 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
303 CopyUseMI = UseMI; continue;
305 // Otherwise this is another use or second copy use.
306 CopyUseMI = NULL; break;
309 MachineInstr *NewMI =
310 BuildMI(*MF, CopyUseMI->getDebugLoc(),
311 TII.get(TargetOpcode::DBG_VALUE))
312 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
313 .addImm(Offset).addMetadata(Variable);
314 EntryMBB->insertAfter(CopyUseMI, NewMI);
319 // Determine if there are any calls in this machine function.
320 MachineFrameInfo *MFI = MF->getFrameInfo();
321 if (!MFI->hasCalls()) {
322 for (MachineFunction::const_iterator
323 I = MF->begin(), E = MF->end(); I != E; ++I) {
324 const MachineBasicBlock *MBB = I;
325 for (MachineBasicBlock::const_iterator
326 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
327 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
329 // Operand 1 of an inline asm instruction indicates whether the asm
330 // needs stack or not.
331 if ((II->isInlineAsm() && II->getOperand(1).getImm()) ||
332 (TID.isCall() && !TID.isReturn())) {
333 MFI->setHasCalls(true);
341 // Determine if there is a call to setjmp in the machine function.
342 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
344 // Replace forward-declared registers with the registers containing
345 // the desired value.
346 MachineRegisterInfo &MRI = MF->getRegInfo();
347 for (DenseMap<unsigned, unsigned>::iterator
348 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
350 unsigned From = I->first;
351 unsigned To = I->second;
352 // If To is also scheduled to be replaced, find what its ultimate
355 DenseMap<unsigned, unsigned>::iterator J =
356 FuncInfo->RegFixups.find(To);
361 MRI.replaceRegWith(From, To);
364 // Release function-specific state. SDB and CurDAG are already cleared
372 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
373 BasicBlock::const_iterator End,
375 // Lower all of the non-terminator instructions. If a call is emitted
376 // as a tail call, cease emitting nodes for this block. Terminators
377 // are handled below.
378 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
381 // Make sure the root of the DAG is up-to-date.
382 CurDAG->setRoot(SDB->getControlRoot());
383 HadTailCall = SDB->HasTailCall;
386 // Final step, emit the lowered DAG as machine code.
390 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
391 SmallPtrSet<SDNode*, 128> VisitedNodes;
392 SmallVector<SDNode*, 128> Worklist;
394 Worklist.push_back(CurDAG->getRoot().getNode());
401 SDNode *N = Worklist.pop_back_val();
403 // If we've already seen this node, ignore it.
404 if (!VisitedNodes.insert(N))
407 // Otherwise, add all chain operands to the worklist.
408 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
409 if (N->getOperand(i).getValueType() == MVT::Other)
410 Worklist.push_back(N->getOperand(i).getNode());
412 // If this is a CopyToReg with a vreg dest, process it.
413 if (N->getOpcode() != ISD::CopyToReg)
416 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
417 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
420 // Ignore non-scalar or non-integer values.
421 SDValue Src = N->getOperand(2);
422 EVT SrcVT = Src.getValueType();
423 if (!SrcVT.isInteger() || SrcVT.isVector())
426 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
427 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
428 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
430 // Only install this information if it tells us something.
431 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
432 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
433 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
434 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
435 FunctionLoweringInfo::LiveOutInfo &LOI =
436 FuncInfo->LiveOutRegInfo[DestReg];
437 LOI.NumSignBits = NumSignBits;
438 LOI.KnownOne = KnownOne;
439 LOI.KnownZero = KnownZero;
441 } while (!Worklist.empty());
444 void SelectionDAGISel::CodeGenAndEmitDAG() {
445 std::string GroupName;
446 if (TimePassesIsEnabled)
447 GroupName = "Instruction Selection and Scheduling";
448 std::string BlockName;
449 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
450 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
452 BlockName = MF->getFunction()->getNameStr() + ":" +
453 FuncInfo->MBB->getBasicBlock()->getNameStr();
455 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
457 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
459 // Run the DAG combiner in pre-legalize mode.
461 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
462 CurDAG->Combine(Unrestricted, *AA, OptLevel);
465 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
467 // Second step, hack on the DAG until it only uses operations and types that
468 // the target supports.
469 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
474 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
475 Changed = CurDAG->LegalizeTypes();
478 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
481 if (ViewDAGCombineLT)
482 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
484 // Run the DAG combiner in post-type-legalize mode.
486 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
487 TimePassesIsEnabled);
488 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
491 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
496 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
497 Changed = CurDAG->LegalizeVectors();
502 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
503 CurDAG->LegalizeTypes();
506 if (ViewDAGCombineLT)
507 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
509 // Run the DAG combiner in post-type-legalize mode.
511 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
512 TimePassesIsEnabled);
513 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
516 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
520 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
523 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
524 CurDAG->Legalize(OptLevel);
527 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
529 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
531 // Run the DAG combiner in post-legalize mode.
533 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
534 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
537 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
539 if (OptLevel != CodeGenOpt::None)
540 ComputeLiveOutVRegInfo();
542 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
544 // Third, instruction select all of the operations to machine code, adding the
545 // code to the MachineBasicBlock.
547 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
548 DoInstructionSelection();
551 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
553 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
555 // Schedule machine code.
556 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
558 NamedRegionTimer T("Instruction Scheduling", GroupName,
559 TimePassesIsEnabled);
560 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
563 if (ViewSUnitDAGs) Scheduler->viewGraph();
565 // Emit machine code to BB. This can change 'BB' to the last block being
568 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
570 FuncInfo->MBB = Scheduler->EmitSchedule();
571 FuncInfo->InsertPt = Scheduler->InsertPos;
574 // Free the scheduler state.
576 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
577 TimePassesIsEnabled);
581 // Free the SelectionDAG state, now that we're finished with it.
585 void SelectionDAGISel::DoInstructionSelection() {
586 DEBUG(errs() << "===== Instruction selection begins:\n");
590 // Select target instructions for the DAG.
592 // Number all nodes with a topological order and set DAGSize.
593 DAGSize = CurDAG->AssignTopologicalOrder();
595 // Create a dummy node (which is not added to allnodes), that adds
596 // a reference to the root node, preventing it from being deleted,
597 // and tracking any changes of the root.
598 HandleSDNode Dummy(CurDAG->getRoot());
599 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
602 // The AllNodes list is now topological-sorted. Visit the
603 // nodes by starting at the end of the list (the root of the
604 // graph) and preceding back toward the beginning (the entry
606 while (ISelPosition != CurDAG->allnodes_begin()) {
607 SDNode *Node = --ISelPosition;
608 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
609 // but there are currently some corner cases that it misses. Also, this
610 // makes it theoretically possible to disable the DAGCombiner.
611 if (Node->use_empty())
614 SDNode *ResNode = Select(Node);
616 // FIXME: This is pretty gross. 'Select' should be changed to not return
617 // anything at all and this code should be nuked with a tactical strike.
619 // If node should not be replaced, continue with the next one.
620 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
624 ReplaceUses(Node, ResNode);
626 // If after the replacement this node is not used any more,
627 // remove this dead node.
628 if (Node->use_empty()) { // Don't delete EntryToken, etc.
629 ISelUpdater ISU(ISelPosition);
630 CurDAG->RemoveDeadNode(Node, &ISU);
634 CurDAG->setRoot(Dummy.getValue());
637 DEBUG(errs() << "===== Instruction selection ends:\n");
639 PostprocessISelDAG();
642 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
643 /// do other setup for EH landing-pad blocks.
644 void SelectionDAGISel::PrepareEHLandingPad() {
645 // Add a label to mark the beginning of the landing pad. Deletion of the
646 // landing pad can thus be detected via the MachineModuleInfo.
647 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
649 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
650 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
653 // Mark exception register as live in.
654 unsigned Reg = TLI.getExceptionAddressRegister();
655 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
657 // Mark exception selector register as live in.
658 Reg = TLI.getExceptionSelectorRegister();
659 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
661 // FIXME: Hack around an exception handling flaw (PR1508): the personality
662 // function and list of typeids logically belong to the invoke (or, if you
663 // like, the basic block containing the invoke), and need to be associated
664 // with it in the dwarf exception handling tables. Currently however the
665 // information is provided by an intrinsic (eh.selector) that can be moved
666 // to unexpected places by the optimizers: if the unwind edge is critical,
667 // then breaking it can result in the intrinsics being in the successor of
668 // the landing pad, not the landing pad itself. This results
669 // in exceptions not being caught because no typeids are associated with
670 // the invoke. This may not be the only way things can go wrong, but it
671 // is the only way we try to work around for the moment.
672 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
673 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
675 if (Br && Br->isUnconditional()) { // Critical edge?
676 BasicBlock::const_iterator I, E;
677 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
678 if (isa<EHSelectorInst>(I))
682 // No catch info found - try to extract some from the successor.
683 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
690 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
692 // Don't try to fold volatile loads. Target has to deal with alignment
694 if (LI->isVolatile()) return false;
696 // Figure out which vreg this is going into.
697 unsigned LoadReg = FastIS->getRegForValue(LI);
698 assert(LoadReg && "Load isn't already assigned a vreg? ");
700 // Check to see what the uses of this vreg are. If it has no uses, or more
701 // than one use (at the machine instr level) then we can't fold it.
702 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
703 if (RI == RegInfo->reg_end())
706 // See if there is exactly one use of the vreg. If there are multiple uses,
707 // then the instruction got lowered to multiple machine instructions or the
708 // use of the loaded value ended up being multiple operands of the result, in
709 // either case, we can't fold this.
710 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
711 if (PostRI != RegInfo->reg_end())
714 assert(RI.getOperand().isUse() &&
715 "The only use of the vreg must be a use, we haven't emitted the def!");
717 // Ask the target to try folding the load.
718 return FastIS->TryToFoldLoad(&*RI, RI.getOperandNo(), LI);
724 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
725 // Initialize the Fast-ISel state, if needed.
726 FastISel *FastIS = 0;
728 FastIS = TLI.createFastISel(*FuncInfo);
730 // Iterate over all basic blocks in the function.
731 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
732 const BasicBlock *LLVMBB = &*I;
733 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
734 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
736 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
737 BasicBlock::const_iterator const End = LLVMBB->end();
738 BasicBlock::const_iterator BI = End;
740 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
742 // Setup an EH landing-pad block.
743 if (FuncInfo->MBB->isLandingPad())
744 PrepareEHLandingPad();
746 // Lower any arguments needed in this block if this is the entry block.
747 if (LLVMBB == &Fn.getEntryBlock())
748 LowerArguments(LLVMBB);
750 // Before doing SelectionDAG ISel, see if FastISel has been requested.
752 FastIS->startNewBlock();
754 // Emit code for any incoming arguments. This must happen before
755 // beginning FastISel on the entry block.
756 if (LLVMBB == &Fn.getEntryBlock()) {
757 CurDAG->setRoot(SDB->getControlRoot());
761 // If we inserted any instructions at the beginning, make a note of
762 // where they are, so we can be sure to emit subsequent instructions
764 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
765 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
767 FastIS->setLastLocalValue(0);
770 // Do FastISel on as many instructions as possible.
771 for (; BI != Begin; --BI) {
772 const Instruction *Inst = llvm::prior(BI);
774 // If we no longer require this instruction, skip it.
775 if (!Inst->mayWriteToMemory() &&
776 !isa<TerminatorInst>(Inst) &&
777 !isa<DbgInfoIntrinsic>(Inst) &&
778 !FuncInfo->isExportedInst(Inst))
781 // Bottom-up: reset the insert pos at the top, after any local-value
783 FastIS->recomputeInsertPt();
785 // Try to select the instruction with FastISel.
786 if (FastIS->SelectInstruction(Inst)) {
787 // If fast isel succeeded, check to see if there is a single-use
788 // non-volatile load right before the selected instruction, and see if
789 // the load is used by the instruction. If so, try to fold it.
790 const Instruction *BeforeInst = 0;
792 BeforeInst = llvm::prior(llvm::prior(BI));
793 if (BeforeInst && isa<LoadInst>(BeforeInst) &&
794 BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst &&
795 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), FastIS)) {
796 // If we succeeded, don't re-select the load.
802 // Then handle certain instructions as single-LLVM-Instruction blocks.
803 if (isa<CallInst>(Inst)) {
804 ++NumFastIselFailures;
805 if (EnableFastISelVerbose || EnableFastISelAbort) {
806 dbgs() << "FastISel missed call: ";
810 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
811 unsigned &R = FuncInfo->ValueMap[Inst];
813 R = FuncInfo->CreateRegs(Inst->getType());
816 bool HadTailCall = false;
817 SelectBasicBlock(Inst, BI, HadTailCall);
819 // If the call was emitted as a tail call, we're done with the block.
828 // Otherwise, give up on FastISel for the rest of the block.
829 // For now, be a little lenient about non-branch terminators.
830 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
831 ++NumFastIselFailures;
832 if (EnableFastISelVerbose || EnableFastISelAbort) {
833 dbgs() << "FastISel miss: ";
836 if (EnableFastISelAbort)
837 // The "fast" selector couldn't handle something and bailed.
838 // For the purpose of debugging, just abort.
839 llvm_unreachable("FastISel didn't select the entire block");
844 FastIS->recomputeInsertPt();
847 // Run SelectionDAG instruction selection on the remainder of the block
848 // not handled by FastISel. If FastISel is not run, this is the entire
851 SelectBasicBlock(Begin, BI, HadTailCall);
854 FuncInfo->PHINodesToUpdate.clear();
861 SelectionDAGISel::FinishBasicBlock() {
863 DEBUG(dbgs() << "Total amount of phi nodes to update: "
864 << FuncInfo->PHINodesToUpdate.size() << "\n";
865 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
866 dbgs() << "Node " << i << " : ("
867 << FuncInfo->PHINodesToUpdate[i].first
868 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
870 // Next, now that we know what the last MBB the LLVM BB expanded is, update
871 // PHI nodes in successors.
872 if (SDB->SwitchCases.empty() &&
873 SDB->JTCases.empty() &&
874 SDB->BitTestCases.empty()) {
875 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
876 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
877 assert(PHI->isPHI() &&
878 "This is not a machine PHI node that we are updating!");
879 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
882 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
883 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
888 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
889 // Lower header first, if it wasn't already lowered
890 if (!SDB->BitTestCases[i].Emitted) {
891 // Set the current basic block to the mbb we wish to insert the code into
892 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
893 FuncInfo->InsertPt = FuncInfo->MBB->end();
895 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
896 CurDAG->setRoot(SDB->getRoot());
901 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
902 // Set the current basic block to the mbb we wish to insert the code into
903 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
904 FuncInfo->InsertPt = FuncInfo->MBB->end();
907 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
908 SDB->BitTestCases[i].Reg,
909 SDB->BitTestCases[i].Cases[j],
912 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
913 SDB->BitTestCases[i].Reg,
914 SDB->BitTestCases[i].Cases[j],
918 CurDAG->setRoot(SDB->getRoot());
924 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
926 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
927 MachineBasicBlock *PHIBB = PHI->getParent();
928 assert(PHI->isPHI() &&
929 "This is not a machine PHI node that we are updating!");
930 // This is "default" BB. We have two jumps to it. From "header" BB and
931 // from last "case" BB.
932 if (PHIBB == SDB->BitTestCases[i].Default) {
933 PHI->addOperand(MachineOperand::
934 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
936 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
937 PHI->addOperand(MachineOperand::
938 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
940 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
943 // One of "cases" BB.
944 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
946 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
947 if (cBB->isSuccessor(PHIBB)) {
948 PHI->addOperand(MachineOperand::
949 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
951 PHI->addOperand(MachineOperand::CreateMBB(cBB));
956 SDB->BitTestCases.clear();
958 // If the JumpTable record is filled in, then we need to emit a jump table.
959 // Updating the PHI nodes is tricky in this case, since we need to determine
960 // whether the PHI is a successor of the range check MBB or the jump table MBB
961 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
962 // Lower header first, if it wasn't already lowered
963 if (!SDB->JTCases[i].first.Emitted) {
964 // Set the current basic block to the mbb we wish to insert the code into
965 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
966 FuncInfo->InsertPt = FuncInfo->MBB->end();
968 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
970 CurDAG->setRoot(SDB->getRoot());
975 // Set the current basic block to the mbb we wish to insert the code into
976 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
977 FuncInfo->InsertPt = FuncInfo->MBB->end();
979 SDB->visitJumpTable(SDB->JTCases[i].second);
980 CurDAG->setRoot(SDB->getRoot());
985 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
987 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
988 MachineBasicBlock *PHIBB = PHI->getParent();
989 assert(PHI->isPHI() &&
990 "This is not a machine PHI node that we are updating!");
991 // "default" BB. We can go there only from header BB.
992 if (PHIBB == SDB->JTCases[i].second.Default) {
994 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
997 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
999 // JT BB. Just iterate over successors here
1000 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1002 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1004 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1008 SDB->JTCases.clear();
1010 // If the switch block involved a branch to one of the actual successors, we
1011 // need to update PHI nodes in that block.
1012 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1013 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1014 assert(PHI->isPHI() &&
1015 "This is not a machine PHI node that we are updating!");
1016 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1018 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1019 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1023 // If we generated any switch lowering information, build and codegen any
1024 // additional DAGs necessary.
1025 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1026 // Set the current basic block to the mbb we wish to insert the code into
1027 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1028 FuncInfo->InsertPt = FuncInfo->MBB->end();
1030 // Determine the unique successors.
1031 SmallVector<MachineBasicBlock *, 2> Succs;
1032 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1033 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1034 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1036 // Emit the code. Note that this could result in ThisBB being split, so
1037 // we need to check for updates.
1038 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1039 CurDAG->setRoot(SDB->getRoot());
1041 CodeGenAndEmitDAG();
1042 ThisBB = FuncInfo->MBB;
1044 // Handle any PHI nodes in successors of this chunk, as if we were coming
1045 // from the original BB before switch expansion. Note that PHI nodes can
1046 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1047 // handle them the right number of times.
1048 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1049 FuncInfo->MBB = Succs[i];
1050 FuncInfo->InsertPt = FuncInfo->MBB->end();
1051 // FuncInfo->MBB may have been removed from the CFG if a branch was
1053 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1054 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1055 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1057 // This value for this PHI node is recorded in PHINodesToUpdate.
1058 for (unsigned pn = 0; ; ++pn) {
1059 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1060 "Didn't find PHI entry!");
1061 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1062 Phi->addOperand(MachineOperand::
1063 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1065 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1073 SDB->SwitchCases.clear();
1077 /// Create the scheduler. If a specific scheduler was specified
1078 /// via the SchedulerRegistry, use it, otherwise select the
1079 /// one preferred by the target.
1081 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1082 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1086 RegisterScheduler::setDefault(Ctor);
1089 return Ctor(this, OptLevel);
1092 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1093 return new ScheduleHazardRecognizer();
1096 //===----------------------------------------------------------------------===//
1097 // Helper functions used by the generated instruction selector.
1098 //===----------------------------------------------------------------------===//
1099 // Calls to these methods are generated by tblgen.
1101 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1102 /// the dag combiner simplified the 255, we still want to match. RHS is the
1103 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1104 /// specified in the .td file (e.g. 255).
1105 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1106 int64_t DesiredMaskS) const {
1107 const APInt &ActualMask = RHS->getAPIntValue();
1108 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1110 // If the actual mask exactly matches, success!
1111 if (ActualMask == DesiredMask)
1114 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1115 if (ActualMask.intersects(~DesiredMask))
1118 // Otherwise, the DAG Combiner may have proven that the value coming in is
1119 // either already zero or is not demanded. Check for known zero input bits.
1120 APInt NeededMask = DesiredMask & ~ActualMask;
1121 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1124 // TODO: check to see if missing bits are just not demanded.
1126 // Otherwise, this pattern doesn't match.
1130 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1131 /// the dag combiner simplified the 255, we still want to match. RHS is the
1132 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1133 /// specified in the .td file (e.g. 255).
1134 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1135 int64_t DesiredMaskS) const {
1136 const APInt &ActualMask = RHS->getAPIntValue();
1137 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1139 // If the actual mask exactly matches, success!
1140 if (ActualMask == DesiredMask)
1143 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1144 if (ActualMask.intersects(~DesiredMask))
1147 // Otherwise, the DAG Combiner may have proven that the value coming in is
1148 // either already zero or is not demanded. Check for known zero input bits.
1149 APInt NeededMask = DesiredMask & ~ActualMask;
1151 APInt KnownZero, KnownOne;
1152 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1154 // If all the missing bits in the or are already known to be set, match!
1155 if ((NeededMask & KnownOne) == NeededMask)
1158 // TODO: check to see if missing bits are just not demanded.
1160 // Otherwise, this pattern doesn't match.
1165 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1166 /// by tblgen. Others should not call it.
1167 void SelectionDAGISel::
1168 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1169 std::vector<SDValue> InOps;
1170 std::swap(InOps, Ops);
1172 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1173 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1174 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1175 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
1177 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1178 if (InOps[e-1].getValueType() == MVT::Flag)
1179 --e; // Don't process a flag operand if it is here.
1182 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1183 if (!InlineAsm::isMemKind(Flags)) {
1184 // Just skip over this operand, copying the operands verbatim.
1185 Ops.insert(Ops.end(), InOps.begin()+i,
1186 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1187 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1189 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1190 "Memory operand with multiple values?");
1191 // Otherwise, this is a memory operand. Ask the target to select it.
1192 std::vector<SDValue> SelOps;
1193 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1194 report_fatal_error("Could not match memory address. Inline asm"
1197 // Add this to the output node.
1199 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1200 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1201 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1206 // Add the flag input back if present.
1207 if (e != InOps.size())
1208 Ops.push_back(InOps.back());
1211 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1214 static SDNode *findFlagUse(SDNode *N) {
1215 unsigned FlagResNo = N->getNumValues()-1;
1216 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1217 SDUse &Use = I.getUse();
1218 if (Use.getResNo() == FlagResNo)
1219 return Use.getUser();
1224 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1225 /// This function recursively traverses up the operand chain, ignoring
1227 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1228 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1229 bool IgnoreChains) {
1230 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1231 // greater than all of its (recursive) operands. If we scan to a point where
1232 // 'use' is smaller than the node we're scanning for, then we know we will
1235 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1236 // happen because we scan down to newly selected nodes in the case of flag
1238 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1241 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1242 // won't fail if we scan it again.
1243 if (!Visited.insert(Use))
1246 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1247 // Ignore chain uses, they are validated by HandleMergeInputChains.
1248 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1251 SDNode *N = Use->getOperand(i).getNode();
1253 if (Use == ImmedUse || Use == Root)
1254 continue; // We are not looking for immediate use.
1259 // Traverse up the operand chain.
1260 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1266 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1267 /// operand node N of U during instruction selection that starts at Root.
1268 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1269 SDNode *Root) const {
1270 if (OptLevel == CodeGenOpt::None) return false;
1271 return N.hasOneUse();
1274 /// IsLegalToFold - Returns true if the specific operand node N of
1275 /// U can be folded during instruction selection that starts at Root.
1276 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1277 CodeGenOpt::Level OptLevel,
1278 bool IgnoreChains) {
1279 if (OptLevel == CodeGenOpt::None) return false;
1281 // If Root use can somehow reach N through a path that that doesn't contain
1282 // U then folding N would create a cycle. e.g. In the following
1283 // diagram, Root can reach N through X. If N is folded into into Root, then
1284 // X is both a predecessor and a successor of U.
1295 // * indicates nodes to be folded together.
1297 // If Root produces a flag, then it gets (even more) interesting. Since it
1298 // will be "glued" together with its flag use in the scheduler, we need to
1299 // check if it might reach N.
1318 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1319 // (call it Fold), then X is a predecessor of FU and a successor of
1320 // Fold. But since Fold and FU are flagged together, this will create
1321 // a cycle in the scheduling graph.
1323 // If the node has flags, walk down the graph to the "lowest" node in the
1325 EVT VT = Root->getValueType(Root->getNumValues()-1);
1326 while (VT == MVT::Flag) {
1327 SDNode *FU = findFlagUse(Root);
1331 VT = Root->getValueType(Root->getNumValues()-1);
1333 // If our query node has a flag result with a use, we've walked up it. If
1334 // the user (which has already been selected) has a chain or indirectly uses
1335 // the chain, our WalkChainUsers predicate will not consider it. Because of
1336 // this, we cannot ignore chains in this predicate.
1337 IgnoreChains = false;
1341 SmallPtrSet<SDNode*, 16> Visited;
1342 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1345 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1346 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1347 SelectInlineAsmMemoryOperands(Ops);
1349 std::vector<EVT> VTs;
1350 VTs.push_back(MVT::Other);
1351 VTs.push_back(MVT::Flag);
1352 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1353 VTs, &Ops[0], Ops.size());
1355 return New.getNode();
1358 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1359 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1362 /// GetVBR - decode a vbr encoding whose top bit is set.
1363 ALWAYS_INLINE static uint64_t
1364 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1365 assert(Val >= 128 && "Not a VBR");
1366 Val &= 127; // Remove first vbr bit.
1371 NextBits = MatcherTable[Idx++];
1372 Val |= (NextBits&127) << Shift;
1374 } while (NextBits & 128);
1380 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1381 /// interior flag and chain results to use the new flag and chain results.
1382 void SelectionDAGISel::
1383 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1384 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1386 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1387 bool isMorphNodeTo) {
1388 SmallVector<SDNode*, 4> NowDeadNodes;
1390 ISelUpdater ISU(ISelPosition);
1392 // Now that all the normal results are replaced, we replace the chain and
1393 // flag results if present.
1394 if (!ChainNodesMatched.empty()) {
1395 assert(InputChain.getNode() != 0 &&
1396 "Matched input chains but didn't produce a chain");
1397 // Loop over all of the nodes we matched that produced a chain result.
1398 // Replace all the chain results with the final chain we ended up with.
1399 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1400 SDNode *ChainNode = ChainNodesMatched[i];
1402 // If this node was already deleted, don't look at it.
1403 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1406 // Don't replace the results of the root node if we're doing a
1408 if (ChainNode == NodeToMatch && isMorphNodeTo)
1411 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1412 if (ChainVal.getValueType() == MVT::Flag)
1413 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1414 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1415 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1417 // If the node became dead and we haven't already seen it, delete it.
1418 if (ChainNode->use_empty() &&
1419 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1420 NowDeadNodes.push_back(ChainNode);
1424 // If the result produces a flag, update any flag results in the matched
1425 // pattern with the flag result.
1426 if (InputFlag.getNode() != 0) {
1427 // Handle any interior nodes explicitly marked.
1428 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1429 SDNode *FRN = FlagResultNodesMatched[i];
1431 // If this node was already deleted, don't look at it.
1432 if (FRN->getOpcode() == ISD::DELETED_NODE)
1435 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1436 "Doesn't have a flag result");
1437 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1440 // If the node became dead and we haven't already seen it, delete it.
1441 if (FRN->use_empty() &&
1442 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1443 NowDeadNodes.push_back(FRN);
1447 if (!NowDeadNodes.empty())
1448 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1450 DEBUG(errs() << "ISEL: Match complete!\n");
1456 CR_LeadsToInteriorNode
1459 /// WalkChainUsers - Walk down the users of the specified chained node that is
1460 /// part of the pattern we're matching, looking at all of the users we find.
1461 /// This determines whether something is an interior node, whether we have a
1462 /// non-pattern node in between two pattern nodes (which prevent folding because
1463 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1464 /// between pattern nodes (in which case the TF becomes part of the pattern).
1466 /// The walk we do here is guaranteed to be small because we quickly get down to
1467 /// already selected nodes "below" us.
1469 WalkChainUsers(SDNode *ChainedNode,
1470 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1471 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1472 ChainResult Result = CR_Simple;
1474 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1475 E = ChainedNode->use_end(); UI != E; ++UI) {
1476 // Make sure the use is of the chain, not some other value we produce.
1477 if (UI.getUse().getValueType() != MVT::Other) continue;
1481 // If we see an already-selected machine node, then we've gone beyond the
1482 // pattern that we're selecting down into the already selected chunk of the
1484 if (User->isMachineOpcode() ||
1485 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1488 if (User->getOpcode() == ISD::CopyToReg ||
1489 User->getOpcode() == ISD::CopyFromReg ||
1490 User->getOpcode() == ISD::INLINEASM ||
1491 User->getOpcode() == ISD::EH_LABEL) {
1492 // If their node ID got reset to -1 then they've already been selected.
1493 // Treat them like a MachineOpcode.
1494 if (User->getNodeId() == -1)
1498 // If we have a TokenFactor, we handle it specially.
1499 if (User->getOpcode() != ISD::TokenFactor) {
1500 // If the node isn't a token factor and isn't part of our pattern, then it
1501 // must be a random chained node in between two nodes we're selecting.
1502 // This happens when we have something like:
1507 // Because we structurally match the load/store as a read/modify/write,
1508 // but the call is chained between them. We cannot fold in this case
1509 // because it would induce a cycle in the graph.
1510 if (!std::count(ChainedNodesInPattern.begin(),
1511 ChainedNodesInPattern.end(), User))
1512 return CR_InducesCycle;
1514 // Otherwise we found a node that is part of our pattern. For example in:
1518 // This would happen when we're scanning down from the load and see the
1519 // store as a user. Record that there is a use of ChainedNode that is
1520 // part of the pattern and keep scanning uses.
1521 Result = CR_LeadsToInteriorNode;
1522 InteriorChainedNodes.push_back(User);
1526 // If we found a TokenFactor, there are two cases to consider: first if the
1527 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1528 // uses of the TF are in our pattern) we just want to ignore it. Second,
1529 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1535 // | \ DAG's like cheese
1538 // [TokenFactor] [Op]
1545 // In this case, the TokenFactor becomes part of our match and we rewrite it
1546 // as a new TokenFactor.
1548 // To distinguish these two cases, do a recursive walk down the uses.
1549 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1551 // If the uses of the TokenFactor are just already-selected nodes, ignore
1552 // it, it is "below" our pattern.
1554 case CR_InducesCycle:
1555 // If the uses of the TokenFactor lead to nodes that are not part of our
1556 // pattern that are not selected, folding would turn this into a cycle,
1558 return CR_InducesCycle;
1559 case CR_LeadsToInteriorNode:
1560 break; // Otherwise, keep processing.
1563 // Okay, we know we're in the interesting interior case. The TokenFactor
1564 // is now going to be considered part of the pattern so that we rewrite its
1565 // uses (it may have uses that are not part of the pattern) with the
1566 // ultimate chain result of the generated code. We will also add its chain
1567 // inputs as inputs to the ultimate TokenFactor we create.
1568 Result = CR_LeadsToInteriorNode;
1569 ChainedNodesInPattern.push_back(User);
1570 InteriorChainedNodes.push_back(User);
1577 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1578 /// operation for when the pattern matched at least one node with a chains. The
1579 /// input vector contains a list of all of the chained nodes that we match. We
1580 /// must determine if this is a valid thing to cover (i.e. matching it won't
1581 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1582 /// be used as the input node chain for the generated nodes.
1584 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1585 SelectionDAG *CurDAG) {
1586 // Walk all of the chained nodes we've matched, recursively scanning down the
1587 // users of the chain result. This adds any TokenFactor nodes that are caught
1588 // in between chained nodes to the chained and interior nodes list.
1589 SmallVector<SDNode*, 3> InteriorChainedNodes;
1590 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1591 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1592 InteriorChainedNodes) == CR_InducesCycle)
1593 return SDValue(); // Would induce a cycle.
1596 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1597 // that we are interested in. Form our input TokenFactor node.
1598 SmallVector<SDValue, 3> InputChains;
1599 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1600 // Add the input chain of this node to the InputChains list (which will be
1601 // the operands of the generated TokenFactor) if it's not an interior node.
1602 SDNode *N = ChainNodesMatched[i];
1603 if (N->getOpcode() != ISD::TokenFactor) {
1604 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1607 // Otherwise, add the input chain.
1608 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1609 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1610 InputChains.push_back(InChain);
1614 // If we have a token factor, we want to add all inputs of the token factor
1615 // that are not part of the pattern we're matching.
1616 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1617 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1618 N->getOperand(op).getNode()))
1619 InputChains.push_back(N->getOperand(op));
1624 if (InputChains.size() == 1)
1625 return InputChains[0];
1626 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1627 MVT::Other, &InputChains[0], InputChains.size());
1630 /// MorphNode - Handle morphing a node in place for the selector.
1631 SDNode *SelectionDAGISel::
1632 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1633 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1634 // It is possible we're using MorphNodeTo to replace a node with no
1635 // normal results with one that has a normal result (or we could be
1636 // adding a chain) and the input could have flags and chains as well.
1637 // In this case we need to shift the operands down.
1638 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1639 // than the old isel though.
1640 int OldFlagResultNo = -1, OldChainResultNo = -1;
1642 unsigned NTMNumResults = Node->getNumValues();
1643 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1644 OldFlagResultNo = NTMNumResults-1;
1645 if (NTMNumResults != 1 &&
1646 Node->getValueType(NTMNumResults-2) == MVT::Other)
1647 OldChainResultNo = NTMNumResults-2;
1648 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1649 OldChainResultNo = NTMNumResults-1;
1651 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1652 // that this deletes operands of the old node that become dead.
1653 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1655 // MorphNodeTo can operate in two ways: if an existing node with the
1656 // specified operands exists, it can just return it. Otherwise, it
1657 // updates the node in place to have the requested operands.
1659 // If we updated the node in place, reset the node ID. To the isel,
1660 // this should be just like a newly allocated machine node.
1664 unsigned ResNumResults = Res->getNumValues();
1665 // Move the flag if needed.
1666 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1667 (unsigned)OldFlagResultNo != ResNumResults-1)
1668 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1669 SDValue(Res, ResNumResults-1));
1671 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1674 // Move the chain reference if needed.
1675 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1676 (unsigned)OldChainResultNo != ResNumResults-1)
1677 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1678 SDValue(Res, ResNumResults-1));
1680 // Otherwise, no replacement happened because the node already exists. Replace
1681 // Uses of the old node with the new one.
1683 CurDAG->ReplaceAllUsesWith(Node, Res);
1688 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1689 ALWAYS_INLINE static bool
1690 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1692 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1693 // Accept if it is exactly the same as a previously recorded node.
1694 unsigned RecNo = MatcherTable[MatcherIndex++];
1695 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1696 return N == RecordedNodes[RecNo].first;
1699 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1700 ALWAYS_INLINE static bool
1701 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1702 SelectionDAGISel &SDISel) {
1703 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1706 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1707 ALWAYS_INLINE static bool
1708 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1709 SelectionDAGISel &SDISel, SDNode *N) {
1710 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1713 ALWAYS_INLINE static bool
1714 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1716 uint16_t Opc = MatcherTable[MatcherIndex++];
1717 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1718 return N->getOpcode() == Opc;
1721 ALWAYS_INLINE static bool
1722 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1723 SDValue N, const TargetLowering &TLI) {
1724 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1725 if (N.getValueType() == VT) return true;
1727 // Handle the case when VT is iPTR.
1728 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1731 ALWAYS_INLINE static bool
1732 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1733 SDValue N, const TargetLowering &TLI,
1735 if (ChildNo >= N.getNumOperands())
1736 return false; // Match fails if out of range child #.
1737 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1741 ALWAYS_INLINE static bool
1742 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1744 return cast<CondCodeSDNode>(N)->get() ==
1745 (ISD::CondCode)MatcherTable[MatcherIndex++];
1748 ALWAYS_INLINE static bool
1749 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1750 SDValue N, const TargetLowering &TLI) {
1751 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1752 if (cast<VTSDNode>(N)->getVT() == VT)
1755 // Handle the case when VT is iPTR.
1756 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1759 ALWAYS_INLINE static bool
1760 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1762 int64_t Val = MatcherTable[MatcherIndex++];
1764 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1766 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1767 return C != 0 && C->getSExtValue() == Val;
1770 ALWAYS_INLINE static bool
1771 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1772 SDValue N, SelectionDAGISel &SDISel) {
1773 int64_t Val = MatcherTable[MatcherIndex++];
1775 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1777 if (N->getOpcode() != ISD::AND) return false;
1779 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1780 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1783 ALWAYS_INLINE static bool
1784 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1785 SDValue N, SelectionDAGISel &SDISel) {
1786 int64_t Val = MatcherTable[MatcherIndex++];
1788 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1790 if (N->getOpcode() != ISD::OR) return false;
1792 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1793 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1796 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1797 /// scope, evaluate the current node. If the current predicate is known to
1798 /// fail, set Result=true and return anything. If the current predicate is
1799 /// known to pass, set Result=false and return the MatcherIndex to continue
1800 /// with. If the current predicate is unknown, set Result=false and return the
1801 /// MatcherIndex to continue with.
1802 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1803 unsigned Index, SDValue N,
1804 bool &Result, SelectionDAGISel &SDISel,
1805 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1806 switch (Table[Index++]) {
1809 return Index-1; // Could not evaluate this predicate.
1810 case SelectionDAGISel::OPC_CheckSame:
1811 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1813 case SelectionDAGISel::OPC_CheckPatternPredicate:
1814 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1816 case SelectionDAGISel::OPC_CheckPredicate:
1817 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1819 case SelectionDAGISel::OPC_CheckOpcode:
1820 Result = !::CheckOpcode(Table, Index, N.getNode());
1822 case SelectionDAGISel::OPC_CheckType:
1823 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1825 case SelectionDAGISel::OPC_CheckChild0Type:
1826 case SelectionDAGISel::OPC_CheckChild1Type:
1827 case SelectionDAGISel::OPC_CheckChild2Type:
1828 case SelectionDAGISel::OPC_CheckChild3Type:
1829 case SelectionDAGISel::OPC_CheckChild4Type:
1830 case SelectionDAGISel::OPC_CheckChild5Type:
1831 case SelectionDAGISel::OPC_CheckChild6Type:
1832 case SelectionDAGISel::OPC_CheckChild7Type:
1833 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1834 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1836 case SelectionDAGISel::OPC_CheckCondCode:
1837 Result = !::CheckCondCode(Table, Index, N);
1839 case SelectionDAGISel::OPC_CheckValueType:
1840 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1842 case SelectionDAGISel::OPC_CheckInteger:
1843 Result = !::CheckInteger(Table, Index, N);
1845 case SelectionDAGISel::OPC_CheckAndImm:
1846 Result = !::CheckAndImm(Table, Index, N, SDISel);
1848 case SelectionDAGISel::OPC_CheckOrImm:
1849 Result = !::CheckOrImm(Table, Index, N, SDISel);
1857 /// FailIndex - If this match fails, this is the index to continue with.
1860 /// NodeStack - The node stack when the scope was formed.
1861 SmallVector<SDValue, 4> NodeStack;
1863 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1864 unsigned NumRecordedNodes;
1866 /// NumMatchedMemRefs - The number of matched memref entries.
1867 unsigned NumMatchedMemRefs;
1869 /// InputChain/InputFlag - The current chain/flag
1870 SDValue InputChain, InputFlag;
1872 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1873 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1878 SDNode *SelectionDAGISel::
1879 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1880 unsigned TableSize) {
1881 // FIXME: Should these even be selected? Handle these cases in the caller?
1882 switch (NodeToMatch->getOpcode()) {
1885 case ISD::EntryToken: // These nodes remain the same.
1886 case ISD::BasicBlock:
1888 //case ISD::VALUETYPE:
1889 //case ISD::CONDCODE:
1890 case ISD::HANDLENODE:
1891 case ISD::MDNODE_SDNODE:
1892 case ISD::TargetConstant:
1893 case ISD::TargetConstantFP:
1894 case ISD::TargetConstantPool:
1895 case ISD::TargetFrameIndex:
1896 case ISD::TargetExternalSymbol:
1897 case ISD::TargetBlockAddress:
1898 case ISD::TargetJumpTable:
1899 case ISD::TargetGlobalTLSAddress:
1900 case ISD::TargetGlobalAddress:
1901 case ISD::TokenFactor:
1902 case ISD::CopyFromReg:
1903 case ISD::CopyToReg:
1905 NodeToMatch->setNodeId(-1); // Mark selected.
1907 case ISD::AssertSext:
1908 case ISD::AssertZext:
1909 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1910 NodeToMatch->getOperand(0));
1912 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1913 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1916 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1918 // Set up the node stack with NodeToMatch as the only node on the stack.
1919 SmallVector<SDValue, 8> NodeStack;
1920 SDValue N = SDValue(NodeToMatch, 0);
1921 NodeStack.push_back(N);
1923 // MatchScopes - Scopes used when matching, if a match failure happens, this
1924 // indicates where to continue checking.
1925 SmallVector<MatchScope, 8> MatchScopes;
1927 // RecordedNodes - This is the set of nodes that have been recorded by the
1928 // state machine. The second value is the parent of the node, or null if the
1929 // root is recorded.
1930 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
1932 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1934 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1936 // These are the current input chain and flag for use when generating nodes.
1937 // Various Emit operations change these. For example, emitting a copytoreg
1938 // uses and updates these.
1939 SDValue InputChain, InputFlag;
1941 // ChainNodesMatched - If a pattern matches nodes that have input/output
1942 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1943 // which ones they are. The result is captured into this list so that we can
1944 // update the chain results when the pattern is complete.
1945 SmallVector<SDNode*, 3> ChainNodesMatched;
1946 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1948 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1949 NodeToMatch->dump(CurDAG);
1952 // Determine where to start the interpreter. Normally we start at opcode #0,
1953 // but if the state machine starts with an OPC_SwitchOpcode, then we
1954 // accelerate the first lookup (which is guaranteed to be hot) with the
1955 // OpcodeOffset table.
1956 unsigned MatcherIndex = 0;
1958 if (!OpcodeOffset.empty()) {
1959 // Already computed the OpcodeOffset table, just index into it.
1960 if (N.getOpcode() < OpcodeOffset.size())
1961 MatcherIndex = OpcodeOffset[N.getOpcode()];
1962 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1964 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1965 // Otherwise, the table isn't computed, but the state machine does start
1966 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1967 // is the first time we're selecting an instruction.
1970 // Get the size of this case.
1971 unsigned CaseSize = MatcherTable[Idx++];
1973 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1974 if (CaseSize == 0) break;
1976 // Get the opcode, add the index to the table.
1977 uint16_t Opc = MatcherTable[Idx++];
1978 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1979 if (Opc >= OpcodeOffset.size())
1980 OpcodeOffset.resize((Opc+1)*2);
1981 OpcodeOffset[Opc] = Idx;
1985 // Okay, do the lookup for the first opcode.
1986 if (N.getOpcode() < OpcodeOffset.size())
1987 MatcherIndex = OpcodeOffset[N.getOpcode()];
1991 assert(MatcherIndex < TableSize && "Invalid index");
1993 unsigned CurrentOpcodeIndex = MatcherIndex;
1995 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1998 // Okay, the semantics of this operation are that we should push a scope
1999 // then evaluate the first child. However, pushing a scope only to have
2000 // the first check fail (which then pops it) is inefficient. If we can
2001 // determine immediately that the first check (or first several) will
2002 // immediately fail, don't even bother pushing a scope for them.
2006 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2007 if (NumToSkip & 128)
2008 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2009 // Found the end of the scope with no match.
2010 if (NumToSkip == 0) {
2015 FailIndex = MatcherIndex+NumToSkip;
2017 unsigned MatcherIndexOfPredicate = MatcherIndex;
2018 (void)MatcherIndexOfPredicate; // silence warning.
2020 // If we can't evaluate this predicate without pushing a scope (e.g. if
2021 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2022 // push the scope and evaluate the full predicate chain.
2024 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2025 Result, *this, RecordedNodes);
2029 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2030 << "index " << MatcherIndexOfPredicate
2031 << ", continuing at " << FailIndex << "\n");
2032 ++NumDAGIselRetries;
2034 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2035 // move to the next case.
2036 MatcherIndex = FailIndex;
2039 // If the whole scope failed to match, bail.
2040 if (FailIndex == 0) break;
2042 // Push a MatchScope which indicates where to go if the first child fails
2044 MatchScope NewEntry;
2045 NewEntry.FailIndex = FailIndex;
2046 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2047 NewEntry.NumRecordedNodes = RecordedNodes.size();
2048 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2049 NewEntry.InputChain = InputChain;
2050 NewEntry.InputFlag = InputFlag;
2051 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2052 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2053 MatchScopes.push_back(NewEntry);
2056 case OPC_RecordNode: {
2057 // Remember this node, it may end up being an operand in the pattern.
2059 if (NodeStack.size() > 1)
2060 Parent = NodeStack[NodeStack.size()-2].getNode();
2061 RecordedNodes.push_back(std::make_pair(N, Parent));
2065 case OPC_RecordChild0: case OPC_RecordChild1:
2066 case OPC_RecordChild2: case OPC_RecordChild3:
2067 case OPC_RecordChild4: case OPC_RecordChild5:
2068 case OPC_RecordChild6: case OPC_RecordChild7: {
2069 unsigned ChildNo = Opcode-OPC_RecordChild0;
2070 if (ChildNo >= N.getNumOperands())
2071 break; // Match fails if out of range child #.
2073 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2077 case OPC_RecordMemRef:
2078 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2081 case OPC_CaptureFlagInput:
2082 // If the current node has an input flag, capture it in InputFlag.
2083 if (N->getNumOperands() != 0 &&
2084 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2085 InputFlag = N->getOperand(N->getNumOperands()-1);
2088 case OPC_MoveChild: {
2089 unsigned ChildNo = MatcherTable[MatcherIndex++];
2090 if (ChildNo >= N.getNumOperands())
2091 break; // Match fails if out of range child #.
2092 N = N.getOperand(ChildNo);
2093 NodeStack.push_back(N);
2097 case OPC_MoveParent:
2098 // Pop the current node off the NodeStack.
2099 NodeStack.pop_back();
2100 assert(!NodeStack.empty() && "Node stack imbalance!");
2101 N = NodeStack.back();
2105 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2107 case OPC_CheckPatternPredicate:
2108 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2110 case OPC_CheckPredicate:
2111 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2115 case OPC_CheckComplexPat: {
2116 unsigned CPNum = MatcherTable[MatcherIndex++];
2117 unsigned RecNo = MatcherTable[MatcherIndex++];
2118 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2119 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2120 RecordedNodes[RecNo].first, CPNum,
2125 case OPC_CheckOpcode:
2126 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2130 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2133 case OPC_SwitchOpcode: {
2134 unsigned CurNodeOpcode = N.getOpcode();
2135 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2138 // Get the size of this case.
2139 CaseSize = MatcherTable[MatcherIndex++];
2141 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2142 if (CaseSize == 0) break;
2144 uint16_t Opc = MatcherTable[MatcherIndex++];
2145 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2147 // If the opcode matches, then we will execute this case.
2148 if (CurNodeOpcode == Opc)
2151 // Otherwise, skip over this case.
2152 MatcherIndex += CaseSize;
2155 // If no cases matched, bail out.
2156 if (CaseSize == 0) break;
2158 // Otherwise, execute the case we found.
2159 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2160 << " to " << MatcherIndex << "\n");
2164 case OPC_SwitchType: {
2165 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2166 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2169 // Get the size of this case.
2170 CaseSize = MatcherTable[MatcherIndex++];
2172 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2173 if (CaseSize == 0) break;
2175 MVT::SimpleValueType CaseVT =
2176 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2177 if (CaseVT == MVT::iPTR)
2178 CaseVT = TLI.getPointerTy().SimpleTy;
2180 // If the VT matches, then we will execute this case.
2181 if (CurNodeVT == CaseVT)
2184 // Otherwise, skip over this case.
2185 MatcherIndex += CaseSize;
2188 // If no cases matched, bail out.
2189 if (CaseSize == 0) break;
2191 // Otherwise, execute the case we found.
2192 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2193 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2196 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2197 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2198 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2199 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2200 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2201 Opcode-OPC_CheckChild0Type))
2204 case OPC_CheckCondCode:
2205 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2207 case OPC_CheckValueType:
2208 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2210 case OPC_CheckInteger:
2211 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2213 case OPC_CheckAndImm:
2214 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2216 case OPC_CheckOrImm:
2217 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2220 case OPC_CheckFoldableChainNode: {
2221 assert(NodeStack.size() != 1 && "No parent node");
2222 // Verify that all intermediate nodes between the root and this one have
2224 bool HasMultipleUses = false;
2225 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2226 if (!NodeStack[i].hasOneUse()) {
2227 HasMultipleUses = true;
2230 if (HasMultipleUses) break;
2232 // Check to see that the target thinks this is profitable to fold and that
2233 // we can fold it without inducing cycles in the graph.
2234 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2236 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2237 NodeToMatch, OptLevel,
2238 true/*We validate our own chains*/))
2243 case OPC_EmitInteger: {
2244 MVT::SimpleValueType VT =
2245 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2246 int64_t Val = MatcherTable[MatcherIndex++];
2248 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2249 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2250 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2253 case OPC_EmitRegister: {
2254 MVT::SimpleValueType VT =
2255 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2256 unsigned RegNo = MatcherTable[MatcherIndex++];
2257 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2258 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2262 case OPC_EmitConvertToTarget: {
2263 // Convert from IMM/FPIMM to target version.
2264 unsigned RecNo = MatcherTable[MatcherIndex++];
2265 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2266 SDValue Imm = RecordedNodes[RecNo].first;
2268 if (Imm->getOpcode() == ISD::Constant) {
2269 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2270 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2271 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2272 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2273 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2276 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2280 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2281 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2282 // These are space-optimized forms of OPC_EmitMergeInputChains.
2283 assert(InputChain.getNode() == 0 &&
2284 "EmitMergeInputChains should be the first chain producing node");
2285 assert(ChainNodesMatched.empty() &&
2286 "Should only have one EmitMergeInputChains per match");
2288 // Read all of the chained nodes.
2289 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2290 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2291 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2293 // FIXME: What if other value results of the node have uses not matched
2295 if (ChainNodesMatched.back() != NodeToMatch &&
2296 !RecordedNodes[RecNo].first.hasOneUse()) {
2297 ChainNodesMatched.clear();
2301 // Merge the input chains if they are not intra-pattern references.
2302 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2304 if (InputChain.getNode() == 0)
2305 break; // Failed to merge.
2309 case OPC_EmitMergeInputChains: {
2310 assert(InputChain.getNode() == 0 &&
2311 "EmitMergeInputChains should be the first chain producing node");
2312 // This node gets a list of nodes we matched in the input that have
2313 // chains. We want to token factor all of the input chains to these nodes
2314 // together. However, if any of the input chains is actually one of the
2315 // nodes matched in this pattern, then we have an intra-match reference.
2316 // Ignore these because the newly token factored chain should not refer to
2318 unsigned NumChains = MatcherTable[MatcherIndex++];
2319 assert(NumChains != 0 && "Can't TF zero chains");
2321 assert(ChainNodesMatched.empty() &&
2322 "Should only have one EmitMergeInputChains per match");
2324 // Read all of the chained nodes.
2325 for (unsigned i = 0; i != NumChains; ++i) {
2326 unsigned RecNo = MatcherTable[MatcherIndex++];
2327 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2328 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2330 // FIXME: What if other value results of the node have uses not matched
2332 if (ChainNodesMatched.back() != NodeToMatch &&
2333 !RecordedNodes[RecNo].first.hasOneUse()) {
2334 ChainNodesMatched.clear();
2339 // If the inner loop broke out, the match fails.
2340 if (ChainNodesMatched.empty())
2343 // Merge the input chains if they are not intra-pattern references.
2344 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2346 if (InputChain.getNode() == 0)
2347 break; // Failed to merge.
2352 case OPC_EmitCopyToReg: {
2353 unsigned RecNo = MatcherTable[MatcherIndex++];
2354 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2355 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2357 if (InputChain.getNode() == 0)
2358 InputChain = CurDAG->getEntryNode();
2360 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2361 DestPhysReg, RecordedNodes[RecNo].first,
2364 InputFlag = InputChain.getValue(1);
2368 case OPC_EmitNodeXForm: {
2369 unsigned XFormNo = MatcherTable[MatcherIndex++];
2370 unsigned RecNo = MatcherTable[MatcherIndex++];
2371 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2372 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2373 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2378 case OPC_MorphNodeTo: {
2379 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2380 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2381 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2382 // Get the result VT list.
2383 unsigned NumVTs = MatcherTable[MatcherIndex++];
2384 SmallVector<EVT, 4> VTs;
2385 for (unsigned i = 0; i != NumVTs; ++i) {
2386 MVT::SimpleValueType VT =
2387 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2388 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2392 if (EmitNodeInfo & OPFL_Chain)
2393 VTs.push_back(MVT::Other);
2394 if (EmitNodeInfo & OPFL_FlagOutput)
2395 VTs.push_back(MVT::Flag);
2397 // This is hot code, so optimize the two most common cases of 1 and 2
2400 if (VTs.size() == 1)
2401 VTList = CurDAG->getVTList(VTs[0]);
2402 else if (VTs.size() == 2)
2403 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2405 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2407 // Get the operand list.
2408 unsigned NumOps = MatcherTable[MatcherIndex++];
2409 SmallVector<SDValue, 8> Ops;
2410 for (unsigned i = 0; i != NumOps; ++i) {
2411 unsigned RecNo = MatcherTable[MatcherIndex++];
2413 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2415 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2416 Ops.push_back(RecordedNodes[RecNo].first);
2419 // If there are variadic operands to add, handle them now.
2420 if (EmitNodeInfo & OPFL_VariadicInfo) {
2421 // Determine the start index to copy from.
2422 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2423 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2424 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2425 "Invalid variadic node");
2426 // Copy all of the variadic operands, not including a potential flag
2428 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2430 SDValue V = NodeToMatch->getOperand(i);
2431 if (V.getValueType() == MVT::Flag) break;
2436 // If this has chain/flag inputs, add them.
2437 if (EmitNodeInfo & OPFL_Chain)
2438 Ops.push_back(InputChain);
2439 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2440 Ops.push_back(InputFlag);
2444 if (Opcode != OPC_MorphNodeTo) {
2445 // If this is a normal EmitNode command, just create the new node and
2446 // add the results to the RecordedNodes list.
2447 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2448 VTList, Ops.data(), Ops.size());
2450 // Add all the non-flag/non-chain results to the RecordedNodes list.
2451 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2452 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2453 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2458 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2462 // If the node had chain/flag results, update our notion of the current
2464 if (EmitNodeInfo & OPFL_FlagOutput) {
2465 InputFlag = SDValue(Res, VTs.size()-1);
2466 if (EmitNodeInfo & OPFL_Chain)
2467 InputChain = SDValue(Res, VTs.size()-2);
2468 } else if (EmitNodeInfo & OPFL_Chain)
2469 InputChain = SDValue(Res, VTs.size()-1);
2471 // If the OPFL_MemRefs flag is set on this node, slap all of the
2472 // accumulated memrefs onto it.
2474 // FIXME: This is vastly incorrect for patterns with multiple outputs
2475 // instructions that access memory and for ComplexPatterns that match
2477 if (EmitNodeInfo & OPFL_MemRefs) {
2478 MachineSDNode::mmo_iterator MemRefs =
2479 MF->allocateMemRefsArray(MatchedMemRefs.size());
2480 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2481 cast<MachineSDNode>(Res)
2482 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2486 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2487 << " node: "; Res->dump(CurDAG); errs() << "\n");
2489 // If this was a MorphNodeTo then we're completely done!
2490 if (Opcode == OPC_MorphNodeTo) {
2491 // Update chain and flag uses.
2492 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2493 InputFlag, FlagResultNodesMatched, true);
2500 case OPC_MarkFlagResults: {
2501 unsigned NumNodes = MatcherTable[MatcherIndex++];
2503 // Read and remember all the flag-result nodes.
2504 for (unsigned i = 0; i != NumNodes; ++i) {
2505 unsigned RecNo = MatcherTable[MatcherIndex++];
2507 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2509 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2510 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2515 case OPC_CompleteMatch: {
2516 // The match has been completed, and any new nodes (if any) have been
2517 // created. Patch up references to the matched dag to use the newly
2519 unsigned NumResults = MatcherTable[MatcherIndex++];
2521 for (unsigned i = 0; i != NumResults; ++i) {
2522 unsigned ResSlot = MatcherTable[MatcherIndex++];
2524 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2526 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2527 SDValue Res = RecordedNodes[ResSlot].first;
2529 assert(i < NodeToMatch->getNumValues() &&
2530 NodeToMatch->getValueType(i) != MVT::Other &&
2531 NodeToMatch->getValueType(i) != MVT::Flag &&
2532 "Invalid number of results to complete!");
2533 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2534 NodeToMatch->getValueType(i) == MVT::iPTR ||
2535 Res.getValueType() == MVT::iPTR ||
2536 NodeToMatch->getValueType(i).getSizeInBits() ==
2537 Res.getValueType().getSizeInBits()) &&
2538 "invalid replacement");
2539 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2542 // If the root node defines a flag, add it to the flag nodes to update
2544 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2545 FlagResultNodesMatched.push_back(NodeToMatch);
2547 // Update chain and flag uses.
2548 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2549 InputFlag, FlagResultNodesMatched, false);
2551 assert(NodeToMatch->use_empty() &&
2552 "Didn't replace all uses of the node?");
2554 // FIXME: We just return here, which interacts correctly with SelectRoot
2555 // above. We should fix this to not return an SDNode* anymore.
2560 // If the code reached this point, then the match failed. See if there is
2561 // another child to try in the current 'Scope', otherwise pop it until we
2562 // find a case to check.
2563 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2564 ++NumDAGIselRetries;
2566 if (MatchScopes.empty()) {
2567 CannotYetSelect(NodeToMatch);
2571 // Restore the interpreter state back to the point where the scope was
2573 MatchScope &LastScope = MatchScopes.back();
2574 RecordedNodes.resize(LastScope.NumRecordedNodes);
2576 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2577 N = NodeStack.back();
2579 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2580 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2581 MatcherIndex = LastScope.FailIndex;
2583 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2585 InputChain = LastScope.InputChain;
2586 InputFlag = LastScope.InputFlag;
2587 if (!LastScope.HasChainNodesMatched)
2588 ChainNodesMatched.clear();
2589 if (!LastScope.HasFlagResultNodesMatched)
2590 FlagResultNodesMatched.clear();
2592 // Check to see what the offset is at the new MatcherIndex. If it is zero
2593 // we have reached the end of this scope, otherwise we have another child
2594 // in the current scope to try.
2595 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2596 if (NumToSkip & 128)
2597 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2599 // If we have another child in this scope to match, update FailIndex and
2601 if (NumToSkip != 0) {
2602 LastScope.FailIndex = MatcherIndex+NumToSkip;
2606 // End of this scope, pop it and try the next child in the containing
2608 MatchScopes.pop_back();
2615 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2617 raw_string_ostream Msg(msg);
2618 Msg << "Cannot yet select: ";
2620 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2621 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2622 N->getOpcode() != ISD::INTRINSIC_VOID) {
2623 N->printrFull(Msg, CurDAG);
2625 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2627 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2628 if (iid < Intrinsic::num_intrinsics)
2629 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2630 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2631 Msg << "target intrinsic %" << TII->getName(iid);
2633 Msg << "unknown intrinsic #" << iid;
2635 report_fatal_error(Msg.str());
2638 char SelectionDAGISel::ID = 0;