1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/ADT/Statistic.h"
55 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
56 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
59 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
60 cl::desc("Enable verbose messages in the \"fast\" "
61 "instruction selector"));
63 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
64 cl::desc("Enable abort calls when \"fast\" instruction fails"));
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before the post legalize types"
84 " dag combine pass"));
86 ViewISelDAGs("view-isel-dags", cl::Hidden,
87 cl::desc("Pop up a window to show isel dags as they are selected"));
89 ViewSchedDAGs("view-sched-dags", cl::Hidden,
90 cl::desc("Pop up a window to show sched dags as they are processed"));
92 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
93 cl::desc("Pop up a window to show SUnit dags after they are processed"));
95 static const bool ViewDAGCombine1 = false,
96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
97 ViewDAGCombine2 = false,
98 ViewDAGCombineLT = false,
99 ViewISelDAGs = false, ViewSchedDAGs = false,
100 ViewSUnitDAGs = false;
103 //===---------------------------------------------------------------------===//
105 /// RegisterScheduler class - Track the registration of instruction schedulers.
107 //===---------------------------------------------------------------------===//
108 MachinePassRegistry RegisterScheduler::Registry;
110 //===---------------------------------------------------------------------===//
112 /// ISHeuristic command line option for instruction schedulers.
114 //===---------------------------------------------------------------------===//
115 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
116 RegisterPassParser<RegisterScheduler> >
117 ISHeuristic("pre-RA-sched",
118 cl::init(&createDefaultScheduler),
119 cl::desc("Instruction schedulers available (before register"
122 static RegisterScheduler
123 defaultListDAGScheduler("default", "Best scheduler for the target",
124 createDefaultScheduler);
127 //===--------------------------------------------------------------------===//
128 /// createDefaultScheduler - This creates an instruction scheduler appropriate
130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
131 CodeGenOpt::Level OptLevel) {
132 const TargetLowering &TLI = IS->getTargetLowering();
134 if (OptLevel == CodeGenOpt::None)
135 return createSourceListDAGScheduler(IS, OptLevel);
136 if (TLI.getSchedulingPreference() == Sched::Latency)
137 return createTDListDAGScheduler(IS, OptLevel);
138 if (TLI.getSchedulingPreference() == Sched::RegPressure)
139 return createBURRListDAGScheduler(IS, OptLevel);
140 if (TLI.getSchedulingPreference() == Sched::Hybrid)
141 return createHybridListDAGScheduler(IS, OptLevel);
142 assert(TLI.getSchedulingPreference() == Sched::ILP &&
143 "Unknown sched type!");
144 return createILPListDAGScheduler(IS, OptLevel);
148 // EmitInstrWithCustomInserter - This method should be implemented by targets
149 // that mark instructions with the 'usesCustomInserter' flag. These
150 // instructions are special in various ways, which require special support to
151 // insert. The specified MachineInstr is created but not inserted into any
152 // basic blocks, and this method is called to expand it into a sequence of
153 // instructions, potentially also creating new basic blocks and control flow.
154 // When new basic blocks are inserted and the edges from MBB to its successors
155 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
158 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
159 MachineBasicBlock *MBB) const {
161 dbgs() << "If a target marks an instruction with "
162 "'usesCustomInserter', it must implement "
163 "TargetLowering::EmitInstrWithCustomInserter!";
169 //===----------------------------------------------------------------------===//
170 // SelectionDAGISel code
171 //===----------------------------------------------------------------------===//
173 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
174 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
175 FuncInfo(new FunctionLoweringInfo(TLI)),
176 CurDAG(new SelectionDAG(tm)),
177 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
183 SelectionDAGISel::~SelectionDAGISel() {
189 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
190 AU.addRequired<AliasAnalysis>();
191 AU.addPreserved<AliasAnalysis>();
192 AU.addRequired<GCModuleInfo>();
193 AU.addPreserved<GCModuleInfo>();
194 MachineFunctionPass::getAnalysisUsage(AU);
197 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
198 /// other function that gcc recognizes as "returning twice". This is used to
199 /// limit code-gen optimizations on the machine function.
201 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
202 static bool FunctionCallsSetJmp(const Function *F) {
203 const Module *M = F->getParent();
204 static const char *ReturnsTwiceFns[] = {
213 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
215 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
216 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
217 if (!Callee->use_empty())
218 for (Value::const_use_iterator
219 I = Callee->use_begin(), E = Callee->use_end();
221 if (const CallInst *CI = dyn_cast<CallInst>(*I))
222 if (CI->getParent()->getParent() == F)
227 #undef NUM_RETURNS_TWICE_FNS
230 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
231 // Do some sanity-checking on the command-line options.
232 assert((!EnableFastISelVerbose || EnableFastISel) &&
233 "-fast-isel-verbose requires -fast-isel");
234 assert((!EnableFastISelAbort || EnableFastISel) &&
235 "-fast-isel-abort requires -fast-isel");
237 const Function &Fn = *mf.getFunction();
238 const TargetInstrInfo &TII = *TM.getInstrInfo();
239 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
242 RegInfo = &MF->getRegInfo();
243 AA = &getAnalysis<AliasAnalysis>();
244 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
246 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
249 FuncInfo->set(Fn, *MF);
252 SelectAllBasicBlocks(Fn);
254 // If the first basic block in the function has live ins that need to be
255 // copied into vregs, emit the copies into the top of the block before
256 // emitting the code for the block.
257 MachineBasicBlock *EntryMBB = MF->begin();
258 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
260 DenseMap<unsigned, unsigned> LiveInMap;
261 if (!FuncInfo->ArgDbgValues.empty())
262 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
263 E = RegInfo->livein_end(); LI != E; ++LI)
265 LiveInMap.insert(std::make_pair(LI->first, LI->second));
267 // Insert DBG_VALUE instructions for function arguments to the entry block.
268 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
269 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
270 unsigned Reg = MI->getOperand(0).getReg();
271 if (TargetRegisterInfo::isPhysicalRegister(Reg))
272 EntryMBB->insert(EntryMBB->begin(), MI);
274 MachineInstr *Def = RegInfo->getVRegDef(Reg);
275 MachineBasicBlock::iterator InsertPos = Def;
276 // FIXME: VR def may not be in entry block.
277 Def->getParent()->insert(llvm::next(InsertPos), MI);
280 // If Reg is live-in then update debug info to track its copy in a vreg.
281 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
282 if (LDI != LiveInMap.end()) {
283 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
284 MachineBasicBlock::iterator InsertPos = Def;
285 const MDNode *Variable =
286 MI->getOperand(MI->getNumOperands()-1).getMetadata();
287 unsigned Offset = MI->getOperand(1).getImm();
288 // Def is never a terminator here, so it is ok to increment InsertPos.
289 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
290 TII.get(TargetOpcode::DBG_VALUE))
291 .addReg(LDI->second, RegState::Debug)
292 .addImm(Offset).addMetadata(Variable);
296 // Determine if there are any calls in this machine function.
297 MachineFrameInfo *MFI = MF->getFrameInfo();
298 if (!MFI->hasCalls()) {
299 for (MachineFunction::const_iterator
300 I = MF->begin(), E = MF->end(); I != E; ++I) {
301 const MachineBasicBlock *MBB = I;
302 for (MachineBasicBlock::const_iterator
303 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
304 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
306 // Operand 1 of an inline asm instruction indicates whether the asm
307 // needs stack or not.
308 if ((II->isInlineAsm() && II->getOperand(1).getImm()) ||
309 (TID.isCall() && !TID.isReturn())) {
310 MFI->setHasCalls(true);
318 // Determine if there is a call to setjmp in the machine function.
319 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
321 // Replace forward-declared registers with the registers containing
322 // the desired value.
323 MachineRegisterInfo &MRI = MF->getRegInfo();
324 for (DenseMap<unsigned, unsigned>::iterator
325 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
327 unsigned From = I->first;
328 unsigned To = I->second;
329 // If To is also scheduled to be replaced, find what its ultimate
332 DenseMap<unsigned, unsigned>::iterator J =
333 FuncInfo->RegFixups.find(To);
338 MRI.replaceRegWith(From, To);
341 // Release function-specific state. SDB and CurDAG are already cleared
349 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
350 BasicBlock::const_iterator End,
352 // Lower all of the non-terminator instructions. If a call is emitted
353 // as a tail call, cease emitting nodes for this block. Terminators
354 // are handled below.
355 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
358 // Make sure the root of the DAG is up-to-date.
359 CurDAG->setRoot(SDB->getControlRoot());
360 HadTailCall = SDB->HasTailCall;
363 // Final step, emit the lowered DAG as machine code.
367 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
368 SmallPtrSet<SDNode*, 128> VisitedNodes;
369 SmallVector<SDNode*, 128> Worklist;
371 Worklist.push_back(CurDAG->getRoot().getNode());
378 SDNode *N = Worklist.pop_back_val();
380 // If we've already seen this node, ignore it.
381 if (!VisitedNodes.insert(N))
384 // Otherwise, add all chain operands to the worklist.
385 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
386 if (N->getOperand(i).getValueType() == MVT::Other)
387 Worklist.push_back(N->getOperand(i).getNode());
389 // If this is a CopyToReg with a vreg dest, process it.
390 if (N->getOpcode() != ISD::CopyToReg)
393 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
394 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
397 // Ignore non-scalar or non-integer values.
398 SDValue Src = N->getOperand(2);
399 EVT SrcVT = Src.getValueType();
400 if (!SrcVT.isInteger() || SrcVT.isVector())
403 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
404 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
405 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
407 // Only install this information if it tells us something.
408 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
409 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
410 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
411 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
412 FunctionLoweringInfo::LiveOutInfo &LOI =
413 FuncInfo->LiveOutRegInfo[DestReg];
414 LOI.NumSignBits = NumSignBits;
415 LOI.KnownOne = KnownOne;
416 LOI.KnownZero = KnownZero;
418 } while (!Worklist.empty());
421 void SelectionDAGISel::CodeGenAndEmitDAG() {
422 std::string GroupName;
423 if (TimePassesIsEnabled)
424 GroupName = "Instruction Selection and Scheduling";
425 std::string BlockName;
426 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
427 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
429 BlockName = MF->getFunction()->getNameStr() + ":" +
430 FuncInfo->MBB->getBasicBlock()->getNameStr();
432 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
434 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
436 // Run the DAG combiner in pre-legalize mode.
438 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
439 CurDAG->Combine(Unrestricted, *AA, OptLevel);
442 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
444 // Second step, hack on the DAG until it only uses operations and types that
445 // the target supports.
446 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
451 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
452 Changed = CurDAG->LegalizeTypes();
455 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
458 if (ViewDAGCombineLT)
459 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
461 // Run the DAG combiner in post-type-legalize mode.
463 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
464 TimePassesIsEnabled);
465 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
468 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
473 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
474 Changed = CurDAG->LegalizeVectors();
479 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
480 CurDAG->LegalizeTypes();
483 if (ViewDAGCombineLT)
484 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
486 // Run the DAG combiner in post-type-legalize mode.
488 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
489 TimePassesIsEnabled);
490 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
493 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
497 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
500 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
501 CurDAG->Legalize(OptLevel);
504 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
506 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
508 // Run the DAG combiner in post-legalize mode.
510 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
511 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
514 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
516 if (OptLevel != CodeGenOpt::None)
517 ComputeLiveOutVRegInfo();
519 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
521 // Third, instruction select all of the operations to machine code, adding the
522 // code to the MachineBasicBlock.
524 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
525 DoInstructionSelection();
528 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
530 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
532 // Schedule machine code.
533 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
535 NamedRegionTimer T("Instruction Scheduling", GroupName,
536 TimePassesIsEnabled);
537 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
540 if (ViewSUnitDAGs) Scheduler->viewGraph();
542 // Emit machine code to BB. This can change 'BB' to the last block being
545 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
547 FuncInfo->MBB = Scheduler->EmitSchedule();
548 FuncInfo->InsertPt = Scheduler->InsertPos;
551 // Free the scheduler state.
553 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
554 TimePassesIsEnabled);
558 // Free the SelectionDAG state, now that we're finished with it.
562 void SelectionDAGISel::DoInstructionSelection() {
563 DEBUG(errs() << "===== Instruction selection begins:\n");
567 // Select target instructions for the DAG.
569 // Number all nodes with a topological order and set DAGSize.
570 DAGSize = CurDAG->AssignTopologicalOrder();
572 // Create a dummy node (which is not added to allnodes), that adds
573 // a reference to the root node, preventing it from being deleted,
574 // and tracking any changes of the root.
575 HandleSDNode Dummy(CurDAG->getRoot());
576 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
579 // The AllNodes list is now topological-sorted. Visit the
580 // nodes by starting at the end of the list (the root of the
581 // graph) and preceding back toward the beginning (the entry
583 while (ISelPosition != CurDAG->allnodes_begin()) {
584 SDNode *Node = --ISelPosition;
585 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
586 // but there are currently some corner cases that it misses. Also, this
587 // makes it theoretically possible to disable the DAGCombiner.
588 if (Node->use_empty())
591 SDNode *ResNode = Select(Node);
593 // FIXME: This is pretty gross. 'Select' should be changed to not return
594 // anything at all and this code should be nuked with a tactical strike.
596 // If node should not be replaced, continue with the next one.
597 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
601 ReplaceUses(Node, ResNode);
603 // If after the replacement this node is not used any more,
604 // remove this dead node.
605 if (Node->use_empty()) { // Don't delete EntryToken, etc.
606 ISelUpdater ISU(ISelPosition);
607 CurDAG->RemoveDeadNode(Node, &ISU);
611 CurDAG->setRoot(Dummy.getValue());
614 DEBUG(errs() << "===== Instruction selection ends:\n");
616 PostprocessISelDAG();
619 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
620 /// do other setup for EH landing-pad blocks.
621 void SelectionDAGISel::PrepareEHLandingPad() {
622 // Add a label to mark the beginning of the landing pad. Deletion of the
623 // landing pad can thus be detected via the MachineModuleInfo.
624 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
626 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
627 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
630 // Mark exception register as live in.
631 unsigned Reg = TLI.getExceptionAddressRegister();
632 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
634 // Mark exception selector register as live in.
635 Reg = TLI.getExceptionSelectorRegister();
636 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
638 // FIXME: Hack around an exception handling flaw (PR1508): the personality
639 // function and list of typeids logically belong to the invoke (or, if you
640 // like, the basic block containing the invoke), and need to be associated
641 // with it in the dwarf exception handling tables. Currently however the
642 // information is provided by an intrinsic (eh.selector) that can be moved
643 // to unexpected places by the optimizers: if the unwind edge is critical,
644 // then breaking it can result in the intrinsics being in the successor of
645 // the landing pad, not the landing pad itself. This results
646 // in exceptions not being caught because no typeids are associated with
647 // the invoke. This may not be the only way things can go wrong, but it
648 // is the only way we try to work around for the moment.
649 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
650 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
652 if (Br && Br->isUnconditional()) { // Critical edge?
653 BasicBlock::const_iterator I, E;
654 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
655 if (isa<EHSelectorInst>(I))
659 // No catch info found - try to extract some from the successor.
660 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
664 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
665 // Initialize the Fast-ISel state, if needed.
666 FastISel *FastIS = 0;
668 FastIS = TLI.createFastISel(*FuncInfo);
670 // Iterate over all basic blocks in the function.
671 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
672 const BasicBlock *LLVMBB = &*I;
673 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
674 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
676 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
677 BasicBlock::const_iterator const End = LLVMBB->end();
678 BasicBlock::const_iterator BI = End;
680 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
682 // Setup an EH landing-pad block.
683 if (FuncInfo->MBB->isLandingPad())
684 PrepareEHLandingPad();
686 // Lower any arguments needed in this block if this is the entry block.
687 if (LLVMBB == &Fn.getEntryBlock())
688 LowerArguments(LLVMBB);
690 // Before doing SelectionDAG ISel, see if FastISel has been requested.
692 FastIS->startNewBlock();
694 // Emit code for any incoming arguments. This must happen before
695 // beginning FastISel on the entry block.
696 if (LLVMBB == &Fn.getEntryBlock()) {
697 CurDAG->setRoot(SDB->getControlRoot());
701 // If we inserted any instructions at the beginning, make a note of
702 // where they are, so we can be sure to emit subsequent instructions
704 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
705 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
707 FastIS->setLastLocalValue(0);
710 // Do FastISel on as many instructions as possible.
711 for (; BI != Begin; --BI) {
712 const Instruction *Inst = llvm::prior(BI);
714 // If we no longer require this instruction, skip it.
715 if (!Inst->mayWriteToMemory() &&
716 !isa<TerminatorInst>(Inst) &&
717 !isa<DbgInfoIntrinsic>(Inst) &&
718 !FuncInfo->isExportedInst(Inst))
721 // Bottom-up: reset the insert pos at the top, after any local-value
723 FastIS->recomputeInsertPt();
725 // Try to select the instruction with FastISel.
726 if (FastIS->SelectInstruction(Inst))
729 // Then handle certain instructions as single-LLVM-Instruction blocks.
730 if (isa<CallInst>(Inst)) {
731 ++NumFastIselFailures;
732 if (EnableFastISelVerbose || EnableFastISelAbort) {
733 dbgs() << "FastISel missed call: ";
737 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
738 unsigned &R = FuncInfo->ValueMap[Inst];
740 R = FuncInfo->CreateRegs(Inst->getType());
743 bool HadTailCall = false;
744 SelectBasicBlock(Inst, BI, HadTailCall);
746 // If the call was emitted as a tail call, we're done with the block.
755 // Otherwise, give up on FastISel for the rest of the block.
756 // For now, be a little lenient about non-branch terminators.
757 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
758 ++NumFastIselFailures;
759 if (EnableFastISelVerbose || EnableFastISelAbort) {
760 dbgs() << "FastISel miss: ";
763 if (EnableFastISelAbort)
764 // The "fast" selector couldn't handle something and bailed.
765 // For the purpose of debugging, just abort.
766 llvm_unreachable("FastISel didn't select the entire block");
771 FastIS->recomputeInsertPt();
774 // Run SelectionDAG instruction selection on the remainder of the block
775 // not handled by FastISel. If FastISel is not run, this is the entire
778 SelectBasicBlock(Begin, BI, HadTailCall);
781 FuncInfo->PHINodesToUpdate.clear();
788 SelectionDAGISel::FinishBasicBlock() {
790 DEBUG(dbgs() << "Total amount of phi nodes to update: "
791 << FuncInfo->PHINodesToUpdate.size() << "\n";
792 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
793 dbgs() << "Node " << i << " : ("
794 << FuncInfo->PHINodesToUpdate[i].first
795 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
797 // Next, now that we know what the last MBB the LLVM BB expanded is, update
798 // PHI nodes in successors.
799 if (SDB->SwitchCases.empty() &&
800 SDB->JTCases.empty() &&
801 SDB->BitTestCases.empty()) {
802 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
803 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
804 assert(PHI->isPHI() &&
805 "This is not a machine PHI node that we are updating!");
806 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
809 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
810 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
815 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
816 // Lower header first, if it wasn't already lowered
817 if (!SDB->BitTestCases[i].Emitted) {
818 // Set the current basic block to the mbb we wish to insert the code into
819 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
820 FuncInfo->InsertPt = FuncInfo->MBB->end();
822 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
823 CurDAG->setRoot(SDB->getRoot());
828 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
829 // Set the current basic block to the mbb we wish to insert the code into
830 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
831 FuncInfo->InsertPt = FuncInfo->MBB->end();
834 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
835 SDB->BitTestCases[i].Reg,
836 SDB->BitTestCases[i].Cases[j],
839 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
840 SDB->BitTestCases[i].Reg,
841 SDB->BitTestCases[i].Cases[j],
845 CurDAG->setRoot(SDB->getRoot());
851 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
853 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
854 MachineBasicBlock *PHIBB = PHI->getParent();
855 assert(PHI->isPHI() &&
856 "This is not a machine PHI node that we are updating!");
857 // This is "default" BB. We have two jumps to it. From "header" BB and
858 // from last "case" BB.
859 if (PHIBB == SDB->BitTestCases[i].Default) {
860 PHI->addOperand(MachineOperand::
861 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
863 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
864 PHI->addOperand(MachineOperand::
865 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
867 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
870 // One of "cases" BB.
871 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
873 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
874 if (cBB->isSuccessor(PHIBB)) {
875 PHI->addOperand(MachineOperand::
876 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
878 PHI->addOperand(MachineOperand::CreateMBB(cBB));
883 SDB->BitTestCases.clear();
885 // If the JumpTable record is filled in, then we need to emit a jump table.
886 // Updating the PHI nodes is tricky in this case, since we need to determine
887 // whether the PHI is a successor of the range check MBB or the jump table MBB
888 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
889 // Lower header first, if it wasn't already lowered
890 if (!SDB->JTCases[i].first.Emitted) {
891 // Set the current basic block to the mbb we wish to insert the code into
892 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
893 FuncInfo->InsertPt = FuncInfo->MBB->end();
895 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
897 CurDAG->setRoot(SDB->getRoot());
902 // Set the current basic block to the mbb we wish to insert the code into
903 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
904 FuncInfo->InsertPt = FuncInfo->MBB->end();
906 SDB->visitJumpTable(SDB->JTCases[i].second);
907 CurDAG->setRoot(SDB->getRoot());
912 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
914 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
915 MachineBasicBlock *PHIBB = PHI->getParent();
916 assert(PHI->isPHI() &&
917 "This is not a machine PHI node that we are updating!");
918 // "default" BB. We can go there only from header BB.
919 if (PHIBB == SDB->JTCases[i].second.Default) {
921 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
924 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
926 // JT BB. Just iterate over successors here
927 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
929 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
931 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
935 SDB->JTCases.clear();
937 // If the switch block involved a branch to one of the actual successors, we
938 // need to update PHI nodes in that block.
939 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
940 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
941 assert(PHI->isPHI() &&
942 "This is not a machine PHI node that we are updating!");
943 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
945 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
946 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
950 // If we generated any switch lowering information, build and codegen any
951 // additional DAGs necessary.
952 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
953 // Set the current basic block to the mbb we wish to insert the code into
954 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
955 FuncInfo->InsertPt = FuncInfo->MBB->end();
957 // Determine the unique successors.
958 SmallVector<MachineBasicBlock *, 2> Succs;
959 Succs.push_back(SDB->SwitchCases[i].TrueBB);
960 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
961 Succs.push_back(SDB->SwitchCases[i].FalseBB);
963 // Emit the code. Note that this could result in ThisBB being split, so
964 // we need to check for updates.
965 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
966 CurDAG->setRoot(SDB->getRoot());
969 ThisBB = FuncInfo->MBB;
971 // Handle any PHI nodes in successors of this chunk, as if we were coming
972 // from the original BB before switch expansion. Note that PHI nodes can
973 // occur multiple times in PHINodesToUpdate. We have to be very careful to
974 // handle them the right number of times.
975 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
976 FuncInfo->MBB = Succs[i];
977 FuncInfo->InsertPt = FuncInfo->MBB->end();
978 // FuncInfo->MBB may have been removed from the CFG if a branch was
980 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
981 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
982 Phi != FuncInfo->MBB->end() && Phi->isPHI();
984 // This value for this PHI node is recorded in PHINodesToUpdate.
985 for (unsigned pn = 0; ; ++pn) {
986 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
987 "Didn't find PHI entry!");
988 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
989 Phi->addOperand(MachineOperand::
990 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
992 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1000 SDB->SwitchCases.clear();
1004 /// Create the scheduler. If a specific scheduler was specified
1005 /// via the SchedulerRegistry, use it, otherwise select the
1006 /// one preferred by the target.
1008 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1009 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1013 RegisterScheduler::setDefault(Ctor);
1016 return Ctor(this, OptLevel);
1019 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1020 return new ScheduleHazardRecognizer();
1023 //===----------------------------------------------------------------------===//
1024 // Helper functions used by the generated instruction selector.
1025 //===----------------------------------------------------------------------===//
1026 // Calls to these methods are generated by tblgen.
1028 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1029 /// the dag combiner simplified the 255, we still want to match. RHS is the
1030 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1031 /// specified in the .td file (e.g. 255).
1032 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1033 int64_t DesiredMaskS) const {
1034 const APInt &ActualMask = RHS->getAPIntValue();
1035 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1037 // If the actual mask exactly matches, success!
1038 if (ActualMask == DesiredMask)
1041 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1042 if (ActualMask.intersects(~DesiredMask))
1045 // Otherwise, the DAG Combiner may have proven that the value coming in is
1046 // either already zero or is not demanded. Check for known zero input bits.
1047 APInt NeededMask = DesiredMask & ~ActualMask;
1048 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1051 // TODO: check to see if missing bits are just not demanded.
1053 // Otherwise, this pattern doesn't match.
1057 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1058 /// the dag combiner simplified the 255, we still want to match. RHS is the
1059 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1060 /// specified in the .td file (e.g. 255).
1061 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1062 int64_t DesiredMaskS) const {
1063 const APInt &ActualMask = RHS->getAPIntValue();
1064 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1066 // If the actual mask exactly matches, success!
1067 if (ActualMask == DesiredMask)
1070 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1071 if (ActualMask.intersects(~DesiredMask))
1074 // Otherwise, the DAG Combiner may have proven that the value coming in is
1075 // either already zero or is not demanded. Check for known zero input bits.
1076 APInt NeededMask = DesiredMask & ~ActualMask;
1078 APInt KnownZero, KnownOne;
1079 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1081 // If all the missing bits in the or are already known to be set, match!
1082 if ((NeededMask & KnownOne) == NeededMask)
1085 // TODO: check to see if missing bits are just not demanded.
1087 // Otherwise, this pattern doesn't match.
1092 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1093 /// by tblgen. Others should not call it.
1094 void SelectionDAGISel::
1095 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1096 std::vector<SDValue> InOps;
1097 std::swap(InOps, Ops);
1099 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1100 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1101 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1102 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
1104 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1105 if (InOps[e-1].getValueType() == MVT::Flag)
1106 --e; // Don't process a flag operand if it is here.
1109 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1110 if (!InlineAsm::isMemKind(Flags)) {
1111 // Just skip over this operand, copying the operands verbatim.
1112 Ops.insert(Ops.end(), InOps.begin()+i,
1113 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1114 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1116 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1117 "Memory operand with multiple values?");
1118 // Otherwise, this is a memory operand. Ask the target to select it.
1119 std::vector<SDValue> SelOps;
1120 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1121 report_fatal_error("Could not match memory address. Inline asm"
1124 // Add this to the output node.
1126 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1127 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1128 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1133 // Add the flag input back if present.
1134 if (e != InOps.size())
1135 Ops.push_back(InOps.back());
1138 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1141 static SDNode *findFlagUse(SDNode *N) {
1142 unsigned FlagResNo = N->getNumValues()-1;
1143 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1144 SDUse &Use = I.getUse();
1145 if (Use.getResNo() == FlagResNo)
1146 return Use.getUser();
1151 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1152 /// This function recursively traverses up the operand chain, ignoring
1154 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1155 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1156 bool IgnoreChains) {
1157 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1158 // greater than all of its (recursive) operands. If we scan to a point where
1159 // 'use' is smaller than the node we're scanning for, then we know we will
1162 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1163 // happen because we scan down to newly selected nodes in the case of flag
1165 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1168 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1169 // won't fail if we scan it again.
1170 if (!Visited.insert(Use))
1173 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1174 // Ignore chain uses, they are validated by HandleMergeInputChains.
1175 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1178 SDNode *N = Use->getOperand(i).getNode();
1180 if (Use == ImmedUse || Use == Root)
1181 continue; // We are not looking for immediate use.
1186 // Traverse up the operand chain.
1187 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1193 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1194 /// operand node N of U during instruction selection that starts at Root.
1195 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1196 SDNode *Root) const {
1197 if (OptLevel == CodeGenOpt::None) return false;
1198 return N.hasOneUse();
1201 /// IsLegalToFold - Returns true if the specific operand node N of
1202 /// U can be folded during instruction selection that starts at Root.
1203 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1204 CodeGenOpt::Level OptLevel,
1205 bool IgnoreChains) {
1206 if (OptLevel == CodeGenOpt::None) return false;
1208 // If Root use can somehow reach N through a path that that doesn't contain
1209 // U then folding N would create a cycle. e.g. In the following
1210 // diagram, Root can reach N through X. If N is folded into into Root, then
1211 // X is both a predecessor and a successor of U.
1222 // * indicates nodes to be folded together.
1224 // If Root produces a flag, then it gets (even more) interesting. Since it
1225 // will be "glued" together with its flag use in the scheduler, we need to
1226 // check if it might reach N.
1245 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1246 // (call it Fold), then X is a predecessor of FU and a successor of
1247 // Fold. But since Fold and FU are flagged together, this will create
1248 // a cycle in the scheduling graph.
1250 // If the node has flags, walk down the graph to the "lowest" node in the
1252 EVT VT = Root->getValueType(Root->getNumValues()-1);
1253 while (VT == MVT::Flag) {
1254 SDNode *FU = findFlagUse(Root);
1258 VT = Root->getValueType(Root->getNumValues()-1);
1260 // If our query node has a flag result with a use, we've walked up it. If
1261 // the user (which has already been selected) has a chain or indirectly uses
1262 // the chain, our WalkChainUsers predicate will not consider it. Because of
1263 // this, we cannot ignore chains in this predicate.
1264 IgnoreChains = false;
1268 SmallPtrSet<SDNode*, 16> Visited;
1269 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1272 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1273 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1274 SelectInlineAsmMemoryOperands(Ops);
1276 std::vector<EVT> VTs;
1277 VTs.push_back(MVT::Other);
1278 VTs.push_back(MVT::Flag);
1279 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1280 VTs, &Ops[0], Ops.size());
1282 return New.getNode();
1285 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1286 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1289 /// GetVBR - decode a vbr encoding whose top bit is set.
1290 ALWAYS_INLINE static uint64_t
1291 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1292 assert(Val >= 128 && "Not a VBR");
1293 Val &= 127; // Remove first vbr bit.
1298 NextBits = MatcherTable[Idx++];
1299 Val |= (NextBits&127) << Shift;
1301 } while (NextBits & 128);
1307 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1308 /// interior flag and chain results to use the new flag and chain results.
1309 void SelectionDAGISel::
1310 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1311 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1313 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1314 bool isMorphNodeTo) {
1315 SmallVector<SDNode*, 4> NowDeadNodes;
1317 ISelUpdater ISU(ISelPosition);
1319 // Now that all the normal results are replaced, we replace the chain and
1320 // flag results if present.
1321 if (!ChainNodesMatched.empty()) {
1322 assert(InputChain.getNode() != 0 &&
1323 "Matched input chains but didn't produce a chain");
1324 // Loop over all of the nodes we matched that produced a chain result.
1325 // Replace all the chain results with the final chain we ended up with.
1326 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1327 SDNode *ChainNode = ChainNodesMatched[i];
1329 // If this node was already deleted, don't look at it.
1330 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1333 // Don't replace the results of the root node if we're doing a
1335 if (ChainNode == NodeToMatch && isMorphNodeTo)
1338 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1339 if (ChainVal.getValueType() == MVT::Flag)
1340 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1341 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1342 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1344 // If the node became dead and we haven't already seen it, delete it.
1345 if (ChainNode->use_empty() &&
1346 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1347 NowDeadNodes.push_back(ChainNode);
1351 // If the result produces a flag, update any flag results in the matched
1352 // pattern with the flag result.
1353 if (InputFlag.getNode() != 0) {
1354 // Handle any interior nodes explicitly marked.
1355 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1356 SDNode *FRN = FlagResultNodesMatched[i];
1358 // If this node was already deleted, don't look at it.
1359 if (FRN->getOpcode() == ISD::DELETED_NODE)
1362 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1363 "Doesn't have a flag result");
1364 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1367 // If the node became dead and we haven't already seen it, delete it.
1368 if (FRN->use_empty() &&
1369 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1370 NowDeadNodes.push_back(FRN);
1374 if (!NowDeadNodes.empty())
1375 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1377 DEBUG(errs() << "ISEL: Match complete!\n");
1383 CR_LeadsToInteriorNode
1386 /// WalkChainUsers - Walk down the users of the specified chained node that is
1387 /// part of the pattern we're matching, looking at all of the users we find.
1388 /// This determines whether something is an interior node, whether we have a
1389 /// non-pattern node in between two pattern nodes (which prevent folding because
1390 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1391 /// between pattern nodes (in which case the TF becomes part of the pattern).
1393 /// The walk we do here is guaranteed to be small because we quickly get down to
1394 /// already selected nodes "below" us.
1396 WalkChainUsers(SDNode *ChainedNode,
1397 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1398 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1399 ChainResult Result = CR_Simple;
1401 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1402 E = ChainedNode->use_end(); UI != E; ++UI) {
1403 // Make sure the use is of the chain, not some other value we produce.
1404 if (UI.getUse().getValueType() != MVT::Other) continue;
1408 // If we see an already-selected machine node, then we've gone beyond the
1409 // pattern that we're selecting down into the already selected chunk of the
1411 if (User->isMachineOpcode() ||
1412 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1415 if (User->getOpcode() == ISD::CopyToReg ||
1416 User->getOpcode() == ISD::CopyFromReg ||
1417 User->getOpcode() == ISD::INLINEASM ||
1418 User->getOpcode() == ISD::EH_LABEL) {
1419 // If their node ID got reset to -1 then they've already been selected.
1420 // Treat them like a MachineOpcode.
1421 if (User->getNodeId() == -1)
1425 // If we have a TokenFactor, we handle it specially.
1426 if (User->getOpcode() != ISD::TokenFactor) {
1427 // If the node isn't a token factor and isn't part of our pattern, then it
1428 // must be a random chained node in between two nodes we're selecting.
1429 // This happens when we have something like:
1434 // Because we structurally match the load/store as a read/modify/write,
1435 // but the call is chained between them. We cannot fold in this case
1436 // because it would induce a cycle in the graph.
1437 if (!std::count(ChainedNodesInPattern.begin(),
1438 ChainedNodesInPattern.end(), User))
1439 return CR_InducesCycle;
1441 // Otherwise we found a node that is part of our pattern. For example in:
1445 // This would happen when we're scanning down from the load and see the
1446 // store as a user. Record that there is a use of ChainedNode that is
1447 // part of the pattern and keep scanning uses.
1448 Result = CR_LeadsToInteriorNode;
1449 InteriorChainedNodes.push_back(User);
1453 // If we found a TokenFactor, there are two cases to consider: first if the
1454 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1455 // uses of the TF are in our pattern) we just want to ignore it. Second,
1456 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1462 // | \ DAG's like cheese
1465 // [TokenFactor] [Op]
1472 // In this case, the TokenFactor becomes part of our match and we rewrite it
1473 // as a new TokenFactor.
1475 // To distinguish these two cases, do a recursive walk down the uses.
1476 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1478 // If the uses of the TokenFactor are just already-selected nodes, ignore
1479 // it, it is "below" our pattern.
1481 case CR_InducesCycle:
1482 // If the uses of the TokenFactor lead to nodes that are not part of our
1483 // pattern that are not selected, folding would turn this into a cycle,
1485 return CR_InducesCycle;
1486 case CR_LeadsToInteriorNode:
1487 break; // Otherwise, keep processing.
1490 // Okay, we know we're in the interesting interior case. The TokenFactor
1491 // is now going to be considered part of the pattern so that we rewrite its
1492 // uses (it may have uses that are not part of the pattern) with the
1493 // ultimate chain result of the generated code. We will also add its chain
1494 // inputs as inputs to the ultimate TokenFactor we create.
1495 Result = CR_LeadsToInteriorNode;
1496 ChainedNodesInPattern.push_back(User);
1497 InteriorChainedNodes.push_back(User);
1504 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1505 /// operation for when the pattern matched at least one node with a chains. The
1506 /// input vector contains a list of all of the chained nodes that we match. We
1507 /// must determine if this is a valid thing to cover (i.e. matching it won't
1508 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1509 /// be used as the input node chain for the generated nodes.
1511 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1512 SelectionDAG *CurDAG) {
1513 // Walk all of the chained nodes we've matched, recursively scanning down the
1514 // users of the chain result. This adds any TokenFactor nodes that are caught
1515 // in between chained nodes to the chained and interior nodes list.
1516 SmallVector<SDNode*, 3> InteriorChainedNodes;
1517 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1518 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1519 InteriorChainedNodes) == CR_InducesCycle)
1520 return SDValue(); // Would induce a cycle.
1523 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1524 // that we are interested in. Form our input TokenFactor node.
1525 SmallVector<SDValue, 3> InputChains;
1526 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1527 // Add the input chain of this node to the InputChains list (which will be
1528 // the operands of the generated TokenFactor) if it's not an interior node.
1529 SDNode *N = ChainNodesMatched[i];
1530 if (N->getOpcode() != ISD::TokenFactor) {
1531 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1534 // Otherwise, add the input chain.
1535 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1536 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1537 InputChains.push_back(InChain);
1541 // If we have a token factor, we want to add all inputs of the token factor
1542 // that are not part of the pattern we're matching.
1543 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1544 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1545 N->getOperand(op).getNode()))
1546 InputChains.push_back(N->getOperand(op));
1551 if (InputChains.size() == 1)
1552 return InputChains[0];
1553 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1554 MVT::Other, &InputChains[0], InputChains.size());
1557 /// MorphNode - Handle morphing a node in place for the selector.
1558 SDNode *SelectionDAGISel::
1559 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1560 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1561 // It is possible we're using MorphNodeTo to replace a node with no
1562 // normal results with one that has a normal result (or we could be
1563 // adding a chain) and the input could have flags and chains as well.
1564 // In this case we need to shift the operands down.
1565 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1566 // than the old isel though.
1567 int OldFlagResultNo = -1, OldChainResultNo = -1;
1569 unsigned NTMNumResults = Node->getNumValues();
1570 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1571 OldFlagResultNo = NTMNumResults-1;
1572 if (NTMNumResults != 1 &&
1573 Node->getValueType(NTMNumResults-2) == MVT::Other)
1574 OldChainResultNo = NTMNumResults-2;
1575 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1576 OldChainResultNo = NTMNumResults-1;
1578 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1579 // that this deletes operands of the old node that become dead.
1580 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1582 // MorphNodeTo can operate in two ways: if an existing node with the
1583 // specified operands exists, it can just return it. Otherwise, it
1584 // updates the node in place to have the requested operands.
1586 // If we updated the node in place, reset the node ID. To the isel,
1587 // this should be just like a newly allocated machine node.
1591 unsigned ResNumResults = Res->getNumValues();
1592 // Move the flag if needed.
1593 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1594 (unsigned)OldFlagResultNo != ResNumResults-1)
1595 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1596 SDValue(Res, ResNumResults-1));
1598 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1601 // Move the chain reference if needed.
1602 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1603 (unsigned)OldChainResultNo != ResNumResults-1)
1604 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1605 SDValue(Res, ResNumResults-1));
1607 // Otherwise, no replacement happened because the node already exists. Replace
1608 // Uses of the old node with the new one.
1610 CurDAG->ReplaceAllUsesWith(Node, Res);
1615 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1616 ALWAYS_INLINE static bool
1617 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1618 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1619 // Accept if it is exactly the same as a previously recorded node.
1620 unsigned RecNo = MatcherTable[MatcherIndex++];
1621 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1622 return N == RecordedNodes[RecNo];
1625 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1626 ALWAYS_INLINE static bool
1627 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1628 SelectionDAGISel &SDISel) {
1629 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1632 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1633 ALWAYS_INLINE static bool
1634 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1635 SelectionDAGISel &SDISel, SDNode *N) {
1636 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1639 ALWAYS_INLINE static bool
1640 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1642 uint16_t Opc = MatcherTable[MatcherIndex++];
1643 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1644 return N->getOpcode() == Opc;
1647 ALWAYS_INLINE static bool
1648 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1649 SDValue N, const TargetLowering &TLI) {
1650 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1651 if (N.getValueType() == VT) return true;
1653 // Handle the case when VT is iPTR.
1654 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1657 ALWAYS_INLINE static bool
1658 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1659 SDValue N, const TargetLowering &TLI,
1661 if (ChildNo >= N.getNumOperands())
1662 return false; // Match fails if out of range child #.
1663 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1667 ALWAYS_INLINE static bool
1668 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1670 return cast<CondCodeSDNode>(N)->get() ==
1671 (ISD::CondCode)MatcherTable[MatcherIndex++];
1674 ALWAYS_INLINE static bool
1675 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1676 SDValue N, const TargetLowering &TLI) {
1677 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1678 if (cast<VTSDNode>(N)->getVT() == VT)
1681 // Handle the case when VT is iPTR.
1682 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1685 ALWAYS_INLINE static bool
1686 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1688 int64_t Val = MatcherTable[MatcherIndex++];
1690 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1692 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1693 return C != 0 && C->getSExtValue() == Val;
1696 ALWAYS_INLINE static bool
1697 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1698 SDValue N, SelectionDAGISel &SDISel) {
1699 int64_t Val = MatcherTable[MatcherIndex++];
1701 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1703 if (N->getOpcode() != ISD::AND) return false;
1705 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1706 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1709 ALWAYS_INLINE static bool
1710 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1711 SDValue N, SelectionDAGISel &SDISel) {
1712 int64_t Val = MatcherTable[MatcherIndex++];
1714 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1716 if (N->getOpcode() != ISD::OR) return false;
1718 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1719 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1722 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1723 /// scope, evaluate the current node. If the current predicate is known to
1724 /// fail, set Result=true and return anything. If the current predicate is
1725 /// known to pass, set Result=false and return the MatcherIndex to continue
1726 /// with. If the current predicate is unknown, set Result=false and return the
1727 /// MatcherIndex to continue with.
1728 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1729 unsigned Index, SDValue N,
1730 bool &Result, SelectionDAGISel &SDISel,
1731 SmallVectorImpl<SDValue> &RecordedNodes){
1732 switch (Table[Index++]) {
1735 return Index-1; // Could not evaluate this predicate.
1736 case SelectionDAGISel::OPC_CheckSame:
1737 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1739 case SelectionDAGISel::OPC_CheckPatternPredicate:
1740 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1742 case SelectionDAGISel::OPC_CheckPredicate:
1743 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1745 case SelectionDAGISel::OPC_CheckOpcode:
1746 Result = !::CheckOpcode(Table, Index, N.getNode());
1748 case SelectionDAGISel::OPC_CheckType:
1749 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1751 case SelectionDAGISel::OPC_CheckChild0Type:
1752 case SelectionDAGISel::OPC_CheckChild1Type:
1753 case SelectionDAGISel::OPC_CheckChild2Type:
1754 case SelectionDAGISel::OPC_CheckChild3Type:
1755 case SelectionDAGISel::OPC_CheckChild4Type:
1756 case SelectionDAGISel::OPC_CheckChild5Type:
1757 case SelectionDAGISel::OPC_CheckChild6Type:
1758 case SelectionDAGISel::OPC_CheckChild7Type:
1759 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1760 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1762 case SelectionDAGISel::OPC_CheckCondCode:
1763 Result = !::CheckCondCode(Table, Index, N);
1765 case SelectionDAGISel::OPC_CheckValueType:
1766 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1768 case SelectionDAGISel::OPC_CheckInteger:
1769 Result = !::CheckInteger(Table, Index, N);
1771 case SelectionDAGISel::OPC_CheckAndImm:
1772 Result = !::CheckAndImm(Table, Index, N, SDISel);
1774 case SelectionDAGISel::OPC_CheckOrImm:
1775 Result = !::CheckOrImm(Table, Index, N, SDISel);
1783 /// FailIndex - If this match fails, this is the index to continue with.
1786 /// NodeStack - The node stack when the scope was formed.
1787 SmallVector<SDValue, 4> NodeStack;
1789 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1790 unsigned NumRecordedNodes;
1792 /// NumMatchedMemRefs - The number of matched memref entries.
1793 unsigned NumMatchedMemRefs;
1795 /// InputChain/InputFlag - The current chain/flag
1796 SDValue InputChain, InputFlag;
1798 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1799 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1804 SDNode *SelectionDAGISel::
1805 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1806 unsigned TableSize) {
1807 // FIXME: Should these even be selected? Handle these cases in the caller?
1808 switch (NodeToMatch->getOpcode()) {
1811 case ISD::EntryToken: // These nodes remain the same.
1812 case ISD::BasicBlock:
1814 //case ISD::VALUETYPE:
1815 //case ISD::CONDCODE:
1816 case ISD::HANDLENODE:
1817 case ISD::MDNODE_SDNODE:
1818 case ISD::TargetConstant:
1819 case ISD::TargetConstantFP:
1820 case ISD::TargetConstantPool:
1821 case ISD::TargetFrameIndex:
1822 case ISD::TargetExternalSymbol:
1823 case ISD::TargetBlockAddress:
1824 case ISD::TargetJumpTable:
1825 case ISD::TargetGlobalTLSAddress:
1826 case ISD::TargetGlobalAddress:
1827 case ISD::TokenFactor:
1828 case ISD::CopyFromReg:
1829 case ISD::CopyToReg:
1831 NodeToMatch->setNodeId(-1); // Mark selected.
1833 case ISD::AssertSext:
1834 case ISD::AssertZext:
1835 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1836 NodeToMatch->getOperand(0));
1838 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1839 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1842 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1844 // Set up the node stack with NodeToMatch as the only node on the stack.
1845 SmallVector<SDValue, 8> NodeStack;
1846 SDValue N = SDValue(NodeToMatch, 0);
1847 NodeStack.push_back(N);
1849 // MatchScopes - Scopes used when matching, if a match failure happens, this
1850 // indicates where to continue checking.
1851 SmallVector<MatchScope, 8> MatchScopes;
1853 // RecordedNodes - This is the set of nodes that have been recorded by the
1855 SmallVector<SDValue, 8> RecordedNodes;
1857 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1859 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1861 // These are the current input chain and flag for use when generating nodes.
1862 // Various Emit operations change these. For example, emitting a copytoreg
1863 // uses and updates these.
1864 SDValue InputChain, InputFlag;
1866 // ChainNodesMatched - If a pattern matches nodes that have input/output
1867 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1868 // which ones they are. The result is captured into this list so that we can
1869 // update the chain results when the pattern is complete.
1870 SmallVector<SDNode*, 3> ChainNodesMatched;
1871 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1873 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1874 NodeToMatch->dump(CurDAG);
1877 // Determine where to start the interpreter. Normally we start at opcode #0,
1878 // but if the state machine starts with an OPC_SwitchOpcode, then we
1879 // accelerate the first lookup (which is guaranteed to be hot) with the
1880 // OpcodeOffset table.
1881 unsigned MatcherIndex = 0;
1883 if (!OpcodeOffset.empty()) {
1884 // Already computed the OpcodeOffset table, just index into it.
1885 if (N.getOpcode() < OpcodeOffset.size())
1886 MatcherIndex = OpcodeOffset[N.getOpcode()];
1887 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1889 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1890 // Otherwise, the table isn't computed, but the state machine does start
1891 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1892 // is the first time we're selecting an instruction.
1895 // Get the size of this case.
1896 unsigned CaseSize = MatcherTable[Idx++];
1898 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1899 if (CaseSize == 0) break;
1901 // Get the opcode, add the index to the table.
1902 uint16_t Opc = MatcherTable[Idx++];
1903 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1904 if (Opc >= OpcodeOffset.size())
1905 OpcodeOffset.resize((Opc+1)*2);
1906 OpcodeOffset[Opc] = Idx;
1910 // Okay, do the lookup for the first opcode.
1911 if (N.getOpcode() < OpcodeOffset.size())
1912 MatcherIndex = OpcodeOffset[N.getOpcode()];
1916 assert(MatcherIndex < TableSize && "Invalid index");
1918 unsigned CurrentOpcodeIndex = MatcherIndex;
1920 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1923 // Okay, the semantics of this operation are that we should push a scope
1924 // then evaluate the first child. However, pushing a scope only to have
1925 // the first check fail (which then pops it) is inefficient. If we can
1926 // determine immediately that the first check (or first several) will
1927 // immediately fail, don't even bother pushing a scope for them.
1931 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1932 if (NumToSkip & 128)
1933 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1934 // Found the end of the scope with no match.
1935 if (NumToSkip == 0) {
1940 FailIndex = MatcherIndex+NumToSkip;
1942 unsigned MatcherIndexOfPredicate = MatcherIndex;
1943 (void)MatcherIndexOfPredicate; // silence warning.
1945 // If we can't evaluate this predicate without pushing a scope (e.g. if
1946 // it is a 'MoveParent') or if the predicate succeeds on this node, we
1947 // push the scope and evaluate the full predicate chain.
1949 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
1950 Result, *this, RecordedNodes);
1954 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
1955 << "index " << MatcherIndexOfPredicate
1956 << ", continuing at " << FailIndex << "\n");
1957 ++NumDAGIselRetries;
1959 // Otherwise, we know that this case of the Scope is guaranteed to fail,
1960 // move to the next case.
1961 MatcherIndex = FailIndex;
1964 // If the whole scope failed to match, bail.
1965 if (FailIndex == 0) break;
1967 // Push a MatchScope which indicates where to go if the first child fails
1969 MatchScope NewEntry;
1970 NewEntry.FailIndex = FailIndex;
1971 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
1972 NewEntry.NumRecordedNodes = RecordedNodes.size();
1973 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
1974 NewEntry.InputChain = InputChain;
1975 NewEntry.InputFlag = InputFlag;
1976 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
1977 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
1978 MatchScopes.push_back(NewEntry);
1981 case OPC_RecordNode:
1982 // Remember this node, it may end up being an operand in the pattern.
1983 RecordedNodes.push_back(N);
1986 case OPC_RecordChild0: case OPC_RecordChild1:
1987 case OPC_RecordChild2: case OPC_RecordChild3:
1988 case OPC_RecordChild4: case OPC_RecordChild5:
1989 case OPC_RecordChild6: case OPC_RecordChild7: {
1990 unsigned ChildNo = Opcode-OPC_RecordChild0;
1991 if (ChildNo >= N.getNumOperands())
1992 break; // Match fails if out of range child #.
1994 RecordedNodes.push_back(N->getOperand(ChildNo));
1997 case OPC_RecordMemRef:
1998 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2001 case OPC_CaptureFlagInput:
2002 // If the current node has an input flag, capture it in InputFlag.
2003 if (N->getNumOperands() != 0 &&
2004 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2005 InputFlag = N->getOperand(N->getNumOperands()-1);
2008 case OPC_MoveChild: {
2009 unsigned ChildNo = MatcherTable[MatcherIndex++];
2010 if (ChildNo >= N.getNumOperands())
2011 break; // Match fails if out of range child #.
2012 N = N.getOperand(ChildNo);
2013 NodeStack.push_back(N);
2017 case OPC_MoveParent:
2018 // Pop the current node off the NodeStack.
2019 NodeStack.pop_back();
2020 assert(!NodeStack.empty() && "Node stack imbalance!");
2021 N = NodeStack.back();
2025 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2027 case OPC_CheckPatternPredicate:
2028 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2030 case OPC_CheckPredicate:
2031 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2035 case OPC_CheckComplexPat: {
2036 unsigned CPNum = MatcherTable[MatcherIndex++];
2037 unsigned RecNo = MatcherTable[MatcherIndex++];
2038 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2039 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2044 case OPC_CheckOpcode:
2045 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2049 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2052 case OPC_SwitchOpcode: {
2053 unsigned CurNodeOpcode = N.getOpcode();
2054 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2057 // Get the size of this case.
2058 CaseSize = MatcherTable[MatcherIndex++];
2060 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2061 if (CaseSize == 0) break;
2063 uint16_t Opc = MatcherTable[MatcherIndex++];
2064 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2066 // If the opcode matches, then we will execute this case.
2067 if (CurNodeOpcode == Opc)
2070 // Otherwise, skip over this case.
2071 MatcherIndex += CaseSize;
2074 // If no cases matched, bail out.
2075 if (CaseSize == 0) break;
2077 // Otherwise, execute the case we found.
2078 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2079 << " to " << MatcherIndex << "\n");
2083 case OPC_SwitchType: {
2084 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2085 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2088 // Get the size of this case.
2089 CaseSize = MatcherTable[MatcherIndex++];
2091 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2092 if (CaseSize == 0) break;
2094 MVT::SimpleValueType CaseVT =
2095 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2096 if (CaseVT == MVT::iPTR)
2097 CaseVT = TLI.getPointerTy().SimpleTy;
2099 // If the VT matches, then we will execute this case.
2100 if (CurNodeVT == CaseVT)
2103 // Otherwise, skip over this case.
2104 MatcherIndex += CaseSize;
2107 // If no cases matched, bail out.
2108 if (CaseSize == 0) break;
2110 // Otherwise, execute the case we found.
2111 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2112 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2115 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2116 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2117 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2118 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2119 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2120 Opcode-OPC_CheckChild0Type))
2123 case OPC_CheckCondCode:
2124 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2126 case OPC_CheckValueType:
2127 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2129 case OPC_CheckInteger:
2130 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2132 case OPC_CheckAndImm:
2133 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2135 case OPC_CheckOrImm:
2136 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2139 case OPC_CheckFoldableChainNode: {
2140 assert(NodeStack.size() != 1 && "No parent node");
2141 // Verify that all intermediate nodes between the root and this one have
2143 bool HasMultipleUses = false;
2144 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2145 if (!NodeStack[i].hasOneUse()) {
2146 HasMultipleUses = true;
2149 if (HasMultipleUses) break;
2151 // Check to see that the target thinks this is profitable to fold and that
2152 // we can fold it without inducing cycles in the graph.
2153 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2155 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2156 NodeToMatch, OptLevel,
2157 true/*We validate our own chains*/))
2162 case OPC_EmitInteger: {
2163 MVT::SimpleValueType VT =
2164 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2165 int64_t Val = MatcherTable[MatcherIndex++];
2167 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2168 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2171 case OPC_EmitRegister: {
2172 MVT::SimpleValueType VT =
2173 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2174 unsigned RegNo = MatcherTable[MatcherIndex++];
2175 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2179 case OPC_EmitConvertToTarget: {
2180 // Convert from IMM/FPIMM to target version.
2181 unsigned RecNo = MatcherTable[MatcherIndex++];
2182 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2183 SDValue Imm = RecordedNodes[RecNo];
2185 if (Imm->getOpcode() == ISD::Constant) {
2186 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2187 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2188 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2189 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2190 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2193 RecordedNodes.push_back(Imm);
2197 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2198 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2199 // These are space-optimized forms of OPC_EmitMergeInputChains.
2200 assert(InputChain.getNode() == 0 &&
2201 "EmitMergeInputChains should be the first chain producing node");
2202 assert(ChainNodesMatched.empty() &&
2203 "Should only have one EmitMergeInputChains per match");
2205 // Read all of the chained nodes.
2206 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2207 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2208 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2210 // FIXME: What if other value results of the node have uses not matched
2212 if (ChainNodesMatched.back() != NodeToMatch &&
2213 !RecordedNodes[RecNo].hasOneUse()) {
2214 ChainNodesMatched.clear();
2218 // Merge the input chains if they are not intra-pattern references.
2219 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2221 if (InputChain.getNode() == 0)
2222 break; // Failed to merge.
2226 case OPC_EmitMergeInputChains: {
2227 assert(InputChain.getNode() == 0 &&
2228 "EmitMergeInputChains should be the first chain producing node");
2229 // This node gets a list of nodes we matched in the input that have
2230 // chains. We want to token factor all of the input chains to these nodes
2231 // together. However, if any of the input chains is actually one of the
2232 // nodes matched in this pattern, then we have an intra-match reference.
2233 // Ignore these because the newly token factored chain should not refer to
2235 unsigned NumChains = MatcherTable[MatcherIndex++];
2236 assert(NumChains != 0 && "Can't TF zero chains");
2238 assert(ChainNodesMatched.empty() &&
2239 "Should only have one EmitMergeInputChains per match");
2241 // Read all of the chained nodes.
2242 for (unsigned i = 0; i != NumChains; ++i) {
2243 unsigned RecNo = MatcherTable[MatcherIndex++];
2244 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2245 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2247 // FIXME: What if other value results of the node have uses not matched
2249 if (ChainNodesMatched.back() != NodeToMatch &&
2250 !RecordedNodes[RecNo].hasOneUse()) {
2251 ChainNodesMatched.clear();
2256 // If the inner loop broke out, the match fails.
2257 if (ChainNodesMatched.empty())
2260 // Merge the input chains if they are not intra-pattern references.
2261 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2263 if (InputChain.getNode() == 0)
2264 break; // Failed to merge.
2269 case OPC_EmitCopyToReg: {
2270 unsigned RecNo = MatcherTable[MatcherIndex++];
2271 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2272 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2274 if (InputChain.getNode() == 0)
2275 InputChain = CurDAG->getEntryNode();
2277 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2278 DestPhysReg, RecordedNodes[RecNo],
2281 InputFlag = InputChain.getValue(1);
2285 case OPC_EmitNodeXForm: {
2286 unsigned XFormNo = MatcherTable[MatcherIndex++];
2287 unsigned RecNo = MatcherTable[MatcherIndex++];
2288 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2289 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2294 case OPC_MorphNodeTo: {
2295 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2296 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2297 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2298 // Get the result VT list.
2299 unsigned NumVTs = MatcherTable[MatcherIndex++];
2300 SmallVector<EVT, 4> VTs;
2301 for (unsigned i = 0; i != NumVTs; ++i) {
2302 MVT::SimpleValueType VT =
2303 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2304 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2308 if (EmitNodeInfo & OPFL_Chain)
2309 VTs.push_back(MVT::Other);
2310 if (EmitNodeInfo & OPFL_FlagOutput)
2311 VTs.push_back(MVT::Flag);
2313 // This is hot code, so optimize the two most common cases of 1 and 2
2316 if (VTs.size() == 1)
2317 VTList = CurDAG->getVTList(VTs[0]);
2318 else if (VTs.size() == 2)
2319 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2321 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2323 // Get the operand list.
2324 unsigned NumOps = MatcherTable[MatcherIndex++];
2325 SmallVector<SDValue, 8> Ops;
2326 for (unsigned i = 0; i != NumOps; ++i) {
2327 unsigned RecNo = MatcherTable[MatcherIndex++];
2329 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2331 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2332 Ops.push_back(RecordedNodes[RecNo]);
2335 // If there are variadic operands to add, handle them now.
2336 if (EmitNodeInfo & OPFL_VariadicInfo) {
2337 // Determine the start index to copy from.
2338 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2339 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2340 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2341 "Invalid variadic node");
2342 // Copy all of the variadic operands, not including a potential flag
2344 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2346 SDValue V = NodeToMatch->getOperand(i);
2347 if (V.getValueType() == MVT::Flag) break;
2352 // If this has chain/flag inputs, add them.
2353 if (EmitNodeInfo & OPFL_Chain)
2354 Ops.push_back(InputChain);
2355 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2356 Ops.push_back(InputFlag);
2360 if (Opcode != OPC_MorphNodeTo) {
2361 // If this is a normal EmitNode command, just create the new node and
2362 // add the results to the RecordedNodes list.
2363 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2364 VTList, Ops.data(), Ops.size());
2366 // Add all the non-flag/non-chain results to the RecordedNodes list.
2367 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2368 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2369 RecordedNodes.push_back(SDValue(Res, i));
2373 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2377 // If the node had chain/flag results, update our notion of the current
2379 if (EmitNodeInfo & OPFL_FlagOutput) {
2380 InputFlag = SDValue(Res, VTs.size()-1);
2381 if (EmitNodeInfo & OPFL_Chain)
2382 InputChain = SDValue(Res, VTs.size()-2);
2383 } else if (EmitNodeInfo & OPFL_Chain)
2384 InputChain = SDValue(Res, VTs.size()-1);
2386 // If the OPFL_MemRefs flag is set on this node, slap all of the
2387 // accumulated memrefs onto it.
2389 // FIXME: This is vastly incorrect for patterns with multiple outputs
2390 // instructions that access memory and for ComplexPatterns that match
2392 if (EmitNodeInfo & OPFL_MemRefs) {
2393 MachineSDNode::mmo_iterator MemRefs =
2394 MF->allocateMemRefsArray(MatchedMemRefs.size());
2395 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2396 cast<MachineSDNode>(Res)
2397 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2401 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2402 << " node: "; Res->dump(CurDAG); errs() << "\n");
2404 // If this was a MorphNodeTo then we're completely done!
2405 if (Opcode == OPC_MorphNodeTo) {
2406 // Update chain and flag uses.
2407 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2408 InputFlag, FlagResultNodesMatched, true);
2415 case OPC_MarkFlagResults: {
2416 unsigned NumNodes = MatcherTable[MatcherIndex++];
2418 // Read and remember all the flag-result nodes.
2419 for (unsigned i = 0; i != NumNodes; ++i) {
2420 unsigned RecNo = MatcherTable[MatcherIndex++];
2422 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2424 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2425 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2430 case OPC_CompleteMatch: {
2431 // The match has been completed, and any new nodes (if any) have been
2432 // created. Patch up references to the matched dag to use the newly
2434 unsigned NumResults = MatcherTable[MatcherIndex++];
2436 for (unsigned i = 0; i != NumResults; ++i) {
2437 unsigned ResSlot = MatcherTable[MatcherIndex++];
2439 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2441 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2442 SDValue Res = RecordedNodes[ResSlot];
2444 assert(i < NodeToMatch->getNumValues() &&
2445 NodeToMatch->getValueType(i) != MVT::Other &&
2446 NodeToMatch->getValueType(i) != MVT::Flag &&
2447 "Invalid number of results to complete!");
2448 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2449 NodeToMatch->getValueType(i) == MVT::iPTR ||
2450 Res.getValueType() == MVT::iPTR ||
2451 NodeToMatch->getValueType(i).getSizeInBits() ==
2452 Res.getValueType().getSizeInBits()) &&
2453 "invalid replacement");
2454 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2457 // If the root node defines a flag, add it to the flag nodes to update
2459 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2460 FlagResultNodesMatched.push_back(NodeToMatch);
2462 // Update chain and flag uses.
2463 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2464 InputFlag, FlagResultNodesMatched, false);
2466 assert(NodeToMatch->use_empty() &&
2467 "Didn't replace all uses of the node?");
2469 // FIXME: We just return here, which interacts correctly with SelectRoot
2470 // above. We should fix this to not return an SDNode* anymore.
2475 // If the code reached this point, then the match failed. See if there is
2476 // another child to try in the current 'Scope', otherwise pop it until we
2477 // find a case to check.
2478 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2479 ++NumDAGIselRetries;
2481 if (MatchScopes.empty()) {
2482 CannotYetSelect(NodeToMatch);
2486 // Restore the interpreter state back to the point where the scope was
2488 MatchScope &LastScope = MatchScopes.back();
2489 RecordedNodes.resize(LastScope.NumRecordedNodes);
2491 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2492 N = NodeStack.back();
2494 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2495 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2496 MatcherIndex = LastScope.FailIndex;
2498 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2500 InputChain = LastScope.InputChain;
2501 InputFlag = LastScope.InputFlag;
2502 if (!LastScope.HasChainNodesMatched)
2503 ChainNodesMatched.clear();
2504 if (!LastScope.HasFlagResultNodesMatched)
2505 FlagResultNodesMatched.clear();
2507 // Check to see what the offset is at the new MatcherIndex. If it is zero
2508 // we have reached the end of this scope, otherwise we have another child
2509 // in the current scope to try.
2510 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2511 if (NumToSkip & 128)
2512 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2514 // If we have another child in this scope to match, update FailIndex and
2516 if (NumToSkip != 0) {
2517 LastScope.FailIndex = MatcherIndex+NumToSkip;
2521 // End of this scope, pop it and try the next child in the containing
2523 MatchScopes.pop_back();
2530 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2532 raw_string_ostream Msg(msg);
2533 Msg << "Cannot yet select: ";
2535 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2536 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2537 N->getOpcode() != ISD::INTRINSIC_VOID) {
2538 N->printrFull(Msg, CurDAG);
2540 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2542 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2543 if (iid < Intrinsic::num_intrinsics)
2544 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2545 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2546 Msg << "target intrinsic %" << TII->getName(iid);
2548 Msg << "unknown intrinsic #" << iid;
2550 report_fatal_error(Msg.str());
2553 char SelectionDAGISel::ID = 0;