1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
37 #include "llvm/CodeGen/SchedulerRegistry.h"
38 #include "llvm/CodeGen/SelectionDAG.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetIntrinsicInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/Timer.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/ADT/Statistic.h"
54 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
55 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
58 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
59 cl::desc("Enable verbose messages in the \"fast\" "
60 "instruction selector"));
62 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
63 cl::desc("Enable abort calls when \"fast\" instruction fails"));
67 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
68 cl::desc("Pop up a window to show dags before the first "
71 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
72 cl::desc("Pop up a window to show dags before legalize types"));
74 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
75 cl::desc("Pop up a window to show dags before legalize"));
77 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
78 cl::desc("Pop up a window to show dags before the second "
81 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
82 cl::desc("Pop up a window to show dags before the post legalize types"
83 " dag combine pass"));
85 ViewISelDAGs("view-isel-dags", cl::Hidden,
86 cl::desc("Pop up a window to show isel dags as they are selected"));
88 ViewSchedDAGs("view-sched-dags", cl::Hidden,
89 cl::desc("Pop up a window to show sched dags as they are processed"));
91 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
92 cl::desc("Pop up a window to show SUnit dags after they are processed"));
94 static const bool ViewDAGCombine1 = false,
95 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
96 ViewDAGCombine2 = false,
97 ViewDAGCombineLT = false,
98 ViewISelDAGs = false, ViewSchedDAGs = false,
99 ViewSUnitDAGs = false;
102 //===---------------------------------------------------------------------===//
104 /// RegisterScheduler class - Track the registration of instruction schedulers.
106 //===---------------------------------------------------------------------===//
107 MachinePassRegistry RegisterScheduler::Registry;
109 //===---------------------------------------------------------------------===//
111 /// ISHeuristic command line option for instruction schedulers.
113 //===---------------------------------------------------------------------===//
114 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
115 RegisterPassParser<RegisterScheduler> >
116 ISHeuristic("pre-RA-sched",
117 cl::init(&createDefaultScheduler),
118 cl::desc("Instruction schedulers available (before register"
121 static RegisterScheduler
122 defaultListDAGScheduler("default", "Best scheduler for the target",
123 createDefaultScheduler);
126 //===--------------------------------------------------------------------===//
127 /// createDefaultScheduler - This creates an instruction scheduler appropriate
129 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
130 CodeGenOpt::Level OptLevel) {
131 const TargetLowering &TLI = IS->getTargetLowering();
133 if (OptLevel == CodeGenOpt::None)
134 return createFastDAGScheduler(IS, OptLevel);
135 if (TLI.getSchedulingPreference() == Sched::Latency)
136 return createTDListDAGScheduler(IS, OptLevel);
137 if (TLI.getSchedulingPreference() == Sched::RegPressure)
138 return createBURRListDAGScheduler(IS, OptLevel);
139 assert(TLI.getSchedulingPreference() == Sched::Hybrid &&
140 "Unknown sched type!");
141 return createHybridListDAGScheduler(IS, OptLevel);
145 // EmitInstrWithCustomInserter - This method should be implemented by targets
146 // that mark instructions with the 'usesCustomInserter' flag. These
147 // instructions are special in various ways, which require special support to
148 // insert. The specified MachineInstr is created but not inserted into any
149 // basic blocks, and this method is called to expand it into a sequence of
150 // instructions, potentially also creating new basic blocks and control flow.
151 // When new basic blocks are inserted and the edges from MBB to its successors
152 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
155 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
156 MachineBasicBlock *MBB) const {
158 dbgs() << "If a target marks an instruction with "
159 "'usesCustomInserter', it must implement "
160 "TargetLowering::EmitInstrWithCustomInserter!";
166 //===----------------------------------------------------------------------===//
167 // SelectionDAGISel code
168 //===----------------------------------------------------------------------===//
170 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
171 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
172 FuncInfo(new FunctionLoweringInfo(TLI)),
173 CurDAG(new SelectionDAG(tm, *FuncInfo)),
174 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
180 SelectionDAGISel::~SelectionDAGISel() {
186 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
187 AU.addRequired<AliasAnalysis>();
188 AU.addPreserved<AliasAnalysis>();
189 AU.addRequired<GCModuleInfo>();
190 AU.addPreserved<GCModuleInfo>();
191 MachineFunctionPass::getAnalysisUsage(AU);
194 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
195 // Do some sanity-checking on the command-line options.
196 assert((!EnableFastISelVerbose || EnableFastISel) &&
197 "-fast-isel-verbose requires -fast-isel");
198 assert((!EnableFastISelAbort || EnableFastISel) &&
199 "-fast-isel-abort requires -fast-isel");
201 const Function &Fn = *mf.getFunction();
202 const TargetInstrInfo &TII = *TM.getInstrInfo();
203 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
206 RegInfo = &MF->getRegInfo();
207 AA = &getAnalysis<AliasAnalysis>();
208 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
210 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
213 FuncInfo->set(Fn, *MF, EnableFastISel);
216 SelectAllBasicBlocks(Fn);
218 // If the first basic block in the function has live ins that need to be
219 // copied into vregs, emit the copies into the top of the block before
220 // emitting the code for the block.
221 MachineBasicBlock *EntryMBB = MF->begin();
222 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
224 // Insert DBG_VALUE instructions for function arguments to the entry block.
225 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
226 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
227 unsigned Reg = MI->getOperand(0).getReg();
228 if (TargetRegisterInfo::isPhysicalRegister(Reg))
229 EntryMBB->insert(EntryMBB->begin(), MI);
231 MachineInstr *Def = RegInfo->getVRegDef(Reg);
232 MachineBasicBlock::iterator InsertPos = Def;
233 // FIXME: VR def may not be in entry block.
234 Def->getParent()->insert(llvm::next(InsertPos), MI);
238 // Determine if there are any calls in this machine function.
239 MachineFrameInfo *MFI = MF->getFrameInfo();
240 if (!MFI->hasCalls()) {
241 for (MachineFunction::const_iterator
242 I = MF->begin(), E = MF->end(); I != E; ++I) {
243 const MachineBasicBlock *MBB = I;
244 for (MachineBasicBlock::const_iterator
245 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
246 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
247 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) {
248 MFI->setHasCalls(true);
256 // Release function-specific state. SDB and CurDAG are already cleared
264 SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
265 const BasicBlock *LLVMBB,
266 BasicBlock::const_iterator Begin,
267 BasicBlock::const_iterator End,
269 // Lower all of the non-terminator instructions. If a call is emitted
270 // as a tail call, cease emitting nodes for this block. Terminators
271 // are handled below.
272 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
275 // Make sure the root of the DAG is up-to-date.
276 CurDAG->setRoot(SDB->getControlRoot());
277 HadTailCall = SDB->HasTailCall;
280 // Final step, emit the lowered DAG as machine code.
281 return CodeGenAndEmitDAG(BB);
285 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
286 /// nodes from the worklist.
287 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
288 SmallVector<SDNode*, 128> &Worklist;
289 SmallPtrSet<SDNode*, 128> &InWorklist;
291 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
292 SmallPtrSet<SDNode*, 128> &inwl)
293 : Worklist(wl), InWorklist(inwl) {}
295 void RemoveFromWorklist(SDNode *N) {
296 if (!InWorklist.erase(N)) return;
298 SmallVector<SDNode*, 128>::iterator I =
299 std::find(Worklist.begin(), Worklist.end(), N);
300 assert(I != Worklist.end() && "Not in worklist");
302 *I = Worklist.back();
306 virtual void NodeDeleted(SDNode *N, SDNode *E) {
307 RemoveFromWorklist(N);
310 virtual void NodeUpdated(SDNode *N) {
316 /// TrivialTruncElim - Eliminate some trivial nops that can result from
317 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
318 static bool TrivialTruncElim(SDValue Op,
319 TargetLowering::TargetLoweringOpt &TLO) {
320 SDValue N0 = Op.getOperand(0);
321 EVT VT = Op.getValueType();
322 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
323 N0.getOpcode() == ISD::SIGN_EXTEND ||
324 N0.getOpcode() == ISD::ANY_EXTEND) &&
325 N0.getOperand(0).getValueType() == VT) {
326 return TLO.CombineTo(Op, N0.getOperand(0));
331 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
332 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
333 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
334 void SelectionDAGISel::ShrinkDemandedOps() {
335 SmallVector<SDNode*, 128> Worklist;
336 SmallPtrSet<SDNode*, 128> InWorklist;
338 // Add all the dag nodes to the worklist.
339 Worklist.reserve(CurDAG->allnodes_size());
340 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
341 E = CurDAG->allnodes_end(); I != E; ++I) {
342 Worklist.push_back(I);
343 InWorklist.insert(I);
346 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true);
347 while (!Worklist.empty()) {
348 SDNode *N = Worklist.pop_back_val();
351 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
352 // Deleting this node may make its operands dead, add them to the worklist
353 // if they aren't already there.
354 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
355 if (InWorklist.insert(N->getOperand(i).getNode()))
356 Worklist.push_back(N->getOperand(i).getNode());
358 CurDAG->DeleteNode(N);
362 // Run ShrinkDemandedOp on scalar binary operations.
363 if (N->getNumValues() != 1 ||
364 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
367 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
368 APInt Demanded = APInt::getAllOnesValue(BitWidth);
369 APInt KnownZero, KnownOne;
370 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
371 KnownZero, KnownOne, TLO) &&
372 (N->getOpcode() != ISD::TRUNCATE ||
373 !TrivialTruncElim(SDValue(N, 0), TLO)))
377 assert(!InWorklist.count(N) && "Already in worklist");
378 Worklist.push_back(N);
379 InWorklist.insert(N);
381 // Replace the old value with the new one.
382 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
383 TLO.Old.getNode()->dump(CurDAG);
384 errs() << "\nWith: ";
385 TLO.New.getNode()->dump(CurDAG);
388 if (InWorklist.insert(TLO.New.getNode()))
389 Worklist.push_back(TLO.New.getNode());
391 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
392 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
394 if (!TLO.Old.getNode()->use_empty()) continue;
396 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
398 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
399 if (OpNode->hasOneUse()) {
400 // Add OpNode to the end of the list to revisit.
401 DeadNodes.RemoveFromWorklist(OpNode);
402 Worklist.push_back(OpNode);
403 InWorklist.insert(OpNode);
407 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
408 CurDAG->DeleteNode(TLO.Old.getNode());
412 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
413 SmallPtrSet<SDNode*, 128> VisitedNodes;
414 SmallVector<SDNode*, 128> Worklist;
416 Worklist.push_back(CurDAG->getRoot().getNode());
423 SDNode *N = Worklist.pop_back_val();
425 // If we've already seen this node, ignore it.
426 if (!VisitedNodes.insert(N))
429 // Otherwise, add all chain operands to the worklist.
430 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
431 if (N->getOperand(i).getValueType() == MVT::Other)
432 Worklist.push_back(N->getOperand(i).getNode());
434 // If this is a CopyToReg with a vreg dest, process it.
435 if (N->getOpcode() != ISD::CopyToReg)
438 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
439 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
442 // Ignore non-scalar or non-integer values.
443 SDValue Src = N->getOperand(2);
444 EVT SrcVT = Src.getValueType();
445 if (!SrcVT.isInteger() || SrcVT.isVector())
448 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
449 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
450 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
452 // Only install this information if it tells us something.
453 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
454 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
455 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
456 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
457 FunctionLoweringInfo::LiveOutInfo &LOI =
458 FuncInfo->LiveOutRegInfo[DestReg];
459 LOI.NumSignBits = NumSignBits;
460 LOI.KnownOne = KnownOne;
461 LOI.KnownZero = KnownZero;
463 } while (!Worklist.empty());
466 MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
467 std::string GroupName;
468 if (TimePassesIsEnabled)
469 GroupName = "Instruction Selection and Scheduling";
470 std::string BlockName;
471 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
472 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
474 BlockName = MF->getFunction()->getNameStr() + ":" +
475 BB->getBasicBlock()->getNameStr();
477 DEBUG(dbgs() << "Initial selection DAG:\n");
478 DEBUG(CurDAG->dump());
480 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
482 // Run the DAG combiner in pre-legalize mode.
483 if (TimePassesIsEnabled) {
484 NamedRegionTimer T("DAG Combining 1", GroupName);
485 CurDAG->Combine(Unrestricted, *AA, OptLevel);
487 CurDAG->Combine(Unrestricted, *AA, OptLevel);
490 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
491 DEBUG(CurDAG->dump());
493 // Second step, hack on the DAG until it only uses operations and types that
494 // the target supports.
495 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
499 if (TimePassesIsEnabled) {
500 NamedRegionTimer T("Type Legalization", GroupName);
501 Changed = CurDAG->LegalizeTypes();
503 Changed = CurDAG->LegalizeTypes();
506 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
507 DEBUG(CurDAG->dump());
510 if (ViewDAGCombineLT)
511 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
513 // Run the DAG combiner in post-type-legalize mode.
514 if (TimePassesIsEnabled) {
515 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
516 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
518 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
521 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
522 DEBUG(CurDAG->dump());
525 if (TimePassesIsEnabled) {
526 NamedRegionTimer T("Vector Legalization", GroupName);
527 Changed = CurDAG->LegalizeVectors();
529 Changed = CurDAG->LegalizeVectors();
533 if (TimePassesIsEnabled) {
534 NamedRegionTimer T("Type Legalization 2", GroupName);
535 CurDAG->LegalizeTypes();
537 CurDAG->LegalizeTypes();
540 if (ViewDAGCombineLT)
541 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
543 // Run the DAG combiner in post-type-legalize mode.
544 if (TimePassesIsEnabled) {
545 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
546 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
548 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
551 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
552 DEBUG(CurDAG->dump());
555 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
557 if (TimePassesIsEnabled) {
558 NamedRegionTimer T("DAG Legalization", GroupName);
559 CurDAG->Legalize(OptLevel);
561 CurDAG->Legalize(OptLevel);
564 DEBUG(dbgs() << "Legalized selection DAG:\n");
565 DEBUG(CurDAG->dump());
567 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
569 // Run the DAG combiner in post-legalize mode.
570 if (TimePassesIsEnabled) {
571 NamedRegionTimer T("DAG Combining 2", GroupName);
572 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
574 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
577 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
578 DEBUG(CurDAG->dump());
580 if (OptLevel != CodeGenOpt::None) {
582 ComputeLiveOutVRegInfo();
585 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
587 // Third, instruction select all of the operations to machine code, adding the
588 // code to the MachineBasicBlock.
589 if (TimePassesIsEnabled) {
590 NamedRegionTimer T("Instruction Selection", GroupName);
591 DoInstructionSelection();
593 DoInstructionSelection();
596 DEBUG(dbgs() << "Selected selection DAG:\n");
597 DEBUG(CurDAG->dump());
599 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
601 // Schedule machine code.
602 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
603 if (TimePassesIsEnabled) {
604 NamedRegionTimer T("Instruction Scheduling", GroupName);
605 Scheduler->Run(CurDAG, BB, BB->end());
607 Scheduler->Run(CurDAG, BB, BB->end());
610 if (ViewSUnitDAGs) Scheduler->viewGraph();
612 // Emit machine code to BB. This can change 'BB' to the last block being
614 if (TimePassesIsEnabled) {
615 NamedRegionTimer T("Instruction Creation", GroupName);
616 BB = Scheduler->EmitSchedule();
618 BB = Scheduler->EmitSchedule();
621 // Free the scheduler state.
622 if (TimePassesIsEnabled) {
623 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
629 // Free the SelectionDAG state, now that we're finished with it.
635 void SelectionDAGISel::DoInstructionSelection() {
636 DEBUG(errs() << "===== Instruction selection begins:\n");
640 // Select target instructions for the DAG.
642 // Number all nodes with a topological order and set DAGSize.
643 DAGSize = CurDAG->AssignTopologicalOrder();
645 // Create a dummy node (which is not added to allnodes), that adds
646 // a reference to the root node, preventing it from being deleted,
647 // and tracking any changes of the root.
648 HandleSDNode Dummy(CurDAG->getRoot());
649 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
652 // The AllNodes list is now topological-sorted. Visit the
653 // nodes by starting at the end of the list (the root of the
654 // graph) and preceding back toward the beginning (the entry
656 while (ISelPosition != CurDAG->allnodes_begin()) {
657 SDNode *Node = --ISelPosition;
658 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
659 // but there are currently some corner cases that it misses. Also, this
660 // makes it theoretically possible to disable the DAGCombiner.
661 if (Node->use_empty())
664 SDNode *ResNode = Select(Node);
666 // FIXME: This is pretty gross. 'Select' should be changed to not return
667 // anything at all and this code should be nuked with a tactical strike.
669 // If node should not be replaced, continue with the next one.
670 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
674 ReplaceUses(Node, ResNode);
676 // If after the replacement this node is not used any more,
677 // remove this dead node.
678 if (Node->use_empty()) { // Don't delete EntryToken, etc.
679 ISelUpdater ISU(ISelPosition);
680 CurDAG->RemoveDeadNode(Node, &ISU);
684 CurDAG->setRoot(Dummy.getValue());
687 DEBUG(errs() << "===== Instruction selection ends:\n");
689 PostprocessISelDAG();
692 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
693 /// do other setup for EH landing-pad blocks.
694 void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
695 // Add a label to mark the beginning of the landing pad. Deletion of the
696 // landing pad can thus be detected via the MachineModuleInfo.
697 MCSymbol *Label = MF->getMMI().addLandingPad(BB);
699 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
700 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
702 // Mark exception register as live in.
703 unsigned Reg = TLI.getExceptionAddressRegister();
704 if (Reg) BB->addLiveIn(Reg);
706 // Mark exception selector register as live in.
707 Reg = TLI.getExceptionSelectorRegister();
708 if (Reg) BB->addLiveIn(Reg);
710 // FIXME: Hack around an exception handling flaw (PR1508): the personality
711 // function and list of typeids logically belong to the invoke (or, if you
712 // like, the basic block containing the invoke), and need to be associated
713 // with it in the dwarf exception handling tables. Currently however the
714 // information is provided by an intrinsic (eh.selector) that can be moved
715 // to unexpected places by the optimizers: if the unwind edge is critical,
716 // then breaking it can result in the intrinsics being in the successor of
717 // the landing pad, not the landing pad itself. This results
718 // in exceptions not being caught because no typeids are associated with
719 // the invoke. This may not be the only way things can go wrong, but it
720 // is the only way we try to work around for the moment.
721 const BasicBlock *LLVMBB = BB->getBasicBlock();
722 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
724 if (Br && Br->isUnconditional()) { // Critical edge?
725 BasicBlock::const_iterator I, E;
726 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
727 if (isa<EHSelectorInst>(I))
731 // No catch info found - try to extract some from the successor.
732 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
736 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
737 // Initialize the Fast-ISel state, if needed.
738 FastISel *FastIS = 0;
740 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
741 FuncInfo->StaticAllocaMap,
742 FuncInfo->PHINodesToUpdate
744 , FuncInfo->CatchInfoLost
748 // Iterate over all basic blocks in the function.
749 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
750 const BasicBlock *LLVMBB = &*I;
751 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
753 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
754 BasicBlock::const_iterator const End = LLVMBB->end();
755 BasicBlock::const_iterator BI = Begin;
757 // Lower any arguments needed in this block if this is the entry block.
758 if (LLVMBB == &Fn.getEntryBlock())
759 LowerArguments(LLVMBB);
761 // Setup an EH landing-pad block.
762 if (BB->isLandingPad())
763 PrepareEHLandingPad(BB);
765 // Before doing SelectionDAG ISel, see if FastISel has been requested.
767 // Emit code for any incoming arguments. This must happen before
768 // beginning FastISel on the entry block.
769 if (LLVMBB == &Fn.getEntryBlock()) {
770 CurDAG->setRoot(SDB->getControlRoot());
772 BB = CodeGenAndEmitDAG(BB);
774 FastIS->startNewBlock(BB);
775 // Do FastISel on as many instructions as possible.
776 for (; BI != End; ++BI) {
777 // Try to select the instruction with FastISel.
778 if (FastIS->SelectInstruction(BI))
781 // Then handle certain instructions as single-LLVM-Instruction blocks.
782 if (isa<CallInst>(BI)) {
783 ++NumFastIselFailures;
784 if (EnableFastISelVerbose || EnableFastISelAbort) {
785 dbgs() << "FastISel missed call: ";
789 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
790 unsigned &R = FuncInfo->ValueMap[BI];
792 R = FuncInfo->CreateRegForValue(BI);
795 bool HadTailCall = false;
796 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall);
798 // If the call was emitted as a tail call, we're done with the block.
804 // If the instruction was codegen'd with multiple blocks,
805 // inform the FastISel object where to resume inserting.
806 FastIS->setCurrentBlock(BB);
810 // Otherwise, give up on FastISel for the rest of the block.
811 // For now, be a little lenient about non-branch terminators.
812 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
813 ++NumFastIselFailures;
814 if (EnableFastISelVerbose || EnableFastISelAbort) {
815 dbgs() << "FastISel miss: ";
818 if (EnableFastISelAbort)
819 // The "fast" selector couldn't handle something and bailed.
820 // For the purpose of debugging, just abort.
821 llvm_unreachable("FastISel didn't select the entire block");
827 // Run SelectionDAG instruction selection on the remainder of the block
828 // not handled by FastISel. If FastISel is not run, this is the entire
832 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall);
835 FinishBasicBlock(BB);
836 FuncInfo->PHINodesToUpdate.clear();
843 SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
845 DEBUG(dbgs() << "Total amount of phi nodes to update: "
846 << FuncInfo->PHINodesToUpdate.size() << "\n");
847 DEBUG(for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
848 dbgs() << "Node " << i << " : ("
849 << FuncInfo->PHINodesToUpdate[i].first
850 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
852 // Next, now that we know what the last MBB the LLVM BB expanded is, update
853 // PHI nodes in successors.
854 if (SDB->SwitchCases.empty() &&
855 SDB->JTCases.empty() &&
856 SDB->BitTestCases.empty()) {
857 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
858 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
859 assert(PHI->isPHI() &&
860 "This is not a machine PHI node that we are updating!");
861 if (!BB->isSuccessor(PHI->getParent()))
864 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
865 PHI->addOperand(MachineOperand::CreateMBB(BB));
870 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
871 // Lower header first, if it wasn't already lowered
872 if (!SDB->BitTestCases[i].Emitted) {
873 // Set the current basic block to the mbb we wish to insert the code into
874 BB = SDB->BitTestCases[i].Parent;
876 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
877 CurDAG->setRoot(SDB->getRoot());
879 BB = CodeGenAndEmitDAG(BB);
882 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
883 // Set the current basic block to the mbb we wish to insert the code into
884 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
887 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
888 SDB->BitTestCases[i].Reg,
889 SDB->BitTestCases[i].Cases[j],
892 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
893 SDB->BitTestCases[i].Reg,
894 SDB->BitTestCases[i].Cases[j],
898 CurDAG->setRoot(SDB->getRoot());
900 BB = CodeGenAndEmitDAG(BB);
904 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
906 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
907 MachineBasicBlock *PHIBB = PHI->getParent();
908 assert(PHI->isPHI() &&
909 "This is not a machine PHI node that we are updating!");
910 // This is "default" BB. We have two jumps to it. From "header" BB and
911 // from last "case" BB.
912 if (PHIBB == SDB->BitTestCases[i].Default) {
913 PHI->addOperand(MachineOperand::
914 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
916 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
917 PHI->addOperand(MachineOperand::
918 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
920 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
923 // One of "cases" BB.
924 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
926 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
927 if (cBB->isSuccessor(PHIBB)) {
928 PHI->addOperand(MachineOperand::
929 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
931 PHI->addOperand(MachineOperand::CreateMBB(cBB));
936 SDB->BitTestCases.clear();
938 // If the JumpTable record is filled in, then we need to emit a jump table.
939 // Updating the PHI nodes is tricky in this case, since we need to determine
940 // whether the PHI is a successor of the range check MBB or the jump table MBB
941 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
942 // Lower header first, if it wasn't already lowered
943 if (!SDB->JTCases[i].first.Emitted) {
944 // Set the current basic block to the mbb we wish to insert the code into
945 BB = SDB->JTCases[i].first.HeaderBB;
947 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
949 CurDAG->setRoot(SDB->getRoot());
951 BB = CodeGenAndEmitDAG(BB);
954 // Set the current basic block to the mbb we wish to insert the code into
955 BB = SDB->JTCases[i].second.MBB;
957 SDB->visitJumpTable(SDB->JTCases[i].second);
958 CurDAG->setRoot(SDB->getRoot());
960 BB = CodeGenAndEmitDAG(BB);
963 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
965 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
966 MachineBasicBlock *PHIBB = PHI->getParent();
967 assert(PHI->isPHI() &&
968 "This is not a machine PHI node that we are updating!");
969 // "default" BB. We can go there only from header BB.
970 if (PHIBB == SDB->JTCases[i].second.Default) {
972 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
975 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
977 // JT BB. Just iterate over successors here
978 if (BB->isSuccessor(PHIBB)) {
980 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
982 PHI->addOperand(MachineOperand::CreateMBB(BB));
986 SDB->JTCases.clear();
988 // If the switch block involved a branch to one of the actual successors, we
989 // need to update PHI nodes in that block.
990 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
991 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
992 assert(PHI->isPHI() &&
993 "This is not a machine PHI node that we are updating!");
994 if (BB->isSuccessor(PHI->getParent())) {
996 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
997 PHI->addOperand(MachineOperand::CreateMBB(BB));
1001 // If we generated any switch lowering information, build and codegen any
1002 // additional DAGs necessary.
1003 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1004 // Set the current basic block to the mbb we wish to insert the code into
1005 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1007 // Determine the unique successors.
1008 SmallVector<MachineBasicBlock *, 2> Succs;
1009 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1010 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1011 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1013 // Emit the code. Note that this could result in ThisBB being split, so
1014 // we need to check for updates.
1015 SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
1016 CurDAG->setRoot(SDB->getRoot());
1018 ThisBB = CodeGenAndEmitDAG(BB);
1020 // Handle any PHI nodes in successors of this chunk, as if we were coming
1021 // from the original BB before switch expansion. Note that PHI nodes can
1022 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1023 // handle them the right number of times.
1024 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1026 // BB may have been removed from the CFG if a branch was constant folded.
1027 if (ThisBB->isSuccessor(BB)) {
1028 for (MachineBasicBlock::iterator Phi = BB->begin();
1029 Phi != BB->end() && Phi->isPHI();
1031 // This value for this PHI node is recorded in PHINodesToUpdate.
1032 for (unsigned pn = 0; ; ++pn) {
1033 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1034 "Didn't find PHI entry!");
1035 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1036 Phi->addOperand(MachineOperand::
1037 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1039 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1047 SDB->SwitchCases.clear();
1051 /// Create the scheduler. If a specific scheduler was specified
1052 /// via the SchedulerRegistry, use it, otherwise select the
1053 /// one preferred by the target.
1055 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1056 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1060 RegisterScheduler::setDefault(Ctor);
1063 return Ctor(this, OptLevel);
1066 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1067 return new ScheduleHazardRecognizer();
1070 //===----------------------------------------------------------------------===//
1071 // Helper functions used by the generated instruction selector.
1072 //===----------------------------------------------------------------------===//
1073 // Calls to these methods are generated by tblgen.
1075 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1076 /// the dag combiner simplified the 255, we still want to match. RHS is the
1077 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1078 /// specified in the .td file (e.g. 255).
1079 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1080 int64_t DesiredMaskS) const {
1081 const APInt &ActualMask = RHS->getAPIntValue();
1082 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1084 // If the actual mask exactly matches, success!
1085 if (ActualMask == DesiredMask)
1088 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1089 if (ActualMask.intersects(~DesiredMask))
1092 // Otherwise, the DAG Combiner may have proven that the value coming in is
1093 // either already zero or is not demanded. Check for known zero input bits.
1094 APInt NeededMask = DesiredMask & ~ActualMask;
1095 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1098 // TODO: check to see if missing bits are just not demanded.
1100 // Otherwise, this pattern doesn't match.
1104 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1105 /// the dag combiner simplified the 255, we still want to match. RHS is the
1106 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1107 /// specified in the .td file (e.g. 255).
1108 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1109 int64_t DesiredMaskS) const {
1110 const APInt &ActualMask = RHS->getAPIntValue();
1111 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1113 // If the actual mask exactly matches, success!
1114 if (ActualMask == DesiredMask)
1117 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1118 if (ActualMask.intersects(~DesiredMask))
1121 // Otherwise, the DAG Combiner may have proven that the value coming in is
1122 // either already zero or is not demanded. Check for known zero input bits.
1123 APInt NeededMask = DesiredMask & ~ActualMask;
1125 APInt KnownZero, KnownOne;
1126 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1128 // If all the missing bits in the or are already known to be set, match!
1129 if ((NeededMask & KnownOne) == NeededMask)
1132 // TODO: check to see if missing bits are just not demanded.
1134 // Otherwise, this pattern doesn't match.
1139 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1140 /// by tblgen. Others should not call it.
1141 void SelectionDAGISel::
1142 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1143 std::vector<SDValue> InOps;
1144 std::swap(InOps, Ops);
1146 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1147 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1148 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1150 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1151 if (InOps[e-1].getValueType() == MVT::Flag)
1152 --e; // Don't process a flag operand if it is here.
1155 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1156 if (!InlineAsm::isMemKind(Flags)) {
1157 // Just skip over this operand, copying the operands verbatim.
1158 Ops.insert(Ops.end(), InOps.begin()+i,
1159 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1160 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1162 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1163 "Memory operand with multiple values?");
1164 // Otherwise, this is a memory operand. Ask the target to select it.
1165 std::vector<SDValue> SelOps;
1166 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1167 report_fatal_error("Could not match memory address. Inline asm"
1170 // Add this to the output node.
1172 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1173 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1174 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1179 // Add the flag input back if present.
1180 if (e != InOps.size())
1181 Ops.push_back(InOps.back());
1184 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1187 static SDNode *findFlagUse(SDNode *N) {
1188 unsigned FlagResNo = N->getNumValues()-1;
1189 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1190 SDUse &Use = I.getUse();
1191 if (Use.getResNo() == FlagResNo)
1192 return Use.getUser();
1197 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1198 /// This function recursively traverses up the operand chain, ignoring
1200 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1201 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1202 bool IgnoreChains) {
1203 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1204 // greater than all of its (recursive) operands. If we scan to a point where
1205 // 'use' is smaller than the node we're scanning for, then we know we will
1208 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1209 // happen because we scan down to newly selected nodes in the case of flag
1211 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1214 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1215 // won't fail if we scan it again.
1216 if (!Visited.insert(Use))
1219 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1220 // Ignore chain uses, they are validated by HandleMergeInputChains.
1221 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1224 SDNode *N = Use->getOperand(i).getNode();
1226 if (Use == ImmedUse || Use == Root)
1227 continue; // We are not looking for immediate use.
1232 // Traverse up the operand chain.
1233 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1239 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1240 /// operand node N of U during instruction selection that starts at Root.
1241 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1242 SDNode *Root) const {
1243 if (OptLevel == CodeGenOpt::None) return false;
1244 return N.hasOneUse();
1247 /// IsLegalToFold - Returns true if the specific operand node N of
1248 /// U can be folded during instruction selection that starts at Root.
1249 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1250 CodeGenOpt::Level OptLevel,
1251 bool IgnoreChains) {
1252 if (OptLevel == CodeGenOpt::None) return false;
1254 // If Root use can somehow reach N through a path that that doesn't contain
1255 // U then folding N would create a cycle. e.g. In the following
1256 // diagram, Root can reach N through X. If N is folded into into Root, then
1257 // X is both a predecessor and a successor of U.
1268 // * indicates nodes to be folded together.
1270 // If Root produces a flag, then it gets (even more) interesting. Since it
1271 // will be "glued" together with its flag use in the scheduler, we need to
1272 // check if it might reach N.
1291 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1292 // (call it Fold), then X is a predecessor of FU and a successor of
1293 // Fold. But since Fold and FU are flagged together, this will create
1294 // a cycle in the scheduling graph.
1296 // If the node has flags, walk down the graph to the "lowest" node in the
1298 EVT VT = Root->getValueType(Root->getNumValues()-1);
1299 while (VT == MVT::Flag) {
1300 SDNode *FU = findFlagUse(Root);
1304 VT = Root->getValueType(Root->getNumValues()-1);
1306 // If our query node has a flag result with a use, we've walked up it. If
1307 // the user (which has already been selected) has a chain or indirectly uses
1308 // the chain, our WalkChainUsers predicate will not consider it. Because of
1309 // this, we cannot ignore chains in this predicate.
1310 IgnoreChains = false;
1314 SmallPtrSet<SDNode*, 16> Visited;
1315 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1318 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1319 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1320 SelectInlineAsmMemoryOperands(Ops);
1322 std::vector<EVT> VTs;
1323 VTs.push_back(MVT::Other);
1324 VTs.push_back(MVT::Flag);
1325 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1326 VTs, &Ops[0], Ops.size());
1328 return New.getNode();
1331 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1332 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1335 /// GetVBR - decode a vbr encoding whose top bit is set.
1336 ALWAYS_INLINE static uint64_t
1337 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1338 assert(Val >= 128 && "Not a VBR");
1339 Val &= 127; // Remove first vbr bit.
1344 NextBits = MatcherTable[Idx++];
1345 Val |= (NextBits&127) << Shift;
1347 } while (NextBits & 128);
1353 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1354 /// interior flag and chain results to use the new flag and chain results.
1355 void SelectionDAGISel::
1356 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1357 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1359 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1360 bool isMorphNodeTo) {
1361 SmallVector<SDNode*, 4> NowDeadNodes;
1363 ISelUpdater ISU(ISelPosition);
1365 // Now that all the normal results are replaced, we replace the chain and
1366 // flag results if present.
1367 if (!ChainNodesMatched.empty()) {
1368 assert(InputChain.getNode() != 0 &&
1369 "Matched input chains but didn't produce a chain");
1370 // Loop over all of the nodes we matched that produced a chain result.
1371 // Replace all the chain results with the final chain we ended up with.
1372 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1373 SDNode *ChainNode = ChainNodesMatched[i];
1375 // If this node was already deleted, don't look at it.
1376 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1379 // Don't replace the results of the root node if we're doing a
1381 if (ChainNode == NodeToMatch && isMorphNodeTo)
1384 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1385 if (ChainVal.getValueType() == MVT::Flag)
1386 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1387 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1388 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1390 // If the node became dead and we haven't already seen it, delete it.
1391 if (ChainNode->use_empty() &&
1392 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1393 NowDeadNodes.push_back(ChainNode);
1397 // If the result produces a flag, update any flag results in the matched
1398 // pattern with the flag result.
1399 if (InputFlag.getNode() != 0) {
1400 // Handle any interior nodes explicitly marked.
1401 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1402 SDNode *FRN = FlagResultNodesMatched[i];
1404 // If this node was already deleted, don't look at it.
1405 if (FRN->getOpcode() == ISD::DELETED_NODE)
1408 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1409 "Doesn't have a flag result");
1410 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1413 // If the node became dead and we haven't already seen it, delete it.
1414 if (FRN->use_empty() &&
1415 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1416 NowDeadNodes.push_back(FRN);
1420 if (!NowDeadNodes.empty())
1421 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1423 DEBUG(errs() << "ISEL: Match complete!\n");
1429 CR_LeadsToInteriorNode
1432 /// WalkChainUsers - Walk down the users of the specified chained node that is
1433 /// part of the pattern we're matching, looking at all of the users we find.
1434 /// This determines whether something is an interior node, whether we have a
1435 /// non-pattern node in between two pattern nodes (which prevent folding because
1436 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1437 /// between pattern nodes (in which case the TF becomes part of the pattern).
1439 /// The walk we do here is guaranteed to be small because we quickly get down to
1440 /// already selected nodes "below" us.
1442 WalkChainUsers(SDNode *ChainedNode,
1443 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1444 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1445 ChainResult Result = CR_Simple;
1447 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1448 E = ChainedNode->use_end(); UI != E; ++UI) {
1449 // Make sure the use is of the chain, not some other value we produce.
1450 if (UI.getUse().getValueType() != MVT::Other) continue;
1454 // If we see an already-selected machine node, then we've gone beyond the
1455 // pattern that we're selecting down into the already selected chunk of the
1457 if (User->isMachineOpcode() ||
1458 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1461 if (User->getOpcode() == ISD::CopyToReg ||
1462 User->getOpcode() == ISD::CopyFromReg ||
1463 User->getOpcode() == ISD::INLINEASM ||
1464 User->getOpcode() == ISD::EH_LABEL) {
1465 // If their node ID got reset to -1 then they've already been selected.
1466 // Treat them like a MachineOpcode.
1467 if (User->getNodeId() == -1)
1471 // If we have a TokenFactor, we handle it specially.
1472 if (User->getOpcode() != ISD::TokenFactor) {
1473 // If the node isn't a token factor and isn't part of our pattern, then it
1474 // must be a random chained node in between two nodes we're selecting.
1475 // This happens when we have something like:
1480 // Because we structurally match the load/store as a read/modify/write,
1481 // but the call is chained between them. We cannot fold in this case
1482 // because it would induce a cycle in the graph.
1483 if (!std::count(ChainedNodesInPattern.begin(),
1484 ChainedNodesInPattern.end(), User))
1485 return CR_InducesCycle;
1487 // Otherwise we found a node that is part of our pattern. For example in:
1491 // This would happen when we're scanning down from the load and see the
1492 // store as a user. Record that there is a use of ChainedNode that is
1493 // part of the pattern and keep scanning uses.
1494 Result = CR_LeadsToInteriorNode;
1495 InteriorChainedNodes.push_back(User);
1499 // If we found a TokenFactor, there are two cases to consider: first if the
1500 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1501 // uses of the TF are in our pattern) we just want to ignore it. Second,
1502 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1508 // | \ DAG's like cheese
1511 // [TokenFactor] [Op]
1518 // In this case, the TokenFactor becomes part of our match and we rewrite it
1519 // as a new TokenFactor.
1521 // To distinguish these two cases, do a recursive walk down the uses.
1522 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1524 // If the uses of the TokenFactor are just already-selected nodes, ignore
1525 // it, it is "below" our pattern.
1527 case CR_InducesCycle:
1528 // If the uses of the TokenFactor lead to nodes that are not part of our
1529 // pattern that are not selected, folding would turn this into a cycle,
1531 return CR_InducesCycle;
1532 case CR_LeadsToInteriorNode:
1533 break; // Otherwise, keep processing.
1536 // Okay, we know we're in the interesting interior case. The TokenFactor
1537 // is now going to be considered part of the pattern so that we rewrite its
1538 // uses (it may have uses that are not part of the pattern) with the
1539 // ultimate chain result of the generated code. We will also add its chain
1540 // inputs as inputs to the ultimate TokenFactor we create.
1541 Result = CR_LeadsToInteriorNode;
1542 ChainedNodesInPattern.push_back(User);
1543 InteriorChainedNodes.push_back(User);
1550 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1551 /// operation for when the pattern matched at least one node with a chains. The
1552 /// input vector contains a list of all of the chained nodes that we match. We
1553 /// must determine if this is a valid thing to cover (i.e. matching it won't
1554 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1555 /// be used as the input node chain for the generated nodes.
1557 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1558 SelectionDAG *CurDAG) {
1559 // Walk all of the chained nodes we've matched, recursively scanning down the
1560 // users of the chain result. This adds any TokenFactor nodes that are caught
1561 // in between chained nodes to the chained and interior nodes list.
1562 SmallVector<SDNode*, 3> InteriorChainedNodes;
1563 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1564 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1565 InteriorChainedNodes) == CR_InducesCycle)
1566 return SDValue(); // Would induce a cycle.
1569 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1570 // that we are interested in. Form our input TokenFactor node.
1571 SmallVector<SDValue, 3> InputChains;
1572 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1573 // Add the input chain of this node to the InputChains list (which will be
1574 // the operands of the generated TokenFactor) if it's not an interior node.
1575 SDNode *N = ChainNodesMatched[i];
1576 if (N->getOpcode() != ISD::TokenFactor) {
1577 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1580 // Otherwise, add the input chain.
1581 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1582 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1583 InputChains.push_back(InChain);
1587 // If we have a token factor, we want to add all inputs of the token factor
1588 // that are not part of the pattern we're matching.
1589 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1590 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1591 N->getOperand(op).getNode()))
1592 InputChains.push_back(N->getOperand(op));
1597 if (InputChains.size() == 1)
1598 return InputChains[0];
1599 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1600 MVT::Other, &InputChains[0], InputChains.size());
1603 /// MorphNode - Handle morphing a node in place for the selector.
1604 SDNode *SelectionDAGISel::
1605 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1606 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1607 // It is possible we're using MorphNodeTo to replace a node with no
1608 // normal results with one that has a normal result (or we could be
1609 // adding a chain) and the input could have flags and chains as well.
1610 // In this case we need to shift the operands down.
1611 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1612 // than the old isel though.
1613 int OldFlagResultNo = -1, OldChainResultNo = -1;
1615 unsigned NTMNumResults = Node->getNumValues();
1616 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1617 OldFlagResultNo = NTMNumResults-1;
1618 if (NTMNumResults != 1 &&
1619 Node->getValueType(NTMNumResults-2) == MVT::Other)
1620 OldChainResultNo = NTMNumResults-2;
1621 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1622 OldChainResultNo = NTMNumResults-1;
1624 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1625 // that this deletes operands of the old node that become dead.
1626 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1628 // MorphNodeTo can operate in two ways: if an existing node with the
1629 // specified operands exists, it can just return it. Otherwise, it
1630 // updates the node in place to have the requested operands.
1632 // If we updated the node in place, reset the node ID. To the isel,
1633 // this should be just like a newly allocated machine node.
1637 unsigned ResNumResults = Res->getNumValues();
1638 // Move the flag if needed.
1639 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1640 (unsigned)OldFlagResultNo != ResNumResults-1)
1641 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1642 SDValue(Res, ResNumResults-1));
1644 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1647 // Move the chain reference if needed.
1648 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1649 (unsigned)OldChainResultNo != ResNumResults-1)
1650 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1651 SDValue(Res, ResNumResults-1));
1653 // Otherwise, no replacement happened because the node already exists. Replace
1654 // Uses of the old node with the new one.
1656 CurDAG->ReplaceAllUsesWith(Node, Res);
1661 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1662 ALWAYS_INLINE static bool
1663 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1664 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1665 // Accept if it is exactly the same as a previously recorded node.
1666 unsigned RecNo = MatcherTable[MatcherIndex++];
1667 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1668 return N == RecordedNodes[RecNo];
1671 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1672 ALWAYS_INLINE static bool
1673 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1674 SelectionDAGISel &SDISel) {
1675 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1678 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1679 ALWAYS_INLINE static bool
1680 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1681 SelectionDAGISel &SDISel, SDNode *N) {
1682 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1685 ALWAYS_INLINE static bool
1686 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1688 uint16_t Opc = MatcherTable[MatcherIndex++];
1689 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1690 return N->getOpcode() == Opc;
1693 ALWAYS_INLINE static bool
1694 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1695 SDValue N, const TargetLowering &TLI) {
1696 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1697 if (N.getValueType() == VT) return true;
1699 // Handle the case when VT is iPTR.
1700 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1703 ALWAYS_INLINE static bool
1704 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1705 SDValue N, const TargetLowering &TLI,
1707 if (ChildNo >= N.getNumOperands())
1708 return false; // Match fails if out of range child #.
1709 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1713 ALWAYS_INLINE static bool
1714 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1716 return cast<CondCodeSDNode>(N)->get() ==
1717 (ISD::CondCode)MatcherTable[MatcherIndex++];
1720 ALWAYS_INLINE static bool
1721 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1722 SDValue N, const TargetLowering &TLI) {
1723 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1724 if (cast<VTSDNode>(N)->getVT() == VT)
1727 // Handle the case when VT is iPTR.
1728 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1731 ALWAYS_INLINE static bool
1732 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1734 int64_t Val = MatcherTable[MatcherIndex++];
1736 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1738 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1739 return C != 0 && C->getSExtValue() == Val;
1742 ALWAYS_INLINE static bool
1743 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1744 SDValue N, SelectionDAGISel &SDISel) {
1745 int64_t Val = MatcherTable[MatcherIndex++];
1747 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1749 if (N->getOpcode() != ISD::AND) return false;
1751 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1752 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1755 ALWAYS_INLINE static bool
1756 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1757 SDValue N, SelectionDAGISel &SDISel) {
1758 int64_t Val = MatcherTable[MatcherIndex++];
1760 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1762 if (N->getOpcode() != ISD::OR) return false;
1764 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1765 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1768 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1769 /// scope, evaluate the current node. If the current predicate is known to
1770 /// fail, set Result=true and return anything. If the current predicate is
1771 /// known to pass, set Result=false and return the MatcherIndex to continue
1772 /// with. If the current predicate is unknown, set Result=false and return the
1773 /// MatcherIndex to continue with.
1774 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1775 unsigned Index, SDValue N,
1776 bool &Result, SelectionDAGISel &SDISel,
1777 SmallVectorImpl<SDValue> &RecordedNodes){
1778 switch (Table[Index++]) {
1781 return Index-1; // Could not evaluate this predicate.
1782 case SelectionDAGISel::OPC_CheckSame:
1783 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1785 case SelectionDAGISel::OPC_CheckPatternPredicate:
1786 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1788 case SelectionDAGISel::OPC_CheckPredicate:
1789 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1791 case SelectionDAGISel::OPC_CheckOpcode:
1792 Result = !::CheckOpcode(Table, Index, N.getNode());
1794 case SelectionDAGISel::OPC_CheckType:
1795 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1797 case SelectionDAGISel::OPC_CheckChild0Type:
1798 case SelectionDAGISel::OPC_CheckChild1Type:
1799 case SelectionDAGISel::OPC_CheckChild2Type:
1800 case SelectionDAGISel::OPC_CheckChild3Type:
1801 case SelectionDAGISel::OPC_CheckChild4Type:
1802 case SelectionDAGISel::OPC_CheckChild5Type:
1803 case SelectionDAGISel::OPC_CheckChild6Type:
1804 case SelectionDAGISel::OPC_CheckChild7Type:
1805 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1806 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1808 case SelectionDAGISel::OPC_CheckCondCode:
1809 Result = !::CheckCondCode(Table, Index, N);
1811 case SelectionDAGISel::OPC_CheckValueType:
1812 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1814 case SelectionDAGISel::OPC_CheckInteger:
1815 Result = !::CheckInteger(Table, Index, N);
1817 case SelectionDAGISel::OPC_CheckAndImm:
1818 Result = !::CheckAndImm(Table, Index, N, SDISel);
1820 case SelectionDAGISel::OPC_CheckOrImm:
1821 Result = !::CheckOrImm(Table, Index, N, SDISel);
1829 /// FailIndex - If this match fails, this is the index to continue with.
1832 /// NodeStack - The node stack when the scope was formed.
1833 SmallVector<SDValue, 4> NodeStack;
1835 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1836 unsigned NumRecordedNodes;
1838 /// NumMatchedMemRefs - The number of matched memref entries.
1839 unsigned NumMatchedMemRefs;
1841 /// InputChain/InputFlag - The current chain/flag
1842 SDValue InputChain, InputFlag;
1844 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1845 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1850 SDNode *SelectionDAGISel::
1851 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1852 unsigned TableSize) {
1853 // FIXME: Should these even be selected? Handle these cases in the caller?
1854 switch (NodeToMatch->getOpcode()) {
1857 case ISD::EntryToken: // These nodes remain the same.
1858 case ISD::BasicBlock:
1860 //case ISD::VALUETYPE:
1861 //case ISD::CONDCODE:
1862 case ISD::HANDLENODE:
1863 case ISD::MDNODE_SDNODE:
1864 case ISD::TargetConstant:
1865 case ISD::TargetConstantFP:
1866 case ISD::TargetConstantPool:
1867 case ISD::TargetFrameIndex:
1868 case ISD::TargetExternalSymbol:
1869 case ISD::TargetBlockAddress:
1870 case ISD::TargetJumpTable:
1871 case ISD::TargetGlobalTLSAddress:
1872 case ISD::TargetGlobalAddress:
1873 case ISD::TokenFactor:
1874 case ISD::CopyFromReg:
1875 case ISD::CopyToReg:
1877 NodeToMatch->setNodeId(-1); // Mark selected.
1879 case ISD::AssertSext:
1880 case ISD::AssertZext:
1881 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1882 NodeToMatch->getOperand(0));
1884 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1885 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1888 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1890 // Set up the node stack with NodeToMatch as the only node on the stack.
1891 SmallVector<SDValue, 8> NodeStack;
1892 SDValue N = SDValue(NodeToMatch, 0);
1893 NodeStack.push_back(N);
1895 // MatchScopes - Scopes used when matching, if a match failure happens, this
1896 // indicates where to continue checking.
1897 SmallVector<MatchScope, 8> MatchScopes;
1899 // RecordedNodes - This is the set of nodes that have been recorded by the
1901 SmallVector<SDValue, 8> RecordedNodes;
1903 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1905 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1907 // These are the current input chain and flag for use when generating nodes.
1908 // Various Emit operations change these. For example, emitting a copytoreg
1909 // uses and updates these.
1910 SDValue InputChain, InputFlag;
1912 // ChainNodesMatched - If a pattern matches nodes that have input/output
1913 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1914 // which ones they are. The result is captured into this list so that we can
1915 // update the chain results when the pattern is complete.
1916 SmallVector<SDNode*, 3> ChainNodesMatched;
1917 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1919 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1920 NodeToMatch->dump(CurDAG);
1923 // Determine where to start the interpreter. Normally we start at opcode #0,
1924 // but if the state machine starts with an OPC_SwitchOpcode, then we
1925 // accelerate the first lookup (which is guaranteed to be hot) with the
1926 // OpcodeOffset table.
1927 unsigned MatcherIndex = 0;
1929 if (!OpcodeOffset.empty()) {
1930 // Already computed the OpcodeOffset table, just index into it.
1931 if (N.getOpcode() < OpcodeOffset.size())
1932 MatcherIndex = OpcodeOffset[N.getOpcode()];
1933 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1935 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1936 // Otherwise, the table isn't computed, but the state machine does start
1937 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1938 // is the first time we're selecting an instruction.
1941 // Get the size of this case.
1942 unsigned CaseSize = MatcherTable[Idx++];
1944 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1945 if (CaseSize == 0) break;
1947 // Get the opcode, add the index to the table.
1948 uint16_t Opc = MatcherTable[Idx++];
1949 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1950 if (Opc >= OpcodeOffset.size())
1951 OpcodeOffset.resize((Opc+1)*2);
1952 OpcodeOffset[Opc] = Idx;
1956 // Okay, do the lookup for the first opcode.
1957 if (N.getOpcode() < OpcodeOffset.size())
1958 MatcherIndex = OpcodeOffset[N.getOpcode()];
1962 assert(MatcherIndex < TableSize && "Invalid index");
1964 unsigned CurrentOpcodeIndex = MatcherIndex;
1966 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1969 // Okay, the semantics of this operation are that we should push a scope
1970 // then evaluate the first child. However, pushing a scope only to have
1971 // the first check fail (which then pops it) is inefficient. If we can
1972 // determine immediately that the first check (or first several) will
1973 // immediately fail, don't even bother pushing a scope for them.
1977 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1978 if (NumToSkip & 128)
1979 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1980 // Found the end of the scope with no match.
1981 if (NumToSkip == 0) {
1986 FailIndex = MatcherIndex+NumToSkip;
1988 unsigned MatcherIndexOfPredicate = MatcherIndex;
1989 (void)MatcherIndexOfPredicate; // silence warning.
1991 // If we can't evaluate this predicate without pushing a scope (e.g. if
1992 // it is a 'MoveParent') or if the predicate succeeds on this node, we
1993 // push the scope and evaluate the full predicate chain.
1995 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
1996 Result, *this, RecordedNodes);
2000 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2001 << "index " << MatcherIndexOfPredicate
2002 << ", continuing at " << FailIndex << "\n");
2003 ++NumDAGIselRetries;
2005 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2006 // move to the next case.
2007 MatcherIndex = FailIndex;
2010 // If the whole scope failed to match, bail.
2011 if (FailIndex == 0) break;
2013 // Push a MatchScope which indicates where to go if the first child fails
2015 MatchScope NewEntry;
2016 NewEntry.FailIndex = FailIndex;
2017 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2018 NewEntry.NumRecordedNodes = RecordedNodes.size();
2019 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2020 NewEntry.InputChain = InputChain;
2021 NewEntry.InputFlag = InputFlag;
2022 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2023 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2024 MatchScopes.push_back(NewEntry);
2027 case OPC_RecordNode:
2028 // Remember this node, it may end up being an operand in the pattern.
2029 RecordedNodes.push_back(N);
2032 case OPC_RecordChild0: case OPC_RecordChild1:
2033 case OPC_RecordChild2: case OPC_RecordChild3:
2034 case OPC_RecordChild4: case OPC_RecordChild5:
2035 case OPC_RecordChild6: case OPC_RecordChild7: {
2036 unsigned ChildNo = Opcode-OPC_RecordChild0;
2037 if (ChildNo >= N.getNumOperands())
2038 break; // Match fails if out of range child #.
2040 RecordedNodes.push_back(N->getOperand(ChildNo));
2043 case OPC_RecordMemRef:
2044 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2047 case OPC_CaptureFlagInput:
2048 // If the current node has an input flag, capture it in InputFlag.
2049 if (N->getNumOperands() != 0 &&
2050 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2051 InputFlag = N->getOperand(N->getNumOperands()-1);
2054 case OPC_MoveChild: {
2055 unsigned ChildNo = MatcherTable[MatcherIndex++];
2056 if (ChildNo >= N.getNumOperands())
2057 break; // Match fails if out of range child #.
2058 N = N.getOperand(ChildNo);
2059 NodeStack.push_back(N);
2063 case OPC_MoveParent:
2064 // Pop the current node off the NodeStack.
2065 NodeStack.pop_back();
2066 assert(!NodeStack.empty() && "Node stack imbalance!");
2067 N = NodeStack.back();
2071 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2073 case OPC_CheckPatternPredicate:
2074 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2076 case OPC_CheckPredicate:
2077 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2081 case OPC_CheckComplexPat: {
2082 unsigned CPNum = MatcherTable[MatcherIndex++];
2083 unsigned RecNo = MatcherTable[MatcherIndex++];
2084 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2085 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2090 case OPC_CheckOpcode:
2091 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2095 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2098 case OPC_SwitchOpcode: {
2099 unsigned CurNodeOpcode = N.getOpcode();
2100 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2103 // Get the size of this case.
2104 CaseSize = MatcherTable[MatcherIndex++];
2106 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2107 if (CaseSize == 0) break;
2109 uint16_t Opc = MatcherTable[MatcherIndex++];
2110 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2112 // If the opcode matches, then we will execute this case.
2113 if (CurNodeOpcode == Opc)
2116 // Otherwise, skip over this case.
2117 MatcherIndex += CaseSize;
2120 // If no cases matched, bail out.
2121 if (CaseSize == 0) break;
2123 // Otherwise, execute the case we found.
2124 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2125 << " to " << MatcherIndex << "\n");
2129 case OPC_SwitchType: {
2130 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2131 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2134 // Get the size of this case.
2135 CaseSize = MatcherTable[MatcherIndex++];
2137 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2138 if (CaseSize == 0) break;
2140 MVT::SimpleValueType CaseVT =
2141 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2142 if (CaseVT == MVT::iPTR)
2143 CaseVT = TLI.getPointerTy().SimpleTy;
2145 // If the VT matches, then we will execute this case.
2146 if (CurNodeVT == CaseVT)
2149 // Otherwise, skip over this case.
2150 MatcherIndex += CaseSize;
2153 // If no cases matched, bail out.
2154 if (CaseSize == 0) break;
2156 // Otherwise, execute the case we found.
2157 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2158 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2161 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2162 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2163 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2164 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2165 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2166 Opcode-OPC_CheckChild0Type))
2169 case OPC_CheckCondCode:
2170 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2172 case OPC_CheckValueType:
2173 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2175 case OPC_CheckInteger:
2176 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2178 case OPC_CheckAndImm:
2179 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2181 case OPC_CheckOrImm:
2182 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2185 case OPC_CheckFoldableChainNode: {
2186 assert(NodeStack.size() != 1 && "No parent node");
2187 // Verify that all intermediate nodes between the root and this one have
2189 bool HasMultipleUses = false;
2190 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2191 if (!NodeStack[i].hasOneUse()) {
2192 HasMultipleUses = true;
2195 if (HasMultipleUses) break;
2197 // Check to see that the target thinks this is profitable to fold and that
2198 // we can fold it without inducing cycles in the graph.
2199 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2201 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2202 NodeToMatch, OptLevel,
2203 true/*We validate our own chains*/))
2208 case OPC_EmitInteger: {
2209 MVT::SimpleValueType VT =
2210 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2211 int64_t Val = MatcherTable[MatcherIndex++];
2213 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2214 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2217 case OPC_EmitRegister: {
2218 MVT::SimpleValueType VT =
2219 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2220 unsigned RegNo = MatcherTable[MatcherIndex++];
2221 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2225 case OPC_EmitConvertToTarget: {
2226 // Convert from IMM/FPIMM to target version.
2227 unsigned RecNo = MatcherTable[MatcherIndex++];
2228 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2229 SDValue Imm = RecordedNodes[RecNo];
2231 if (Imm->getOpcode() == ISD::Constant) {
2232 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2233 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2234 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2235 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2236 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2239 RecordedNodes.push_back(Imm);
2243 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2244 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2245 // These are space-optimized forms of OPC_EmitMergeInputChains.
2246 assert(InputChain.getNode() == 0 &&
2247 "EmitMergeInputChains should be the first chain producing node");
2248 assert(ChainNodesMatched.empty() &&
2249 "Should only have one EmitMergeInputChains per match");
2251 // Read all of the chained nodes.
2252 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2253 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2254 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2256 // FIXME: What if other value results of the node have uses not matched
2258 if (ChainNodesMatched.back() != NodeToMatch &&
2259 !RecordedNodes[RecNo].hasOneUse()) {
2260 ChainNodesMatched.clear();
2264 // Merge the input chains if they are not intra-pattern references.
2265 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2267 if (InputChain.getNode() == 0)
2268 break; // Failed to merge.
2272 case OPC_EmitMergeInputChains: {
2273 assert(InputChain.getNode() == 0 &&
2274 "EmitMergeInputChains should be the first chain producing node");
2275 // This node gets a list of nodes we matched in the input that have
2276 // chains. We want to token factor all of the input chains to these nodes
2277 // together. However, if any of the input chains is actually one of the
2278 // nodes matched in this pattern, then we have an intra-match reference.
2279 // Ignore these because the newly token factored chain should not refer to
2281 unsigned NumChains = MatcherTable[MatcherIndex++];
2282 assert(NumChains != 0 && "Can't TF zero chains");
2284 assert(ChainNodesMatched.empty() &&
2285 "Should only have one EmitMergeInputChains per match");
2287 // Read all of the chained nodes.
2288 for (unsigned i = 0; i != NumChains; ++i) {
2289 unsigned RecNo = MatcherTable[MatcherIndex++];
2290 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2291 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2293 // FIXME: What if other value results of the node have uses not matched
2295 if (ChainNodesMatched.back() != NodeToMatch &&
2296 !RecordedNodes[RecNo].hasOneUse()) {
2297 ChainNodesMatched.clear();
2302 // If the inner loop broke out, the match fails.
2303 if (ChainNodesMatched.empty())
2306 // Merge the input chains if they are not intra-pattern references.
2307 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2309 if (InputChain.getNode() == 0)
2310 break; // Failed to merge.
2315 case OPC_EmitCopyToReg: {
2316 unsigned RecNo = MatcherTable[MatcherIndex++];
2317 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2318 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2320 if (InputChain.getNode() == 0)
2321 InputChain = CurDAG->getEntryNode();
2323 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2324 DestPhysReg, RecordedNodes[RecNo],
2327 InputFlag = InputChain.getValue(1);
2331 case OPC_EmitNodeXForm: {
2332 unsigned XFormNo = MatcherTable[MatcherIndex++];
2333 unsigned RecNo = MatcherTable[MatcherIndex++];
2334 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2335 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2340 case OPC_MorphNodeTo: {
2341 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2342 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2343 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2344 // Get the result VT list.
2345 unsigned NumVTs = MatcherTable[MatcherIndex++];
2346 SmallVector<EVT, 4> VTs;
2347 for (unsigned i = 0; i != NumVTs; ++i) {
2348 MVT::SimpleValueType VT =
2349 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2350 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2354 if (EmitNodeInfo & OPFL_Chain)
2355 VTs.push_back(MVT::Other);
2356 if (EmitNodeInfo & OPFL_FlagOutput)
2357 VTs.push_back(MVT::Flag);
2359 // This is hot code, so optimize the two most common cases of 1 and 2
2362 if (VTs.size() == 1)
2363 VTList = CurDAG->getVTList(VTs[0]);
2364 else if (VTs.size() == 2)
2365 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2367 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2369 // Get the operand list.
2370 unsigned NumOps = MatcherTable[MatcherIndex++];
2371 SmallVector<SDValue, 8> Ops;
2372 for (unsigned i = 0; i != NumOps; ++i) {
2373 unsigned RecNo = MatcherTable[MatcherIndex++];
2375 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2377 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2378 Ops.push_back(RecordedNodes[RecNo]);
2381 // If there are variadic operands to add, handle them now.
2382 if (EmitNodeInfo & OPFL_VariadicInfo) {
2383 // Determine the start index to copy from.
2384 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2385 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2386 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2387 "Invalid variadic node");
2388 // Copy all of the variadic operands, not including a potential flag
2390 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2392 SDValue V = NodeToMatch->getOperand(i);
2393 if (V.getValueType() == MVT::Flag) break;
2398 // If this has chain/flag inputs, add them.
2399 if (EmitNodeInfo & OPFL_Chain)
2400 Ops.push_back(InputChain);
2401 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2402 Ops.push_back(InputFlag);
2406 if (Opcode != OPC_MorphNodeTo) {
2407 // If this is a normal EmitNode command, just create the new node and
2408 // add the results to the RecordedNodes list.
2409 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2410 VTList, Ops.data(), Ops.size());
2412 // Add all the non-flag/non-chain results to the RecordedNodes list.
2413 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2414 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2415 RecordedNodes.push_back(SDValue(Res, i));
2419 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2423 // If the node had chain/flag results, update our notion of the current
2425 if (EmitNodeInfo & OPFL_FlagOutput) {
2426 InputFlag = SDValue(Res, VTs.size()-1);
2427 if (EmitNodeInfo & OPFL_Chain)
2428 InputChain = SDValue(Res, VTs.size()-2);
2429 } else if (EmitNodeInfo & OPFL_Chain)
2430 InputChain = SDValue(Res, VTs.size()-1);
2432 // If the OPFL_MemRefs flag is set on this node, slap all of the
2433 // accumulated memrefs onto it.
2435 // FIXME: This is vastly incorrect for patterns with multiple outputs
2436 // instructions that access memory and for ComplexPatterns that match
2438 if (EmitNodeInfo & OPFL_MemRefs) {
2439 MachineSDNode::mmo_iterator MemRefs =
2440 MF->allocateMemRefsArray(MatchedMemRefs.size());
2441 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2442 cast<MachineSDNode>(Res)
2443 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2447 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2448 << " node: "; Res->dump(CurDAG); errs() << "\n");
2450 // If this was a MorphNodeTo then we're completely done!
2451 if (Opcode == OPC_MorphNodeTo) {
2452 // Update chain and flag uses.
2453 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2454 InputFlag, FlagResultNodesMatched, true);
2461 case OPC_MarkFlagResults: {
2462 unsigned NumNodes = MatcherTable[MatcherIndex++];
2464 // Read and remember all the flag-result nodes.
2465 for (unsigned i = 0; i != NumNodes; ++i) {
2466 unsigned RecNo = MatcherTable[MatcherIndex++];
2468 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2470 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2471 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2476 case OPC_CompleteMatch: {
2477 // The match has been completed, and any new nodes (if any) have been
2478 // created. Patch up references to the matched dag to use the newly
2480 unsigned NumResults = MatcherTable[MatcherIndex++];
2482 for (unsigned i = 0; i != NumResults; ++i) {
2483 unsigned ResSlot = MatcherTable[MatcherIndex++];
2485 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2487 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2488 SDValue Res = RecordedNodes[ResSlot];
2490 assert(i < NodeToMatch->getNumValues() &&
2491 NodeToMatch->getValueType(i) != MVT::Other &&
2492 NodeToMatch->getValueType(i) != MVT::Flag &&
2493 "Invalid number of results to complete!");
2494 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2495 NodeToMatch->getValueType(i) == MVT::iPTR ||
2496 Res.getValueType() == MVT::iPTR ||
2497 NodeToMatch->getValueType(i).getSizeInBits() ==
2498 Res.getValueType().getSizeInBits()) &&
2499 "invalid replacement");
2500 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2503 // If the root node defines a flag, add it to the flag nodes to update
2505 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2506 FlagResultNodesMatched.push_back(NodeToMatch);
2508 // Update chain and flag uses.
2509 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2510 InputFlag, FlagResultNodesMatched, false);
2512 assert(NodeToMatch->use_empty() &&
2513 "Didn't replace all uses of the node?");
2515 // FIXME: We just return here, which interacts correctly with SelectRoot
2516 // above. We should fix this to not return an SDNode* anymore.
2521 // If the code reached this point, then the match failed. See if there is
2522 // another child to try in the current 'Scope', otherwise pop it until we
2523 // find a case to check.
2524 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2525 ++NumDAGIselRetries;
2527 if (MatchScopes.empty()) {
2528 CannotYetSelect(NodeToMatch);
2532 // Restore the interpreter state back to the point where the scope was
2534 MatchScope &LastScope = MatchScopes.back();
2535 RecordedNodes.resize(LastScope.NumRecordedNodes);
2537 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2538 N = NodeStack.back();
2540 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2541 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2542 MatcherIndex = LastScope.FailIndex;
2544 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2546 InputChain = LastScope.InputChain;
2547 InputFlag = LastScope.InputFlag;
2548 if (!LastScope.HasChainNodesMatched)
2549 ChainNodesMatched.clear();
2550 if (!LastScope.HasFlagResultNodesMatched)
2551 FlagResultNodesMatched.clear();
2553 // Check to see what the offset is at the new MatcherIndex. If it is zero
2554 // we have reached the end of this scope, otherwise we have another child
2555 // in the current scope to try.
2556 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2557 if (NumToSkip & 128)
2558 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2560 // If we have another child in this scope to match, update FailIndex and
2562 if (NumToSkip != 0) {
2563 LastScope.FailIndex = MatcherIndex+NumToSkip;
2567 // End of this scope, pop it and try the next child in the containing
2569 MatchScopes.pop_back();
2576 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2578 raw_string_ostream Msg(msg);
2579 Msg << "Cannot yet select: ";
2581 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2582 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2583 N->getOpcode() != ISD::INTRINSIC_VOID) {
2584 N->printrFull(Msg, CurDAG);
2586 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2588 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2589 if (iid < Intrinsic::num_intrinsics)
2590 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2591 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2592 Msg << "target intrinsic %" << TII->getName(iid);
2594 Msg << "unknown intrinsic #" << iid;
2596 report_fatal_error(Msg.str());
2599 char SelectionDAGISel::ID = 0;