1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/ADT/Statistic.h"
55 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
56 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
59 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
60 cl::desc("Enable verbose messages in the \"fast\" "
61 "instruction selector"));
63 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
64 cl::desc("Enable abort calls when \"fast\" instruction fails"));
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before the post legalize types"
84 " dag combine pass"));
86 ViewISelDAGs("view-isel-dags", cl::Hidden,
87 cl::desc("Pop up a window to show isel dags as they are selected"));
89 ViewSchedDAGs("view-sched-dags", cl::Hidden,
90 cl::desc("Pop up a window to show sched dags as they are processed"));
92 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
93 cl::desc("Pop up a window to show SUnit dags after they are processed"));
95 static const bool ViewDAGCombine1 = false,
96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
97 ViewDAGCombine2 = false,
98 ViewDAGCombineLT = false,
99 ViewISelDAGs = false, ViewSchedDAGs = false,
100 ViewSUnitDAGs = false;
103 //===---------------------------------------------------------------------===//
105 /// RegisterScheduler class - Track the registration of instruction schedulers.
107 //===---------------------------------------------------------------------===//
108 MachinePassRegistry RegisterScheduler::Registry;
110 //===---------------------------------------------------------------------===//
112 /// ISHeuristic command line option for instruction schedulers.
114 //===---------------------------------------------------------------------===//
115 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
116 RegisterPassParser<RegisterScheduler> >
117 ISHeuristic("pre-RA-sched",
118 cl::init(&createDefaultScheduler),
119 cl::desc("Instruction schedulers available (before register"
122 static RegisterScheduler
123 defaultListDAGScheduler("default", "Best scheduler for the target",
124 createDefaultScheduler);
127 //===--------------------------------------------------------------------===//
128 /// createDefaultScheduler - This creates an instruction scheduler appropriate
130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
131 CodeGenOpt::Level OptLevel) {
132 const TargetLowering &TLI = IS->getTargetLowering();
134 if (OptLevel == CodeGenOpt::None)
135 return createSourceListDAGScheduler(IS, OptLevel);
136 if (TLI.getSchedulingPreference() == Sched::Latency)
137 return createTDListDAGScheduler(IS, OptLevel);
138 if (TLI.getSchedulingPreference() == Sched::RegPressure)
139 return createBURRListDAGScheduler(IS, OptLevel);
140 if (TLI.getSchedulingPreference() == Sched::Hybrid)
141 return createHybridListDAGScheduler(IS, OptLevel);
142 assert(TLI.getSchedulingPreference() == Sched::ILP &&
143 "Unknown sched type!");
144 return createILPListDAGScheduler(IS, OptLevel);
148 // EmitInstrWithCustomInserter - This method should be implemented by targets
149 // that mark instructions with the 'usesCustomInserter' flag. These
150 // instructions are special in various ways, which require special support to
151 // insert. The specified MachineInstr is created but not inserted into any
152 // basic blocks, and this method is called to expand it into a sequence of
153 // instructions, potentially also creating new basic blocks and control flow.
154 // When new basic blocks are inserted and the edges from MBB to its successors
155 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
158 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
159 MachineBasicBlock *MBB) const {
161 dbgs() << "If a target marks an instruction with "
162 "'usesCustomInserter', it must implement "
163 "TargetLowering::EmitInstrWithCustomInserter!";
169 //===----------------------------------------------------------------------===//
170 // SelectionDAGISel code
171 //===----------------------------------------------------------------------===//
173 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
174 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
175 FuncInfo(new FunctionLoweringInfo(TLI)),
176 CurDAG(new SelectionDAG(tm)),
177 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
183 SelectionDAGISel::~SelectionDAGISel() {
189 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
190 AU.addRequired<AliasAnalysis>();
191 AU.addPreserved<AliasAnalysis>();
192 AU.addRequired<GCModuleInfo>();
193 AU.addPreserved<GCModuleInfo>();
194 MachineFunctionPass::getAnalysisUsage(AU);
197 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
198 /// other function that gcc recognizes as "returning twice". This is used to
199 /// limit code-gen optimizations on the machine function.
201 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
202 static bool FunctionCallsSetJmp(const Function *F) {
203 const Module *M = F->getParent();
204 static const char *ReturnsTwiceFns[] = {
213 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
215 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
216 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
217 if (!Callee->use_empty())
218 for (Value::const_use_iterator
219 I = Callee->use_begin(), E = Callee->use_end();
221 if (const CallInst *CI = dyn_cast<CallInst>(*I))
222 if (CI->getParent()->getParent() == F)
227 #undef NUM_RETURNS_TWICE_FNS
230 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
231 // Do some sanity-checking on the command-line options.
232 assert((!EnableFastISelVerbose || EnableFastISel) &&
233 "-fast-isel-verbose requires -fast-isel");
234 assert((!EnableFastISelAbort || EnableFastISel) &&
235 "-fast-isel-abort requires -fast-isel");
237 const Function &Fn = *mf.getFunction();
238 const TargetInstrInfo &TII = *TM.getInstrInfo();
239 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
242 RegInfo = &MF->getRegInfo();
243 AA = &getAnalysis<AliasAnalysis>();
244 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
246 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
249 FuncInfo->set(Fn, *MF);
252 SelectAllBasicBlocks(Fn);
254 // If the first basic block in the function has live ins that need to be
255 // copied into vregs, emit the copies into the top of the block before
256 // emitting the code for the block.
257 MachineBasicBlock *EntryMBB = MF->begin();
258 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
260 DenseMap<unsigned, unsigned> LiveInMap;
261 if (!FuncInfo->ArgDbgValues.empty())
262 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
263 E = RegInfo->livein_end(); LI != E; ++LI)
265 LiveInMap.insert(std::make_pair(LI->first, LI->second));
267 // Insert DBG_VALUE instructions for function arguments to the entry block.
268 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
269 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
270 unsigned Reg = MI->getOperand(0).getReg();
271 if (TargetRegisterInfo::isPhysicalRegister(Reg))
272 EntryMBB->insert(EntryMBB->begin(), MI);
274 MachineInstr *Def = RegInfo->getVRegDef(Reg);
275 MachineBasicBlock::iterator InsertPos = Def;
276 // FIXME: VR def may not be in entry block.
277 Def->getParent()->insert(llvm::next(InsertPos), MI);
280 // If Reg is live-in then update debug info to track its copy in a vreg.
281 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
282 if (LDI != LiveInMap.end()) {
283 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
284 MachineBasicBlock::iterator InsertPos = Def;
285 const MDNode *Variable =
286 MI->getOperand(MI->getNumOperands()-1).getMetadata();
287 unsigned Offset = MI->getOperand(1).getImm();
288 // Def is never a terminator here, so it is ok to increment InsertPos.
289 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
290 TII.get(TargetOpcode::DBG_VALUE))
291 .addReg(LDI->second, RegState::Debug)
292 .addImm(Offset).addMetadata(Variable);
296 // Determine if there are any calls in this machine function.
297 MachineFrameInfo *MFI = MF->getFrameInfo();
298 if (!MFI->hasCalls()) {
299 for (MachineFunction::const_iterator
300 I = MF->begin(), E = MF->end(); I != E; ++I) {
301 const MachineBasicBlock *MBB = I;
302 for (MachineBasicBlock::const_iterator
303 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
304 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
306 // Operand 1 of an inline asm instruction indicates whether the asm
307 // needs stack or not.
308 if ((II->isInlineAsm() && II->getOperand(1).getImm()) ||
309 (TID.isCall() && !TID.isReturn())) {
310 MFI->setHasCalls(true);
318 // Determine if there is a call to setjmp in the machine function.
319 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
321 // Replace forward-declared registers with the registers containing
322 // the desired value.
323 MachineRegisterInfo &MRI = MF->getRegInfo();
324 for (DenseMap<unsigned, unsigned>::iterator
325 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
327 unsigned From = I->first;
328 unsigned To = I->second;
329 // If To is also scheduled to be replaced, find what its ultimate
332 DenseMap<unsigned, unsigned>::iterator J =
333 FuncInfo->RegFixups.find(To);
338 MRI.replaceRegWith(From, To);
341 // Release function-specific state. SDB and CurDAG are already cleared
349 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
350 BasicBlock::const_iterator End,
352 // Lower all of the non-terminator instructions. If a call is emitted
353 // as a tail call, cease emitting nodes for this block. Terminators
354 // are handled below.
355 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
358 // Make sure the root of the DAG is up-to-date.
359 CurDAG->setRoot(SDB->getControlRoot());
360 HadTailCall = SDB->HasTailCall;
363 // Final step, emit the lowered DAG as machine code.
368 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
369 /// nodes from the worklist.
370 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
371 SmallVector<SDNode*, 128> &Worklist;
372 SmallPtrSet<SDNode*, 128> &InWorklist;
374 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
375 SmallPtrSet<SDNode*, 128> &inwl)
376 : Worklist(wl), InWorklist(inwl) {}
378 void RemoveFromWorklist(SDNode *N) {
379 if (!InWorklist.erase(N)) return;
381 SmallVector<SDNode*, 128>::iterator I =
382 std::find(Worklist.begin(), Worklist.end(), N);
383 assert(I != Worklist.end() && "Not in worklist");
385 *I = Worklist.back();
389 virtual void NodeDeleted(SDNode *N, SDNode *E) {
390 RemoveFromWorklist(N);
393 virtual void NodeUpdated(SDNode *N) {
399 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
400 SmallPtrSet<SDNode*, 128> VisitedNodes;
401 SmallVector<SDNode*, 128> Worklist;
403 Worklist.push_back(CurDAG->getRoot().getNode());
410 SDNode *N = Worklist.pop_back_val();
412 // If we've already seen this node, ignore it.
413 if (!VisitedNodes.insert(N))
416 // Otherwise, add all chain operands to the worklist.
417 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
418 if (N->getOperand(i).getValueType() == MVT::Other)
419 Worklist.push_back(N->getOperand(i).getNode());
421 // If this is a CopyToReg with a vreg dest, process it.
422 if (N->getOpcode() != ISD::CopyToReg)
425 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
426 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
429 // Ignore non-scalar or non-integer values.
430 SDValue Src = N->getOperand(2);
431 EVT SrcVT = Src.getValueType();
432 if (!SrcVT.isInteger() || SrcVT.isVector())
435 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
436 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
437 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
439 // Only install this information if it tells us something.
440 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
441 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
442 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
443 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
444 FunctionLoweringInfo::LiveOutInfo &LOI =
445 FuncInfo->LiveOutRegInfo[DestReg];
446 LOI.NumSignBits = NumSignBits;
447 LOI.KnownOne = KnownOne;
448 LOI.KnownZero = KnownZero;
450 } while (!Worklist.empty());
453 void SelectionDAGISel::CodeGenAndEmitDAG() {
454 std::string GroupName;
455 if (TimePassesIsEnabled)
456 GroupName = "Instruction Selection and Scheduling";
457 std::string BlockName;
458 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
459 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
461 BlockName = MF->getFunction()->getNameStr() + ":" +
462 FuncInfo->MBB->getBasicBlock()->getNameStr();
464 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
466 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
468 // Run the DAG combiner in pre-legalize mode.
470 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
471 CurDAG->Combine(Unrestricted, *AA, OptLevel);
474 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
476 // Second step, hack on the DAG until it only uses operations and types that
477 // the target supports.
478 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
483 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
484 Changed = CurDAG->LegalizeTypes();
487 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
490 if (ViewDAGCombineLT)
491 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
493 // Run the DAG combiner in post-type-legalize mode.
495 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
496 TimePassesIsEnabled);
497 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
500 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
505 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
506 Changed = CurDAG->LegalizeVectors();
511 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
512 CurDAG->LegalizeTypes();
515 if (ViewDAGCombineLT)
516 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
518 // Run the DAG combiner in post-type-legalize mode.
520 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
521 TimePassesIsEnabled);
522 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
525 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
529 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
532 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
533 CurDAG->Legalize(OptLevel);
536 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
538 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
540 // Run the DAG combiner in post-legalize mode.
542 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
543 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
546 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
548 if (OptLevel != CodeGenOpt::None)
549 ComputeLiveOutVRegInfo();
551 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
553 // Third, instruction select all of the operations to machine code, adding the
554 // code to the MachineBasicBlock.
556 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
557 DoInstructionSelection();
560 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
562 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
564 // Schedule machine code.
565 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
567 NamedRegionTimer T("Instruction Scheduling", GroupName,
568 TimePassesIsEnabled);
569 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
572 if (ViewSUnitDAGs) Scheduler->viewGraph();
574 // Emit machine code to BB. This can change 'BB' to the last block being
577 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
579 FuncInfo->MBB = Scheduler->EmitSchedule();
580 FuncInfo->InsertPt = Scheduler->InsertPos;
583 // Free the scheduler state.
585 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
586 TimePassesIsEnabled);
590 // Free the SelectionDAG state, now that we're finished with it.
594 void SelectionDAGISel::DoInstructionSelection() {
595 DEBUG(errs() << "===== Instruction selection begins:\n");
599 // Select target instructions for the DAG.
601 // Number all nodes with a topological order and set DAGSize.
602 DAGSize = CurDAG->AssignTopologicalOrder();
604 // Create a dummy node (which is not added to allnodes), that adds
605 // a reference to the root node, preventing it from being deleted,
606 // and tracking any changes of the root.
607 HandleSDNode Dummy(CurDAG->getRoot());
608 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
611 // The AllNodes list is now topological-sorted. Visit the
612 // nodes by starting at the end of the list (the root of the
613 // graph) and preceding back toward the beginning (the entry
615 while (ISelPosition != CurDAG->allnodes_begin()) {
616 SDNode *Node = --ISelPosition;
617 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
618 // but there are currently some corner cases that it misses. Also, this
619 // makes it theoretically possible to disable the DAGCombiner.
620 if (Node->use_empty())
623 SDNode *ResNode = Select(Node);
625 // FIXME: This is pretty gross. 'Select' should be changed to not return
626 // anything at all and this code should be nuked with a tactical strike.
628 // If node should not be replaced, continue with the next one.
629 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
633 ReplaceUses(Node, ResNode);
635 // If after the replacement this node is not used any more,
636 // remove this dead node.
637 if (Node->use_empty()) { // Don't delete EntryToken, etc.
638 ISelUpdater ISU(ISelPosition);
639 CurDAG->RemoveDeadNode(Node, &ISU);
643 CurDAG->setRoot(Dummy.getValue());
646 DEBUG(errs() << "===== Instruction selection ends:\n");
648 PostprocessISelDAG();
651 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
652 /// do other setup for EH landing-pad blocks.
653 void SelectionDAGISel::PrepareEHLandingPad() {
654 // Add a label to mark the beginning of the landing pad. Deletion of the
655 // landing pad can thus be detected via the MachineModuleInfo.
656 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
658 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
659 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
662 // Mark exception register as live in.
663 unsigned Reg = TLI.getExceptionAddressRegister();
664 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
666 // Mark exception selector register as live in.
667 Reg = TLI.getExceptionSelectorRegister();
668 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
670 // FIXME: Hack around an exception handling flaw (PR1508): the personality
671 // function and list of typeids logically belong to the invoke (or, if you
672 // like, the basic block containing the invoke), and need to be associated
673 // with it in the dwarf exception handling tables. Currently however the
674 // information is provided by an intrinsic (eh.selector) that can be moved
675 // to unexpected places by the optimizers: if the unwind edge is critical,
676 // then breaking it can result in the intrinsics being in the successor of
677 // the landing pad, not the landing pad itself. This results
678 // in exceptions not being caught because no typeids are associated with
679 // the invoke. This may not be the only way things can go wrong, but it
680 // is the only way we try to work around for the moment.
681 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
682 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
684 if (Br && Br->isUnconditional()) { // Critical edge?
685 BasicBlock::const_iterator I, E;
686 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
687 if (isa<EHSelectorInst>(I))
691 // No catch info found - try to extract some from the successor.
692 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
696 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
697 // Initialize the Fast-ISel state, if needed.
698 FastISel *FastIS = 0;
700 FastIS = TLI.createFastISel(*FuncInfo);
702 // Iterate over all basic blocks in the function.
703 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
704 const BasicBlock *LLVMBB = &*I;
705 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
706 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
708 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
709 BasicBlock::const_iterator const End = LLVMBB->end();
710 BasicBlock::const_iterator BI = End;
712 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
714 // Setup an EH landing-pad block.
715 if (FuncInfo->MBB->isLandingPad())
716 PrepareEHLandingPad();
718 // Lower any arguments needed in this block if this is the entry block.
719 if (LLVMBB == &Fn.getEntryBlock())
720 LowerArguments(LLVMBB);
722 // Before doing SelectionDAG ISel, see if FastISel has been requested.
724 FastIS->startNewBlock();
726 // Emit code for any incoming arguments. This must happen before
727 // beginning FastISel on the entry block.
728 if (LLVMBB == &Fn.getEntryBlock()) {
729 CurDAG->setRoot(SDB->getControlRoot());
733 // If we inserted any instructions at the beginning, make a note of
734 // where they are, so we can be sure to emit subsequent instructions
736 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
737 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
739 FastIS->setLastLocalValue(0);
742 // Do FastISel on as many instructions as possible.
743 for (; BI != Begin; --BI) {
744 const Instruction *Inst = llvm::prior(BI);
746 // If we no longer require this instruction, skip it.
747 if (!Inst->mayWriteToMemory() &&
748 !isa<TerminatorInst>(Inst) &&
749 !isa<DbgInfoIntrinsic>(Inst) &&
750 !FuncInfo->isExportedInst(Inst))
753 // Bottom-up: reset the insert pos at the top, after any local-value
755 FastIS->recomputeInsertPt();
757 // Try to select the instruction with FastISel.
758 if (FastIS->SelectInstruction(Inst))
761 // Then handle certain instructions as single-LLVM-Instruction blocks.
762 if (isa<CallInst>(Inst)) {
763 ++NumFastIselFailures;
764 if (EnableFastISelVerbose || EnableFastISelAbort) {
765 dbgs() << "FastISel missed call: ";
769 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
770 unsigned &R = FuncInfo->ValueMap[Inst];
772 R = FuncInfo->CreateRegs(Inst->getType());
775 bool HadTailCall = false;
776 SelectBasicBlock(Inst, BI, HadTailCall);
778 // If the call was emitted as a tail call, we're done with the block.
787 // Otherwise, give up on FastISel for the rest of the block.
788 // For now, be a little lenient about non-branch terminators.
789 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
790 ++NumFastIselFailures;
791 if (EnableFastISelVerbose || EnableFastISelAbort) {
792 dbgs() << "FastISel miss: ";
795 if (EnableFastISelAbort)
796 // The "fast" selector couldn't handle something and bailed.
797 // For the purpose of debugging, just abort.
798 llvm_unreachable("FastISel didn't select the entire block");
803 FastIS->recomputeInsertPt();
806 // Run SelectionDAG instruction selection on the remainder of the block
807 // not handled by FastISel. If FastISel is not run, this is the entire
810 SelectBasicBlock(Begin, BI, HadTailCall);
813 FuncInfo->PHINodesToUpdate.clear();
820 SelectionDAGISel::FinishBasicBlock() {
822 DEBUG(dbgs() << "Total amount of phi nodes to update: "
823 << FuncInfo->PHINodesToUpdate.size() << "\n";
824 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
825 dbgs() << "Node " << i << " : ("
826 << FuncInfo->PHINodesToUpdate[i].first
827 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
829 // Next, now that we know what the last MBB the LLVM BB expanded is, update
830 // PHI nodes in successors.
831 if (SDB->SwitchCases.empty() &&
832 SDB->JTCases.empty() &&
833 SDB->BitTestCases.empty()) {
834 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
835 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
836 assert(PHI->isPHI() &&
837 "This is not a machine PHI node that we are updating!");
838 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
841 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
842 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
847 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
848 // Lower header first, if it wasn't already lowered
849 if (!SDB->BitTestCases[i].Emitted) {
850 // Set the current basic block to the mbb we wish to insert the code into
851 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
852 FuncInfo->InsertPt = FuncInfo->MBB->end();
854 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
855 CurDAG->setRoot(SDB->getRoot());
860 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
861 // Set the current basic block to the mbb we wish to insert the code into
862 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
863 FuncInfo->InsertPt = FuncInfo->MBB->end();
866 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
867 SDB->BitTestCases[i].Reg,
868 SDB->BitTestCases[i].Cases[j],
871 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
872 SDB->BitTestCases[i].Reg,
873 SDB->BitTestCases[i].Cases[j],
877 CurDAG->setRoot(SDB->getRoot());
883 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
885 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
886 MachineBasicBlock *PHIBB = PHI->getParent();
887 assert(PHI->isPHI() &&
888 "This is not a machine PHI node that we are updating!");
889 // This is "default" BB. We have two jumps to it. From "header" BB and
890 // from last "case" BB.
891 if (PHIBB == SDB->BitTestCases[i].Default) {
892 PHI->addOperand(MachineOperand::
893 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
895 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
896 PHI->addOperand(MachineOperand::
897 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
899 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
902 // One of "cases" BB.
903 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
905 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
906 if (cBB->isSuccessor(PHIBB)) {
907 PHI->addOperand(MachineOperand::
908 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
910 PHI->addOperand(MachineOperand::CreateMBB(cBB));
915 SDB->BitTestCases.clear();
917 // If the JumpTable record is filled in, then we need to emit a jump table.
918 // Updating the PHI nodes is tricky in this case, since we need to determine
919 // whether the PHI is a successor of the range check MBB or the jump table MBB
920 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
921 // Lower header first, if it wasn't already lowered
922 if (!SDB->JTCases[i].first.Emitted) {
923 // Set the current basic block to the mbb we wish to insert the code into
924 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
925 FuncInfo->InsertPt = FuncInfo->MBB->end();
927 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
929 CurDAG->setRoot(SDB->getRoot());
934 // Set the current basic block to the mbb we wish to insert the code into
935 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
936 FuncInfo->InsertPt = FuncInfo->MBB->end();
938 SDB->visitJumpTable(SDB->JTCases[i].second);
939 CurDAG->setRoot(SDB->getRoot());
944 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
946 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
947 MachineBasicBlock *PHIBB = PHI->getParent();
948 assert(PHI->isPHI() &&
949 "This is not a machine PHI node that we are updating!");
950 // "default" BB. We can go there only from header BB.
951 if (PHIBB == SDB->JTCases[i].second.Default) {
953 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
956 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
958 // JT BB. Just iterate over successors here
959 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
961 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
963 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
967 SDB->JTCases.clear();
969 // If the switch block involved a branch to one of the actual successors, we
970 // need to update PHI nodes in that block.
971 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
972 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
973 assert(PHI->isPHI() &&
974 "This is not a machine PHI node that we are updating!");
975 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
977 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
978 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
982 // If we generated any switch lowering information, build and codegen any
983 // additional DAGs necessary.
984 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
985 // Set the current basic block to the mbb we wish to insert the code into
986 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
987 FuncInfo->InsertPt = FuncInfo->MBB->end();
989 // Determine the unique successors.
990 SmallVector<MachineBasicBlock *, 2> Succs;
991 Succs.push_back(SDB->SwitchCases[i].TrueBB);
992 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
993 Succs.push_back(SDB->SwitchCases[i].FalseBB);
995 // Emit the code. Note that this could result in ThisBB being split, so
996 // we need to check for updates.
997 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
998 CurDAG->setRoot(SDB->getRoot());
1000 CodeGenAndEmitDAG();
1001 ThisBB = FuncInfo->MBB;
1003 // Handle any PHI nodes in successors of this chunk, as if we were coming
1004 // from the original BB before switch expansion. Note that PHI nodes can
1005 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1006 // handle them the right number of times.
1007 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1008 FuncInfo->MBB = Succs[i];
1009 FuncInfo->InsertPt = FuncInfo->MBB->end();
1010 // FuncInfo->MBB may have been removed from the CFG if a branch was
1012 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1013 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1014 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1016 // This value for this PHI node is recorded in PHINodesToUpdate.
1017 for (unsigned pn = 0; ; ++pn) {
1018 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1019 "Didn't find PHI entry!");
1020 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1021 Phi->addOperand(MachineOperand::
1022 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1024 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1032 SDB->SwitchCases.clear();
1036 /// Create the scheduler. If a specific scheduler was specified
1037 /// via the SchedulerRegistry, use it, otherwise select the
1038 /// one preferred by the target.
1040 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1041 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1045 RegisterScheduler::setDefault(Ctor);
1048 return Ctor(this, OptLevel);
1051 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1052 return new ScheduleHazardRecognizer();
1055 //===----------------------------------------------------------------------===//
1056 // Helper functions used by the generated instruction selector.
1057 //===----------------------------------------------------------------------===//
1058 // Calls to these methods are generated by tblgen.
1060 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1061 /// the dag combiner simplified the 255, we still want to match. RHS is the
1062 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1063 /// specified in the .td file (e.g. 255).
1064 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1065 int64_t DesiredMaskS) const {
1066 const APInt &ActualMask = RHS->getAPIntValue();
1067 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1069 // If the actual mask exactly matches, success!
1070 if (ActualMask == DesiredMask)
1073 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1074 if (ActualMask.intersects(~DesiredMask))
1077 // Otherwise, the DAG Combiner may have proven that the value coming in is
1078 // either already zero or is not demanded. Check for known zero input bits.
1079 APInt NeededMask = DesiredMask & ~ActualMask;
1080 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1083 // TODO: check to see if missing bits are just not demanded.
1085 // Otherwise, this pattern doesn't match.
1089 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1090 /// the dag combiner simplified the 255, we still want to match. RHS is the
1091 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1092 /// specified in the .td file (e.g. 255).
1093 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1094 int64_t DesiredMaskS) const {
1095 const APInt &ActualMask = RHS->getAPIntValue();
1096 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1098 // If the actual mask exactly matches, success!
1099 if (ActualMask == DesiredMask)
1102 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1103 if (ActualMask.intersects(~DesiredMask))
1106 // Otherwise, the DAG Combiner may have proven that the value coming in is
1107 // either already zero or is not demanded. Check for known zero input bits.
1108 APInt NeededMask = DesiredMask & ~ActualMask;
1110 APInt KnownZero, KnownOne;
1111 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1113 // If all the missing bits in the or are already known to be set, match!
1114 if ((NeededMask & KnownOne) == NeededMask)
1117 // TODO: check to see if missing bits are just not demanded.
1119 // Otherwise, this pattern doesn't match.
1124 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1125 /// by tblgen. Others should not call it.
1126 void SelectionDAGISel::
1127 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1128 std::vector<SDValue> InOps;
1129 std::swap(InOps, Ops);
1131 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1132 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1133 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1134 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
1136 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1137 if (InOps[e-1].getValueType() == MVT::Flag)
1138 --e; // Don't process a flag operand if it is here.
1141 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1142 if (!InlineAsm::isMemKind(Flags)) {
1143 // Just skip over this operand, copying the operands verbatim.
1144 Ops.insert(Ops.end(), InOps.begin()+i,
1145 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1146 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1148 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1149 "Memory operand with multiple values?");
1150 // Otherwise, this is a memory operand. Ask the target to select it.
1151 std::vector<SDValue> SelOps;
1152 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1153 report_fatal_error("Could not match memory address. Inline asm"
1156 // Add this to the output node.
1158 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1159 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1160 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1165 // Add the flag input back if present.
1166 if (e != InOps.size())
1167 Ops.push_back(InOps.back());
1170 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1173 static SDNode *findFlagUse(SDNode *N) {
1174 unsigned FlagResNo = N->getNumValues()-1;
1175 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1176 SDUse &Use = I.getUse();
1177 if (Use.getResNo() == FlagResNo)
1178 return Use.getUser();
1183 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1184 /// This function recursively traverses up the operand chain, ignoring
1186 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1187 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1188 bool IgnoreChains) {
1189 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1190 // greater than all of its (recursive) operands. If we scan to a point where
1191 // 'use' is smaller than the node we're scanning for, then we know we will
1194 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1195 // happen because we scan down to newly selected nodes in the case of flag
1197 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1200 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1201 // won't fail if we scan it again.
1202 if (!Visited.insert(Use))
1205 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1206 // Ignore chain uses, they are validated by HandleMergeInputChains.
1207 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1210 SDNode *N = Use->getOperand(i).getNode();
1212 if (Use == ImmedUse || Use == Root)
1213 continue; // We are not looking for immediate use.
1218 // Traverse up the operand chain.
1219 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1225 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1226 /// operand node N of U during instruction selection that starts at Root.
1227 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1228 SDNode *Root) const {
1229 if (OptLevel == CodeGenOpt::None) return false;
1230 return N.hasOneUse();
1233 /// IsLegalToFold - Returns true if the specific operand node N of
1234 /// U can be folded during instruction selection that starts at Root.
1235 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1236 CodeGenOpt::Level OptLevel,
1237 bool IgnoreChains) {
1238 if (OptLevel == CodeGenOpt::None) return false;
1240 // If Root use can somehow reach N through a path that that doesn't contain
1241 // U then folding N would create a cycle. e.g. In the following
1242 // diagram, Root can reach N through X. If N is folded into into Root, then
1243 // X is both a predecessor and a successor of U.
1254 // * indicates nodes to be folded together.
1256 // If Root produces a flag, then it gets (even more) interesting. Since it
1257 // will be "glued" together with its flag use in the scheduler, we need to
1258 // check if it might reach N.
1277 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1278 // (call it Fold), then X is a predecessor of FU and a successor of
1279 // Fold. But since Fold and FU are flagged together, this will create
1280 // a cycle in the scheduling graph.
1282 // If the node has flags, walk down the graph to the "lowest" node in the
1284 EVT VT = Root->getValueType(Root->getNumValues()-1);
1285 while (VT == MVT::Flag) {
1286 SDNode *FU = findFlagUse(Root);
1290 VT = Root->getValueType(Root->getNumValues()-1);
1292 // If our query node has a flag result with a use, we've walked up it. If
1293 // the user (which has already been selected) has a chain or indirectly uses
1294 // the chain, our WalkChainUsers predicate will not consider it. Because of
1295 // this, we cannot ignore chains in this predicate.
1296 IgnoreChains = false;
1300 SmallPtrSet<SDNode*, 16> Visited;
1301 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1304 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1305 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1306 SelectInlineAsmMemoryOperands(Ops);
1308 std::vector<EVT> VTs;
1309 VTs.push_back(MVT::Other);
1310 VTs.push_back(MVT::Flag);
1311 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1312 VTs, &Ops[0], Ops.size());
1314 return New.getNode();
1317 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1318 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1321 /// GetVBR - decode a vbr encoding whose top bit is set.
1322 ALWAYS_INLINE static uint64_t
1323 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1324 assert(Val >= 128 && "Not a VBR");
1325 Val &= 127; // Remove first vbr bit.
1330 NextBits = MatcherTable[Idx++];
1331 Val |= (NextBits&127) << Shift;
1333 } while (NextBits & 128);
1339 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1340 /// interior flag and chain results to use the new flag and chain results.
1341 void SelectionDAGISel::
1342 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1343 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1345 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1346 bool isMorphNodeTo) {
1347 SmallVector<SDNode*, 4> NowDeadNodes;
1349 ISelUpdater ISU(ISelPosition);
1351 // Now that all the normal results are replaced, we replace the chain and
1352 // flag results if present.
1353 if (!ChainNodesMatched.empty()) {
1354 assert(InputChain.getNode() != 0 &&
1355 "Matched input chains but didn't produce a chain");
1356 // Loop over all of the nodes we matched that produced a chain result.
1357 // Replace all the chain results with the final chain we ended up with.
1358 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1359 SDNode *ChainNode = ChainNodesMatched[i];
1361 // If this node was already deleted, don't look at it.
1362 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1365 // Don't replace the results of the root node if we're doing a
1367 if (ChainNode == NodeToMatch && isMorphNodeTo)
1370 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1371 if (ChainVal.getValueType() == MVT::Flag)
1372 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1373 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1374 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1376 // If the node became dead and we haven't already seen it, delete it.
1377 if (ChainNode->use_empty() &&
1378 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1379 NowDeadNodes.push_back(ChainNode);
1383 // If the result produces a flag, update any flag results in the matched
1384 // pattern with the flag result.
1385 if (InputFlag.getNode() != 0) {
1386 // Handle any interior nodes explicitly marked.
1387 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1388 SDNode *FRN = FlagResultNodesMatched[i];
1390 // If this node was already deleted, don't look at it.
1391 if (FRN->getOpcode() == ISD::DELETED_NODE)
1394 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1395 "Doesn't have a flag result");
1396 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1399 // If the node became dead and we haven't already seen it, delete it.
1400 if (FRN->use_empty() &&
1401 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1402 NowDeadNodes.push_back(FRN);
1406 if (!NowDeadNodes.empty())
1407 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1409 DEBUG(errs() << "ISEL: Match complete!\n");
1415 CR_LeadsToInteriorNode
1418 /// WalkChainUsers - Walk down the users of the specified chained node that is
1419 /// part of the pattern we're matching, looking at all of the users we find.
1420 /// This determines whether something is an interior node, whether we have a
1421 /// non-pattern node in between two pattern nodes (which prevent folding because
1422 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1423 /// between pattern nodes (in which case the TF becomes part of the pattern).
1425 /// The walk we do here is guaranteed to be small because we quickly get down to
1426 /// already selected nodes "below" us.
1428 WalkChainUsers(SDNode *ChainedNode,
1429 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1430 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1431 ChainResult Result = CR_Simple;
1433 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1434 E = ChainedNode->use_end(); UI != E; ++UI) {
1435 // Make sure the use is of the chain, not some other value we produce.
1436 if (UI.getUse().getValueType() != MVT::Other) continue;
1440 // If we see an already-selected machine node, then we've gone beyond the
1441 // pattern that we're selecting down into the already selected chunk of the
1443 if (User->isMachineOpcode() ||
1444 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1447 if (User->getOpcode() == ISD::CopyToReg ||
1448 User->getOpcode() == ISD::CopyFromReg ||
1449 User->getOpcode() == ISD::INLINEASM ||
1450 User->getOpcode() == ISD::EH_LABEL) {
1451 // If their node ID got reset to -1 then they've already been selected.
1452 // Treat them like a MachineOpcode.
1453 if (User->getNodeId() == -1)
1457 // If we have a TokenFactor, we handle it specially.
1458 if (User->getOpcode() != ISD::TokenFactor) {
1459 // If the node isn't a token factor and isn't part of our pattern, then it
1460 // must be a random chained node in between two nodes we're selecting.
1461 // This happens when we have something like:
1466 // Because we structurally match the load/store as a read/modify/write,
1467 // but the call is chained between them. We cannot fold in this case
1468 // because it would induce a cycle in the graph.
1469 if (!std::count(ChainedNodesInPattern.begin(),
1470 ChainedNodesInPattern.end(), User))
1471 return CR_InducesCycle;
1473 // Otherwise we found a node that is part of our pattern. For example in:
1477 // This would happen when we're scanning down from the load and see the
1478 // store as a user. Record that there is a use of ChainedNode that is
1479 // part of the pattern and keep scanning uses.
1480 Result = CR_LeadsToInteriorNode;
1481 InteriorChainedNodes.push_back(User);
1485 // If we found a TokenFactor, there are two cases to consider: first if the
1486 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1487 // uses of the TF are in our pattern) we just want to ignore it. Second,
1488 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1494 // | \ DAG's like cheese
1497 // [TokenFactor] [Op]
1504 // In this case, the TokenFactor becomes part of our match and we rewrite it
1505 // as a new TokenFactor.
1507 // To distinguish these two cases, do a recursive walk down the uses.
1508 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1510 // If the uses of the TokenFactor are just already-selected nodes, ignore
1511 // it, it is "below" our pattern.
1513 case CR_InducesCycle:
1514 // If the uses of the TokenFactor lead to nodes that are not part of our
1515 // pattern that are not selected, folding would turn this into a cycle,
1517 return CR_InducesCycle;
1518 case CR_LeadsToInteriorNode:
1519 break; // Otherwise, keep processing.
1522 // Okay, we know we're in the interesting interior case. The TokenFactor
1523 // is now going to be considered part of the pattern so that we rewrite its
1524 // uses (it may have uses that are not part of the pattern) with the
1525 // ultimate chain result of the generated code. We will also add its chain
1526 // inputs as inputs to the ultimate TokenFactor we create.
1527 Result = CR_LeadsToInteriorNode;
1528 ChainedNodesInPattern.push_back(User);
1529 InteriorChainedNodes.push_back(User);
1536 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1537 /// operation for when the pattern matched at least one node with a chains. The
1538 /// input vector contains a list of all of the chained nodes that we match. We
1539 /// must determine if this is a valid thing to cover (i.e. matching it won't
1540 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1541 /// be used as the input node chain for the generated nodes.
1543 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1544 SelectionDAG *CurDAG) {
1545 // Walk all of the chained nodes we've matched, recursively scanning down the
1546 // users of the chain result. This adds any TokenFactor nodes that are caught
1547 // in between chained nodes to the chained and interior nodes list.
1548 SmallVector<SDNode*, 3> InteriorChainedNodes;
1549 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1550 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1551 InteriorChainedNodes) == CR_InducesCycle)
1552 return SDValue(); // Would induce a cycle.
1555 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1556 // that we are interested in. Form our input TokenFactor node.
1557 SmallVector<SDValue, 3> InputChains;
1558 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1559 // Add the input chain of this node to the InputChains list (which will be
1560 // the operands of the generated TokenFactor) if it's not an interior node.
1561 SDNode *N = ChainNodesMatched[i];
1562 if (N->getOpcode() != ISD::TokenFactor) {
1563 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1566 // Otherwise, add the input chain.
1567 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1568 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1569 InputChains.push_back(InChain);
1573 // If we have a token factor, we want to add all inputs of the token factor
1574 // that are not part of the pattern we're matching.
1575 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1576 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1577 N->getOperand(op).getNode()))
1578 InputChains.push_back(N->getOperand(op));
1583 if (InputChains.size() == 1)
1584 return InputChains[0];
1585 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1586 MVT::Other, &InputChains[0], InputChains.size());
1589 /// MorphNode - Handle morphing a node in place for the selector.
1590 SDNode *SelectionDAGISel::
1591 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1592 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1593 // It is possible we're using MorphNodeTo to replace a node with no
1594 // normal results with one that has a normal result (or we could be
1595 // adding a chain) and the input could have flags and chains as well.
1596 // In this case we need to shift the operands down.
1597 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1598 // than the old isel though.
1599 int OldFlagResultNo = -1, OldChainResultNo = -1;
1601 unsigned NTMNumResults = Node->getNumValues();
1602 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1603 OldFlagResultNo = NTMNumResults-1;
1604 if (NTMNumResults != 1 &&
1605 Node->getValueType(NTMNumResults-2) == MVT::Other)
1606 OldChainResultNo = NTMNumResults-2;
1607 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1608 OldChainResultNo = NTMNumResults-1;
1610 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1611 // that this deletes operands of the old node that become dead.
1612 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1614 // MorphNodeTo can operate in two ways: if an existing node with the
1615 // specified operands exists, it can just return it. Otherwise, it
1616 // updates the node in place to have the requested operands.
1618 // If we updated the node in place, reset the node ID. To the isel,
1619 // this should be just like a newly allocated machine node.
1623 unsigned ResNumResults = Res->getNumValues();
1624 // Move the flag if needed.
1625 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1626 (unsigned)OldFlagResultNo != ResNumResults-1)
1627 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1628 SDValue(Res, ResNumResults-1));
1630 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1633 // Move the chain reference if needed.
1634 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1635 (unsigned)OldChainResultNo != ResNumResults-1)
1636 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1637 SDValue(Res, ResNumResults-1));
1639 // Otherwise, no replacement happened because the node already exists. Replace
1640 // Uses of the old node with the new one.
1642 CurDAG->ReplaceAllUsesWith(Node, Res);
1647 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1648 ALWAYS_INLINE static bool
1649 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1650 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1651 // Accept if it is exactly the same as a previously recorded node.
1652 unsigned RecNo = MatcherTable[MatcherIndex++];
1653 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1654 return N == RecordedNodes[RecNo];
1657 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1658 ALWAYS_INLINE static bool
1659 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1660 SelectionDAGISel &SDISel) {
1661 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1664 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1665 ALWAYS_INLINE static bool
1666 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1667 SelectionDAGISel &SDISel, SDNode *N) {
1668 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1671 ALWAYS_INLINE static bool
1672 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1674 uint16_t Opc = MatcherTable[MatcherIndex++];
1675 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1676 return N->getOpcode() == Opc;
1679 ALWAYS_INLINE static bool
1680 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1681 SDValue N, const TargetLowering &TLI) {
1682 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1683 if (N.getValueType() == VT) return true;
1685 // Handle the case when VT is iPTR.
1686 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1689 ALWAYS_INLINE static bool
1690 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1691 SDValue N, const TargetLowering &TLI,
1693 if (ChildNo >= N.getNumOperands())
1694 return false; // Match fails if out of range child #.
1695 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1699 ALWAYS_INLINE static bool
1700 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1702 return cast<CondCodeSDNode>(N)->get() ==
1703 (ISD::CondCode)MatcherTable[MatcherIndex++];
1706 ALWAYS_INLINE static bool
1707 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1708 SDValue N, const TargetLowering &TLI) {
1709 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1710 if (cast<VTSDNode>(N)->getVT() == VT)
1713 // Handle the case when VT is iPTR.
1714 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1717 ALWAYS_INLINE static bool
1718 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1720 int64_t Val = MatcherTable[MatcherIndex++];
1722 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1724 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1725 return C != 0 && C->getSExtValue() == Val;
1728 ALWAYS_INLINE static bool
1729 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1730 SDValue N, SelectionDAGISel &SDISel) {
1731 int64_t Val = MatcherTable[MatcherIndex++];
1733 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1735 if (N->getOpcode() != ISD::AND) return false;
1737 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1738 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1741 ALWAYS_INLINE static bool
1742 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1743 SDValue N, SelectionDAGISel &SDISel) {
1744 int64_t Val = MatcherTable[MatcherIndex++];
1746 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1748 if (N->getOpcode() != ISD::OR) return false;
1750 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1751 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1754 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1755 /// scope, evaluate the current node. If the current predicate is known to
1756 /// fail, set Result=true and return anything. If the current predicate is
1757 /// known to pass, set Result=false and return the MatcherIndex to continue
1758 /// with. If the current predicate is unknown, set Result=false and return the
1759 /// MatcherIndex to continue with.
1760 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1761 unsigned Index, SDValue N,
1762 bool &Result, SelectionDAGISel &SDISel,
1763 SmallVectorImpl<SDValue> &RecordedNodes){
1764 switch (Table[Index++]) {
1767 return Index-1; // Could not evaluate this predicate.
1768 case SelectionDAGISel::OPC_CheckSame:
1769 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1771 case SelectionDAGISel::OPC_CheckPatternPredicate:
1772 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1774 case SelectionDAGISel::OPC_CheckPredicate:
1775 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1777 case SelectionDAGISel::OPC_CheckOpcode:
1778 Result = !::CheckOpcode(Table, Index, N.getNode());
1780 case SelectionDAGISel::OPC_CheckType:
1781 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1783 case SelectionDAGISel::OPC_CheckChild0Type:
1784 case SelectionDAGISel::OPC_CheckChild1Type:
1785 case SelectionDAGISel::OPC_CheckChild2Type:
1786 case SelectionDAGISel::OPC_CheckChild3Type:
1787 case SelectionDAGISel::OPC_CheckChild4Type:
1788 case SelectionDAGISel::OPC_CheckChild5Type:
1789 case SelectionDAGISel::OPC_CheckChild6Type:
1790 case SelectionDAGISel::OPC_CheckChild7Type:
1791 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1792 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1794 case SelectionDAGISel::OPC_CheckCondCode:
1795 Result = !::CheckCondCode(Table, Index, N);
1797 case SelectionDAGISel::OPC_CheckValueType:
1798 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1800 case SelectionDAGISel::OPC_CheckInteger:
1801 Result = !::CheckInteger(Table, Index, N);
1803 case SelectionDAGISel::OPC_CheckAndImm:
1804 Result = !::CheckAndImm(Table, Index, N, SDISel);
1806 case SelectionDAGISel::OPC_CheckOrImm:
1807 Result = !::CheckOrImm(Table, Index, N, SDISel);
1815 /// FailIndex - If this match fails, this is the index to continue with.
1818 /// NodeStack - The node stack when the scope was formed.
1819 SmallVector<SDValue, 4> NodeStack;
1821 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1822 unsigned NumRecordedNodes;
1824 /// NumMatchedMemRefs - The number of matched memref entries.
1825 unsigned NumMatchedMemRefs;
1827 /// InputChain/InputFlag - The current chain/flag
1828 SDValue InputChain, InputFlag;
1830 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1831 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1836 SDNode *SelectionDAGISel::
1837 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1838 unsigned TableSize) {
1839 // FIXME: Should these even be selected? Handle these cases in the caller?
1840 switch (NodeToMatch->getOpcode()) {
1843 case ISD::EntryToken: // These nodes remain the same.
1844 case ISD::BasicBlock:
1846 //case ISD::VALUETYPE:
1847 //case ISD::CONDCODE:
1848 case ISD::HANDLENODE:
1849 case ISD::MDNODE_SDNODE:
1850 case ISD::TargetConstant:
1851 case ISD::TargetConstantFP:
1852 case ISD::TargetConstantPool:
1853 case ISD::TargetFrameIndex:
1854 case ISD::TargetExternalSymbol:
1855 case ISD::TargetBlockAddress:
1856 case ISD::TargetJumpTable:
1857 case ISD::TargetGlobalTLSAddress:
1858 case ISD::TargetGlobalAddress:
1859 case ISD::TokenFactor:
1860 case ISD::CopyFromReg:
1861 case ISD::CopyToReg:
1863 NodeToMatch->setNodeId(-1); // Mark selected.
1865 case ISD::AssertSext:
1866 case ISD::AssertZext:
1867 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1868 NodeToMatch->getOperand(0));
1870 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1871 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1874 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1876 // Set up the node stack with NodeToMatch as the only node on the stack.
1877 SmallVector<SDValue, 8> NodeStack;
1878 SDValue N = SDValue(NodeToMatch, 0);
1879 NodeStack.push_back(N);
1881 // MatchScopes - Scopes used when matching, if a match failure happens, this
1882 // indicates where to continue checking.
1883 SmallVector<MatchScope, 8> MatchScopes;
1885 // RecordedNodes - This is the set of nodes that have been recorded by the
1887 SmallVector<SDValue, 8> RecordedNodes;
1889 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1891 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1893 // These are the current input chain and flag for use when generating nodes.
1894 // Various Emit operations change these. For example, emitting a copytoreg
1895 // uses and updates these.
1896 SDValue InputChain, InputFlag;
1898 // ChainNodesMatched - If a pattern matches nodes that have input/output
1899 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1900 // which ones they are. The result is captured into this list so that we can
1901 // update the chain results when the pattern is complete.
1902 SmallVector<SDNode*, 3> ChainNodesMatched;
1903 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1905 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1906 NodeToMatch->dump(CurDAG);
1909 // Determine where to start the interpreter. Normally we start at opcode #0,
1910 // but if the state machine starts with an OPC_SwitchOpcode, then we
1911 // accelerate the first lookup (which is guaranteed to be hot) with the
1912 // OpcodeOffset table.
1913 unsigned MatcherIndex = 0;
1915 if (!OpcodeOffset.empty()) {
1916 // Already computed the OpcodeOffset table, just index into it.
1917 if (N.getOpcode() < OpcodeOffset.size())
1918 MatcherIndex = OpcodeOffset[N.getOpcode()];
1919 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1921 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1922 // Otherwise, the table isn't computed, but the state machine does start
1923 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1924 // is the first time we're selecting an instruction.
1927 // Get the size of this case.
1928 unsigned CaseSize = MatcherTable[Idx++];
1930 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1931 if (CaseSize == 0) break;
1933 // Get the opcode, add the index to the table.
1934 uint16_t Opc = MatcherTable[Idx++];
1935 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1936 if (Opc >= OpcodeOffset.size())
1937 OpcodeOffset.resize((Opc+1)*2);
1938 OpcodeOffset[Opc] = Idx;
1942 // Okay, do the lookup for the first opcode.
1943 if (N.getOpcode() < OpcodeOffset.size())
1944 MatcherIndex = OpcodeOffset[N.getOpcode()];
1948 assert(MatcherIndex < TableSize && "Invalid index");
1950 unsigned CurrentOpcodeIndex = MatcherIndex;
1952 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1955 // Okay, the semantics of this operation are that we should push a scope
1956 // then evaluate the first child. However, pushing a scope only to have
1957 // the first check fail (which then pops it) is inefficient. If we can
1958 // determine immediately that the first check (or first several) will
1959 // immediately fail, don't even bother pushing a scope for them.
1963 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1964 if (NumToSkip & 128)
1965 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1966 // Found the end of the scope with no match.
1967 if (NumToSkip == 0) {
1972 FailIndex = MatcherIndex+NumToSkip;
1974 unsigned MatcherIndexOfPredicate = MatcherIndex;
1975 (void)MatcherIndexOfPredicate; // silence warning.
1977 // If we can't evaluate this predicate without pushing a scope (e.g. if
1978 // it is a 'MoveParent') or if the predicate succeeds on this node, we
1979 // push the scope and evaluate the full predicate chain.
1981 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
1982 Result, *this, RecordedNodes);
1986 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
1987 << "index " << MatcherIndexOfPredicate
1988 << ", continuing at " << FailIndex << "\n");
1989 ++NumDAGIselRetries;
1991 // Otherwise, we know that this case of the Scope is guaranteed to fail,
1992 // move to the next case.
1993 MatcherIndex = FailIndex;
1996 // If the whole scope failed to match, bail.
1997 if (FailIndex == 0) break;
1999 // Push a MatchScope which indicates where to go if the first child fails
2001 MatchScope NewEntry;
2002 NewEntry.FailIndex = FailIndex;
2003 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2004 NewEntry.NumRecordedNodes = RecordedNodes.size();
2005 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2006 NewEntry.InputChain = InputChain;
2007 NewEntry.InputFlag = InputFlag;
2008 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2009 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2010 MatchScopes.push_back(NewEntry);
2013 case OPC_RecordNode:
2014 // Remember this node, it may end up being an operand in the pattern.
2015 RecordedNodes.push_back(N);
2018 case OPC_RecordChild0: case OPC_RecordChild1:
2019 case OPC_RecordChild2: case OPC_RecordChild3:
2020 case OPC_RecordChild4: case OPC_RecordChild5:
2021 case OPC_RecordChild6: case OPC_RecordChild7: {
2022 unsigned ChildNo = Opcode-OPC_RecordChild0;
2023 if (ChildNo >= N.getNumOperands())
2024 break; // Match fails if out of range child #.
2026 RecordedNodes.push_back(N->getOperand(ChildNo));
2029 case OPC_RecordMemRef:
2030 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2033 case OPC_CaptureFlagInput:
2034 // If the current node has an input flag, capture it in InputFlag.
2035 if (N->getNumOperands() != 0 &&
2036 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2037 InputFlag = N->getOperand(N->getNumOperands()-1);
2040 case OPC_MoveChild: {
2041 unsigned ChildNo = MatcherTable[MatcherIndex++];
2042 if (ChildNo >= N.getNumOperands())
2043 break; // Match fails if out of range child #.
2044 N = N.getOperand(ChildNo);
2045 NodeStack.push_back(N);
2049 case OPC_MoveParent:
2050 // Pop the current node off the NodeStack.
2051 NodeStack.pop_back();
2052 assert(!NodeStack.empty() && "Node stack imbalance!");
2053 N = NodeStack.back();
2057 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2059 case OPC_CheckPatternPredicate:
2060 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2062 case OPC_CheckPredicate:
2063 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2067 case OPC_CheckComplexPat: {
2068 unsigned CPNum = MatcherTable[MatcherIndex++];
2069 unsigned RecNo = MatcherTable[MatcherIndex++];
2070 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2071 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2076 case OPC_CheckOpcode:
2077 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2081 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2084 case OPC_SwitchOpcode: {
2085 unsigned CurNodeOpcode = N.getOpcode();
2086 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2089 // Get the size of this case.
2090 CaseSize = MatcherTable[MatcherIndex++];
2092 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2093 if (CaseSize == 0) break;
2095 uint16_t Opc = MatcherTable[MatcherIndex++];
2096 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2098 // If the opcode matches, then we will execute this case.
2099 if (CurNodeOpcode == Opc)
2102 // Otherwise, skip over this case.
2103 MatcherIndex += CaseSize;
2106 // If no cases matched, bail out.
2107 if (CaseSize == 0) break;
2109 // Otherwise, execute the case we found.
2110 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2111 << " to " << MatcherIndex << "\n");
2115 case OPC_SwitchType: {
2116 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2117 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2120 // Get the size of this case.
2121 CaseSize = MatcherTable[MatcherIndex++];
2123 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2124 if (CaseSize == 0) break;
2126 MVT::SimpleValueType CaseVT =
2127 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2128 if (CaseVT == MVT::iPTR)
2129 CaseVT = TLI.getPointerTy().SimpleTy;
2131 // If the VT matches, then we will execute this case.
2132 if (CurNodeVT == CaseVT)
2135 // Otherwise, skip over this case.
2136 MatcherIndex += CaseSize;
2139 // If no cases matched, bail out.
2140 if (CaseSize == 0) break;
2142 // Otherwise, execute the case we found.
2143 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2144 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2147 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2148 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2149 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2150 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2151 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2152 Opcode-OPC_CheckChild0Type))
2155 case OPC_CheckCondCode:
2156 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2158 case OPC_CheckValueType:
2159 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2161 case OPC_CheckInteger:
2162 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2164 case OPC_CheckAndImm:
2165 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2167 case OPC_CheckOrImm:
2168 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2171 case OPC_CheckFoldableChainNode: {
2172 assert(NodeStack.size() != 1 && "No parent node");
2173 // Verify that all intermediate nodes between the root and this one have
2175 bool HasMultipleUses = false;
2176 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2177 if (!NodeStack[i].hasOneUse()) {
2178 HasMultipleUses = true;
2181 if (HasMultipleUses) break;
2183 // Check to see that the target thinks this is profitable to fold and that
2184 // we can fold it without inducing cycles in the graph.
2185 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2187 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2188 NodeToMatch, OptLevel,
2189 true/*We validate our own chains*/))
2194 case OPC_EmitInteger: {
2195 MVT::SimpleValueType VT =
2196 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2197 int64_t Val = MatcherTable[MatcherIndex++];
2199 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2200 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2203 case OPC_EmitRegister: {
2204 MVT::SimpleValueType VT =
2205 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2206 unsigned RegNo = MatcherTable[MatcherIndex++];
2207 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2211 case OPC_EmitConvertToTarget: {
2212 // Convert from IMM/FPIMM to target version.
2213 unsigned RecNo = MatcherTable[MatcherIndex++];
2214 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2215 SDValue Imm = RecordedNodes[RecNo];
2217 if (Imm->getOpcode() == ISD::Constant) {
2218 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2219 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2220 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2221 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2222 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2225 RecordedNodes.push_back(Imm);
2229 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2230 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2231 // These are space-optimized forms of OPC_EmitMergeInputChains.
2232 assert(InputChain.getNode() == 0 &&
2233 "EmitMergeInputChains should be the first chain producing node");
2234 assert(ChainNodesMatched.empty() &&
2235 "Should only have one EmitMergeInputChains per match");
2237 // Read all of the chained nodes.
2238 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2239 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2240 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2242 // FIXME: What if other value results of the node have uses not matched
2244 if (ChainNodesMatched.back() != NodeToMatch &&
2245 !RecordedNodes[RecNo].hasOneUse()) {
2246 ChainNodesMatched.clear();
2250 // Merge the input chains if they are not intra-pattern references.
2251 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2253 if (InputChain.getNode() == 0)
2254 break; // Failed to merge.
2258 case OPC_EmitMergeInputChains: {
2259 assert(InputChain.getNode() == 0 &&
2260 "EmitMergeInputChains should be the first chain producing node");
2261 // This node gets a list of nodes we matched in the input that have
2262 // chains. We want to token factor all of the input chains to these nodes
2263 // together. However, if any of the input chains is actually one of the
2264 // nodes matched in this pattern, then we have an intra-match reference.
2265 // Ignore these because the newly token factored chain should not refer to
2267 unsigned NumChains = MatcherTable[MatcherIndex++];
2268 assert(NumChains != 0 && "Can't TF zero chains");
2270 assert(ChainNodesMatched.empty() &&
2271 "Should only have one EmitMergeInputChains per match");
2273 // Read all of the chained nodes.
2274 for (unsigned i = 0; i != NumChains; ++i) {
2275 unsigned RecNo = MatcherTable[MatcherIndex++];
2276 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2277 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2279 // FIXME: What if other value results of the node have uses not matched
2281 if (ChainNodesMatched.back() != NodeToMatch &&
2282 !RecordedNodes[RecNo].hasOneUse()) {
2283 ChainNodesMatched.clear();
2288 // If the inner loop broke out, the match fails.
2289 if (ChainNodesMatched.empty())
2292 // Merge the input chains if they are not intra-pattern references.
2293 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2295 if (InputChain.getNode() == 0)
2296 break; // Failed to merge.
2301 case OPC_EmitCopyToReg: {
2302 unsigned RecNo = MatcherTable[MatcherIndex++];
2303 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2304 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2306 if (InputChain.getNode() == 0)
2307 InputChain = CurDAG->getEntryNode();
2309 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2310 DestPhysReg, RecordedNodes[RecNo],
2313 InputFlag = InputChain.getValue(1);
2317 case OPC_EmitNodeXForm: {
2318 unsigned XFormNo = MatcherTable[MatcherIndex++];
2319 unsigned RecNo = MatcherTable[MatcherIndex++];
2320 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2321 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2326 case OPC_MorphNodeTo: {
2327 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2328 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2329 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2330 // Get the result VT list.
2331 unsigned NumVTs = MatcherTable[MatcherIndex++];
2332 SmallVector<EVT, 4> VTs;
2333 for (unsigned i = 0; i != NumVTs; ++i) {
2334 MVT::SimpleValueType VT =
2335 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2336 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2340 if (EmitNodeInfo & OPFL_Chain)
2341 VTs.push_back(MVT::Other);
2342 if (EmitNodeInfo & OPFL_FlagOutput)
2343 VTs.push_back(MVT::Flag);
2345 // This is hot code, so optimize the two most common cases of 1 and 2
2348 if (VTs.size() == 1)
2349 VTList = CurDAG->getVTList(VTs[0]);
2350 else if (VTs.size() == 2)
2351 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2353 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2355 // Get the operand list.
2356 unsigned NumOps = MatcherTable[MatcherIndex++];
2357 SmallVector<SDValue, 8> Ops;
2358 for (unsigned i = 0; i != NumOps; ++i) {
2359 unsigned RecNo = MatcherTable[MatcherIndex++];
2361 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2363 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2364 Ops.push_back(RecordedNodes[RecNo]);
2367 // If there are variadic operands to add, handle them now.
2368 if (EmitNodeInfo & OPFL_VariadicInfo) {
2369 // Determine the start index to copy from.
2370 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2371 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2372 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2373 "Invalid variadic node");
2374 // Copy all of the variadic operands, not including a potential flag
2376 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2378 SDValue V = NodeToMatch->getOperand(i);
2379 if (V.getValueType() == MVT::Flag) break;
2384 // If this has chain/flag inputs, add them.
2385 if (EmitNodeInfo & OPFL_Chain)
2386 Ops.push_back(InputChain);
2387 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2388 Ops.push_back(InputFlag);
2392 if (Opcode != OPC_MorphNodeTo) {
2393 // If this is a normal EmitNode command, just create the new node and
2394 // add the results to the RecordedNodes list.
2395 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2396 VTList, Ops.data(), Ops.size());
2398 // Add all the non-flag/non-chain results to the RecordedNodes list.
2399 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2400 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2401 RecordedNodes.push_back(SDValue(Res, i));
2405 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2409 // If the node had chain/flag results, update our notion of the current
2411 if (EmitNodeInfo & OPFL_FlagOutput) {
2412 InputFlag = SDValue(Res, VTs.size()-1);
2413 if (EmitNodeInfo & OPFL_Chain)
2414 InputChain = SDValue(Res, VTs.size()-2);
2415 } else if (EmitNodeInfo & OPFL_Chain)
2416 InputChain = SDValue(Res, VTs.size()-1);
2418 // If the OPFL_MemRefs flag is set on this node, slap all of the
2419 // accumulated memrefs onto it.
2421 // FIXME: This is vastly incorrect for patterns with multiple outputs
2422 // instructions that access memory and for ComplexPatterns that match
2424 if (EmitNodeInfo & OPFL_MemRefs) {
2425 MachineSDNode::mmo_iterator MemRefs =
2426 MF->allocateMemRefsArray(MatchedMemRefs.size());
2427 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2428 cast<MachineSDNode>(Res)
2429 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2433 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2434 << " node: "; Res->dump(CurDAG); errs() << "\n");
2436 // If this was a MorphNodeTo then we're completely done!
2437 if (Opcode == OPC_MorphNodeTo) {
2438 // Update chain and flag uses.
2439 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2440 InputFlag, FlagResultNodesMatched, true);
2447 case OPC_MarkFlagResults: {
2448 unsigned NumNodes = MatcherTable[MatcherIndex++];
2450 // Read and remember all the flag-result nodes.
2451 for (unsigned i = 0; i != NumNodes; ++i) {
2452 unsigned RecNo = MatcherTable[MatcherIndex++];
2454 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2456 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2457 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2462 case OPC_CompleteMatch: {
2463 // The match has been completed, and any new nodes (if any) have been
2464 // created. Patch up references to the matched dag to use the newly
2466 unsigned NumResults = MatcherTable[MatcherIndex++];
2468 for (unsigned i = 0; i != NumResults; ++i) {
2469 unsigned ResSlot = MatcherTable[MatcherIndex++];
2471 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2473 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2474 SDValue Res = RecordedNodes[ResSlot];
2476 assert(i < NodeToMatch->getNumValues() &&
2477 NodeToMatch->getValueType(i) != MVT::Other &&
2478 NodeToMatch->getValueType(i) != MVT::Flag &&
2479 "Invalid number of results to complete!");
2480 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2481 NodeToMatch->getValueType(i) == MVT::iPTR ||
2482 Res.getValueType() == MVT::iPTR ||
2483 NodeToMatch->getValueType(i).getSizeInBits() ==
2484 Res.getValueType().getSizeInBits()) &&
2485 "invalid replacement");
2486 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2489 // If the root node defines a flag, add it to the flag nodes to update
2491 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2492 FlagResultNodesMatched.push_back(NodeToMatch);
2494 // Update chain and flag uses.
2495 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2496 InputFlag, FlagResultNodesMatched, false);
2498 assert(NodeToMatch->use_empty() &&
2499 "Didn't replace all uses of the node?");
2501 // FIXME: We just return here, which interacts correctly with SelectRoot
2502 // above. We should fix this to not return an SDNode* anymore.
2507 // If the code reached this point, then the match failed. See if there is
2508 // another child to try in the current 'Scope', otherwise pop it until we
2509 // find a case to check.
2510 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2511 ++NumDAGIselRetries;
2513 if (MatchScopes.empty()) {
2514 CannotYetSelect(NodeToMatch);
2518 // Restore the interpreter state back to the point where the scope was
2520 MatchScope &LastScope = MatchScopes.back();
2521 RecordedNodes.resize(LastScope.NumRecordedNodes);
2523 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2524 N = NodeStack.back();
2526 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2527 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2528 MatcherIndex = LastScope.FailIndex;
2530 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2532 InputChain = LastScope.InputChain;
2533 InputFlag = LastScope.InputFlag;
2534 if (!LastScope.HasChainNodesMatched)
2535 ChainNodesMatched.clear();
2536 if (!LastScope.HasFlagResultNodesMatched)
2537 FlagResultNodesMatched.clear();
2539 // Check to see what the offset is at the new MatcherIndex. If it is zero
2540 // we have reached the end of this scope, otherwise we have another child
2541 // in the current scope to try.
2542 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2543 if (NumToSkip & 128)
2544 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2546 // If we have another child in this scope to match, update FailIndex and
2548 if (NumToSkip != 0) {
2549 LastScope.FailIndex = MatcherIndex+NumToSkip;
2553 // End of this scope, pop it and try the next child in the containing
2555 MatchScopes.pop_back();
2562 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2564 raw_string_ostream Msg(msg);
2565 Msg << "Cannot yet select: ";
2567 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2568 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2569 N->getOpcode() != ISD::INTRINSIC_VOID) {
2570 N->printrFull(Msg, CurDAG);
2572 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2574 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2575 if (iid < Intrinsic::num_intrinsics)
2576 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2577 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2578 Msg << "target intrinsic %" << TII->getName(iid);
2580 Msg << "unknown intrinsic #" << iid;
2582 report_fatal_error(Msg.str());
2585 char SelectionDAGISel::ID = 0;