1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "SelectionDAGBuild.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleDAG.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetData.h"
42 #include "llvm/Target/TargetFrameInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/Timer.h"
55 EnableValueProp("enable-value-prop", cl::Hidden);
57 DisableLegalizeTypes("disable-legalize-types", cl::Hidden);
60 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
61 cl::desc("Enable verbose messages in the \"fast\" "
62 "instruction selector"));
64 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
65 cl::desc("Enable abort calls when \"fast\" instruction fails"));
67 static const bool EnableFastISelVerbose = false,
68 EnableFastISelAbort = false;
71 SchedLiveInCopies("schedule-livein-copies",
72 cl::desc("Schedule copies of livein registers"),
77 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
78 cl::desc("Pop up a window to show dags before the first "
81 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
82 cl::desc("Pop up a window to show dags before legalize types"));
84 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
85 cl::desc("Pop up a window to show dags before legalize"));
87 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
88 cl::desc("Pop up a window to show dags before the second "
91 ViewISelDAGs("view-isel-dags", cl::Hidden,
92 cl::desc("Pop up a window to show isel dags as they are selected"));
94 ViewSchedDAGs("view-sched-dags", cl::Hidden,
95 cl::desc("Pop up a window to show sched dags as they are processed"));
97 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
98 cl::desc("Pop up a window to show SUnit dags after they are processed"));
100 static const bool ViewDAGCombine1 = false,
101 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
102 ViewDAGCombine2 = false,
103 ViewISelDAGs = false, ViewSchedDAGs = false,
104 ViewSUnitDAGs = false;
107 //===---------------------------------------------------------------------===//
109 /// RegisterScheduler class - Track the registration of instruction schedulers.
111 //===---------------------------------------------------------------------===//
112 MachinePassRegistry RegisterScheduler::Registry;
114 //===---------------------------------------------------------------------===//
116 /// ISHeuristic command line option for instruction schedulers.
118 //===---------------------------------------------------------------------===//
119 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
120 RegisterPassParser<RegisterScheduler> >
121 ISHeuristic("pre-RA-sched",
122 cl::init(&createDefaultScheduler),
123 cl::desc("Instruction schedulers available (before register"
126 static RegisterScheduler
127 defaultListDAGScheduler("default", "Best scheduler for the target",
128 createDefaultScheduler);
131 //===--------------------------------------------------------------------===//
132 /// createDefaultScheduler - This creates an instruction scheduler appropriate
134 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
136 MachineBasicBlock *BB,
138 TargetLowering &TLI = IS->getTargetLowering();
140 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
141 return createTDListDAGScheduler(IS, DAG, BB, Fast);
143 assert(TLI.getSchedulingPreference() ==
144 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
145 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
150 // EmitInstrWithCustomInserter - This method should be implemented by targets
151 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
152 // instructions are special in various ways, which require special support to
153 // insert. The specified MachineInstr is created but not inserted into any
154 // basic blocks, and the scheduler passes ownership of it to this method.
155 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
156 MachineBasicBlock *MBB) {
157 cerr << "If a target marks an instruction with "
158 << "'usesCustomDAGSchedInserter', it must implement "
159 << "TargetLowering::EmitInstrWithCustomInserter!\n";
164 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
165 /// physical register has only a single copy use, then coalesced the copy
167 static void EmitLiveInCopy(MachineBasicBlock *MBB,
168 MachineBasicBlock::iterator &InsertPos,
169 unsigned VirtReg, unsigned PhysReg,
170 const TargetRegisterClass *RC,
171 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
172 const MachineRegisterInfo &MRI,
173 const TargetRegisterInfo &TRI,
174 const TargetInstrInfo &TII) {
175 unsigned NumUses = 0;
176 MachineInstr *UseMI = NULL;
177 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
178 UE = MRI.use_end(); UI != UE; ++UI) {
184 // If the number of uses is not one, or the use is not a move instruction,
185 // don't coalesce. Also, only coalesce away a virtual register to virtual
187 bool Coalesced = false;
188 unsigned SrcReg, DstReg;
190 TII.isMoveInstr(*UseMI, SrcReg, DstReg) &&
191 TargetRegisterInfo::isVirtualRegister(DstReg)) {
196 // Now find an ideal location to insert the copy.
197 MachineBasicBlock::iterator Pos = InsertPos;
198 while (Pos != MBB->begin()) {
199 MachineInstr *PrevMI = prior(Pos);
200 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
201 // copyRegToReg might emit multiple instructions to do a copy.
202 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
203 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
204 // This is what the BB looks like right now:
209 // We want to insert "r1025 = mov r1". Inserting this copy below the
210 // move to r1024 makes it impossible for that move to be coalesced.
217 break; // Woot! Found a good location.
221 TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
222 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
224 if (&*InsertPos == UseMI) ++InsertPos;
229 /// EmitLiveInCopies - If this is the first basic block in the function,
230 /// and if it has live ins that need to be copied into vregs, emit the
231 /// copies into the block.
232 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
233 const MachineRegisterInfo &MRI,
234 const TargetRegisterInfo &TRI,
235 const TargetInstrInfo &TII) {
236 if (SchedLiveInCopies) {
237 // Emit the copies at a heuristically-determined location in the block.
238 DenseMap<MachineInstr*, unsigned> CopyRegMap;
239 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
240 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
241 E = MRI.livein_end(); LI != E; ++LI)
243 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
244 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
245 RC, CopyRegMap, MRI, TRI, TII);
248 // Emit the copies into the top of the block.
249 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
250 E = MRI.livein_end(); LI != E; ++LI)
252 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
253 TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
254 LI->second, LI->first, RC, RC);
259 //===----------------------------------------------------------------------===//
260 // SelectionDAGISel code
261 //===----------------------------------------------------------------------===//
263 SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) :
264 FunctionPass(&ID), TLI(tli),
265 FuncInfo(new FunctionLoweringInfo(TLI)),
266 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
267 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)),
273 SelectionDAGISel::~SelectionDAGISel() {
279 unsigned SelectionDAGISel::MakeReg(MVT VT) {
280 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
283 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
284 AU.addRequired<AliasAnalysis>();
285 AU.addRequired<GCModuleInfo>();
286 AU.setPreservesAll();
289 bool SelectionDAGISel::runOnFunction(Function &Fn) {
290 // Do some sanity-checking on the command-line options.
291 assert((!EnableFastISelVerbose || EnableFastISel) &&
292 "-fast-isel-verbose requires -fast-isel");
293 assert((!EnableFastISelAbort || EnableFastISel) &&
294 "-fast-isel-abort requires -fast-isel");
296 // Get alias analysis for load/store combining.
297 AA = &getAnalysis<AliasAnalysis>();
299 TargetMachine &TM = TLI.getTargetMachine();
300 MachineFunction &MF = MachineFunction::construct(&Fn, TM);
301 const MachineRegisterInfo &MRI = MF.getRegInfo();
302 const TargetInstrInfo &TII = *TM.getInstrInfo();
303 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
305 if (MF.getFunction()->hasGC())
306 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction());
309 RegInfo = &MF.getRegInfo();
310 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
312 FuncInfo->set(Fn, MF, EnableFastISel);
313 MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>();
314 CurDAG->init(MF, MMI);
317 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
318 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
320 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
322 SelectAllBasicBlocks(Fn, MF, MMI, TII);
324 // If the first basic block in the function has live ins that need to be
325 // copied into vregs, emit the copies into the top of the block before
326 // emitting the code for the block.
327 EmitLiveInCopies(MF.begin(), MRI, TRI, TII);
329 // Add function live-ins to entry block live-in set.
330 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
331 E = RegInfo->livein_end(); I != E; ++I)
332 MF.begin()->addLiveIn(I->first);
335 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
336 "Not all catch info was assigned to a landing pad!");
344 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
345 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
346 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
347 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) {
348 // Apply the catch info to DestBB.
349 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]);
351 if (!FLI.MBBMap[SrcBB]->isLandingPad())
352 FLI.CatchInfoFound.insert(EHSel);
357 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
358 /// whether object offset >= 0.
360 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
361 if (!isa<FrameIndexSDNode>(Op)) return false;
363 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
364 int FrameIdx = FrameIdxNode->getIndex();
365 return MFI->isFixedObjectIndex(FrameIdx) &&
366 MFI->getObjectOffset(FrameIdx) >= 0;
369 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
370 /// possibly be overwritten when lowering the outgoing arguments in a tail
371 /// call. Currently the implementation of this call is very conservative and
372 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
373 /// virtual registers would be overwritten by direct lowering.
374 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
375 MachineFrameInfo * MFI) {
376 RegisterSDNode * OpReg = NULL;
377 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
378 (Op.getOpcode()== ISD::CopyFromReg &&
379 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
380 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
381 (Op.getOpcode() == ISD::LOAD &&
382 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
383 (Op.getOpcode() == ISD::MERGE_VALUES &&
384 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD &&
385 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()).
391 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
392 /// DAG and fixes their tailcall attribute operand.
393 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
394 TargetLowering& TLI) {
396 SDValue Terminator = DAG.getRoot();
399 if (Terminator.getOpcode() == ISD::RET) {
400 Ret = Terminator.getNode();
403 // Fix tail call attribute of CALL nodes.
404 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
405 BI = DAG.allnodes_end(); BI != BE; ) {
407 if (CallSDNode *TheCall = dyn_cast<CallSDNode>(BI)) {
408 SDValue OpRet(Ret, 0);
409 SDValue OpCall(BI, 0);
410 bool isMarkedTailCall = TheCall->isTailCall();
411 // If CALL node has tail call attribute set to true and the call is not
412 // eligible (no RET or the target rejects) the attribute is fixed to
413 // false. The TargetLowering::IsEligibleForTailCallOptimization function
414 // must correctly identify tail call optimizable calls.
415 if (!isMarkedTailCall) continue;
417 !TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) {
418 // Not eligible. Mark CALL node as non tail call. Note that we
419 // can modify the call node in place since calls are not CSE'd.
420 TheCall->setNotTailCall();
422 // Look for tail call clobbered arguments. Emit a series of
423 // copyto/copyfrom virtual register nodes to protect them.
424 SmallVector<SDValue, 32> Ops;
425 SDValue Chain = TheCall->getChain(), InFlag;
426 Ops.push_back(Chain);
427 Ops.push_back(TheCall->getCallee());
428 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
429 SDValue Arg = TheCall->getArg(i);
430 bool isByVal = TheCall->getArgFlags(i).isByVal();
431 MachineFunction &MF = DAG.getMachineFunction();
432 MachineFrameInfo *MFI = MF.getFrameInfo();
434 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
435 MVT VT = Arg.getValueType();
436 unsigned VReg = MF.getRegInfo().
437 createVirtualRegister(TLI.getRegClassFor(VT));
438 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
439 InFlag = Chain.getValue(1);
440 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
441 Chain = Arg.getValue(1);
442 InFlag = Arg.getValue(2);
445 Ops.push_back(TheCall->getArgFlagsVal(i));
447 // Link in chain of CopyTo/CopyFromReg.
449 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
455 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
456 BasicBlock::iterator Begin,
457 BasicBlock::iterator End) {
458 SDL->setCurrentBasicBlock(BB);
460 // Lower all of the non-terminator instructions.
461 for (BasicBlock::iterator I = Begin; I != End; ++I)
462 if (!isa<TerminatorInst>(I))
465 // Ensure that all instructions which are used outside of their defining
466 // blocks are available as virtual registers. Invoke is handled elsewhere.
467 for (BasicBlock::iterator I = Begin; I != End; ++I)
468 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
469 DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I);
470 if (VMI != FuncInfo->ValueMap.end())
471 SDL->CopyValueToVirtualRegister(I, VMI->second);
474 // Handle PHI nodes in successor blocks.
475 if (End == LLVMBB->end()) {
476 HandlePHINodesInSuccessorBlocks(LLVMBB);
478 // Lower the terminator after the copies are emitted.
479 SDL->visit(*LLVMBB->getTerminator());
482 // Make sure the root of the DAG is up-to-date.
483 CurDAG->setRoot(SDL->getControlRoot());
485 // Check whether calls in this block are real tail calls. Fix up CALL nodes
486 // with correct tailcall attribute so that the target can rely on the tailcall
487 // attribute indicating whether the call is really eligible for tail call
489 if (PerformTailCallOpt)
490 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI);
492 // Final step, emit the lowered DAG as machine code.
497 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
498 SmallPtrSet<SDNode*, 128> VisitedNodes;
499 SmallVector<SDNode*, 128> Worklist;
501 Worklist.push_back(CurDAG->getRoot().getNode());
507 while (!Worklist.empty()) {
508 SDNode *N = Worklist.back();
511 // If we've already seen this node, ignore it.
512 if (!VisitedNodes.insert(N))
515 // Otherwise, add all chain operands to the worklist.
516 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
517 if (N->getOperand(i).getValueType() == MVT::Other)
518 Worklist.push_back(N->getOperand(i).getNode());
520 // If this is a CopyToReg with a vreg dest, process it.
521 if (N->getOpcode() != ISD::CopyToReg)
524 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
525 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
528 // Ignore non-scalar or non-integer values.
529 SDValue Src = N->getOperand(2);
530 MVT SrcVT = Src.getValueType();
531 if (!SrcVT.isInteger() || SrcVT.isVector())
534 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
535 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
536 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
538 // Only install this information if it tells us something.
539 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
540 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
541 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo();
542 if (DestReg >= FLI.LiveOutRegInfo.size())
543 FLI.LiveOutRegInfo.resize(DestReg+1);
544 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
545 LOI.NumSignBits = NumSignBits;
546 LOI.KnownOne = NumSignBits;
547 LOI.KnownZero = NumSignBits;
552 void SelectionDAGISel::CodeGenAndEmitDAG() {
553 std::string GroupName;
554 if (TimePassesIsEnabled)
555 GroupName = "Instruction Selection and Scheduling";
556 std::string BlockName;
557 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
558 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
559 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' +
560 BB->getBasicBlock()->getName();
562 DOUT << "Initial selection DAG:\n";
563 DEBUG(CurDAG->dump());
565 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
567 // Run the DAG combiner in pre-legalize mode.
568 if (TimePassesIsEnabled) {
569 NamedRegionTimer T("DAG Combining 1", GroupName);
570 CurDAG->Combine(false, *AA, Fast);
572 CurDAG->Combine(false, *AA, Fast);
575 DOUT << "Optimized lowered selection DAG:\n";
576 DEBUG(CurDAG->dump());
578 // Second step, hack on the DAG until it only uses operations and types that
579 // the target supports.
580 if (!DisableLegalizeTypes) {
581 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
584 if (TimePassesIsEnabled) {
585 NamedRegionTimer T("Type Legalization", GroupName);
586 CurDAG->LegalizeTypes();
588 CurDAG->LegalizeTypes();
591 DOUT << "Type-legalized selection DAG:\n";
592 DEBUG(CurDAG->dump());
594 // TODO: enable a dag combine pass here.
597 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
599 if (TimePassesIsEnabled) {
600 NamedRegionTimer T("DAG Legalization", GroupName);
606 DOUT << "Legalized selection DAG:\n";
607 DEBUG(CurDAG->dump());
609 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
611 // Run the DAG combiner in post-legalize mode.
612 if (TimePassesIsEnabled) {
613 NamedRegionTimer T("DAG Combining 2", GroupName);
614 CurDAG->Combine(true, *AA, Fast);
616 CurDAG->Combine(true, *AA, Fast);
619 DOUT << "Optimized legalized selection DAG:\n";
620 DEBUG(CurDAG->dump());
622 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
624 if (!Fast && EnableValueProp)
625 ComputeLiveOutVRegInfo();
627 // Third, instruction select all of the operations to machine code, adding the
628 // code to the MachineBasicBlock.
629 if (TimePassesIsEnabled) {
630 NamedRegionTimer T("Instruction Selection", GroupName);
636 DOUT << "Selected selection DAG:\n";
637 DEBUG(CurDAG->dump());
639 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
641 // Schedule machine code.
642 ScheduleDAG *Scheduler;
643 if (TimePassesIsEnabled) {
644 NamedRegionTimer T("Instruction Scheduling", GroupName);
645 Scheduler = Schedule();
647 Scheduler = Schedule();
650 if (ViewSUnitDAGs) Scheduler->viewGraph();
652 // Emit machine code to BB. This can change 'BB' to the last block being
654 if (TimePassesIsEnabled) {
655 NamedRegionTimer T("Instruction Creation", GroupName);
656 BB = Scheduler->EmitSchedule();
658 BB = Scheduler->EmitSchedule();
661 // Free the scheduler state.
662 if (TimePassesIsEnabled) {
663 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
669 DOUT << "Selected machine code:\n";
673 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
674 MachineModuleInfo *MMI,
675 const TargetInstrInfo &TII) {
676 // Initialize the Fast-ISel state, if needed.
677 FastISel *FastIS = 0;
679 FastIS = TLI.createFastISel(*FuncInfo->MF, MMI,
682 FuncInfo->StaticAllocaMap
684 , FuncInfo->CatchInfoLost
688 // Iterate over all basic blocks in the function.
689 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
690 BasicBlock *LLVMBB = &*I;
691 BB = FuncInfo->MBBMap[LLVMBB];
693 BasicBlock::iterator const Begin = LLVMBB->begin();
694 BasicBlock::iterator const End = LLVMBB->end();
695 BasicBlock::iterator BI = Begin;
697 // Lower any arguments needed in this block if this is the entry block.
698 bool SuppressFastISel = false;
699 if (LLVMBB == &Fn.getEntryBlock()) {
700 LowerArguments(LLVMBB);
702 // If any of the arguments has the byval attribute, forgo
703 // fast-isel in the entry block.
706 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
708 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
709 if (EnableFastISelVerbose || EnableFastISelAbort)
710 cerr << "FastISel skips entry block due to byval argument\n";
711 SuppressFastISel = true;
717 if (MMI && BB->isLandingPad()) {
718 // Add a label to mark the beginning of the landing pad. Deletion of the
719 // landing pad can thus be detected via the MachineModuleInfo.
720 unsigned LabelID = MMI->addLandingPad(BB);
722 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL);
723 BuildMI(BB, II).addImm(LabelID);
725 // Mark exception register as live in.
726 unsigned Reg = TLI.getExceptionAddressRegister();
727 if (Reg) BB->addLiveIn(Reg);
729 // Mark exception selector register as live in.
730 Reg = TLI.getExceptionSelectorRegister();
731 if (Reg) BB->addLiveIn(Reg);
733 // FIXME: Hack around an exception handling flaw (PR1508): the personality
734 // function and list of typeids logically belong to the invoke (or, if you
735 // like, the basic block containing the invoke), and need to be associated
736 // with it in the dwarf exception handling tables. Currently however the
737 // information is provided by an intrinsic (eh.selector) that can be moved
738 // to unexpected places by the optimizers: if the unwind edge is critical,
739 // then breaking it can result in the intrinsics being in the successor of
740 // the landing pad, not the landing pad itself. This results in exceptions
741 // not being caught because no typeids are associated with the invoke.
742 // This may not be the only way things can go wrong, but it is the only way
743 // we try to work around for the moment.
744 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
746 if (Br && Br->isUnconditional()) { // Critical edge?
747 BasicBlock::iterator I, E;
748 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
749 if (isa<EHSelectorInst>(I))
753 // No catch info found - try to extract some from the successor.
754 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
758 // Before doing SelectionDAG ISel, see if FastISel has been requested.
759 if (FastIS && !SuppressFastISel) {
760 // Emit code for any incoming arguments. This must happen before
761 // beginning FastISel on the entry block.
762 if (LLVMBB == &Fn.getEntryBlock()) {
763 CurDAG->setRoot(SDL->getControlRoot());
767 FastIS->startNewBlock(BB);
768 // Do FastISel on as many instructions as possible.
769 for (; BI != End; ++BI) {
770 // Just before the terminator instruction, insert instructions to
771 // feed PHI nodes in successor blocks.
772 if (isa<TerminatorInst>(BI))
773 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
774 if (EnableFastISelVerbose || EnableFastISelAbort) {
775 cerr << "FastISel miss: ";
778 if (EnableFastISelAbort)
779 assert(0 && "FastISel didn't handle a PHI in a successor");
783 // First try normal tablegen-generated "fast" selection.
784 if (FastIS->SelectInstruction(BI))
787 // Next, try calling the target to attempt to handle the instruction.
788 if (FastIS->TargetSelectInstruction(BI))
791 // Then handle certain instructions as single-LLVM-Instruction blocks.
792 if (isa<CallInst>(BI)) {
793 if (EnableFastISelVerbose || EnableFastISelAbort) {
794 cerr << "FastISel missed call: ";
798 if (BI->getType() != Type::VoidTy) {
799 unsigned &R = FuncInfo->ValueMap[BI];
801 R = FuncInfo->CreateRegForValue(BI);
804 SelectBasicBlock(LLVMBB, BI, next(BI));
805 // If the instruction was codegen'd with multiple blocks,
806 // inform the FastISel object where to resume inserting.
807 FastIS->setCurrentBlock(BB);
811 // Otherwise, give up on FastISel for the rest of the block.
812 // For now, be a little lenient about non-branch terminators.
813 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
814 if (EnableFastISelVerbose || EnableFastISelAbort) {
815 cerr << "FastISel miss: ";
818 if (EnableFastISelAbort)
819 // The "fast" selector couldn't handle something and bailed.
820 // For the purpose of debugging, just abort.
821 assert(0 && "FastISel didn't select the entire block");
827 // Run SelectionDAG instruction selection on the remainder of the block
828 // not handled by FastISel. If FastISel is not run, this is the entire
831 SelectBasicBlock(LLVMBB, BI, End);
840 SelectionDAGISel::FinishBasicBlock() {
842 // Perform target specific isel post processing.
843 InstructionSelectPostProcessing();
845 DOUT << "Target-post-processed machine code:\n";
848 DOUT << "Total amount of phi nodes to update: "
849 << SDL->PHINodesToUpdate.size() << "\n";
850 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i)
851 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first
852 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";);
854 // Next, now that we know what the last MBB the LLVM BB expanded is, update
855 // PHI nodes in successors.
856 if (SDL->SwitchCases.empty() &&
857 SDL->JTCases.empty() &&
858 SDL->BitTestCases.empty()) {
859 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
860 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
861 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
862 "This is not a machine PHI node that we are updating!");
863 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
865 PHI->addOperand(MachineOperand::CreateMBB(BB));
867 SDL->PHINodesToUpdate.clear();
871 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) {
872 // Lower header first, if it wasn't already lowered
873 if (!SDL->BitTestCases[i].Emitted) {
874 // Set the current basic block to the mbb we wish to insert the code into
875 BB = SDL->BitTestCases[i].Parent;
876 SDL->setCurrentBasicBlock(BB);
878 SDL->visitBitTestHeader(SDL->BitTestCases[i]);
879 CurDAG->setRoot(SDL->getRoot());
884 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
885 // Set the current basic block to the mbb we wish to insert the code into
886 BB = SDL->BitTestCases[i].Cases[j].ThisBB;
887 SDL->setCurrentBasicBlock(BB);
890 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB,
891 SDL->BitTestCases[i].Reg,
892 SDL->BitTestCases[i].Cases[j]);
894 SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
895 SDL->BitTestCases[i].Reg,
896 SDL->BitTestCases[i].Cases[j]);
899 CurDAG->setRoot(SDL->getRoot());
905 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
906 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
907 MachineBasicBlock *PHIBB = PHI->getParent();
908 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
909 "This is not a machine PHI node that we are updating!");
910 // This is "default" BB. We have two jumps to it. From "header" BB and
911 // from last "case" BB.
912 if (PHIBB == SDL->BitTestCases[i].Default) {
913 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
915 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent));
916 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
918 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases.
921 // One of "cases" BB.
922 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size();
924 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB;
925 if (cBB->succ_end() !=
926 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
927 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
929 PHI->addOperand(MachineOperand::CreateMBB(cBB));
934 SDL->BitTestCases.clear();
936 // If the JumpTable record is filled in, then we need to emit a jump table.
937 // Updating the PHI nodes is tricky in this case, since we need to determine
938 // whether the PHI is a successor of the range check MBB or the jump table MBB
939 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) {
940 // Lower header first, if it wasn't already lowered
941 if (!SDL->JTCases[i].first.Emitted) {
942 // Set the current basic block to the mbb we wish to insert the code into
943 BB = SDL->JTCases[i].first.HeaderBB;
944 SDL->setCurrentBasicBlock(BB);
946 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first);
947 CurDAG->setRoot(SDL->getRoot());
952 // Set the current basic block to the mbb we wish to insert the code into
953 BB = SDL->JTCases[i].second.MBB;
954 SDL->setCurrentBasicBlock(BB);
956 SDL->visitJumpTable(SDL->JTCases[i].second);
957 CurDAG->setRoot(SDL->getRoot());
962 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
963 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
964 MachineBasicBlock *PHIBB = PHI->getParent();
965 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
966 "This is not a machine PHI node that we are updating!");
967 // "default" BB. We can go there only from header BB.
968 if (PHIBB == SDL->JTCases[i].second.Default) {
969 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
971 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
973 // JT BB. Just iterate over successors here
974 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
975 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
977 PHI->addOperand(MachineOperand::CreateMBB(BB));
981 SDL->JTCases.clear();
983 // If the switch block involved a branch to one of the actual successors, we
984 // need to update PHI nodes in that block.
985 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
986 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
987 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
988 "This is not a machine PHI node that we are updating!");
989 if (BB->isSuccessor(PHI->getParent())) {
990 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
992 PHI->addOperand(MachineOperand::CreateMBB(BB));
996 // If we generated any switch lowering information, build and codegen any
997 // additional DAGs necessary.
998 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
999 // Set the current basic block to the mbb we wish to insert the code into
1000 BB = SDL->SwitchCases[i].ThisBB;
1001 SDL->setCurrentBasicBlock(BB);
1004 SDL->visitSwitchCase(SDL->SwitchCases[i]);
1005 CurDAG->setRoot(SDL->getRoot());
1006 CodeGenAndEmitDAG();
1009 // Handle any PHI nodes in successors of this chunk, as if we were coming
1010 // from the original BB before switch expansion. Note that PHI nodes can
1011 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1012 // handle them the right number of times.
1013 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1014 for (MachineBasicBlock::iterator Phi = BB->begin();
1015 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
1016 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
1017 for (unsigned pn = 0; ; ++pn) {
1018 assert(pn != SDL->PHINodesToUpdate.size() &&
1019 "Didn't find PHI entry!");
1020 if (SDL->PHINodesToUpdate[pn].first == Phi) {
1021 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
1023 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
1029 // Don't process RHS if same block as LHS.
1030 if (BB == SDL->SwitchCases[i].FalseBB)
1031 SDL->SwitchCases[i].FalseBB = 0;
1033 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1034 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
1035 SDL->SwitchCases[i].FalseBB = 0;
1037 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0);
1039 SDL->SwitchCases.clear();
1041 SDL->PHINodesToUpdate.clear();
1045 /// Schedule - Pick a safe ordering for instructions for each
1046 /// target node in the graph.
1048 ScheduleDAG *SelectionDAGISel::Schedule() {
1049 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1053 RegisterScheduler::setDefault(Ctor);
1056 ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast);
1063 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1064 return new HazardRecognizer();
1067 //===----------------------------------------------------------------------===//
1068 // Helper functions used by the generated instruction selector.
1069 //===----------------------------------------------------------------------===//
1070 // Calls to these methods are generated by tblgen.
1072 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1073 /// the dag combiner simplified the 255, we still want to match. RHS is the
1074 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1075 /// specified in the .td file (e.g. 255).
1076 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1077 int64_t DesiredMaskS) const {
1078 const APInt &ActualMask = RHS->getAPIntValue();
1079 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1081 // If the actual mask exactly matches, success!
1082 if (ActualMask == DesiredMask)
1085 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1086 if (ActualMask.intersects(~DesiredMask))
1089 // Otherwise, the DAG Combiner may have proven that the value coming in is
1090 // either already zero or is not demanded. Check for known zero input bits.
1091 APInt NeededMask = DesiredMask & ~ActualMask;
1092 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1095 // TODO: check to see if missing bits are just not demanded.
1097 // Otherwise, this pattern doesn't match.
1101 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1102 /// the dag combiner simplified the 255, we still want to match. RHS is the
1103 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1104 /// specified in the .td file (e.g. 255).
1105 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1106 int64_t DesiredMaskS) const {
1107 const APInt &ActualMask = RHS->getAPIntValue();
1108 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1110 // If the actual mask exactly matches, success!
1111 if (ActualMask == DesiredMask)
1114 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1115 if (ActualMask.intersects(~DesiredMask))
1118 // Otherwise, the DAG Combiner may have proven that the value coming in is
1119 // either already zero or is not demanded. Check for known zero input bits.
1120 APInt NeededMask = DesiredMask & ~ActualMask;
1122 APInt KnownZero, KnownOne;
1123 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1125 // If all the missing bits in the or are already known to be set, match!
1126 if ((NeededMask & KnownOne) == NeededMask)
1129 // TODO: check to see if missing bits are just not demanded.
1131 // Otherwise, this pattern doesn't match.
1136 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1137 /// by tblgen. Others should not call it.
1138 void SelectionDAGISel::
1139 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1140 std::vector<SDValue> InOps;
1141 std::swap(InOps, Ops);
1143 Ops.push_back(InOps[0]); // input chain.
1144 Ops.push_back(InOps[1]); // input asm string.
1146 unsigned i = 2, e = InOps.size();
1147 if (InOps[e-1].getValueType() == MVT::Flag)
1148 --e; // Don't process a flag operand if it is here.
1151 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1152 if ((Flags & 7) != 4 /*MEM*/) {
1153 // Just skip over this operand, copying the operands verbatim.
1154 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
1155 i += (Flags >> 3) + 1;
1157 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
1158 // Otherwise, this is a memory operand. Ask the target to select it.
1159 std::vector<SDValue> SelOps;
1160 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1161 cerr << "Could not match memory address. Inline asm failure!\n";
1165 // Add this to the output node.
1166 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
1167 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1169 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1174 // Add the flag input back if present.
1175 if (e != InOps.size())
1176 Ops.push_back(InOps.back());
1179 char SelectionDAGISel::ID = 0;