1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/ADT/PostOrderIterator.h"
53 #include "llvm/ADT/Statistic.h"
57 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
58 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
59 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
60 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
61 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
64 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
65 cl::desc("Enable verbose messages in the \"fast\" "
66 "instruction selector"));
68 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
69 cl::desc("Enable abort calls when \"fast\" instruction fails"));
73 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
74 cl::desc("Pop up a window to show dags before the first "
77 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
78 cl::desc("Pop up a window to show dags before legalize types"));
80 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before legalize"));
83 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before the second "
87 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
88 cl::desc("Pop up a window to show dags before the post legalize types"
89 " dag combine pass"));
91 ViewISelDAGs("view-isel-dags", cl::Hidden,
92 cl::desc("Pop up a window to show isel dags as they are selected"));
94 ViewSchedDAGs("view-sched-dags", cl::Hidden,
95 cl::desc("Pop up a window to show sched dags as they are processed"));
97 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
98 cl::desc("Pop up a window to show SUnit dags after they are processed"));
100 static const bool ViewDAGCombine1 = false,
101 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
102 ViewDAGCombine2 = false,
103 ViewDAGCombineLT = false,
104 ViewISelDAGs = false, ViewSchedDAGs = false,
105 ViewSUnitDAGs = false;
108 //===---------------------------------------------------------------------===//
110 /// RegisterScheduler class - Track the registration of instruction schedulers.
112 //===---------------------------------------------------------------------===//
113 MachinePassRegistry RegisterScheduler::Registry;
115 //===---------------------------------------------------------------------===//
117 /// ISHeuristic command line option for instruction schedulers.
119 //===---------------------------------------------------------------------===//
120 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
121 RegisterPassParser<RegisterScheduler> >
122 ISHeuristic("pre-RA-sched",
123 cl::init(&createDefaultScheduler),
124 cl::desc("Instruction schedulers available (before register"
127 static RegisterScheduler
128 defaultListDAGScheduler("default", "Best scheduler for the target",
129 createDefaultScheduler);
132 //===--------------------------------------------------------------------===//
133 /// createDefaultScheduler - This creates an instruction scheduler appropriate
135 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
136 CodeGenOpt::Level OptLevel) {
137 const TargetLowering &TLI = IS->getTargetLowering();
139 if (OptLevel == CodeGenOpt::None)
140 return createSourceListDAGScheduler(IS, OptLevel);
141 if (TLI.getSchedulingPreference() == Sched::Latency)
142 return createTDListDAGScheduler(IS, OptLevel);
143 if (TLI.getSchedulingPreference() == Sched::RegPressure)
144 return createBURRListDAGScheduler(IS, OptLevel);
145 if (TLI.getSchedulingPreference() == Sched::Hybrid)
146 return createHybridListDAGScheduler(IS, OptLevel);
147 assert(TLI.getSchedulingPreference() == Sched::ILP &&
148 "Unknown sched type!");
149 return createILPListDAGScheduler(IS, OptLevel);
153 // EmitInstrWithCustomInserter - This method should be implemented by targets
154 // that mark instructions with the 'usesCustomInserter' flag. These
155 // instructions are special in various ways, which require special support to
156 // insert. The specified MachineInstr is created but not inserted into any
157 // basic blocks, and this method is called to expand it into a sequence of
158 // instructions, potentially also creating new basic blocks and control flow.
159 // When new basic blocks are inserted and the edges from MBB to its successors
160 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
163 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
164 MachineBasicBlock *MBB) const {
166 dbgs() << "If a target marks an instruction with "
167 "'usesCustomInserter', it must implement "
168 "TargetLowering::EmitInstrWithCustomInserter!";
174 //===----------------------------------------------------------------------===//
175 // SelectionDAGISel code
176 //===----------------------------------------------------------------------===//
178 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
179 CodeGenOpt::Level OL) :
180 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
181 FuncInfo(new FunctionLoweringInfo(TLI)),
182 CurDAG(new SelectionDAG(tm)),
183 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
187 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
188 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
191 SelectionDAGISel::~SelectionDAGISel() {
197 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
198 AU.addRequired<AliasAnalysis>();
199 AU.addPreserved<AliasAnalysis>();
200 AU.addRequired<GCModuleInfo>();
201 AU.addPreserved<GCModuleInfo>();
202 MachineFunctionPass::getAnalysisUsage(AU);
205 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
206 /// may trap on it. In this case we have to split the edge so that the path
207 /// through the predecessor block that doesn't go to the phi block doesn't
208 /// execute the possibly trapping instruction.
210 /// This is required for correctness, so it must be done at -O0.
212 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
213 // Loop for blocks with phi nodes.
214 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
215 PHINode *PN = dyn_cast<PHINode>(BB->begin());
216 if (PN == 0) continue;
219 // For each block with a PHI node, check to see if any of the input values
220 // are potentially trapping constant expressions. Constant expressions are
221 // the only potentially trapping value that can occur as the argument to a
223 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
224 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
225 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
226 if (CE == 0 || !CE->canTrap()) continue;
228 // The only case we have to worry about is when the edge is critical.
229 // Since this block has a PHI Node, we assume it has multiple input
230 // edges: check to see if the pred has multiple successors.
231 BasicBlock *Pred = PN->getIncomingBlock(i);
232 if (Pred->getTerminator()->getNumSuccessors() == 1)
235 // Okay, we have to split this edge.
236 SplitCriticalEdge(Pred->getTerminator(),
237 GetSuccessorNumber(Pred, BB), SDISel, true);
243 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
244 // Do some sanity-checking on the command-line options.
245 assert((!EnableFastISelVerbose || EnableFastISel) &&
246 "-fast-isel-verbose requires -fast-isel");
247 assert((!EnableFastISelAbort || EnableFastISel) &&
248 "-fast-isel-abort requires -fast-isel");
250 const Function &Fn = *mf.getFunction();
251 const TargetInstrInfo &TII = *TM.getInstrInfo();
252 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
255 RegInfo = &MF->getRegInfo();
256 AA = &getAnalysis<AliasAnalysis>();
257 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
259 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
261 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
264 FuncInfo->set(Fn, *MF);
267 SelectAllBasicBlocks(Fn);
269 // If the first basic block in the function has live ins that need to be
270 // copied into vregs, emit the copies into the top of the block before
271 // emitting the code for the block.
272 MachineBasicBlock *EntryMBB = MF->begin();
273 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
275 DenseMap<unsigned, unsigned> LiveInMap;
276 if (!FuncInfo->ArgDbgValues.empty())
277 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
278 E = RegInfo->livein_end(); LI != E; ++LI)
280 LiveInMap.insert(std::make_pair(LI->first, LI->second));
282 // Insert DBG_VALUE instructions for function arguments to the entry block.
283 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
284 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
285 unsigned Reg = MI->getOperand(0).getReg();
286 if (TargetRegisterInfo::isPhysicalRegister(Reg))
287 EntryMBB->insert(EntryMBB->begin(), MI);
289 MachineInstr *Def = RegInfo->getVRegDef(Reg);
290 MachineBasicBlock::iterator InsertPos = Def;
291 // FIXME: VR def may not be in entry block.
292 Def->getParent()->insert(llvm::next(InsertPos), MI);
295 // If Reg is live-in then update debug info to track its copy in a vreg.
296 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
297 if (LDI != LiveInMap.end()) {
298 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
299 MachineBasicBlock::iterator InsertPos = Def;
300 const MDNode *Variable =
301 MI->getOperand(MI->getNumOperands()-1).getMetadata();
302 unsigned Offset = MI->getOperand(1).getImm();
303 // Def is never a terminator here, so it is ok to increment InsertPos.
304 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
305 TII.get(TargetOpcode::DBG_VALUE))
306 .addReg(LDI->second, RegState::Debug)
307 .addImm(Offset).addMetadata(Variable);
309 // If this vreg is directly copied into an exported register then
310 // that COPY instructions also need DBG_VALUE, if it is the only
311 // user of LDI->second.
312 MachineInstr *CopyUseMI = NULL;
313 for (MachineRegisterInfo::use_iterator
314 UI = RegInfo->use_begin(LDI->second);
315 MachineInstr *UseMI = UI.skipInstruction();) {
316 if (UseMI->isDebugValue()) continue;
317 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
318 CopyUseMI = UseMI; continue;
320 // Otherwise this is another use or second copy use.
321 CopyUseMI = NULL; break;
324 MachineInstr *NewMI =
325 BuildMI(*MF, CopyUseMI->getDebugLoc(),
326 TII.get(TargetOpcode::DBG_VALUE))
327 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
328 .addImm(Offset).addMetadata(Variable);
329 EntryMBB->insertAfter(CopyUseMI, NewMI);
334 // Determine if there are any calls in this machine function.
335 MachineFrameInfo *MFI = MF->getFrameInfo();
336 if (!MFI->hasCalls()) {
337 for (MachineFunction::const_iterator
338 I = MF->begin(), E = MF->end(); I != E; ++I) {
339 const MachineBasicBlock *MBB = I;
340 for (MachineBasicBlock::const_iterator
341 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
342 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
344 if ((TID.isCall() && !TID.isReturn()) ||
345 II->isStackAligningInlineAsm()) {
346 MFI->setHasCalls(true);
354 // Determine if there is a call to setjmp in the machine function.
355 MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice());
357 // Replace forward-declared registers with the registers containing
358 // the desired value.
359 MachineRegisterInfo &MRI = MF->getRegInfo();
360 for (DenseMap<unsigned, unsigned>::iterator
361 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
363 unsigned From = I->first;
364 unsigned To = I->second;
365 // If To is also scheduled to be replaced, find what its ultimate
368 DenseMap<unsigned, unsigned>::iterator J =
369 FuncInfo->RegFixups.find(To);
374 MRI.replaceRegWith(From, To);
377 // Release function-specific state. SDB and CurDAG are already cleared
384 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
385 BasicBlock::const_iterator End,
387 // Lower all of the non-terminator instructions. If a call is emitted
388 // as a tail call, cease emitting nodes for this block. Terminators
389 // are handled below.
390 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
393 // Make sure the root of the DAG is up-to-date.
394 CurDAG->setRoot(SDB->getControlRoot());
395 HadTailCall = SDB->HasTailCall;
398 // Final step, emit the lowered DAG as machine code.
402 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
403 SmallPtrSet<SDNode*, 128> VisitedNodes;
404 SmallVector<SDNode*, 128> Worklist;
406 Worklist.push_back(CurDAG->getRoot().getNode());
413 SDNode *N = Worklist.pop_back_val();
415 // If we've already seen this node, ignore it.
416 if (!VisitedNodes.insert(N))
419 // Otherwise, add all chain operands to the worklist.
420 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
421 if (N->getOperand(i).getValueType() == MVT::Other)
422 Worklist.push_back(N->getOperand(i).getNode());
424 // If this is a CopyToReg with a vreg dest, process it.
425 if (N->getOpcode() != ISD::CopyToReg)
428 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
429 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
432 // Ignore non-scalar or non-integer values.
433 SDValue Src = N->getOperand(2);
434 EVT SrcVT = Src.getValueType();
435 if (!SrcVT.isInteger() || SrcVT.isVector())
438 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
439 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
440 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
441 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
442 } while (!Worklist.empty());
445 void SelectionDAGISel::CodeGenAndEmitDAG() {
446 std::string GroupName;
447 if (TimePassesIsEnabled)
448 GroupName = "Instruction Selection and Scheduling";
449 std::string BlockName;
450 int BlockNumber = -1;
452 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
453 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
457 BlockNumber = FuncInfo->MBB->getNumber();
458 BlockName = MF->getFunction()->getNameStr() + ":" +
459 FuncInfo->MBB->getBasicBlock()->getNameStr();
461 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
462 << " '" << BlockName << "'\n"; CurDAG->dump());
464 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
466 // Run the DAG combiner in pre-legalize mode.
468 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
469 CurDAG->Combine(Unrestricted, *AA, OptLevel);
472 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
473 << " '" << BlockName << "'\n"; CurDAG->dump());
475 // Second step, hack on the DAG until it only uses operations and types that
476 // the target supports.
477 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
482 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
483 Changed = CurDAG->LegalizeTypes();
486 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
487 << " '" << BlockName << "'\n"; CurDAG->dump());
490 if (ViewDAGCombineLT)
491 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
493 // Run the DAG combiner in post-type-legalize mode.
495 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
496 TimePassesIsEnabled);
497 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
500 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
501 << " '" << BlockName << "'\n"; CurDAG->dump());
505 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
506 Changed = CurDAG->LegalizeVectors();
511 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
512 CurDAG->LegalizeTypes();
515 if (ViewDAGCombineLT)
516 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
518 // Run the DAG combiner in post-type-legalize mode.
520 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
521 TimePassesIsEnabled);
522 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
525 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
526 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
529 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
532 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
536 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
537 << " '" << BlockName << "'\n"; CurDAG->dump());
539 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
541 // Run the DAG combiner in post-legalize mode.
543 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
544 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
547 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
548 << " '" << BlockName << "'\n"; CurDAG->dump());
550 if (OptLevel != CodeGenOpt::None)
551 ComputeLiveOutVRegInfo();
553 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
555 // Third, instruction select all of the operations to machine code, adding the
556 // code to the MachineBasicBlock.
558 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
559 DoInstructionSelection();
562 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
563 << " '" << BlockName << "'\n"; CurDAG->dump());
565 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
567 // Schedule machine code.
568 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
570 NamedRegionTimer T("Instruction Scheduling", GroupName,
571 TimePassesIsEnabled);
572 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
575 if (ViewSUnitDAGs) Scheduler->viewGraph();
577 // Emit machine code to BB. This can change 'BB' to the last block being
579 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
581 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
583 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
584 FuncInfo->InsertPt = Scheduler->InsertPos;
587 // If the block was split, make sure we update any references that are used to
588 // update PHI nodes later on.
589 if (FirstMBB != LastMBB)
590 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
592 // Free the scheduler state.
594 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
595 TimePassesIsEnabled);
599 // Free the SelectionDAG state, now that we're finished with it.
603 void SelectionDAGISel::DoInstructionSelection() {
604 DEBUG(errs() << "===== Instruction selection begins: BB#"
605 << FuncInfo->MBB->getNumber()
606 << " '" << FuncInfo->MBB->getName() << "'\n");
610 // Select target instructions for the DAG.
612 // Number all nodes with a topological order and set DAGSize.
613 DAGSize = CurDAG->AssignTopologicalOrder();
615 // Create a dummy node (which is not added to allnodes), that adds
616 // a reference to the root node, preventing it from being deleted,
617 // and tracking any changes of the root.
618 HandleSDNode Dummy(CurDAG->getRoot());
619 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
622 // The AllNodes list is now topological-sorted. Visit the
623 // nodes by starting at the end of the list (the root of the
624 // graph) and preceding back toward the beginning (the entry
626 while (ISelPosition != CurDAG->allnodes_begin()) {
627 SDNode *Node = --ISelPosition;
628 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
629 // but there are currently some corner cases that it misses. Also, this
630 // makes it theoretically possible to disable the DAGCombiner.
631 if (Node->use_empty())
634 SDNode *ResNode = Select(Node);
636 // FIXME: This is pretty gross. 'Select' should be changed to not return
637 // anything at all and this code should be nuked with a tactical strike.
639 // If node should not be replaced, continue with the next one.
640 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
644 ReplaceUses(Node, ResNode);
646 // If after the replacement this node is not used any more,
647 // remove this dead node.
648 if (Node->use_empty()) { // Don't delete EntryToken, etc.
649 ISelUpdater ISU(ISelPosition);
650 CurDAG->RemoveDeadNode(Node, &ISU);
654 CurDAG->setRoot(Dummy.getValue());
657 DEBUG(errs() << "===== Instruction selection ends:\n");
659 PostprocessISelDAG();
662 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
663 /// do other setup for EH landing-pad blocks.
664 void SelectionDAGISel::PrepareEHLandingPad() {
665 // Add a label to mark the beginning of the landing pad. Deletion of the
666 // landing pad can thus be detected via the MachineModuleInfo.
667 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
669 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
670 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
673 // Mark exception register as live in.
674 unsigned Reg = TLI.getExceptionAddressRegister();
675 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
677 // Mark exception selector register as live in.
678 Reg = TLI.getExceptionSelectorRegister();
679 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
681 // FIXME: Hack around an exception handling flaw (PR1508): the personality
682 // function and list of typeids logically belong to the invoke (or, if you
683 // like, the basic block containing the invoke), and need to be associated
684 // with it in the dwarf exception handling tables. Currently however the
685 // information is provided by an intrinsic (eh.selector) that can be moved
686 // to unexpected places by the optimizers: if the unwind edge is critical,
687 // then breaking it can result in the intrinsics being in the successor of
688 // the landing pad, not the landing pad itself. This results
689 // in exceptions not being caught because no typeids are associated with
690 // the invoke. This may not be the only way things can go wrong, but it
691 // is the only way we try to work around for the moment.
692 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
693 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
695 if (Br && Br->isUnconditional()) { // Critical edge?
696 BasicBlock::const_iterator I, E;
697 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
698 if (isa<EHSelectorInst>(I))
702 // No catch info found - try to extract some from the successor.
703 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
709 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
710 /// load into the specified FoldInst. Note that we could have a sequence where
711 /// multiple LLVM IR instructions are folded into the same machineinstr. For
712 /// example we could have:
713 /// A: x = load i32 *P
714 /// B: y = icmp A, 42
717 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
718 /// any other folded instructions) because it is between A and C.
720 /// If we succeed in folding the load into the operation, return true.
722 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
723 const Instruction *FoldInst,
725 // We know that the load has a single use, but don't know what it is. If it
726 // isn't one of the folded instructions, then we can't succeed here. Handle
727 // this by scanning the single-use users of the load until we get to FoldInst.
728 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
730 const Instruction *TheUser = LI->use_back();
731 while (TheUser != FoldInst && // Scan up until we find FoldInst.
732 // Stay in the right block.
733 TheUser->getParent() == FoldInst->getParent() &&
734 --MaxUsers) { // Don't scan too far.
735 // If there are multiple or no uses of this instruction, then bail out.
736 if (!TheUser->hasOneUse())
739 TheUser = TheUser->use_back();
742 // Don't try to fold volatile loads. Target has to deal with alignment
744 if (LI->isVolatile()) return false;
746 // Figure out which vreg this is going into. If there is no assigned vreg yet
747 // then there actually was no reference to it. Perhaps the load is referenced
748 // by a dead instruction.
749 unsigned LoadReg = FastIS->getRegForValue(LI);
753 // Check to see what the uses of this vreg are. If it has no uses, or more
754 // than one use (at the machine instr level) then we can't fold it.
755 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
756 if (RI == RegInfo->reg_end())
759 // See if there is exactly one use of the vreg. If there are multiple uses,
760 // then the instruction got lowered to multiple machine instructions or the
761 // use of the loaded value ended up being multiple operands of the result, in
762 // either case, we can't fold this.
763 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
764 if (PostRI != RegInfo->reg_end())
767 assert(RI.getOperand().isUse() &&
768 "The only use of the vreg must be a use, we haven't emitted the def!");
770 MachineInstr *User = &*RI;
772 // Set the insertion point properly. Folding the load can cause generation of
773 // other random instructions (like sign extends) for addressing modes, make
774 // sure they get inserted in a logical place before the new instruction.
775 FuncInfo->InsertPt = User;
776 FuncInfo->MBB = User->getParent();
778 // Ask the target to try folding the load.
779 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
782 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
783 /// side-effect free and is either dead or folded into a generated instruction.
784 /// Return false if it needs to be emitted.
785 static bool isFoldedOrDeadInstruction(const Instruction *I,
786 FunctionLoweringInfo *FuncInfo) {
787 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
788 !isa<TerminatorInst>(I) && // Terminators aren't folded.
789 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
790 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
793 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
794 // Initialize the Fast-ISel state, if needed.
795 FastISel *FastIS = 0;
797 FastIS = TLI.createFastISel(*FuncInfo);
799 // Iterate over all basic blocks in the function.
800 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
801 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
802 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
803 const BasicBlock *LLVMBB = *I;
805 if (OptLevel != CodeGenOpt::None) {
806 bool AllPredsVisited = true;
807 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
809 if (!FuncInfo->VisitedBBs.count(*PI)) {
810 AllPredsVisited = false;
815 if (AllPredsVisited) {
816 for (BasicBlock::const_iterator I = LLVMBB->begin();
817 isa<PHINode>(I); ++I)
818 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
820 for (BasicBlock::const_iterator I = LLVMBB->begin();
821 isa<PHINode>(I); ++I)
822 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
825 FuncInfo->VisitedBBs.insert(LLVMBB);
828 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
829 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
831 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
832 BasicBlock::const_iterator const End = LLVMBB->end();
833 BasicBlock::const_iterator BI = End;
835 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
837 // Setup an EH landing-pad block.
838 if (FuncInfo->MBB->isLandingPad())
839 PrepareEHLandingPad();
841 // Lower any arguments needed in this block if this is the entry block.
842 if (LLVMBB == &Fn.getEntryBlock())
843 LowerArguments(LLVMBB);
845 // Before doing SelectionDAG ISel, see if FastISel has been requested.
847 FastIS->startNewBlock();
849 // Emit code for any incoming arguments. This must happen before
850 // beginning FastISel on the entry block.
851 if (LLVMBB == &Fn.getEntryBlock()) {
852 CurDAG->setRoot(SDB->getControlRoot());
856 // If we inserted any instructions at the beginning, make a note of
857 // where they are, so we can be sure to emit subsequent instructions
859 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
860 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
862 FastIS->setLastLocalValue(0);
865 // Do FastISel on as many instructions as possible.
866 for (; BI != Begin; --BI) {
867 const Instruction *Inst = llvm::prior(BI);
869 // If we no longer require this instruction, skip it.
870 if (isFoldedOrDeadInstruction(Inst, FuncInfo))
873 // Bottom-up: reset the insert pos at the top, after any local-value
875 FastIS->recomputeInsertPt();
877 // Try to select the instruction with FastISel.
878 if (FastIS->SelectInstruction(Inst)) {
879 ++NumFastIselSuccess;
880 // If fast isel succeeded, skip over all the folded instructions, and
881 // then see if there is a load right before the selected instructions.
882 // Try to fold the load if so.
883 const Instruction *BeforeInst = Inst;
884 while (BeforeInst != Begin) {
885 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
886 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
889 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
890 BeforeInst->hasOneUse() &&
891 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS))
892 // If we succeeded, don't re-select the load.
893 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
897 // Then handle certain instructions as single-LLVM-Instruction blocks.
898 if (isa<CallInst>(Inst)) {
899 ++NumFastIselFailures;
900 if (EnableFastISelVerbose || EnableFastISelAbort) {
901 dbgs() << "FastISel missed call: ";
905 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
906 unsigned &R = FuncInfo->ValueMap[Inst];
908 R = FuncInfo->CreateRegs(Inst->getType());
911 bool HadTailCall = false;
912 SelectBasicBlock(Inst, BI, HadTailCall);
914 // If the call was emitted as a tail call, we're done with the block.
923 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
924 // Don't abort, and use a different message for terminator misses.
925 ++NumFastIselFailures;
926 if (EnableFastISelVerbose || EnableFastISelAbort) {
927 dbgs() << "FastISel missed terminator: ";
931 ++NumFastIselFailures;
932 if (EnableFastISelVerbose || EnableFastISelAbort) {
933 dbgs() << "FastISel miss: ";
936 if (EnableFastISelAbort)
937 // The "fast" selector couldn't handle something and bailed.
938 // For the purpose of debugging, just abort.
939 llvm_unreachable("FastISel didn't select the entire block");
944 FastIS->recomputeInsertPt();
953 // Run SelectionDAG instruction selection on the remainder of the block
954 // not handled by FastISel. If FastISel is not run, this is the entire
957 SelectBasicBlock(Begin, BI, HadTailCall);
961 FuncInfo->PHINodesToUpdate.clear();
965 SDB->clearDanglingDebugInfo();
969 SelectionDAGISel::FinishBasicBlock() {
971 DEBUG(dbgs() << "Total amount of phi nodes to update: "
972 << FuncInfo->PHINodesToUpdate.size() << "\n";
973 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
974 dbgs() << "Node " << i << " : ("
975 << FuncInfo->PHINodesToUpdate[i].first
976 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
978 // Next, now that we know what the last MBB the LLVM BB expanded is, update
979 // PHI nodes in successors.
980 if (SDB->SwitchCases.empty() &&
981 SDB->JTCases.empty() &&
982 SDB->BitTestCases.empty()) {
983 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
984 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
985 assert(PHI->isPHI() &&
986 "This is not a machine PHI node that we are updating!");
987 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
990 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
991 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
996 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
997 // Lower header first, if it wasn't already lowered
998 if (!SDB->BitTestCases[i].Emitted) {
999 // Set the current basic block to the mbb we wish to insert the code into
1000 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1001 FuncInfo->InsertPt = FuncInfo->MBB->end();
1003 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1004 CurDAG->setRoot(SDB->getRoot());
1006 CodeGenAndEmitDAG();
1009 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1010 // Set the current basic block to the mbb we wish to insert the code into
1011 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1012 FuncInfo->InsertPt = FuncInfo->MBB->end();
1015 SDB->visitBitTestCase(SDB->BitTestCases[i],
1016 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1017 SDB->BitTestCases[i].Reg,
1018 SDB->BitTestCases[i].Cases[j],
1021 SDB->visitBitTestCase(SDB->BitTestCases[i],
1022 SDB->BitTestCases[i].Default,
1023 SDB->BitTestCases[i].Reg,
1024 SDB->BitTestCases[i].Cases[j],
1028 CurDAG->setRoot(SDB->getRoot());
1030 CodeGenAndEmitDAG();
1034 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1036 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1037 MachineBasicBlock *PHIBB = PHI->getParent();
1038 assert(PHI->isPHI() &&
1039 "This is not a machine PHI node that we are updating!");
1040 // This is "default" BB. We have two jumps to it. From "header" BB and
1041 // from last "case" BB.
1042 if (PHIBB == SDB->BitTestCases[i].Default) {
1043 PHI->addOperand(MachineOperand::
1044 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1046 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1047 PHI->addOperand(MachineOperand::
1048 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1050 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1053 // One of "cases" BB.
1054 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1056 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1057 if (cBB->isSuccessor(PHIBB)) {
1058 PHI->addOperand(MachineOperand::
1059 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1061 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1066 SDB->BitTestCases.clear();
1068 // If the JumpTable record is filled in, then we need to emit a jump table.
1069 // Updating the PHI nodes is tricky in this case, since we need to determine
1070 // whether the PHI is a successor of the range check MBB or the jump table MBB
1071 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1072 // Lower header first, if it wasn't already lowered
1073 if (!SDB->JTCases[i].first.Emitted) {
1074 // Set the current basic block to the mbb we wish to insert the code into
1075 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1076 FuncInfo->InsertPt = FuncInfo->MBB->end();
1078 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1080 CurDAG->setRoot(SDB->getRoot());
1082 CodeGenAndEmitDAG();
1085 // Set the current basic block to the mbb we wish to insert the code into
1086 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1087 FuncInfo->InsertPt = FuncInfo->MBB->end();
1089 SDB->visitJumpTable(SDB->JTCases[i].second);
1090 CurDAG->setRoot(SDB->getRoot());
1092 CodeGenAndEmitDAG();
1095 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1097 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1098 MachineBasicBlock *PHIBB = PHI->getParent();
1099 assert(PHI->isPHI() &&
1100 "This is not a machine PHI node that we are updating!");
1101 // "default" BB. We can go there only from header BB.
1102 if (PHIBB == SDB->JTCases[i].second.Default) {
1104 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1107 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1109 // JT BB. Just iterate over successors here
1110 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1112 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1114 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1118 SDB->JTCases.clear();
1120 // If the switch block involved a branch to one of the actual successors, we
1121 // need to update PHI nodes in that block.
1122 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1123 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1124 assert(PHI->isPHI() &&
1125 "This is not a machine PHI node that we are updating!");
1126 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1128 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1129 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1133 // If we generated any switch lowering information, build and codegen any
1134 // additional DAGs necessary.
1135 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1136 // Set the current basic block to the mbb we wish to insert the code into
1137 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1138 FuncInfo->InsertPt = FuncInfo->MBB->end();
1140 // Determine the unique successors.
1141 SmallVector<MachineBasicBlock *, 2> Succs;
1142 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1143 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1144 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1146 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1147 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1148 CurDAG->setRoot(SDB->getRoot());
1150 CodeGenAndEmitDAG();
1152 // Remember the last block, now that any splitting is done, for use in
1153 // populating PHI nodes in successors.
1154 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1156 // Handle any PHI nodes in successors of this chunk, as if we were coming
1157 // from the original BB before switch expansion. Note that PHI nodes can
1158 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1159 // handle them the right number of times.
1160 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1161 FuncInfo->MBB = Succs[i];
1162 FuncInfo->InsertPt = FuncInfo->MBB->end();
1163 // FuncInfo->MBB may have been removed from the CFG if a branch was
1165 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1166 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1167 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1169 // This value for this PHI node is recorded in PHINodesToUpdate.
1170 for (unsigned pn = 0; ; ++pn) {
1171 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1172 "Didn't find PHI entry!");
1173 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1174 Phi->addOperand(MachineOperand::
1175 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1177 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1185 SDB->SwitchCases.clear();
1189 /// Create the scheduler. If a specific scheduler was specified
1190 /// via the SchedulerRegistry, use it, otherwise select the
1191 /// one preferred by the target.
1193 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1194 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1198 RegisterScheduler::setDefault(Ctor);
1201 return Ctor(this, OptLevel);
1204 //===----------------------------------------------------------------------===//
1205 // Helper functions used by the generated instruction selector.
1206 //===----------------------------------------------------------------------===//
1207 // Calls to these methods are generated by tblgen.
1209 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1210 /// the dag combiner simplified the 255, we still want to match. RHS is the
1211 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1212 /// specified in the .td file (e.g. 255).
1213 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1214 int64_t DesiredMaskS) const {
1215 const APInt &ActualMask = RHS->getAPIntValue();
1216 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1218 // If the actual mask exactly matches, success!
1219 if (ActualMask == DesiredMask)
1222 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1223 if (ActualMask.intersects(~DesiredMask))
1226 // Otherwise, the DAG Combiner may have proven that the value coming in is
1227 // either already zero or is not demanded. Check for known zero input bits.
1228 APInt NeededMask = DesiredMask & ~ActualMask;
1229 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1232 // TODO: check to see if missing bits are just not demanded.
1234 // Otherwise, this pattern doesn't match.
1238 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1239 /// the dag combiner simplified the 255, we still want to match. RHS is the
1240 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1241 /// specified in the .td file (e.g. 255).
1242 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1243 int64_t DesiredMaskS) const {
1244 const APInt &ActualMask = RHS->getAPIntValue();
1245 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1247 // If the actual mask exactly matches, success!
1248 if (ActualMask == DesiredMask)
1251 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1252 if (ActualMask.intersects(~DesiredMask))
1255 // Otherwise, the DAG Combiner may have proven that the value coming in is
1256 // either already zero or is not demanded. Check for known zero input bits.
1257 APInt NeededMask = DesiredMask & ~ActualMask;
1259 APInt KnownZero, KnownOne;
1260 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1262 // If all the missing bits in the or are already known to be set, match!
1263 if ((NeededMask & KnownOne) == NeededMask)
1266 // TODO: check to see if missing bits are just not demanded.
1268 // Otherwise, this pattern doesn't match.
1273 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1274 /// by tblgen. Others should not call it.
1275 void SelectionDAGISel::
1276 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1277 std::vector<SDValue> InOps;
1278 std::swap(InOps, Ops);
1280 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1281 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1282 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1283 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1285 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1286 if (InOps[e-1].getValueType() == MVT::Glue)
1287 --e; // Don't process a glue operand if it is here.
1290 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1291 if (!InlineAsm::isMemKind(Flags)) {
1292 // Just skip over this operand, copying the operands verbatim.
1293 Ops.insert(Ops.end(), InOps.begin()+i,
1294 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1295 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1297 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1298 "Memory operand with multiple values?");
1299 // Otherwise, this is a memory operand. Ask the target to select it.
1300 std::vector<SDValue> SelOps;
1301 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1302 report_fatal_error("Could not match memory address. Inline asm"
1305 // Add this to the output node.
1307 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1308 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1309 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1314 // Add the glue input back if present.
1315 if (e != InOps.size())
1316 Ops.push_back(InOps.back());
1319 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1322 static SDNode *findGlueUse(SDNode *N) {
1323 unsigned FlagResNo = N->getNumValues()-1;
1324 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1325 SDUse &Use = I.getUse();
1326 if (Use.getResNo() == FlagResNo)
1327 return Use.getUser();
1332 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1333 /// This function recursively traverses up the operand chain, ignoring
1335 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1336 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1337 bool IgnoreChains) {
1338 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1339 // greater than all of its (recursive) operands. If we scan to a point where
1340 // 'use' is smaller than the node we're scanning for, then we know we will
1343 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1344 // happen because we scan down to newly selected nodes in the case of glue
1346 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1349 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1350 // won't fail if we scan it again.
1351 if (!Visited.insert(Use))
1354 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1355 // Ignore chain uses, they are validated by HandleMergeInputChains.
1356 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1359 SDNode *N = Use->getOperand(i).getNode();
1361 if (Use == ImmedUse || Use == Root)
1362 continue; // We are not looking for immediate use.
1367 // Traverse up the operand chain.
1368 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1374 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1375 /// operand node N of U during instruction selection that starts at Root.
1376 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1377 SDNode *Root) const {
1378 if (OptLevel == CodeGenOpt::None) return false;
1379 return N.hasOneUse();
1382 /// IsLegalToFold - Returns true if the specific operand node N of
1383 /// U can be folded during instruction selection that starts at Root.
1384 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1385 CodeGenOpt::Level OptLevel,
1386 bool IgnoreChains) {
1387 if (OptLevel == CodeGenOpt::None) return false;
1389 // If Root use can somehow reach N through a path that that doesn't contain
1390 // U then folding N would create a cycle. e.g. In the following
1391 // diagram, Root can reach N through X. If N is folded into into Root, then
1392 // X is both a predecessor and a successor of U.
1403 // * indicates nodes to be folded together.
1405 // If Root produces glue, then it gets (even more) interesting. Since it
1406 // will be "glued" together with its glue use in the scheduler, we need to
1407 // check if it might reach N.
1426 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1427 // (call it Fold), then X is a predecessor of GU and a successor of
1428 // Fold. But since Fold and GU are glued together, this will create
1429 // a cycle in the scheduling graph.
1431 // If the node has glue, walk down the graph to the "lowest" node in the
1433 EVT VT = Root->getValueType(Root->getNumValues()-1);
1434 while (VT == MVT::Glue) {
1435 SDNode *GU = findGlueUse(Root);
1439 VT = Root->getValueType(Root->getNumValues()-1);
1441 // If our query node has a glue result with a use, we've walked up it. If
1442 // the user (which has already been selected) has a chain or indirectly uses
1443 // the chain, our WalkChainUsers predicate will not consider it. Because of
1444 // this, we cannot ignore chains in this predicate.
1445 IgnoreChains = false;
1449 SmallPtrSet<SDNode*, 16> Visited;
1450 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1453 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1454 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1455 SelectInlineAsmMemoryOperands(Ops);
1457 std::vector<EVT> VTs;
1458 VTs.push_back(MVT::Other);
1459 VTs.push_back(MVT::Glue);
1460 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1461 VTs, &Ops[0], Ops.size());
1463 return New.getNode();
1466 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1467 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1470 /// GetVBR - decode a vbr encoding whose top bit is set.
1471 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1472 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1473 assert(Val >= 128 && "Not a VBR");
1474 Val &= 127; // Remove first vbr bit.
1479 NextBits = MatcherTable[Idx++];
1480 Val |= (NextBits&127) << Shift;
1482 } while (NextBits & 128);
1488 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1489 /// interior glue and chain results to use the new glue and chain results.
1490 void SelectionDAGISel::
1491 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1492 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1494 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1495 bool isMorphNodeTo) {
1496 SmallVector<SDNode*, 4> NowDeadNodes;
1498 ISelUpdater ISU(ISelPosition);
1500 // Now that all the normal results are replaced, we replace the chain and
1501 // glue results if present.
1502 if (!ChainNodesMatched.empty()) {
1503 assert(InputChain.getNode() != 0 &&
1504 "Matched input chains but didn't produce a chain");
1505 // Loop over all of the nodes we matched that produced a chain result.
1506 // Replace all the chain results with the final chain we ended up with.
1507 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1508 SDNode *ChainNode = ChainNodesMatched[i];
1510 // If this node was already deleted, don't look at it.
1511 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1514 // Don't replace the results of the root node if we're doing a
1516 if (ChainNode == NodeToMatch && isMorphNodeTo)
1519 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1520 if (ChainVal.getValueType() == MVT::Glue)
1521 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1522 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1523 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1525 // If the node became dead and we haven't already seen it, delete it.
1526 if (ChainNode->use_empty() &&
1527 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1528 NowDeadNodes.push_back(ChainNode);
1532 // If the result produces glue, update any glue results in the matched
1533 // pattern with the glue result.
1534 if (InputGlue.getNode() != 0) {
1535 // Handle any interior nodes explicitly marked.
1536 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1537 SDNode *FRN = GlueResultNodesMatched[i];
1539 // If this node was already deleted, don't look at it.
1540 if (FRN->getOpcode() == ISD::DELETED_NODE)
1543 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1544 "Doesn't have a glue result");
1545 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1548 // If the node became dead and we haven't already seen it, delete it.
1549 if (FRN->use_empty() &&
1550 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1551 NowDeadNodes.push_back(FRN);
1555 if (!NowDeadNodes.empty())
1556 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1558 DEBUG(errs() << "ISEL: Match complete!\n");
1564 CR_LeadsToInteriorNode
1567 /// WalkChainUsers - Walk down the users of the specified chained node that is
1568 /// part of the pattern we're matching, looking at all of the users we find.
1569 /// This determines whether something is an interior node, whether we have a
1570 /// non-pattern node in between two pattern nodes (which prevent folding because
1571 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1572 /// between pattern nodes (in which case the TF becomes part of the pattern).
1574 /// The walk we do here is guaranteed to be small because we quickly get down to
1575 /// already selected nodes "below" us.
1577 WalkChainUsers(SDNode *ChainedNode,
1578 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1579 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1580 ChainResult Result = CR_Simple;
1582 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1583 E = ChainedNode->use_end(); UI != E; ++UI) {
1584 // Make sure the use is of the chain, not some other value we produce.
1585 if (UI.getUse().getValueType() != MVT::Other) continue;
1589 // If we see an already-selected machine node, then we've gone beyond the
1590 // pattern that we're selecting down into the already selected chunk of the
1592 if (User->isMachineOpcode() ||
1593 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1596 if (User->getOpcode() == ISD::CopyToReg ||
1597 User->getOpcode() == ISD::CopyFromReg ||
1598 User->getOpcode() == ISD::INLINEASM ||
1599 User->getOpcode() == ISD::EH_LABEL) {
1600 // If their node ID got reset to -1 then they've already been selected.
1601 // Treat them like a MachineOpcode.
1602 if (User->getNodeId() == -1)
1606 // If we have a TokenFactor, we handle it specially.
1607 if (User->getOpcode() != ISD::TokenFactor) {
1608 // If the node isn't a token factor and isn't part of our pattern, then it
1609 // must be a random chained node in between two nodes we're selecting.
1610 // This happens when we have something like:
1615 // Because we structurally match the load/store as a read/modify/write,
1616 // but the call is chained between them. We cannot fold in this case
1617 // because it would induce a cycle in the graph.
1618 if (!std::count(ChainedNodesInPattern.begin(),
1619 ChainedNodesInPattern.end(), User))
1620 return CR_InducesCycle;
1622 // Otherwise we found a node that is part of our pattern. For example in:
1626 // This would happen when we're scanning down from the load and see the
1627 // store as a user. Record that there is a use of ChainedNode that is
1628 // part of the pattern and keep scanning uses.
1629 Result = CR_LeadsToInteriorNode;
1630 InteriorChainedNodes.push_back(User);
1634 // If we found a TokenFactor, there are two cases to consider: first if the
1635 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1636 // uses of the TF are in our pattern) we just want to ignore it. Second,
1637 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1643 // | \ DAG's like cheese
1646 // [TokenFactor] [Op]
1653 // In this case, the TokenFactor becomes part of our match and we rewrite it
1654 // as a new TokenFactor.
1656 // To distinguish these two cases, do a recursive walk down the uses.
1657 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1659 // If the uses of the TokenFactor are just already-selected nodes, ignore
1660 // it, it is "below" our pattern.
1662 case CR_InducesCycle:
1663 // If the uses of the TokenFactor lead to nodes that are not part of our
1664 // pattern that are not selected, folding would turn this into a cycle,
1666 return CR_InducesCycle;
1667 case CR_LeadsToInteriorNode:
1668 break; // Otherwise, keep processing.
1671 // Okay, we know we're in the interesting interior case. The TokenFactor
1672 // is now going to be considered part of the pattern so that we rewrite its
1673 // uses (it may have uses that are not part of the pattern) with the
1674 // ultimate chain result of the generated code. We will also add its chain
1675 // inputs as inputs to the ultimate TokenFactor we create.
1676 Result = CR_LeadsToInteriorNode;
1677 ChainedNodesInPattern.push_back(User);
1678 InteriorChainedNodes.push_back(User);
1685 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1686 /// operation for when the pattern matched at least one node with a chains. The
1687 /// input vector contains a list of all of the chained nodes that we match. We
1688 /// must determine if this is a valid thing to cover (i.e. matching it won't
1689 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1690 /// be used as the input node chain for the generated nodes.
1692 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1693 SelectionDAG *CurDAG) {
1694 // Walk all of the chained nodes we've matched, recursively scanning down the
1695 // users of the chain result. This adds any TokenFactor nodes that are caught
1696 // in between chained nodes to the chained and interior nodes list.
1697 SmallVector<SDNode*, 3> InteriorChainedNodes;
1698 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1699 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1700 InteriorChainedNodes) == CR_InducesCycle)
1701 return SDValue(); // Would induce a cycle.
1704 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1705 // that we are interested in. Form our input TokenFactor node.
1706 SmallVector<SDValue, 3> InputChains;
1707 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1708 // Add the input chain of this node to the InputChains list (which will be
1709 // the operands of the generated TokenFactor) if it's not an interior node.
1710 SDNode *N = ChainNodesMatched[i];
1711 if (N->getOpcode() != ISD::TokenFactor) {
1712 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1715 // Otherwise, add the input chain.
1716 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1717 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1718 InputChains.push_back(InChain);
1722 // If we have a token factor, we want to add all inputs of the token factor
1723 // that are not part of the pattern we're matching.
1724 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1725 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1726 N->getOperand(op).getNode()))
1727 InputChains.push_back(N->getOperand(op));
1732 if (InputChains.size() == 1)
1733 return InputChains[0];
1734 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1735 MVT::Other, &InputChains[0], InputChains.size());
1738 /// MorphNode - Handle morphing a node in place for the selector.
1739 SDNode *SelectionDAGISel::
1740 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1741 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1742 // It is possible we're using MorphNodeTo to replace a node with no
1743 // normal results with one that has a normal result (or we could be
1744 // adding a chain) and the input could have glue and chains as well.
1745 // In this case we need to shift the operands down.
1746 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1747 // than the old isel though.
1748 int OldGlueResultNo = -1, OldChainResultNo = -1;
1750 unsigned NTMNumResults = Node->getNumValues();
1751 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1752 OldGlueResultNo = NTMNumResults-1;
1753 if (NTMNumResults != 1 &&
1754 Node->getValueType(NTMNumResults-2) == MVT::Other)
1755 OldChainResultNo = NTMNumResults-2;
1756 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1757 OldChainResultNo = NTMNumResults-1;
1759 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1760 // that this deletes operands of the old node that become dead.
1761 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1763 // MorphNodeTo can operate in two ways: if an existing node with the
1764 // specified operands exists, it can just return it. Otherwise, it
1765 // updates the node in place to have the requested operands.
1767 // If we updated the node in place, reset the node ID. To the isel,
1768 // this should be just like a newly allocated machine node.
1772 unsigned ResNumResults = Res->getNumValues();
1773 // Move the glue if needed.
1774 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1775 (unsigned)OldGlueResultNo != ResNumResults-1)
1776 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1777 SDValue(Res, ResNumResults-1));
1779 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1782 // Move the chain reference if needed.
1783 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1784 (unsigned)OldChainResultNo != ResNumResults-1)
1785 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1786 SDValue(Res, ResNumResults-1));
1788 // Otherwise, no replacement happened because the node already exists. Replace
1789 // Uses of the old node with the new one.
1791 CurDAG->ReplaceAllUsesWith(Node, Res);
1796 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1797 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1798 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1800 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1801 // Accept if it is exactly the same as a previously recorded node.
1802 unsigned RecNo = MatcherTable[MatcherIndex++];
1803 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1804 return N == RecordedNodes[RecNo].first;
1807 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1808 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1809 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1810 SelectionDAGISel &SDISel) {
1811 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1814 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1815 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1816 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1817 SelectionDAGISel &SDISel, SDNode *N) {
1818 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1821 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1822 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1824 uint16_t Opc = MatcherTable[MatcherIndex++];
1825 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1826 return N->getOpcode() == Opc;
1829 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1830 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1831 SDValue N, const TargetLowering &TLI) {
1832 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1833 if (N.getValueType() == VT) return true;
1835 // Handle the case when VT is iPTR.
1836 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1839 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1840 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1841 SDValue N, const TargetLowering &TLI,
1843 if (ChildNo >= N.getNumOperands())
1844 return false; // Match fails if out of range child #.
1845 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1849 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1850 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1852 return cast<CondCodeSDNode>(N)->get() ==
1853 (ISD::CondCode)MatcherTable[MatcherIndex++];
1856 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1857 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1858 SDValue N, const TargetLowering &TLI) {
1859 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1860 if (cast<VTSDNode>(N)->getVT() == VT)
1863 // Handle the case when VT is iPTR.
1864 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1867 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1868 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1870 int64_t Val = MatcherTable[MatcherIndex++];
1872 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1874 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1875 return C != 0 && C->getSExtValue() == Val;
1878 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1879 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1880 SDValue N, SelectionDAGISel &SDISel) {
1881 int64_t Val = MatcherTable[MatcherIndex++];
1883 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1885 if (N->getOpcode() != ISD::AND) return false;
1887 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1888 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1891 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1892 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1893 SDValue N, SelectionDAGISel &SDISel) {
1894 int64_t Val = MatcherTable[MatcherIndex++];
1896 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1898 if (N->getOpcode() != ISD::OR) return false;
1900 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1901 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1904 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1905 /// scope, evaluate the current node. If the current predicate is known to
1906 /// fail, set Result=true and return anything. If the current predicate is
1907 /// known to pass, set Result=false and return the MatcherIndex to continue
1908 /// with. If the current predicate is unknown, set Result=false and return the
1909 /// MatcherIndex to continue with.
1910 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1911 unsigned Index, SDValue N,
1912 bool &Result, SelectionDAGISel &SDISel,
1913 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1914 switch (Table[Index++]) {
1917 return Index-1; // Could not evaluate this predicate.
1918 case SelectionDAGISel::OPC_CheckSame:
1919 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1921 case SelectionDAGISel::OPC_CheckPatternPredicate:
1922 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1924 case SelectionDAGISel::OPC_CheckPredicate:
1925 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1927 case SelectionDAGISel::OPC_CheckOpcode:
1928 Result = !::CheckOpcode(Table, Index, N.getNode());
1930 case SelectionDAGISel::OPC_CheckType:
1931 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1933 case SelectionDAGISel::OPC_CheckChild0Type:
1934 case SelectionDAGISel::OPC_CheckChild1Type:
1935 case SelectionDAGISel::OPC_CheckChild2Type:
1936 case SelectionDAGISel::OPC_CheckChild3Type:
1937 case SelectionDAGISel::OPC_CheckChild4Type:
1938 case SelectionDAGISel::OPC_CheckChild5Type:
1939 case SelectionDAGISel::OPC_CheckChild6Type:
1940 case SelectionDAGISel::OPC_CheckChild7Type:
1941 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1942 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1944 case SelectionDAGISel::OPC_CheckCondCode:
1945 Result = !::CheckCondCode(Table, Index, N);
1947 case SelectionDAGISel::OPC_CheckValueType:
1948 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1950 case SelectionDAGISel::OPC_CheckInteger:
1951 Result = !::CheckInteger(Table, Index, N);
1953 case SelectionDAGISel::OPC_CheckAndImm:
1954 Result = !::CheckAndImm(Table, Index, N, SDISel);
1956 case SelectionDAGISel::OPC_CheckOrImm:
1957 Result = !::CheckOrImm(Table, Index, N, SDISel);
1965 /// FailIndex - If this match fails, this is the index to continue with.
1968 /// NodeStack - The node stack when the scope was formed.
1969 SmallVector<SDValue, 4> NodeStack;
1971 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1972 unsigned NumRecordedNodes;
1974 /// NumMatchedMemRefs - The number of matched memref entries.
1975 unsigned NumMatchedMemRefs;
1977 /// InputChain/InputGlue - The current chain/glue
1978 SDValue InputChain, InputGlue;
1980 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1981 bool HasChainNodesMatched, HasGlueResultNodesMatched;
1986 SDNode *SelectionDAGISel::
1987 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1988 unsigned TableSize) {
1989 // FIXME: Should these even be selected? Handle these cases in the caller?
1990 switch (NodeToMatch->getOpcode()) {
1993 case ISD::EntryToken: // These nodes remain the same.
1994 case ISD::BasicBlock:
1996 //case ISD::VALUETYPE:
1997 //case ISD::CONDCODE:
1998 case ISD::HANDLENODE:
1999 case ISD::MDNODE_SDNODE:
2000 case ISD::TargetConstant:
2001 case ISD::TargetConstantFP:
2002 case ISD::TargetConstantPool:
2003 case ISD::TargetFrameIndex:
2004 case ISD::TargetExternalSymbol:
2005 case ISD::TargetBlockAddress:
2006 case ISD::TargetJumpTable:
2007 case ISD::TargetGlobalTLSAddress:
2008 case ISD::TargetGlobalAddress:
2009 case ISD::TokenFactor:
2010 case ISD::CopyFromReg:
2011 case ISD::CopyToReg:
2013 NodeToMatch->setNodeId(-1); // Mark selected.
2015 case ISD::AssertSext:
2016 case ISD::AssertZext:
2017 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2018 NodeToMatch->getOperand(0));
2020 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2021 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2024 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2026 // Set up the node stack with NodeToMatch as the only node on the stack.
2027 SmallVector<SDValue, 8> NodeStack;
2028 SDValue N = SDValue(NodeToMatch, 0);
2029 NodeStack.push_back(N);
2031 // MatchScopes - Scopes used when matching, if a match failure happens, this
2032 // indicates where to continue checking.
2033 SmallVector<MatchScope, 8> MatchScopes;
2035 // RecordedNodes - This is the set of nodes that have been recorded by the
2036 // state machine. The second value is the parent of the node, or null if the
2037 // root is recorded.
2038 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2040 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2042 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2044 // These are the current input chain and glue for use when generating nodes.
2045 // Various Emit operations change these. For example, emitting a copytoreg
2046 // uses and updates these.
2047 SDValue InputChain, InputGlue;
2049 // ChainNodesMatched - If a pattern matches nodes that have input/output
2050 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2051 // which ones they are. The result is captured into this list so that we can
2052 // update the chain results when the pattern is complete.
2053 SmallVector<SDNode*, 3> ChainNodesMatched;
2054 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2056 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2057 NodeToMatch->dump(CurDAG);
2060 // Determine where to start the interpreter. Normally we start at opcode #0,
2061 // but if the state machine starts with an OPC_SwitchOpcode, then we
2062 // accelerate the first lookup (which is guaranteed to be hot) with the
2063 // OpcodeOffset table.
2064 unsigned MatcherIndex = 0;
2066 if (!OpcodeOffset.empty()) {
2067 // Already computed the OpcodeOffset table, just index into it.
2068 if (N.getOpcode() < OpcodeOffset.size())
2069 MatcherIndex = OpcodeOffset[N.getOpcode()];
2070 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2072 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2073 // Otherwise, the table isn't computed, but the state machine does start
2074 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2075 // is the first time we're selecting an instruction.
2078 // Get the size of this case.
2079 unsigned CaseSize = MatcherTable[Idx++];
2081 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2082 if (CaseSize == 0) break;
2084 // Get the opcode, add the index to the table.
2085 uint16_t Opc = MatcherTable[Idx++];
2086 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2087 if (Opc >= OpcodeOffset.size())
2088 OpcodeOffset.resize((Opc+1)*2);
2089 OpcodeOffset[Opc] = Idx;
2093 // Okay, do the lookup for the first opcode.
2094 if (N.getOpcode() < OpcodeOffset.size())
2095 MatcherIndex = OpcodeOffset[N.getOpcode()];
2099 assert(MatcherIndex < TableSize && "Invalid index");
2101 unsigned CurrentOpcodeIndex = MatcherIndex;
2103 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2106 // Okay, the semantics of this operation are that we should push a scope
2107 // then evaluate the first child. However, pushing a scope only to have
2108 // the first check fail (which then pops it) is inefficient. If we can
2109 // determine immediately that the first check (or first several) will
2110 // immediately fail, don't even bother pushing a scope for them.
2114 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2115 if (NumToSkip & 128)
2116 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2117 // Found the end of the scope with no match.
2118 if (NumToSkip == 0) {
2123 FailIndex = MatcherIndex+NumToSkip;
2125 unsigned MatcherIndexOfPredicate = MatcherIndex;
2126 (void)MatcherIndexOfPredicate; // silence warning.
2128 // If we can't evaluate this predicate without pushing a scope (e.g. if
2129 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2130 // push the scope and evaluate the full predicate chain.
2132 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2133 Result, *this, RecordedNodes);
2137 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2138 << "index " << MatcherIndexOfPredicate
2139 << ", continuing at " << FailIndex << "\n");
2140 ++NumDAGIselRetries;
2142 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2143 // move to the next case.
2144 MatcherIndex = FailIndex;
2147 // If the whole scope failed to match, bail.
2148 if (FailIndex == 0) break;
2150 // Push a MatchScope which indicates where to go if the first child fails
2152 MatchScope NewEntry;
2153 NewEntry.FailIndex = FailIndex;
2154 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2155 NewEntry.NumRecordedNodes = RecordedNodes.size();
2156 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2157 NewEntry.InputChain = InputChain;
2158 NewEntry.InputGlue = InputGlue;
2159 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2160 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2161 MatchScopes.push_back(NewEntry);
2164 case OPC_RecordNode: {
2165 // Remember this node, it may end up being an operand in the pattern.
2167 if (NodeStack.size() > 1)
2168 Parent = NodeStack[NodeStack.size()-2].getNode();
2169 RecordedNodes.push_back(std::make_pair(N, Parent));
2173 case OPC_RecordChild0: case OPC_RecordChild1:
2174 case OPC_RecordChild2: case OPC_RecordChild3:
2175 case OPC_RecordChild4: case OPC_RecordChild5:
2176 case OPC_RecordChild6: case OPC_RecordChild7: {
2177 unsigned ChildNo = Opcode-OPC_RecordChild0;
2178 if (ChildNo >= N.getNumOperands())
2179 break; // Match fails if out of range child #.
2181 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2185 case OPC_RecordMemRef:
2186 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2189 case OPC_CaptureGlueInput:
2190 // If the current node has an input glue, capture it in InputGlue.
2191 if (N->getNumOperands() != 0 &&
2192 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2193 InputGlue = N->getOperand(N->getNumOperands()-1);
2196 case OPC_MoveChild: {
2197 unsigned ChildNo = MatcherTable[MatcherIndex++];
2198 if (ChildNo >= N.getNumOperands())
2199 break; // Match fails if out of range child #.
2200 N = N.getOperand(ChildNo);
2201 NodeStack.push_back(N);
2205 case OPC_MoveParent:
2206 // Pop the current node off the NodeStack.
2207 NodeStack.pop_back();
2208 assert(!NodeStack.empty() && "Node stack imbalance!");
2209 N = NodeStack.back();
2213 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2215 case OPC_CheckPatternPredicate:
2216 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2218 case OPC_CheckPredicate:
2219 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2223 case OPC_CheckComplexPat: {
2224 unsigned CPNum = MatcherTable[MatcherIndex++];
2225 unsigned RecNo = MatcherTable[MatcherIndex++];
2226 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2227 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2228 RecordedNodes[RecNo].first, CPNum,
2233 case OPC_CheckOpcode:
2234 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2238 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2241 case OPC_SwitchOpcode: {
2242 unsigned CurNodeOpcode = N.getOpcode();
2243 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2246 // Get the size of this case.
2247 CaseSize = MatcherTable[MatcherIndex++];
2249 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2250 if (CaseSize == 0) break;
2252 uint16_t Opc = MatcherTable[MatcherIndex++];
2253 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2255 // If the opcode matches, then we will execute this case.
2256 if (CurNodeOpcode == Opc)
2259 // Otherwise, skip over this case.
2260 MatcherIndex += CaseSize;
2263 // If no cases matched, bail out.
2264 if (CaseSize == 0) break;
2266 // Otherwise, execute the case we found.
2267 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2268 << " to " << MatcherIndex << "\n");
2272 case OPC_SwitchType: {
2273 MVT CurNodeVT = N.getValueType().getSimpleVT();
2274 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2277 // Get the size of this case.
2278 CaseSize = MatcherTable[MatcherIndex++];
2280 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2281 if (CaseSize == 0) break;
2283 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2284 if (CaseVT == MVT::iPTR)
2285 CaseVT = TLI.getPointerTy();
2287 // If the VT matches, then we will execute this case.
2288 if (CurNodeVT == CaseVT)
2291 // Otherwise, skip over this case.
2292 MatcherIndex += CaseSize;
2295 // If no cases matched, bail out.
2296 if (CaseSize == 0) break;
2298 // Otherwise, execute the case we found.
2299 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2300 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2303 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2304 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2305 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2306 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2307 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2308 Opcode-OPC_CheckChild0Type))
2311 case OPC_CheckCondCode:
2312 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2314 case OPC_CheckValueType:
2315 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2317 case OPC_CheckInteger:
2318 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2320 case OPC_CheckAndImm:
2321 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2323 case OPC_CheckOrImm:
2324 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2327 case OPC_CheckFoldableChainNode: {
2328 assert(NodeStack.size() != 1 && "No parent node");
2329 // Verify that all intermediate nodes between the root and this one have
2331 bool HasMultipleUses = false;
2332 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2333 if (!NodeStack[i].hasOneUse()) {
2334 HasMultipleUses = true;
2337 if (HasMultipleUses) break;
2339 // Check to see that the target thinks this is profitable to fold and that
2340 // we can fold it without inducing cycles in the graph.
2341 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2343 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2344 NodeToMatch, OptLevel,
2345 true/*We validate our own chains*/))
2350 case OPC_EmitInteger: {
2351 MVT::SimpleValueType VT =
2352 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2353 int64_t Val = MatcherTable[MatcherIndex++];
2355 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2356 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2357 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2360 case OPC_EmitRegister: {
2361 MVT::SimpleValueType VT =
2362 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2363 unsigned RegNo = MatcherTable[MatcherIndex++];
2364 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2365 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2368 case OPC_EmitRegister2: {
2369 // For targets w/ more than 256 register names, the register enum
2370 // values are stored in two bytes in the matcher table (just like
2372 MVT::SimpleValueType VT =
2373 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2374 unsigned RegNo = MatcherTable[MatcherIndex++];
2375 RegNo |= MatcherTable[MatcherIndex++] << 8;
2376 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2377 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2381 case OPC_EmitConvertToTarget: {
2382 // Convert from IMM/FPIMM to target version.
2383 unsigned RecNo = MatcherTable[MatcherIndex++];
2384 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2385 SDValue Imm = RecordedNodes[RecNo].first;
2387 if (Imm->getOpcode() == ISD::Constant) {
2388 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2389 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2390 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2391 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2392 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2395 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2399 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2400 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2401 // These are space-optimized forms of OPC_EmitMergeInputChains.
2402 assert(InputChain.getNode() == 0 &&
2403 "EmitMergeInputChains should be the first chain producing node");
2404 assert(ChainNodesMatched.empty() &&
2405 "Should only have one EmitMergeInputChains per match");
2407 // Read all of the chained nodes.
2408 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2409 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2410 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2412 // FIXME: What if other value results of the node have uses not matched
2414 if (ChainNodesMatched.back() != NodeToMatch &&
2415 !RecordedNodes[RecNo].first.hasOneUse()) {
2416 ChainNodesMatched.clear();
2420 // Merge the input chains if they are not intra-pattern references.
2421 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2423 if (InputChain.getNode() == 0)
2424 break; // Failed to merge.
2428 case OPC_EmitMergeInputChains: {
2429 assert(InputChain.getNode() == 0 &&
2430 "EmitMergeInputChains should be the first chain producing node");
2431 // This node gets a list of nodes we matched in the input that have
2432 // chains. We want to token factor all of the input chains to these nodes
2433 // together. However, if any of the input chains is actually one of the
2434 // nodes matched in this pattern, then we have an intra-match reference.
2435 // Ignore these because the newly token factored chain should not refer to
2437 unsigned NumChains = MatcherTable[MatcherIndex++];
2438 assert(NumChains != 0 && "Can't TF zero chains");
2440 assert(ChainNodesMatched.empty() &&
2441 "Should only have one EmitMergeInputChains per match");
2443 // Read all of the chained nodes.
2444 for (unsigned i = 0; i != NumChains; ++i) {
2445 unsigned RecNo = MatcherTable[MatcherIndex++];
2446 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2447 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2449 // FIXME: What if other value results of the node have uses not matched
2451 if (ChainNodesMatched.back() != NodeToMatch &&
2452 !RecordedNodes[RecNo].first.hasOneUse()) {
2453 ChainNodesMatched.clear();
2458 // If the inner loop broke out, the match fails.
2459 if (ChainNodesMatched.empty())
2462 // Merge the input chains if they are not intra-pattern references.
2463 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2465 if (InputChain.getNode() == 0)
2466 break; // Failed to merge.
2471 case OPC_EmitCopyToReg: {
2472 unsigned RecNo = MatcherTable[MatcherIndex++];
2473 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2474 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2476 if (InputChain.getNode() == 0)
2477 InputChain = CurDAG->getEntryNode();
2479 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2480 DestPhysReg, RecordedNodes[RecNo].first,
2483 InputGlue = InputChain.getValue(1);
2487 case OPC_EmitNodeXForm: {
2488 unsigned XFormNo = MatcherTable[MatcherIndex++];
2489 unsigned RecNo = MatcherTable[MatcherIndex++];
2490 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2491 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2492 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2497 case OPC_MorphNodeTo: {
2498 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2499 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2500 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2501 // Get the result VT list.
2502 unsigned NumVTs = MatcherTable[MatcherIndex++];
2503 SmallVector<EVT, 4> VTs;
2504 for (unsigned i = 0; i != NumVTs; ++i) {
2505 MVT::SimpleValueType VT =
2506 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2507 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2511 if (EmitNodeInfo & OPFL_Chain)
2512 VTs.push_back(MVT::Other);
2513 if (EmitNodeInfo & OPFL_GlueOutput)
2514 VTs.push_back(MVT::Glue);
2516 // This is hot code, so optimize the two most common cases of 1 and 2
2519 if (VTs.size() == 1)
2520 VTList = CurDAG->getVTList(VTs[0]);
2521 else if (VTs.size() == 2)
2522 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2524 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2526 // Get the operand list.
2527 unsigned NumOps = MatcherTable[MatcherIndex++];
2528 SmallVector<SDValue, 8> Ops;
2529 for (unsigned i = 0; i != NumOps; ++i) {
2530 unsigned RecNo = MatcherTable[MatcherIndex++];
2532 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2534 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2535 Ops.push_back(RecordedNodes[RecNo].first);
2538 // If there are variadic operands to add, handle them now.
2539 if (EmitNodeInfo & OPFL_VariadicInfo) {
2540 // Determine the start index to copy from.
2541 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2542 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2543 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2544 "Invalid variadic node");
2545 // Copy all of the variadic operands, not including a potential glue
2547 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2549 SDValue V = NodeToMatch->getOperand(i);
2550 if (V.getValueType() == MVT::Glue) break;
2555 // If this has chain/glue inputs, add them.
2556 if (EmitNodeInfo & OPFL_Chain)
2557 Ops.push_back(InputChain);
2558 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2559 Ops.push_back(InputGlue);
2563 if (Opcode != OPC_MorphNodeTo) {
2564 // If this is a normal EmitNode command, just create the new node and
2565 // add the results to the RecordedNodes list.
2566 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2567 VTList, Ops.data(), Ops.size());
2569 // Add all the non-glue/non-chain results to the RecordedNodes list.
2570 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2571 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2572 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2577 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2581 // If the node had chain/glue results, update our notion of the current
2583 if (EmitNodeInfo & OPFL_GlueOutput) {
2584 InputGlue = SDValue(Res, VTs.size()-1);
2585 if (EmitNodeInfo & OPFL_Chain)
2586 InputChain = SDValue(Res, VTs.size()-2);
2587 } else if (EmitNodeInfo & OPFL_Chain)
2588 InputChain = SDValue(Res, VTs.size()-1);
2590 // If the OPFL_MemRefs glue is set on this node, slap all of the
2591 // accumulated memrefs onto it.
2593 // FIXME: This is vastly incorrect for patterns with multiple outputs
2594 // instructions that access memory and for ComplexPatterns that match
2596 if (EmitNodeInfo & OPFL_MemRefs) {
2597 // Only attach load or store memory operands if the generated
2598 // instruction may load or store.
2599 const TargetInstrDesc &TID = TM.getInstrInfo()->get(TargetOpc);
2600 bool mayLoad = TID.mayLoad();
2601 bool mayStore = TID.mayStore();
2603 unsigned NumMemRefs = 0;
2604 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2605 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2606 if ((*I)->isLoad()) {
2609 } else if ((*I)->isStore()) {
2617 MachineSDNode::mmo_iterator MemRefs =
2618 MF->allocateMemRefsArray(NumMemRefs);
2620 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2621 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2622 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2623 if ((*I)->isLoad()) {
2626 } else if ((*I)->isStore()) {
2634 cast<MachineSDNode>(Res)
2635 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2639 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2640 << " node: "; Res->dump(CurDAG); errs() << "\n");
2642 // If this was a MorphNodeTo then we're completely done!
2643 if (Opcode == OPC_MorphNodeTo) {
2644 // Update chain and glue uses.
2645 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2646 InputGlue, GlueResultNodesMatched, true);
2653 case OPC_MarkGlueResults: {
2654 unsigned NumNodes = MatcherTable[MatcherIndex++];
2656 // Read and remember all the glue-result nodes.
2657 for (unsigned i = 0; i != NumNodes; ++i) {
2658 unsigned RecNo = MatcherTable[MatcherIndex++];
2660 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2662 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2663 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2668 case OPC_CompleteMatch: {
2669 // The match has been completed, and any new nodes (if any) have been
2670 // created. Patch up references to the matched dag to use the newly
2672 unsigned NumResults = MatcherTable[MatcherIndex++];
2674 for (unsigned i = 0; i != NumResults; ++i) {
2675 unsigned ResSlot = MatcherTable[MatcherIndex++];
2677 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2679 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2680 SDValue Res = RecordedNodes[ResSlot].first;
2682 assert(i < NodeToMatch->getNumValues() &&
2683 NodeToMatch->getValueType(i) != MVT::Other &&
2684 NodeToMatch->getValueType(i) != MVT::Glue &&
2685 "Invalid number of results to complete!");
2686 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2687 NodeToMatch->getValueType(i) == MVT::iPTR ||
2688 Res.getValueType() == MVT::iPTR ||
2689 NodeToMatch->getValueType(i).getSizeInBits() ==
2690 Res.getValueType().getSizeInBits()) &&
2691 "invalid replacement");
2692 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2695 // If the root node defines glue, add it to the glue nodes to update list.
2696 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2697 GlueResultNodesMatched.push_back(NodeToMatch);
2699 // Update chain and glue uses.
2700 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2701 InputGlue, GlueResultNodesMatched, false);
2703 assert(NodeToMatch->use_empty() &&
2704 "Didn't replace all uses of the node?");
2706 // FIXME: We just return here, which interacts correctly with SelectRoot
2707 // above. We should fix this to not return an SDNode* anymore.
2712 // If the code reached this point, then the match failed. See if there is
2713 // another child to try in the current 'Scope', otherwise pop it until we
2714 // find a case to check.
2715 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2716 ++NumDAGIselRetries;
2718 if (MatchScopes.empty()) {
2719 CannotYetSelect(NodeToMatch);
2723 // Restore the interpreter state back to the point where the scope was
2725 MatchScope &LastScope = MatchScopes.back();
2726 RecordedNodes.resize(LastScope.NumRecordedNodes);
2728 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2729 N = NodeStack.back();
2731 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2732 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2733 MatcherIndex = LastScope.FailIndex;
2735 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2737 InputChain = LastScope.InputChain;
2738 InputGlue = LastScope.InputGlue;
2739 if (!LastScope.HasChainNodesMatched)
2740 ChainNodesMatched.clear();
2741 if (!LastScope.HasGlueResultNodesMatched)
2742 GlueResultNodesMatched.clear();
2744 // Check to see what the offset is at the new MatcherIndex. If it is zero
2745 // we have reached the end of this scope, otherwise we have another child
2746 // in the current scope to try.
2747 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2748 if (NumToSkip & 128)
2749 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2751 // If we have another child in this scope to match, update FailIndex and
2753 if (NumToSkip != 0) {
2754 LastScope.FailIndex = MatcherIndex+NumToSkip;
2758 // End of this scope, pop it and try the next child in the containing
2760 MatchScopes.pop_back();
2767 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2769 raw_string_ostream Msg(msg);
2770 Msg << "Cannot select: ";
2772 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2773 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2774 N->getOpcode() != ISD::INTRINSIC_VOID) {
2775 N->printrFull(Msg, CurDAG);
2777 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2779 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2780 if (iid < Intrinsic::num_intrinsics)
2781 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2782 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2783 Msg << "target intrinsic %" << TII->getName(iid);
2785 Msg << "unknown intrinsic #" << iid;
2787 report_fatal_error(Msg.str());
2790 char SelectionDAGISel::ID = 0;