1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/CFG.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLibraryInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
61 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
62 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
63 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
64 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
66 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
67 STATISTIC(NumFastIselFailLowerArguments,
68 "Number of entry blocks where fast isel failed to lower arguments");
72 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
73 cl::desc("Enable extra verbose messages in the \"fast\" "
74 "instruction selector"));
77 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
78 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
79 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
80 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
81 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
82 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
83 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
85 // Standard binary operators...
86 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
87 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
88 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
89 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
90 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
91 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
92 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
93 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
94 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
95 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
96 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
97 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
99 // Logical operators...
100 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
101 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
102 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
104 // Memory instructions...
105 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
106 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
107 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
108 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
109 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
110 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
111 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
113 // Convert instructions...
114 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
115 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
116 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
117 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
118 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
119 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
120 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
121 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
122 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
123 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
124 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
125 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
127 // Other instructions...
128 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
129 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
130 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
131 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
132 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
133 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
134 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
135 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
136 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
137 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
138 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
139 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
140 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
141 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
142 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
146 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
147 cl::desc("Enable verbose messages in the \"fast\" "
148 "instruction selector"));
150 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
151 cl::desc("Enable abort calls when \"fast\" instruction selection "
152 "fails to lower an instruction"));
154 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
155 cl::desc("Enable abort calls when \"fast\" instruction selection "
156 "fails to lower a formal argument"));
160 cl::desc("use Machine Branch Probability Info"),
161 cl::init(true), cl::Hidden);
165 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
166 cl::desc("Pop up a window to show dags before the first "
167 "dag combine pass"));
169 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
170 cl::desc("Pop up a window to show dags before legalize types"));
172 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
173 cl::desc("Pop up a window to show dags before legalize"));
175 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
176 cl::desc("Pop up a window to show dags before the second "
177 "dag combine pass"));
179 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
180 cl::desc("Pop up a window to show dags before the post legalize types"
181 " dag combine pass"));
183 ViewISelDAGs("view-isel-dags", cl::Hidden,
184 cl::desc("Pop up a window to show isel dags as they are selected"));
186 ViewSchedDAGs("view-sched-dags", cl::Hidden,
187 cl::desc("Pop up a window to show sched dags as they are processed"));
189 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
190 cl::desc("Pop up a window to show SUnit dags after they are processed"));
192 static const bool ViewDAGCombine1 = false,
193 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
194 ViewDAGCombine2 = false,
195 ViewDAGCombineLT = false,
196 ViewISelDAGs = false, ViewSchedDAGs = false,
197 ViewSUnitDAGs = false;
200 //===---------------------------------------------------------------------===//
202 /// RegisterScheduler class - Track the registration of instruction schedulers.
204 //===---------------------------------------------------------------------===//
205 MachinePassRegistry RegisterScheduler::Registry;
207 //===---------------------------------------------------------------------===//
209 /// ISHeuristic command line option for instruction schedulers.
211 //===---------------------------------------------------------------------===//
212 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
213 RegisterPassParser<RegisterScheduler> >
214 ISHeuristic("pre-RA-sched",
215 cl::init(&createDefaultScheduler), cl::Hidden,
216 cl::desc("Instruction schedulers available (before register"
219 static RegisterScheduler
220 defaultListDAGScheduler("default", "Best scheduler for the target",
221 createDefaultScheduler);
224 //===--------------------------------------------------------------------===//
225 /// \brief This class is used by SelectionDAGISel to temporarily override
226 /// the optimization level on a per-function basis.
227 class OptLevelChanger {
228 SelectionDAGISel &IS;
229 CodeGenOpt::Level SavedOptLevel;
233 OptLevelChanger(SelectionDAGISel &ISel,
234 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
235 SavedOptLevel = IS.OptLevel;
236 if (NewOptLevel == SavedOptLevel)
238 IS.OptLevel = NewOptLevel;
239 IS.TM.setOptLevel(NewOptLevel);
240 SavedFastISel = IS.TM.Options.EnableFastISel;
241 if (NewOptLevel == CodeGenOpt::None)
242 IS.TM.setFastISel(true);
243 DEBUG(dbgs() << "\nChanging optimization level for Function "
244 << IS.MF->getFunction()->getName() << "\n");
245 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
246 << " ; After: -O" << NewOptLevel << "\n");
250 if (IS.OptLevel == SavedOptLevel)
252 DEBUG(dbgs() << "\nRestoring optimization level for Function "
253 << IS.MF->getFunction()->getName() << "\n");
254 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
255 << " ; After: -O" << SavedOptLevel << "\n");
256 IS.OptLevel = SavedOptLevel;
257 IS.TM.setOptLevel(SavedOptLevel);
258 IS.TM.setFastISel(SavedFastISel);
262 //===--------------------------------------------------------------------===//
263 /// createDefaultScheduler - This creates an instruction scheduler appropriate
265 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
266 CodeGenOpt::Level OptLevel) {
267 const TargetLowering *TLI = IS->getTargetLowering();
268 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
270 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
271 TLI->getSchedulingPreference() == Sched::Source)
272 return createSourceListDAGScheduler(IS, OptLevel);
273 if (TLI->getSchedulingPreference() == Sched::RegPressure)
274 return createBURRListDAGScheduler(IS, OptLevel);
275 if (TLI->getSchedulingPreference() == Sched::Hybrid)
276 return createHybridListDAGScheduler(IS, OptLevel);
277 if (TLI->getSchedulingPreference() == Sched::VLIW)
278 return createVLIWDAGScheduler(IS, OptLevel);
279 assert(TLI->getSchedulingPreference() == Sched::ILP &&
280 "Unknown sched type!");
281 return createILPListDAGScheduler(IS, OptLevel);
285 // EmitInstrWithCustomInserter - This method should be implemented by targets
286 // that mark instructions with the 'usesCustomInserter' flag. These
287 // instructions are special in various ways, which require special support to
288 // insert. The specified MachineInstr is created but not inserted into any
289 // basic blocks, and this method is called to expand it into a sequence of
290 // instructions, potentially also creating new basic blocks and control flow.
291 // When new basic blocks are inserted and the edges from MBB to its successors
292 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
295 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
296 MachineBasicBlock *MBB) const {
298 dbgs() << "If a target marks an instruction with "
299 "'usesCustomInserter', it must implement "
300 "TargetLowering::EmitInstrWithCustomInserter!";
305 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
306 SDNode *Node) const {
307 assert(!MI->hasPostISelHook() &&
308 "If a target marks an instruction with 'hasPostISelHook', "
309 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
312 //===----------------------------------------------------------------------===//
313 // SelectionDAGISel code
314 //===----------------------------------------------------------------------===//
316 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
317 CodeGenOpt::Level OL) :
318 MachineFunctionPass(ID), TM(tm),
319 FuncInfo(new FunctionLoweringInfo(TM)),
320 CurDAG(new SelectionDAG(tm, OL)),
321 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
325 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
326 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
327 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
328 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
331 SelectionDAGISel::~SelectionDAGISel() {
337 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
338 AU.addRequired<AliasAnalysis>();
339 AU.addPreserved<AliasAnalysis>();
340 AU.addRequired<GCModuleInfo>();
341 AU.addPreserved<GCModuleInfo>();
342 AU.addRequired<TargetLibraryInfo>();
343 if (UseMBPI && OptLevel != CodeGenOpt::None)
344 AU.addRequired<BranchProbabilityInfo>();
345 MachineFunctionPass::getAnalysisUsage(AU);
348 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
349 /// may trap on it. In this case we have to split the edge so that the path
350 /// through the predecessor block that doesn't go to the phi block doesn't
351 /// execute the possibly trapping instruction.
353 /// This is required for correctness, so it must be done at -O0.
355 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
356 // Loop for blocks with phi nodes.
357 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
358 PHINode *PN = dyn_cast<PHINode>(BB->begin());
359 if (PN == 0) continue;
362 // For each block with a PHI node, check to see if any of the input values
363 // are potentially trapping constant expressions. Constant expressions are
364 // the only potentially trapping value that can occur as the argument to a
366 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
367 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
368 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
369 if (CE == 0 || !CE->canTrap()) continue;
371 // The only case we have to worry about is when the edge is critical.
372 // Since this block has a PHI Node, we assume it has multiple input
373 // edges: check to see if the pred has multiple successors.
374 BasicBlock *Pred = PN->getIncomingBlock(i);
375 if (Pred->getTerminator()->getNumSuccessors() == 1)
378 // Okay, we have to split this edge.
379 SplitCriticalEdge(Pred->getTerminator(),
380 GetSuccessorNumber(Pred, BB), SDISel, true);
386 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
387 // Do some sanity-checking on the command-line options.
388 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
389 "-fast-isel-verbose requires -fast-isel");
390 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
391 "-fast-isel-abort requires -fast-isel");
393 const Function &Fn = *mf.getFunction();
394 const TargetInstrInfo &TII = *TM.getInstrInfo();
395 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
396 const TargetLowering *TLI = TM.getTargetLowering();
399 RegInfo = &MF->getRegInfo();
400 AA = &getAnalysis<AliasAnalysis>();
401 LibInfo = &getAnalysis<TargetLibraryInfo>();
402 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
404 TargetSubtargetInfo &ST =
405 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
406 ST.resetSubtargetFeatures(MF);
407 TM.resetTargetOptions(MF);
409 // Reset OptLevel to None for optnone functions.
410 CodeGenOpt::Level NewOptLevel = OptLevel;
411 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
412 NewOptLevel = CodeGenOpt::None;
413 OptLevelChanger OLC(*this, NewOptLevel);
415 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
417 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
419 CurDAG->init(*MF, TLI);
420 FuncInfo->set(Fn, *MF, CurDAG);
422 if (UseMBPI && OptLevel != CodeGenOpt::None)
423 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
427 SDB->init(GFI, *AA, LibInfo);
429 MF->setHasInlineAsm(false);
431 SelectAllBasicBlocks(Fn);
433 // If the first basic block in the function has live ins that need to be
434 // copied into vregs, emit the copies into the top of the block before
435 // emitting the code for the block.
436 MachineBasicBlock *EntryMBB = MF->begin();
437 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
439 DenseMap<unsigned, unsigned> LiveInMap;
440 if (!FuncInfo->ArgDbgValues.empty())
441 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
442 E = RegInfo->livein_end(); LI != E; ++LI)
444 LiveInMap.insert(std::make_pair(LI->first, LI->second));
446 // Insert DBG_VALUE instructions for function arguments to the entry block.
447 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
448 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
449 bool hasFI = MI->getOperand(0).isFI();
451 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
452 if (TargetRegisterInfo::isPhysicalRegister(Reg))
453 EntryMBB->insert(EntryMBB->begin(), MI);
455 MachineInstr *Def = RegInfo->getVRegDef(Reg);
457 MachineBasicBlock::iterator InsertPos = Def;
458 // FIXME: VR def may not be in entry block.
459 Def->getParent()->insert(std::next(InsertPos), MI);
461 DEBUG(dbgs() << "Dropping debug info for dead vreg"
462 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
465 // If Reg is live-in then update debug info to track its copy in a vreg.
466 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
467 if (LDI != LiveInMap.end()) {
468 assert(!hasFI && "There's no handling of frame pointer updating here yet "
470 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
471 MachineBasicBlock::iterator InsertPos = Def;
472 const MDNode *Variable =
473 MI->getOperand(MI->getNumOperands()-1).getMetadata();
474 bool IsIndirect = MI->isIndirectDebugValue();
475 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
476 // Def is never a terminator here, so it is ok to increment InsertPos.
477 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
478 TII.get(TargetOpcode::DBG_VALUE),
480 LDI->second, Offset, Variable);
482 // If this vreg is directly copied into an exported register then
483 // that COPY instructions also need DBG_VALUE, if it is the only
484 // user of LDI->second.
485 MachineInstr *CopyUseMI = NULL;
486 for (MachineRegisterInfo::use_iterator
487 UI = RegInfo->use_begin(LDI->second);
488 MachineInstr *UseMI = UI.skipInstruction();) {
489 if (UseMI->isDebugValue()) continue;
490 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
491 CopyUseMI = UseMI; continue;
493 // Otherwise this is another use or second copy use.
494 CopyUseMI = NULL; break;
497 MachineInstr *NewMI =
498 BuildMI(*MF, CopyUseMI->getDebugLoc(),
499 TII.get(TargetOpcode::DBG_VALUE),
501 CopyUseMI->getOperand(0).getReg(),
503 MachineBasicBlock::iterator Pos = CopyUseMI;
504 EntryMBB->insertAfter(Pos, NewMI);
509 // Determine if there are any calls in this machine function.
510 MachineFrameInfo *MFI = MF->getFrameInfo();
511 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
514 if (MFI->hasCalls() && MF->hasInlineAsm())
517 const MachineBasicBlock *MBB = I;
518 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
520 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
521 if ((MCID.isCall() && !MCID.isReturn()) ||
522 II->isStackAligningInlineAsm()) {
523 MFI->setHasCalls(true);
525 if (II->isInlineAsm()) {
526 MF->setHasInlineAsm(true);
531 // Determine if there is a call to setjmp in the machine function.
532 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
534 // Replace forward-declared registers with the registers containing
535 // the desired value.
536 MachineRegisterInfo &MRI = MF->getRegInfo();
537 for (DenseMap<unsigned, unsigned>::iterator
538 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
540 unsigned From = I->first;
541 unsigned To = I->second;
542 // If To is also scheduled to be replaced, find what its ultimate
545 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
549 // Make sure the new register has a sufficiently constrained register class.
550 if (TargetRegisterInfo::isVirtualRegister(From) &&
551 TargetRegisterInfo::isVirtualRegister(To))
552 MRI.constrainRegClass(To, MRI.getRegClass(From));
554 MRI.replaceRegWith(From, To);
557 // Freeze the set of reserved registers now that MachineFrameInfo has been
558 // set up. All the information required by getReservedRegs() should be
560 MRI.freezeReservedRegs(*MF);
562 // Release function-specific state. SDB and CurDAG are already cleared
566 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
567 DEBUG(MF->print(dbgs()));
572 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
573 BasicBlock::const_iterator End,
575 // Lower all of the non-terminator instructions. If a call is emitted
576 // as a tail call, cease emitting nodes for this block. Terminators
577 // are handled below.
578 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
581 // Make sure the root of the DAG is up-to-date.
582 CurDAG->setRoot(SDB->getControlRoot());
583 HadTailCall = SDB->HasTailCall;
586 // Final step, emit the lowered DAG as machine code.
590 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
591 SmallPtrSet<SDNode*, 128> VisitedNodes;
592 SmallVector<SDNode*, 128> Worklist;
594 Worklist.push_back(CurDAG->getRoot().getNode());
600 SDNode *N = Worklist.pop_back_val();
602 // If we've already seen this node, ignore it.
603 if (!VisitedNodes.insert(N))
606 // Otherwise, add all chain operands to the worklist.
607 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
608 if (N->getOperand(i).getValueType() == MVT::Other)
609 Worklist.push_back(N->getOperand(i).getNode());
611 // If this is a CopyToReg with a vreg dest, process it.
612 if (N->getOpcode() != ISD::CopyToReg)
615 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
616 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
619 // Ignore non-scalar or non-integer values.
620 SDValue Src = N->getOperand(2);
621 EVT SrcVT = Src.getValueType();
622 if (!SrcVT.isInteger() || SrcVT.isVector())
625 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
626 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
627 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
628 } while (!Worklist.empty());
631 void SelectionDAGISel::CodeGenAndEmitDAG() {
632 std::string GroupName;
633 if (TimePassesIsEnabled)
634 GroupName = "Instruction Selection and Scheduling";
635 std::string BlockName;
636 int BlockNumber = -1;
639 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
640 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
644 BlockNumber = FuncInfo->MBB->getNumber();
645 BlockName = MF->getName().str() + ":" +
646 FuncInfo->MBB->getBasicBlock()->getName().str();
648 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
649 << " '" << BlockName << "'\n"; CurDAG->dump());
651 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
653 // Run the DAG combiner in pre-legalize mode.
655 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
656 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
659 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
660 << " '" << BlockName << "'\n"; CurDAG->dump());
662 // Second step, hack on the DAG until it only uses operations and types that
663 // the target supports.
664 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
669 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
670 Changed = CurDAG->LegalizeTypes();
673 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
674 << " '" << BlockName << "'\n"; CurDAG->dump());
676 CurDAG->NewNodesMustHaveLegalTypes = true;
679 if (ViewDAGCombineLT)
680 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
682 // Run the DAG combiner in post-type-legalize mode.
684 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
685 TimePassesIsEnabled);
686 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
689 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
690 << " '" << BlockName << "'\n"; CurDAG->dump());
695 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
696 Changed = CurDAG->LegalizeVectors();
701 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
702 CurDAG->LegalizeTypes();
705 if (ViewDAGCombineLT)
706 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
708 // Run the DAG combiner in post-type-legalize mode.
710 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
711 TimePassesIsEnabled);
712 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
715 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
716 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
719 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
722 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
726 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
727 << " '" << BlockName << "'\n"; CurDAG->dump());
729 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
731 // Run the DAG combiner in post-legalize mode.
733 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
734 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
737 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
738 << " '" << BlockName << "'\n"; CurDAG->dump());
740 if (OptLevel != CodeGenOpt::None)
741 ComputeLiveOutVRegInfo();
743 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
745 // Third, instruction select all of the operations to machine code, adding the
746 // code to the MachineBasicBlock.
748 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
749 DoInstructionSelection();
752 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
753 << " '" << BlockName << "'\n"; CurDAG->dump());
755 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
757 // Schedule machine code.
758 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
760 NamedRegionTimer T("Instruction Scheduling", GroupName,
761 TimePassesIsEnabled);
762 Scheduler->Run(CurDAG, FuncInfo->MBB);
765 if (ViewSUnitDAGs) Scheduler->viewGraph();
767 // Emit machine code to BB. This can change 'BB' to the last block being
769 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
771 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
773 // FuncInfo->InsertPt is passed by reference and set to the end of the
774 // scheduled instructions.
775 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
778 // If the block was split, make sure we update any references that are used to
779 // update PHI nodes later on.
780 if (FirstMBB != LastMBB)
781 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
783 // Free the scheduler state.
785 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
786 TimePassesIsEnabled);
790 // Free the SelectionDAG state, now that we're finished with it.
795 /// ISelUpdater - helper class to handle updates of the instruction selection
797 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
798 SelectionDAG::allnodes_iterator &ISelPosition;
800 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
801 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
803 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
804 /// deleted is the current ISelPosition node, update ISelPosition.
806 virtual void NodeDeleted(SDNode *N, SDNode *E) {
807 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
811 } // end anonymous namespace
813 void SelectionDAGISel::DoInstructionSelection() {
814 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
815 << FuncInfo->MBB->getNumber()
816 << " '" << FuncInfo->MBB->getName() << "'\n");
820 // Select target instructions for the DAG.
822 // Number all nodes with a topological order and set DAGSize.
823 DAGSize = CurDAG->AssignTopologicalOrder();
825 // Create a dummy node (which is not added to allnodes), that adds
826 // a reference to the root node, preventing it from being deleted,
827 // and tracking any changes of the root.
828 HandleSDNode Dummy(CurDAG->getRoot());
829 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
832 // Make sure that ISelPosition gets properly updated when nodes are deleted
833 // in calls made from this function.
834 ISelUpdater ISU(*CurDAG, ISelPosition);
836 // The AllNodes list is now topological-sorted. Visit the
837 // nodes by starting at the end of the list (the root of the
838 // graph) and preceding back toward the beginning (the entry
840 while (ISelPosition != CurDAG->allnodes_begin()) {
841 SDNode *Node = --ISelPosition;
842 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
843 // but there are currently some corner cases that it misses. Also, this
844 // makes it theoretically possible to disable the DAGCombiner.
845 if (Node->use_empty())
848 SDNode *ResNode = Select(Node);
850 // FIXME: This is pretty gross. 'Select' should be changed to not return
851 // anything at all and this code should be nuked with a tactical strike.
853 // If node should not be replaced, continue with the next one.
854 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
858 ReplaceUses(Node, ResNode);
861 // If after the replacement this node is not used any more,
862 // remove this dead node.
863 if (Node->use_empty()) // Don't delete EntryToken, etc.
864 CurDAG->RemoveDeadNode(Node);
867 CurDAG->setRoot(Dummy.getValue());
870 DEBUG(dbgs() << "===== Instruction selection ends:\n");
872 PostprocessISelDAG();
875 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
876 /// do other setup for EH landing-pad blocks.
877 void SelectionDAGISel::PrepareEHLandingPad() {
878 MachineBasicBlock *MBB = FuncInfo->MBB;
880 // Add a label to mark the beginning of the landing pad. Deletion of the
881 // landing pad can thus be detected via the MachineModuleInfo.
882 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
884 // Assign the call site to the landing pad's begin label.
885 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
887 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
888 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
891 // Mark exception register as live in.
892 const TargetLowering *TLI = getTargetLowering();
893 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
894 if (unsigned Reg = TLI->getExceptionPointerRegister())
895 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
897 // Mark exception selector register as live in.
898 if (unsigned Reg = TLI->getExceptionSelectorRegister())
899 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
902 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
903 /// side-effect free and is either dead or folded into a generated instruction.
904 /// Return false if it needs to be emitted.
905 static bool isFoldedOrDeadInstruction(const Instruction *I,
906 FunctionLoweringInfo *FuncInfo) {
907 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
908 !isa<TerminatorInst>(I) && // Terminators aren't folded.
909 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
910 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
911 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
915 // Collect per Instruction statistics for fast-isel misses. Only those
916 // instructions that cause the bail are accounted for. It does not account for
917 // instructions higher in the block. Thus, summing the per instructions stats
918 // will not add up to what is reported by NumFastIselFailures.
919 static void collectFailStats(const Instruction *I) {
920 switch (I->getOpcode()) {
921 default: assert (0 && "<Invalid operator> ");
924 case Instruction::Ret: NumFastIselFailRet++; return;
925 case Instruction::Br: NumFastIselFailBr++; return;
926 case Instruction::Switch: NumFastIselFailSwitch++; return;
927 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
928 case Instruction::Invoke: NumFastIselFailInvoke++; return;
929 case Instruction::Resume: NumFastIselFailResume++; return;
930 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
932 // Standard binary operators...
933 case Instruction::Add: NumFastIselFailAdd++; return;
934 case Instruction::FAdd: NumFastIselFailFAdd++; return;
935 case Instruction::Sub: NumFastIselFailSub++; return;
936 case Instruction::FSub: NumFastIselFailFSub++; return;
937 case Instruction::Mul: NumFastIselFailMul++; return;
938 case Instruction::FMul: NumFastIselFailFMul++; return;
939 case Instruction::UDiv: NumFastIselFailUDiv++; return;
940 case Instruction::SDiv: NumFastIselFailSDiv++; return;
941 case Instruction::FDiv: NumFastIselFailFDiv++; return;
942 case Instruction::URem: NumFastIselFailURem++; return;
943 case Instruction::SRem: NumFastIselFailSRem++; return;
944 case Instruction::FRem: NumFastIselFailFRem++; return;
946 // Logical operators...
947 case Instruction::And: NumFastIselFailAnd++; return;
948 case Instruction::Or: NumFastIselFailOr++; return;
949 case Instruction::Xor: NumFastIselFailXor++; return;
951 // Memory instructions...
952 case Instruction::Alloca: NumFastIselFailAlloca++; return;
953 case Instruction::Load: NumFastIselFailLoad++; return;
954 case Instruction::Store: NumFastIselFailStore++; return;
955 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
956 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
957 case Instruction::Fence: NumFastIselFailFence++; return;
958 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
960 // Convert instructions...
961 case Instruction::Trunc: NumFastIselFailTrunc++; return;
962 case Instruction::ZExt: NumFastIselFailZExt++; return;
963 case Instruction::SExt: NumFastIselFailSExt++; return;
964 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
965 case Instruction::FPExt: NumFastIselFailFPExt++; return;
966 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
967 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
968 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
969 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
970 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
971 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
972 case Instruction::BitCast: NumFastIselFailBitCast++; return;
974 // Other instructions...
975 case Instruction::ICmp: NumFastIselFailICmp++; return;
976 case Instruction::FCmp: NumFastIselFailFCmp++; return;
977 case Instruction::PHI: NumFastIselFailPHI++; return;
978 case Instruction::Select: NumFastIselFailSelect++; return;
979 case Instruction::Call: NumFastIselFailCall++; return;
980 case Instruction::Shl: NumFastIselFailShl++; return;
981 case Instruction::LShr: NumFastIselFailLShr++; return;
982 case Instruction::AShr: NumFastIselFailAShr++; return;
983 case Instruction::VAArg: NumFastIselFailVAArg++; return;
984 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
985 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
986 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
987 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
988 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
989 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
994 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
995 // Initialize the Fast-ISel state, if needed.
996 FastISel *FastIS = 0;
997 if (TM.Options.EnableFastISel)
998 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo);
1000 // Iterate over all basic blocks in the function.
1001 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1002 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1003 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1004 const BasicBlock *LLVMBB = *I;
1006 if (OptLevel != CodeGenOpt::None) {
1007 bool AllPredsVisited = true;
1008 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1010 if (!FuncInfo->VisitedBBs.count(*PI)) {
1011 AllPredsVisited = false;
1016 if (AllPredsVisited) {
1017 for (BasicBlock::const_iterator I = LLVMBB->begin();
1018 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1019 FuncInfo->ComputePHILiveOutRegInfo(PN);
1021 for (BasicBlock::const_iterator I = LLVMBB->begin();
1022 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1023 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1026 FuncInfo->VisitedBBs.insert(LLVMBB);
1029 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1030 BasicBlock::const_iterator const End = LLVMBB->end();
1031 BasicBlock::const_iterator BI = End;
1033 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1034 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1036 // Setup an EH landing-pad block.
1037 FuncInfo->ExceptionPointerVirtReg = 0;
1038 FuncInfo->ExceptionSelectorVirtReg = 0;
1039 if (FuncInfo->MBB->isLandingPad())
1040 PrepareEHLandingPad();
1042 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1044 FastIS->startNewBlock();
1046 // Emit code for any incoming arguments. This must happen before
1047 // beginning FastISel on the entry block.
1048 if (LLVMBB == &Fn.getEntryBlock()) {
1051 // Lower any arguments needed in this block if this is the entry block.
1052 if (!FastIS->LowerArguments()) {
1053 // Fast isel failed to lower these arguments
1054 ++NumFastIselFailLowerArguments;
1055 if (EnableFastISelAbortArgs)
1056 llvm_unreachable("FastISel didn't lower all arguments");
1058 // Use SelectionDAG argument lowering
1060 CurDAG->setRoot(SDB->getControlRoot());
1062 CodeGenAndEmitDAG();
1065 // If we inserted any instructions at the beginning, make a note of
1066 // where they are, so we can be sure to emit subsequent instructions
1068 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1069 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1071 FastIS->setLastLocalValue(0);
1074 unsigned NumFastIselRemaining = std::distance(Begin, End);
1075 // Do FastISel on as many instructions as possible.
1076 for (; BI != Begin; --BI) {
1077 const Instruction *Inst = std::prev(BI);
1079 // If we no longer require this instruction, skip it.
1080 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1081 --NumFastIselRemaining;
1085 // Bottom-up: reset the insert pos at the top, after any local-value
1087 FastIS->recomputeInsertPt();
1089 // Try to select the instruction with FastISel.
1090 if (FastIS->SelectInstruction(Inst)) {
1091 --NumFastIselRemaining;
1092 ++NumFastIselSuccess;
1093 // If fast isel succeeded, skip over all the folded instructions, and
1094 // then see if there is a load right before the selected instructions.
1095 // Try to fold the load if so.
1096 const Instruction *BeforeInst = Inst;
1097 while (BeforeInst != Begin) {
1098 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1099 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1102 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1103 BeforeInst->hasOneUse() &&
1104 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1105 // If we succeeded, don't re-select the load.
1106 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1107 --NumFastIselRemaining;
1108 ++NumFastIselSuccess;
1114 if (EnableFastISelVerbose2)
1115 collectFailStats(Inst);
1118 // Then handle certain instructions as single-LLVM-Instruction blocks.
1119 if (isa<CallInst>(Inst)) {
1121 if (EnableFastISelVerbose || EnableFastISelAbort) {
1122 dbgs() << "FastISel missed call: ";
1126 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1127 unsigned &R = FuncInfo->ValueMap[Inst];
1129 R = FuncInfo->CreateRegs(Inst->getType());
1132 bool HadTailCall = false;
1133 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1134 SelectBasicBlock(Inst, BI, HadTailCall);
1136 // If the call was emitted as a tail call, we're done with the block.
1137 // We also need to delete any previously emitted instructions.
1139 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1144 // Recompute NumFastIselRemaining as Selection DAG instruction
1145 // selection may have handled the call, input args, etc.
1146 unsigned RemainingNow = std::distance(Begin, BI);
1147 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1148 NumFastIselRemaining = RemainingNow;
1152 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1153 // Don't abort, and use a different message for terminator misses.
1154 NumFastIselFailures += NumFastIselRemaining;
1155 if (EnableFastISelVerbose || EnableFastISelAbort) {
1156 dbgs() << "FastISel missed terminator: ";
1160 NumFastIselFailures += NumFastIselRemaining;
1161 if (EnableFastISelVerbose || EnableFastISelAbort) {
1162 dbgs() << "FastISel miss: ";
1165 if (EnableFastISelAbort)
1166 // The "fast" selector couldn't handle something and bailed.
1167 // For the purpose of debugging, just abort.
1168 llvm_unreachable("FastISel didn't select the entire block");
1173 FastIS->recomputeInsertPt();
1175 // Lower any arguments needed in this block if this is the entry block.
1176 if (LLVMBB == &Fn.getEntryBlock()) {
1185 ++NumFastIselBlocks;
1188 // Run SelectionDAG instruction selection on the remainder of the block
1189 // not handled by FastISel. If FastISel is not run, this is the entire
1192 SelectBasicBlock(Begin, BI, HadTailCall);
1196 FuncInfo->PHINodesToUpdate.clear();
1200 SDB->clearDanglingDebugInfo();
1201 SDB->SPDescriptor.resetPerFunctionState();
1204 /// Given that the input MI is before a partial terminator sequence TSeq, return
1205 /// true if M + TSeq also a partial terminator sequence.
1207 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1208 /// lowering copy vregs into physical registers, which are then passed into
1209 /// terminator instructors so we can satisfy ABI constraints. A partial
1210 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1211 /// may be the whole terminator sequence).
1212 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1213 // If we do not have a copy or an implicit def, we return true if and only if
1214 // MI is a debug value.
1215 if (!MI->isCopy() && !MI->isImplicitDef())
1216 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1217 // physical registers if there is debug info associated with the terminator
1218 // of our mbb. We want to include said debug info in our terminator
1219 // sequence, so we return true in that case.
1220 return MI->isDebugValue();
1222 // We have left the terminator sequence if we are not doing one of the
1225 // 1. Copying a vreg into a physical register.
1226 // 2. Copying a vreg into a vreg.
1227 // 3. Defining a register via an implicit def.
1229 // OPI should always be a register definition...
1230 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1231 if (!OPI->isReg() || !OPI->isDef())
1234 // Defining any register via an implicit def is always ok.
1235 if (MI->isImplicitDef())
1238 // Grab the copy source...
1239 MachineInstr::const_mop_iterator OPI2 = OPI;
1241 assert(OPI2 != MI->operands_end()
1242 && "Should have a copy implying we should have 2 arguments.");
1244 // Make sure that the copy dest is not a vreg when the copy source is a
1245 // physical register.
1246 if (!OPI2->isReg() ||
1247 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1248 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1254 /// Find the split point at which to splice the end of BB into its success stack
1255 /// protector check machine basic block.
1257 /// On many platforms, due to ABI constraints, terminators, even before register
1258 /// allocation, use physical registers. This creates an issue for us since
1259 /// physical registers at this point can not travel across basic
1260 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1261 /// when they enter functions and moves them through a sequence of copies back
1262 /// into the physical registers right before the terminator creating a
1263 /// ``Terminator Sequence''. This function is searching for the beginning of the
1264 /// terminator sequence so that we can ensure that we splice off not just the
1265 /// terminator, but additionally the copies that move the vregs into the
1266 /// physical registers.
1267 static MachineBasicBlock::iterator
1268 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1269 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1271 if (SplitPoint == BB->begin())
1274 MachineBasicBlock::iterator Start = BB->begin();
1275 MachineBasicBlock::iterator Previous = SplitPoint;
1278 while (MIIsInTerminatorSequence(Previous)) {
1279 SplitPoint = Previous;
1280 if (Previous == Start)
1289 SelectionDAGISel::FinishBasicBlock() {
1291 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1292 << FuncInfo->PHINodesToUpdate.size() << "\n";
1293 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1294 dbgs() << "Node " << i << " : ("
1295 << FuncInfo->PHINodesToUpdate[i].first
1296 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1298 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1299 SDB->JTCases.empty() &&
1300 SDB->BitTestCases.empty();
1302 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1303 // PHI nodes in successors.
1304 if (MustUpdatePHINodes) {
1305 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1306 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1307 assert(PHI->isPHI() &&
1308 "This is not a machine PHI node that we are updating!");
1309 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1311 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1315 // Handle stack protector.
1316 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1317 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1318 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1320 // Find the split point to split the parent mbb. At the same time copy all
1321 // physical registers used in the tail of parent mbb into virtual registers
1322 // before the split point and back into physical registers after the split
1323 // point. This prevents us needing to deal with Live-ins and many other
1324 // register allocation issues caused by us splitting the parent mbb. The
1325 // register allocator will clean up said virtual copies later on.
1326 MachineBasicBlock::iterator SplitPoint =
1327 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1329 // Splice the terminator of ParentMBB into SuccessMBB.
1330 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1334 // Add compare/jump on neq/jump to the parent BB.
1335 FuncInfo->MBB = ParentMBB;
1336 FuncInfo->InsertPt = ParentMBB->end();
1337 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1338 CurDAG->setRoot(SDB->getRoot());
1340 CodeGenAndEmitDAG();
1342 // CodeGen Failure MBB if we have not codegened it yet.
1343 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1344 if (!FailureMBB->size()) {
1345 FuncInfo->MBB = FailureMBB;
1346 FuncInfo->InsertPt = FailureMBB->end();
1347 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1348 CurDAG->setRoot(SDB->getRoot());
1350 CodeGenAndEmitDAG();
1353 // Clear the Per-BB State.
1354 SDB->SPDescriptor.resetPerBBState();
1357 // If we updated PHI Nodes, return early.
1358 if (MustUpdatePHINodes)
1361 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1362 // Lower header first, if it wasn't already lowered
1363 if (!SDB->BitTestCases[i].Emitted) {
1364 // Set the current basic block to the mbb we wish to insert the code into
1365 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1366 FuncInfo->InsertPt = FuncInfo->MBB->end();
1368 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1369 CurDAG->setRoot(SDB->getRoot());
1371 CodeGenAndEmitDAG();
1374 uint32_t UnhandledWeight = 0;
1375 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1376 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1378 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1379 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1380 // Set the current basic block to the mbb we wish to insert the code into
1381 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1382 FuncInfo->InsertPt = FuncInfo->MBB->end();
1385 SDB->visitBitTestCase(SDB->BitTestCases[i],
1386 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1388 SDB->BitTestCases[i].Reg,
1389 SDB->BitTestCases[i].Cases[j],
1392 SDB->visitBitTestCase(SDB->BitTestCases[i],
1393 SDB->BitTestCases[i].Default,
1395 SDB->BitTestCases[i].Reg,
1396 SDB->BitTestCases[i].Cases[j],
1400 CurDAG->setRoot(SDB->getRoot());
1402 CodeGenAndEmitDAG();
1406 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1408 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1409 MachineBasicBlock *PHIBB = PHI->getParent();
1410 assert(PHI->isPHI() &&
1411 "This is not a machine PHI node that we are updating!");
1412 // This is "default" BB. We have two jumps to it. From "header" BB and
1413 // from last "case" BB.
1414 if (PHIBB == SDB->BitTestCases[i].Default)
1415 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1416 .addMBB(SDB->BitTestCases[i].Parent)
1417 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1418 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1419 // One of "cases" BB.
1420 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1422 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1423 if (cBB->isSuccessor(PHIBB))
1424 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1428 SDB->BitTestCases.clear();
1430 // If the JumpTable record is filled in, then we need to emit a jump table.
1431 // Updating the PHI nodes is tricky in this case, since we need to determine
1432 // whether the PHI is a successor of the range check MBB or the jump table MBB
1433 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1434 // Lower header first, if it wasn't already lowered
1435 if (!SDB->JTCases[i].first.Emitted) {
1436 // Set the current basic block to the mbb we wish to insert the code into
1437 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1438 FuncInfo->InsertPt = FuncInfo->MBB->end();
1440 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1442 CurDAG->setRoot(SDB->getRoot());
1444 CodeGenAndEmitDAG();
1447 // Set the current basic block to the mbb we wish to insert the code into
1448 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1449 FuncInfo->InsertPt = FuncInfo->MBB->end();
1451 SDB->visitJumpTable(SDB->JTCases[i].second);
1452 CurDAG->setRoot(SDB->getRoot());
1454 CodeGenAndEmitDAG();
1457 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1459 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1460 MachineBasicBlock *PHIBB = PHI->getParent();
1461 assert(PHI->isPHI() &&
1462 "This is not a machine PHI node that we are updating!");
1463 // "default" BB. We can go there only from header BB.
1464 if (PHIBB == SDB->JTCases[i].second.Default)
1465 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1466 .addMBB(SDB->JTCases[i].first.HeaderBB);
1467 // JT BB. Just iterate over successors here
1468 if (FuncInfo->MBB->isSuccessor(PHIBB))
1469 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1472 SDB->JTCases.clear();
1474 // If the switch block involved a branch to one of the actual successors, we
1475 // need to update PHI nodes in that block.
1476 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1477 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1478 assert(PHI->isPHI() &&
1479 "This is not a machine PHI node that we are updating!");
1480 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1481 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1484 // If we generated any switch lowering information, build and codegen any
1485 // additional DAGs necessary.
1486 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1487 // Set the current basic block to the mbb we wish to insert the code into
1488 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1489 FuncInfo->InsertPt = FuncInfo->MBB->end();
1491 // Determine the unique successors.
1492 SmallVector<MachineBasicBlock *, 2> Succs;
1493 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1494 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1495 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1497 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1498 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1499 CurDAG->setRoot(SDB->getRoot());
1501 CodeGenAndEmitDAG();
1503 // Remember the last block, now that any splitting is done, for use in
1504 // populating PHI nodes in successors.
1505 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1507 // Handle any PHI nodes in successors of this chunk, as if we were coming
1508 // from the original BB before switch expansion. Note that PHI nodes can
1509 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1510 // handle them the right number of times.
1511 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1512 FuncInfo->MBB = Succs[i];
1513 FuncInfo->InsertPt = FuncInfo->MBB->end();
1514 // FuncInfo->MBB may have been removed from the CFG if a branch was
1516 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1517 for (MachineBasicBlock::iterator
1518 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1519 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1520 MachineInstrBuilder PHI(*MF, MBBI);
1521 // This value for this PHI node is recorded in PHINodesToUpdate.
1522 for (unsigned pn = 0; ; ++pn) {
1523 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1524 "Didn't find PHI entry!");
1525 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1526 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1534 SDB->SwitchCases.clear();
1538 /// Create the scheduler. If a specific scheduler was specified
1539 /// via the SchedulerRegistry, use it, otherwise select the
1540 /// one preferred by the target.
1542 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1543 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1547 RegisterScheduler::setDefault(Ctor);
1550 return Ctor(this, OptLevel);
1553 //===----------------------------------------------------------------------===//
1554 // Helper functions used by the generated instruction selector.
1555 //===----------------------------------------------------------------------===//
1556 // Calls to these methods are generated by tblgen.
1558 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1559 /// the dag combiner simplified the 255, we still want to match. RHS is the
1560 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1561 /// specified in the .td file (e.g. 255).
1562 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1563 int64_t DesiredMaskS) const {
1564 const APInt &ActualMask = RHS->getAPIntValue();
1565 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1567 // If the actual mask exactly matches, success!
1568 if (ActualMask == DesiredMask)
1571 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1572 if (ActualMask.intersects(~DesiredMask))
1575 // Otherwise, the DAG Combiner may have proven that the value coming in is
1576 // either already zero or is not demanded. Check for known zero input bits.
1577 APInt NeededMask = DesiredMask & ~ActualMask;
1578 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1581 // TODO: check to see if missing bits are just not demanded.
1583 // Otherwise, this pattern doesn't match.
1587 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1588 /// the dag combiner simplified the 255, we still want to match. RHS is the
1589 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1590 /// specified in the .td file (e.g. 255).
1591 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1592 int64_t DesiredMaskS) const {
1593 const APInt &ActualMask = RHS->getAPIntValue();
1594 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1596 // If the actual mask exactly matches, success!
1597 if (ActualMask == DesiredMask)
1600 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1601 if (ActualMask.intersects(~DesiredMask))
1604 // Otherwise, the DAG Combiner may have proven that the value coming in is
1605 // either already zero or is not demanded. Check for known zero input bits.
1606 APInt NeededMask = DesiredMask & ~ActualMask;
1608 APInt KnownZero, KnownOne;
1609 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1611 // If all the missing bits in the or are already known to be set, match!
1612 if ((NeededMask & KnownOne) == NeededMask)
1615 // TODO: check to see if missing bits are just not demanded.
1617 // Otherwise, this pattern doesn't match.
1622 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1623 /// by tblgen. Others should not call it.
1624 void SelectionDAGISel::
1625 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1626 std::vector<SDValue> InOps;
1627 std::swap(InOps, Ops);
1629 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1630 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1631 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1632 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1634 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1635 if (InOps[e-1].getValueType() == MVT::Glue)
1636 --e; // Don't process a glue operand if it is here.
1639 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1640 if (!InlineAsm::isMemKind(Flags)) {
1641 // Just skip over this operand, copying the operands verbatim.
1642 Ops.insert(Ops.end(), InOps.begin()+i,
1643 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1644 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1646 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1647 "Memory operand with multiple values?");
1648 // Otherwise, this is a memory operand. Ask the target to select it.
1649 std::vector<SDValue> SelOps;
1650 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1651 report_fatal_error("Could not match memory address. Inline asm"
1654 // Add this to the output node.
1656 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1657 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1658 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1663 // Add the glue input back if present.
1664 if (e != InOps.size())
1665 Ops.push_back(InOps.back());
1668 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1671 static SDNode *findGlueUse(SDNode *N) {
1672 unsigned FlagResNo = N->getNumValues()-1;
1673 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1674 SDUse &Use = I.getUse();
1675 if (Use.getResNo() == FlagResNo)
1676 return Use.getUser();
1681 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1682 /// This function recursively traverses up the operand chain, ignoring
1684 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1685 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1686 bool IgnoreChains) {
1687 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1688 // greater than all of its (recursive) operands. If we scan to a point where
1689 // 'use' is smaller than the node we're scanning for, then we know we will
1692 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1693 // happen because we scan down to newly selected nodes in the case of glue
1695 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1698 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1699 // won't fail if we scan it again.
1700 if (!Visited.insert(Use))
1703 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1704 // Ignore chain uses, they are validated by HandleMergeInputChains.
1705 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1708 SDNode *N = Use->getOperand(i).getNode();
1710 if (Use == ImmedUse || Use == Root)
1711 continue; // We are not looking for immediate use.
1716 // Traverse up the operand chain.
1717 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1723 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1724 /// operand node N of U during instruction selection that starts at Root.
1725 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1726 SDNode *Root) const {
1727 if (OptLevel == CodeGenOpt::None) return false;
1728 return N.hasOneUse();
1731 /// IsLegalToFold - Returns true if the specific operand node N of
1732 /// U can be folded during instruction selection that starts at Root.
1733 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1734 CodeGenOpt::Level OptLevel,
1735 bool IgnoreChains) {
1736 if (OptLevel == CodeGenOpt::None) return false;
1738 // If Root use can somehow reach N through a path that that doesn't contain
1739 // U then folding N would create a cycle. e.g. In the following
1740 // diagram, Root can reach N through X. If N is folded into into Root, then
1741 // X is both a predecessor and a successor of U.
1752 // * indicates nodes to be folded together.
1754 // If Root produces glue, then it gets (even more) interesting. Since it
1755 // will be "glued" together with its glue use in the scheduler, we need to
1756 // check if it might reach N.
1775 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1776 // (call it Fold), then X is a predecessor of GU and a successor of
1777 // Fold. But since Fold and GU are glued together, this will create
1778 // a cycle in the scheduling graph.
1780 // If the node has glue, walk down the graph to the "lowest" node in the
1782 EVT VT = Root->getValueType(Root->getNumValues()-1);
1783 while (VT == MVT::Glue) {
1784 SDNode *GU = findGlueUse(Root);
1788 VT = Root->getValueType(Root->getNumValues()-1);
1790 // If our query node has a glue result with a use, we've walked up it. If
1791 // the user (which has already been selected) has a chain or indirectly uses
1792 // the chain, our WalkChainUsers predicate will not consider it. Because of
1793 // this, we cannot ignore chains in this predicate.
1794 IgnoreChains = false;
1798 SmallPtrSet<SDNode*, 16> Visited;
1799 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1802 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1803 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1804 SelectInlineAsmMemoryOperands(Ops);
1806 EVT VTs[] = { MVT::Other, MVT::Glue };
1807 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
1808 VTs, &Ops[0], Ops.size());
1810 return New.getNode();
1813 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1814 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1817 /// GetVBR - decode a vbr encoding whose top bit is set.
1818 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1819 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1820 assert(Val >= 128 && "Not a VBR");
1821 Val &= 127; // Remove first vbr bit.
1826 NextBits = MatcherTable[Idx++];
1827 Val |= (NextBits&127) << Shift;
1829 } while (NextBits & 128);
1835 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1836 /// interior glue and chain results to use the new glue and chain results.
1837 void SelectionDAGISel::
1838 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1839 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1841 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1842 bool isMorphNodeTo) {
1843 SmallVector<SDNode*, 4> NowDeadNodes;
1845 // Now that all the normal results are replaced, we replace the chain and
1846 // glue results if present.
1847 if (!ChainNodesMatched.empty()) {
1848 assert(InputChain.getNode() != 0 &&
1849 "Matched input chains but didn't produce a chain");
1850 // Loop over all of the nodes we matched that produced a chain result.
1851 // Replace all the chain results with the final chain we ended up with.
1852 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1853 SDNode *ChainNode = ChainNodesMatched[i];
1855 // If this node was already deleted, don't look at it.
1856 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1859 // Don't replace the results of the root node if we're doing a
1861 if (ChainNode == NodeToMatch && isMorphNodeTo)
1864 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1865 if (ChainVal.getValueType() == MVT::Glue)
1866 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1867 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1868 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1870 // If the node became dead and we haven't already seen it, delete it.
1871 if (ChainNode->use_empty() &&
1872 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1873 NowDeadNodes.push_back(ChainNode);
1877 // If the result produces glue, update any glue results in the matched
1878 // pattern with the glue result.
1879 if (InputGlue.getNode() != 0) {
1880 // Handle any interior nodes explicitly marked.
1881 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1882 SDNode *FRN = GlueResultNodesMatched[i];
1884 // If this node was already deleted, don't look at it.
1885 if (FRN->getOpcode() == ISD::DELETED_NODE)
1888 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1889 "Doesn't have a glue result");
1890 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1893 // If the node became dead and we haven't already seen it, delete it.
1894 if (FRN->use_empty() &&
1895 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1896 NowDeadNodes.push_back(FRN);
1900 if (!NowDeadNodes.empty())
1901 CurDAG->RemoveDeadNodes(NowDeadNodes);
1903 DEBUG(dbgs() << "ISEL: Match complete!\n");
1909 CR_LeadsToInteriorNode
1912 /// WalkChainUsers - Walk down the users of the specified chained node that is
1913 /// part of the pattern we're matching, looking at all of the users we find.
1914 /// This determines whether something is an interior node, whether we have a
1915 /// non-pattern node in between two pattern nodes (which prevent folding because
1916 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1917 /// between pattern nodes (in which case the TF becomes part of the pattern).
1919 /// The walk we do here is guaranteed to be small because we quickly get down to
1920 /// already selected nodes "below" us.
1922 WalkChainUsers(const SDNode *ChainedNode,
1923 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1924 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1925 ChainResult Result = CR_Simple;
1927 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1928 E = ChainedNode->use_end(); UI != E; ++UI) {
1929 // Make sure the use is of the chain, not some other value we produce.
1930 if (UI.getUse().getValueType() != MVT::Other) continue;
1934 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1937 // If we see an already-selected machine node, then we've gone beyond the
1938 // pattern that we're selecting down into the already selected chunk of the
1940 unsigned UserOpcode = User->getOpcode();
1941 if (User->isMachineOpcode() ||
1942 UserOpcode == ISD::CopyToReg ||
1943 UserOpcode == ISD::CopyFromReg ||
1944 UserOpcode == ISD::INLINEASM ||
1945 UserOpcode == ISD::EH_LABEL ||
1946 UserOpcode == ISD::LIFETIME_START ||
1947 UserOpcode == ISD::LIFETIME_END) {
1948 // If their node ID got reset to -1 then they've already been selected.
1949 // Treat them like a MachineOpcode.
1950 if (User->getNodeId() == -1)
1954 // If we have a TokenFactor, we handle it specially.
1955 if (User->getOpcode() != ISD::TokenFactor) {
1956 // If the node isn't a token factor and isn't part of our pattern, then it
1957 // must be a random chained node in between two nodes we're selecting.
1958 // This happens when we have something like:
1963 // Because we structurally match the load/store as a read/modify/write,
1964 // but the call is chained between them. We cannot fold in this case
1965 // because it would induce a cycle in the graph.
1966 if (!std::count(ChainedNodesInPattern.begin(),
1967 ChainedNodesInPattern.end(), User))
1968 return CR_InducesCycle;
1970 // Otherwise we found a node that is part of our pattern. For example in:
1974 // This would happen when we're scanning down from the load and see the
1975 // store as a user. Record that there is a use of ChainedNode that is
1976 // part of the pattern and keep scanning uses.
1977 Result = CR_LeadsToInteriorNode;
1978 InteriorChainedNodes.push_back(User);
1982 // If we found a TokenFactor, there are two cases to consider: first if the
1983 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1984 // uses of the TF are in our pattern) we just want to ignore it. Second,
1985 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1991 // | \ DAG's like cheese
1994 // [TokenFactor] [Op]
2001 // In this case, the TokenFactor becomes part of our match and we rewrite it
2002 // as a new TokenFactor.
2004 // To distinguish these two cases, do a recursive walk down the uses.
2005 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2007 // If the uses of the TokenFactor are just already-selected nodes, ignore
2008 // it, it is "below" our pattern.
2010 case CR_InducesCycle:
2011 // If the uses of the TokenFactor lead to nodes that are not part of our
2012 // pattern that are not selected, folding would turn this into a cycle,
2014 return CR_InducesCycle;
2015 case CR_LeadsToInteriorNode:
2016 break; // Otherwise, keep processing.
2019 // Okay, we know we're in the interesting interior case. The TokenFactor
2020 // is now going to be considered part of the pattern so that we rewrite its
2021 // uses (it may have uses that are not part of the pattern) with the
2022 // ultimate chain result of the generated code. We will also add its chain
2023 // inputs as inputs to the ultimate TokenFactor we create.
2024 Result = CR_LeadsToInteriorNode;
2025 ChainedNodesInPattern.push_back(User);
2026 InteriorChainedNodes.push_back(User);
2033 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2034 /// operation for when the pattern matched at least one node with a chains. The
2035 /// input vector contains a list of all of the chained nodes that we match. We
2036 /// must determine if this is a valid thing to cover (i.e. matching it won't
2037 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2038 /// be used as the input node chain for the generated nodes.
2040 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2041 SelectionDAG *CurDAG) {
2042 // Walk all of the chained nodes we've matched, recursively scanning down the
2043 // users of the chain result. This adds any TokenFactor nodes that are caught
2044 // in between chained nodes to the chained and interior nodes list.
2045 SmallVector<SDNode*, 3> InteriorChainedNodes;
2046 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2047 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2048 InteriorChainedNodes) == CR_InducesCycle)
2049 return SDValue(); // Would induce a cycle.
2052 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2053 // that we are interested in. Form our input TokenFactor node.
2054 SmallVector<SDValue, 3> InputChains;
2055 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2056 // Add the input chain of this node to the InputChains list (which will be
2057 // the operands of the generated TokenFactor) if it's not an interior node.
2058 SDNode *N = ChainNodesMatched[i];
2059 if (N->getOpcode() != ISD::TokenFactor) {
2060 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2063 // Otherwise, add the input chain.
2064 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2065 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2066 InputChains.push_back(InChain);
2070 // If we have a token factor, we want to add all inputs of the token factor
2071 // that are not part of the pattern we're matching.
2072 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2073 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2074 N->getOperand(op).getNode()))
2075 InputChains.push_back(N->getOperand(op));
2079 if (InputChains.size() == 1)
2080 return InputChains[0];
2081 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2082 MVT::Other, &InputChains[0], InputChains.size());
2085 /// MorphNode - Handle morphing a node in place for the selector.
2086 SDNode *SelectionDAGISel::
2087 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2088 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
2089 // It is possible we're using MorphNodeTo to replace a node with no
2090 // normal results with one that has a normal result (or we could be
2091 // adding a chain) and the input could have glue and chains as well.
2092 // In this case we need to shift the operands down.
2093 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2094 // than the old isel though.
2095 int OldGlueResultNo = -1, OldChainResultNo = -1;
2097 unsigned NTMNumResults = Node->getNumValues();
2098 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2099 OldGlueResultNo = NTMNumResults-1;
2100 if (NTMNumResults != 1 &&
2101 Node->getValueType(NTMNumResults-2) == MVT::Other)
2102 OldChainResultNo = NTMNumResults-2;
2103 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2104 OldChainResultNo = NTMNumResults-1;
2106 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2107 // that this deletes operands of the old node that become dead.
2108 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
2110 // MorphNodeTo can operate in two ways: if an existing node with the
2111 // specified operands exists, it can just return it. Otherwise, it
2112 // updates the node in place to have the requested operands.
2114 // If we updated the node in place, reset the node ID. To the isel,
2115 // this should be just like a newly allocated machine node.
2119 unsigned ResNumResults = Res->getNumValues();
2120 // Move the glue if needed.
2121 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2122 (unsigned)OldGlueResultNo != ResNumResults-1)
2123 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2124 SDValue(Res, ResNumResults-1));
2126 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2129 // Move the chain reference if needed.
2130 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2131 (unsigned)OldChainResultNo != ResNumResults-1)
2132 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2133 SDValue(Res, ResNumResults-1));
2135 // Otherwise, no replacement happened because the node already exists. Replace
2136 // Uses of the old node with the new one.
2138 CurDAG->ReplaceAllUsesWith(Node, Res);
2143 /// CheckSame - Implements OP_CheckSame.
2144 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2145 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2147 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2148 // Accept if it is exactly the same as a previously recorded node.
2149 unsigned RecNo = MatcherTable[MatcherIndex++];
2150 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2151 return N == RecordedNodes[RecNo].first;
2154 /// CheckChildSame - Implements OP_CheckChildXSame.
2155 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2156 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2158 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2160 if (ChildNo >= N.getNumOperands())
2161 return false; // Match fails if out of range child #.
2162 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2166 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2167 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2168 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2169 const SelectionDAGISel &SDISel) {
2170 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2173 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2174 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2175 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2176 const SelectionDAGISel &SDISel, SDNode *N) {
2177 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2180 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2181 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2183 uint16_t Opc = MatcherTable[MatcherIndex++];
2184 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2185 return N->getOpcode() == Opc;
2188 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2189 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2190 SDValue N, const TargetLowering *TLI) {
2191 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2192 if (N.getValueType() == VT) return true;
2194 // Handle the case when VT is iPTR.
2195 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2198 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2199 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2200 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2201 if (ChildNo >= N.getNumOperands())
2202 return false; // Match fails if out of range child #.
2203 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2206 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2207 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2209 return cast<CondCodeSDNode>(N)->get() ==
2210 (ISD::CondCode)MatcherTable[MatcherIndex++];
2213 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2214 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2215 SDValue N, const TargetLowering *TLI) {
2216 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2217 if (cast<VTSDNode>(N)->getVT() == VT)
2220 // Handle the case when VT is iPTR.
2221 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2224 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2225 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2227 int64_t Val = MatcherTable[MatcherIndex++];
2229 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2231 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2232 return C != 0 && C->getSExtValue() == Val;
2235 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2236 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2237 SDValue N, unsigned ChildNo) {
2238 if (ChildNo >= N.getNumOperands())
2239 return false; // Match fails if out of range child #.
2240 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2243 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2244 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2245 SDValue N, const SelectionDAGISel &SDISel) {
2246 int64_t Val = MatcherTable[MatcherIndex++];
2248 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2250 if (N->getOpcode() != ISD::AND) return false;
2252 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2253 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2256 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2257 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2258 SDValue N, const SelectionDAGISel &SDISel) {
2259 int64_t Val = MatcherTable[MatcherIndex++];
2261 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2263 if (N->getOpcode() != ISD::OR) return false;
2265 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2266 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2269 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2270 /// scope, evaluate the current node. If the current predicate is known to
2271 /// fail, set Result=true and return anything. If the current predicate is
2272 /// known to pass, set Result=false and return the MatcherIndex to continue
2273 /// with. If the current predicate is unknown, set Result=false and return the
2274 /// MatcherIndex to continue with.
2275 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2276 unsigned Index, SDValue N,
2278 const SelectionDAGISel &SDISel,
2279 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2280 switch (Table[Index++]) {
2283 return Index-1; // Could not evaluate this predicate.
2284 case SelectionDAGISel::OPC_CheckSame:
2285 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2287 case SelectionDAGISel::OPC_CheckChild0Same:
2288 case SelectionDAGISel::OPC_CheckChild1Same:
2289 case SelectionDAGISel::OPC_CheckChild2Same:
2290 case SelectionDAGISel::OPC_CheckChild3Same:
2291 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2292 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2294 case SelectionDAGISel::OPC_CheckPatternPredicate:
2295 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2297 case SelectionDAGISel::OPC_CheckPredicate:
2298 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2300 case SelectionDAGISel::OPC_CheckOpcode:
2301 Result = !::CheckOpcode(Table, Index, N.getNode());
2303 case SelectionDAGISel::OPC_CheckType:
2304 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering());
2306 case SelectionDAGISel::OPC_CheckChild0Type:
2307 case SelectionDAGISel::OPC_CheckChild1Type:
2308 case SelectionDAGISel::OPC_CheckChild2Type:
2309 case SelectionDAGISel::OPC_CheckChild3Type:
2310 case SelectionDAGISel::OPC_CheckChild4Type:
2311 case SelectionDAGISel::OPC_CheckChild5Type:
2312 case SelectionDAGISel::OPC_CheckChild6Type:
2313 case SelectionDAGISel::OPC_CheckChild7Type:
2314 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(),
2315 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2317 case SelectionDAGISel::OPC_CheckCondCode:
2318 Result = !::CheckCondCode(Table, Index, N);
2320 case SelectionDAGISel::OPC_CheckValueType:
2321 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering());
2323 case SelectionDAGISel::OPC_CheckInteger:
2324 Result = !::CheckInteger(Table, Index, N);
2326 case SelectionDAGISel::OPC_CheckChild0Integer:
2327 case SelectionDAGISel::OPC_CheckChild1Integer:
2328 case SelectionDAGISel::OPC_CheckChild2Integer:
2329 case SelectionDAGISel::OPC_CheckChild3Integer:
2330 case SelectionDAGISel::OPC_CheckChild4Integer:
2331 Result = !::CheckChildInteger(Table, Index, N,
2332 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2334 case SelectionDAGISel::OPC_CheckAndImm:
2335 Result = !::CheckAndImm(Table, Index, N, SDISel);
2337 case SelectionDAGISel::OPC_CheckOrImm:
2338 Result = !::CheckOrImm(Table, Index, N, SDISel);
2346 /// FailIndex - If this match fails, this is the index to continue with.
2349 /// NodeStack - The node stack when the scope was formed.
2350 SmallVector<SDValue, 4> NodeStack;
2352 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2353 unsigned NumRecordedNodes;
2355 /// NumMatchedMemRefs - The number of matched memref entries.
2356 unsigned NumMatchedMemRefs;
2358 /// InputChain/InputGlue - The current chain/glue
2359 SDValue InputChain, InputGlue;
2361 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2362 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2367 SDNode *SelectionDAGISel::
2368 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2369 unsigned TableSize) {
2370 // FIXME: Should these even be selected? Handle these cases in the caller?
2371 switch (NodeToMatch->getOpcode()) {
2374 case ISD::EntryToken: // These nodes remain the same.
2375 case ISD::BasicBlock:
2377 case ISD::RegisterMask:
2378 //case ISD::VALUETYPE:
2379 //case ISD::CONDCODE:
2380 case ISD::HANDLENODE:
2381 case ISD::MDNODE_SDNODE:
2382 case ISD::TargetConstant:
2383 case ISD::TargetConstantFP:
2384 case ISD::TargetConstantPool:
2385 case ISD::TargetFrameIndex:
2386 case ISD::TargetExternalSymbol:
2387 case ISD::TargetBlockAddress:
2388 case ISD::TargetJumpTable:
2389 case ISD::TargetGlobalTLSAddress:
2390 case ISD::TargetGlobalAddress:
2391 case ISD::TokenFactor:
2392 case ISD::CopyFromReg:
2393 case ISD::CopyToReg:
2395 case ISD::LIFETIME_START:
2396 case ISD::LIFETIME_END:
2397 NodeToMatch->setNodeId(-1); // Mark selected.
2399 case ISD::AssertSext:
2400 case ISD::AssertZext:
2401 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2402 NodeToMatch->getOperand(0));
2404 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2405 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2408 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2410 // Set up the node stack with NodeToMatch as the only node on the stack.
2411 SmallVector<SDValue, 8> NodeStack;
2412 SDValue N = SDValue(NodeToMatch, 0);
2413 NodeStack.push_back(N);
2415 // MatchScopes - Scopes used when matching, if a match failure happens, this
2416 // indicates where to continue checking.
2417 SmallVector<MatchScope, 8> MatchScopes;
2419 // RecordedNodes - This is the set of nodes that have been recorded by the
2420 // state machine. The second value is the parent of the node, or null if the
2421 // root is recorded.
2422 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2424 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2426 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2428 // These are the current input chain and glue for use when generating nodes.
2429 // Various Emit operations change these. For example, emitting a copytoreg
2430 // uses and updates these.
2431 SDValue InputChain, InputGlue;
2433 // ChainNodesMatched - If a pattern matches nodes that have input/output
2434 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2435 // which ones they are. The result is captured into this list so that we can
2436 // update the chain results when the pattern is complete.
2437 SmallVector<SDNode*, 3> ChainNodesMatched;
2438 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2440 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2441 NodeToMatch->dump(CurDAG);
2444 // Determine where to start the interpreter. Normally we start at opcode #0,
2445 // but if the state machine starts with an OPC_SwitchOpcode, then we
2446 // accelerate the first lookup (which is guaranteed to be hot) with the
2447 // OpcodeOffset table.
2448 unsigned MatcherIndex = 0;
2450 if (!OpcodeOffset.empty()) {
2451 // Already computed the OpcodeOffset table, just index into it.
2452 if (N.getOpcode() < OpcodeOffset.size())
2453 MatcherIndex = OpcodeOffset[N.getOpcode()];
2454 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2456 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2457 // Otherwise, the table isn't computed, but the state machine does start
2458 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2459 // is the first time we're selecting an instruction.
2462 // Get the size of this case.
2463 unsigned CaseSize = MatcherTable[Idx++];
2465 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2466 if (CaseSize == 0) break;
2468 // Get the opcode, add the index to the table.
2469 uint16_t Opc = MatcherTable[Idx++];
2470 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2471 if (Opc >= OpcodeOffset.size())
2472 OpcodeOffset.resize((Opc+1)*2);
2473 OpcodeOffset[Opc] = Idx;
2477 // Okay, do the lookup for the first opcode.
2478 if (N.getOpcode() < OpcodeOffset.size())
2479 MatcherIndex = OpcodeOffset[N.getOpcode()];
2483 assert(MatcherIndex < TableSize && "Invalid index");
2485 unsigned CurrentOpcodeIndex = MatcherIndex;
2487 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2490 // Okay, the semantics of this operation are that we should push a scope
2491 // then evaluate the first child. However, pushing a scope only to have
2492 // the first check fail (which then pops it) is inefficient. If we can
2493 // determine immediately that the first check (or first several) will
2494 // immediately fail, don't even bother pushing a scope for them.
2498 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2499 if (NumToSkip & 128)
2500 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2501 // Found the end of the scope with no match.
2502 if (NumToSkip == 0) {
2507 FailIndex = MatcherIndex+NumToSkip;
2509 unsigned MatcherIndexOfPredicate = MatcherIndex;
2510 (void)MatcherIndexOfPredicate; // silence warning.
2512 // If we can't evaluate this predicate without pushing a scope (e.g. if
2513 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2514 // push the scope and evaluate the full predicate chain.
2516 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2517 Result, *this, RecordedNodes);
2521 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2522 << "index " << MatcherIndexOfPredicate
2523 << ", continuing at " << FailIndex << "\n");
2524 ++NumDAGIselRetries;
2526 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2527 // move to the next case.
2528 MatcherIndex = FailIndex;
2531 // If the whole scope failed to match, bail.
2532 if (FailIndex == 0) break;
2534 // Push a MatchScope which indicates where to go if the first child fails
2536 MatchScope NewEntry;
2537 NewEntry.FailIndex = FailIndex;
2538 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2539 NewEntry.NumRecordedNodes = RecordedNodes.size();
2540 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2541 NewEntry.InputChain = InputChain;
2542 NewEntry.InputGlue = InputGlue;
2543 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2544 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2545 MatchScopes.push_back(NewEntry);
2548 case OPC_RecordNode: {
2549 // Remember this node, it may end up being an operand in the pattern.
2551 if (NodeStack.size() > 1)
2552 Parent = NodeStack[NodeStack.size()-2].getNode();
2553 RecordedNodes.push_back(std::make_pair(N, Parent));
2557 case OPC_RecordChild0: case OPC_RecordChild1:
2558 case OPC_RecordChild2: case OPC_RecordChild3:
2559 case OPC_RecordChild4: case OPC_RecordChild5:
2560 case OPC_RecordChild6: case OPC_RecordChild7: {
2561 unsigned ChildNo = Opcode-OPC_RecordChild0;
2562 if (ChildNo >= N.getNumOperands())
2563 break; // Match fails if out of range child #.
2565 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2569 case OPC_RecordMemRef:
2570 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2573 case OPC_CaptureGlueInput:
2574 // If the current node has an input glue, capture it in InputGlue.
2575 if (N->getNumOperands() != 0 &&
2576 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2577 InputGlue = N->getOperand(N->getNumOperands()-1);
2580 case OPC_MoveChild: {
2581 unsigned ChildNo = MatcherTable[MatcherIndex++];
2582 if (ChildNo >= N.getNumOperands())
2583 break; // Match fails if out of range child #.
2584 N = N.getOperand(ChildNo);
2585 NodeStack.push_back(N);
2589 case OPC_MoveParent:
2590 // Pop the current node off the NodeStack.
2591 NodeStack.pop_back();
2592 assert(!NodeStack.empty() && "Node stack imbalance!");
2593 N = NodeStack.back();
2597 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2600 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2601 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2602 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2603 Opcode-OPC_CheckChild0Same))
2607 case OPC_CheckPatternPredicate:
2608 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2610 case OPC_CheckPredicate:
2611 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2615 case OPC_CheckComplexPat: {
2616 unsigned CPNum = MatcherTable[MatcherIndex++];
2617 unsigned RecNo = MatcherTable[MatcherIndex++];
2618 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2619 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2620 RecordedNodes[RecNo].first, CPNum,
2625 case OPC_CheckOpcode:
2626 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2630 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2634 case OPC_SwitchOpcode: {
2635 unsigned CurNodeOpcode = N.getOpcode();
2636 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2639 // Get the size of this case.
2640 CaseSize = MatcherTable[MatcherIndex++];
2642 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2643 if (CaseSize == 0) break;
2645 uint16_t Opc = MatcherTable[MatcherIndex++];
2646 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2648 // If the opcode matches, then we will execute this case.
2649 if (CurNodeOpcode == Opc)
2652 // Otherwise, skip over this case.
2653 MatcherIndex += CaseSize;
2656 // If no cases matched, bail out.
2657 if (CaseSize == 0) break;
2659 // Otherwise, execute the case we found.
2660 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2661 << " to " << MatcherIndex << "\n");
2665 case OPC_SwitchType: {
2666 MVT CurNodeVT = N.getSimpleValueType();
2667 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2670 // Get the size of this case.
2671 CaseSize = MatcherTable[MatcherIndex++];
2673 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2674 if (CaseSize == 0) break;
2676 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2677 if (CaseVT == MVT::iPTR)
2678 CaseVT = getTargetLowering()->getPointerTy();
2680 // If the VT matches, then we will execute this case.
2681 if (CurNodeVT == CaseVT)
2684 // Otherwise, skip over this case.
2685 MatcherIndex += CaseSize;
2688 // If no cases matched, bail out.
2689 if (CaseSize == 0) break;
2691 // Otherwise, execute the case we found.
2692 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2693 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2696 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2697 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2698 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2699 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2700 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(),
2701 Opcode-OPC_CheckChild0Type))
2704 case OPC_CheckCondCode:
2705 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2707 case OPC_CheckValueType:
2708 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2711 case OPC_CheckInteger:
2712 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2714 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2715 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2716 case OPC_CheckChild4Integer:
2717 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2718 Opcode-OPC_CheckChild0Integer)) break;
2720 case OPC_CheckAndImm:
2721 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2723 case OPC_CheckOrImm:
2724 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2727 case OPC_CheckFoldableChainNode: {
2728 assert(NodeStack.size() != 1 && "No parent node");
2729 // Verify that all intermediate nodes between the root and this one have
2731 bool HasMultipleUses = false;
2732 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2733 if (!NodeStack[i].hasOneUse()) {
2734 HasMultipleUses = true;
2737 if (HasMultipleUses) break;
2739 // Check to see that the target thinks this is profitable to fold and that
2740 // we can fold it without inducing cycles in the graph.
2741 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2743 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2744 NodeToMatch, OptLevel,
2745 true/*We validate our own chains*/))
2750 case OPC_EmitInteger: {
2751 MVT::SimpleValueType VT =
2752 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2753 int64_t Val = MatcherTable[MatcherIndex++];
2755 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2756 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2757 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2760 case OPC_EmitRegister: {
2761 MVT::SimpleValueType VT =
2762 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2763 unsigned RegNo = MatcherTable[MatcherIndex++];
2764 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2765 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2768 case OPC_EmitRegister2: {
2769 // For targets w/ more than 256 register names, the register enum
2770 // values are stored in two bytes in the matcher table (just like
2772 MVT::SimpleValueType VT =
2773 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2774 unsigned RegNo = MatcherTable[MatcherIndex++];
2775 RegNo |= MatcherTable[MatcherIndex++] << 8;
2776 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2777 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2781 case OPC_EmitConvertToTarget: {
2782 // Convert from IMM/FPIMM to target version.
2783 unsigned RecNo = MatcherTable[MatcherIndex++];
2784 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2785 SDValue Imm = RecordedNodes[RecNo].first;
2787 if (Imm->getOpcode() == ISD::Constant) {
2788 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2789 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2790 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2791 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2792 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2795 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2799 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2800 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2801 // These are space-optimized forms of OPC_EmitMergeInputChains.
2802 assert(InputChain.getNode() == 0 &&
2803 "EmitMergeInputChains should be the first chain producing node");
2804 assert(ChainNodesMatched.empty() &&
2805 "Should only have one EmitMergeInputChains per match");
2807 // Read all of the chained nodes.
2808 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2809 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2810 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2812 // FIXME: What if other value results of the node have uses not matched
2814 if (ChainNodesMatched.back() != NodeToMatch &&
2815 !RecordedNodes[RecNo].first.hasOneUse()) {
2816 ChainNodesMatched.clear();
2820 // Merge the input chains if they are not intra-pattern references.
2821 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2823 if (InputChain.getNode() == 0)
2824 break; // Failed to merge.
2828 case OPC_EmitMergeInputChains: {
2829 assert(InputChain.getNode() == 0 &&
2830 "EmitMergeInputChains should be the first chain producing node");
2831 // This node gets a list of nodes we matched in the input that have
2832 // chains. We want to token factor all of the input chains to these nodes
2833 // together. However, if any of the input chains is actually one of the
2834 // nodes matched in this pattern, then we have an intra-match reference.
2835 // Ignore these because the newly token factored chain should not refer to
2837 unsigned NumChains = MatcherTable[MatcherIndex++];
2838 assert(NumChains != 0 && "Can't TF zero chains");
2840 assert(ChainNodesMatched.empty() &&
2841 "Should only have one EmitMergeInputChains per match");
2843 // Read all of the chained nodes.
2844 for (unsigned i = 0; i != NumChains; ++i) {
2845 unsigned RecNo = MatcherTable[MatcherIndex++];
2846 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2847 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2849 // FIXME: What if other value results of the node have uses not matched
2851 if (ChainNodesMatched.back() != NodeToMatch &&
2852 !RecordedNodes[RecNo].first.hasOneUse()) {
2853 ChainNodesMatched.clear();
2858 // If the inner loop broke out, the match fails.
2859 if (ChainNodesMatched.empty())
2862 // Merge the input chains if they are not intra-pattern references.
2863 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2865 if (InputChain.getNode() == 0)
2866 break; // Failed to merge.
2871 case OPC_EmitCopyToReg: {
2872 unsigned RecNo = MatcherTable[MatcherIndex++];
2873 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
2874 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2876 if (InputChain.getNode() == 0)
2877 InputChain = CurDAG->getEntryNode();
2879 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2880 DestPhysReg, RecordedNodes[RecNo].first,
2883 InputGlue = InputChain.getValue(1);
2887 case OPC_EmitNodeXForm: {
2888 unsigned XFormNo = MatcherTable[MatcherIndex++];
2889 unsigned RecNo = MatcherTable[MatcherIndex++];
2890 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
2891 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2892 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2897 case OPC_MorphNodeTo: {
2898 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2899 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2900 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2901 // Get the result VT list.
2902 unsigned NumVTs = MatcherTable[MatcherIndex++];
2903 SmallVector<EVT, 4> VTs;
2904 for (unsigned i = 0; i != NumVTs; ++i) {
2905 MVT::SimpleValueType VT =
2906 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2907 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy;
2911 if (EmitNodeInfo & OPFL_Chain)
2912 VTs.push_back(MVT::Other);
2913 if (EmitNodeInfo & OPFL_GlueOutput)
2914 VTs.push_back(MVT::Glue);
2916 // This is hot code, so optimize the two most common cases of 1 and 2
2919 if (VTs.size() == 1)
2920 VTList = CurDAG->getVTList(VTs[0]);
2921 else if (VTs.size() == 2)
2922 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2924 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2926 // Get the operand list.
2927 unsigned NumOps = MatcherTable[MatcherIndex++];
2928 SmallVector<SDValue, 8> Ops;
2929 for (unsigned i = 0; i != NumOps; ++i) {
2930 unsigned RecNo = MatcherTable[MatcherIndex++];
2932 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2934 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2935 Ops.push_back(RecordedNodes[RecNo].first);
2938 // If there are variadic operands to add, handle them now.
2939 if (EmitNodeInfo & OPFL_VariadicInfo) {
2940 // Determine the start index to copy from.
2941 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2942 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2943 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2944 "Invalid variadic node");
2945 // Copy all of the variadic operands, not including a potential glue
2947 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2949 SDValue V = NodeToMatch->getOperand(i);
2950 if (V.getValueType() == MVT::Glue) break;
2955 // If this has chain/glue inputs, add them.
2956 if (EmitNodeInfo & OPFL_Chain)
2957 Ops.push_back(InputChain);
2958 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2959 Ops.push_back(InputGlue);
2963 if (Opcode != OPC_MorphNodeTo) {
2964 // If this is a normal EmitNode command, just create the new node and
2965 // add the results to the RecordedNodes list.
2966 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
2969 // Add all the non-glue/non-chain results to the RecordedNodes list.
2970 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2971 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2972 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2976 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2977 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2980 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2981 // We will visit the equivalent node later.
2982 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2986 // If the node had chain/glue results, update our notion of the current
2988 if (EmitNodeInfo & OPFL_GlueOutput) {
2989 InputGlue = SDValue(Res, VTs.size()-1);
2990 if (EmitNodeInfo & OPFL_Chain)
2991 InputChain = SDValue(Res, VTs.size()-2);
2992 } else if (EmitNodeInfo & OPFL_Chain)
2993 InputChain = SDValue(Res, VTs.size()-1);
2995 // If the OPFL_MemRefs glue is set on this node, slap all of the
2996 // accumulated memrefs onto it.
2998 // FIXME: This is vastly incorrect for patterns with multiple outputs
2999 // instructions that access memory and for ComplexPatterns that match
3001 if (EmitNodeInfo & OPFL_MemRefs) {
3002 // Only attach load or store memory operands if the generated
3003 // instruction may load or store.
3004 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
3005 bool mayLoad = MCID.mayLoad();
3006 bool mayStore = MCID.mayStore();
3008 unsigned NumMemRefs = 0;
3009 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3010 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3011 if ((*I)->isLoad()) {
3014 } else if ((*I)->isStore()) {
3022 MachineSDNode::mmo_iterator MemRefs =
3023 MF->allocateMemRefsArray(NumMemRefs);
3025 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3026 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3027 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3028 if ((*I)->isLoad()) {
3031 } else if ((*I)->isStore()) {
3039 cast<MachineSDNode>(Res)
3040 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3044 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3045 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3047 // If this was a MorphNodeTo then we're completely done!
3048 if (Opcode == OPC_MorphNodeTo) {
3049 // Update chain and glue uses.
3050 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3051 InputGlue, GlueResultNodesMatched, true);
3058 case OPC_MarkGlueResults: {
3059 unsigned NumNodes = MatcherTable[MatcherIndex++];
3061 // Read and remember all the glue-result nodes.
3062 for (unsigned i = 0; i != NumNodes; ++i) {
3063 unsigned RecNo = MatcherTable[MatcherIndex++];
3065 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3067 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3068 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3073 case OPC_CompleteMatch: {
3074 // The match has been completed, and any new nodes (if any) have been
3075 // created. Patch up references to the matched dag to use the newly
3077 unsigned NumResults = MatcherTable[MatcherIndex++];
3079 for (unsigned i = 0; i != NumResults; ++i) {
3080 unsigned ResSlot = MatcherTable[MatcherIndex++];
3082 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3084 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3085 SDValue Res = RecordedNodes[ResSlot].first;
3087 assert(i < NodeToMatch->getNumValues() &&
3088 NodeToMatch->getValueType(i) != MVT::Other &&
3089 NodeToMatch->getValueType(i) != MVT::Glue &&
3090 "Invalid number of results to complete!");
3091 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3092 NodeToMatch->getValueType(i) == MVT::iPTR ||
3093 Res.getValueType() == MVT::iPTR ||
3094 NodeToMatch->getValueType(i).getSizeInBits() ==
3095 Res.getValueType().getSizeInBits()) &&
3096 "invalid replacement");
3097 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3100 // If the root node defines glue, add it to the glue nodes to update list.
3101 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3102 GlueResultNodesMatched.push_back(NodeToMatch);
3104 // Update chain and glue uses.
3105 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3106 InputGlue, GlueResultNodesMatched, false);
3108 assert(NodeToMatch->use_empty() &&
3109 "Didn't replace all uses of the node?");
3111 // FIXME: We just return here, which interacts correctly with SelectRoot
3112 // above. We should fix this to not return an SDNode* anymore.
3117 // If the code reached this point, then the match failed. See if there is
3118 // another child to try in the current 'Scope', otherwise pop it until we
3119 // find a case to check.
3120 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3121 ++NumDAGIselRetries;
3123 if (MatchScopes.empty()) {
3124 CannotYetSelect(NodeToMatch);
3128 // Restore the interpreter state back to the point where the scope was
3130 MatchScope &LastScope = MatchScopes.back();
3131 RecordedNodes.resize(LastScope.NumRecordedNodes);
3133 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3134 N = NodeStack.back();
3136 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3137 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3138 MatcherIndex = LastScope.FailIndex;
3140 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3142 InputChain = LastScope.InputChain;
3143 InputGlue = LastScope.InputGlue;
3144 if (!LastScope.HasChainNodesMatched)
3145 ChainNodesMatched.clear();
3146 if (!LastScope.HasGlueResultNodesMatched)
3147 GlueResultNodesMatched.clear();
3149 // Check to see what the offset is at the new MatcherIndex. If it is zero
3150 // we have reached the end of this scope, otherwise we have another child
3151 // in the current scope to try.
3152 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3153 if (NumToSkip & 128)
3154 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3156 // If we have another child in this scope to match, update FailIndex and
3158 if (NumToSkip != 0) {
3159 LastScope.FailIndex = MatcherIndex+NumToSkip;
3163 // End of this scope, pop it and try the next child in the containing
3165 MatchScopes.pop_back();
3172 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3174 raw_string_ostream Msg(msg);
3175 Msg << "Cannot select: ";
3177 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3178 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3179 N->getOpcode() != ISD::INTRINSIC_VOID) {
3180 N->printrFull(Msg, CurDAG);
3181 Msg << "\nIn function: " << MF->getName();
3183 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3185 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3186 if (iid < Intrinsic::num_intrinsics)
3187 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3188 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3189 Msg << "target intrinsic %" << TII->getName(iid);
3191 Msg << "unknown intrinsic #" << iid;
3193 report_fatal_error(Msg.str());
3196 char SelectionDAGISel::ID = 0;