1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAGISel.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/FunctionLoweringInfo.h"
24 #include "llvm/CodeGen/GCMetadata.h"
25 #include "llvm/CodeGen/GCStrategy.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
32 #include "llvm/CodeGen/SchedulerRegistry.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DebugInfo.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/InlineAsm.h"
38 #include "llvm/IR/Instructions.h"
39 #include "llvm/IR/IntrinsicInst.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/IR/Module.h"
43 #include "llvm/Support/Compiler.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/Timer.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLibraryInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetMachine.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "llvm/Target/TargetRegisterInfo.h"
55 #include "llvm/Target/TargetSubtargetInfo.h"
56 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
60 #define DEBUG_TYPE "isel"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
64 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
65 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
66 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
68 STATISTIC(NumFastIselFailLowerArguments,
69 "Number of entry blocks where fast isel failed to lower arguments");
73 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
74 cl::desc("Enable extra verbose messages in the \"fast\" "
75 "instruction selector"));
78 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
79 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
80 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
81 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
82 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
83 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
84 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
86 // Standard binary operators...
87 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
88 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
89 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
90 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
91 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
92 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
93 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
94 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
95 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
96 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
97 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
98 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
100 // Logical operators...
101 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
102 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
103 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
105 // Memory instructions...
106 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
107 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
108 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
109 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
110 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
111 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
112 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
114 // Convert instructions...
115 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
116 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
117 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
118 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
119 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
120 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
121 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
122 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
123 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
124 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
125 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
126 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
128 // Other instructions...
129 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
130 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
131 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
132 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
133 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
134 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
135 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
136 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
137 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
138 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
139 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
140 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
141 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
142 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
143 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
145 // Intrinsic instructions...
146 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
147 STATISTIC(NumFastIselFailSAddWithOverflow,
148 "Fast isel fails on sadd.with.overflow");
149 STATISTIC(NumFastIselFailUAddWithOverflow,
150 "Fast isel fails on uadd.with.overflow");
151 STATISTIC(NumFastIselFailSSubWithOverflow,
152 "Fast isel fails on ssub.with.overflow");
153 STATISTIC(NumFastIselFailUSubWithOverflow,
154 "Fast isel fails on usub.with.overflow");
155 STATISTIC(NumFastIselFailSMulWithOverflow,
156 "Fast isel fails on smul.with.overflow");
157 STATISTIC(NumFastIselFailUMulWithOverflow,
158 "Fast isel fails on umul.with.overflow");
159 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
160 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
161 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
162 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
166 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
167 cl::desc("Enable verbose messages in the \"fast\" "
168 "instruction selector"));
170 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
171 cl::desc("Enable abort calls when \"fast\" instruction selection "
172 "fails to lower an instruction"));
174 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
175 cl::desc("Enable abort calls when \"fast\" instruction selection "
176 "fails to lower a formal argument"));
180 cl::desc("use Machine Branch Probability Info"),
181 cl::init(true), cl::Hidden);
185 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
186 cl::desc("Pop up a window to show dags before the first "
187 "dag combine pass"));
189 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
190 cl::desc("Pop up a window to show dags before legalize types"));
192 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
193 cl::desc("Pop up a window to show dags before legalize"));
195 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before the second "
197 "dag combine pass"));
199 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
200 cl::desc("Pop up a window to show dags before the post legalize types"
201 " dag combine pass"));
203 ViewISelDAGs("view-isel-dags", cl::Hidden,
204 cl::desc("Pop up a window to show isel dags as they are selected"));
206 ViewSchedDAGs("view-sched-dags", cl::Hidden,
207 cl::desc("Pop up a window to show sched dags as they are processed"));
209 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
210 cl::desc("Pop up a window to show SUnit dags after they are processed"));
212 static const bool ViewDAGCombine1 = false,
213 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
214 ViewDAGCombine2 = false,
215 ViewDAGCombineLT = false,
216 ViewISelDAGs = false, ViewSchedDAGs = false,
217 ViewSUnitDAGs = false;
220 //===---------------------------------------------------------------------===//
222 /// RegisterScheduler class - Track the registration of instruction schedulers.
224 //===---------------------------------------------------------------------===//
225 MachinePassRegistry RegisterScheduler::Registry;
227 //===---------------------------------------------------------------------===//
229 /// ISHeuristic command line option for instruction schedulers.
231 //===---------------------------------------------------------------------===//
232 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
233 RegisterPassParser<RegisterScheduler> >
234 ISHeuristic("pre-RA-sched",
235 cl::init(&createDefaultScheduler), cl::Hidden,
236 cl::desc("Instruction schedulers available (before register"
239 static RegisterScheduler
240 defaultListDAGScheduler("default", "Best scheduler for the target",
241 createDefaultScheduler);
244 //===--------------------------------------------------------------------===//
245 /// \brief This class is used by SelectionDAGISel to temporarily override
246 /// the optimization level on a per-function basis.
247 class OptLevelChanger {
248 SelectionDAGISel &IS;
249 CodeGenOpt::Level SavedOptLevel;
253 OptLevelChanger(SelectionDAGISel &ISel,
254 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
255 SavedOptLevel = IS.OptLevel;
256 if (NewOptLevel == SavedOptLevel)
258 IS.OptLevel = NewOptLevel;
259 IS.TM.setOptLevel(NewOptLevel);
260 SavedFastISel = IS.TM.Options.EnableFastISel;
261 if (NewOptLevel == CodeGenOpt::None)
262 IS.TM.setFastISel(true);
263 DEBUG(dbgs() << "\nChanging optimization level for Function "
264 << IS.MF->getFunction()->getName() << "\n");
265 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
266 << " ; After: -O" << NewOptLevel << "\n");
270 if (IS.OptLevel == SavedOptLevel)
272 DEBUG(dbgs() << "\nRestoring optimization level for Function "
273 << IS.MF->getFunction()->getName() << "\n");
274 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
275 << " ; After: -O" << SavedOptLevel << "\n");
276 IS.OptLevel = SavedOptLevel;
277 IS.TM.setOptLevel(SavedOptLevel);
278 IS.TM.setFastISel(SavedFastISel);
282 //===--------------------------------------------------------------------===//
283 /// createDefaultScheduler - This creates an instruction scheduler appropriate
285 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
286 CodeGenOpt::Level OptLevel) {
287 const TargetLowering *TLI = IS->TLI;
288 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
290 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
291 TLI->getSchedulingPreference() == Sched::Source)
292 return createSourceListDAGScheduler(IS, OptLevel);
293 if (TLI->getSchedulingPreference() == Sched::RegPressure)
294 return createBURRListDAGScheduler(IS, OptLevel);
295 if (TLI->getSchedulingPreference() == Sched::Hybrid)
296 return createHybridListDAGScheduler(IS, OptLevel);
297 if (TLI->getSchedulingPreference() == Sched::VLIW)
298 return createVLIWDAGScheduler(IS, OptLevel);
299 assert(TLI->getSchedulingPreference() == Sched::ILP &&
300 "Unknown sched type!");
301 return createILPListDAGScheduler(IS, OptLevel);
305 // EmitInstrWithCustomInserter - This method should be implemented by targets
306 // that mark instructions with the 'usesCustomInserter' flag. These
307 // instructions are special in various ways, which require special support to
308 // insert. The specified MachineInstr is created but not inserted into any
309 // basic blocks, and this method is called to expand it into a sequence of
310 // instructions, potentially also creating new basic blocks and control flow.
311 // When new basic blocks are inserted and the edges from MBB to its successors
312 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
315 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
316 MachineBasicBlock *MBB) const {
318 dbgs() << "If a target marks an instruction with "
319 "'usesCustomInserter', it must implement "
320 "TargetLowering::EmitInstrWithCustomInserter!";
322 llvm_unreachable(nullptr);
325 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
326 SDNode *Node) const {
327 assert(!MI->hasPostISelHook() &&
328 "If a target marks an instruction with 'hasPostISelHook', "
329 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
332 //===----------------------------------------------------------------------===//
333 // SelectionDAGISel code
334 //===----------------------------------------------------------------------===//
336 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
337 CodeGenOpt::Level OL) :
338 MachineFunctionPass(ID), TM(tm),
339 FuncInfo(new FunctionLoweringInfo()),
340 CurDAG(new SelectionDAG(tm, OL)),
341 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
345 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
346 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
347 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
348 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
351 SelectionDAGISel::~SelectionDAGISel() {
357 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
358 AU.addRequired<AliasAnalysis>();
359 AU.addPreserved<AliasAnalysis>();
360 AU.addRequired<GCModuleInfo>();
361 AU.addPreserved<GCModuleInfo>();
362 AU.addRequired<TargetLibraryInfo>();
363 if (UseMBPI && OptLevel != CodeGenOpt::None)
364 AU.addRequired<BranchProbabilityInfo>();
365 MachineFunctionPass::getAnalysisUsage(AU);
368 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
369 /// may trap on it. In this case we have to split the edge so that the path
370 /// through the predecessor block that doesn't go to the phi block doesn't
371 /// execute the possibly trapping instruction.
373 /// This is required for correctness, so it must be done at -O0.
375 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
376 // Loop for blocks with phi nodes.
377 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
378 PHINode *PN = dyn_cast<PHINode>(BB->begin());
382 // For each block with a PHI node, check to see if any of the input values
383 // are potentially trapping constant expressions. Constant expressions are
384 // the only potentially trapping value that can occur as the argument to a
386 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
387 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
388 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
389 if (!CE || !CE->canTrap()) continue;
391 // The only case we have to worry about is when the edge is critical.
392 // Since this block has a PHI Node, we assume it has multiple input
393 // edges: check to see if the pred has multiple successors.
394 BasicBlock *Pred = PN->getIncomingBlock(i);
395 if (Pred->getTerminator()->getNumSuccessors() == 1)
398 // Okay, we have to split this edge.
399 SplitCriticalEdge(Pred->getTerminator(),
400 GetSuccessorNumber(Pred, BB), SDISel, true);
406 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
407 // Do some sanity-checking on the command-line options.
408 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
409 "-fast-isel-verbose requires -fast-isel");
410 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
411 "-fast-isel-abort requires -fast-isel");
413 const Function &Fn = *mf.getFunction();
416 // Reset the target options before resetting the optimization
418 // FIXME: This is a horrible hack and should be processed via
419 // codegen looking at the optimization level explicitly when
420 // it wants to look at it.
421 TM.resetTargetOptions(Fn);
422 // Reset OptLevel to None for optnone functions.
423 CodeGenOpt::Level NewOptLevel = OptLevel;
424 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
425 NewOptLevel = CodeGenOpt::None;
426 OptLevelChanger OLC(*this, NewOptLevel);
428 TII = MF->getSubtarget().getInstrInfo();
429 TLI = MF->getSubtarget().getTargetLowering();
430 RegInfo = &MF->getRegInfo();
431 AA = &getAnalysis<AliasAnalysis>();
432 LibInfo = &getAnalysis<TargetLibraryInfo>();
433 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
435 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
437 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
440 FuncInfo->set(Fn, *MF, CurDAG);
442 if (UseMBPI && OptLevel != CodeGenOpt::None)
443 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
445 FuncInfo->BPI = nullptr;
447 SDB->init(GFI, *AA, LibInfo);
449 MF->setHasInlineAsm(false);
451 SelectAllBasicBlocks(Fn);
453 // If the first basic block in the function has live ins that need to be
454 // copied into vregs, emit the copies into the top of the block before
455 // emitting the code for the block.
456 MachineBasicBlock *EntryMBB = MF->begin();
457 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
458 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
460 DenseMap<unsigned, unsigned> LiveInMap;
461 if (!FuncInfo->ArgDbgValues.empty())
462 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
463 E = RegInfo->livein_end(); LI != E; ++LI)
465 LiveInMap.insert(std::make_pair(LI->first, LI->second));
467 // Insert DBG_VALUE instructions for function arguments to the entry block.
468 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
469 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
470 bool hasFI = MI->getOperand(0).isFI();
472 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
473 if (TargetRegisterInfo::isPhysicalRegister(Reg))
474 EntryMBB->insert(EntryMBB->begin(), MI);
476 MachineInstr *Def = RegInfo->getVRegDef(Reg);
478 MachineBasicBlock::iterator InsertPos = Def;
479 // FIXME: VR def may not be in entry block.
480 Def->getParent()->insert(std::next(InsertPos), MI);
482 DEBUG(dbgs() << "Dropping debug info for dead vreg"
483 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
486 // If Reg is live-in then update debug info to track its copy in a vreg.
487 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
488 if (LDI != LiveInMap.end()) {
489 assert(!hasFI && "There's no handling of frame pointer updating here yet "
491 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
492 MachineBasicBlock::iterator InsertPos = Def;
493 const MDNode *Variable = MI->getDebugVariable();
494 const MDNode *Expr = MI->getDebugExpression();
495 bool IsIndirect = MI->isIndirectDebugValue();
496 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
497 // Def is never a terminator here, so it is ok to increment InsertPos.
498 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
499 TII->get(TargetOpcode::DBG_VALUE), IsIndirect, LDI->second, Offset,
502 // If this vreg is directly copied into an exported register then
503 // that COPY instructions also need DBG_VALUE, if it is the only
504 // user of LDI->second.
505 MachineInstr *CopyUseMI = nullptr;
506 for (MachineRegisterInfo::use_instr_iterator
507 UI = RegInfo->use_instr_begin(LDI->second),
508 E = RegInfo->use_instr_end(); UI != E; ) {
509 MachineInstr *UseMI = &*(UI++);
510 if (UseMI->isDebugValue()) continue;
511 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
512 CopyUseMI = UseMI; continue;
514 // Otherwise this is another use or second copy use.
515 CopyUseMI = nullptr; break;
518 MachineInstr *NewMI =
519 BuildMI(*MF, CopyUseMI->getDebugLoc(),
520 TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
521 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
522 MachineBasicBlock::iterator Pos = CopyUseMI;
523 EntryMBB->insertAfter(Pos, NewMI);
528 // Determine if there are any calls in this machine function.
529 MachineFrameInfo *MFI = MF->getFrameInfo();
530 for (const auto &MBB : *MF) {
531 if (MFI->hasCalls() && MF->hasInlineAsm())
534 for (const auto &MI : MBB) {
535 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
536 if ((MCID.isCall() && !MCID.isReturn()) ||
537 MI.isStackAligningInlineAsm()) {
538 MFI->setHasCalls(true);
540 if (MI.isInlineAsm()) {
541 MF->setHasInlineAsm(true);
546 // Determine if there is a call to setjmp in the machine function.
547 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
549 // Replace forward-declared registers with the registers containing
550 // the desired value.
551 MachineRegisterInfo &MRI = MF->getRegInfo();
552 for (DenseMap<unsigned, unsigned>::iterator
553 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
555 unsigned From = I->first;
556 unsigned To = I->second;
557 // If To is also scheduled to be replaced, find what its ultimate
560 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
564 // Make sure the new register has a sufficiently constrained register class.
565 if (TargetRegisterInfo::isVirtualRegister(From) &&
566 TargetRegisterInfo::isVirtualRegister(To))
567 MRI.constrainRegClass(To, MRI.getRegClass(From));
569 MRI.replaceRegWith(From, To);
572 // Freeze the set of reserved registers now that MachineFrameInfo has been
573 // set up. All the information required by getReservedRegs() should be
575 MRI.freezeReservedRegs(*MF);
577 // Release function-specific state. SDB and CurDAG are already cleared
581 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
582 DEBUG(MF->print(dbgs()));
587 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
588 BasicBlock::const_iterator End,
590 // Lower all of the non-terminator instructions. If a call is emitted
591 // as a tail call, cease emitting nodes for this block. Terminators
592 // are handled below.
593 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
596 // Make sure the root of the DAG is up-to-date.
597 CurDAG->setRoot(SDB->getControlRoot());
598 HadTailCall = SDB->HasTailCall;
601 // Final step, emit the lowered DAG as machine code.
605 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
606 SmallPtrSet<SDNode*, 128> VisitedNodes;
607 SmallVector<SDNode*, 128> Worklist;
609 Worklist.push_back(CurDAG->getRoot().getNode());
615 SDNode *N = Worklist.pop_back_val();
617 // If we've already seen this node, ignore it.
618 if (!VisitedNodes.insert(N).second)
621 // Otherwise, add all chain operands to the worklist.
622 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
623 if (N->getOperand(i).getValueType() == MVT::Other)
624 Worklist.push_back(N->getOperand(i).getNode());
626 // If this is a CopyToReg with a vreg dest, process it.
627 if (N->getOpcode() != ISD::CopyToReg)
630 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
631 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
634 // Ignore non-scalar or non-integer values.
635 SDValue Src = N->getOperand(2);
636 EVT SrcVT = Src.getValueType();
637 if (!SrcVT.isInteger() || SrcVT.isVector())
640 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
641 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
642 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
643 } while (!Worklist.empty());
646 void SelectionDAGISel::CodeGenAndEmitDAG() {
647 std::string GroupName;
648 if (TimePassesIsEnabled)
649 GroupName = "Instruction Selection and Scheduling";
650 std::string BlockName;
651 int BlockNumber = -1;
654 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
655 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
659 BlockNumber = FuncInfo->MBB->getNumber();
660 BlockName = MF->getName().str() + ":" +
661 FuncInfo->MBB->getBasicBlock()->getName().str();
663 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
664 << " '" << BlockName << "'\n"; CurDAG->dump());
666 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
668 // Run the DAG combiner in pre-legalize mode.
670 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
671 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
674 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
675 << " '" << BlockName << "'\n"; CurDAG->dump());
677 // Second step, hack on the DAG until it only uses operations and types that
678 // the target supports.
679 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
684 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
685 Changed = CurDAG->LegalizeTypes();
688 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
689 << " '" << BlockName << "'\n"; CurDAG->dump());
691 CurDAG->NewNodesMustHaveLegalTypes = true;
694 if (ViewDAGCombineLT)
695 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
697 // Run the DAG combiner in post-type-legalize mode.
699 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
700 TimePassesIsEnabled);
701 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
704 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
705 << " '" << BlockName << "'\n"; CurDAG->dump());
710 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
711 Changed = CurDAG->LegalizeVectors();
716 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
717 CurDAG->LegalizeTypes();
720 if (ViewDAGCombineLT)
721 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
723 // Run the DAG combiner in post-type-legalize mode.
725 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
726 TimePassesIsEnabled);
727 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
730 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
731 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
734 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
737 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
741 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
742 << " '" << BlockName << "'\n"; CurDAG->dump());
744 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
746 // Run the DAG combiner in post-legalize mode.
748 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
749 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
752 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
753 << " '" << BlockName << "'\n"; CurDAG->dump());
755 if (OptLevel != CodeGenOpt::None)
756 ComputeLiveOutVRegInfo();
758 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
760 // Third, instruction select all of the operations to machine code, adding the
761 // code to the MachineBasicBlock.
763 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
764 DoInstructionSelection();
767 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
768 << " '" << BlockName << "'\n"; CurDAG->dump());
770 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
772 // Schedule machine code.
773 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
775 NamedRegionTimer T("Instruction Scheduling", GroupName,
776 TimePassesIsEnabled);
777 Scheduler->Run(CurDAG, FuncInfo->MBB);
780 if (ViewSUnitDAGs) Scheduler->viewGraph();
782 // Emit machine code to BB. This can change 'BB' to the last block being
784 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
786 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
788 // FuncInfo->InsertPt is passed by reference and set to the end of the
789 // scheduled instructions.
790 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
793 // If the block was split, make sure we update any references that are used to
794 // update PHI nodes later on.
795 if (FirstMBB != LastMBB)
796 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
798 // Free the scheduler state.
800 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
801 TimePassesIsEnabled);
805 // Free the SelectionDAG state, now that we're finished with it.
810 /// ISelUpdater - helper class to handle updates of the instruction selection
812 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
813 SelectionDAG::allnodes_iterator &ISelPosition;
815 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
816 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
818 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
819 /// deleted is the current ISelPosition node, update ISelPosition.
821 void NodeDeleted(SDNode *N, SDNode *E) override {
822 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
826 } // end anonymous namespace
828 void SelectionDAGISel::DoInstructionSelection() {
829 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
830 << FuncInfo->MBB->getNumber()
831 << " '" << FuncInfo->MBB->getName() << "'\n");
835 // Select target instructions for the DAG.
837 // Number all nodes with a topological order and set DAGSize.
838 DAGSize = CurDAG->AssignTopologicalOrder();
840 // Create a dummy node (which is not added to allnodes), that adds
841 // a reference to the root node, preventing it from being deleted,
842 // and tracking any changes of the root.
843 HandleSDNode Dummy(CurDAG->getRoot());
844 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
847 // Make sure that ISelPosition gets properly updated when nodes are deleted
848 // in calls made from this function.
849 ISelUpdater ISU(*CurDAG, ISelPosition);
851 // The AllNodes list is now topological-sorted. Visit the
852 // nodes by starting at the end of the list (the root of the
853 // graph) and preceding back toward the beginning (the entry
855 while (ISelPosition != CurDAG->allnodes_begin()) {
856 SDNode *Node = --ISelPosition;
857 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
858 // but there are currently some corner cases that it misses. Also, this
859 // makes it theoretically possible to disable the DAGCombiner.
860 if (Node->use_empty())
863 SDNode *ResNode = Select(Node);
865 // FIXME: This is pretty gross. 'Select' should be changed to not return
866 // anything at all and this code should be nuked with a tactical strike.
868 // If node should not be replaced, continue with the next one.
869 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
873 ReplaceUses(Node, ResNode);
876 // If after the replacement this node is not used any more,
877 // remove this dead node.
878 if (Node->use_empty()) // Don't delete EntryToken, etc.
879 CurDAG->RemoveDeadNode(Node);
882 CurDAG->setRoot(Dummy.getValue());
885 DEBUG(dbgs() << "===== Instruction selection ends:\n");
887 PostprocessISelDAG();
890 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
891 /// do other setup for EH landing-pad blocks.
892 void SelectionDAGISel::PrepareEHLandingPad() {
893 MachineBasicBlock *MBB = FuncInfo->MBB;
895 // Add a label to mark the beginning of the landing pad. Deletion of the
896 // landing pad can thus be detected via the MachineModuleInfo.
897 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
899 // Assign the call site to the landing pad's begin label.
900 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
902 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
903 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
906 // Mark exception register as live in.
907 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
908 if (unsigned Reg = TLI->getExceptionPointerRegister())
909 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
911 // Mark exception selector register as live in.
912 if (unsigned Reg = TLI->getExceptionSelectorRegister())
913 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
916 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
917 /// side-effect free and is either dead or folded into a generated instruction.
918 /// Return false if it needs to be emitted.
919 static bool isFoldedOrDeadInstruction(const Instruction *I,
920 FunctionLoweringInfo *FuncInfo) {
921 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
922 !isa<TerminatorInst>(I) && // Terminators aren't folded.
923 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
924 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
925 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
929 // Collect per Instruction statistics for fast-isel misses. Only those
930 // instructions that cause the bail are accounted for. It does not account for
931 // instructions higher in the block. Thus, summing the per instructions stats
932 // will not add up to what is reported by NumFastIselFailures.
933 static void collectFailStats(const Instruction *I) {
934 switch (I->getOpcode()) {
935 default: assert (0 && "<Invalid operator> ");
938 case Instruction::Ret: NumFastIselFailRet++; return;
939 case Instruction::Br: NumFastIselFailBr++; return;
940 case Instruction::Switch: NumFastIselFailSwitch++; return;
941 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
942 case Instruction::Invoke: NumFastIselFailInvoke++; return;
943 case Instruction::Resume: NumFastIselFailResume++; return;
944 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
946 // Standard binary operators...
947 case Instruction::Add: NumFastIselFailAdd++; return;
948 case Instruction::FAdd: NumFastIselFailFAdd++; return;
949 case Instruction::Sub: NumFastIselFailSub++; return;
950 case Instruction::FSub: NumFastIselFailFSub++; return;
951 case Instruction::Mul: NumFastIselFailMul++; return;
952 case Instruction::FMul: NumFastIselFailFMul++; return;
953 case Instruction::UDiv: NumFastIselFailUDiv++; return;
954 case Instruction::SDiv: NumFastIselFailSDiv++; return;
955 case Instruction::FDiv: NumFastIselFailFDiv++; return;
956 case Instruction::URem: NumFastIselFailURem++; return;
957 case Instruction::SRem: NumFastIselFailSRem++; return;
958 case Instruction::FRem: NumFastIselFailFRem++; return;
960 // Logical operators...
961 case Instruction::And: NumFastIselFailAnd++; return;
962 case Instruction::Or: NumFastIselFailOr++; return;
963 case Instruction::Xor: NumFastIselFailXor++; return;
965 // Memory instructions...
966 case Instruction::Alloca: NumFastIselFailAlloca++; return;
967 case Instruction::Load: NumFastIselFailLoad++; return;
968 case Instruction::Store: NumFastIselFailStore++; return;
969 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
970 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
971 case Instruction::Fence: NumFastIselFailFence++; return;
972 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
974 // Convert instructions...
975 case Instruction::Trunc: NumFastIselFailTrunc++; return;
976 case Instruction::ZExt: NumFastIselFailZExt++; return;
977 case Instruction::SExt: NumFastIselFailSExt++; return;
978 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
979 case Instruction::FPExt: NumFastIselFailFPExt++; return;
980 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
981 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
982 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
983 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
984 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
985 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
986 case Instruction::BitCast: NumFastIselFailBitCast++; return;
988 // Other instructions...
989 case Instruction::ICmp: NumFastIselFailICmp++; return;
990 case Instruction::FCmp: NumFastIselFailFCmp++; return;
991 case Instruction::PHI: NumFastIselFailPHI++; return;
992 case Instruction::Select: NumFastIselFailSelect++; return;
993 case Instruction::Call: {
994 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
995 switch (Intrinsic->getIntrinsicID()) {
997 NumFastIselFailIntrinsicCall++; return;
998 case Intrinsic::sadd_with_overflow:
999 NumFastIselFailSAddWithOverflow++; return;
1000 case Intrinsic::uadd_with_overflow:
1001 NumFastIselFailUAddWithOverflow++; return;
1002 case Intrinsic::ssub_with_overflow:
1003 NumFastIselFailSSubWithOverflow++; return;
1004 case Intrinsic::usub_with_overflow:
1005 NumFastIselFailUSubWithOverflow++; return;
1006 case Intrinsic::smul_with_overflow:
1007 NumFastIselFailSMulWithOverflow++; return;
1008 case Intrinsic::umul_with_overflow:
1009 NumFastIselFailUMulWithOverflow++; return;
1010 case Intrinsic::frameaddress:
1011 NumFastIselFailFrameaddress++; return;
1012 case Intrinsic::sqrt:
1013 NumFastIselFailSqrt++; return;
1014 case Intrinsic::experimental_stackmap:
1015 NumFastIselFailStackMap++; return;
1016 case Intrinsic::experimental_patchpoint_void: // fall-through
1017 case Intrinsic::experimental_patchpoint_i64:
1018 NumFastIselFailPatchPoint++; return;
1021 NumFastIselFailCall++;
1024 case Instruction::Shl: NumFastIselFailShl++; return;
1025 case Instruction::LShr: NumFastIselFailLShr++; return;
1026 case Instruction::AShr: NumFastIselFailAShr++; return;
1027 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1028 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1029 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1030 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1031 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1032 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1033 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1038 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1039 // Initialize the Fast-ISel state, if needed.
1040 FastISel *FastIS = nullptr;
1041 if (TM.Options.EnableFastISel)
1042 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1044 // Iterate over all basic blocks in the function.
1045 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1046 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1047 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1048 const BasicBlock *LLVMBB = *I;
1050 if (OptLevel != CodeGenOpt::None) {
1051 bool AllPredsVisited = true;
1052 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1054 if (!FuncInfo->VisitedBBs.count(*PI)) {
1055 AllPredsVisited = false;
1060 if (AllPredsVisited) {
1061 for (BasicBlock::const_iterator I = LLVMBB->begin();
1062 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1063 FuncInfo->ComputePHILiveOutRegInfo(PN);
1065 for (BasicBlock::const_iterator I = LLVMBB->begin();
1066 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1067 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1070 FuncInfo->VisitedBBs.insert(LLVMBB);
1073 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1074 BasicBlock::const_iterator const End = LLVMBB->end();
1075 BasicBlock::const_iterator BI = End;
1077 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1078 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1080 // Setup an EH landing-pad block.
1081 FuncInfo->ExceptionPointerVirtReg = 0;
1082 FuncInfo->ExceptionSelectorVirtReg = 0;
1083 if (FuncInfo->MBB->isLandingPad())
1084 PrepareEHLandingPad();
1086 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1088 FastIS->startNewBlock();
1090 // Emit code for any incoming arguments. This must happen before
1091 // beginning FastISel on the entry block.
1092 if (LLVMBB == &Fn.getEntryBlock()) {
1095 // Lower any arguments needed in this block if this is the entry block.
1096 if (!FastIS->lowerArguments()) {
1097 // Fast isel failed to lower these arguments
1098 ++NumFastIselFailLowerArguments;
1099 if (EnableFastISelAbortArgs)
1100 llvm_unreachable("FastISel didn't lower all arguments");
1102 // Use SelectionDAG argument lowering
1104 CurDAG->setRoot(SDB->getControlRoot());
1106 CodeGenAndEmitDAG();
1109 // If we inserted any instructions at the beginning, make a note of
1110 // where they are, so we can be sure to emit subsequent instructions
1112 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1113 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1115 FastIS->setLastLocalValue(nullptr);
1118 unsigned NumFastIselRemaining = std::distance(Begin, End);
1119 // Do FastISel on as many instructions as possible.
1120 for (; BI != Begin; --BI) {
1121 const Instruction *Inst = std::prev(BI);
1123 // If we no longer require this instruction, skip it.
1124 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1125 --NumFastIselRemaining;
1129 // Bottom-up: reset the insert pos at the top, after any local-value
1131 FastIS->recomputeInsertPt();
1133 // Try to select the instruction with FastISel.
1134 if (FastIS->selectInstruction(Inst)) {
1135 --NumFastIselRemaining;
1136 ++NumFastIselSuccess;
1137 // If fast isel succeeded, skip over all the folded instructions, and
1138 // then see if there is a load right before the selected instructions.
1139 // Try to fold the load if so.
1140 const Instruction *BeforeInst = Inst;
1141 while (BeforeInst != Begin) {
1142 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1143 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1146 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1147 BeforeInst->hasOneUse() &&
1148 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1149 // If we succeeded, don't re-select the load.
1150 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1151 --NumFastIselRemaining;
1152 ++NumFastIselSuccess;
1158 if (EnableFastISelVerbose2)
1159 collectFailStats(Inst);
1162 // Then handle certain instructions as single-LLVM-Instruction blocks.
1163 if (isa<CallInst>(Inst)) {
1165 if (EnableFastISelVerbose || EnableFastISelAbort) {
1166 dbgs() << "FastISel missed call: ";
1170 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1171 unsigned &R = FuncInfo->ValueMap[Inst];
1173 R = FuncInfo->CreateRegs(Inst->getType());
1176 bool HadTailCall = false;
1177 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1178 SelectBasicBlock(Inst, BI, HadTailCall);
1180 // If the call was emitted as a tail call, we're done with the block.
1181 // We also need to delete any previously emitted instructions.
1183 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1188 // Recompute NumFastIselRemaining as Selection DAG instruction
1189 // selection may have handled the call, input args, etc.
1190 unsigned RemainingNow = std::distance(Begin, BI);
1191 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1192 NumFastIselRemaining = RemainingNow;
1196 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1197 // Don't abort, and use a different message for terminator misses.
1198 NumFastIselFailures += NumFastIselRemaining;
1199 if (EnableFastISelVerbose || EnableFastISelAbort) {
1200 dbgs() << "FastISel missed terminator: ";
1204 NumFastIselFailures += NumFastIselRemaining;
1205 if (EnableFastISelVerbose || EnableFastISelAbort) {
1206 dbgs() << "FastISel miss: ";
1209 if (EnableFastISelAbort)
1210 // The "fast" selector couldn't handle something and bailed.
1211 // For the purpose of debugging, just abort.
1212 llvm_unreachable("FastISel didn't select the entire block");
1217 FastIS->recomputeInsertPt();
1219 // Lower any arguments needed in this block if this is the entry block.
1220 if (LLVMBB == &Fn.getEntryBlock()) {
1229 ++NumFastIselBlocks;
1232 // Run SelectionDAG instruction selection on the remainder of the block
1233 // not handled by FastISel. If FastISel is not run, this is the entire
1236 SelectBasicBlock(Begin, BI, HadTailCall);
1240 FuncInfo->PHINodesToUpdate.clear();
1244 SDB->clearDanglingDebugInfo();
1245 SDB->SPDescriptor.resetPerFunctionState();
1248 /// Given that the input MI is before a partial terminator sequence TSeq, return
1249 /// true if M + TSeq also a partial terminator sequence.
1251 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1252 /// lowering copy vregs into physical registers, which are then passed into
1253 /// terminator instructors so we can satisfy ABI constraints. A partial
1254 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1255 /// may be the whole terminator sequence).
1256 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1257 // If we do not have a copy or an implicit def, we return true if and only if
1258 // MI is a debug value.
1259 if (!MI->isCopy() && !MI->isImplicitDef())
1260 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1261 // physical registers if there is debug info associated with the terminator
1262 // of our mbb. We want to include said debug info in our terminator
1263 // sequence, so we return true in that case.
1264 return MI->isDebugValue();
1266 // We have left the terminator sequence if we are not doing one of the
1269 // 1. Copying a vreg into a physical register.
1270 // 2. Copying a vreg into a vreg.
1271 // 3. Defining a register via an implicit def.
1273 // OPI should always be a register definition...
1274 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1275 if (!OPI->isReg() || !OPI->isDef())
1278 // Defining any register via an implicit def is always ok.
1279 if (MI->isImplicitDef())
1282 // Grab the copy source...
1283 MachineInstr::const_mop_iterator OPI2 = OPI;
1285 assert(OPI2 != MI->operands_end()
1286 && "Should have a copy implying we should have 2 arguments.");
1288 // Make sure that the copy dest is not a vreg when the copy source is a
1289 // physical register.
1290 if (!OPI2->isReg() ||
1291 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1292 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1298 /// Find the split point at which to splice the end of BB into its success stack
1299 /// protector check machine basic block.
1301 /// On many platforms, due to ABI constraints, terminators, even before register
1302 /// allocation, use physical registers. This creates an issue for us since
1303 /// physical registers at this point can not travel across basic
1304 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1305 /// when they enter functions and moves them through a sequence of copies back
1306 /// into the physical registers right before the terminator creating a
1307 /// ``Terminator Sequence''. This function is searching for the beginning of the
1308 /// terminator sequence so that we can ensure that we splice off not just the
1309 /// terminator, but additionally the copies that move the vregs into the
1310 /// physical registers.
1311 static MachineBasicBlock::iterator
1312 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1313 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1315 if (SplitPoint == BB->begin())
1318 MachineBasicBlock::iterator Start = BB->begin();
1319 MachineBasicBlock::iterator Previous = SplitPoint;
1322 while (MIIsInTerminatorSequence(Previous)) {
1323 SplitPoint = Previous;
1324 if (Previous == Start)
1333 SelectionDAGISel::FinishBasicBlock() {
1335 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1336 << FuncInfo->PHINodesToUpdate.size() << "\n";
1337 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1338 dbgs() << "Node " << i << " : ("
1339 << FuncInfo->PHINodesToUpdate[i].first
1340 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1342 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1343 SDB->JTCases.empty() &&
1344 SDB->BitTestCases.empty();
1346 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1347 // PHI nodes in successors.
1348 if (MustUpdatePHINodes) {
1349 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1350 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1351 assert(PHI->isPHI() &&
1352 "This is not a machine PHI node that we are updating!");
1353 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1355 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1359 // Handle stack protector.
1360 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1361 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1362 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1364 // Find the split point to split the parent mbb. At the same time copy all
1365 // physical registers used in the tail of parent mbb into virtual registers
1366 // before the split point and back into physical registers after the split
1367 // point. This prevents us needing to deal with Live-ins and many other
1368 // register allocation issues caused by us splitting the parent mbb. The
1369 // register allocator will clean up said virtual copies later on.
1370 MachineBasicBlock::iterator SplitPoint =
1371 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1373 // Splice the terminator of ParentMBB into SuccessMBB.
1374 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1378 // Add compare/jump on neq/jump to the parent BB.
1379 FuncInfo->MBB = ParentMBB;
1380 FuncInfo->InsertPt = ParentMBB->end();
1381 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1382 CurDAG->setRoot(SDB->getRoot());
1384 CodeGenAndEmitDAG();
1386 // CodeGen Failure MBB if we have not codegened it yet.
1387 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1388 if (!FailureMBB->size()) {
1389 FuncInfo->MBB = FailureMBB;
1390 FuncInfo->InsertPt = FailureMBB->end();
1391 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1392 CurDAG->setRoot(SDB->getRoot());
1394 CodeGenAndEmitDAG();
1397 // Clear the Per-BB State.
1398 SDB->SPDescriptor.resetPerBBState();
1401 // If we updated PHI Nodes, return early.
1402 if (MustUpdatePHINodes)
1405 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1406 // Lower header first, if it wasn't already lowered
1407 if (!SDB->BitTestCases[i].Emitted) {
1408 // Set the current basic block to the mbb we wish to insert the code into
1409 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1410 FuncInfo->InsertPt = FuncInfo->MBB->end();
1412 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1413 CurDAG->setRoot(SDB->getRoot());
1415 CodeGenAndEmitDAG();
1418 uint32_t UnhandledWeight = 0;
1419 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1420 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1422 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1423 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1424 // Set the current basic block to the mbb we wish to insert the code into
1425 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1426 FuncInfo->InsertPt = FuncInfo->MBB->end();
1429 SDB->visitBitTestCase(SDB->BitTestCases[i],
1430 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1432 SDB->BitTestCases[i].Reg,
1433 SDB->BitTestCases[i].Cases[j],
1436 SDB->visitBitTestCase(SDB->BitTestCases[i],
1437 SDB->BitTestCases[i].Default,
1439 SDB->BitTestCases[i].Reg,
1440 SDB->BitTestCases[i].Cases[j],
1444 CurDAG->setRoot(SDB->getRoot());
1446 CodeGenAndEmitDAG();
1450 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1452 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1453 MachineBasicBlock *PHIBB = PHI->getParent();
1454 assert(PHI->isPHI() &&
1455 "This is not a machine PHI node that we are updating!");
1456 // This is "default" BB. We have two jumps to it. From "header" BB and
1457 // from last "case" BB.
1458 if (PHIBB == SDB->BitTestCases[i].Default)
1459 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1460 .addMBB(SDB->BitTestCases[i].Parent)
1461 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1462 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1463 // One of "cases" BB.
1464 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1466 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1467 if (cBB->isSuccessor(PHIBB))
1468 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1472 SDB->BitTestCases.clear();
1474 // If the JumpTable record is filled in, then we need to emit a jump table.
1475 // Updating the PHI nodes is tricky in this case, since we need to determine
1476 // whether the PHI is a successor of the range check MBB or the jump table MBB
1477 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1478 // Lower header first, if it wasn't already lowered
1479 if (!SDB->JTCases[i].first.Emitted) {
1480 // Set the current basic block to the mbb we wish to insert the code into
1481 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1482 FuncInfo->InsertPt = FuncInfo->MBB->end();
1484 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1486 CurDAG->setRoot(SDB->getRoot());
1488 CodeGenAndEmitDAG();
1491 // Set the current basic block to the mbb we wish to insert the code into
1492 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1493 FuncInfo->InsertPt = FuncInfo->MBB->end();
1495 SDB->visitJumpTable(SDB->JTCases[i].second);
1496 CurDAG->setRoot(SDB->getRoot());
1498 CodeGenAndEmitDAG();
1501 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1503 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1504 MachineBasicBlock *PHIBB = PHI->getParent();
1505 assert(PHI->isPHI() &&
1506 "This is not a machine PHI node that we are updating!");
1507 // "default" BB. We can go there only from header BB.
1508 if (PHIBB == SDB->JTCases[i].second.Default)
1509 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1510 .addMBB(SDB->JTCases[i].first.HeaderBB);
1511 // JT BB. Just iterate over successors here
1512 if (FuncInfo->MBB->isSuccessor(PHIBB))
1513 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1516 SDB->JTCases.clear();
1518 // If the switch block involved a branch to one of the actual successors, we
1519 // need to update PHI nodes in that block.
1520 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1521 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1522 assert(PHI->isPHI() &&
1523 "This is not a machine PHI node that we are updating!");
1524 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1525 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1528 // If we generated any switch lowering information, build and codegen any
1529 // additional DAGs necessary.
1530 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1531 // Set the current basic block to the mbb we wish to insert the code into
1532 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1533 FuncInfo->InsertPt = FuncInfo->MBB->end();
1535 // Determine the unique successors.
1536 SmallVector<MachineBasicBlock *, 2> Succs;
1537 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1538 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1539 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1541 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1542 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1543 CurDAG->setRoot(SDB->getRoot());
1545 CodeGenAndEmitDAG();
1547 // Remember the last block, now that any splitting is done, for use in
1548 // populating PHI nodes in successors.
1549 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1551 // Handle any PHI nodes in successors of this chunk, as if we were coming
1552 // from the original BB before switch expansion. Note that PHI nodes can
1553 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1554 // handle them the right number of times.
1555 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1556 FuncInfo->MBB = Succs[i];
1557 FuncInfo->InsertPt = FuncInfo->MBB->end();
1558 // FuncInfo->MBB may have been removed from the CFG if a branch was
1560 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1561 for (MachineBasicBlock::iterator
1562 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1563 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1564 MachineInstrBuilder PHI(*MF, MBBI);
1565 // This value for this PHI node is recorded in PHINodesToUpdate.
1566 for (unsigned pn = 0; ; ++pn) {
1567 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1568 "Didn't find PHI entry!");
1569 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1570 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1578 SDB->SwitchCases.clear();
1582 /// Create the scheduler. If a specific scheduler was specified
1583 /// via the SchedulerRegistry, use it, otherwise select the
1584 /// one preferred by the target.
1586 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1587 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1591 RegisterScheduler::setDefault(Ctor);
1594 return Ctor(this, OptLevel);
1597 //===----------------------------------------------------------------------===//
1598 // Helper functions used by the generated instruction selector.
1599 //===----------------------------------------------------------------------===//
1600 // Calls to these methods are generated by tblgen.
1602 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1603 /// the dag combiner simplified the 255, we still want to match. RHS is the
1604 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1605 /// specified in the .td file (e.g. 255).
1606 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1607 int64_t DesiredMaskS) const {
1608 const APInt &ActualMask = RHS->getAPIntValue();
1609 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1611 // If the actual mask exactly matches, success!
1612 if (ActualMask == DesiredMask)
1615 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1616 if (ActualMask.intersects(~DesiredMask))
1619 // Otherwise, the DAG Combiner may have proven that the value coming in is
1620 // either already zero or is not demanded. Check for known zero input bits.
1621 APInt NeededMask = DesiredMask & ~ActualMask;
1622 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1625 // TODO: check to see if missing bits are just not demanded.
1627 // Otherwise, this pattern doesn't match.
1631 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1632 /// the dag combiner simplified the 255, we still want to match. RHS is the
1633 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1634 /// specified in the .td file (e.g. 255).
1635 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1636 int64_t DesiredMaskS) const {
1637 const APInt &ActualMask = RHS->getAPIntValue();
1638 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1640 // If the actual mask exactly matches, success!
1641 if (ActualMask == DesiredMask)
1644 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1645 if (ActualMask.intersects(~DesiredMask))
1648 // Otherwise, the DAG Combiner may have proven that the value coming in is
1649 // either already zero or is not demanded. Check for known zero input bits.
1650 APInt NeededMask = DesiredMask & ~ActualMask;
1652 APInt KnownZero, KnownOne;
1653 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1655 // If all the missing bits in the or are already known to be set, match!
1656 if ((NeededMask & KnownOne) == NeededMask)
1659 // TODO: check to see if missing bits are just not demanded.
1661 // Otherwise, this pattern doesn't match.
1666 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1667 /// by tblgen. Others should not call it.
1668 void SelectionDAGISel::
1669 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1670 std::vector<SDValue> InOps;
1671 std::swap(InOps, Ops);
1673 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1674 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1675 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1676 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1678 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1679 if (InOps[e-1].getValueType() == MVT::Glue)
1680 --e; // Don't process a glue operand if it is here.
1683 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1684 if (!InlineAsm::isMemKind(Flags)) {
1685 // Just skip over this operand, copying the operands verbatim.
1686 Ops.insert(Ops.end(), InOps.begin()+i,
1687 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1688 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1690 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1691 "Memory operand with multiple values?");
1692 // Otherwise, this is a memory operand. Ask the target to select it.
1693 std::vector<SDValue> SelOps;
1694 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1695 report_fatal_error("Could not match memory address. Inline asm"
1698 // Add this to the output node.
1700 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1701 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1702 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1707 // Add the glue input back if present.
1708 if (e != InOps.size())
1709 Ops.push_back(InOps.back());
1712 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1715 static SDNode *findGlueUse(SDNode *N) {
1716 unsigned FlagResNo = N->getNumValues()-1;
1717 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1718 SDUse &Use = I.getUse();
1719 if (Use.getResNo() == FlagResNo)
1720 return Use.getUser();
1725 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1726 /// This function recursively traverses up the operand chain, ignoring
1728 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1729 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1730 bool IgnoreChains) {
1731 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1732 // greater than all of its (recursive) operands. If we scan to a point where
1733 // 'use' is smaller than the node we're scanning for, then we know we will
1736 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1737 // happen because we scan down to newly selected nodes in the case of glue
1739 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1742 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1743 // won't fail if we scan it again.
1744 if (!Visited.insert(Use).second)
1747 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1748 // Ignore chain uses, they are validated by HandleMergeInputChains.
1749 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1752 SDNode *N = Use->getOperand(i).getNode();
1754 if (Use == ImmedUse || Use == Root)
1755 continue; // We are not looking for immediate use.
1760 // Traverse up the operand chain.
1761 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1767 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1768 /// operand node N of U during instruction selection that starts at Root.
1769 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1770 SDNode *Root) const {
1771 if (OptLevel == CodeGenOpt::None) return false;
1772 return N.hasOneUse();
1775 /// IsLegalToFold - Returns true if the specific operand node N of
1776 /// U can be folded during instruction selection that starts at Root.
1777 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1778 CodeGenOpt::Level OptLevel,
1779 bool IgnoreChains) {
1780 if (OptLevel == CodeGenOpt::None) return false;
1782 // If Root use can somehow reach N through a path that that doesn't contain
1783 // U then folding N would create a cycle. e.g. In the following
1784 // diagram, Root can reach N through X. If N is folded into into Root, then
1785 // X is both a predecessor and a successor of U.
1796 // * indicates nodes to be folded together.
1798 // If Root produces glue, then it gets (even more) interesting. Since it
1799 // will be "glued" together with its glue use in the scheduler, we need to
1800 // check if it might reach N.
1819 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1820 // (call it Fold), then X is a predecessor of GU and a successor of
1821 // Fold. But since Fold and GU are glued together, this will create
1822 // a cycle in the scheduling graph.
1824 // If the node has glue, walk down the graph to the "lowest" node in the
1826 EVT VT = Root->getValueType(Root->getNumValues()-1);
1827 while (VT == MVT::Glue) {
1828 SDNode *GU = findGlueUse(Root);
1832 VT = Root->getValueType(Root->getNumValues()-1);
1834 // If our query node has a glue result with a use, we've walked up it. If
1835 // the user (which has already been selected) has a chain or indirectly uses
1836 // the chain, our WalkChainUsers predicate will not consider it. Because of
1837 // this, we cannot ignore chains in this predicate.
1838 IgnoreChains = false;
1842 SmallPtrSet<SDNode*, 16> Visited;
1843 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1846 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1847 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1848 SelectInlineAsmMemoryOperands(Ops);
1850 EVT VTs[] = { MVT::Other, MVT::Glue };
1851 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
1853 return New.getNode();
1857 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1859 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
1860 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1862 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
1863 SDValue New = CurDAG->getCopyFromReg(
1864 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
1866 return New.getNode();
1870 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1872 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1873 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1874 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1875 Op->getOperand(2).getValueType());
1876 SDValue New = CurDAG->getCopyToReg(
1877 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
1879 return New.getNode();
1884 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1885 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1888 /// GetVBR - decode a vbr encoding whose top bit is set.
1889 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1890 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1891 assert(Val >= 128 && "Not a VBR");
1892 Val &= 127; // Remove first vbr bit.
1897 NextBits = MatcherTable[Idx++];
1898 Val |= (NextBits&127) << Shift;
1900 } while (NextBits & 128);
1906 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1907 /// interior glue and chain results to use the new glue and chain results.
1908 void SelectionDAGISel::
1909 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1910 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1912 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1913 bool isMorphNodeTo) {
1914 SmallVector<SDNode*, 4> NowDeadNodes;
1916 // Now that all the normal results are replaced, we replace the chain and
1917 // glue results if present.
1918 if (!ChainNodesMatched.empty()) {
1919 assert(InputChain.getNode() &&
1920 "Matched input chains but didn't produce a chain");
1921 // Loop over all of the nodes we matched that produced a chain result.
1922 // Replace all the chain results with the final chain we ended up with.
1923 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1924 SDNode *ChainNode = ChainNodesMatched[i];
1926 // If this node was already deleted, don't look at it.
1927 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1930 // Don't replace the results of the root node if we're doing a
1932 if (ChainNode == NodeToMatch && isMorphNodeTo)
1935 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1936 if (ChainVal.getValueType() == MVT::Glue)
1937 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1938 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1939 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1941 // If the node became dead and we haven't already seen it, delete it.
1942 if (ChainNode->use_empty() &&
1943 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1944 NowDeadNodes.push_back(ChainNode);
1948 // If the result produces glue, update any glue results in the matched
1949 // pattern with the glue result.
1950 if (InputGlue.getNode()) {
1951 // Handle any interior nodes explicitly marked.
1952 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1953 SDNode *FRN = GlueResultNodesMatched[i];
1955 // If this node was already deleted, don't look at it.
1956 if (FRN->getOpcode() == ISD::DELETED_NODE)
1959 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1960 "Doesn't have a glue result");
1961 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1964 // If the node became dead and we haven't already seen it, delete it.
1965 if (FRN->use_empty() &&
1966 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1967 NowDeadNodes.push_back(FRN);
1971 if (!NowDeadNodes.empty())
1972 CurDAG->RemoveDeadNodes(NowDeadNodes);
1974 DEBUG(dbgs() << "ISEL: Match complete!\n");
1980 CR_LeadsToInteriorNode
1983 /// WalkChainUsers - Walk down the users of the specified chained node that is
1984 /// part of the pattern we're matching, looking at all of the users we find.
1985 /// This determines whether something is an interior node, whether we have a
1986 /// non-pattern node in between two pattern nodes (which prevent folding because
1987 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1988 /// between pattern nodes (in which case the TF becomes part of the pattern).
1990 /// The walk we do here is guaranteed to be small because we quickly get down to
1991 /// already selected nodes "below" us.
1993 WalkChainUsers(const SDNode *ChainedNode,
1994 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1995 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1996 ChainResult Result = CR_Simple;
1998 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1999 E = ChainedNode->use_end(); UI != E; ++UI) {
2000 // Make sure the use is of the chain, not some other value we produce.
2001 if (UI.getUse().getValueType() != MVT::Other) continue;
2005 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2008 // If we see an already-selected machine node, then we've gone beyond the
2009 // pattern that we're selecting down into the already selected chunk of the
2011 unsigned UserOpcode = User->getOpcode();
2012 if (User->isMachineOpcode() ||
2013 UserOpcode == ISD::CopyToReg ||
2014 UserOpcode == ISD::CopyFromReg ||
2015 UserOpcode == ISD::INLINEASM ||
2016 UserOpcode == ISD::EH_LABEL ||
2017 UserOpcode == ISD::LIFETIME_START ||
2018 UserOpcode == ISD::LIFETIME_END) {
2019 // If their node ID got reset to -1 then they've already been selected.
2020 // Treat them like a MachineOpcode.
2021 if (User->getNodeId() == -1)
2025 // If we have a TokenFactor, we handle it specially.
2026 if (User->getOpcode() != ISD::TokenFactor) {
2027 // If the node isn't a token factor and isn't part of our pattern, then it
2028 // must be a random chained node in between two nodes we're selecting.
2029 // This happens when we have something like:
2034 // Because we structurally match the load/store as a read/modify/write,
2035 // but the call is chained between them. We cannot fold in this case
2036 // because it would induce a cycle in the graph.
2037 if (!std::count(ChainedNodesInPattern.begin(),
2038 ChainedNodesInPattern.end(), User))
2039 return CR_InducesCycle;
2041 // Otherwise we found a node that is part of our pattern. For example in:
2045 // This would happen when we're scanning down from the load and see the
2046 // store as a user. Record that there is a use of ChainedNode that is
2047 // part of the pattern and keep scanning uses.
2048 Result = CR_LeadsToInteriorNode;
2049 InteriorChainedNodes.push_back(User);
2053 // If we found a TokenFactor, there are two cases to consider: first if the
2054 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2055 // uses of the TF are in our pattern) we just want to ignore it. Second,
2056 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2062 // | \ DAG's like cheese
2065 // [TokenFactor] [Op]
2072 // In this case, the TokenFactor becomes part of our match and we rewrite it
2073 // as a new TokenFactor.
2075 // To distinguish these two cases, do a recursive walk down the uses.
2076 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2078 // If the uses of the TokenFactor are just already-selected nodes, ignore
2079 // it, it is "below" our pattern.
2081 case CR_InducesCycle:
2082 // If the uses of the TokenFactor lead to nodes that are not part of our
2083 // pattern that are not selected, folding would turn this into a cycle,
2085 return CR_InducesCycle;
2086 case CR_LeadsToInteriorNode:
2087 break; // Otherwise, keep processing.
2090 // Okay, we know we're in the interesting interior case. The TokenFactor
2091 // is now going to be considered part of the pattern so that we rewrite its
2092 // uses (it may have uses that are not part of the pattern) with the
2093 // ultimate chain result of the generated code. We will also add its chain
2094 // inputs as inputs to the ultimate TokenFactor we create.
2095 Result = CR_LeadsToInteriorNode;
2096 ChainedNodesInPattern.push_back(User);
2097 InteriorChainedNodes.push_back(User);
2104 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2105 /// operation for when the pattern matched at least one node with a chains. The
2106 /// input vector contains a list of all of the chained nodes that we match. We
2107 /// must determine if this is a valid thing to cover (i.e. matching it won't
2108 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2109 /// be used as the input node chain for the generated nodes.
2111 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2112 SelectionDAG *CurDAG) {
2113 // Walk all of the chained nodes we've matched, recursively scanning down the
2114 // users of the chain result. This adds any TokenFactor nodes that are caught
2115 // in between chained nodes to the chained and interior nodes list.
2116 SmallVector<SDNode*, 3> InteriorChainedNodes;
2117 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2118 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2119 InteriorChainedNodes) == CR_InducesCycle)
2120 return SDValue(); // Would induce a cycle.
2123 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2124 // that we are interested in. Form our input TokenFactor node.
2125 SmallVector<SDValue, 3> InputChains;
2126 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2127 // Add the input chain of this node to the InputChains list (which will be
2128 // the operands of the generated TokenFactor) if it's not an interior node.
2129 SDNode *N = ChainNodesMatched[i];
2130 if (N->getOpcode() != ISD::TokenFactor) {
2131 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2134 // Otherwise, add the input chain.
2135 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2136 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2137 InputChains.push_back(InChain);
2141 // If we have a token factor, we want to add all inputs of the token factor
2142 // that are not part of the pattern we're matching.
2143 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2144 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2145 N->getOperand(op).getNode()))
2146 InputChains.push_back(N->getOperand(op));
2150 if (InputChains.size() == 1)
2151 return InputChains[0];
2152 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2153 MVT::Other, InputChains);
2156 /// MorphNode - Handle morphing a node in place for the selector.
2157 SDNode *SelectionDAGISel::
2158 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2159 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2160 // It is possible we're using MorphNodeTo to replace a node with no
2161 // normal results with one that has a normal result (or we could be
2162 // adding a chain) and the input could have glue and chains as well.
2163 // In this case we need to shift the operands down.
2164 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2165 // than the old isel though.
2166 int OldGlueResultNo = -1, OldChainResultNo = -1;
2168 unsigned NTMNumResults = Node->getNumValues();
2169 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2170 OldGlueResultNo = NTMNumResults-1;
2171 if (NTMNumResults != 1 &&
2172 Node->getValueType(NTMNumResults-2) == MVT::Other)
2173 OldChainResultNo = NTMNumResults-2;
2174 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2175 OldChainResultNo = NTMNumResults-1;
2177 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2178 // that this deletes operands of the old node that become dead.
2179 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2181 // MorphNodeTo can operate in two ways: if an existing node with the
2182 // specified operands exists, it can just return it. Otherwise, it
2183 // updates the node in place to have the requested operands.
2185 // If we updated the node in place, reset the node ID. To the isel,
2186 // this should be just like a newly allocated machine node.
2190 unsigned ResNumResults = Res->getNumValues();
2191 // Move the glue if needed.
2192 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2193 (unsigned)OldGlueResultNo != ResNumResults-1)
2194 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2195 SDValue(Res, ResNumResults-1));
2197 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2200 // Move the chain reference if needed.
2201 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2202 (unsigned)OldChainResultNo != ResNumResults-1)
2203 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2204 SDValue(Res, ResNumResults-1));
2206 // Otherwise, no replacement happened because the node already exists. Replace
2207 // Uses of the old node with the new one.
2209 CurDAG->ReplaceAllUsesWith(Node, Res);
2214 /// CheckSame - Implements OP_CheckSame.
2215 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2216 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2218 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2219 // Accept if it is exactly the same as a previously recorded node.
2220 unsigned RecNo = MatcherTable[MatcherIndex++];
2221 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2222 return N == RecordedNodes[RecNo].first;
2225 /// CheckChildSame - Implements OP_CheckChildXSame.
2226 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2227 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2229 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2231 if (ChildNo >= N.getNumOperands())
2232 return false; // Match fails if out of range child #.
2233 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2237 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2238 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2239 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2240 const SelectionDAGISel &SDISel) {
2241 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2244 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2245 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2246 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2247 const SelectionDAGISel &SDISel, SDNode *N) {
2248 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2251 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2252 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2254 uint16_t Opc = MatcherTable[MatcherIndex++];
2255 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2256 return N->getOpcode() == Opc;
2259 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2260 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2261 SDValue N, const TargetLowering *TLI) {
2262 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2263 if (N.getValueType() == VT) return true;
2265 // Handle the case when VT is iPTR.
2266 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2269 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2270 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2271 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2272 if (ChildNo >= N.getNumOperands())
2273 return false; // Match fails if out of range child #.
2274 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2277 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2278 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2280 return cast<CondCodeSDNode>(N)->get() ==
2281 (ISD::CondCode)MatcherTable[MatcherIndex++];
2284 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2285 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2286 SDValue N, const TargetLowering *TLI) {
2287 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2288 if (cast<VTSDNode>(N)->getVT() == VT)
2291 // Handle the case when VT is iPTR.
2292 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2295 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2296 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2298 int64_t Val = MatcherTable[MatcherIndex++];
2300 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2302 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2303 return C && C->getSExtValue() == Val;
2306 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2307 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2308 SDValue N, unsigned ChildNo) {
2309 if (ChildNo >= N.getNumOperands())
2310 return false; // Match fails if out of range child #.
2311 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2314 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2315 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2316 SDValue N, const SelectionDAGISel &SDISel) {
2317 int64_t Val = MatcherTable[MatcherIndex++];
2319 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2321 if (N->getOpcode() != ISD::AND) return false;
2323 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2324 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2327 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2328 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2329 SDValue N, const SelectionDAGISel &SDISel) {
2330 int64_t Val = MatcherTable[MatcherIndex++];
2332 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2334 if (N->getOpcode() != ISD::OR) return false;
2336 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2337 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2340 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2341 /// scope, evaluate the current node. If the current predicate is known to
2342 /// fail, set Result=true and return anything. If the current predicate is
2343 /// known to pass, set Result=false and return the MatcherIndex to continue
2344 /// with. If the current predicate is unknown, set Result=false and return the
2345 /// MatcherIndex to continue with.
2346 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2347 unsigned Index, SDValue N,
2349 const SelectionDAGISel &SDISel,
2350 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2351 switch (Table[Index++]) {
2354 return Index-1; // Could not evaluate this predicate.
2355 case SelectionDAGISel::OPC_CheckSame:
2356 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2358 case SelectionDAGISel::OPC_CheckChild0Same:
2359 case SelectionDAGISel::OPC_CheckChild1Same:
2360 case SelectionDAGISel::OPC_CheckChild2Same:
2361 case SelectionDAGISel::OPC_CheckChild3Same:
2362 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2363 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2365 case SelectionDAGISel::OPC_CheckPatternPredicate:
2366 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2368 case SelectionDAGISel::OPC_CheckPredicate:
2369 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2371 case SelectionDAGISel::OPC_CheckOpcode:
2372 Result = !::CheckOpcode(Table, Index, N.getNode());
2374 case SelectionDAGISel::OPC_CheckType:
2375 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2377 case SelectionDAGISel::OPC_CheckChild0Type:
2378 case SelectionDAGISel::OPC_CheckChild1Type:
2379 case SelectionDAGISel::OPC_CheckChild2Type:
2380 case SelectionDAGISel::OPC_CheckChild3Type:
2381 case SelectionDAGISel::OPC_CheckChild4Type:
2382 case SelectionDAGISel::OPC_CheckChild5Type:
2383 case SelectionDAGISel::OPC_CheckChild6Type:
2384 case SelectionDAGISel::OPC_CheckChild7Type:
2385 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2387 SelectionDAGISel::OPC_CheckChild0Type);
2389 case SelectionDAGISel::OPC_CheckCondCode:
2390 Result = !::CheckCondCode(Table, Index, N);
2392 case SelectionDAGISel::OPC_CheckValueType:
2393 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2395 case SelectionDAGISel::OPC_CheckInteger:
2396 Result = !::CheckInteger(Table, Index, N);
2398 case SelectionDAGISel::OPC_CheckChild0Integer:
2399 case SelectionDAGISel::OPC_CheckChild1Integer:
2400 case SelectionDAGISel::OPC_CheckChild2Integer:
2401 case SelectionDAGISel::OPC_CheckChild3Integer:
2402 case SelectionDAGISel::OPC_CheckChild4Integer:
2403 Result = !::CheckChildInteger(Table, Index, N,
2404 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2406 case SelectionDAGISel::OPC_CheckAndImm:
2407 Result = !::CheckAndImm(Table, Index, N, SDISel);
2409 case SelectionDAGISel::OPC_CheckOrImm:
2410 Result = !::CheckOrImm(Table, Index, N, SDISel);
2418 /// FailIndex - If this match fails, this is the index to continue with.
2421 /// NodeStack - The node stack when the scope was formed.
2422 SmallVector<SDValue, 4> NodeStack;
2424 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2425 unsigned NumRecordedNodes;
2427 /// NumMatchedMemRefs - The number of matched memref entries.
2428 unsigned NumMatchedMemRefs;
2430 /// InputChain/InputGlue - The current chain/glue
2431 SDValue InputChain, InputGlue;
2433 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2434 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2437 /// \\brief A DAG update listener to keep the matching state
2438 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2439 /// change the DAG while matching. X86 addressing mode matcher is an example
2441 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2443 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2444 SmallVectorImpl<MatchScope> &MatchScopes;
2446 MatchStateUpdater(SelectionDAG &DAG,
2447 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2448 SmallVectorImpl<MatchScope> &MS) :
2449 SelectionDAG::DAGUpdateListener(DAG),
2450 RecordedNodes(RN), MatchScopes(MS) { }
2452 void NodeDeleted(SDNode *N, SDNode *E) {
2453 // Some early-returns here to avoid the search if we deleted the node or
2454 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2455 // do, so it's unnecessary to update matching state at that point).
2456 // Neither of these can occur currently because we only install this
2457 // update listener during matching a complex patterns.
2458 if (!E || E->isMachineOpcode())
2460 // Performing linear search here does not matter because we almost never
2461 // run this code. You'd have to have a CSE during complex pattern
2463 for (auto &I : RecordedNodes)
2464 if (I.first.getNode() == N)
2467 for (auto &I : MatchScopes)
2468 for (auto &J : I.NodeStack)
2469 if (J.getNode() == N)
2475 SDNode *SelectionDAGISel::
2476 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2477 unsigned TableSize) {
2478 // FIXME: Should these even be selected? Handle these cases in the caller?
2479 switch (NodeToMatch->getOpcode()) {
2482 case ISD::EntryToken: // These nodes remain the same.
2483 case ISD::BasicBlock:
2485 case ISD::RegisterMask:
2486 case ISD::HANDLENODE:
2487 case ISD::MDNODE_SDNODE:
2488 case ISD::TargetConstant:
2489 case ISD::TargetConstantFP:
2490 case ISD::TargetConstantPool:
2491 case ISD::TargetFrameIndex:
2492 case ISD::TargetExternalSymbol:
2493 case ISD::TargetBlockAddress:
2494 case ISD::TargetJumpTable:
2495 case ISD::TargetGlobalTLSAddress:
2496 case ISD::TargetGlobalAddress:
2497 case ISD::TokenFactor:
2498 case ISD::CopyFromReg:
2499 case ISD::CopyToReg:
2501 case ISD::LIFETIME_START:
2502 case ISD::LIFETIME_END:
2503 NodeToMatch->setNodeId(-1); // Mark selected.
2505 case ISD::AssertSext:
2506 case ISD::AssertZext:
2507 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2508 NodeToMatch->getOperand(0));
2510 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2511 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2512 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2513 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2516 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2518 // Set up the node stack with NodeToMatch as the only node on the stack.
2519 SmallVector<SDValue, 8> NodeStack;
2520 SDValue N = SDValue(NodeToMatch, 0);
2521 NodeStack.push_back(N);
2523 // MatchScopes - Scopes used when matching, if a match failure happens, this
2524 // indicates where to continue checking.
2525 SmallVector<MatchScope, 8> MatchScopes;
2527 // RecordedNodes - This is the set of nodes that have been recorded by the
2528 // state machine. The second value is the parent of the node, or null if the
2529 // root is recorded.
2530 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2532 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2534 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2536 // These are the current input chain and glue for use when generating nodes.
2537 // Various Emit operations change these. For example, emitting a copytoreg
2538 // uses and updates these.
2539 SDValue InputChain, InputGlue;
2541 // ChainNodesMatched - If a pattern matches nodes that have input/output
2542 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2543 // which ones they are. The result is captured into this list so that we can
2544 // update the chain results when the pattern is complete.
2545 SmallVector<SDNode*, 3> ChainNodesMatched;
2546 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2548 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2549 NodeToMatch->dump(CurDAG);
2552 // Determine where to start the interpreter. Normally we start at opcode #0,
2553 // but if the state machine starts with an OPC_SwitchOpcode, then we
2554 // accelerate the first lookup (which is guaranteed to be hot) with the
2555 // OpcodeOffset table.
2556 unsigned MatcherIndex = 0;
2558 if (!OpcodeOffset.empty()) {
2559 // Already computed the OpcodeOffset table, just index into it.
2560 if (N.getOpcode() < OpcodeOffset.size())
2561 MatcherIndex = OpcodeOffset[N.getOpcode()];
2562 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2564 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2565 // Otherwise, the table isn't computed, but the state machine does start
2566 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2567 // is the first time we're selecting an instruction.
2570 // Get the size of this case.
2571 unsigned CaseSize = MatcherTable[Idx++];
2573 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2574 if (CaseSize == 0) break;
2576 // Get the opcode, add the index to the table.
2577 uint16_t Opc = MatcherTable[Idx++];
2578 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2579 if (Opc >= OpcodeOffset.size())
2580 OpcodeOffset.resize((Opc+1)*2);
2581 OpcodeOffset[Opc] = Idx;
2585 // Okay, do the lookup for the first opcode.
2586 if (N.getOpcode() < OpcodeOffset.size())
2587 MatcherIndex = OpcodeOffset[N.getOpcode()];
2591 assert(MatcherIndex < TableSize && "Invalid index");
2593 unsigned CurrentOpcodeIndex = MatcherIndex;
2595 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2598 // Okay, the semantics of this operation are that we should push a scope
2599 // then evaluate the first child. However, pushing a scope only to have
2600 // the first check fail (which then pops it) is inefficient. If we can
2601 // determine immediately that the first check (or first several) will
2602 // immediately fail, don't even bother pushing a scope for them.
2606 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2607 if (NumToSkip & 128)
2608 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2609 // Found the end of the scope with no match.
2610 if (NumToSkip == 0) {
2615 FailIndex = MatcherIndex+NumToSkip;
2617 unsigned MatcherIndexOfPredicate = MatcherIndex;
2618 (void)MatcherIndexOfPredicate; // silence warning.
2620 // If we can't evaluate this predicate without pushing a scope (e.g. if
2621 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2622 // push the scope and evaluate the full predicate chain.
2624 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2625 Result, *this, RecordedNodes);
2629 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2630 << "index " << MatcherIndexOfPredicate
2631 << ", continuing at " << FailIndex << "\n");
2632 ++NumDAGIselRetries;
2634 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2635 // move to the next case.
2636 MatcherIndex = FailIndex;
2639 // If the whole scope failed to match, bail.
2640 if (FailIndex == 0) break;
2642 // Push a MatchScope which indicates where to go if the first child fails
2644 MatchScope NewEntry;
2645 NewEntry.FailIndex = FailIndex;
2646 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2647 NewEntry.NumRecordedNodes = RecordedNodes.size();
2648 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2649 NewEntry.InputChain = InputChain;
2650 NewEntry.InputGlue = InputGlue;
2651 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2652 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2653 MatchScopes.push_back(NewEntry);
2656 case OPC_RecordNode: {
2657 // Remember this node, it may end up being an operand in the pattern.
2658 SDNode *Parent = nullptr;
2659 if (NodeStack.size() > 1)
2660 Parent = NodeStack[NodeStack.size()-2].getNode();
2661 RecordedNodes.push_back(std::make_pair(N, Parent));
2665 case OPC_RecordChild0: case OPC_RecordChild1:
2666 case OPC_RecordChild2: case OPC_RecordChild3:
2667 case OPC_RecordChild4: case OPC_RecordChild5:
2668 case OPC_RecordChild6: case OPC_RecordChild7: {
2669 unsigned ChildNo = Opcode-OPC_RecordChild0;
2670 if (ChildNo >= N.getNumOperands())
2671 break; // Match fails if out of range child #.
2673 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2677 case OPC_RecordMemRef:
2678 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2681 case OPC_CaptureGlueInput:
2682 // If the current node has an input glue, capture it in InputGlue.
2683 if (N->getNumOperands() != 0 &&
2684 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2685 InputGlue = N->getOperand(N->getNumOperands()-1);
2688 case OPC_MoveChild: {
2689 unsigned ChildNo = MatcherTable[MatcherIndex++];
2690 if (ChildNo >= N.getNumOperands())
2691 break; // Match fails if out of range child #.
2692 N = N.getOperand(ChildNo);
2693 NodeStack.push_back(N);
2697 case OPC_MoveParent:
2698 // Pop the current node off the NodeStack.
2699 NodeStack.pop_back();
2700 assert(!NodeStack.empty() && "Node stack imbalance!");
2701 N = NodeStack.back();
2705 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2708 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2709 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2710 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2711 Opcode-OPC_CheckChild0Same))
2715 case OPC_CheckPatternPredicate:
2716 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2718 case OPC_CheckPredicate:
2719 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2723 case OPC_CheckComplexPat: {
2724 unsigned CPNum = MatcherTable[MatcherIndex++];
2725 unsigned RecNo = MatcherTable[MatcherIndex++];
2726 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2728 // If target can modify DAG during matching, keep the matching state
2730 std::unique_ptr<MatchStateUpdater> MSU;
2731 if (ComplexPatternFuncMutatesDAG())
2732 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2735 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2736 RecordedNodes[RecNo].first, CPNum,
2741 case OPC_CheckOpcode:
2742 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2746 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2750 case OPC_SwitchOpcode: {
2751 unsigned CurNodeOpcode = N.getOpcode();
2752 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2755 // Get the size of this case.
2756 CaseSize = MatcherTable[MatcherIndex++];
2758 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2759 if (CaseSize == 0) break;
2761 uint16_t Opc = MatcherTable[MatcherIndex++];
2762 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2764 // If the opcode matches, then we will execute this case.
2765 if (CurNodeOpcode == Opc)
2768 // Otherwise, skip over this case.
2769 MatcherIndex += CaseSize;
2772 // If no cases matched, bail out.
2773 if (CaseSize == 0) break;
2775 // Otherwise, execute the case we found.
2776 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2777 << " to " << MatcherIndex << "\n");
2781 case OPC_SwitchType: {
2782 MVT CurNodeVT = N.getSimpleValueType();
2783 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2786 // Get the size of this case.
2787 CaseSize = MatcherTable[MatcherIndex++];
2789 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2790 if (CaseSize == 0) break;
2792 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2793 if (CaseVT == MVT::iPTR)
2794 CaseVT = TLI->getPointerTy();
2796 // If the VT matches, then we will execute this case.
2797 if (CurNodeVT == CaseVT)
2800 // Otherwise, skip over this case.
2801 MatcherIndex += CaseSize;
2804 // If no cases matched, bail out.
2805 if (CaseSize == 0) break;
2807 // Otherwise, execute the case we found.
2808 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2809 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2812 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2813 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2814 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2815 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2816 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2817 Opcode-OPC_CheckChild0Type))
2820 case OPC_CheckCondCode:
2821 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2823 case OPC_CheckValueType:
2824 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2827 case OPC_CheckInteger:
2828 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2830 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2831 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2832 case OPC_CheckChild4Integer:
2833 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2834 Opcode-OPC_CheckChild0Integer)) break;
2836 case OPC_CheckAndImm:
2837 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2839 case OPC_CheckOrImm:
2840 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2843 case OPC_CheckFoldableChainNode: {
2844 assert(NodeStack.size() != 1 && "No parent node");
2845 // Verify that all intermediate nodes between the root and this one have
2847 bool HasMultipleUses = false;
2848 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2849 if (!NodeStack[i].hasOneUse()) {
2850 HasMultipleUses = true;
2853 if (HasMultipleUses) break;
2855 // Check to see that the target thinks this is profitable to fold and that
2856 // we can fold it without inducing cycles in the graph.
2857 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2859 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2860 NodeToMatch, OptLevel,
2861 true/*We validate our own chains*/))
2866 case OPC_EmitInteger: {
2867 MVT::SimpleValueType VT =
2868 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2869 int64_t Val = MatcherTable[MatcherIndex++];
2871 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2872 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2873 CurDAG->getTargetConstant(Val, VT), nullptr));
2876 case OPC_EmitRegister: {
2877 MVT::SimpleValueType VT =
2878 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2879 unsigned RegNo = MatcherTable[MatcherIndex++];
2880 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2881 CurDAG->getRegister(RegNo, VT), nullptr));
2884 case OPC_EmitRegister2: {
2885 // For targets w/ more than 256 register names, the register enum
2886 // values are stored in two bytes in the matcher table (just like
2888 MVT::SimpleValueType VT =
2889 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2890 unsigned RegNo = MatcherTable[MatcherIndex++];
2891 RegNo |= MatcherTable[MatcherIndex++] << 8;
2892 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2893 CurDAG->getRegister(RegNo, VT), nullptr));
2897 case OPC_EmitConvertToTarget: {
2898 // Convert from IMM/FPIMM to target version.
2899 unsigned RecNo = MatcherTable[MatcherIndex++];
2900 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2901 SDValue Imm = RecordedNodes[RecNo].first;
2903 if (Imm->getOpcode() == ISD::Constant) {
2904 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2905 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2906 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2907 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2908 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2911 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2915 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2916 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2917 // These are space-optimized forms of OPC_EmitMergeInputChains.
2918 assert(!InputChain.getNode() &&
2919 "EmitMergeInputChains should be the first chain producing node");
2920 assert(ChainNodesMatched.empty() &&
2921 "Should only have one EmitMergeInputChains per match");
2923 // Read all of the chained nodes.
2924 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2925 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2926 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2928 // FIXME: What if other value results of the node have uses not matched
2930 if (ChainNodesMatched.back() != NodeToMatch &&
2931 !RecordedNodes[RecNo].first.hasOneUse()) {
2932 ChainNodesMatched.clear();
2936 // Merge the input chains if they are not intra-pattern references.
2937 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2939 if (!InputChain.getNode())
2940 break; // Failed to merge.
2944 case OPC_EmitMergeInputChains: {
2945 assert(!InputChain.getNode() &&
2946 "EmitMergeInputChains should be the first chain producing node");
2947 // This node gets a list of nodes we matched in the input that have
2948 // chains. We want to token factor all of the input chains to these nodes
2949 // together. However, if any of the input chains is actually one of the
2950 // nodes matched in this pattern, then we have an intra-match reference.
2951 // Ignore these because the newly token factored chain should not refer to
2953 unsigned NumChains = MatcherTable[MatcherIndex++];
2954 assert(NumChains != 0 && "Can't TF zero chains");
2956 assert(ChainNodesMatched.empty() &&
2957 "Should only have one EmitMergeInputChains per match");
2959 // Read all of the chained nodes.
2960 for (unsigned i = 0; i != NumChains; ++i) {
2961 unsigned RecNo = MatcherTable[MatcherIndex++];
2962 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2963 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2965 // FIXME: What if other value results of the node have uses not matched
2967 if (ChainNodesMatched.back() != NodeToMatch &&
2968 !RecordedNodes[RecNo].first.hasOneUse()) {
2969 ChainNodesMatched.clear();
2974 // If the inner loop broke out, the match fails.
2975 if (ChainNodesMatched.empty())
2978 // Merge the input chains if they are not intra-pattern references.
2979 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2981 if (!InputChain.getNode())
2982 break; // Failed to merge.
2987 case OPC_EmitCopyToReg: {
2988 unsigned RecNo = MatcherTable[MatcherIndex++];
2989 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
2990 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2992 if (!InputChain.getNode())
2993 InputChain = CurDAG->getEntryNode();
2995 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2996 DestPhysReg, RecordedNodes[RecNo].first,
2999 InputGlue = InputChain.getValue(1);
3003 case OPC_EmitNodeXForm: {
3004 unsigned XFormNo = MatcherTable[MatcherIndex++];
3005 unsigned RecNo = MatcherTable[MatcherIndex++];
3006 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3007 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3008 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3013 case OPC_MorphNodeTo: {
3014 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3015 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3016 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3017 // Get the result VT list.
3018 unsigned NumVTs = MatcherTable[MatcherIndex++];
3019 SmallVector<EVT, 4> VTs;
3020 for (unsigned i = 0; i != NumVTs; ++i) {
3021 MVT::SimpleValueType VT =
3022 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3023 if (VT == MVT::iPTR)
3024 VT = TLI->getPointerTy().SimpleTy;
3028 if (EmitNodeInfo & OPFL_Chain)
3029 VTs.push_back(MVT::Other);
3030 if (EmitNodeInfo & OPFL_GlueOutput)
3031 VTs.push_back(MVT::Glue);
3033 // This is hot code, so optimize the two most common cases of 1 and 2
3036 if (VTs.size() == 1)
3037 VTList = CurDAG->getVTList(VTs[0]);
3038 else if (VTs.size() == 2)
3039 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3041 VTList = CurDAG->getVTList(VTs);
3043 // Get the operand list.
3044 unsigned NumOps = MatcherTable[MatcherIndex++];
3045 SmallVector<SDValue, 8> Ops;
3046 for (unsigned i = 0; i != NumOps; ++i) {
3047 unsigned RecNo = MatcherTable[MatcherIndex++];
3049 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3051 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3052 Ops.push_back(RecordedNodes[RecNo].first);
3055 // If there are variadic operands to add, handle them now.
3056 if (EmitNodeInfo & OPFL_VariadicInfo) {
3057 // Determine the start index to copy from.
3058 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3059 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3060 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3061 "Invalid variadic node");
3062 // Copy all of the variadic operands, not including a potential glue
3064 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3066 SDValue V = NodeToMatch->getOperand(i);
3067 if (V.getValueType() == MVT::Glue) break;
3072 // If this has chain/glue inputs, add them.
3073 if (EmitNodeInfo & OPFL_Chain)
3074 Ops.push_back(InputChain);
3075 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3076 Ops.push_back(InputGlue);
3079 SDNode *Res = nullptr;
3080 if (Opcode != OPC_MorphNodeTo) {
3081 // If this is a normal EmitNode command, just create the new node and
3082 // add the results to the RecordedNodes list.
3083 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3086 // Add all the non-glue/non-chain results to the RecordedNodes list.
3087 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3088 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3089 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3093 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3094 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3096 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3097 // We will visit the equivalent node later.
3098 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3102 // If the node had chain/glue results, update our notion of the current
3104 if (EmitNodeInfo & OPFL_GlueOutput) {
3105 InputGlue = SDValue(Res, VTs.size()-1);
3106 if (EmitNodeInfo & OPFL_Chain)
3107 InputChain = SDValue(Res, VTs.size()-2);
3108 } else if (EmitNodeInfo & OPFL_Chain)
3109 InputChain = SDValue(Res, VTs.size()-1);
3111 // If the OPFL_MemRefs glue is set on this node, slap all of the
3112 // accumulated memrefs onto it.
3114 // FIXME: This is vastly incorrect for patterns with multiple outputs
3115 // instructions that access memory and for ComplexPatterns that match
3117 if (EmitNodeInfo & OPFL_MemRefs) {
3118 // Only attach load or store memory operands if the generated
3119 // instruction may load or store.
3120 const MCInstrDesc &MCID = TII->get(TargetOpc);
3121 bool mayLoad = MCID.mayLoad();
3122 bool mayStore = MCID.mayStore();
3124 unsigned NumMemRefs = 0;
3125 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3126 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3127 if ((*I)->isLoad()) {
3130 } else if ((*I)->isStore()) {
3138 MachineSDNode::mmo_iterator MemRefs =
3139 MF->allocateMemRefsArray(NumMemRefs);
3141 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3142 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3143 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3144 if ((*I)->isLoad()) {
3147 } else if ((*I)->isStore()) {
3155 cast<MachineSDNode>(Res)
3156 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3160 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3161 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3163 // If this was a MorphNodeTo then we're completely done!
3164 if (Opcode == OPC_MorphNodeTo) {
3165 // Update chain and glue uses.
3166 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3167 InputGlue, GlueResultNodesMatched, true);
3174 case OPC_MarkGlueResults: {
3175 unsigned NumNodes = MatcherTable[MatcherIndex++];
3177 // Read and remember all the glue-result nodes.
3178 for (unsigned i = 0; i != NumNodes; ++i) {
3179 unsigned RecNo = MatcherTable[MatcherIndex++];
3181 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3183 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3184 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3189 case OPC_CompleteMatch: {
3190 // The match has been completed, and any new nodes (if any) have been
3191 // created. Patch up references to the matched dag to use the newly
3193 unsigned NumResults = MatcherTable[MatcherIndex++];
3195 for (unsigned i = 0; i != NumResults; ++i) {
3196 unsigned ResSlot = MatcherTable[MatcherIndex++];
3198 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3200 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3201 SDValue Res = RecordedNodes[ResSlot].first;
3203 assert(i < NodeToMatch->getNumValues() &&
3204 NodeToMatch->getValueType(i) != MVT::Other &&
3205 NodeToMatch->getValueType(i) != MVT::Glue &&
3206 "Invalid number of results to complete!");
3207 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3208 NodeToMatch->getValueType(i) == MVT::iPTR ||
3209 Res.getValueType() == MVT::iPTR ||
3210 NodeToMatch->getValueType(i).getSizeInBits() ==
3211 Res.getValueType().getSizeInBits()) &&
3212 "invalid replacement");
3213 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3216 // If the root node defines glue, add it to the glue nodes to update list.
3217 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3218 GlueResultNodesMatched.push_back(NodeToMatch);
3220 // Update chain and glue uses.
3221 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3222 InputGlue, GlueResultNodesMatched, false);
3224 assert(NodeToMatch->use_empty() &&
3225 "Didn't replace all uses of the node?");
3227 // FIXME: We just return here, which interacts correctly with SelectRoot
3228 // above. We should fix this to not return an SDNode* anymore.
3233 // If the code reached this point, then the match failed. See if there is
3234 // another child to try in the current 'Scope', otherwise pop it until we
3235 // find a case to check.
3236 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3237 ++NumDAGIselRetries;
3239 if (MatchScopes.empty()) {
3240 CannotYetSelect(NodeToMatch);
3244 // Restore the interpreter state back to the point where the scope was
3246 MatchScope &LastScope = MatchScopes.back();
3247 RecordedNodes.resize(LastScope.NumRecordedNodes);
3249 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3250 N = NodeStack.back();
3252 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3253 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3254 MatcherIndex = LastScope.FailIndex;
3256 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3258 InputChain = LastScope.InputChain;
3259 InputGlue = LastScope.InputGlue;
3260 if (!LastScope.HasChainNodesMatched)
3261 ChainNodesMatched.clear();
3262 if (!LastScope.HasGlueResultNodesMatched)
3263 GlueResultNodesMatched.clear();
3265 // Check to see what the offset is at the new MatcherIndex. If it is zero
3266 // we have reached the end of this scope, otherwise we have another child
3267 // in the current scope to try.
3268 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3269 if (NumToSkip & 128)
3270 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3272 // If we have another child in this scope to match, update FailIndex and
3274 if (NumToSkip != 0) {
3275 LastScope.FailIndex = MatcherIndex+NumToSkip;
3279 // End of this scope, pop it and try the next child in the containing
3281 MatchScopes.pop_back();
3288 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3290 raw_string_ostream Msg(msg);
3291 Msg << "Cannot select: ";
3293 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3294 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3295 N->getOpcode() != ISD::INTRINSIC_VOID) {
3296 N->printrFull(Msg, CurDAG);
3297 Msg << "\nIn function: " << MF->getName();
3299 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3301 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3302 if (iid < Intrinsic::num_intrinsics)
3303 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3304 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3305 Msg << "target intrinsic %" << TII->getName(iid);
3307 Msg << "unknown intrinsic #" << iid;
3309 report_fatal_error(Msg.str());
3312 char SelectionDAGISel::ID = 0;