1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/LibCallSemantics.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGISel.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/InlineAsm.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/IntrinsicInst.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/IR/LLVMContext.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/MC/MCAsmInfo.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetIntrinsicInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Target/TargetOptions.h"
58 #include "llvm/Target/TargetRegisterInfo.h"
59 #include "llvm/Target/TargetSubtargetInfo.h"
60 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
64 #define DEBUG_TYPE "isel"
66 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
67 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
68 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
69 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
70 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
71 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
72 STATISTIC(NumFastIselFailLowerArguments,
73 "Number of entry blocks where fast isel failed to lower arguments");
77 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
78 cl::desc("Enable extra verbose messages in the \"fast\" "
79 "instruction selector"));
82 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
83 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
84 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
85 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
86 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
87 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
88 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
90 // Standard binary operators...
91 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
92 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
93 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
94 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
95 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
96 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
97 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
98 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
99 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
100 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
101 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
102 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
104 // Logical operators...
105 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
106 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
107 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
109 // Memory instructions...
110 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
111 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
112 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
113 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
114 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
115 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
116 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
118 // Convert instructions...
119 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
120 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
121 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
122 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
123 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
124 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
125 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
126 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
127 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
128 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
129 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
130 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
132 // Other instructions...
133 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
134 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
135 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
136 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
137 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
138 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
139 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
140 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
141 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
142 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
143 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
144 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
145 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
146 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
147 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
149 // Intrinsic instructions...
150 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
151 STATISTIC(NumFastIselFailSAddWithOverflow,
152 "Fast isel fails on sadd.with.overflow");
153 STATISTIC(NumFastIselFailUAddWithOverflow,
154 "Fast isel fails on uadd.with.overflow");
155 STATISTIC(NumFastIselFailSSubWithOverflow,
156 "Fast isel fails on ssub.with.overflow");
157 STATISTIC(NumFastIselFailUSubWithOverflow,
158 "Fast isel fails on usub.with.overflow");
159 STATISTIC(NumFastIselFailSMulWithOverflow,
160 "Fast isel fails on smul.with.overflow");
161 STATISTIC(NumFastIselFailUMulWithOverflow,
162 "Fast isel fails on umul.with.overflow");
163 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
164 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
165 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
166 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
170 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
171 cl::desc("Enable verbose messages in the \"fast\" "
172 "instruction selector"));
173 static cl::opt<int> EnableFastISelAbort(
174 "fast-isel-abort", cl::Hidden,
175 cl::desc("Enable abort calls when \"fast\" instruction selection "
176 "fails to lower an instruction: 0 disable the abort, 1 will "
177 "abort but for args, calls and terminators, 2 will also "
178 "abort for argument lowering, and 3 will never fallback "
179 "to SelectionDAG."));
183 cl::desc("use Machine Branch Probability Info"),
184 cl::init(true), cl::Hidden);
187 static cl::opt<std::string>
188 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
189 cl::desc("Only display the basic block whose name "
190 "matches this for all view-*-dags options"));
192 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
193 cl::desc("Pop up a window to show dags before the first "
194 "dag combine pass"));
196 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
197 cl::desc("Pop up a window to show dags before legalize types"));
199 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
200 cl::desc("Pop up a window to show dags before legalize"));
202 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
203 cl::desc("Pop up a window to show dags before the second "
204 "dag combine pass"));
206 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
207 cl::desc("Pop up a window to show dags before the post legalize types"
208 " dag combine pass"));
210 ViewISelDAGs("view-isel-dags", cl::Hidden,
211 cl::desc("Pop up a window to show isel dags as they are selected"));
213 ViewSchedDAGs("view-sched-dags", cl::Hidden,
214 cl::desc("Pop up a window to show sched dags as they are processed"));
216 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
217 cl::desc("Pop up a window to show SUnit dags after they are processed"));
219 static const bool ViewDAGCombine1 = false,
220 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
221 ViewDAGCombine2 = false,
222 ViewDAGCombineLT = false,
223 ViewISelDAGs = false, ViewSchedDAGs = false,
224 ViewSUnitDAGs = false;
227 //===---------------------------------------------------------------------===//
229 /// RegisterScheduler class - Track the registration of instruction schedulers.
231 //===---------------------------------------------------------------------===//
232 MachinePassRegistry RegisterScheduler::Registry;
234 //===---------------------------------------------------------------------===//
236 /// ISHeuristic command line option for instruction schedulers.
238 //===---------------------------------------------------------------------===//
239 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
240 RegisterPassParser<RegisterScheduler> >
241 ISHeuristic("pre-RA-sched",
242 cl::init(&createDefaultScheduler), cl::Hidden,
243 cl::desc("Instruction schedulers available (before register"
246 static RegisterScheduler
247 defaultListDAGScheduler("default", "Best scheduler for the target",
248 createDefaultScheduler);
251 //===--------------------------------------------------------------------===//
252 /// \brief This class is used by SelectionDAGISel to temporarily override
253 /// the optimization level on a per-function basis.
254 class OptLevelChanger {
255 SelectionDAGISel &IS;
256 CodeGenOpt::Level SavedOptLevel;
260 OptLevelChanger(SelectionDAGISel &ISel,
261 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
262 SavedOptLevel = IS.OptLevel;
263 if (NewOptLevel == SavedOptLevel)
265 IS.OptLevel = NewOptLevel;
266 IS.TM.setOptLevel(NewOptLevel);
267 SavedFastISel = IS.TM.Options.EnableFastISel;
268 if (NewOptLevel == CodeGenOpt::None)
269 IS.TM.setFastISel(true);
270 DEBUG(dbgs() << "\nChanging optimization level for Function "
271 << IS.MF->getFunction()->getName() << "\n");
272 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
273 << " ; After: -O" << NewOptLevel << "\n");
277 if (IS.OptLevel == SavedOptLevel)
279 DEBUG(dbgs() << "\nRestoring optimization level for Function "
280 << IS.MF->getFunction()->getName() << "\n");
281 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
282 << " ; After: -O" << SavedOptLevel << "\n");
283 IS.OptLevel = SavedOptLevel;
284 IS.TM.setOptLevel(SavedOptLevel);
285 IS.TM.setFastISel(SavedFastISel);
289 //===--------------------------------------------------------------------===//
290 /// createDefaultScheduler - This creates an instruction scheduler appropriate
292 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
293 CodeGenOpt::Level OptLevel) {
294 const TargetLowering *TLI = IS->TLI;
295 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
297 // Try first to see if the Target has its own way of selecting a scheduler
298 if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
299 return SchedulerCtor(IS, OptLevel);
302 if (OptLevel == CodeGenOpt::None ||
303 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
304 TLI->getSchedulingPreference() == Sched::Source)
305 return createSourceListDAGScheduler(IS, OptLevel);
306 if (TLI->getSchedulingPreference() == Sched::RegPressure)
307 return createBURRListDAGScheduler(IS, OptLevel);
308 if (TLI->getSchedulingPreference() == Sched::Hybrid)
309 return createHybridListDAGScheduler(IS, OptLevel);
310 if (TLI->getSchedulingPreference() == Sched::VLIW)
311 return createVLIWDAGScheduler(IS, OptLevel);
312 assert(TLI->getSchedulingPreference() == Sched::ILP &&
313 "Unknown sched type!");
314 return createILPListDAGScheduler(IS, OptLevel);
318 // EmitInstrWithCustomInserter - This method should be implemented by targets
319 // that mark instructions with the 'usesCustomInserter' flag. These
320 // instructions are special in various ways, which require special support to
321 // insert. The specified MachineInstr is created but not inserted into any
322 // basic blocks, and this method is called to expand it into a sequence of
323 // instructions, potentially also creating new basic blocks and control flow.
324 // When new basic blocks are inserted and the edges from MBB to its successors
325 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
328 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
329 MachineBasicBlock *MBB) const {
331 dbgs() << "If a target marks an instruction with "
332 "'usesCustomInserter', it must implement "
333 "TargetLowering::EmitInstrWithCustomInserter!";
335 llvm_unreachable(nullptr);
338 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
339 SDNode *Node) const {
340 assert(!MI->hasPostISelHook() &&
341 "If a target marks an instruction with 'hasPostISelHook', "
342 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
345 //===----------------------------------------------------------------------===//
346 // SelectionDAGISel code
347 //===----------------------------------------------------------------------===//
349 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
350 CodeGenOpt::Level OL) :
351 MachineFunctionPass(ID), TM(tm),
352 FuncInfo(new FunctionLoweringInfo()),
353 CurDAG(new SelectionDAG(tm, OL)),
354 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
358 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
359 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
360 initializeBranchProbabilityInfoWrapperPassPass(
361 *PassRegistry::getPassRegistry());
362 initializeTargetLibraryInfoWrapperPassPass(
363 *PassRegistry::getPassRegistry());
366 SelectionDAGISel::~SelectionDAGISel() {
372 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
373 AU.addRequired<AliasAnalysis>();
374 AU.addPreserved<AliasAnalysis>();
375 AU.addRequired<GCModuleInfo>();
376 AU.addPreserved<GCModuleInfo>();
377 AU.addRequired<TargetLibraryInfoWrapperPass>();
378 if (UseMBPI && OptLevel != CodeGenOpt::None)
379 AU.addRequired<BranchProbabilityInfoWrapperPass>();
380 MachineFunctionPass::getAnalysisUsage(AU);
383 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
384 /// may trap on it. In this case we have to split the edge so that the path
385 /// through the predecessor block that doesn't go to the phi block doesn't
386 /// execute the possibly trapping instruction.
388 /// This is required for correctness, so it must be done at -O0.
390 static void SplitCriticalSideEffectEdges(Function &Fn) {
391 // Loop for blocks with phi nodes.
392 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
393 PHINode *PN = dyn_cast<PHINode>(BB->begin());
397 // For each block with a PHI node, check to see if any of the input values
398 // are potentially trapping constant expressions. Constant expressions are
399 // the only potentially trapping value that can occur as the argument to a
401 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
402 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
403 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
404 if (!CE || !CE->canTrap()) continue;
406 // The only case we have to worry about is when the edge is critical.
407 // Since this block has a PHI Node, we assume it has multiple input
408 // edges: check to see if the pred has multiple successors.
409 BasicBlock *Pred = PN->getIncomingBlock(i);
410 if (Pred->getTerminator()->getNumSuccessors() == 1)
413 // Okay, we have to split this edge.
415 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
416 CriticalEdgeSplittingOptions().setMergeIdenticalEdges());
422 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
423 // Do some sanity-checking on the command-line options.
424 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
425 "-fast-isel-verbose requires -fast-isel");
426 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
427 "-fast-isel-abort > 0 requires -fast-isel");
429 const Function &Fn = *mf.getFunction();
432 // Reset the target options before resetting the optimization
434 // FIXME: This is a horrible hack and should be processed via
435 // codegen looking at the optimization level explicitly when
436 // it wants to look at it.
437 TM.resetTargetOptions(Fn);
438 // Reset OptLevel to None for optnone functions.
439 CodeGenOpt::Level NewOptLevel = OptLevel;
440 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
441 NewOptLevel = CodeGenOpt::None;
442 OptLevelChanger OLC(*this, NewOptLevel);
444 TII = MF->getSubtarget().getInstrInfo();
445 TLI = MF->getSubtarget().getTargetLowering();
446 RegInfo = &MF->getRegInfo();
447 AA = &getAnalysis<AliasAnalysis>();
448 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
449 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
451 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
453 SplitCriticalSideEffectEdges(const_cast<Function &>(Fn));
456 FuncInfo->set(Fn, *MF, CurDAG);
458 if (UseMBPI && OptLevel != CodeGenOpt::None)
459 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
461 FuncInfo->BPI = nullptr;
463 SDB->init(GFI, *AA, LibInfo);
465 MF->setHasInlineAsm(false);
467 SelectAllBasicBlocks(Fn);
469 // If the first basic block in the function has live ins that need to be
470 // copied into vregs, emit the copies into the top of the block before
471 // emitting the code for the block.
472 MachineBasicBlock *EntryMBB = MF->begin();
473 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
474 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
476 DenseMap<unsigned, unsigned> LiveInMap;
477 if (!FuncInfo->ArgDbgValues.empty())
478 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
479 E = RegInfo->livein_end(); LI != E; ++LI)
481 LiveInMap.insert(std::make_pair(LI->first, LI->second));
483 // Insert DBG_VALUE instructions for function arguments to the entry block.
484 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
485 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
486 bool hasFI = MI->getOperand(0).isFI();
488 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
489 if (TargetRegisterInfo::isPhysicalRegister(Reg))
490 EntryMBB->insert(EntryMBB->begin(), MI);
492 MachineInstr *Def = RegInfo->getVRegDef(Reg);
494 MachineBasicBlock::iterator InsertPos = Def;
495 // FIXME: VR def may not be in entry block.
496 Def->getParent()->insert(std::next(InsertPos), MI);
498 DEBUG(dbgs() << "Dropping debug info for dead vreg"
499 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
502 // If Reg is live-in then update debug info to track its copy in a vreg.
503 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
504 if (LDI != LiveInMap.end()) {
505 assert(!hasFI && "There's no handling of frame pointer updating here yet "
507 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
508 MachineBasicBlock::iterator InsertPos = Def;
509 const MDNode *Variable = MI->getDebugVariable();
510 const MDNode *Expr = MI->getDebugExpression();
511 DebugLoc DL = MI->getDebugLoc();
512 bool IsIndirect = MI->isIndirectDebugValue();
513 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
514 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
515 "Expected inlined-at fields to agree");
516 // Def is never a terminator here, so it is ok to increment InsertPos.
517 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
518 IsIndirect, LDI->second, Offset, Variable, Expr);
520 // If this vreg is directly copied into an exported register then
521 // that COPY instructions also need DBG_VALUE, if it is the only
522 // user of LDI->second.
523 MachineInstr *CopyUseMI = nullptr;
524 for (MachineRegisterInfo::use_instr_iterator
525 UI = RegInfo->use_instr_begin(LDI->second),
526 E = RegInfo->use_instr_end(); UI != E; ) {
527 MachineInstr *UseMI = &*(UI++);
528 if (UseMI->isDebugValue()) continue;
529 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
530 CopyUseMI = UseMI; continue;
532 // Otherwise this is another use or second copy use.
533 CopyUseMI = nullptr; break;
536 // Use MI's debug location, which describes where Variable was
537 // declared, rather than whatever is attached to CopyUseMI.
538 MachineInstr *NewMI =
539 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
540 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
541 MachineBasicBlock::iterator Pos = CopyUseMI;
542 EntryMBB->insertAfter(Pos, NewMI);
547 // Determine if there are any calls in this machine function.
548 MachineFrameInfo *MFI = MF->getFrameInfo();
549 for (const auto &MBB : *MF) {
550 if (MFI->hasCalls() && MF->hasInlineAsm())
553 for (const auto &MI : MBB) {
554 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
555 if ((MCID.isCall() && !MCID.isReturn()) ||
556 MI.isStackAligningInlineAsm()) {
557 MFI->setHasCalls(true);
559 if (MI.isInlineAsm()) {
560 MF->setHasInlineAsm(true);
565 // Determine if there is a call to setjmp in the machine function.
566 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
568 // Replace forward-declared registers with the registers containing
569 // the desired value.
570 MachineRegisterInfo &MRI = MF->getRegInfo();
571 for (DenseMap<unsigned, unsigned>::iterator
572 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
574 unsigned From = I->first;
575 unsigned To = I->second;
576 // If To is also scheduled to be replaced, find what its ultimate
579 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
583 // Make sure the new register has a sufficiently constrained register class.
584 if (TargetRegisterInfo::isVirtualRegister(From) &&
585 TargetRegisterInfo::isVirtualRegister(To))
586 MRI.constrainRegClass(To, MRI.getRegClass(From));
590 // Replacing one register with another won't touch the kill flags.
591 // We need to conservatively clear the kill flags as a kill on the old
592 // register might dominate existing uses of the new register.
593 if (!MRI.use_empty(To))
594 MRI.clearKillFlags(From);
595 MRI.replaceRegWith(From, To);
598 // Freeze the set of reserved registers now that MachineFrameInfo has been
599 // set up. All the information required by getReservedRegs() should be
601 MRI.freezeReservedRegs(*MF);
603 // Release function-specific state. SDB and CurDAG are already cleared
607 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
608 DEBUG(MF->print(dbgs()));
613 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
614 BasicBlock::const_iterator End,
616 // Lower the instructions. If a call is emitted as a tail call, cease emitting
617 // nodes for this block.
618 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
621 // Make sure the root of the DAG is up-to-date.
622 CurDAG->setRoot(SDB->getControlRoot());
623 HadTailCall = SDB->HasTailCall;
626 // Final step, emit the lowered DAG as machine code.
630 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
631 SmallPtrSet<SDNode*, 128> VisitedNodes;
632 SmallVector<SDNode*, 128> Worklist;
634 Worklist.push_back(CurDAG->getRoot().getNode());
640 SDNode *N = Worklist.pop_back_val();
642 // If we've already seen this node, ignore it.
643 if (!VisitedNodes.insert(N).second)
646 // Otherwise, add all chain operands to the worklist.
647 for (const SDValue &Op : N->op_values())
648 if (Op.getValueType() == MVT::Other)
649 Worklist.push_back(Op.getNode());
651 // If this is a CopyToReg with a vreg dest, process it.
652 if (N->getOpcode() != ISD::CopyToReg)
655 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
656 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
659 // Ignore non-scalar or non-integer values.
660 SDValue Src = N->getOperand(2);
661 EVT SrcVT = Src.getValueType();
662 if (!SrcVT.isInteger() || SrcVT.isVector())
665 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
666 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
667 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
668 } while (!Worklist.empty());
671 void SelectionDAGISel::CodeGenAndEmitDAG() {
672 std::string GroupName;
673 if (TimePassesIsEnabled)
674 GroupName = "Instruction Selection and Scheduling";
675 std::string BlockName;
676 int BlockNumber = -1;
678 bool MatchFilterBB = false; (void)MatchFilterBB;
680 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
681 FilterDAGBasicBlockName ==
682 FuncInfo->MBB->getBasicBlock()->getName().str());
685 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
686 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
690 BlockNumber = FuncInfo->MBB->getNumber();
692 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
694 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
695 << " '" << BlockName << "'\n"; CurDAG->dump());
697 if (ViewDAGCombine1 && MatchFilterBB)
698 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
700 // Run the DAG combiner in pre-legalize mode.
702 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
703 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
706 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
707 << " '" << BlockName << "'\n"; CurDAG->dump());
709 // Second step, hack on the DAG until it only uses operations and types that
710 // the target supports.
711 if (ViewLegalizeTypesDAGs && MatchFilterBB)
712 CurDAG->viewGraph("legalize-types input for " + BlockName);
716 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
717 Changed = CurDAG->LegalizeTypes();
720 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
721 << " '" << BlockName << "'\n"; CurDAG->dump());
723 CurDAG->NewNodesMustHaveLegalTypes = true;
726 if (ViewDAGCombineLT && MatchFilterBB)
727 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
729 // Run the DAG combiner in post-type-legalize mode.
731 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
732 TimePassesIsEnabled);
733 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
736 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
737 << " '" << BlockName << "'\n"; CurDAG->dump());
742 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
743 Changed = CurDAG->LegalizeVectors();
748 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
749 CurDAG->LegalizeTypes();
752 if (ViewDAGCombineLT && MatchFilterBB)
753 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
755 // Run the DAG combiner in post-type-legalize mode.
757 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
758 TimePassesIsEnabled);
759 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
762 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
763 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
766 if (ViewLegalizeDAGs && MatchFilterBB)
767 CurDAG->viewGraph("legalize input for " + BlockName);
770 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
774 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
775 << " '" << BlockName << "'\n"; CurDAG->dump());
777 if (ViewDAGCombine2 && MatchFilterBB)
778 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
780 // Run the DAG combiner in post-legalize mode.
782 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
783 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
786 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
787 << " '" << BlockName << "'\n"; CurDAG->dump());
789 if (OptLevel != CodeGenOpt::None)
790 ComputeLiveOutVRegInfo();
792 if (ViewISelDAGs && MatchFilterBB)
793 CurDAG->viewGraph("isel input for " + BlockName);
795 // Third, instruction select all of the operations to machine code, adding the
796 // code to the MachineBasicBlock.
798 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
799 DoInstructionSelection();
802 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
803 << " '" << BlockName << "'\n"; CurDAG->dump());
805 if (ViewSchedDAGs && MatchFilterBB)
806 CurDAG->viewGraph("scheduler input for " + BlockName);
808 // Schedule machine code.
809 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
811 NamedRegionTimer T("Instruction Scheduling", GroupName,
812 TimePassesIsEnabled);
813 Scheduler->Run(CurDAG, FuncInfo->MBB);
816 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
818 // Emit machine code to BB. This can change 'BB' to the last block being
820 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
822 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
824 // FuncInfo->InsertPt is passed by reference and set to the end of the
825 // scheduled instructions.
826 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
829 // If the block was split, make sure we update any references that are used to
830 // update PHI nodes later on.
831 if (FirstMBB != LastMBB)
832 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
834 // Free the scheduler state.
836 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
837 TimePassesIsEnabled);
841 // Free the SelectionDAG state, now that we're finished with it.
846 /// ISelUpdater - helper class to handle updates of the instruction selection
848 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
849 SelectionDAG::allnodes_iterator &ISelPosition;
851 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
852 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
854 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
855 /// deleted is the current ISelPosition node, update ISelPosition.
857 void NodeDeleted(SDNode *N, SDNode *E) override {
858 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
862 } // end anonymous namespace
864 void SelectionDAGISel::DoInstructionSelection() {
865 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
866 << FuncInfo->MBB->getNumber()
867 << " '" << FuncInfo->MBB->getName() << "'\n");
871 // Select target instructions for the DAG.
873 // Number all nodes with a topological order and set DAGSize.
874 DAGSize = CurDAG->AssignTopologicalOrder();
876 // Create a dummy node (which is not added to allnodes), that adds
877 // a reference to the root node, preventing it from being deleted,
878 // and tracking any changes of the root.
879 HandleSDNode Dummy(CurDAG->getRoot());
880 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
883 // Make sure that ISelPosition gets properly updated when nodes are deleted
884 // in calls made from this function.
885 ISelUpdater ISU(*CurDAG, ISelPosition);
887 // The AllNodes list is now topological-sorted. Visit the
888 // nodes by starting at the end of the list (the root of the
889 // graph) and preceding back toward the beginning (the entry
891 while (ISelPosition != CurDAG->allnodes_begin()) {
892 SDNode *Node = --ISelPosition;
893 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
894 // but there are currently some corner cases that it misses. Also, this
895 // makes it theoretically possible to disable the DAGCombiner.
896 if (Node->use_empty())
899 SDNode *ResNode = Select(Node);
901 // FIXME: This is pretty gross. 'Select' should be changed to not return
902 // anything at all and this code should be nuked with a tactical strike.
904 // If node should not be replaced, continue with the next one.
905 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
909 ReplaceUses(Node, ResNode);
912 // If after the replacement this node is not used any more,
913 // remove this dead node.
914 if (Node->use_empty()) // Don't delete EntryToken, etc.
915 CurDAG->RemoveDeadNode(Node);
918 CurDAG->setRoot(Dummy.getValue());
921 DEBUG(dbgs() << "===== Instruction selection ends:\n");
923 PostprocessISelDAG();
926 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
927 /// do other setup for EH landing-pad blocks.
928 bool SelectionDAGISel::PrepareEHLandingPad() {
929 MachineBasicBlock *MBB = FuncInfo->MBB;
931 const TargetRegisterClass *PtrRC =
932 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));
934 // Add a label to mark the beginning of the landing pad. Deletion of the
935 // landing pad can thus be detected via the MachineModuleInfo.
936 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
938 // Assign the call site to the landing pad's begin label.
939 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
941 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
942 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
945 // If this is an MSVC-style personality function, we need to split the landing
946 // pad into several BBs.
947 const BasicBlock *LLVMBB = MBB->getBasicBlock();
948 const Constant *Personality = MF->getFunction()->getPersonalityFn();
949 if (const auto *PF = dyn_cast<Function>(Personality->stripPointerCasts()))
950 MF->getMMI().addPersonality(PF);
951 EHPersonality PersonalityType = classifyEHPersonality(Personality);
953 if (isMSVCEHPersonality(PersonalityType)) {
954 SmallVector<MachineBasicBlock *, 4> ClauseBBs;
955 const IntrinsicInst *ActionsCall =
956 dyn_cast<IntrinsicInst>(LLVMBB->getFirstInsertionPt());
957 // Get all invoke BBs that unwind to this landingpad.
958 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
960 if (ActionsCall && ActionsCall->getIntrinsicID() == Intrinsic::eh_actions) {
961 // If this is a call to llvm.eh.actions followed by indirectbr, then we've
962 // run WinEHPrepare, and we should remove this block from the machine CFG.
963 // Mark the targets of the indirectbr as landingpads instead.
964 for (const BasicBlock *LLVMSucc : successors(LLVMBB)) {
965 MachineBasicBlock *ClauseBB = FuncInfo->MBBMap[LLVMSucc];
966 // Add the edge from the invoke to the clause.
967 for (MachineBasicBlock *InvokeBB : InvokeBBs)
968 InvokeBB->addSuccessor(ClauseBB);
970 // Mark the clause as a landing pad or MI passes will delete it.
971 ClauseBB->setIsEHPad();
975 // Remove the edge from the invoke to the lpad.
976 for (MachineBasicBlock *InvokeBB : InvokeBBs)
977 InvokeBB->removeSuccessor(MBB);
979 // Don't select instructions for the landingpad.
983 // Mark exception register as live in.
984 if (unsigned Reg = TLI->getExceptionPointerRegister())
985 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
987 // Mark exception selector register as live in.
988 if (unsigned Reg = TLI->getExceptionSelectorRegister())
989 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
994 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
995 /// side-effect free and is either dead or folded into a generated instruction.
996 /// Return false if it needs to be emitted.
997 static bool isFoldedOrDeadInstruction(const Instruction *I,
998 FunctionLoweringInfo *FuncInfo) {
999 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
1000 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1001 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1002 !I->isEHPad() && // EH pad instructions aren't folded.
1003 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1007 // Collect per Instruction statistics for fast-isel misses. Only those
1008 // instructions that cause the bail are accounted for. It does not account for
1009 // instructions higher in the block. Thus, summing the per instructions stats
1010 // will not add up to what is reported by NumFastIselFailures.
1011 static void collectFailStats(const Instruction *I) {
1012 switch (I->getOpcode()) {
1013 default: assert (0 && "<Invalid operator> ");
1016 case Instruction::Ret: NumFastIselFailRet++; return;
1017 case Instruction::Br: NumFastIselFailBr++; return;
1018 case Instruction::Switch: NumFastIselFailSwitch++; return;
1019 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1020 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1021 case Instruction::Resume: NumFastIselFailResume++; return;
1022 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1024 // Standard binary operators...
1025 case Instruction::Add: NumFastIselFailAdd++; return;
1026 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1027 case Instruction::Sub: NumFastIselFailSub++; return;
1028 case Instruction::FSub: NumFastIselFailFSub++; return;
1029 case Instruction::Mul: NumFastIselFailMul++; return;
1030 case Instruction::FMul: NumFastIselFailFMul++; return;
1031 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1032 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1033 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1034 case Instruction::URem: NumFastIselFailURem++; return;
1035 case Instruction::SRem: NumFastIselFailSRem++; return;
1036 case Instruction::FRem: NumFastIselFailFRem++; return;
1038 // Logical operators...
1039 case Instruction::And: NumFastIselFailAnd++; return;
1040 case Instruction::Or: NumFastIselFailOr++; return;
1041 case Instruction::Xor: NumFastIselFailXor++; return;
1043 // Memory instructions...
1044 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1045 case Instruction::Load: NumFastIselFailLoad++; return;
1046 case Instruction::Store: NumFastIselFailStore++; return;
1047 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1048 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1049 case Instruction::Fence: NumFastIselFailFence++; return;
1050 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1052 // Convert instructions...
1053 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1054 case Instruction::ZExt: NumFastIselFailZExt++; return;
1055 case Instruction::SExt: NumFastIselFailSExt++; return;
1056 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1057 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1058 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1059 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1060 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1061 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1062 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1063 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1064 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1066 // Other instructions...
1067 case Instruction::ICmp: NumFastIselFailICmp++; return;
1068 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1069 case Instruction::PHI: NumFastIselFailPHI++; return;
1070 case Instruction::Select: NumFastIselFailSelect++; return;
1071 case Instruction::Call: {
1072 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1073 switch (Intrinsic->getIntrinsicID()) {
1075 NumFastIselFailIntrinsicCall++; return;
1076 case Intrinsic::sadd_with_overflow:
1077 NumFastIselFailSAddWithOverflow++; return;
1078 case Intrinsic::uadd_with_overflow:
1079 NumFastIselFailUAddWithOverflow++; return;
1080 case Intrinsic::ssub_with_overflow:
1081 NumFastIselFailSSubWithOverflow++; return;
1082 case Intrinsic::usub_with_overflow:
1083 NumFastIselFailUSubWithOverflow++; return;
1084 case Intrinsic::smul_with_overflow:
1085 NumFastIselFailSMulWithOverflow++; return;
1086 case Intrinsic::umul_with_overflow:
1087 NumFastIselFailUMulWithOverflow++; return;
1088 case Intrinsic::frameaddress:
1089 NumFastIselFailFrameaddress++; return;
1090 case Intrinsic::sqrt:
1091 NumFastIselFailSqrt++; return;
1092 case Intrinsic::experimental_stackmap:
1093 NumFastIselFailStackMap++; return;
1094 case Intrinsic::experimental_patchpoint_void: // fall-through
1095 case Intrinsic::experimental_patchpoint_i64:
1096 NumFastIselFailPatchPoint++; return;
1099 NumFastIselFailCall++;
1102 case Instruction::Shl: NumFastIselFailShl++; return;
1103 case Instruction::LShr: NumFastIselFailLShr++; return;
1104 case Instruction::AShr: NumFastIselFailAShr++; return;
1105 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1106 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1107 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1108 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1109 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1110 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1111 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1116 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1117 // Initialize the Fast-ISel state, if needed.
1118 FastISel *FastIS = nullptr;
1119 if (TM.Options.EnableFastISel)
1120 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1122 // Iterate over all basic blocks in the function.
1123 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1124 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1125 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1126 const BasicBlock *LLVMBB = *I;
1128 if (OptLevel != CodeGenOpt::None) {
1129 bool AllPredsVisited = true;
1130 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1132 if (!FuncInfo->VisitedBBs.count(*PI)) {
1133 AllPredsVisited = false;
1138 if (AllPredsVisited) {
1139 for (BasicBlock::const_iterator I = LLVMBB->begin();
1140 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1141 FuncInfo->ComputePHILiveOutRegInfo(PN);
1143 for (BasicBlock::const_iterator I = LLVMBB->begin();
1144 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1145 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1148 FuncInfo->VisitedBBs.insert(LLVMBB);
1151 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1152 BasicBlock::const_iterator const End = LLVMBB->end();
1153 BasicBlock::const_iterator BI = End;
1155 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1156 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1158 // Setup an EH landing-pad block.
1159 FuncInfo->ExceptionPointerVirtReg = 0;
1160 FuncInfo->ExceptionSelectorVirtReg = 0;
1161 if (LLVMBB->isLandingPad())
1162 if (!PrepareEHLandingPad())
1166 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1168 FastIS->startNewBlock();
1170 // Emit code for any incoming arguments. This must happen before
1171 // beginning FastISel on the entry block.
1172 if (LLVMBB == &Fn.getEntryBlock()) {
1175 // Lower any arguments needed in this block if this is the entry block.
1176 if (!FastIS->lowerArguments()) {
1177 // Fast isel failed to lower these arguments
1178 ++NumFastIselFailLowerArguments;
1179 if (EnableFastISelAbort > 1)
1180 report_fatal_error("FastISel didn't lower all arguments");
1182 // Use SelectionDAG argument lowering
1184 CurDAG->setRoot(SDB->getControlRoot());
1186 CodeGenAndEmitDAG();
1189 // If we inserted any instructions at the beginning, make a note of
1190 // where they are, so we can be sure to emit subsequent instructions
1192 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1193 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1195 FastIS->setLastLocalValue(nullptr);
1198 unsigned NumFastIselRemaining = std::distance(Begin, End);
1199 // Do FastISel on as many instructions as possible.
1200 for (; BI != Begin; --BI) {
1201 const Instruction *Inst = std::prev(BI);
1203 // If we no longer require this instruction, skip it.
1204 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1205 --NumFastIselRemaining;
1209 // Bottom-up: reset the insert pos at the top, after any local-value
1211 FastIS->recomputeInsertPt();
1213 // Try to select the instruction with FastISel.
1214 if (FastIS->selectInstruction(Inst)) {
1215 --NumFastIselRemaining;
1216 ++NumFastIselSuccess;
1217 // If fast isel succeeded, skip over all the folded instructions, and
1218 // then see if there is a load right before the selected instructions.
1219 // Try to fold the load if so.
1220 const Instruction *BeforeInst = Inst;
1221 while (BeforeInst != Begin) {
1222 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1223 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1226 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1227 BeforeInst->hasOneUse() &&
1228 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1229 // If we succeeded, don't re-select the load.
1230 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1231 --NumFastIselRemaining;
1232 ++NumFastIselSuccess;
1238 if (EnableFastISelVerbose2)
1239 collectFailStats(Inst);
1242 // Then handle certain instructions as single-LLVM-Instruction blocks.
1243 if (isa<CallInst>(Inst)) {
1245 if (EnableFastISelVerbose || EnableFastISelAbort) {
1246 dbgs() << "FastISel missed call: ";
1249 if (EnableFastISelAbort > 2)
1250 // FastISel selector couldn't handle something and bailed.
1251 // For the purpose of debugging, just abort.
1252 report_fatal_error("FastISel didn't select the entire block");
1254 if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() &&
1255 !Inst->use_empty()) {
1256 unsigned &R = FuncInfo->ValueMap[Inst];
1258 R = FuncInfo->CreateRegs(Inst->getType());
1261 bool HadTailCall = false;
1262 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1263 SelectBasicBlock(Inst, BI, HadTailCall);
1265 // If the call was emitted as a tail call, we're done with the block.
1266 // We also need to delete any previously emitted instructions.
1268 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1273 // Recompute NumFastIselRemaining as Selection DAG instruction
1274 // selection may have handled the call, input args, etc.
1275 unsigned RemainingNow = std::distance(Begin, BI);
1276 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1277 NumFastIselRemaining = RemainingNow;
1281 bool ShouldAbort = EnableFastISelAbort;
1282 if (EnableFastISelVerbose || EnableFastISelAbort) {
1283 if (isa<TerminatorInst>(Inst)) {
1284 // Use a different message for terminator misses.
1285 dbgs() << "FastISel missed terminator: ";
1286 // Don't abort unless for terminator unless the level is really high
1287 ShouldAbort = (EnableFastISelAbort > 2);
1289 dbgs() << "FastISel miss: ";
1294 // FastISel selector couldn't handle something and bailed.
1295 // For the purpose of debugging, just abort.
1296 report_fatal_error("FastISel didn't select the entire block");
1298 NumFastIselFailures += NumFastIselRemaining;
1302 FastIS->recomputeInsertPt();
1304 // Lower any arguments needed in this block if this is the entry block.
1305 if (LLVMBB == &Fn.getEntryBlock()) {
1314 ++NumFastIselBlocks;
1317 // Run SelectionDAG instruction selection on the remainder of the block
1318 // not handled by FastISel. If FastISel is not run, this is the entire
1321 SelectBasicBlock(Begin, BI, HadTailCall);
1325 FuncInfo->PHINodesToUpdate.clear();
1329 SDB->clearDanglingDebugInfo();
1330 SDB->SPDescriptor.resetPerFunctionState();
1333 /// Given that the input MI is before a partial terminator sequence TSeq, return
1334 /// true if M + TSeq also a partial terminator sequence.
1336 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1337 /// lowering copy vregs into physical registers, which are then passed into
1338 /// terminator instructors so we can satisfy ABI constraints. A partial
1339 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1340 /// may be the whole terminator sequence).
1341 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1342 // If we do not have a copy or an implicit def, we return true if and only if
1343 // MI is a debug value.
1344 if (!MI->isCopy() && !MI->isImplicitDef())
1345 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1346 // physical registers if there is debug info associated with the terminator
1347 // of our mbb. We want to include said debug info in our terminator
1348 // sequence, so we return true in that case.
1349 return MI->isDebugValue();
1351 // We have left the terminator sequence if we are not doing one of the
1354 // 1. Copying a vreg into a physical register.
1355 // 2. Copying a vreg into a vreg.
1356 // 3. Defining a register via an implicit def.
1358 // OPI should always be a register definition...
1359 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1360 if (!OPI->isReg() || !OPI->isDef())
1363 // Defining any register via an implicit def is always ok.
1364 if (MI->isImplicitDef())
1367 // Grab the copy source...
1368 MachineInstr::const_mop_iterator OPI2 = OPI;
1370 assert(OPI2 != MI->operands_end()
1371 && "Should have a copy implying we should have 2 arguments.");
1373 // Make sure that the copy dest is not a vreg when the copy source is a
1374 // physical register.
1375 if (!OPI2->isReg() ||
1376 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1377 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1383 /// Find the split point at which to splice the end of BB into its success stack
1384 /// protector check machine basic block.
1386 /// On many platforms, due to ABI constraints, terminators, even before register
1387 /// allocation, use physical registers. This creates an issue for us since
1388 /// physical registers at this point can not travel across basic
1389 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1390 /// when they enter functions and moves them through a sequence of copies back
1391 /// into the physical registers right before the terminator creating a
1392 /// ``Terminator Sequence''. This function is searching for the beginning of the
1393 /// terminator sequence so that we can ensure that we splice off not just the
1394 /// terminator, but additionally the copies that move the vregs into the
1395 /// physical registers.
1396 static MachineBasicBlock::iterator
1397 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1398 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1400 if (SplitPoint == BB->begin())
1403 MachineBasicBlock::iterator Start = BB->begin();
1404 MachineBasicBlock::iterator Previous = SplitPoint;
1407 while (MIIsInTerminatorSequence(Previous)) {
1408 SplitPoint = Previous;
1409 if (Previous == Start)
1418 SelectionDAGISel::FinishBasicBlock() {
1420 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1421 << FuncInfo->PHINodesToUpdate.size() << "\n";
1422 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1423 dbgs() << "Node " << i << " : ("
1424 << FuncInfo->PHINodesToUpdate[i].first
1425 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1427 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1428 // PHI nodes in successors.
1429 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1430 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1431 assert(PHI->isPHI() &&
1432 "This is not a machine PHI node that we are updating!");
1433 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1435 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1438 // Handle stack protector.
1439 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1440 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1441 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1443 // Find the split point to split the parent mbb. At the same time copy all
1444 // physical registers used in the tail of parent mbb into virtual registers
1445 // before the split point and back into physical registers after the split
1446 // point. This prevents us needing to deal with Live-ins and many other
1447 // register allocation issues caused by us splitting the parent mbb. The
1448 // register allocator will clean up said virtual copies later on.
1449 MachineBasicBlock::iterator SplitPoint =
1450 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1452 // Splice the terminator of ParentMBB into SuccessMBB.
1453 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1457 // Add compare/jump on neq/jump to the parent BB.
1458 FuncInfo->MBB = ParentMBB;
1459 FuncInfo->InsertPt = ParentMBB->end();
1460 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1461 CurDAG->setRoot(SDB->getRoot());
1463 CodeGenAndEmitDAG();
1465 // CodeGen Failure MBB if we have not codegened it yet.
1466 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1467 if (!FailureMBB->size()) {
1468 FuncInfo->MBB = FailureMBB;
1469 FuncInfo->InsertPt = FailureMBB->end();
1470 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1471 CurDAG->setRoot(SDB->getRoot());
1473 CodeGenAndEmitDAG();
1476 // Clear the Per-BB State.
1477 SDB->SPDescriptor.resetPerBBState();
1480 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1481 // Lower header first, if it wasn't already lowered
1482 if (!SDB->BitTestCases[i].Emitted) {
1483 // Set the current basic block to the mbb we wish to insert the code into
1484 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1485 FuncInfo->InsertPt = FuncInfo->MBB->end();
1487 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1488 CurDAG->setRoot(SDB->getRoot());
1490 CodeGenAndEmitDAG();
1493 uint32_t UnhandledWeight = SDB->BitTestCases[i].Weight;
1495 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1496 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1497 // Set the current basic block to the mbb we wish to insert the code into
1498 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1499 FuncInfo->InsertPt = FuncInfo->MBB->end();
1502 // If all cases cover a contiguous range, it is not necessary to jump to
1503 // the default block after the last bit test fails. This is because the
1504 // range check during bit test header creation has guaranteed that every
1505 // case here doesn't go outside the range.
1506 MachineBasicBlock *NextMBB;
1507 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1508 NextMBB = SDB->BitTestCases[i].Cases[j + 1].TargetBB;
1509 else if (j + 1 != ej)
1510 NextMBB = SDB->BitTestCases[i].Cases[j + 1].ThisBB;
1512 NextMBB = SDB->BitTestCases[i].Default;
1514 SDB->visitBitTestCase(SDB->BitTestCases[i],
1517 SDB->BitTestCases[i].Reg,
1518 SDB->BitTestCases[i].Cases[j],
1521 CurDAG->setRoot(SDB->getRoot());
1523 CodeGenAndEmitDAG();
1525 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1530 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1532 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1533 MachineBasicBlock *PHIBB = PHI->getParent();
1534 assert(PHI->isPHI() &&
1535 "This is not a machine PHI node that we are updating!");
1536 // This is "default" BB. We have two jumps to it. From "header" BB and
1537 // from last "case" BB.
1538 if (PHIBB == SDB->BitTestCases[i].Default)
1539 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1540 .addMBB(SDB->BitTestCases[i].Parent)
1541 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1542 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1543 // One of "cases" BB.
1544 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1546 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1547 if (cBB->isSuccessor(PHIBB))
1548 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1552 SDB->BitTestCases.clear();
1554 // If the JumpTable record is filled in, then we need to emit a jump table.
1555 // Updating the PHI nodes is tricky in this case, since we need to determine
1556 // whether the PHI is a successor of the range check MBB or the jump table MBB
1557 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1558 // Lower header first, if it wasn't already lowered
1559 if (!SDB->JTCases[i].first.Emitted) {
1560 // Set the current basic block to the mbb we wish to insert the code into
1561 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1562 FuncInfo->InsertPt = FuncInfo->MBB->end();
1564 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1566 CurDAG->setRoot(SDB->getRoot());
1568 CodeGenAndEmitDAG();
1571 // Set the current basic block to the mbb we wish to insert the code into
1572 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1573 FuncInfo->InsertPt = FuncInfo->MBB->end();
1575 SDB->visitJumpTable(SDB->JTCases[i].second);
1576 CurDAG->setRoot(SDB->getRoot());
1578 CodeGenAndEmitDAG();
1581 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1583 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1584 MachineBasicBlock *PHIBB = PHI->getParent();
1585 assert(PHI->isPHI() &&
1586 "This is not a machine PHI node that we are updating!");
1587 // "default" BB. We can go there only from header BB.
1588 if (PHIBB == SDB->JTCases[i].second.Default)
1589 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1590 .addMBB(SDB->JTCases[i].first.HeaderBB);
1591 // JT BB. Just iterate over successors here
1592 if (FuncInfo->MBB->isSuccessor(PHIBB))
1593 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1596 SDB->JTCases.clear();
1598 // If we generated any switch lowering information, build and codegen any
1599 // additional DAGs necessary.
1600 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1601 // Set the current basic block to the mbb we wish to insert the code into
1602 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1603 FuncInfo->InsertPt = FuncInfo->MBB->end();
1605 // Determine the unique successors.
1606 SmallVector<MachineBasicBlock *, 2> Succs;
1607 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1608 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1609 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1611 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1612 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1613 CurDAG->setRoot(SDB->getRoot());
1615 CodeGenAndEmitDAG();
1617 // Remember the last block, now that any splitting is done, for use in
1618 // populating PHI nodes in successors.
1619 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1621 // Handle any PHI nodes in successors of this chunk, as if we were coming
1622 // from the original BB before switch expansion. Note that PHI nodes can
1623 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1624 // handle them the right number of times.
1625 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1626 FuncInfo->MBB = Succs[i];
1627 FuncInfo->InsertPt = FuncInfo->MBB->end();
1628 // FuncInfo->MBB may have been removed from the CFG if a branch was
1630 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1631 for (MachineBasicBlock::iterator
1632 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1633 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1634 MachineInstrBuilder PHI(*MF, MBBI);
1635 // This value for this PHI node is recorded in PHINodesToUpdate.
1636 for (unsigned pn = 0; ; ++pn) {
1637 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1638 "Didn't find PHI entry!");
1639 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1640 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1648 SDB->SwitchCases.clear();
1652 /// Create the scheduler. If a specific scheduler was specified
1653 /// via the SchedulerRegistry, use it, otherwise select the
1654 /// one preferred by the target.
1656 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1657 return ISHeuristic(this, OptLevel);
1660 //===----------------------------------------------------------------------===//
1661 // Helper functions used by the generated instruction selector.
1662 //===----------------------------------------------------------------------===//
1663 // Calls to these methods are generated by tblgen.
1665 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1666 /// the dag combiner simplified the 255, we still want to match. RHS is the
1667 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1668 /// specified in the .td file (e.g. 255).
1669 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1670 int64_t DesiredMaskS) const {
1671 const APInt &ActualMask = RHS->getAPIntValue();
1672 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1674 // If the actual mask exactly matches, success!
1675 if (ActualMask == DesiredMask)
1678 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1679 if (ActualMask.intersects(~DesiredMask))
1682 // Otherwise, the DAG Combiner may have proven that the value coming in is
1683 // either already zero or is not demanded. Check for known zero input bits.
1684 APInt NeededMask = DesiredMask & ~ActualMask;
1685 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1688 // TODO: check to see if missing bits are just not demanded.
1690 // Otherwise, this pattern doesn't match.
1694 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1695 /// the dag combiner simplified the 255, we still want to match. RHS is the
1696 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1697 /// specified in the .td file (e.g. 255).
1698 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1699 int64_t DesiredMaskS) const {
1700 const APInt &ActualMask = RHS->getAPIntValue();
1701 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1703 // If the actual mask exactly matches, success!
1704 if (ActualMask == DesiredMask)
1707 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1708 if (ActualMask.intersects(~DesiredMask))
1711 // Otherwise, the DAG Combiner may have proven that the value coming in is
1712 // either already zero or is not demanded. Check for known zero input bits.
1713 APInt NeededMask = DesiredMask & ~ActualMask;
1715 APInt KnownZero, KnownOne;
1716 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1718 // If all the missing bits in the or are already known to be set, match!
1719 if ((NeededMask & KnownOne) == NeededMask)
1722 // TODO: check to see if missing bits are just not demanded.
1724 // Otherwise, this pattern doesn't match.
1728 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1729 /// by tblgen. Others should not call it.
1730 void SelectionDAGISel::
1731 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL) {
1732 std::vector<SDValue> InOps;
1733 std::swap(InOps, Ops);
1735 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1736 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1737 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1738 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1740 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1741 if (InOps[e-1].getValueType() == MVT::Glue)
1742 --e; // Don't process a glue operand if it is here.
1745 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1746 if (!InlineAsm::isMemKind(Flags)) {
1747 // Just skip over this operand, copying the operands verbatim.
1748 Ops.insert(Ops.end(), InOps.begin()+i,
1749 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1750 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1752 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1753 "Memory operand with multiple values?");
1755 unsigned TiedToOperand;
1756 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1757 // We need the constraint ID from the operand this is tied to.
1758 unsigned CurOp = InlineAsm::Op_FirstOperand;
1759 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1760 for (; TiedToOperand; --TiedToOperand) {
1761 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1762 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1766 // Otherwise, this is a memory operand. Ask the target to select it.
1767 std::vector<SDValue> SelOps;
1768 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1769 InlineAsm::getMemoryConstraintID(Flags),
1771 report_fatal_error("Could not match memory address. Inline asm"
1774 // Add this to the output node.
1776 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1777 Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
1778 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1783 // Add the glue input back if present.
1784 if (e != InOps.size())
1785 Ops.push_back(InOps.back());
1788 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1791 static SDNode *findGlueUse(SDNode *N) {
1792 unsigned FlagResNo = N->getNumValues()-1;
1793 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1794 SDUse &Use = I.getUse();
1795 if (Use.getResNo() == FlagResNo)
1796 return Use.getUser();
1801 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1802 /// This function recursively traverses up the operand chain, ignoring
1804 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1805 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1806 bool IgnoreChains) {
1807 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1808 // greater than all of its (recursive) operands. If we scan to a point where
1809 // 'use' is smaller than the node we're scanning for, then we know we will
1812 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1813 // happen because we scan down to newly selected nodes in the case of glue
1815 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1818 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1819 // won't fail if we scan it again.
1820 if (!Visited.insert(Use).second)
1823 for (const SDValue &Op : Use->op_values()) {
1824 // Ignore chain uses, they are validated by HandleMergeInputChains.
1825 if (Op.getValueType() == MVT::Other && IgnoreChains)
1828 SDNode *N = Op.getNode();
1830 if (Use == ImmedUse || Use == Root)
1831 continue; // We are not looking for immediate use.
1836 // Traverse up the operand chain.
1837 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1843 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1844 /// operand node N of U during instruction selection that starts at Root.
1845 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1846 SDNode *Root) const {
1847 if (OptLevel == CodeGenOpt::None) return false;
1848 return N.hasOneUse();
1851 /// IsLegalToFold - Returns true if the specific operand node N of
1852 /// U can be folded during instruction selection that starts at Root.
1853 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1854 CodeGenOpt::Level OptLevel,
1855 bool IgnoreChains) {
1856 if (OptLevel == CodeGenOpt::None) return false;
1858 // If Root use can somehow reach N through a path that that doesn't contain
1859 // U then folding N would create a cycle. e.g. In the following
1860 // diagram, Root can reach N through X. If N is folded into into Root, then
1861 // X is both a predecessor and a successor of U.
1872 // * indicates nodes to be folded together.
1874 // If Root produces glue, then it gets (even more) interesting. Since it
1875 // will be "glued" together with its glue use in the scheduler, we need to
1876 // check if it might reach N.
1895 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1896 // (call it Fold), then X is a predecessor of GU and a successor of
1897 // Fold. But since Fold and GU are glued together, this will create
1898 // a cycle in the scheduling graph.
1900 // If the node has glue, walk down the graph to the "lowest" node in the
1902 EVT VT = Root->getValueType(Root->getNumValues()-1);
1903 while (VT == MVT::Glue) {
1904 SDNode *GU = findGlueUse(Root);
1908 VT = Root->getValueType(Root->getNumValues()-1);
1910 // If our query node has a glue result with a use, we've walked up it. If
1911 // the user (which has already been selected) has a chain or indirectly uses
1912 // the chain, our WalkChainUsers predicate will not consider it. Because of
1913 // this, we cannot ignore chains in this predicate.
1914 IgnoreChains = false;
1918 SmallPtrSet<SDNode*, 16> Visited;
1919 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1922 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1925 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1926 SelectInlineAsmMemoryOperands(Ops, DL);
1928 const EVT VTs[] = {MVT::Other, MVT::Glue};
1929 SDValue New = CurDAG->getNode(ISD::INLINEASM, DL, VTs, Ops);
1931 return New.getNode();
1935 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1937 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1938 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1940 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0),
1942 SDValue New = CurDAG->getCopyFromReg(
1943 Op->getOperand(0), dl, Reg, Op->getValueType(0));
1945 return New.getNode();
1949 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1951 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1952 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1953 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1954 Op->getOperand(2).getValueType(),
1956 SDValue New = CurDAG->getCopyToReg(
1957 Op->getOperand(0), dl, Reg, Op->getOperand(2));
1959 return New.getNode();
1964 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1965 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1968 /// GetVBR - decode a vbr encoding whose top bit is set.
1969 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1970 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1971 assert(Val >= 128 && "Not a VBR");
1972 Val &= 127; // Remove first vbr bit.
1977 NextBits = MatcherTable[Idx++];
1978 Val |= (NextBits&127) << Shift;
1980 } while (NextBits & 128);
1986 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1987 /// interior glue and chain results to use the new glue and chain results.
1988 void SelectionDAGISel::
1989 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1990 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1992 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1993 bool isMorphNodeTo) {
1994 SmallVector<SDNode*, 4> NowDeadNodes;
1996 // Now that all the normal results are replaced, we replace the chain and
1997 // glue results if present.
1998 if (!ChainNodesMatched.empty()) {
1999 assert(InputChain.getNode() &&
2000 "Matched input chains but didn't produce a chain");
2001 // Loop over all of the nodes we matched that produced a chain result.
2002 // Replace all the chain results with the final chain we ended up with.
2003 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2004 SDNode *ChainNode = ChainNodesMatched[i];
2006 // If this node was already deleted, don't look at it.
2007 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2010 // Don't replace the results of the root node if we're doing a
2012 if (ChainNode == NodeToMatch && isMorphNodeTo)
2015 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2016 if (ChainVal.getValueType() == MVT::Glue)
2017 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2018 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2019 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2021 // If the node became dead and we haven't already seen it, delete it.
2022 if (ChainNode->use_empty() &&
2023 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2024 NowDeadNodes.push_back(ChainNode);
2028 // If the result produces glue, update any glue results in the matched
2029 // pattern with the glue result.
2030 if (InputGlue.getNode()) {
2031 // Handle any interior nodes explicitly marked.
2032 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2033 SDNode *FRN = GlueResultNodesMatched[i];
2035 // If this node was already deleted, don't look at it.
2036 if (FRN->getOpcode() == ISD::DELETED_NODE)
2039 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2040 "Doesn't have a glue result");
2041 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2044 // If the node became dead and we haven't already seen it, delete it.
2045 if (FRN->use_empty() &&
2046 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2047 NowDeadNodes.push_back(FRN);
2051 if (!NowDeadNodes.empty())
2052 CurDAG->RemoveDeadNodes(NowDeadNodes);
2054 DEBUG(dbgs() << "ISEL: Match complete!\n");
2060 CR_LeadsToInteriorNode
2063 /// WalkChainUsers - Walk down the users of the specified chained node that is
2064 /// part of the pattern we're matching, looking at all of the users we find.
2065 /// This determines whether something is an interior node, whether we have a
2066 /// non-pattern node in between two pattern nodes (which prevent folding because
2067 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2068 /// between pattern nodes (in which case the TF becomes part of the pattern).
2070 /// The walk we do here is guaranteed to be small because we quickly get down to
2071 /// already selected nodes "below" us.
2073 WalkChainUsers(const SDNode *ChainedNode,
2074 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2075 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2076 ChainResult Result = CR_Simple;
2078 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2079 E = ChainedNode->use_end(); UI != E; ++UI) {
2080 // Make sure the use is of the chain, not some other value we produce.
2081 if (UI.getUse().getValueType() != MVT::Other) continue;
2085 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2088 // If we see an already-selected machine node, then we've gone beyond the
2089 // pattern that we're selecting down into the already selected chunk of the
2091 unsigned UserOpcode = User->getOpcode();
2092 if (User->isMachineOpcode() ||
2093 UserOpcode == ISD::CopyToReg ||
2094 UserOpcode == ISD::CopyFromReg ||
2095 UserOpcode == ISD::INLINEASM ||
2096 UserOpcode == ISD::EH_LABEL ||
2097 UserOpcode == ISD::LIFETIME_START ||
2098 UserOpcode == ISD::LIFETIME_END) {
2099 // If their node ID got reset to -1 then they've already been selected.
2100 // Treat them like a MachineOpcode.
2101 if (User->getNodeId() == -1)
2105 // If we have a TokenFactor, we handle it specially.
2106 if (User->getOpcode() != ISD::TokenFactor) {
2107 // If the node isn't a token factor and isn't part of our pattern, then it
2108 // must be a random chained node in between two nodes we're selecting.
2109 // This happens when we have something like:
2114 // Because we structurally match the load/store as a read/modify/write,
2115 // but the call is chained between them. We cannot fold in this case
2116 // because it would induce a cycle in the graph.
2117 if (!std::count(ChainedNodesInPattern.begin(),
2118 ChainedNodesInPattern.end(), User))
2119 return CR_InducesCycle;
2121 // Otherwise we found a node that is part of our pattern. For example in:
2125 // This would happen when we're scanning down from the load and see the
2126 // store as a user. Record that there is a use of ChainedNode that is
2127 // part of the pattern and keep scanning uses.
2128 Result = CR_LeadsToInteriorNode;
2129 InteriorChainedNodes.push_back(User);
2133 // If we found a TokenFactor, there are two cases to consider: first if the
2134 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2135 // uses of the TF are in our pattern) we just want to ignore it. Second,
2136 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2142 // | \ DAG's like cheese
2145 // [TokenFactor] [Op]
2152 // In this case, the TokenFactor becomes part of our match and we rewrite it
2153 // as a new TokenFactor.
2155 // To distinguish these two cases, do a recursive walk down the uses.
2156 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2158 // If the uses of the TokenFactor are just already-selected nodes, ignore
2159 // it, it is "below" our pattern.
2161 case CR_InducesCycle:
2162 // If the uses of the TokenFactor lead to nodes that are not part of our
2163 // pattern that are not selected, folding would turn this into a cycle,
2165 return CR_InducesCycle;
2166 case CR_LeadsToInteriorNode:
2167 break; // Otherwise, keep processing.
2170 // Okay, we know we're in the interesting interior case. The TokenFactor
2171 // is now going to be considered part of the pattern so that we rewrite its
2172 // uses (it may have uses that are not part of the pattern) with the
2173 // ultimate chain result of the generated code. We will also add its chain
2174 // inputs as inputs to the ultimate TokenFactor we create.
2175 Result = CR_LeadsToInteriorNode;
2176 ChainedNodesInPattern.push_back(User);
2177 InteriorChainedNodes.push_back(User);
2184 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2185 /// operation for when the pattern matched at least one node with a chains. The
2186 /// input vector contains a list of all of the chained nodes that we match. We
2187 /// must determine if this is a valid thing to cover (i.e. matching it won't
2188 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2189 /// be used as the input node chain for the generated nodes.
2191 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2192 SelectionDAG *CurDAG) {
2193 // Walk all of the chained nodes we've matched, recursively scanning down the
2194 // users of the chain result. This adds any TokenFactor nodes that are caught
2195 // in between chained nodes to the chained and interior nodes list.
2196 SmallVector<SDNode*, 3> InteriorChainedNodes;
2197 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2198 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2199 InteriorChainedNodes) == CR_InducesCycle)
2200 return SDValue(); // Would induce a cycle.
2203 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2204 // that we are interested in. Form our input TokenFactor node.
2205 SmallVector<SDValue, 3> InputChains;
2206 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2207 // Add the input chain of this node to the InputChains list (which will be
2208 // the operands of the generated TokenFactor) if it's not an interior node.
2209 SDNode *N = ChainNodesMatched[i];
2210 if (N->getOpcode() != ISD::TokenFactor) {
2211 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2214 // Otherwise, add the input chain.
2215 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2216 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2217 InputChains.push_back(InChain);
2221 // If we have a token factor, we want to add all inputs of the token factor
2222 // that are not part of the pattern we're matching.
2223 for (const SDValue &Op : N->op_values()) {
2224 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2226 InputChains.push_back(Op);
2230 if (InputChains.size() == 1)
2231 return InputChains[0];
2232 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2233 MVT::Other, InputChains);
2236 /// MorphNode - Handle morphing a node in place for the selector.
2237 SDNode *SelectionDAGISel::
2238 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2239 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2240 // It is possible we're using MorphNodeTo to replace a node with no
2241 // normal results with one that has a normal result (or we could be
2242 // adding a chain) and the input could have glue and chains as well.
2243 // In this case we need to shift the operands down.
2244 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2245 // than the old isel though.
2246 int OldGlueResultNo = -1, OldChainResultNo = -1;
2248 unsigned NTMNumResults = Node->getNumValues();
2249 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2250 OldGlueResultNo = NTMNumResults-1;
2251 if (NTMNumResults != 1 &&
2252 Node->getValueType(NTMNumResults-2) == MVT::Other)
2253 OldChainResultNo = NTMNumResults-2;
2254 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2255 OldChainResultNo = NTMNumResults-1;
2257 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2258 // that this deletes operands of the old node that become dead.
2259 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2261 // MorphNodeTo can operate in two ways: if an existing node with the
2262 // specified operands exists, it can just return it. Otherwise, it
2263 // updates the node in place to have the requested operands.
2265 // If we updated the node in place, reset the node ID. To the isel,
2266 // this should be just like a newly allocated machine node.
2270 unsigned ResNumResults = Res->getNumValues();
2271 // Move the glue if needed.
2272 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2273 (unsigned)OldGlueResultNo != ResNumResults-1)
2274 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2275 SDValue(Res, ResNumResults-1));
2277 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2280 // Move the chain reference if needed.
2281 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2282 (unsigned)OldChainResultNo != ResNumResults-1)
2283 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2284 SDValue(Res, ResNumResults-1));
2286 // Otherwise, no replacement happened because the node already exists. Replace
2287 // Uses of the old node with the new one.
2289 CurDAG->ReplaceAllUsesWith(Node, Res);
2294 /// CheckSame - Implements OP_CheckSame.
2295 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2296 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2298 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2299 // Accept if it is exactly the same as a previously recorded node.
2300 unsigned RecNo = MatcherTable[MatcherIndex++];
2301 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2302 return N == RecordedNodes[RecNo].first;
2305 /// CheckChildSame - Implements OP_CheckChildXSame.
2306 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2307 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2309 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2311 if (ChildNo >= N.getNumOperands())
2312 return false; // Match fails if out of range child #.
2313 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2317 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2318 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2319 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2320 const SelectionDAGISel &SDISel) {
2321 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2324 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2325 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2326 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2327 const SelectionDAGISel &SDISel, SDNode *N) {
2328 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2331 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2332 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2334 uint16_t Opc = MatcherTable[MatcherIndex++];
2335 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2336 return N->getOpcode() == Opc;
2339 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2340 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
2341 const TargetLowering *TLI, const DataLayout &DL) {
2342 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2343 if (N.getValueType() == VT) return true;
2345 // Handle the case when VT is iPTR.
2346 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(DL);
2349 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2350 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2351 SDValue N, const TargetLowering *TLI, const DataLayout &DL,
2353 if (ChildNo >= N.getNumOperands())
2354 return false; // Match fails if out of range child #.
2355 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI,
2359 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2360 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2362 return cast<CondCodeSDNode>(N)->get() ==
2363 (ISD::CondCode)MatcherTable[MatcherIndex++];
2366 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2367 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2368 SDValue N, const TargetLowering *TLI, const DataLayout &DL) {
2369 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2370 if (cast<VTSDNode>(N)->getVT() == VT)
2373 // Handle the case when VT is iPTR.
2374 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL);
2377 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2378 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2380 int64_t Val = MatcherTable[MatcherIndex++];
2382 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2384 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2385 return C && C->getSExtValue() == Val;
2388 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2389 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2390 SDValue N, unsigned ChildNo) {
2391 if (ChildNo >= N.getNumOperands())
2392 return false; // Match fails if out of range child #.
2393 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2396 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2397 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2398 SDValue N, const SelectionDAGISel &SDISel) {
2399 int64_t Val = MatcherTable[MatcherIndex++];
2401 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2403 if (N->getOpcode() != ISD::AND) return false;
2405 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2406 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2409 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2410 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2411 SDValue N, const SelectionDAGISel &SDISel) {
2412 int64_t Val = MatcherTable[MatcherIndex++];
2414 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2416 if (N->getOpcode() != ISD::OR) return false;
2418 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2419 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2422 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2423 /// scope, evaluate the current node. If the current predicate is known to
2424 /// fail, set Result=true and return anything. If the current predicate is
2425 /// known to pass, set Result=false and return the MatcherIndex to continue
2426 /// with. If the current predicate is unknown, set Result=false and return the
2427 /// MatcherIndex to continue with.
2428 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2429 unsigned Index, SDValue N,
2431 const SelectionDAGISel &SDISel,
2432 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2433 switch (Table[Index++]) {
2436 return Index-1; // Could not evaluate this predicate.
2437 case SelectionDAGISel::OPC_CheckSame:
2438 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2440 case SelectionDAGISel::OPC_CheckChild0Same:
2441 case SelectionDAGISel::OPC_CheckChild1Same:
2442 case SelectionDAGISel::OPC_CheckChild2Same:
2443 case SelectionDAGISel::OPC_CheckChild3Same:
2444 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2445 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2447 case SelectionDAGISel::OPC_CheckPatternPredicate:
2448 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2450 case SelectionDAGISel::OPC_CheckPredicate:
2451 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2453 case SelectionDAGISel::OPC_CheckOpcode:
2454 Result = !::CheckOpcode(Table, Index, N.getNode());
2456 case SelectionDAGISel::OPC_CheckType:
2457 Result = !::CheckType(Table, Index, N, SDISel.TLI,
2458 SDISel.CurDAG->getDataLayout());
2460 case SelectionDAGISel::OPC_CheckChild0Type:
2461 case SelectionDAGISel::OPC_CheckChild1Type:
2462 case SelectionDAGISel::OPC_CheckChild2Type:
2463 case SelectionDAGISel::OPC_CheckChild3Type:
2464 case SelectionDAGISel::OPC_CheckChild4Type:
2465 case SelectionDAGISel::OPC_CheckChild5Type:
2466 case SelectionDAGISel::OPC_CheckChild6Type:
2467 case SelectionDAGISel::OPC_CheckChild7Type:
2468 Result = !::CheckChildType(
2469 Table, Index, N, SDISel.TLI, SDISel.CurDAG->getDataLayout(),
2470 Table[Index - 1] - SelectionDAGISel::OPC_CheckChild0Type);
2472 case SelectionDAGISel::OPC_CheckCondCode:
2473 Result = !::CheckCondCode(Table, Index, N);
2475 case SelectionDAGISel::OPC_CheckValueType:
2476 Result = !::CheckValueType(Table, Index, N, SDISel.TLI,
2477 SDISel.CurDAG->getDataLayout());
2479 case SelectionDAGISel::OPC_CheckInteger:
2480 Result = !::CheckInteger(Table, Index, N);
2482 case SelectionDAGISel::OPC_CheckChild0Integer:
2483 case SelectionDAGISel::OPC_CheckChild1Integer:
2484 case SelectionDAGISel::OPC_CheckChild2Integer:
2485 case SelectionDAGISel::OPC_CheckChild3Integer:
2486 case SelectionDAGISel::OPC_CheckChild4Integer:
2487 Result = !::CheckChildInteger(Table, Index, N,
2488 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2490 case SelectionDAGISel::OPC_CheckAndImm:
2491 Result = !::CheckAndImm(Table, Index, N, SDISel);
2493 case SelectionDAGISel::OPC_CheckOrImm:
2494 Result = !::CheckOrImm(Table, Index, N, SDISel);
2502 /// FailIndex - If this match fails, this is the index to continue with.
2505 /// NodeStack - The node stack when the scope was formed.
2506 SmallVector<SDValue, 4> NodeStack;
2508 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2509 unsigned NumRecordedNodes;
2511 /// NumMatchedMemRefs - The number of matched memref entries.
2512 unsigned NumMatchedMemRefs;
2514 /// InputChain/InputGlue - The current chain/glue
2515 SDValue InputChain, InputGlue;
2517 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2518 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2521 /// \\brief A DAG update listener to keep the matching state
2522 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2523 /// change the DAG while matching. X86 addressing mode matcher is an example
2525 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2527 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2528 SmallVectorImpl<MatchScope> &MatchScopes;
2530 MatchStateUpdater(SelectionDAG &DAG,
2531 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2532 SmallVectorImpl<MatchScope> &MS) :
2533 SelectionDAG::DAGUpdateListener(DAG),
2534 RecordedNodes(RN), MatchScopes(MS) { }
2536 void NodeDeleted(SDNode *N, SDNode *E) override {
2537 // Some early-returns here to avoid the search if we deleted the node or
2538 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2539 // do, so it's unnecessary to update matching state at that point).
2540 // Neither of these can occur currently because we only install this
2541 // update listener during matching a complex patterns.
2542 if (!E || E->isMachineOpcode())
2544 // Performing linear search here does not matter because we almost never
2545 // run this code. You'd have to have a CSE during complex pattern
2547 for (auto &I : RecordedNodes)
2548 if (I.first.getNode() == N)
2551 for (auto &I : MatchScopes)
2552 for (auto &J : I.NodeStack)
2553 if (J.getNode() == N)
2559 SDNode *SelectionDAGISel::
2560 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2561 unsigned TableSize) {
2562 // FIXME: Should these even be selected? Handle these cases in the caller?
2563 switch (NodeToMatch->getOpcode()) {
2566 case ISD::EntryToken: // These nodes remain the same.
2567 case ISD::BasicBlock:
2569 case ISD::RegisterMask:
2570 case ISD::HANDLENODE:
2571 case ISD::MDNODE_SDNODE:
2572 case ISD::TargetConstant:
2573 case ISD::TargetConstantFP:
2574 case ISD::TargetConstantPool:
2575 case ISD::TargetFrameIndex:
2576 case ISD::TargetExternalSymbol:
2578 case ISD::TargetBlockAddress:
2579 case ISD::TargetJumpTable:
2580 case ISD::TargetGlobalTLSAddress:
2581 case ISD::TargetGlobalAddress:
2582 case ISD::TokenFactor:
2583 case ISD::CopyFromReg:
2584 case ISD::CopyToReg:
2586 case ISD::LIFETIME_START:
2587 case ISD::LIFETIME_END:
2588 NodeToMatch->setNodeId(-1); // Mark selected.
2590 case ISD::AssertSext:
2591 case ISD::AssertZext:
2592 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2593 NodeToMatch->getOperand(0));
2595 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2596 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2597 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2598 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2601 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2603 // Set up the node stack with NodeToMatch as the only node on the stack.
2604 SmallVector<SDValue, 8> NodeStack;
2605 SDValue N = SDValue(NodeToMatch, 0);
2606 NodeStack.push_back(N);
2608 // MatchScopes - Scopes used when matching, if a match failure happens, this
2609 // indicates where to continue checking.
2610 SmallVector<MatchScope, 8> MatchScopes;
2612 // RecordedNodes - This is the set of nodes that have been recorded by the
2613 // state machine. The second value is the parent of the node, or null if the
2614 // root is recorded.
2615 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2617 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2619 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2621 // These are the current input chain and glue for use when generating nodes.
2622 // Various Emit operations change these. For example, emitting a copytoreg
2623 // uses and updates these.
2624 SDValue InputChain, InputGlue;
2626 // ChainNodesMatched - If a pattern matches nodes that have input/output
2627 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2628 // which ones they are. The result is captured into this list so that we can
2629 // update the chain results when the pattern is complete.
2630 SmallVector<SDNode*, 3> ChainNodesMatched;
2631 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2633 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2634 NodeToMatch->dump(CurDAG);
2637 // Determine where to start the interpreter. Normally we start at opcode #0,
2638 // but if the state machine starts with an OPC_SwitchOpcode, then we
2639 // accelerate the first lookup (which is guaranteed to be hot) with the
2640 // OpcodeOffset table.
2641 unsigned MatcherIndex = 0;
2643 if (!OpcodeOffset.empty()) {
2644 // Already computed the OpcodeOffset table, just index into it.
2645 if (N.getOpcode() < OpcodeOffset.size())
2646 MatcherIndex = OpcodeOffset[N.getOpcode()];
2647 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2649 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2650 // Otherwise, the table isn't computed, but the state machine does start
2651 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2652 // is the first time we're selecting an instruction.
2655 // Get the size of this case.
2656 unsigned CaseSize = MatcherTable[Idx++];
2658 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2659 if (CaseSize == 0) break;
2661 // Get the opcode, add the index to the table.
2662 uint16_t Opc = MatcherTable[Idx++];
2663 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2664 if (Opc >= OpcodeOffset.size())
2665 OpcodeOffset.resize((Opc+1)*2);
2666 OpcodeOffset[Opc] = Idx;
2670 // Okay, do the lookup for the first opcode.
2671 if (N.getOpcode() < OpcodeOffset.size())
2672 MatcherIndex = OpcodeOffset[N.getOpcode()];
2676 assert(MatcherIndex < TableSize && "Invalid index");
2678 unsigned CurrentOpcodeIndex = MatcherIndex;
2680 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2683 // Okay, the semantics of this operation are that we should push a scope
2684 // then evaluate the first child. However, pushing a scope only to have
2685 // the first check fail (which then pops it) is inefficient. If we can
2686 // determine immediately that the first check (or first several) will
2687 // immediately fail, don't even bother pushing a scope for them.
2691 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2692 if (NumToSkip & 128)
2693 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2694 // Found the end of the scope with no match.
2695 if (NumToSkip == 0) {
2700 FailIndex = MatcherIndex+NumToSkip;
2702 unsigned MatcherIndexOfPredicate = MatcherIndex;
2703 (void)MatcherIndexOfPredicate; // silence warning.
2705 // If we can't evaluate this predicate without pushing a scope (e.g. if
2706 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2707 // push the scope and evaluate the full predicate chain.
2709 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2710 Result, *this, RecordedNodes);
2714 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2715 << "index " << MatcherIndexOfPredicate
2716 << ", continuing at " << FailIndex << "\n");
2717 ++NumDAGIselRetries;
2719 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2720 // move to the next case.
2721 MatcherIndex = FailIndex;
2724 // If the whole scope failed to match, bail.
2725 if (FailIndex == 0) break;
2727 // Push a MatchScope which indicates where to go if the first child fails
2729 MatchScope NewEntry;
2730 NewEntry.FailIndex = FailIndex;
2731 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2732 NewEntry.NumRecordedNodes = RecordedNodes.size();
2733 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2734 NewEntry.InputChain = InputChain;
2735 NewEntry.InputGlue = InputGlue;
2736 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2737 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2738 MatchScopes.push_back(NewEntry);
2741 case OPC_RecordNode: {
2742 // Remember this node, it may end up being an operand in the pattern.
2743 SDNode *Parent = nullptr;
2744 if (NodeStack.size() > 1)
2745 Parent = NodeStack[NodeStack.size()-2].getNode();
2746 RecordedNodes.push_back(std::make_pair(N, Parent));
2750 case OPC_RecordChild0: case OPC_RecordChild1:
2751 case OPC_RecordChild2: case OPC_RecordChild3:
2752 case OPC_RecordChild4: case OPC_RecordChild5:
2753 case OPC_RecordChild6: case OPC_RecordChild7: {
2754 unsigned ChildNo = Opcode-OPC_RecordChild0;
2755 if (ChildNo >= N.getNumOperands())
2756 break; // Match fails if out of range child #.
2758 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2762 case OPC_RecordMemRef:
2763 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2766 case OPC_CaptureGlueInput:
2767 // If the current node has an input glue, capture it in InputGlue.
2768 if (N->getNumOperands() != 0 &&
2769 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2770 InputGlue = N->getOperand(N->getNumOperands()-1);
2773 case OPC_MoveChild: {
2774 unsigned ChildNo = MatcherTable[MatcherIndex++];
2775 if (ChildNo >= N.getNumOperands())
2776 break; // Match fails if out of range child #.
2777 N = N.getOperand(ChildNo);
2778 NodeStack.push_back(N);
2782 case OPC_MoveParent:
2783 // Pop the current node off the NodeStack.
2784 NodeStack.pop_back();
2785 assert(!NodeStack.empty() && "Node stack imbalance!");
2786 N = NodeStack.back();
2790 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2793 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2794 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2795 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2796 Opcode-OPC_CheckChild0Same))
2800 case OPC_CheckPatternPredicate:
2801 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2803 case OPC_CheckPredicate:
2804 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2808 case OPC_CheckComplexPat: {
2809 unsigned CPNum = MatcherTable[MatcherIndex++];
2810 unsigned RecNo = MatcherTable[MatcherIndex++];
2811 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2813 // If target can modify DAG during matching, keep the matching state
2815 std::unique_ptr<MatchStateUpdater> MSU;
2816 if (ComplexPatternFuncMutatesDAG())
2817 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2820 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2821 RecordedNodes[RecNo].first, CPNum,
2826 case OPC_CheckOpcode:
2827 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2831 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI,
2832 CurDAG->getDataLayout()))
2836 case OPC_SwitchOpcode: {
2837 unsigned CurNodeOpcode = N.getOpcode();
2838 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2841 // Get the size of this case.
2842 CaseSize = MatcherTable[MatcherIndex++];
2844 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2845 if (CaseSize == 0) break;
2847 uint16_t Opc = MatcherTable[MatcherIndex++];
2848 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2850 // If the opcode matches, then we will execute this case.
2851 if (CurNodeOpcode == Opc)
2854 // Otherwise, skip over this case.
2855 MatcherIndex += CaseSize;
2858 // If no cases matched, bail out.
2859 if (CaseSize == 0) break;
2861 // Otherwise, execute the case we found.
2862 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2863 << " to " << MatcherIndex << "\n");
2867 case OPC_SwitchType: {
2868 MVT CurNodeVT = N.getSimpleValueType();
2869 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2872 // Get the size of this case.
2873 CaseSize = MatcherTable[MatcherIndex++];
2875 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2876 if (CaseSize == 0) break;
2878 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2879 if (CaseVT == MVT::iPTR)
2880 CaseVT = TLI->getPointerTy(CurDAG->getDataLayout());
2882 // If the VT matches, then we will execute this case.
2883 if (CurNodeVT == CaseVT)
2886 // Otherwise, skip over this case.
2887 MatcherIndex += CaseSize;
2890 // If no cases matched, bail out.
2891 if (CaseSize == 0) break;
2893 // Otherwise, execute the case we found.
2894 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2895 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2898 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2899 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2900 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2901 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2902 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2903 CurDAG->getDataLayout(),
2904 Opcode - OPC_CheckChild0Type))
2907 case OPC_CheckCondCode:
2908 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2910 case OPC_CheckValueType:
2911 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI,
2912 CurDAG->getDataLayout()))
2915 case OPC_CheckInteger:
2916 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2918 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2919 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2920 case OPC_CheckChild4Integer:
2921 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2922 Opcode-OPC_CheckChild0Integer)) break;
2924 case OPC_CheckAndImm:
2925 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2927 case OPC_CheckOrImm:
2928 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2931 case OPC_CheckFoldableChainNode: {
2932 assert(NodeStack.size() != 1 && "No parent node");
2933 // Verify that all intermediate nodes between the root and this one have
2935 bool HasMultipleUses = false;
2936 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2937 if (!NodeStack[i].hasOneUse()) {
2938 HasMultipleUses = true;
2941 if (HasMultipleUses) break;
2943 // Check to see that the target thinks this is profitable to fold and that
2944 // we can fold it without inducing cycles in the graph.
2945 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2947 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2948 NodeToMatch, OptLevel,
2949 true/*We validate our own chains*/))
2954 case OPC_EmitInteger: {
2955 MVT::SimpleValueType VT =
2956 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2957 int64_t Val = MatcherTable[MatcherIndex++];
2959 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2960 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2961 CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch),
2965 case OPC_EmitRegister: {
2966 MVT::SimpleValueType VT =
2967 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2968 unsigned RegNo = MatcherTable[MatcherIndex++];
2969 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2970 CurDAG->getRegister(RegNo, VT), nullptr));
2973 case OPC_EmitRegister2: {
2974 // For targets w/ more than 256 register names, the register enum
2975 // values are stored in two bytes in the matcher table (just like
2977 MVT::SimpleValueType VT =
2978 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2979 unsigned RegNo = MatcherTable[MatcherIndex++];
2980 RegNo |= MatcherTable[MatcherIndex++] << 8;
2981 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2982 CurDAG->getRegister(RegNo, VT), nullptr));
2986 case OPC_EmitConvertToTarget: {
2987 // Convert from IMM/FPIMM to target version.
2988 unsigned RecNo = MatcherTable[MatcherIndex++];
2989 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2990 SDValue Imm = RecordedNodes[RecNo].first;
2992 if (Imm->getOpcode() == ISD::Constant) {
2993 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2994 Imm = CurDAG->getConstant(*Val, SDLoc(NodeToMatch), Imm.getValueType(),
2996 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2997 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2998 Imm = CurDAG->getConstantFP(*Val, SDLoc(NodeToMatch),
2999 Imm.getValueType(), true);
3002 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3006 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
3007 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
3008 // These are space-optimized forms of OPC_EmitMergeInputChains.
3009 assert(!InputChain.getNode() &&
3010 "EmitMergeInputChains should be the first chain producing node");
3011 assert(ChainNodesMatched.empty() &&
3012 "Should only have one EmitMergeInputChains per match");
3014 // Read all of the chained nodes.
3015 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3016 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3017 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3019 // FIXME: What if other value results of the node have uses not matched
3021 if (ChainNodesMatched.back() != NodeToMatch &&
3022 !RecordedNodes[RecNo].first.hasOneUse()) {
3023 ChainNodesMatched.clear();
3027 // Merge the input chains if they are not intra-pattern references.
3028 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3030 if (!InputChain.getNode())
3031 break; // Failed to merge.
3035 case OPC_EmitMergeInputChains: {
3036 assert(!InputChain.getNode() &&
3037 "EmitMergeInputChains should be the first chain producing node");
3038 // This node gets a list of nodes we matched in the input that have
3039 // chains. We want to token factor all of the input chains to these nodes
3040 // together. However, if any of the input chains is actually one of the
3041 // nodes matched in this pattern, then we have an intra-match reference.
3042 // Ignore these because the newly token factored chain should not refer to
3044 unsigned NumChains = MatcherTable[MatcherIndex++];
3045 assert(NumChains != 0 && "Can't TF zero chains");
3047 assert(ChainNodesMatched.empty() &&
3048 "Should only have one EmitMergeInputChains per match");
3050 // Read all of the chained nodes.
3051 for (unsigned i = 0; i != NumChains; ++i) {
3052 unsigned RecNo = MatcherTable[MatcherIndex++];
3053 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3054 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3056 // FIXME: What if other value results of the node have uses not matched
3058 if (ChainNodesMatched.back() != NodeToMatch &&
3059 !RecordedNodes[RecNo].first.hasOneUse()) {
3060 ChainNodesMatched.clear();
3065 // If the inner loop broke out, the match fails.
3066 if (ChainNodesMatched.empty())
3069 // Merge the input chains if they are not intra-pattern references.
3070 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3072 if (!InputChain.getNode())
3073 break; // Failed to merge.
3078 case OPC_EmitCopyToReg: {
3079 unsigned RecNo = MatcherTable[MatcherIndex++];
3080 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3081 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3083 if (!InputChain.getNode())
3084 InputChain = CurDAG->getEntryNode();
3086 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3087 DestPhysReg, RecordedNodes[RecNo].first,
3090 InputGlue = InputChain.getValue(1);
3094 case OPC_EmitNodeXForm: {
3095 unsigned XFormNo = MatcherTable[MatcherIndex++];
3096 unsigned RecNo = MatcherTable[MatcherIndex++];
3097 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3098 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3099 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3104 case OPC_MorphNodeTo: {
3105 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3106 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3107 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3108 // Get the result VT list.
3109 unsigned NumVTs = MatcherTable[MatcherIndex++];
3110 SmallVector<EVT, 4> VTs;
3111 for (unsigned i = 0; i != NumVTs; ++i) {
3112 MVT::SimpleValueType VT =
3113 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3114 if (VT == MVT::iPTR)
3115 VT = TLI->getPointerTy(CurDAG->getDataLayout()).SimpleTy;
3119 if (EmitNodeInfo & OPFL_Chain)
3120 VTs.push_back(MVT::Other);
3121 if (EmitNodeInfo & OPFL_GlueOutput)
3122 VTs.push_back(MVT::Glue);
3124 // This is hot code, so optimize the two most common cases of 1 and 2
3127 if (VTs.size() == 1)
3128 VTList = CurDAG->getVTList(VTs[0]);
3129 else if (VTs.size() == 2)
3130 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3132 VTList = CurDAG->getVTList(VTs);
3134 // Get the operand list.
3135 unsigned NumOps = MatcherTable[MatcherIndex++];
3136 SmallVector<SDValue, 8> Ops;
3137 for (unsigned i = 0; i != NumOps; ++i) {
3138 unsigned RecNo = MatcherTable[MatcherIndex++];
3140 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3142 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3143 Ops.push_back(RecordedNodes[RecNo].first);
3146 // If there are variadic operands to add, handle them now.
3147 if (EmitNodeInfo & OPFL_VariadicInfo) {
3148 // Determine the start index to copy from.
3149 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3150 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3151 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3152 "Invalid variadic node");
3153 // Copy all of the variadic operands, not including a potential glue
3155 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3157 SDValue V = NodeToMatch->getOperand(i);
3158 if (V.getValueType() == MVT::Glue) break;
3163 // If this has chain/glue inputs, add them.
3164 if (EmitNodeInfo & OPFL_Chain)
3165 Ops.push_back(InputChain);
3166 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3167 Ops.push_back(InputGlue);
3170 SDNode *Res = nullptr;
3171 if (Opcode != OPC_MorphNodeTo) {
3172 // If this is a normal EmitNode command, just create the new node and
3173 // add the results to the RecordedNodes list.
3174 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3177 // Add all the non-glue/non-chain results to the RecordedNodes list.
3178 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3179 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3180 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3184 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3185 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3187 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3188 // We will visit the equivalent node later.
3189 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3193 // If the node had chain/glue results, update our notion of the current
3195 if (EmitNodeInfo & OPFL_GlueOutput) {
3196 InputGlue = SDValue(Res, VTs.size()-1);
3197 if (EmitNodeInfo & OPFL_Chain)
3198 InputChain = SDValue(Res, VTs.size()-2);
3199 } else if (EmitNodeInfo & OPFL_Chain)
3200 InputChain = SDValue(Res, VTs.size()-1);
3202 // If the OPFL_MemRefs glue is set on this node, slap all of the
3203 // accumulated memrefs onto it.
3205 // FIXME: This is vastly incorrect for patterns with multiple outputs
3206 // instructions that access memory and for ComplexPatterns that match
3208 if (EmitNodeInfo & OPFL_MemRefs) {
3209 // Only attach load or store memory operands if the generated
3210 // instruction may load or store.
3211 const MCInstrDesc &MCID = TII->get(TargetOpc);
3212 bool mayLoad = MCID.mayLoad();
3213 bool mayStore = MCID.mayStore();
3215 unsigned NumMemRefs = 0;
3216 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3217 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3218 if ((*I)->isLoad()) {
3221 } else if ((*I)->isStore()) {
3229 MachineSDNode::mmo_iterator MemRefs =
3230 MF->allocateMemRefsArray(NumMemRefs);
3232 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3233 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3234 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3235 if ((*I)->isLoad()) {
3238 } else if ((*I)->isStore()) {
3246 cast<MachineSDNode>(Res)
3247 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3251 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3252 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3254 // If this was a MorphNodeTo then we're completely done!
3255 if (Opcode == OPC_MorphNodeTo) {
3256 // Update chain and glue uses.
3257 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3258 InputGlue, GlueResultNodesMatched, true);
3265 case OPC_MarkGlueResults: {
3266 unsigned NumNodes = MatcherTable[MatcherIndex++];
3268 // Read and remember all the glue-result nodes.
3269 for (unsigned i = 0; i != NumNodes; ++i) {
3270 unsigned RecNo = MatcherTable[MatcherIndex++];
3272 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3274 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3275 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3280 case OPC_CompleteMatch: {
3281 // The match has been completed, and any new nodes (if any) have been
3282 // created. Patch up references to the matched dag to use the newly
3284 unsigned NumResults = MatcherTable[MatcherIndex++];
3286 for (unsigned i = 0; i != NumResults; ++i) {
3287 unsigned ResSlot = MatcherTable[MatcherIndex++];
3289 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3291 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3292 SDValue Res = RecordedNodes[ResSlot].first;
3294 assert(i < NodeToMatch->getNumValues() &&
3295 NodeToMatch->getValueType(i) != MVT::Other &&
3296 NodeToMatch->getValueType(i) != MVT::Glue &&
3297 "Invalid number of results to complete!");
3298 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3299 NodeToMatch->getValueType(i) == MVT::iPTR ||
3300 Res.getValueType() == MVT::iPTR ||
3301 NodeToMatch->getValueType(i).getSizeInBits() ==
3302 Res.getValueType().getSizeInBits()) &&
3303 "invalid replacement");
3304 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3307 // If the root node defines glue, add it to the glue nodes to update list.
3308 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3309 GlueResultNodesMatched.push_back(NodeToMatch);
3311 // Update chain and glue uses.
3312 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3313 InputGlue, GlueResultNodesMatched, false);
3315 assert(NodeToMatch->use_empty() &&
3316 "Didn't replace all uses of the node?");
3318 // FIXME: We just return here, which interacts correctly with SelectRoot
3319 // above. We should fix this to not return an SDNode* anymore.
3324 // If the code reached this point, then the match failed. See if there is
3325 // another child to try in the current 'Scope', otherwise pop it until we
3326 // find a case to check.
3327 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3328 ++NumDAGIselRetries;
3330 if (MatchScopes.empty()) {
3331 CannotYetSelect(NodeToMatch);
3335 // Restore the interpreter state back to the point where the scope was
3337 MatchScope &LastScope = MatchScopes.back();
3338 RecordedNodes.resize(LastScope.NumRecordedNodes);
3340 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3341 N = NodeStack.back();
3343 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3344 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3345 MatcherIndex = LastScope.FailIndex;
3347 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3349 InputChain = LastScope.InputChain;
3350 InputGlue = LastScope.InputGlue;
3351 if (!LastScope.HasChainNodesMatched)
3352 ChainNodesMatched.clear();
3353 if (!LastScope.HasGlueResultNodesMatched)
3354 GlueResultNodesMatched.clear();
3356 // Check to see what the offset is at the new MatcherIndex. If it is zero
3357 // we have reached the end of this scope, otherwise we have another child
3358 // in the current scope to try.
3359 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3360 if (NumToSkip & 128)
3361 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3363 // If we have another child in this scope to match, update FailIndex and
3365 if (NumToSkip != 0) {
3366 LastScope.FailIndex = MatcherIndex+NumToSkip;
3370 // End of this scope, pop it and try the next child in the containing
3372 MatchScopes.pop_back();
3379 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3381 raw_string_ostream Msg(msg);
3382 Msg << "Cannot select: ";
3384 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3385 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3386 N->getOpcode() != ISD::INTRINSIC_VOID) {
3387 N->printrFull(Msg, CurDAG);
3388 Msg << "\nIn function: " << MF->getName();
3390 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3392 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3393 if (iid < Intrinsic::num_intrinsics)
3394 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3395 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3396 Msg << "target intrinsic %" << TII->getName(iid);
3398 Msg << "unknown intrinsic #" << iid;
3400 report_fatal_error(Msg.str());
3403 char SelectionDAGISel::ID = 0;