1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
60 cl::desc("Pop up a window to show SUnit dags after they are processed"));
62 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
65 //===---------------------------------------------------------------------===//
67 /// RegisterScheduler class - Track the registration of instruction schedulers.
69 //===---------------------------------------------------------------------===//
70 MachinePassRegistry RegisterScheduler::Registry;
72 //===---------------------------------------------------------------------===//
74 /// ISHeuristic command line option for instruction schedulers.
76 //===---------------------------------------------------------------------===//
78 cl::opt<RegisterScheduler::FunctionPassCtor, false,
79 RegisterPassParser<RegisterScheduler> >
80 ISHeuristic("pre-RA-sched",
81 cl::init(&createDefaultScheduler),
82 cl::desc("Instruction schedulers available (before register"
85 static RegisterScheduler
86 defaultListDAGScheduler("default", " Best scheduler for the target",
87 createDefaultScheduler);
90 namespace { struct SDISelAsmOperandInfo; }
93 /// RegsForValue - This struct represents the physical registers that a
94 /// particular value is assigned and the type information about the value.
95 /// This is needed because values can be promoted into larger registers and
96 /// expanded into multiple smaller registers than the value.
97 struct VISIBILITY_HIDDEN RegsForValue {
98 /// Regs - This list holds the register (for legal and promoted values)
99 /// or register set (for expanded values) that the value should be assigned
101 std::vector<unsigned> Regs;
103 /// RegVT - The value type of each register.
105 MVT::ValueType RegVT;
107 /// ValueVT - The value type of the LLVM value, which may be promoted from
108 /// RegVT or made from merging the two expanded parts.
109 MVT::ValueType ValueVT;
111 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
113 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
114 : RegVT(regvt), ValueVT(valuevt) {
117 RegsForValue(const std::vector<unsigned> ®s,
118 MVT::ValueType regvt, MVT::ValueType valuevt)
119 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
122 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
123 /// this value and returns the result as a ValueVT value. This uses
124 /// Chain/Flag as the input and updates them for the output Chain/Flag.
125 /// If the Flag pointer is NULL, no flag is used.
126 SDOperand getCopyFromRegs(SelectionDAG &DAG,
127 SDOperand &Chain, SDOperand *Flag) const;
129 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
130 /// specified value into the registers specified by this object. This uses
131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
132 /// If the Flag pointer is NULL, no flag is used.
133 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
134 SDOperand &Chain, SDOperand *Flag) const;
136 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
137 /// operand list. This adds the code marker and includes the number of
138 /// values added into it.
139 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
140 std::vector<SDOperand> &Ops) const;
145 //===--------------------------------------------------------------------===//
146 /// createDefaultScheduler - This creates an instruction scheduler appropriate
148 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
150 MachineBasicBlock *BB) {
151 TargetLowering &TLI = IS->getTargetLowering();
153 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
154 return createTDListDAGScheduler(IS, DAG, BB);
156 assert(TLI.getSchedulingPreference() ==
157 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
158 return createBURRListDAGScheduler(IS, DAG, BB);
163 //===--------------------------------------------------------------------===//
164 /// FunctionLoweringInfo - This contains information that is global to a
165 /// function that is used when lowering a region of the function.
166 class FunctionLoweringInfo {
171 MachineRegisterInfo &RegInfo;
173 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
175 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
176 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
178 /// ValueMap - Since we emit code for the function a basic block at a time,
179 /// we must remember which virtual registers hold the values for
180 /// cross-basic-block values.
181 DenseMap<const Value*, unsigned> ValueMap;
183 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
184 /// the entry block. This allows the allocas to be efficiently referenced
185 /// anywhere in the function.
186 std::map<const AllocaInst*, int> StaticAllocaMap;
189 SmallSet<Instruction*, 8> CatchInfoLost;
190 SmallSet<Instruction*, 8> CatchInfoFound;
193 unsigned MakeReg(MVT::ValueType VT) {
194 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
197 /// isExportedInst - Return true if the specified value is an instruction
198 /// exported from its block.
199 bool isExportedInst(const Value *V) {
200 return ValueMap.count(V);
203 unsigned CreateRegForValue(const Value *V);
205 unsigned InitializeRegForValue(const Value *V) {
206 unsigned &R = ValueMap[V];
207 assert(R == 0 && "Already initialized this value register!");
208 return R = CreateRegForValue(V);
213 /// isSelector - Return true if this instruction is a call to the
214 /// eh.selector intrinsic.
215 static bool isSelector(Instruction *I) {
216 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
217 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
218 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
222 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
223 /// PHI nodes or outside of the basic block that defines it, or used by a
224 /// switch or atomic instruction, which may expand to multiple basic blocks.
225 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
226 if (isa<PHINode>(I)) return true;
227 BasicBlock *BB = I->getParent();
228 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
229 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
230 // FIXME: Remove switchinst special case.
231 isa<SwitchInst>(*UI))
236 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
237 /// entry block, return true. This includes arguments used by switches, since
238 /// the switch may expand into multiple basic blocks.
239 static bool isOnlyUsedInEntryBlock(Argument *A) {
240 BasicBlock *Entry = A->getParent()->begin();
241 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
242 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
243 return false; // Use not in entry block.
247 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
248 Function &fn, MachineFunction &mf)
249 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
251 // Create a vreg for each argument register that is not dead and is used
252 // outside of the entry block for the function.
253 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
255 if (!isOnlyUsedInEntryBlock(AI))
256 InitializeRegForValue(AI);
258 // Initialize the mapping of values to registers. This is only set up for
259 // instruction values that are used outside of the block that defines
261 Function::iterator BB = Fn.begin(), EB = Fn.end();
262 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
263 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
264 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
265 const Type *Ty = AI->getAllocatedType();
266 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
268 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
271 TySize *= CUI->getZExtValue(); // Get total allocated size.
272 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
273 StaticAllocaMap[AI] =
274 MF.getFrameInfo()->CreateStackObject(TySize, Align);
277 for (; BB != EB; ++BB)
278 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
279 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
280 if (!isa<AllocaInst>(I) ||
281 !StaticAllocaMap.count(cast<AllocaInst>(I)))
282 InitializeRegForValue(I);
284 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
285 // also creates the initial PHI MachineInstrs, though none of the input
286 // operands are populated.
287 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
288 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
290 MF.getBasicBlockList().push_back(MBB);
292 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
295 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
296 if (PN->use_empty()) continue;
298 MVT::ValueType VT = TLI.getValueType(PN->getType());
299 unsigned NumRegisters = TLI.getNumRegisters(VT);
300 unsigned PHIReg = ValueMap[PN];
301 assert(PHIReg && "PHI node does not have an assigned virtual register!");
302 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
303 for (unsigned i = 0; i != NumRegisters; ++i)
304 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
309 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
310 /// the correctly promoted or expanded types. Assign these registers
311 /// consecutive vreg numbers and return the first assigned number.
312 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
313 MVT::ValueType VT = TLI.getValueType(V->getType());
315 unsigned NumRegisters = TLI.getNumRegisters(VT);
316 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
318 unsigned R = MakeReg(RegisterVT);
319 for (unsigned i = 1; i != NumRegisters; ++i)
325 //===----------------------------------------------------------------------===//
326 /// SelectionDAGLowering - This is the common target-independent lowering
327 /// implementation that is parameterized by a TargetLowering object.
328 /// Also, targets can overload any lowering method.
331 class SelectionDAGLowering {
332 MachineBasicBlock *CurMBB;
334 DenseMap<const Value*, SDOperand> NodeMap;
336 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
337 /// them up and then emit token factor nodes when possible. This allows us to
338 /// get simple disambiguation between loads without worrying about alias
340 std::vector<SDOperand> PendingLoads;
342 /// Case - A struct to record the Value for a switch case, and the
343 /// case's target basic block.
347 MachineBasicBlock* BB;
349 Case() : Low(0), High(0), BB(0) { }
350 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
351 Low(low), High(high), BB(bb) { }
352 uint64_t size() const {
353 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
354 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
355 return (rHigh - rLow + 1ULL);
361 MachineBasicBlock* BB;
364 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
365 Mask(mask), BB(bb), Bits(bits) { }
368 typedef std::vector<Case> CaseVector;
369 typedef std::vector<CaseBits> CaseBitsVector;
370 typedef CaseVector::iterator CaseItr;
371 typedef std::pair<CaseItr, CaseItr> CaseRange;
373 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
374 /// of conditional branches.
376 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
377 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
379 /// CaseBB - The MBB in which to emit the compare and branch
380 MachineBasicBlock *CaseBB;
381 /// LT, GE - If nonzero, we know the current case value must be less-than or
382 /// greater-than-or-equal-to these Constants.
385 /// Range - A pair of iterators representing the range of case values to be
386 /// processed at this point in the binary search tree.
390 typedef std::vector<CaseRec> CaseRecVector;
392 /// The comparison function for sorting the switch case values in the vector.
393 /// WARNING: Case ranges should be disjoint!
395 bool operator () (const Case& C1, const Case& C2) {
396 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
397 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
398 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
399 return CI1->getValue().slt(CI2->getValue());
404 bool operator () (const CaseBits& C1, const CaseBits& C2) {
405 return C1.Bits > C2.Bits;
409 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
412 // TLI - This is information that describes the available target features we
413 // need for lowering. This indicates when operations are unavailable,
414 // implemented with a libcall, etc.
417 const TargetData *TD;
420 /// SwitchCases - Vector of CaseBlock structures used to communicate
421 /// SwitchInst code generation information.
422 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
423 /// JTCases - Vector of JumpTable structures used to communicate
424 /// SwitchInst code generation information.
425 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
426 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
428 /// FuncInfo - Information about the function as a whole.
430 FunctionLoweringInfo &FuncInfo;
432 /// GCI - Garbage collection metadata for the function.
433 CollectorMetadata *GCI;
435 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
437 FunctionLoweringInfo &funcinfo,
438 CollectorMetadata *gci)
439 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
440 FuncInfo(funcinfo), GCI(gci) {
443 /// getRoot - Return the current virtual root of the Selection DAG.
445 SDOperand getRoot() {
446 if (PendingLoads.empty())
447 return DAG.getRoot();
449 if (PendingLoads.size() == 1) {
450 SDOperand Root = PendingLoads[0];
452 PendingLoads.clear();
456 // Otherwise, we have to make a token factor node.
457 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
458 &PendingLoads[0], PendingLoads.size());
459 PendingLoads.clear();
464 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
466 void visit(Instruction &I) { visit(I.getOpcode(), I); }
468 void visit(unsigned Opcode, User &I) {
469 // Note: this doesn't use InstVisitor, because it has to work with
470 // ConstantExpr's in addition to instructions.
472 default: assert(0 && "Unknown instruction type encountered!");
474 // Build the switch statement using the Instruction.def file.
475 #define HANDLE_INST(NUM, OPCODE, CLASS) \
476 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
477 #include "llvm/Instruction.def"
481 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
483 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
484 const Value *SV, SDOperand Root,
485 bool isVolatile, unsigned Alignment);
487 SDOperand getValue(const Value *V);
489 void setValue(const Value *V, SDOperand NewN) {
490 SDOperand &N = NodeMap[V];
491 assert(N.Val == 0 && "Already set a value for this node!");
495 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
496 std::set<unsigned> &OutputRegs,
497 std::set<unsigned> &InputRegs);
499 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
500 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
502 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
503 void ExportFromCurrentBlock(Value *V);
504 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
505 MachineBasicBlock *LandingPad = NULL);
507 // Terminator instructions.
508 void visitRet(ReturnInst &I);
509 void visitBr(BranchInst &I);
510 void visitSwitch(SwitchInst &I);
511 void visitUnreachable(UnreachableInst &I) { /* noop */ }
513 // Helpers for visitSwitch
514 bool handleSmallSwitchRange(CaseRec& CR,
515 CaseRecVector& WorkList,
517 MachineBasicBlock* Default);
518 bool handleJTSwitchCase(CaseRec& CR,
519 CaseRecVector& WorkList,
521 MachineBasicBlock* Default);
522 bool handleBTSplitSwitchCase(CaseRec& CR,
523 CaseRecVector& WorkList,
525 MachineBasicBlock* Default);
526 bool handleBitTestsSwitchCase(CaseRec& CR,
527 CaseRecVector& WorkList,
529 MachineBasicBlock* Default);
530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
532 void visitBitTestCase(MachineBasicBlock* NextMBB,
534 SelectionDAGISel::BitTestCase &B);
535 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
537 SelectionDAGISel::JumpTableHeader &JTH);
539 // These all get lowered before this pass.
540 void visitInvoke(InvokeInst &I);
541 void visitUnwind(UnwindInst &I);
543 void visitBinary(User &I, unsigned OpCode);
544 void visitShift(User &I, unsigned Opcode);
545 void visitAdd(User &I) {
546 if (I.getType()->isFPOrFPVector())
547 visitBinary(I, ISD::FADD);
549 visitBinary(I, ISD::ADD);
551 void visitSub(User &I);
552 void visitMul(User &I) {
553 if (I.getType()->isFPOrFPVector())
554 visitBinary(I, ISD::FMUL);
556 visitBinary(I, ISD::MUL);
558 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
564 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
565 void visitOr (User &I) { visitBinary(I, ISD::OR); }
566 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
567 void visitShl (User &I) { visitShift(I, ISD::SHL); }
568 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
569 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
570 void visitICmp(User &I);
571 void visitFCmp(User &I);
572 // Visit the conversion instructions
573 void visitTrunc(User &I);
574 void visitZExt(User &I);
575 void visitSExt(User &I);
576 void visitFPTrunc(User &I);
577 void visitFPExt(User &I);
578 void visitFPToUI(User &I);
579 void visitFPToSI(User &I);
580 void visitUIToFP(User &I);
581 void visitSIToFP(User &I);
582 void visitPtrToInt(User &I);
583 void visitIntToPtr(User &I);
584 void visitBitCast(User &I);
586 void visitExtractElement(User &I);
587 void visitInsertElement(User &I);
588 void visitShuffleVector(User &I);
590 void visitGetElementPtr(User &I);
591 void visitSelect(User &I);
593 void visitMalloc(MallocInst &I);
594 void visitFree(FreeInst &I);
595 void visitAlloca(AllocaInst &I);
596 void visitLoad(LoadInst &I);
597 void visitStore(StoreInst &I);
598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
599 void visitCall(CallInst &I);
600 void visitInlineAsm(CallSite CS);
601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
604 void visitVAStart(CallInst &I);
605 void visitVAArg(VAArgInst &I);
606 void visitVAEnd(CallInst &I);
607 void visitVACopy(CallInst &I);
609 void visitMemIntrinsic(CallInst &I, unsigned Op);
611 void visitGetResult(GetResultInst &I) {
612 assert (0 && "getresult unimplemented");
615 void visitUserOp1(Instruction &I) {
616 assert(0 && "UserOp1 should not exist at instruction selection time!");
619 void visitUserOp2(Instruction &I) {
620 assert(0 && "UserOp2 should not exist at instruction selection time!");
624 } // end namespace llvm
627 /// getCopyFromParts - Create a value that contains the specified legal parts
628 /// combined into the value they represent. If the parts combine to a type
629 /// larger then ValueVT then AssertOp can be used to specify whether the extra
630 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
631 /// (ISD::AssertSext).
632 static SDOperand getCopyFromParts(SelectionDAG &DAG,
633 const SDOperand *Parts,
635 MVT::ValueType PartVT,
636 MVT::ValueType ValueVT,
637 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
638 assert(NumParts > 0 && "No parts to assemble!");
639 TargetLowering &TLI = DAG.getTargetLoweringInfo();
640 SDOperand Val = Parts[0];
643 // Assemble the value from multiple parts.
644 if (!MVT::isVector(ValueVT)) {
645 unsigned PartBits = MVT::getSizeInBits(PartVT);
646 unsigned ValueBits = MVT::getSizeInBits(ValueVT);
648 // Assemble the power of 2 part.
649 unsigned RoundParts = NumParts & (NumParts - 1) ?
650 1 << Log2_32(NumParts) : NumParts;
651 unsigned RoundBits = PartBits * RoundParts;
652 MVT::ValueType RoundVT = RoundBits == ValueBits ?
653 ValueVT : MVT::getIntegerType(RoundBits);
656 if (RoundParts > 2) {
657 MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2);
658 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
659 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
665 if (TLI.isBigEndian())
667 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
669 if (RoundParts < NumParts) {
670 // Assemble the trailing non-power-of-2 part.
671 unsigned OddParts = NumParts - RoundParts;
672 MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits);
673 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
675 // Combine the round and odd parts.
677 if (TLI.isBigEndian())
679 MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits);
680 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
681 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
682 DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()),
683 TLI.getShiftAmountTy()));
684 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
685 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
688 // Handle a multi-element vector.
689 MVT::ValueType IntermediateVT, RegisterVT;
690 unsigned NumIntermediates;
692 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
695 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
696 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
697 assert(RegisterVT == Parts[0].getValueType() &&
698 "Part type doesn't match part!");
700 // Assemble the parts into intermediate operands.
701 SmallVector<SDOperand, 8> Ops(NumIntermediates);
702 if (NumIntermediates == NumParts) {
703 // If the register was not expanded, truncate or copy the value,
705 for (unsigned i = 0; i != NumParts; ++i)
706 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
707 PartVT, IntermediateVT);
708 } else if (NumParts > 0) {
709 // If the intermediate type was expanded, build the intermediate operands
711 assert(NumParts % NumIntermediates == 0 &&
712 "Must expand into a divisible number of parts!");
713 unsigned Factor = NumParts / NumIntermediates;
714 for (unsigned i = 0; i != NumIntermediates; ++i)
715 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
716 PartVT, IntermediateVT);
719 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
721 Val = DAG.getNode(MVT::isVector(IntermediateVT) ?
722 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
723 ValueVT, &Ops[0], NumIntermediates);
727 // There is now one part, held in Val. Correct it to match ValueVT.
728 PartVT = Val.getValueType();
730 if (PartVT == ValueVT)
733 if (MVT::isVector(PartVT)) {
734 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
735 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
738 if (MVT::isVector(ValueVT)) {
739 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
740 MVT::getVectorNumElements(ValueVT) == 1 &&
741 "Only trivial scalar-to-vector conversions should get here!");
742 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
745 if (MVT::isInteger(PartVT) &&
746 MVT::isInteger(ValueVT)) {
747 if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) {
748 // For a truncate, see if we have any information to
749 // indicate whether the truncated bits will always be
750 // zero or sign-extension.
751 if (AssertOp != ISD::DELETED_NODE)
752 Val = DAG.getNode(AssertOp, PartVT, Val,
753 DAG.getValueType(ValueVT));
754 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
756 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
760 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
761 if (ValueVT < Val.getValueType())
762 // FP_ROUND's are always exact here.
763 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
764 DAG.getIntPtrConstant(1));
765 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
768 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
769 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
771 assert(0 && "Unknown mismatch!");
774 /// getCopyToParts - Create a series of nodes that contain the specified value
775 /// split into legal parts. If the parts contain more bits than Val, then, for
776 /// integers, ExtendKind can be used to specify how to generate the extra bits.
777 static void getCopyToParts(SelectionDAG &DAG,
781 MVT::ValueType PartVT,
782 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
783 TargetLowering &TLI = DAG.getTargetLoweringInfo();
784 MVT::ValueType PtrVT = TLI.getPointerTy();
785 MVT::ValueType ValueVT = Val.getValueType();
786 unsigned PartBits = MVT::getSizeInBits(PartVT);
787 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
792 if (!MVT::isVector(ValueVT)) {
793 if (PartVT == ValueVT) {
794 assert(NumParts == 1 && "No-op copy with multiple parts!");
799 if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) {
800 // If the parts cover more bits than the value has, promote the value.
801 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
802 assert(NumParts == 1 && "Do not know what to promote to!");
803 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
804 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
805 ValueVT = MVT::getIntegerType(NumParts * PartBits);
806 Val = DAG.getNode(ExtendKind, ValueVT, Val);
808 assert(0 && "Unknown mismatch!");
810 } else if (PartBits == MVT::getSizeInBits(ValueVT)) {
811 // Different types of the same size.
812 assert(NumParts == 1 && PartVT != ValueVT);
813 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
814 } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) {
815 // If the parts cover less bits than value has, truncate the value.
816 if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
817 ValueVT = MVT::getIntegerType(NumParts * PartBits);
818 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
820 assert(0 && "Unknown mismatch!");
824 // The value may have changed - recompute ValueVT.
825 ValueVT = Val.getValueType();
826 assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) &&
827 "Failed to tile the value with PartVT!");
830 assert(PartVT == ValueVT && "Type conversion failed!");
835 // Expand the value into multiple parts.
836 if (NumParts & (NumParts - 1)) {
837 // The number of parts is not a power of 2. Split off and copy the tail.
838 assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) &&
839 "Do not know what to expand to!");
840 unsigned RoundParts = 1 << Log2_32(NumParts);
841 unsigned RoundBits = RoundParts * PartBits;
842 unsigned OddParts = NumParts - RoundParts;
843 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
844 DAG.getConstant(RoundBits,
845 TLI.getShiftAmountTy()));
846 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
847 if (TLI.isBigEndian())
848 // The odd parts were reversed by getCopyToParts - unreverse them.
849 std::reverse(Parts + RoundParts, Parts + NumParts);
850 NumParts = RoundParts;
851 ValueVT = MVT::getIntegerType(NumParts * PartBits);
852 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
855 // The number of parts is a power of 2. Repeatedly bisect the value using
858 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
859 for (unsigned i = 0; i < NumParts; i += StepSize) {
860 unsigned ThisBits = StepSize * PartBits / 2;
861 MVT::ValueType ThisVT =
862 ThisBits == PartBits ? PartVT : MVT::getIntegerType (ThisBits);
864 Parts[i+StepSize/2] =
865 DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Parts[i],
866 DAG.getConstant(1, PtrVT));
868 DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Parts[i],
869 DAG.getConstant(0, PtrVT));
873 if (TLI.isBigEndian())
874 std::reverse(Parts, Parts + NumParts);
881 if (PartVT != ValueVT) {
882 if (MVT::isVector(PartVT)) {
883 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
885 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
886 MVT::getVectorNumElements(ValueVT) == 1 &&
887 "Only trivial vector-to-scalar conversions should get here!");
888 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
889 DAG.getConstant(0, PtrVT));
897 // Handle a multi-element vector.
898 MVT::ValueType IntermediateVT, RegisterVT;
899 unsigned NumIntermediates;
901 DAG.getTargetLoweringInfo()
902 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
904 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
906 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
907 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
909 // Split the vector into intermediate operands.
910 SmallVector<SDOperand, 8> Ops(NumIntermediates);
911 for (unsigned i = 0; i != NumIntermediates; ++i)
912 if (MVT::isVector(IntermediateVT))
913 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
915 DAG.getConstant(i * (NumElements / NumIntermediates),
918 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
920 DAG.getConstant(i, PtrVT));
922 // Split the intermediate operands into legal parts.
923 if (NumParts == NumIntermediates) {
924 // If the register was not expanded, promote or copy the value,
926 for (unsigned i = 0; i != NumParts; ++i)
927 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
928 } else if (NumParts > 0) {
929 // If the intermediate type was expanded, split each the value into
931 assert(NumParts % NumIntermediates == 0 &&
932 "Must expand into a divisible number of parts!");
933 unsigned Factor = NumParts / NumIntermediates;
934 for (unsigned i = 0; i != NumIntermediates; ++i)
935 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
940 SDOperand SelectionDAGLowering::getValue(const Value *V) {
941 SDOperand &N = NodeMap[V];
944 const Type *VTy = V->getType();
945 MVT::ValueType VT = TLI.getValueType(VTy);
946 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
947 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
948 visit(CE->getOpcode(), *CE);
949 SDOperand N1 = NodeMap[V];
950 assert(N1.Val && "visit didn't populate the ValueMap!");
952 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
953 return N = DAG.getGlobalAddress(GV, VT);
954 } else if (isa<ConstantPointerNull>(C)) {
955 return N = DAG.getConstant(0, TLI.getPointerTy());
956 } else if (isa<UndefValue>(C)) {
957 if (!isa<VectorType>(VTy))
958 return N = DAG.getNode(ISD::UNDEF, VT);
960 // Create a BUILD_VECTOR of undef nodes.
961 const VectorType *PTy = cast<VectorType>(VTy);
962 unsigned NumElements = PTy->getNumElements();
963 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
965 SmallVector<SDOperand, 8> Ops;
966 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
968 // Create a VConstant node with generic Vector type.
969 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
970 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
971 &Ops[0], Ops.size());
972 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
973 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
974 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
975 unsigned NumElements = PTy->getNumElements();
976 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
978 // Now that we know the number and type of the elements, push a
979 // Constant or ConstantFP node onto the ops list for each element of
980 // the vector constant.
981 SmallVector<SDOperand, 8> Ops;
982 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
983 for (unsigned i = 0; i != NumElements; ++i)
984 Ops.push_back(getValue(CP->getOperand(i)));
986 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
988 if (MVT::isFloatingPoint(PVT))
989 Op = DAG.getConstantFP(0, PVT);
991 Op = DAG.getConstant(0, PVT);
992 Ops.assign(NumElements, Op);
995 // Create a BUILD_VECTOR node.
996 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
997 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
1000 // Canonicalize all constant ints to be unsigned.
1001 return N = DAG.getConstant(cast<ConstantInt>(C)->getValue(),VT);
1005 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1006 std::map<const AllocaInst*, int>::iterator SI =
1007 FuncInfo.StaticAllocaMap.find(AI);
1008 if (SI != FuncInfo.StaticAllocaMap.end())
1009 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1012 unsigned InReg = FuncInfo.ValueMap[V];
1013 assert(InReg && "Value not in map!");
1015 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
1016 unsigned NumRegs = TLI.getNumRegisters(VT);
1018 std::vector<unsigned> Regs(NumRegs);
1019 for (unsigned i = 0; i != NumRegs; ++i)
1020 Regs[i] = InReg + i;
1022 RegsForValue RFV(Regs, RegisterVT, VT);
1023 SDOperand Chain = DAG.getEntryNode();
1025 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1029 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1030 if (I.getNumOperands() == 0) {
1031 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
1034 SmallVector<SDOperand, 8> NewValues;
1035 NewValues.push_back(getRoot());
1036 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1037 SDOperand RetOp = getValue(I.getOperand(i));
1038 MVT::ValueType VT = RetOp.getValueType();
1040 // FIXME: C calling convention requires the return type to be promoted to
1041 // at least 32-bit. But this is not necessary for non-C calling conventions.
1042 if (MVT::isInteger(VT)) {
1043 MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32);
1044 if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT))
1048 unsigned NumParts = TLI.getNumRegisters(VT);
1049 MVT::ValueType PartVT = TLI.getRegisterType(VT);
1050 SmallVector<SDOperand, 4> Parts(NumParts);
1051 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1053 const Function *F = I.getParent()->getParent();
1054 if (F->paramHasAttr(0, ParamAttr::SExt))
1055 ExtendKind = ISD::SIGN_EXTEND;
1056 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1057 ExtendKind = ISD::ZERO_EXTEND;
1059 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind);
1061 for (unsigned i = 0; i < NumParts; ++i) {
1062 NewValues.push_back(Parts[i]);
1063 NewValues.push_back(DAG.getConstant(false, MVT::i32));
1066 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1067 &NewValues[0], NewValues.size()));
1070 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1071 /// the current basic block, add it to ValueMap now so that we'll get a
1073 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1074 // No need to export constants.
1075 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1077 // Already exported?
1078 if (FuncInfo.isExportedInst(V)) return;
1080 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1081 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
1084 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1085 const BasicBlock *FromBB) {
1086 // The operands of the setcc have to be in this block. We don't know
1087 // how to export them from some other block.
1088 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1089 // Can export from current BB.
1090 if (VI->getParent() == FromBB)
1093 // Is already exported, noop.
1094 return FuncInfo.isExportedInst(V);
1097 // If this is an argument, we can export it if the BB is the entry block or
1098 // if it is already exported.
1099 if (isa<Argument>(V)) {
1100 if (FromBB == &FromBB->getParent()->getEntryBlock())
1103 // Otherwise, can only export this if it is already exported.
1104 return FuncInfo.isExportedInst(V);
1107 // Otherwise, constants can always be exported.
1111 static bool InBlock(const Value *V, const BasicBlock *BB) {
1112 if (const Instruction *I = dyn_cast<Instruction>(V))
1113 return I->getParent() == BB;
1117 /// FindMergedConditions - If Cond is an expression like
1118 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1119 MachineBasicBlock *TBB,
1120 MachineBasicBlock *FBB,
1121 MachineBasicBlock *CurBB,
1123 // If this node is not part of the or/and tree, emit it as a branch.
1124 Instruction *BOp = dyn_cast<Instruction>(Cond);
1126 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1127 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1128 BOp->getParent() != CurBB->getBasicBlock() ||
1129 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1130 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1131 const BasicBlock *BB = CurBB->getBasicBlock();
1133 // If the leaf of the tree is a comparison, merge the condition into
1135 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1136 // The operands of the cmp have to be in this block. We don't know
1137 // how to export them from some other block. If this is the first block
1138 // of the sequence, no exporting is needed.
1140 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1141 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1142 BOp = cast<Instruction>(Cond);
1143 ISD::CondCode Condition;
1144 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1145 switch (IC->getPredicate()) {
1146 default: assert(0 && "Unknown icmp predicate opcode!");
1147 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1148 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1149 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1150 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1151 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1152 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1153 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1154 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1155 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1156 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1158 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1159 ISD::CondCode FPC, FOC;
1160 switch (FC->getPredicate()) {
1161 default: assert(0 && "Unknown fcmp predicate opcode!");
1162 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1163 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1164 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1165 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1166 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1167 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1168 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1169 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1170 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1171 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1172 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1173 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1174 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1175 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1176 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1177 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1179 if (FiniteOnlyFPMath())
1184 Condition = ISD::SETEQ; // silence warning.
1185 assert(0 && "Unknown compare instruction");
1188 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1189 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1190 SwitchCases.push_back(CB);
1194 // Create a CaseBlock record representing this branch.
1195 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1196 NULL, TBB, FBB, CurBB);
1197 SwitchCases.push_back(CB);
1202 // Create TmpBB after CurBB.
1203 MachineFunction::iterator BBI = CurBB;
1204 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1205 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1207 if (Opc == Instruction::Or) {
1208 // Codegen X | Y as:
1216 // Emit the LHS condition.
1217 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1219 // Emit the RHS condition into TmpBB.
1220 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1222 assert(Opc == Instruction::And && "Unknown merge op!");
1223 // Codegen X & Y as:
1230 // This requires creation of TmpBB after CurBB.
1232 // Emit the LHS condition.
1233 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1235 // Emit the RHS condition into TmpBB.
1236 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1240 /// If the set of cases should be emitted as a series of branches, return true.
1241 /// If we should emit this as a bunch of and/or'd together conditions, return
1244 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1245 if (Cases.size() != 2) return true;
1247 // If this is two comparisons of the same values or'd or and'd together, they
1248 // will get folded into a single comparison, so don't emit two blocks.
1249 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1250 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1251 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1252 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1259 void SelectionDAGLowering::visitBr(BranchInst &I) {
1260 // Update machine-CFG edges.
1261 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1263 // Figure out which block is immediately after the current one.
1264 MachineBasicBlock *NextBlock = 0;
1265 MachineFunction::iterator BBI = CurMBB;
1266 if (++BBI != CurMBB->getParent()->end())
1269 if (I.isUnconditional()) {
1270 // If this is not a fall-through branch, emit the branch.
1271 if (Succ0MBB != NextBlock)
1272 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1273 DAG.getBasicBlock(Succ0MBB)));
1275 // Update machine-CFG edges.
1276 CurMBB->addSuccessor(Succ0MBB);
1280 // If this condition is one of the special cases we handle, do special stuff
1282 Value *CondVal = I.getCondition();
1283 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1285 // If this is a series of conditions that are or'd or and'd together, emit
1286 // this as a sequence of branches instead of setcc's with and/or operations.
1287 // For example, instead of something like:
1300 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1301 if (BOp->hasOneUse() &&
1302 (BOp->getOpcode() == Instruction::And ||
1303 BOp->getOpcode() == Instruction::Or)) {
1304 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1305 // If the compares in later blocks need to use values not currently
1306 // exported from this block, export them now. This block should always
1307 // be the first entry.
1308 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1310 // Allow some cases to be rejected.
1311 if (ShouldEmitAsBranches(SwitchCases)) {
1312 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1313 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1314 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1317 // Emit the branch for this block.
1318 visitSwitchCase(SwitchCases[0]);
1319 SwitchCases.erase(SwitchCases.begin());
1323 // Okay, we decided not to do this, remove any inserted MBB's and clear
1325 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1326 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1328 SwitchCases.clear();
1332 // Create a CaseBlock record representing this branch.
1333 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1334 NULL, Succ0MBB, Succ1MBB, CurMBB);
1335 // Use visitSwitchCase to actually insert the fast branch sequence for this
1337 visitSwitchCase(CB);
1340 /// visitSwitchCase - Emits the necessary code to represent a single node in
1341 /// the binary search tree resulting from lowering a switch instruction.
1342 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1344 SDOperand CondLHS = getValue(CB.CmpLHS);
1346 // Build the setcc now.
1347 if (CB.CmpMHS == NULL) {
1348 // Fold "(X == true)" to X and "(X == false)" to !X to
1349 // handle common cases produced by branch lowering.
1350 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1352 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1353 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1354 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1356 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1358 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1360 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1361 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1363 SDOperand CmpOp = getValue(CB.CmpMHS);
1364 MVT::ValueType VT = CmpOp.getValueType();
1366 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1367 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1369 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1370 Cond = DAG.getSetCC(MVT::i1, SUB,
1371 DAG.getConstant(High-Low, VT), ISD::SETULE);
1376 // Set NextBlock to be the MBB immediately after the current one, if any.
1377 // This is used to avoid emitting unnecessary branches to the next block.
1378 MachineBasicBlock *NextBlock = 0;
1379 MachineFunction::iterator BBI = CurMBB;
1380 if (++BBI != CurMBB->getParent()->end())
1383 // If the lhs block is the next block, invert the condition so that we can
1384 // fall through to the lhs instead of the rhs block.
1385 if (CB.TrueBB == NextBlock) {
1386 std::swap(CB.TrueBB, CB.FalseBB);
1387 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1388 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1390 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1391 DAG.getBasicBlock(CB.TrueBB));
1392 if (CB.FalseBB == NextBlock)
1393 DAG.setRoot(BrCond);
1395 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1396 DAG.getBasicBlock(CB.FalseBB)));
1397 // Update successor info
1398 CurMBB->addSuccessor(CB.TrueBB);
1399 CurMBB->addSuccessor(CB.FalseBB);
1402 /// visitJumpTable - Emit JumpTable node in the current MBB
1403 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1404 // Emit the code for the jump table
1405 assert(JT.Reg != -1U && "Should lower JT Header first!");
1406 MVT::ValueType PTy = TLI.getPointerTy();
1407 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1408 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1409 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1414 /// visitJumpTableHeader - This function emits necessary code to produce index
1415 /// in the JumpTable from switch case.
1416 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1417 SelectionDAGISel::JumpTableHeader &JTH) {
1418 // Subtract the lowest switch case value from the value being switched on
1419 // and conditional branch to default mbb if the result is greater than the
1420 // difference between smallest and largest cases.
1421 SDOperand SwitchOp = getValue(JTH.SValue);
1422 MVT::ValueType VT = SwitchOp.getValueType();
1423 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1424 DAG.getConstant(JTH.First, VT));
1426 // The SDNode we just created, which holds the value being switched on
1427 // minus the the smallest case value, needs to be copied to a virtual
1428 // register so it can be used as an index into the jump table in a
1429 // subsequent basic block. This value may be smaller or larger than the
1430 // target's pointer type, and therefore require extension or truncating.
1431 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1432 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1434 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1436 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1437 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1438 JT.Reg = JumpTableReg;
1440 // Emit the range check for the jump table, and branch to the default
1441 // block for the switch statement if the value being switched on exceeds
1442 // the largest case in the switch.
1443 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1444 DAG.getConstant(JTH.Last-JTH.First,VT),
1447 // Set NextBlock to be the MBB immediately after the current one, if any.
1448 // This is used to avoid emitting unnecessary branches to the next block.
1449 MachineBasicBlock *NextBlock = 0;
1450 MachineFunction::iterator BBI = CurMBB;
1451 if (++BBI != CurMBB->getParent()->end())
1454 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1455 DAG.getBasicBlock(JT.Default));
1457 if (JT.MBB == NextBlock)
1458 DAG.setRoot(BrCond);
1460 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1461 DAG.getBasicBlock(JT.MBB)));
1466 /// visitBitTestHeader - This function emits necessary code to produce value
1467 /// suitable for "bit tests"
1468 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1469 // Subtract the minimum value
1470 SDOperand SwitchOp = getValue(B.SValue);
1471 MVT::ValueType VT = SwitchOp.getValueType();
1472 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1473 DAG.getConstant(B.First, VT));
1476 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1477 DAG.getConstant(B.Range, VT),
1481 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1482 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1484 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1486 // Make desired shift
1487 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1488 DAG.getConstant(1, TLI.getPointerTy()),
1491 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1492 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1495 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1496 DAG.getBasicBlock(B.Default));
1498 // Set NextBlock to be the MBB immediately after the current one, if any.
1499 // This is used to avoid emitting unnecessary branches to the next block.
1500 MachineBasicBlock *NextBlock = 0;
1501 MachineFunction::iterator BBI = CurMBB;
1502 if (++BBI != CurMBB->getParent()->end())
1505 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1506 if (MBB == NextBlock)
1507 DAG.setRoot(BrRange);
1509 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1510 DAG.getBasicBlock(MBB)));
1512 CurMBB->addSuccessor(B.Default);
1513 CurMBB->addSuccessor(MBB);
1518 /// visitBitTestCase - this function produces one "bit test"
1519 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1521 SelectionDAGISel::BitTestCase &B) {
1522 // Emit bit tests and jumps
1523 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1525 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1527 DAG.getConstant(B.Mask,
1528 TLI.getPointerTy()));
1529 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1530 DAG.getConstant(0, TLI.getPointerTy()),
1532 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1533 AndCmp, DAG.getBasicBlock(B.TargetBB));
1535 // Set NextBlock to be the MBB immediately after the current one, if any.
1536 // This is used to avoid emitting unnecessary branches to the next block.
1537 MachineBasicBlock *NextBlock = 0;
1538 MachineFunction::iterator BBI = CurMBB;
1539 if (++BBI != CurMBB->getParent()->end())
1542 if (NextMBB == NextBlock)
1545 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1546 DAG.getBasicBlock(NextMBB)));
1548 CurMBB->addSuccessor(B.TargetBB);
1549 CurMBB->addSuccessor(NextMBB);
1554 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1555 // Retrieve successors.
1556 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1557 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1559 if (isa<InlineAsm>(I.getCalledValue()))
1562 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1564 // If the value of the invoke is used outside of its defining block, make it
1565 // available as a virtual register.
1566 if (!I.use_empty()) {
1567 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1568 if (VMI != FuncInfo.ValueMap.end())
1569 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
1572 // Drop into normal successor.
1573 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1574 DAG.getBasicBlock(Return)));
1576 // Update successor info
1577 CurMBB->addSuccessor(Return);
1578 CurMBB->addSuccessor(LandingPad);
1581 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1584 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1585 /// small case ranges).
1586 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1587 CaseRecVector& WorkList,
1589 MachineBasicBlock* Default) {
1590 Case& BackCase = *(CR.Range.second-1);
1592 // Size is the number of Cases represented by this range.
1593 unsigned Size = CR.Range.second - CR.Range.first;
1597 // Get the MachineFunction which holds the current MBB. This is used when
1598 // inserting any additional MBBs necessary to represent the switch.
1599 MachineFunction *CurMF = CurMBB->getParent();
1601 // Figure out which block is immediately after the current one.
1602 MachineBasicBlock *NextBlock = 0;
1603 MachineFunction::iterator BBI = CR.CaseBB;
1605 if (++BBI != CurMBB->getParent()->end())
1608 // TODO: If any two of the cases has the same destination, and if one value
1609 // is the same as the other, but has one bit unset that the other has set,
1610 // use bit manipulation to do two compares at once. For example:
1611 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1613 // Rearrange the case blocks so that the last one falls through if possible.
1614 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1615 // The last case block won't fall through into 'NextBlock' if we emit the
1616 // branches in this order. See if rearranging a case value would help.
1617 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1618 if (I->BB == NextBlock) {
1619 std::swap(*I, BackCase);
1625 // Create a CaseBlock record representing a conditional branch to
1626 // the Case's target mbb if the value being switched on SV is equal
1628 MachineBasicBlock *CurBlock = CR.CaseBB;
1629 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1630 MachineBasicBlock *FallThrough;
1632 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1633 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1635 // If the last case doesn't match, go to the default block.
1636 FallThrough = Default;
1639 Value *RHS, *LHS, *MHS;
1641 if (I->High == I->Low) {
1642 // This is just small small case range :) containing exactly 1 case
1644 LHS = SV; RHS = I->High; MHS = NULL;
1647 LHS = I->Low; MHS = SV; RHS = I->High;
1649 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1650 I->BB, FallThrough, CurBlock);
1652 // If emitting the first comparison, just call visitSwitchCase to emit the
1653 // code into the current block. Otherwise, push the CaseBlock onto the
1654 // vector to be later processed by SDISel, and insert the node's MBB
1655 // before the next MBB.
1656 if (CurBlock == CurMBB)
1657 visitSwitchCase(CB);
1659 SwitchCases.push_back(CB);
1661 CurBlock = FallThrough;
1667 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1668 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1669 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1672 /// handleJTSwitchCase - Emit jumptable for current switch case range
1673 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1674 CaseRecVector& WorkList,
1676 MachineBasicBlock* Default) {
1677 Case& FrontCase = *CR.Range.first;
1678 Case& BackCase = *(CR.Range.second-1);
1680 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1681 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1684 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1688 if (!areJTsAllowed(TLI) || TSize <= 3)
1691 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1695 DOUT << "Lowering jump table\n"
1696 << "First entry: " << First << ". Last entry: " << Last << "\n"
1697 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1699 // Get the MachineFunction which holds the current MBB. This is used when
1700 // inserting any additional MBBs necessary to represent the switch.
1701 MachineFunction *CurMF = CurMBB->getParent();
1703 // Figure out which block is immediately after the current one.
1704 MachineBasicBlock *NextBlock = 0;
1705 MachineFunction::iterator BBI = CR.CaseBB;
1707 if (++BBI != CurMBB->getParent()->end())
1710 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1712 // Create a new basic block to hold the code for loading the address
1713 // of the jump table, and jumping to it. Update successor information;
1714 // we will either branch to the default case for the switch, or the jump
1716 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1717 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1718 CR.CaseBB->addSuccessor(Default);
1719 CR.CaseBB->addSuccessor(JumpTableBB);
1721 // Build a vector of destination BBs, corresponding to each target
1722 // of the jump table. If the value of the jump table slot corresponds to
1723 // a case statement, push the case's BB onto the vector, otherwise, push
1725 std::vector<MachineBasicBlock*> DestBBs;
1726 int64_t TEI = First;
1727 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1728 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1729 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1731 if ((Low <= TEI) && (TEI <= High)) {
1732 DestBBs.push_back(I->BB);
1736 DestBBs.push_back(Default);
1740 // Update successor info. Add one edge to each unique successor.
1741 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1742 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1743 E = DestBBs.end(); I != E; ++I) {
1744 if (!SuccsHandled[(*I)->getNumber()]) {
1745 SuccsHandled[(*I)->getNumber()] = true;
1746 JumpTableBB->addSuccessor(*I);
1750 // Create a jump table index for this jump table, or return an existing
1752 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1754 // Set the jump table information so that we can codegen it as a second
1755 // MachineBasicBlock
1756 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1757 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1758 (CR.CaseBB == CurMBB));
1759 if (CR.CaseBB == CurMBB)
1760 visitJumpTableHeader(JT, JTH);
1762 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1767 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1769 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1770 CaseRecVector& WorkList,
1772 MachineBasicBlock* Default) {
1773 // Get the MachineFunction which holds the current MBB. This is used when
1774 // inserting any additional MBBs necessary to represent the switch.
1775 MachineFunction *CurMF = CurMBB->getParent();
1777 // Figure out which block is immediately after the current one.
1778 MachineBasicBlock *NextBlock = 0;
1779 MachineFunction::iterator BBI = CR.CaseBB;
1781 if (++BBI != CurMBB->getParent()->end())
1784 Case& FrontCase = *CR.Range.first;
1785 Case& BackCase = *(CR.Range.second-1);
1786 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1788 // Size is the number of Cases represented by this range.
1789 unsigned Size = CR.Range.second - CR.Range.first;
1791 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1792 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1794 CaseItr Pivot = CR.Range.first + Size/2;
1796 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1797 // (heuristically) allow us to emit JumpTable's later.
1799 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1803 uint64_t LSize = FrontCase.size();
1804 uint64_t RSize = TSize-LSize;
1805 DOUT << "Selecting best pivot: \n"
1806 << "First: " << First << ", Last: " << Last <<"\n"
1807 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1808 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1810 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1811 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1812 assert((RBegin-LEnd>=1) && "Invalid case distance");
1813 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1814 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1815 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1816 // Should always split in some non-trivial place
1818 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1819 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1820 << "Metric: " << Metric << "\n";
1821 if (FMetric < Metric) {
1824 DOUT << "Current metric set to: " << FMetric << "\n";
1830 if (areJTsAllowed(TLI)) {
1831 // If our case is dense we *really* should handle it earlier!
1832 assert((FMetric > 0) && "Should handle dense range earlier!");
1834 Pivot = CR.Range.first + Size/2;
1837 CaseRange LHSR(CR.Range.first, Pivot);
1838 CaseRange RHSR(Pivot, CR.Range.second);
1839 Constant *C = Pivot->Low;
1840 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1842 // We know that we branch to the LHS if the Value being switched on is
1843 // less than the Pivot value, C. We use this to optimize our binary
1844 // tree a bit, by recognizing that if SV is greater than or equal to the
1845 // LHS's Case Value, and that Case Value is exactly one less than the
1846 // Pivot's Value, then we can branch directly to the LHS's Target,
1847 // rather than creating a leaf node for it.
1848 if ((LHSR.second - LHSR.first) == 1 &&
1849 LHSR.first->High == CR.GE &&
1850 cast<ConstantInt>(C)->getSExtValue() ==
1851 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1852 TrueBB = LHSR.first->BB;
1854 TrueBB = new MachineBasicBlock(LLVMBB);
1855 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1856 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1859 // Similar to the optimization above, if the Value being switched on is
1860 // known to be less than the Constant CR.LT, and the current Case Value
1861 // is CR.LT - 1, then we can branch directly to the target block for
1862 // the current Case Value, rather than emitting a RHS leaf node for it.
1863 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1864 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1865 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1866 FalseBB = RHSR.first->BB;
1868 FalseBB = new MachineBasicBlock(LLVMBB);
1869 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1870 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1873 // Create a CaseBlock record representing a conditional branch to
1874 // the LHS node if the value being switched on SV is less than C.
1875 // Otherwise, branch to LHS.
1876 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1877 TrueBB, FalseBB, CR.CaseBB);
1879 if (CR.CaseBB == CurMBB)
1880 visitSwitchCase(CB);
1882 SwitchCases.push_back(CB);
1887 /// handleBitTestsSwitchCase - if current case range has few destination and
1888 /// range span less, than machine word bitwidth, encode case range into series
1889 /// of masks and emit bit tests with these masks.
1890 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1891 CaseRecVector& WorkList,
1893 MachineBasicBlock* Default){
1894 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1896 Case& FrontCase = *CR.Range.first;
1897 Case& BackCase = *(CR.Range.second-1);
1899 // Get the MachineFunction which holds the current MBB. This is used when
1900 // inserting any additional MBBs necessary to represent the switch.
1901 MachineFunction *CurMF = CurMBB->getParent();
1903 unsigned numCmps = 0;
1904 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1906 // Single case counts one, case range - two.
1907 if (I->Low == I->High)
1913 // Count unique destinations
1914 SmallSet<MachineBasicBlock*, 4> Dests;
1915 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1916 Dests.insert(I->BB);
1917 if (Dests.size() > 3)
1918 // Don't bother the code below, if there are too much unique destinations
1921 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1922 << "Total number of comparisons: " << numCmps << "\n";
1924 // Compute span of values.
1925 Constant* minValue = FrontCase.Low;
1926 Constant* maxValue = BackCase.High;
1927 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1928 cast<ConstantInt>(minValue)->getSExtValue();
1929 DOUT << "Compare range: " << range << "\n"
1930 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1931 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1933 if (range>=IntPtrBits ||
1934 (!(Dests.size() == 1 && numCmps >= 3) &&
1935 !(Dests.size() == 2 && numCmps >= 5) &&
1936 !(Dests.size() >= 3 && numCmps >= 6)))
1939 DOUT << "Emitting bit tests\n";
1940 int64_t lowBound = 0;
1942 // Optimize the case where all the case values fit in a
1943 // word without having to subtract minValue. In this case,
1944 // we can optimize away the subtraction.
1945 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1946 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1947 range = cast<ConstantInt>(maxValue)->getSExtValue();
1949 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1952 CaseBitsVector CasesBits;
1953 unsigned i, count = 0;
1955 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1956 MachineBasicBlock* Dest = I->BB;
1957 for (i = 0; i < count; ++i)
1958 if (Dest == CasesBits[i].BB)
1962 assert((count < 3) && "Too much destinations to test!");
1963 CasesBits.push_back(CaseBits(0, Dest, 0));
1967 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1968 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1970 for (uint64_t j = lo; j <= hi; j++) {
1971 CasesBits[i].Mask |= 1ULL << j;
1972 CasesBits[i].Bits++;
1976 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1978 SelectionDAGISel::BitTestInfo BTC;
1980 // Figure out which block is immediately after the current one.
1981 MachineFunction::iterator BBI = CR.CaseBB;
1984 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1987 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1988 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1989 << ", BB: " << CasesBits[i].BB << "\n";
1991 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1992 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1993 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1998 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1999 -1U, (CR.CaseBB == CurMBB),
2000 CR.CaseBB, Default, BTC);
2002 if (CR.CaseBB == CurMBB)
2003 visitBitTestHeader(BTB);
2005 BitTestCases.push_back(BTB);
2011 // Clusterify - Transform simple list of Cases into list of CaseRange's
2012 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2013 const SwitchInst& SI) {
2014 unsigned numCmps = 0;
2016 // Start with "simple" cases
2017 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2018 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2019 Cases.push_back(Case(SI.getSuccessorValue(i),
2020 SI.getSuccessorValue(i),
2023 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2025 // Merge case into clusters
2026 if (Cases.size()>=2)
2027 // Must recompute end() each iteration because it may be
2028 // invalidated by erase if we hold on to it
2029 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2030 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2031 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2032 MachineBasicBlock* nextBB = J->BB;
2033 MachineBasicBlock* currentBB = I->BB;
2035 // If the two neighboring cases go to the same destination, merge them
2036 // into a single case.
2037 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2045 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2046 if (I->Low != I->High)
2047 // A range counts double, since it requires two compares.
2054 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2055 // Figure out which block is immediately after the current one.
2056 MachineBasicBlock *NextBlock = 0;
2057 MachineFunction::iterator BBI = CurMBB;
2059 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2061 // If there is only the default destination, branch to it if it is not the
2062 // next basic block. Otherwise, just fall through.
2063 if (SI.getNumOperands() == 2) {
2064 // Update machine-CFG edges.
2066 // If this is not a fall-through branch, emit the branch.
2067 if (Default != NextBlock)
2068 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
2069 DAG.getBasicBlock(Default)));
2071 CurMBB->addSuccessor(Default);
2075 // If there are any non-default case statements, create a vector of Cases
2076 // representing each one, and sort the vector so that we can efficiently
2077 // create a binary search tree from them.
2079 unsigned numCmps = Clusterify(Cases, SI);
2080 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2081 << ". Total compares: " << numCmps << "\n";
2083 // Get the Value to be switched on and default basic blocks, which will be
2084 // inserted into CaseBlock records, representing basic blocks in the binary
2086 Value *SV = SI.getOperand(0);
2088 // Push the initial CaseRec onto the worklist
2089 CaseRecVector WorkList;
2090 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2092 while (!WorkList.empty()) {
2093 // Grab a record representing a case range to process off the worklist
2094 CaseRec CR = WorkList.back();
2095 WorkList.pop_back();
2097 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2100 // If the range has few cases (two or less) emit a series of specific
2102 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2105 // If the switch has more than 5 blocks, and at least 40% dense, and the
2106 // target supports indirect branches, then emit a jump table rather than
2107 // lowering the switch to a binary tree of conditional branches.
2108 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2111 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2112 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2113 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2118 void SelectionDAGLowering::visitSub(User &I) {
2119 // -0.0 - X --> fneg
2120 const Type *Ty = I.getType();
2121 if (isa<VectorType>(Ty)) {
2122 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2123 const VectorType *DestTy = cast<VectorType>(I.getType());
2124 const Type *ElTy = DestTy->getElementType();
2125 if (ElTy->isFloatingPoint()) {
2126 unsigned VL = DestTy->getNumElements();
2127 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2128 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2130 SDOperand Op2 = getValue(I.getOperand(1));
2131 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2137 if (Ty->isFloatingPoint()) {
2138 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2139 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2140 SDOperand Op2 = getValue(I.getOperand(1));
2141 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2146 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2149 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2150 SDOperand Op1 = getValue(I.getOperand(0));
2151 SDOperand Op2 = getValue(I.getOperand(1));
2153 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2156 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2157 SDOperand Op1 = getValue(I.getOperand(0));
2158 SDOperand Op2 = getValue(I.getOperand(1));
2160 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2161 MVT::getSizeInBits(Op2.getValueType()))
2162 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2163 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2164 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2166 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2169 void SelectionDAGLowering::visitICmp(User &I) {
2170 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2171 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2172 predicate = IC->getPredicate();
2173 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2174 predicate = ICmpInst::Predicate(IC->getPredicate());
2175 SDOperand Op1 = getValue(I.getOperand(0));
2176 SDOperand Op2 = getValue(I.getOperand(1));
2177 ISD::CondCode Opcode;
2178 switch (predicate) {
2179 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2180 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2181 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2182 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2183 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2184 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2185 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2186 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2187 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2188 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2190 assert(!"Invalid ICmp predicate value");
2191 Opcode = ISD::SETEQ;
2194 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2197 void SelectionDAGLowering::visitFCmp(User &I) {
2198 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2199 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2200 predicate = FC->getPredicate();
2201 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2202 predicate = FCmpInst::Predicate(FC->getPredicate());
2203 SDOperand Op1 = getValue(I.getOperand(0));
2204 SDOperand Op2 = getValue(I.getOperand(1));
2205 ISD::CondCode Condition, FOC, FPC;
2206 switch (predicate) {
2207 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2208 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2209 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2210 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2211 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2212 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2213 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2214 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2215 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2216 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2217 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2218 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2219 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2220 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2221 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2222 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2224 assert(!"Invalid FCmp predicate value");
2225 FOC = FPC = ISD::SETFALSE;
2228 if (FiniteOnlyFPMath())
2232 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2235 void SelectionDAGLowering::visitSelect(User &I) {
2236 SDOperand Cond = getValue(I.getOperand(0));
2237 SDOperand TrueVal = getValue(I.getOperand(1));
2238 SDOperand FalseVal = getValue(I.getOperand(2));
2239 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2240 TrueVal, FalseVal));
2244 void SelectionDAGLowering::visitTrunc(User &I) {
2245 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2246 SDOperand N = getValue(I.getOperand(0));
2247 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2248 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2251 void SelectionDAGLowering::visitZExt(User &I) {
2252 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2253 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2254 SDOperand N = getValue(I.getOperand(0));
2255 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2256 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2259 void SelectionDAGLowering::visitSExt(User &I) {
2260 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2261 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2262 SDOperand N = getValue(I.getOperand(0));
2263 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2264 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2267 void SelectionDAGLowering::visitFPTrunc(User &I) {
2268 // FPTrunc is never a no-op cast, no need to check
2269 SDOperand N = getValue(I.getOperand(0));
2270 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2271 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2274 void SelectionDAGLowering::visitFPExt(User &I){
2275 // FPTrunc is never a no-op cast, no need to check
2276 SDOperand N = getValue(I.getOperand(0));
2277 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2278 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2281 void SelectionDAGLowering::visitFPToUI(User &I) {
2282 // FPToUI is never a no-op cast, no need to check
2283 SDOperand N = getValue(I.getOperand(0));
2284 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2285 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2288 void SelectionDAGLowering::visitFPToSI(User &I) {
2289 // FPToSI is never a no-op cast, no need to check
2290 SDOperand N = getValue(I.getOperand(0));
2291 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2292 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2295 void SelectionDAGLowering::visitUIToFP(User &I) {
2296 // UIToFP is never a no-op cast, no need to check
2297 SDOperand N = getValue(I.getOperand(0));
2298 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2299 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2302 void SelectionDAGLowering::visitSIToFP(User &I){
2303 // UIToFP is never a no-op cast, no need to check
2304 SDOperand N = getValue(I.getOperand(0));
2305 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2306 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2309 void SelectionDAGLowering::visitPtrToInt(User &I) {
2310 // What to do depends on the size of the integer and the size of the pointer.
2311 // We can either truncate, zero extend, or no-op, accordingly.
2312 SDOperand N = getValue(I.getOperand(0));
2313 MVT::ValueType SrcVT = N.getValueType();
2314 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2316 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2317 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2319 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2320 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2321 setValue(&I, Result);
2324 void SelectionDAGLowering::visitIntToPtr(User &I) {
2325 // What to do depends on the size of the integer and the size of the pointer.
2326 // We can either truncate, zero extend, or no-op, accordingly.
2327 SDOperand N = getValue(I.getOperand(0));
2328 MVT::ValueType SrcVT = N.getValueType();
2329 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2330 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2331 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2333 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2334 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2337 void SelectionDAGLowering::visitBitCast(User &I) {
2338 SDOperand N = getValue(I.getOperand(0));
2339 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2341 // BitCast assures us that source and destination are the same size so this
2342 // is either a BIT_CONVERT or a no-op.
2343 if (DestVT != N.getValueType())
2344 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2346 setValue(&I, N); // noop cast.
2349 void SelectionDAGLowering::visitInsertElement(User &I) {
2350 SDOperand InVec = getValue(I.getOperand(0));
2351 SDOperand InVal = getValue(I.getOperand(1));
2352 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2353 getValue(I.getOperand(2)));
2355 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2356 TLI.getValueType(I.getType()),
2357 InVec, InVal, InIdx));
2360 void SelectionDAGLowering::visitExtractElement(User &I) {
2361 SDOperand InVec = getValue(I.getOperand(0));
2362 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2363 getValue(I.getOperand(1)));
2364 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2365 TLI.getValueType(I.getType()), InVec, InIdx));
2368 void SelectionDAGLowering::visitShuffleVector(User &I) {
2369 SDOperand V1 = getValue(I.getOperand(0));
2370 SDOperand V2 = getValue(I.getOperand(1));
2371 SDOperand Mask = getValue(I.getOperand(2));
2373 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2374 TLI.getValueType(I.getType()),
2379 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2380 SDOperand N = getValue(I.getOperand(0));
2381 const Type *Ty = I.getOperand(0)->getType();
2383 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2386 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2387 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2390 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2391 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2392 DAG.getIntPtrConstant(Offset));
2394 Ty = StTy->getElementType(Field);
2396 Ty = cast<SequentialType>(Ty)->getElementType();
2398 // If this is a constant subscript, handle it quickly.
2399 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2400 if (CI->getZExtValue() == 0) continue;
2402 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2403 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2404 DAG.getIntPtrConstant(Offs));
2408 // N = N + Idx * ElementSize;
2409 uint64_t ElementSize = TD->getABITypeSize(Ty);
2410 SDOperand IdxN = getValue(Idx);
2412 // If the index is smaller or larger than intptr_t, truncate or extend
2414 if (IdxN.getValueType() < N.getValueType()) {
2415 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2416 } else if (IdxN.getValueType() > N.getValueType())
2417 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2419 // If this is a multiply by a power of two, turn it into a shl
2420 // immediately. This is a very common case.
2421 if (isPowerOf2_64(ElementSize)) {
2422 unsigned Amt = Log2_64(ElementSize);
2423 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2424 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2425 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2429 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2430 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2431 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2437 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2438 // If this is a fixed sized alloca in the entry block of the function,
2439 // allocate it statically on the stack.
2440 if (FuncInfo.StaticAllocaMap.count(&I))
2441 return; // getValue will auto-populate this.
2443 const Type *Ty = I.getAllocatedType();
2444 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2446 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2449 SDOperand AllocSize = getValue(I.getArraySize());
2450 MVT::ValueType IntPtr = TLI.getPointerTy();
2451 if (IntPtr < AllocSize.getValueType())
2452 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2453 else if (IntPtr > AllocSize.getValueType())
2454 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2456 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2457 DAG.getIntPtrConstant(TySize));
2459 // Handle alignment. If the requested alignment is less than or equal to
2460 // the stack alignment, ignore it. If the size is greater than or equal to
2461 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2462 unsigned StackAlign =
2463 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2464 if (Align <= StackAlign)
2467 // Round the size of the allocation up to the stack alignment size
2468 // by add SA-1 to the size.
2469 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2470 DAG.getIntPtrConstant(StackAlign-1));
2471 // Mask out the low bits for alignment purposes.
2472 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2473 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2475 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2476 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2478 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2480 DAG.setRoot(DSA.getValue(1));
2482 // Inform the Frame Information that we have just allocated a variable-sized
2484 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2487 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2488 SDOperand Ptr = getValue(I.getOperand(0));
2494 // Do not serialize non-volatile loads against each other.
2495 Root = DAG.getRoot();
2498 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2499 Root, I.isVolatile(), I.getAlignment()));
2502 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2503 const Value *SV, SDOperand Root,
2505 unsigned Alignment) {
2507 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2508 isVolatile, Alignment);
2511 DAG.setRoot(L.getValue(1));
2513 PendingLoads.push_back(L.getValue(1));
2519 void SelectionDAGLowering::visitStore(StoreInst &I) {
2520 Value *SrcV = I.getOperand(0);
2521 SDOperand Src = getValue(SrcV);
2522 SDOperand Ptr = getValue(I.getOperand(1));
2523 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2524 I.isVolatile(), I.getAlignment()));
2527 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2529 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2530 unsigned Intrinsic) {
2531 bool HasChain = !I.doesNotAccessMemory();
2532 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2534 // Build the operand list.
2535 SmallVector<SDOperand, 8> Ops;
2536 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2538 // We don't need to serialize loads against other loads.
2539 Ops.push_back(DAG.getRoot());
2541 Ops.push_back(getRoot());
2545 // Add the intrinsic ID as an integer operand.
2546 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2548 // Add all operands of the call to the operand list.
2549 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2550 SDOperand Op = getValue(I.getOperand(i));
2551 assert(TLI.isTypeLegal(Op.getValueType()) &&
2552 "Intrinsic uses a non-legal type?");
2556 std::vector<MVT::ValueType> VTs;
2557 if (I.getType() != Type::VoidTy) {
2558 MVT::ValueType VT = TLI.getValueType(I.getType());
2559 if (MVT::isVector(VT)) {
2560 const VectorType *DestTy = cast<VectorType>(I.getType());
2561 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2563 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2564 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2567 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2571 VTs.push_back(MVT::Other);
2573 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2578 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2579 &Ops[0], Ops.size());
2580 else if (I.getType() != Type::VoidTy)
2581 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2582 &Ops[0], Ops.size());
2584 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2585 &Ops[0], Ops.size());
2588 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2590 PendingLoads.push_back(Chain);
2594 if (I.getType() != Type::VoidTy) {
2595 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2596 MVT::ValueType VT = TLI.getValueType(PTy);
2597 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2599 setValue(&I, Result);
2603 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2604 static GlobalVariable *ExtractTypeInfo (Value *V) {
2605 V = IntrinsicInst::StripPointerCasts(V);
2606 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2607 assert ((GV || isa<ConstantPointerNull>(V)) &&
2608 "TypeInfo must be a global variable or NULL");
2612 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2613 /// call, and add them to the specified machine basic block.
2614 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2615 MachineBasicBlock *MBB) {
2616 // Inform the MachineModuleInfo of the personality for this landing pad.
2617 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2618 assert(CE->getOpcode() == Instruction::BitCast &&
2619 isa<Function>(CE->getOperand(0)) &&
2620 "Personality should be a function");
2621 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2623 // Gather all the type infos for this landing pad and pass them along to
2624 // MachineModuleInfo.
2625 std::vector<GlobalVariable *> TyInfo;
2626 unsigned N = I.getNumOperands();
2628 for (unsigned i = N - 1; i > 2; --i) {
2629 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2630 unsigned FilterLength = CI->getZExtValue();
2631 unsigned FirstCatch = i + FilterLength + !FilterLength;
2632 assert (FirstCatch <= N && "Invalid filter length");
2634 if (FirstCatch < N) {
2635 TyInfo.reserve(N - FirstCatch);
2636 for (unsigned j = FirstCatch; j < N; ++j)
2637 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2638 MMI->addCatchTypeInfo(MBB, TyInfo);
2642 if (!FilterLength) {
2644 MMI->addCleanup(MBB);
2647 TyInfo.reserve(FilterLength - 1);
2648 for (unsigned j = i + 1; j < FirstCatch; ++j)
2649 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2650 MMI->addFilterTypeInfo(MBB, TyInfo);
2659 TyInfo.reserve(N - 3);
2660 for (unsigned j = 3; j < N; ++j)
2661 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2662 MMI->addCatchTypeInfo(MBB, TyInfo);
2666 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2667 /// we want to emit this as a call to a named external function, return the name
2668 /// otherwise lower it and return null.
2670 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2671 switch (Intrinsic) {
2673 // By default, turn this into a target intrinsic node.
2674 visitTargetIntrinsic(I, Intrinsic);
2676 case Intrinsic::vastart: visitVAStart(I); return 0;
2677 case Intrinsic::vaend: visitVAEnd(I); return 0;
2678 case Intrinsic::vacopy: visitVACopy(I); return 0;
2679 case Intrinsic::returnaddress:
2680 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2681 getValue(I.getOperand(1))));
2683 case Intrinsic::frameaddress:
2684 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2685 getValue(I.getOperand(1))));
2687 case Intrinsic::setjmp:
2688 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2690 case Intrinsic::longjmp:
2691 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2693 case Intrinsic::memcpy_i32:
2694 case Intrinsic::memcpy_i64:
2695 visitMemIntrinsic(I, ISD::MEMCPY);
2697 case Intrinsic::memset_i32:
2698 case Intrinsic::memset_i64:
2699 visitMemIntrinsic(I, ISD::MEMSET);
2701 case Intrinsic::memmove_i32:
2702 case Intrinsic::memmove_i64:
2703 visitMemIntrinsic(I, ISD::MEMMOVE);
2706 case Intrinsic::dbg_stoppoint: {
2707 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2708 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2709 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2713 Ops[1] = getValue(SPI.getLineValue());
2714 Ops[2] = getValue(SPI.getColumnValue());
2716 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2717 assert(DD && "Not a debug information descriptor");
2718 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2720 Ops[3] = DAG.getString(CompileUnit->getFileName());
2721 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2723 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2728 case Intrinsic::dbg_region_start: {
2729 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2730 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2731 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2732 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2733 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2734 DAG.getConstant(LabelID, MVT::i32),
2735 DAG.getConstant(0, MVT::i32)));
2740 case Intrinsic::dbg_region_end: {
2741 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2742 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2743 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2744 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2745 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2746 DAG.getConstant(LabelID, MVT::i32),
2747 DAG.getConstant(0, MVT::i32)));
2752 case Intrinsic::dbg_func_start: {
2753 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2755 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2756 Value *SP = FSI.getSubprogram();
2757 if (SP && MMI->Verify(SP)) {
2758 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
2759 // what (most?) gdb expects.
2760 DebugInfoDesc *DD = MMI->getDescFor(SP);
2761 assert(DD && "Not a debug information descriptor");
2762 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
2763 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
2764 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(),
2765 CompileUnit->getFileName());
2766 // Record the source line but does create a label. It will be emitted
2767 // at asm emission time.
2768 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
2773 case Intrinsic::dbg_declare: {
2774 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2775 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2776 Value *Variable = DI.getVariable();
2777 if (MMI && Variable && MMI->Verify(Variable))
2778 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
2779 getValue(DI.getAddress()), getValue(Variable)));
2783 case Intrinsic::eh_exception: {
2784 if (ExceptionHandling) {
2785 if (!CurMBB->isLandingPad()) {
2786 // FIXME: Mark exception register as live in. Hack for PR1508.
2787 unsigned Reg = TLI.getExceptionAddressRegister();
2788 if (Reg) CurMBB->addLiveIn(Reg);
2790 // Insert the EXCEPTIONADDR instruction.
2791 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2793 Ops[0] = DAG.getRoot();
2794 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2796 DAG.setRoot(Op.getValue(1));
2798 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2803 case Intrinsic::eh_selector_i32:
2804 case Intrinsic::eh_selector_i64: {
2805 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2806 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2807 MVT::i32 : MVT::i64);
2809 if (ExceptionHandling && MMI) {
2810 if (CurMBB->isLandingPad())
2811 addCatchInfo(I, MMI, CurMBB);
2814 FuncInfo.CatchInfoLost.insert(&I);
2816 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2817 unsigned Reg = TLI.getExceptionSelectorRegister();
2818 if (Reg) CurMBB->addLiveIn(Reg);
2821 // Insert the EHSELECTION instruction.
2822 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2824 Ops[0] = getValue(I.getOperand(1));
2826 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2828 DAG.setRoot(Op.getValue(1));
2830 setValue(&I, DAG.getConstant(0, VT));
2836 case Intrinsic::eh_typeid_for_i32:
2837 case Intrinsic::eh_typeid_for_i64: {
2838 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2839 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2840 MVT::i32 : MVT::i64);
2843 // Find the type id for the given typeinfo.
2844 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2846 unsigned TypeID = MMI->getTypeIDFor(GV);
2847 setValue(&I, DAG.getConstant(TypeID, VT));
2849 // Return something different to eh_selector.
2850 setValue(&I, DAG.getConstant(1, VT));
2856 case Intrinsic::eh_return: {
2857 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2859 if (MMI && ExceptionHandling) {
2860 MMI->setCallsEHReturn(true);
2861 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2864 getValue(I.getOperand(1)),
2865 getValue(I.getOperand(2))));
2867 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2873 case Intrinsic::eh_unwind_init: {
2874 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2875 MMI->setCallsUnwindInit(true);
2881 case Intrinsic::eh_dwarf_cfa: {
2882 if (ExceptionHandling) {
2883 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2885 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2886 CfaArg = DAG.getNode(ISD::TRUNCATE,
2887 TLI.getPointerTy(), getValue(I.getOperand(1)));
2889 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2890 TLI.getPointerTy(), getValue(I.getOperand(1)));
2892 SDOperand Offset = DAG.getNode(ISD::ADD,
2894 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2895 TLI.getPointerTy()),
2897 setValue(&I, DAG.getNode(ISD::ADD,
2899 DAG.getNode(ISD::FRAMEADDR,
2902 TLI.getPointerTy())),
2905 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2911 case Intrinsic::sqrt:
2912 setValue(&I, DAG.getNode(ISD::FSQRT,
2913 getValue(I.getOperand(1)).getValueType(),
2914 getValue(I.getOperand(1))));
2916 case Intrinsic::powi:
2917 setValue(&I, DAG.getNode(ISD::FPOWI,
2918 getValue(I.getOperand(1)).getValueType(),
2919 getValue(I.getOperand(1)),
2920 getValue(I.getOperand(2))));
2922 case Intrinsic::sin:
2923 setValue(&I, DAG.getNode(ISD::FSIN,
2924 getValue(I.getOperand(1)).getValueType(),
2925 getValue(I.getOperand(1))));
2927 case Intrinsic::cos:
2928 setValue(&I, DAG.getNode(ISD::FCOS,
2929 getValue(I.getOperand(1)).getValueType(),
2930 getValue(I.getOperand(1))));
2932 case Intrinsic::pow:
2933 setValue(&I, DAG.getNode(ISD::FPOW,
2934 getValue(I.getOperand(1)).getValueType(),
2935 getValue(I.getOperand(1)),
2936 getValue(I.getOperand(2))));
2938 case Intrinsic::pcmarker: {
2939 SDOperand Tmp = getValue(I.getOperand(1));
2940 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2943 case Intrinsic::readcyclecounter: {
2944 SDOperand Op = getRoot();
2945 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2946 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2949 DAG.setRoot(Tmp.getValue(1));
2952 case Intrinsic::part_select: {
2953 // Currently not implemented: just abort
2954 assert(0 && "part_select intrinsic not implemented");
2957 case Intrinsic::part_set: {
2958 // Currently not implemented: just abort
2959 assert(0 && "part_set intrinsic not implemented");
2962 case Intrinsic::bswap:
2963 setValue(&I, DAG.getNode(ISD::BSWAP,
2964 getValue(I.getOperand(1)).getValueType(),
2965 getValue(I.getOperand(1))));
2967 case Intrinsic::cttz: {
2968 SDOperand Arg = getValue(I.getOperand(1));
2969 MVT::ValueType Ty = Arg.getValueType();
2970 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2971 setValue(&I, result);
2974 case Intrinsic::ctlz: {
2975 SDOperand Arg = getValue(I.getOperand(1));
2976 MVT::ValueType Ty = Arg.getValueType();
2977 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2978 setValue(&I, result);
2981 case Intrinsic::ctpop: {
2982 SDOperand Arg = getValue(I.getOperand(1));
2983 MVT::ValueType Ty = Arg.getValueType();
2984 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2985 setValue(&I, result);
2988 case Intrinsic::stacksave: {
2989 SDOperand Op = getRoot();
2990 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2991 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2993 DAG.setRoot(Tmp.getValue(1));
2996 case Intrinsic::stackrestore: {
2997 SDOperand Tmp = getValue(I.getOperand(1));
2998 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3001 case Intrinsic::var_annotation:
3002 // Discard annotate attributes
3005 case Intrinsic::init_trampoline: {
3007 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
3011 Ops[1] = getValue(I.getOperand(1));
3012 Ops[2] = getValue(I.getOperand(2));
3013 Ops[3] = getValue(I.getOperand(3));
3014 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3015 Ops[5] = DAG.getSrcValue(F);
3017 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
3018 DAG.getNodeValueTypes(TLI.getPointerTy(),
3023 DAG.setRoot(Tmp.getValue(1));
3027 case Intrinsic::gcroot:
3029 Value *Alloca = I.getOperand(1);
3030 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3032 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3033 GCI->addStackRoot(FI->getIndex(), TypeMap);
3037 case Intrinsic::gcread:
3038 case Intrinsic::gcwrite:
3039 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3042 case Intrinsic::flt_rounds: {
3043 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3047 case Intrinsic::trap: {
3048 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3051 case Intrinsic::prefetch: {
3054 Ops[1] = getValue(I.getOperand(1));
3055 Ops[2] = getValue(I.getOperand(2));
3056 Ops[3] = getValue(I.getOperand(3));
3057 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3061 case Intrinsic::memory_barrier: {
3064 for (int x = 1; x < 6; ++x)
3065 Ops[x] = getValue(I.getOperand(x));
3067 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3070 case Intrinsic::atomic_lcs: {
3071 SDOperand Root = getRoot();
3072 SDOperand O3 = getValue(I.getOperand(3));
3073 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LCS, Root,
3074 getValue(I.getOperand(1)),
3075 getValue(I.getOperand(2)),
3076 O3, O3.getValueType());
3078 DAG.setRoot(L.getValue(1));
3081 case Intrinsic::atomic_las: {
3082 SDOperand Root = getRoot();
3083 SDOperand O2 = getValue(I.getOperand(2));
3084 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LAS, Root,
3085 getValue(I.getOperand(1)),
3086 O2, O2.getValueType());
3088 DAG.setRoot(L.getValue(1));
3091 case Intrinsic::atomic_swap: {
3092 SDOperand Root = getRoot();
3093 SDOperand O2 = getValue(I.getOperand(2));
3094 SDOperand L = DAG.getAtomic(ISD::ATOMIC_SWAP, Root,
3095 getValue(I.getOperand(1)),
3096 O2, O2.getValueType());
3098 DAG.setRoot(L.getValue(1));
3106 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
3108 MachineBasicBlock *LandingPad) {
3109 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3110 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3111 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3112 unsigned BeginLabel = 0, EndLabel = 0;
3114 TargetLowering::ArgListTy Args;
3115 TargetLowering::ArgListEntry Entry;
3116 Args.reserve(CS.arg_size());
3117 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3119 SDOperand ArgNode = getValue(*i);
3120 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3122 unsigned attrInd = i - CS.arg_begin() + 1;
3123 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3124 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3125 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3126 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3127 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3128 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3129 Entry.Alignment = CS.getParamAlignment(attrInd);
3130 Args.push_back(Entry);
3133 bool MarkTryRange = LandingPad ||
3134 // C++ requires special handling of 'nounwind' calls.
3135 (CS.doesNotThrow());
3137 if (MarkTryRange && ExceptionHandling && MMI) {
3138 // Insert a label before the invoke call to mark the try range. This can be
3139 // used to detect deletion of the invoke via the MachineModuleInfo.
3140 BeginLabel = MMI->NextLabelID();
3141 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3142 DAG.getConstant(BeginLabel, MVT::i32),
3143 DAG.getConstant(1, MVT::i32)));
3146 std::pair<SDOperand,SDOperand> Result =
3147 TLI.LowerCallTo(getRoot(), CS.getType(),
3148 CS.paramHasAttr(0, ParamAttr::SExt),
3149 CS.paramHasAttr(0, ParamAttr::ZExt),
3150 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3152 if (CS.getType() != Type::VoidTy)
3153 setValue(CS.getInstruction(), Result.first);
3154 DAG.setRoot(Result.second);
3156 if (MarkTryRange && ExceptionHandling && MMI) {
3157 // Insert a label at the end of the invoke call to mark the try range. This
3158 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3159 EndLabel = MMI->NextLabelID();
3160 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3161 DAG.getConstant(EndLabel, MVT::i32),
3162 DAG.getConstant(1, MVT::i32)));
3164 // Inform MachineModuleInfo of range.
3165 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3170 void SelectionDAGLowering::visitCall(CallInst &I) {
3171 const char *RenameFn = 0;
3172 if (Function *F = I.getCalledFunction()) {
3173 if (F->isDeclaration()) {
3174 if (unsigned IID = F->getIntrinsicID()) {
3175 RenameFn = visitIntrinsicCall(I, IID);
3181 // Check for well-known libc/libm calls. If the function is internal, it
3182 // can't be a library call.
3183 unsigned NameLen = F->getNameLen();
3184 if (!F->hasInternalLinkage() && NameLen) {
3185 const char *NameStr = F->getNameStart();
3186 if (NameStr[0] == 'c' &&
3187 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3188 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3189 if (I.getNumOperands() == 3 && // Basic sanity checks.
3190 I.getOperand(1)->getType()->isFloatingPoint() &&
3191 I.getType() == I.getOperand(1)->getType() &&
3192 I.getType() == I.getOperand(2)->getType()) {
3193 SDOperand LHS = getValue(I.getOperand(1));
3194 SDOperand RHS = getValue(I.getOperand(2));
3195 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3199 } else if (NameStr[0] == 'f' &&
3200 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3201 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3202 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3203 if (I.getNumOperands() == 2 && // Basic sanity checks.
3204 I.getOperand(1)->getType()->isFloatingPoint() &&
3205 I.getType() == I.getOperand(1)->getType()) {
3206 SDOperand Tmp = getValue(I.getOperand(1));
3207 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3210 } else if (NameStr[0] == 's' &&
3211 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3212 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3213 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3214 if (I.getNumOperands() == 2 && // Basic sanity checks.
3215 I.getOperand(1)->getType()->isFloatingPoint() &&
3216 I.getType() == I.getOperand(1)->getType()) {
3217 SDOperand Tmp = getValue(I.getOperand(1));
3218 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3221 } else if (NameStr[0] == 'c' &&
3222 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3223 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3224 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3225 if (I.getNumOperands() == 2 && // Basic sanity checks.
3226 I.getOperand(1)->getType()->isFloatingPoint() &&
3227 I.getType() == I.getOperand(1)->getType()) {
3228 SDOperand Tmp = getValue(I.getOperand(1));
3229 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3234 } else if (isa<InlineAsm>(I.getOperand(0))) {
3241 Callee = getValue(I.getOperand(0));
3243 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3245 LowerCallTo(&I, Callee, I.isTailCall());
3249 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3250 /// this value and returns the result as a ValueVT value. This uses
3251 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3252 /// If the Flag pointer is NULL, no flag is used.
3253 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3254 SDOperand &Chain, SDOperand *Flag)const{
3255 // Copy the legal parts from the registers.
3256 unsigned NumParts = Regs.size();
3257 SmallVector<SDOperand, 8> Parts(NumParts);
3258 for (unsigned i = 0; i != NumParts; ++i) {
3259 SDOperand Part = Flag ?
3260 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3261 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3262 Chain = Part.getValue(1);
3264 *Flag = Part.getValue(2);
3268 // Assemble the legal parts into the final value.
3269 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3272 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3273 /// specified value into the registers specified by this object. This uses
3274 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3275 /// If the Flag pointer is NULL, no flag is used.
3276 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3277 SDOperand &Chain, SDOperand *Flag) const {
3278 // Get the list of the values's legal parts.
3279 unsigned NumParts = Regs.size();
3280 SmallVector<SDOperand, 8> Parts(NumParts);
3281 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3283 // Copy the parts into the registers.
3284 for (unsigned i = 0; i != NumParts; ++i) {
3285 SDOperand Part = Flag ?
3286 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3287 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3288 Chain = Part.getValue(0);
3290 *Flag = Part.getValue(1);
3294 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3295 /// operand list. This adds the code marker and includes the number of
3296 /// values added into it.
3297 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3298 std::vector<SDOperand> &Ops) const {
3299 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3300 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3301 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3302 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3305 /// isAllocatableRegister - If the specified register is safe to allocate,
3306 /// i.e. it isn't a stack pointer or some other special register, return the
3307 /// register class for the register. Otherwise, return null.
3308 static const TargetRegisterClass *
3309 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3310 const TargetLowering &TLI,
3311 const TargetRegisterInfo *TRI) {
3312 MVT::ValueType FoundVT = MVT::Other;
3313 const TargetRegisterClass *FoundRC = 0;
3314 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3315 E = TRI->regclass_end(); RCI != E; ++RCI) {
3316 MVT::ValueType ThisVT = MVT::Other;
3318 const TargetRegisterClass *RC = *RCI;
3319 // If none of the the value types for this register class are valid, we
3320 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3321 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3323 if (TLI.isTypeLegal(*I)) {
3324 // If we have already found this register in a different register class,
3325 // choose the one with the largest VT specified. For example, on
3326 // PowerPC, we favor f64 register classes over f32.
3327 if (FoundVT == MVT::Other ||
3328 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3335 if (ThisVT == MVT::Other) continue;
3337 // NOTE: This isn't ideal. In particular, this might allocate the
3338 // frame pointer in functions that need it (due to them not being taken
3339 // out of allocation, because a variable sized allocation hasn't been seen
3340 // yet). This is a slight code pessimization, but should still work.
3341 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3342 E = RC->allocation_order_end(MF); I != E; ++I)
3344 // We found a matching register class. Keep looking at others in case
3345 // we find one with larger registers that this physreg is also in.
3356 /// AsmOperandInfo - This contains information for each constraint that we are
3358 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3359 /// CallOperand - If this is the result output operand or a clobber
3360 /// this is null, otherwise it is the incoming operand to the CallInst.
3361 /// This gets modified as the asm is processed.
3362 SDOperand CallOperand;
3364 /// AssignedRegs - If this is a register or register class operand, this
3365 /// contains the set of register corresponding to the operand.
3366 RegsForValue AssignedRegs;
3368 SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3369 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3372 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3373 /// busy in OutputRegs/InputRegs.
3374 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3375 std::set<unsigned> &OutputRegs,
3376 std::set<unsigned> &InputRegs,
3377 const TargetRegisterInfo &TRI) const {
3379 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3380 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3383 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3384 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3389 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3391 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3392 const TargetRegisterInfo &TRI) {
3393 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3395 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3396 for (; *Aliases; ++Aliases)
3397 Regs.insert(*Aliases);
3400 } // end anon namespace.
3403 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3404 /// specified operand. We prefer to assign virtual registers, to allow the
3405 /// register allocator handle the assignment process. However, if the asm uses
3406 /// features that we can't model on machineinstrs, we have SDISel do the
3407 /// allocation. This produces generally horrible, but correct, code.
3409 /// OpInfo describes the operand.
3410 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3411 /// or any explicitly clobbered registers.
3412 /// Input and OutputRegs are the set of already allocated physical registers.
3414 void SelectionDAGLowering::
3415 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3416 std::set<unsigned> &OutputRegs,
3417 std::set<unsigned> &InputRegs) {
3418 // Compute whether this value requires an input register, an output register,
3420 bool isOutReg = false;
3421 bool isInReg = false;
3422 switch (OpInfo.Type) {
3423 case InlineAsm::isOutput:
3426 // If this is an early-clobber output, or if there is an input
3427 // constraint that matches this, we need to reserve the input register
3428 // so no other inputs allocate to it.
3429 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3431 case InlineAsm::isInput:
3435 case InlineAsm::isClobber:
3442 MachineFunction &MF = DAG.getMachineFunction();
3443 std::vector<unsigned> Regs;
3445 // If this is a constraint for a single physreg, or a constraint for a
3446 // register class, find it.
3447 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3448 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3449 OpInfo.ConstraintVT);
3451 unsigned NumRegs = 1;
3452 if (OpInfo.ConstraintVT != MVT::Other)
3453 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3454 MVT::ValueType RegVT;
3455 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3458 // If this is a constraint for a specific physical register, like {r17},
3460 if (PhysReg.first) {
3461 if (OpInfo.ConstraintVT == MVT::Other)
3462 ValueVT = *PhysReg.second->vt_begin();
3464 // Get the actual register value type. This is important, because the user
3465 // may have asked for (e.g.) the AX register in i32 type. We need to
3466 // remember that AX is actually i16 to get the right extension.
3467 RegVT = *PhysReg.second->vt_begin();
3469 // This is a explicit reference to a physical register.
3470 Regs.push_back(PhysReg.first);
3472 // If this is an expanded reference, add the rest of the regs to Regs.
3474 TargetRegisterClass::iterator I = PhysReg.second->begin();
3475 TargetRegisterClass::iterator E = PhysReg.second->end();
3476 for (; *I != PhysReg.first; ++I)
3477 assert(I != E && "Didn't find reg!");
3479 // Already added the first reg.
3481 for (; NumRegs; --NumRegs, ++I) {
3482 assert(I != E && "Ran out of registers to allocate!");
3486 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3487 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3488 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
3492 // Otherwise, if this was a reference to an LLVM register class, create vregs
3493 // for this reference.
3494 std::vector<unsigned> RegClassRegs;
3495 const TargetRegisterClass *RC = PhysReg.second;
3497 // If this is an early clobber or tied register, our regalloc doesn't know
3498 // how to maintain the constraint. If it isn't, go ahead and create vreg
3499 // and let the regalloc do the right thing.
3500 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3501 // If there is some other early clobber and this is an input register,
3502 // then we are forced to pre-allocate the input reg so it doesn't
3503 // conflict with the earlyclobber.
3504 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3505 RegVT = *PhysReg.second->vt_begin();
3507 if (OpInfo.ConstraintVT == MVT::Other)
3510 // Create the appropriate number of virtual registers.
3511 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3512 for (; NumRegs; --NumRegs)
3513 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
3515 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3519 // Otherwise, we can't allocate it. Let the code below figure out how to
3520 // maintain these constraints.
3521 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3524 // This is a reference to a register class that doesn't directly correspond
3525 // to an LLVM register class. Allocate NumRegs consecutive, available,
3526 // registers from the class.
3527 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3528 OpInfo.ConstraintVT);
3531 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3532 unsigned NumAllocated = 0;
3533 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3534 unsigned Reg = RegClassRegs[i];
3535 // See if this register is available.
3536 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3537 (isInReg && InputRegs.count(Reg))) { // Already used.
3538 // Make sure we find consecutive registers.
3543 // Check to see if this register is allocatable (i.e. don't give out the
3546 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
3547 if (!RC) { // Couldn't allocate this register.
3548 // Reset NumAllocated to make sure we return consecutive registers.
3554 // Okay, this register is good, we can use it.
3557 // If we allocated enough consecutive registers, succeed.
3558 if (NumAllocated == NumRegs) {
3559 unsigned RegStart = (i-NumAllocated)+1;
3560 unsigned RegEnd = i+1;
3561 // Mark all of the allocated registers used.
3562 for (unsigned i = RegStart; i != RegEnd; ++i)
3563 Regs.push_back(RegClassRegs[i]);
3565 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3566 OpInfo.ConstraintVT);
3567 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
3572 // Otherwise, we couldn't allocate enough registers for this.
3577 /// visitInlineAsm - Handle a call to an InlineAsm object.
3579 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3580 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3582 /// ConstraintOperands - Information about all of the constraints.
3583 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
3585 SDOperand Chain = getRoot();
3588 std::set<unsigned> OutputRegs, InputRegs;
3590 // Do a prepass over the constraints, canonicalizing them, and building up the
3591 // ConstraintOperands list.
3592 std::vector<InlineAsm::ConstraintInfo>
3593 ConstraintInfos = IA->ParseConstraints();
3595 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3596 // constraint. If so, we can't let the register allocator allocate any input
3597 // registers, because it will not know to avoid the earlyclobbered output reg.
3598 bool SawEarlyClobber = false;
3600 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3601 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3602 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
3603 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
3605 MVT::ValueType OpVT = MVT::Other;
3607 // Compute the value type for each operand.
3608 switch (OpInfo.Type) {
3609 case InlineAsm::isOutput:
3610 if (!OpInfo.isIndirect) {
3611 // The return value of the call is this value. As such, there is no
3612 // corresponding argument.
3613 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3614 OpVT = TLI.getValueType(CS.getType());
3616 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3619 case InlineAsm::isInput:
3620 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3622 case InlineAsm::isClobber:
3627 // If this is an input or an indirect output, process the call argument.
3628 // BasicBlocks are labels, currently appearing only in asm's.
3629 if (OpInfo.CallOperandVal) {
3630 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3631 OpInfo.CallOperand =
3632 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(
3633 OpInfo.CallOperandVal)]);
3635 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3636 const Type *OpTy = OpInfo.CallOperandVal->getType();
3637 // If this is an indirect operand, the operand is a pointer to the
3639 if (OpInfo.isIndirect)
3640 OpTy = cast<PointerType>(OpTy)->getElementType();
3642 // If OpTy is not a first-class value, it may be a struct/union that we
3643 // can tile with integers.
3644 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3645 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3653 OpTy = IntegerType::get(BitSize);
3658 OpVT = TLI.getValueType(OpTy, true);
3662 OpInfo.ConstraintVT = OpVT;
3664 // Compute the constraint code and ConstraintType to use.
3665 OpInfo.ComputeConstraintToUse(TLI);
3667 // Keep track of whether we see an earlyclobber.
3668 SawEarlyClobber |= OpInfo.isEarlyClobber;
3670 // If we see a clobber of a register, it is an early clobber.
3671 if (!SawEarlyClobber &&
3672 OpInfo.Type == InlineAsm::isClobber &&
3673 OpInfo.ConstraintType == TargetLowering::C_Register) {
3674 // Note that we want to ignore things that we don't trick here, like
3675 // dirflag, fpsr, flags, etc.
3676 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3677 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3678 OpInfo.ConstraintVT);
3679 if (PhysReg.first || PhysReg.second) {
3680 // This is a register we know of.
3681 SawEarlyClobber = true;
3685 // If this is a memory input, and if the operand is not indirect, do what we
3686 // need to to provide an address for the memory input.
3687 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3688 !OpInfo.isIndirect) {
3689 assert(OpInfo.Type == InlineAsm::isInput &&
3690 "Can only indirectify direct input operands!");
3692 // Memory operands really want the address of the value. If we don't have
3693 // an indirect input, put it in the constpool if we can, otherwise spill
3694 // it to a stack slot.
3696 // If the operand is a float, integer, or vector constant, spill to a
3697 // constant pool entry to get its address.
3698 Value *OpVal = OpInfo.CallOperandVal;
3699 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3700 isa<ConstantVector>(OpVal)) {
3701 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3702 TLI.getPointerTy());
3704 // Otherwise, create a stack slot and emit a store to it before the
3706 const Type *Ty = OpVal->getType();
3707 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3708 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3709 MachineFunction &MF = DAG.getMachineFunction();
3710 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3711 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3712 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3713 OpInfo.CallOperand = StackSlot;
3716 // There is no longer a Value* corresponding to this operand.
3717 OpInfo.CallOperandVal = 0;
3718 // It is now an indirect operand.
3719 OpInfo.isIndirect = true;
3722 // If this constraint is for a specific register, allocate it before
3724 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3725 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3727 ConstraintInfos.clear();
3730 // Second pass - Loop over all of the operands, assigning virtual or physregs
3731 // to registerclass operands.
3732 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3733 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
3735 // C_Register operands have already been allocated, Other/Memory don't need
3737 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3738 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3741 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3742 std::vector<SDOperand> AsmNodeOperands;
3743 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3744 AsmNodeOperands.push_back(
3745 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3748 // Loop over all of the inputs, copying the operand values into the
3749 // appropriate registers and processing the output regs.
3750 RegsForValue RetValRegs;
3752 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3753 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3755 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3756 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
3758 switch (OpInfo.Type) {
3759 case InlineAsm::isOutput: {
3760 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3761 OpInfo.ConstraintType != TargetLowering::C_Register) {
3762 // Memory output, or 'other' output (e.g. 'X' constraint).
3763 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3765 // Add information to the INLINEASM node to know about this output.
3766 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3767 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3768 TLI.getPointerTy()));
3769 AsmNodeOperands.push_back(OpInfo.CallOperand);
3773 // Otherwise, this is a register or register class output.
3775 // Copy the output from the appropriate register. Find a register that
3777 if (OpInfo.AssignedRegs.Regs.empty()) {
3778 cerr << "Couldn't allocate output reg for contraint '"
3779 << OpInfo.ConstraintCode << "'!\n";
3783 if (!OpInfo.isIndirect) {
3784 // This is the result value of the call.
3785 assert(RetValRegs.Regs.empty() &&
3786 "Cannot have multiple output constraints yet!");
3787 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3788 RetValRegs = OpInfo.AssignedRegs;
3790 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3791 OpInfo.CallOperandVal));
3794 // Add information to the INLINEASM node to know that this register is
3796 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3800 case InlineAsm::isInput: {
3801 SDOperand InOperandVal = OpInfo.CallOperand;
3803 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3804 // If this is required to match an output register we have already set,
3805 // just use its register.
3806 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3808 // Scan until we find the definition we already emitted of this operand.
3809 // When we find it, create a RegsForValue operand.
3810 unsigned CurOp = 2; // The first operand.
3811 for (; OperandNo; --OperandNo) {
3812 // Advance to the next operand.
3814 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3815 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3816 (NumOps & 7) == 4 /*MEM*/) &&
3817 "Skipped past definitions?");
3818 CurOp += (NumOps>>3)+1;
3822 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3823 if ((NumOps & 7) == 2 /*REGDEF*/) {
3824 // Add NumOps>>3 registers to MatchedRegs.
3825 RegsForValue MatchedRegs;
3826 MatchedRegs.ValueVT = InOperandVal.getValueType();
3827 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3828 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3830 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3831 MatchedRegs.Regs.push_back(Reg);
3834 // Use the produced MatchedRegs object to
3835 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3836 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3839 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3840 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
3841 // Add information to the INLINEASM node to know about this input.
3842 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3843 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3844 TLI.getPointerTy()));
3845 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
3850 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3851 assert(!OpInfo.isIndirect &&
3852 "Don't know how to handle indirect other inputs yet!");
3854 std::vector<SDOperand> Ops;
3855 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3858 cerr << "Invalid operand for inline asm constraint '"
3859 << OpInfo.ConstraintCode << "'!\n";
3863 // Add information to the INLINEASM node to know about this input.
3864 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
3865 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3866 TLI.getPointerTy()));
3867 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
3869 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3870 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3871 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3872 "Memory operands expect pointer values");
3874 // Add information to the INLINEASM node to know about this input.
3875 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3876 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3877 TLI.getPointerTy()));
3878 AsmNodeOperands.push_back(InOperandVal);
3882 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3883 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3884 "Unknown constraint type!");
3885 assert(!OpInfo.isIndirect &&
3886 "Don't know how to handle indirect register inputs yet!");
3888 // Copy the input into the appropriate registers.
3889 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3890 "Couldn't allocate input reg!");
3892 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3894 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3898 case InlineAsm::isClobber: {
3899 // Add the clobbered value to the operand list, so that the register
3900 // allocator is aware that the physreg got clobbered.
3901 if (!OpInfo.AssignedRegs.Regs.empty())
3902 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3909 // Finish up input operands.
3910 AsmNodeOperands[0] = Chain;
3911 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3913 Chain = DAG.getNode(ISD::INLINEASM,
3914 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3915 &AsmNodeOperands[0], AsmNodeOperands.size());
3916 Flag = Chain.getValue(1);
3918 // If this asm returns a register value, copy the result from that register
3919 // and set it as the value of the call.
3920 if (!RetValRegs.Regs.empty()) {
3921 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3923 // If the result of the inline asm is a vector, it may have the wrong
3924 // width/num elts. Make sure to convert it to the right type with
3926 if (MVT::isVector(Val.getValueType())) {
3927 const VectorType *VTy = cast<VectorType>(CS.getType());
3928 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3930 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3933 setValue(CS.getInstruction(), Val);
3936 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3938 // Process indirect outputs, first output all of the flagged copies out of
3940 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3941 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3942 Value *Ptr = IndirectStoresToEmit[i].second;
3943 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3944 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3947 // Emit the non-flagged stores from the physregs.
3948 SmallVector<SDOperand, 8> OutChains;
3949 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3950 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3951 getValue(StoresToEmit[i].second),
3952 StoresToEmit[i].second, 0));
3953 if (!OutChains.empty())
3954 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3955 &OutChains[0], OutChains.size());
3960 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3961 SDOperand Src = getValue(I.getOperand(0));
3963 MVT::ValueType IntPtr = TLI.getPointerTy();
3965 if (IntPtr < Src.getValueType())
3966 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3967 else if (IntPtr > Src.getValueType())
3968 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
3970 // Scale the source by the type size.
3971 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
3972 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3973 Src, DAG.getIntPtrConstant(ElementSize));
3975 TargetLowering::ArgListTy Args;
3976 TargetLowering::ArgListEntry Entry;
3978 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3979 Args.push_back(Entry);
3981 std::pair<SDOperand,SDOperand> Result =
3982 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
3983 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
3984 setValue(&I, Result.first); // Pointers always fit in registers
3985 DAG.setRoot(Result.second);
3988 void SelectionDAGLowering::visitFree(FreeInst &I) {
3989 TargetLowering::ArgListTy Args;
3990 TargetLowering::ArgListEntry Entry;
3991 Entry.Node = getValue(I.getOperand(0));
3992 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3993 Args.push_back(Entry);
3994 MVT::ValueType IntPtr = TLI.getPointerTy();
3995 std::pair<SDOperand,SDOperand> Result =
3996 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
3997 CallingConv::C, true,
3998 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3999 DAG.setRoot(Result.second);
4002 // EmitInstrWithCustomInserter - This method should be implemented by targets
4003 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4004 // instructions are special in various ways, which require special support to
4005 // insert. The specified MachineInstr is created but not inserted into any
4006 // basic blocks, and the scheduler passes ownership of it to this method.
4007 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4008 MachineBasicBlock *MBB) {
4009 cerr << "If a target marks an instruction with "
4010 << "'usesCustomDAGSchedInserter', it must implement "
4011 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4016 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4017 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4018 getValue(I.getOperand(1)),
4019 DAG.getSrcValue(I.getOperand(1))));
4022 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4023 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4024 getValue(I.getOperand(0)),
4025 DAG.getSrcValue(I.getOperand(0)));
4027 DAG.setRoot(V.getValue(1));
4030 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4031 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4032 getValue(I.getOperand(1)),
4033 DAG.getSrcValue(I.getOperand(1))));
4036 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4037 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4038 getValue(I.getOperand(1)),
4039 getValue(I.getOperand(2)),
4040 DAG.getSrcValue(I.getOperand(1)),
4041 DAG.getSrcValue(I.getOperand(2))));
4044 /// TargetLowering::LowerArguments - This is the default LowerArguments
4045 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4046 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4047 /// integrated into SDISel.
4048 std::vector<SDOperand>
4049 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
4050 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4051 std::vector<SDOperand> Ops;
4052 Ops.push_back(DAG.getRoot());
4053 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4054 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4056 // Add one result value for each formal argument.
4057 std::vector<MVT::ValueType> RetVals;
4059 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4061 MVT::ValueType VT = getValueType(I->getType());
4062 ISD::ParamFlags::ParamFlagsTy Flags = ISD::ParamFlags::NoFlagSet;
4063 unsigned OriginalAlignment =
4064 getTargetData()->getABITypeAlignment(I->getType());
4066 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
4067 // that is zero extended!
4068 if (F.paramHasAttr(j, ParamAttr::ZExt))
4069 Flags &= ~(ISD::ParamFlags::SExt);
4070 if (F.paramHasAttr(j, ParamAttr::SExt))
4071 Flags |= ISD::ParamFlags::SExt;
4072 if (F.paramHasAttr(j, ParamAttr::InReg))
4073 Flags |= ISD::ParamFlags::InReg;
4074 if (F.paramHasAttr(j, ParamAttr::StructRet))
4075 Flags |= ISD::ParamFlags::StructReturn;
4076 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4077 Flags |= ISD::ParamFlags::ByVal;
4078 const PointerType *Ty = cast<PointerType>(I->getType());
4079 const Type *ElementTy = Ty->getElementType();
4080 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy));
4081 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4082 // For ByVal, alignment should be passed from FE. BE will guess if
4083 // this info is not there but there are cases it cannot get right.
4084 if (F.getParamAlignment(j))
4085 FrameAlign = Log2_32(F.getParamAlignment(j));
4086 Flags |= ((ISD::ParamFlags::ParamFlagsTy)FrameAlign
4087 << ISD::ParamFlags::ByValAlignOffs);
4088 Flags |= ((ISD::ParamFlags::ParamFlagsTy)FrameSize
4089 << ISD::ParamFlags::ByValSizeOffs);
4091 if (F.paramHasAttr(j, ParamAttr::Nest))
4092 Flags |= ISD::ParamFlags::Nest;
4093 Flags |= ((ISD::ParamFlags::ParamFlagsTy)OriginalAlignment
4094 << ISD::ParamFlags::OrigAlignmentOffs);
4096 MVT::ValueType RegisterVT = getRegisterType(VT);
4097 unsigned NumRegs = getNumRegisters(VT);
4098 for (unsigned i = 0; i != NumRegs; ++i) {
4099 RetVals.push_back(RegisterVT);
4100 // if it isn't first piece, alignment must be 1
4102 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
4103 (ISD::ParamFlags::One << ISD::ParamFlags::OrigAlignmentOffs);
4104 Ops.push_back(DAG.getConstant(Flags, MVT::i64));
4108 RetVals.push_back(MVT::Other);
4111 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4112 DAG.getVTList(&RetVals[0], RetVals.size()),
4113 &Ops[0], Ops.size()).Val;
4115 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4116 // allows exposing the loads that may be part of the argument access to the
4117 // first DAGCombiner pass.
4118 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
4120 // The number of results should match up, except that the lowered one may have
4121 // an extra flag result.
4122 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4123 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4124 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4125 && "Lowering produced unexpected number of results!");
4126 Result = TmpRes.Val;
4128 unsigned NumArgRegs = Result->getNumValues() - 1;
4129 DAG.setRoot(SDOperand(Result, NumArgRegs));
4131 // Set up the return result vector.
4135 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4137 MVT::ValueType VT = getValueType(I->getType());
4138 MVT::ValueType PartVT = getRegisterType(VT);
4140 unsigned NumParts = getNumRegisters(VT);
4141 SmallVector<SDOperand, 4> Parts(NumParts);
4142 for (unsigned j = 0; j != NumParts; ++j)
4143 Parts[j] = SDOperand(Result, i++);
4145 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4146 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4147 AssertOp = ISD::AssertSext;
4148 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4149 AssertOp = ISD::AssertZext;
4151 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4154 assert(i == NumArgRegs && "Argument register count mismatch!");
4159 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4160 /// implementation, which just inserts an ISD::CALL node, which is later custom
4161 /// lowered by the target to something concrete. FIXME: When all targets are
4162 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4163 std::pair<SDOperand, SDOperand>
4164 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4165 bool RetSExt, bool RetZExt, bool isVarArg,
4166 unsigned CallingConv, bool isTailCall,
4168 ArgListTy &Args, SelectionDAG &DAG) {
4169 SmallVector<SDOperand, 32> Ops;
4170 Ops.push_back(Chain); // Op#0 - Chain
4171 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4172 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4173 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4174 Ops.push_back(Callee);
4176 // Handle all of the outgoing arguments.
4177 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4178 MVT::ValueType VT = getValueType(Args[i].Ty);
4179 SDOperand Op = Args[i].Node;
4180 ISD::ParamFlags::ParamFlagsTy Flags = ISD::ParamFlags::NoFlagSet;
4181 unsigned OriginalAlignment =
4182 getTargetData()->getABITypeAlignment(Args[i].Ty);
4185 Flags |= ISD::ParamFlags::SExt;
4187 Flags |= ISD::ParamFlags::ZExt;
4188 if (Args[i].isInReg)
4189 Flags |= ISD::ParamFlags::InReg;
4191 Flags |= ISD::ParamFlags::StructReturn;
4192 if (Args[i].isByVal) {
4193 Flags |= ISD::ParamFlags::ByVal;
4194 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4195 const Type *ElementTy = Ty->getElementType();
4196 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy));
4197 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4198 // For ByVal, alignment should come from FE. BE will guess if this
4199 // info is not there but there are cases it cannot get right.
4200 if (Args[i].Alignment)
4201 FrameAlign = Log2_32(Args[i].Alignment);
4202 Flags |= ((ISD::ParamFlags::ParamFlagsTy)FrameAlign
4203 << ISD::ParamFlags::ByValAlignOffs);
4204 Flags |= ((ISD::ParamFlags::ParamFlagsTy)FrameSize
4205 << ISD::ParamFlags::ByValSizeOffs);
4208 Flags |= ISD::ParamFlags::Nest;
4209 Flags |= ((ISD::ParamFlags::ParamFlagsTy)OriginalAlignment)
4210 << ISD::ParamFlags::OrigAlignmentOffs;
4212 MVT::ValueType PartVT = getRegisterType(VT);
4213 unsigned NumParts = getNumRegisters(VT);
4214 SmallVector<SDOperand, 4> Parts(NumParts);
4215 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4218 ExtendKind = ISD::SIGN_EXTEND;
4219 else if (Args[i].isZExt)
4220 ExtendKind = ISD::ZERO_EXTEND;
4222 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4224 for (unsigned i = 0; i != NumParts; ++i) {
4225 // if it isn't first piece, alignment must be 1
4226 ISD::ParamFlags::ParamFlagsTy MyFlags = Flags;
4228 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4229 (ISD::ParamFlags::One << ISD::ParamFlags::OrigAlignmentOffs);
4231 Ops.push_back(Parts[i]);
4232 Ops.push_back(DAG.getConstant(MyFlags, MVT::i64));
4236 // Figure out the result value types.
4237 MVT::ValueType VT = getValueType(RetTy);
4238 MVT::ValueType RegisterVT = getRegisterType(VT);
4239 unsigned NumRegs = getNumRegisters(VT);
4240 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4241 for (unsigned i = 0; i != NumRegs; ++i)
4242 RetTys[i] = RegisterVT;
4244 RetTys.push_back(MVT::Other); // Always has a chain.
4246 // Create the CALL node.
4247 SDOperand Res = DAG.getNode(ISD::CALL,
4248 DAG.getVTList(&RetTys[0], NumRegs + 1),
4249 &Ops[0], Ops.size());
4250 Chain = Res.getValue(NumRegs);
4252 // Gather up the call result into a single value.
4253 if (RetTy != Type::VoidTy) {
4254 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4257 AssertOp = ISD::AssertSext;
4259 AssertOp = ISD::AssertZext;
4261 SmallVector<SDOperand, 4> Results(NumRegs);
4262 for (unsigned i = 0; i != NumRegs; ++i)
4263 Results[i] = Res.getValue(i);
4264 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4268 return std::make_pair(Res, Chain);
4271 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4272 assert(0 && "LowerOperation not implemented for this target!");
4277 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4278 SelectionDAG &DAG) {
4279 assert(0 && "CustomPromoteOperation not implemented for this target!");
4284 /// getMemsetValue - Vectorized representation of the memset value
4286 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4287 SelectionDAG &DAG) {
4288 MVT::ValueType CurVT = VT;
4289 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4290 uint64_t Val = C->getValue() & 255;
4292 while (CurVT != MVT::i8) {
4293 Val = (Val << Shift) | Val;
4295 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4297 return DAG.getConstant(Val, VT);
4299 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4301 while (CurVT != MVT::i8) {
4303 DAG.getNode(ISD::OR, VT,
4304 DAG.getNode(ISD::SHL, VT, Value,
4305 DAG.getConstant(Shift, MVT::i8)), Value);
4307 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4314 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4315 /// used when a memcpy is turned into a memset when the source is a constant
4317 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4318 SelectionDAG &DAG, TargetLowering &TLI,
4319 std::string &Str, unsigned Offset) {
4321 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4322 if (TLI.isLittleEndian())
4323 Offset = Offset + MSB - 1;
4324 for (unsigned i = 0; i != MSB; ++i) {
4325 Val = (Val << 8) | (unsigned char)Str[Offset];
4326 Offset += TLI.isLittleEndian() ? -1 : 1;
4328 return DAG.getConstant(Val, VT);
4331 /// getMemBasePlusOffset - Returns base and offset node for the
4332 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4333 SelectionDAG &DAG, TargetLowering &TLI) {
4334 MVT::ValueType VT = Base.getValueType();
4335 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4338 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4339 /// to replace the memset / memcpy is below the threshold. It also returns the
4340 /// types of the sequence of memory ops to perform memset / memcpy.
4341 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4342 unsigned Limit, uint64_t Size,
4343 unsigned Align, TargetLowering &TLI) {
4346 if (TLI.allowsUnalignedMemoryAccesses()) {
4349 switch (Align & 7) {
4365 MVT::ValueType LVT = MVT::i64;
4366 while (!TLI.isTypeLegal(LVT))
4367 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4368 assert(MVT::isInteger(LVT));
4373 unsigned NumMemOps = 0;
4375 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4376 while (VTSize > Size) {
4377 VT = (MVT::ValueType)((unsigned)VT - 1);
4380 assert(MVT::isInteger(VT));
4382 if (++NumMemOps > Limit)
4384 MemOps.push_back(VT);
4391 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4392 SDOperand Op1 = getValue(I.getOperand(1));
4393 SDOperand Op2 = getValue(I.getOperand(2));
4394 SDOperand Op3 = getValue(I.getOperand(3));
4395 SDOperand Op4 = getValue(I.getOperand(4));
4396 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4397 if (Align == 0) Align = 1;
4399 // If the source and destination are known to not be aliases, we can
4400 // lower memmove as memcpy.
4401 if (Op == ISD::MEMMOVE) {
4402 uint64_t Size = -1ULL;
4403 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4404 Size = C->getValue();
4405 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4406 AliasAnalysis::NoAlias)
4410 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4411 std::vector<MVT::ValueType> MemOps;
4413 // Expand memset / memcpy to a series of load / store ops
4414 // if the size operand falls below a certain threshold.
4415 SmallVector<SDOperand, 8> OutChains;
4417 default: break; // Do nothing for now.
4419 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4420 Size->getValue(), Align, TLI)) {
4421 unsigned NumMemOps = MemOps.size();
4422 unsigned Offset = 0;
4423 for (unsigned i = 0; i < NumMemOps; i++) {
4424 MVT::ValueType VT = MemOps[i];
4425 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4426 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4427 SDOperand Store = DAG.getStore(getRoot(), Value,
4428 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4429 I.getOperand(1), Offset);
4430 OutChains.push_back(Store);
4437 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4438 Size->getValue(), Align, TLI)) {
4439 unsigned NumMemOps = MemOps.size();
4440 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4441 GlobalAddressSDNode *G = NULL;
4443 bool CopyFromStr = false;
4445 if (Op2.getOpcode() == ISD::GlobalAddress)
4446 G = cast<GlobalAddressSDNode>(Op2);
4447 else if (Op2.getOpcode() == ISD::ADD &&
4448 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4449 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4450 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4451 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4454 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4455 if (GV && GV->isConstant()) {
4456 Str = GV->getStringValue(false);
4464 for (unsigned i = 0; i < NumMemOps; i++) {
4465 MVT::ValueType VT = MemOps[i];
4466 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4467 SDOperand Value, Chain, Store;
4470 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4473 DAG.getStore(Chain, Value,
4474 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4475 I.getOperand(1), DstOff);
4477 Value = DAG.getLoad(VT, getRoot(),
4478 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4479 I.getOperand(2), SrcOff, false, Align);
4480 Chain = Value.getValue(1);
4482 DAG.getStore(Chain, Value,
4483 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4484 I.getOperand(1), DstOff, false, Align);
4486 OutChains.push_back(Store);
4495 if (!OutChains.empty()) {
4496 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4497 &OutChains[0], OutChains.size()));
4502 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4506 assert(0 && "Unknown Op");
4508 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4511 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4514 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4520 //===----------------------------------------------------------------------===//
4521 // SelectionDAGISel code
4522 //===----------------------------------------------------------------------===//
4524 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4525 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4528 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4529 AU.addRequired<AliasAnalysis>();
4530 AU.addRequired<CollectorModuleMetadata>();
4531 AU.setPreservesAll();
4536 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4537 // Get alias analysis for load/store combining.
4538 AA = &getAnalysis<AliasAnalysis>();
4540 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4541 if (MF.getFunction()->hasCollector())
4542 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4545 RegInfo = &MF.getRegInfo();
4546 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4548 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4550 if (ExceptionHandling)
4551 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4552 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4553 // Mark landing pad.
4554 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4556 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4557 SelectBasicBlock(I, MF, FuncInfo);
4559 // Add function live-ins to entry block live-in set.
4560 BasicBlock *EntryBB = &Fn.getEntryBlock();
4561 BB = FuncInfo.MBBMap[EntryBB];
4562 if (!RegInfo->livein_empty())
4563 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4564 E = RegInfo->livein_end(); I != E; ++I)
4565 BB->addLiveIn(I->first);
4568 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4569 "Not all catch info was assigned to a landing pad!");
4575 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4577 SDOperand Op = getValue(V);
4578 assert((Op.getOpcode() != ISD::CopyFromReg ||
4579 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4580 "Copy from a reg to the same reg!");
4582 MVT::ValueType SrcVT = Op.getValueType();
4583 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4584 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4585 SmallVector<SDOperand, 8> Regs(NumRegs);
4586 SmallVector<SDOperand, 8> Chains(NumRegs);
4588 // Copy the value by legal parts into sequential virtual registers.
4589 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4590 for (unsigned i = 0; i != NumRegs; ++i)
4591 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4592 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4595 void SelectionDAGISel::
4596 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4597 std::vector<SDOperand> &UnorderedChains) {
4598 // If this is the entry block, emit arguments.
4599 Function &F = *LLVMBB->getParent();
4600 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4601 SDOperand OldRoot = SDL.DAG.getRoot();
4602 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4605 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4607 if (!AI->use_empty()) {
4608 SDL.setValue(AI, Args[a]);
4610 // If this argument is live outside of the entry block, insert a copy from
4611 // whereever we got it to the vreg that other BB's will reference it as.
4612 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4613 if (VMI != FuncInfo.ValueMap.end()) {
4614 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4615 UnorderedChains.push_back(Copy);
4619 // Finally, if the target has anything special to do, allow it to do so.
4620 // FIXME: this should insert code into the DAG!
4621 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4624 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4625 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4626 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4627 if (isSelector(I)) {
4628 // Apply the catch info to DestBB.
4629 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4631 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4632 FLI.CatchInfoFound.insert(I);
4637 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4638 /// DAG and fixes their tailcall attribute operand.
4639 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4640 TargetLowering& TLI) {
4641 SDNode * Ret = NULL;
4642 SDOperand Terminator = DAG.getRoot();
4645 if (Terminator.getOpcode() == ISD::RET) {
4646 Ret = Terminator.Val;
4649 // Fix tail call attribute of CALL nodes.
4650 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4651 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4652 if (BI->getOpcode() == ISD::CALL) {
4653 SDOperand OpRet(Ret, 0);
4654 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4655 bool isMarkedTailCall =
4656 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4657 // If CALL node has tail call attribute set to true and the call is not
4658 // eligible (no RET or the target rejects) the attribute is fixed to
4659 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4660 // must correctly identify tail call optimizable calls.
4661 if (isMarkedTailCall &&
4663 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4664 SmallVector<SDOperand, 32> Ops;
4666 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4667 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4671 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4673 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4679 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4680 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4681 FunctionLoweringInfo &FuncInfo) {
4682 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
4684 std::vector<SDOperand> UnorderedChains;
4686 // Lower any arguments needed in this block if this is the entry block.
4687 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4688 LowerArguments(LLVMBB, SDL, UnorderedChains);
4690 BB = FuncInfo.MBBMap[LLVMBB];
4691 SDL.setCurrentBasicBlock(BB);
4693 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4695 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4696 // Add a label to mark the beginning of the landing pad. Deletion of the
4697 // landing pad can thus be detected via the MachineModuleInfo.
4698 unsigned LabelID = MMI->addLandingPad(BB);
4699 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4700 DAG.getConstant(LabelID, MVT::i32),
4701 DAG.getConstant(1, MVT::i32)));
4703 // Mark exception register as live in.
4704 unsigned Reg = TLI.getExceptionAddressRegister();
4705 if (Reg) BB->addLiveIn(Reg);
4707 // Mark exception selector register as live in.
4708 Reg = TLI.getExceptionSelectorRegister();
4709 if (Reg) BB->addLiveIn(Reg);
4711 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4712 // function and list of typeids logically belong to the invoke (or, if you
4713 // like, the basic block containing the invoke), and need to be associated
4714 // with it in the dwarf exception handling tables. Currently however the
4715 // information is provided by an intrinsic (eh.selector) that can be moved
4716 // to unexpected places by the optimizers: if the unwind edge is critical,
4717 // then breaking it can result in the intrinsics being in the successor of
4718 // the landing pad, not the landing pad itself. This results in exceptions
4719 // not being caught because no typeids are associated with the invoke.
4720 // This may not be the only way things can go wrong, but it is the only way
4721 // we try to work around for the moment.
4722 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4724 if (Br && Br->isUnconditional()) { // Critical edge?
4725 BasicBlock::iterator I, E;
4726 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4731 // No catch info found - try to extract some from the successor.
4732 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4736 // Lower all of the non-terminator instructions.
4737 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4741 // Ensure that all instructions which are used outside of their defining
4742 // blocks are available as virtual registers. Invoke is handled elsewhere.
4743 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4744 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4745 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4746 if (VMI != FuncInfo.ValueMap.end())
4747 UnorderedChains.push_back(
4748 SDL.CopyValueToVirtualRegister(I, VMI->second));
4751 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4752 // ensure constants are generated when needed. Remember the virtual registers
4753 // that need to be added to the Machine PHI nodes as input. We cannot just
4754 // directly add them, because expansion might result in multiple MBB's for one
4755 // BB. As such, the start of the BB might correspond to a different MBB than
4758 TerminatorInst *TI = LLVMBB->getTerminator();
4760 // Emit constants only once even if used by multiple PHI nodes.
4761 std::map<Constant*, unsigned> ConstantsOut;
4763 // Vector bool would be better, but vector<bool> is really slow.
4764 std::vector<unsigned char> SuccsHandled;
4765 if (TI->getNumSuccessors())
4766 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4768 // Check successor nodes' PHI nodes that expect a constant to be available
4770 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4771 BasicBlock *SuccBB = TI->getSuccessor(succ);
4772 if (!isa<PHINode>(SuccBB->begin())) continue;
4773 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4775 // If this terminator has multiple identical successors (common for
4776 // switches), only handle each succ once.
4777 unsigned SuccMBBNo = SuccMBB->getNumber();
4778 if (SuccsHandled[SuccMBBNo]) continue;
4779 SuccsHandled[SuccMBBNo] = true;
4781 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4784 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4785 // nodes and Machine PHI nodes, but the incoming operands have not been
4787 for (BasicBlock::iterator I = SuccBB->begin();
4788 (PN = dyn_cast<PHINode>(I)); ++I) {
4789 // Ignore dead phi's.
4790 if (PN->use_empty()) continue;
4793 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4795 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4796 unsigned &RegOut = ConstantsOut[C];
4798 RegOut = FuncInfo.CreateRegForValue(C);
4799 UnorderedChains.push_back(
4800 SDL.CopyValueToVirtualRegister(C, RegOut));
4804 Reg = FuncInfo.ValueMap[PHIOp];
4806 assert(isa<AllocaInst>(PHIOp) &&
4807 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4808 "Didn't codegen value into a register!??");
4809 Reg = FuncInfo.CreateRegForValue(PHIOp);
4810 UnorderedChains.push_back(
4811 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4815 // Remember that this register needs to added to the machine PHI node as
4816 // the input for this MBB.
4817 MVT::ValueType VT = TLI.getValueType(PN->getType());
4818 unsigned NumRegisters = TLI.getNumRegisters(VT);
4819 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4820 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4823 ConstantsOut.clear();
4825 // Turn all of the unordered chains into one factored node.
4826 if (!UnorderedChains.empty()) {
4827 SDOperand Root = SDL.getRoot();
4828 if (Root.getOpcode() != ISD::EntryToken) {
4829 unsigned i = 0, e = UnorderedChains.size();
4830 for (; i != e; ++i) {
4831 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4832 if (UnorderedChains[i].Val->getOperand(0) == Root)
4833 break; // Don't add the root if we already indirectly depend on it.
4837 UnorderedChains.push_back(Root);
4839 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4840 &UnorderedChains[0], UnorderedChains.size()));
4843 // Lower the terminator after the copies are emitted.
4844 SDL.visit(*LLVMBB->getTerminator());
4846 // Copy over any CaseBlock records that may now exist due to SwitchInst
4847 // lowering, as well as any jump table information.
4848 SwitchCases.clear();
4849 SwitchCases = SDL.SwitchCases;
4851 JTCases = SDL.JTCases;
4852 BitTestCases.clear();
4853 BitTestCases = SDL.BitTestCases;
4855 // Make sure the root of the DAG is up-to-date.
4856 DAG.setRoot(SDL.getRoot());
4858 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4859 // with correct tailcall attribute so that the target can rely on the tailcall
4860 // attribute indicating whether the call is really eligible for tail call
4862 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4865 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4866 DOUT << "Lowered selection DAG:\n";
4869 // Run the DAG combiner in pre-legalize mode.
4870 DAG.Combine(false, *AA);
4872 DOUT << "Optimized lowered selection DAG:\n";
4875 // Second step, hack on the DAG until it only uses operations and types that
4876 // the target supports.
4877 #if 0 // Enable this some day.
4878 DAG.LegalizeTypes();
4879 // Someday even later, enable a dag combine pass here.
4883 DOUT << "Legalized selection DAG:\n";
4886 // Run the DAG combiner in post-legalize mode.
4887 DAG.Combine(true, *AA);
4889 DOUT << "Optimized legalized selection DAG:\n";
4892 if (ViewISelDAGs) DAG.viewGraph();
4894 // Third, instruction select all of the operations to machine code, adding the
4895 // code to the MachineBasicBlock.
4896 InstructionSelectBasicBlock(DAG);
4898 DOUT << "Selected machine code:\n";
4902 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4903 FunctionLoweringInfo &FuncInfo) {
4904 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4906 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4909 // First step, lower LLVM code to some DAG. This DAG may use operations and
4910 // types that are not supported by the target.
4911 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4913 // Second step, emit the lowered DAG as machine code.
4914 CodeGenAndEmitDAG(DAG);
4917 DOUT << "Total amount of phi nodes to update: "
4918 << PHINodesToUpdate.size() << "\n";
4919 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4920 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4921 << ", " << PHINodesToUpdate[i].second << ")\n";);
4923 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4924 // PHI nodes in successors.
4925 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4926 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4927 MachineInstr *PHI = PHINodesToUpdate[i].first;
4928 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4929 "This is not a machine PHI node that we are updating!");
4930 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4932 PHI->addOperand(MachineOperand::CreateMBB(BB));
4937 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4938 // Lower header first, if it wasn't already lowered
4939 if (!BitTestCases[i].Emitted) {
4940 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4942 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4943 // Set the current basic block to the mbb we wish to insert the code into
4944 BB = BitTestCases[i].Parent;
4945 HSDL.setCurrentBasicBlock(BB);
4947 HSDL.visitBitTestHeader(BitTestCases[i]);
4948 HSDAG.setRoot(HSDL.getRoot());
4949 CodeGenAndEmitDAG(HSDAG);
4952 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4953 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4955 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
4956 // Set the current basic block to the mbb we wish to insert the code into
4957 BB = BitTestCases[i].Cases[j].ThisBB;
4958 BSDL.setCurrentBasicBlock(BB);
4961 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4962 BitTestCases[i].Reg,
4963 BitTestCases[i].Cases[j]);
4965 BSDL.visitBitTestCase(BitTestCases[i].Default,
4966 BitTestCases[i].Reg,
4967 BitTestCases[i].Cases[j]);
4970 BSDAG.setRoot(BSDL.getRoot());
4971 CodeGenAndEmitDAG(BSDAG);
4975 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4976 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4977 MachineBasicBlock *PHIBB = PHI->getParent();
4978 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4979 "This is not a machine PHI node that we are updating!");
4980 // This is "default" BB. We have two jumps to it. From "header" BB and
4981 // from last "case" BB.
4982 if (PHIBB == BitTestCases[i].Default) {
4983 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4985 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
4986 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4988 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
4991 // One of "cases" BB.
4992 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4993 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4994 if (cBB->succ_end() !=
4995 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4996 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4998 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5004 // If the JumpTable record is filled in, then we need to emit a jump table.
5005 // Updating the PHI nodes is tricky in this case, since we need to determine
5006 // whether the PHI is a successor of the range check MBB or the jump table MBB
5007 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5008 // Lower header first, if it wasn't already lowered
5009 if (!JTCases[i].first.Emitted) {
5010 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5012 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5013 // Set the current basic block to the mbb we wish to insert the code into
5014 BB = JTCases[i].first.HeaderBB;
5015 HSDL.setCurrentBasicBlock(BB);
5017 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5018 HSDAG.setRoot(HSDL.getRoot());
5019 CodeGenAndEmitDAG(HSDAG);
5022 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5024 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5025 // Set the current basic block to the mbb we wish to insert the code into
5026 BB = JTCases[i].second.MBB;
5027 JSDL.setCurrentBasicBlock(BB);
5029 JSDL.visitJumpTable(JTCases[i].second);
5030 JSDAG.setRoot(JSDL.getRoot());
5031 CodeGenAndEmitDAG(JSDAG);
5034 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5035 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5036 MachineBasicBlock *PHIBB = PHI->getParent();
5037 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5038 "This is not a machine PHI node that we are updating!");
5039 // "default" BB. We can go there only from header BB.
5040 if (PHIBB == JTCases[i].second.Default) {
5041 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5043 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5045 // JT BB. Just iterate over successors here
5046 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5047 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5049 PHI->addOperand(MachineOperand::CreateMBB(BB));
5054 // If the switch block involved a branch to one of the actual successors, we
5055 // need to update PHI nodes in that block.
5056 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5057 MachineInstr *PHI = PHINodesToUpdate[i].first;
5058 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5059 "This is not a machine PHI node that we are updating!");
5060 if (BB->isSuccessor(PHI->getParent())) {
5061 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5063 PHI->addOperand(MachineOperand::CreateMBB(BB));
5067 // If we generated any switch lowering information, build and codegen any
5068 // additional DAGs necessary.
5069 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5070 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5072 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5074 // Set the current basic block to the mbb we wish to insert the code into
5075 BB = SwitchCases[i].ThisBB;
5076 SDL.setCurrentBasicBlock(BB);
5079 SDL.visitSwitchCase(SwitchCases[i]);
5080 SDAG.setRoot(SDL.getRoot());
5081 CodeGenAndEmitDAG(SDAG);
5083 // Handle any PHI nodes in successors of this chunk, as if we were coming
5084 // from the original BB before switch expansion. Note that PHI nodes can
5085 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5086 // handle them the right number of times.
5087 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5088 for (MachineBasicBlock::iterator Phi = BB->begin();
5089 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5090 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5091 for (unsigned pn = 0; ; ++pn) {
5092 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5093 if (PHINodesToUpdate[pn].first == Phi) {
5094 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5096 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5102 // Don't process RHS if same block as LHS.
5103 if (BB == SwitchCases[i].FalseBB)
5104 SwitchCases[i].FalseBB = 0;
5106 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5107 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5108 SwitchCases[i].FalseBB = 0;
5110 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5115 //===----------------------------------------------------------------------===//
5116 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
5117 /// target node in the graph.
5118 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
5119 if (ViewSchedDAGs) DAG.viewGraph();
5121 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5125 RegisterScheduler::setDefault(Ctor);
5128 ScheduleDAG *SL = Ctor(this, &DAG, BB);
5131 if (ViewSUnitDAGs) SL->viewGraph();
5137 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5138 return new HazardRecognizer();
5141 //===----------------------------------------------------------------------===//
5142 // Helper functions used by the generated instruction selector.
5143 //===----------------------------------------------------------------------===//
5144 // Calls to these methods are generated by tblgen.
5146 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5147 /// the dag combiner simplified the 255, we still want to match. RHS is the
5148 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5149 /// specified in the .td file (e.g. 255).
5150 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5151 int64_t DesiredMaskS) const {
5152 const APInt &ActualMask = RHS->getAPIntValue();
5153 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5155 // If the actual mask exactly matches, success!
5156 if (ActualMask == DesiredMask)
5159 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5160 if (ActualMask.intersects(~DesiredMask))
5163 // Otherwise, the DAG Combiner may have proven that the value coming in is
5164 // either already zero or is not demanded. Check for known zero input bits.
5165 APInt NeededMask = DesiredMask & ~ActualMask;
5166 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5169 // TODO: check to see if missing bits are just not demanded.
5171 // Otherwise, this pattern doesn't match.
5175 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5176 /// the dag combiner simplified the 255, we still want to match. RHS is the
5177 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5178 /// specified in the .td file (e.g. 255).
5179 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5180 int64_t DesiredMaskS) const {
5181 const APInt &ActualMask = RHS->getAPIntValue();
5182 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5184 // If the actual mask exactly matches, success!
5185 if (ActualMask == DesiredMask)
5188 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5189 if (ActualMask.intersects(~DesiredMask))
5192 // Otherwise, the DAG Combiner may have proven that the value coming in is
5193 // either already zero or is not demanded. Check for known zero input bits.
5194 APInt NeededMask = DesiredMask & ~ActualMask;
5196 APInt KnownZero, KnownOne;
5197 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5199 // If all the missing bits in the or are already known to be set, match!
5200 if ((NeededMask & KnownOne) == NeededMask)
5203 // TODO: check to see if missing bits are just not demanded.
5205 // Otherwise, this pattern doesn't match.
5210 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5211 /// by tblgen. Others should not call it.
5212 void SelectionDAGISel::
5213 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5214 std::vector<SDOperand> InOps;
5215 std::swap(InOps, Ops);
5217 Ops.push_back(InOps[0]); // input chain.
5218 Ops.push_back(InOps[1]); // input asm string.
5220 unsigned i = 2, e = InOps.size();
5221 if (InOps[e-1].getValueType() == MVT::Flag)
5222 --e; // Don't process a flag operand if it is here.
5225 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5226 if ((Flags & 7) != 4 /*MEM*/) {
5227 // Just skip over this operand, copying the operands verbatim.
5228 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5229 i += (Flags >> 3) + 1;
5231 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5232 // Otherwise, this is a memory operand. Ask the target to select it.
5233 std::vector<SDOperand> SelOps;
5234 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5235 cerr << "Could not match memory address. Inline asm failure!\n";
5239 // Add this to the output node.
5240 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5241 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5243 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5248 // Add the flag input back if present.
5249 if (e != InOps.size())
5250 Ops.push_back(InOps.back());
5253 char SelectionDAGISel::ID = 0;