1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/ADT/PostOrderIterator.h"
53 #include "llvm/ADT/Statistic.h"
57 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
58 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
59 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
60 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
61 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
64 STATISTIC(NumBBWithOutOfOrderLineInfo,
65 "Number of blocks with out of order line number info");
66 STATISTIC(NumMBBWithOutOfOrderLineInfo,
67 "Number of machine blocks with out of order line number info");
71 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
72 cl::desc("Enable verbose messages in the \"fast\" "
73 "instruction selector"));
75 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
76 cl::desc("Enable abort calls when \"fast\" instruction fails"));
80 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the first "
84 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
85 cl::desc("Pop up a window to show dags before legalize types"));
87 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
88 cl::desc("Pop up a window to show dags before legalize"));
90 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
91 cl::desc("Pop up a window to show dags before the second "
94 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
95 cl::desc("Pop up a window to show dags before the post legalize types"
96 " dag combine pass"));
98 ViewISelDAGs("view-isel-dags", cl::Hidden,
99 cl::desc("Pop up a window to show isel dags as they are selected"));
101 ViewSchedDAGs("view-sched-dags", cl::Hidden,
102 cl::desc("Pop up a window to show sched dags as they are processed"));
104 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
105 cl::desc("Pop up a window to show SUnit dags after they are processed"));
107 static const bool ViewDAGCombine1 = false,
108 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
109 ViewDAGCombine2 = false,
110 ViewDAGCombineLT = false,
111 ViewISelDAGs = false, ViewSchedDAGs = false,
112 ViewSUnitDAGs = false;
115 //===---------------------------------------------------------------------===//
117 /// RegisterScheduler class - Track the registration of instruction schedulers.
119 //===---------------------------------------------------------------------===//
120 MachinePassRegistry RegisterScheduler::Registry;
122 //===---------------------------------------------------------------------===//
124 /// ISHeuristic command line option for instruction schedulers.
126 //===---------------------------------------------------------------------===//
127 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
128 RegisterPassParser<RegisterScheduler> >
129 ISHeuristic("pre-RA-sched",
130 cl::init(&createDefaultScheduler),
131 cl::desc("Instruction schedulers available (before register"
134 static RegisterScheduler
135 defaultListDAGScheduler("default", "Best scheduler for the target",
136 createDefaultScheduler);
139 //===--------------------------------------------------------------------===//
140 /// createDefaultScheduler - This creates an instruction scheduler appropriate
142 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
143 CodeGenOpt::Level OptLevel) {
144 const TargetLowering &TLI = IS->getTargetLowering();
146 if (OptLevel == CodeGenOpt::None)
147 return createSourceListDAGScheduler(IS, OptLevel);
148 if (TLI.getSchedulingPreference() == Sched::Latency)
149 return createTDListDAGScheduler(IS, OptLevel);
150 if (TLI.getSchedulingPreference() == Sched::RegPressure)
151 return createBURRListDAGScheduler(IS, OptLevel);
152 if (TLI.getSchedulingPreference() == Sched::Hybrid)
153 return createHybridListDAGScheduler(IS, OptLevel);
154 assert(TLI.getSchedulingPreference() == Sched::ILP &&
155 "Unknown sched type!");
156 return createILPListDAGScheduler(IS, OptLevel);
160 // EmitInstrWithCustomInserter - This method should be implemented by targets
161 // that mark instructions with the 'usesCustomInserter' flag. These
162 // instructions are special in various ways, which require special support to
163 // insert. The specified MachineInstr is created but not inserted into any
164 // basic blocks, and this method is called to expand it into a sequence of
165 // instructions, potentially also creating new basic blocks and control flow.
166 // When new basic blocks are inserted and the edges from MBB to its successors
167 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
170 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
171 MachineBasicBlock *MBB) const {
173 dbgs() << "If a target marks an instruction with "
174 "'usesCustomInserter', it must implement "
175 "TargetLowering::EmitInstrWithCustomInserter!";
181 //===----------------------------------------------------------------------===//
182 // SelectionDAGISel code
183 //===----------------------------------------------------------------------===//
185 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
186 CodeGenOpt::Level OL) :
187 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
188 FuncInfo(new FunctionLoweringInfo(TLI)),
189 CurDAG(new SelectionDAG(tm)),
190 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
194 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
195 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
198 SelectionDAGISel::~SelectionDAGISel() {
204 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
205 AU.addRequired<AliasAnalysis>();
206 AU.addPreserved<AliasAnalysis>();
207 AU.addRequired<GCModuleInfo>();
208 AU.addPreserved<GCModuleInfo>();
209 MachineFunctionPass::getAnalysisUsage(AU);
212 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
213 /// may trap on it. In this case we have to split the edge so that the path
214 /// through the predecessor block that doesn't go to the phi block doesn't
215 /// execute the possibly trapping instruction.
217 /// This is required for correctness, so it must be done at -O0.
219 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
220 // Loop for blocks with phi nodes.
221 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
222 PHINode *PN = dyn_cast<PHINode>(BB->begin());
223 if (PN == 0) continue;
226 // For each block with a PHI node, check to see if any of the input values
227 // are potentially trapping constant expressions. Constant expressions are
228 // the only potentially trapping value that can occur as the argument to a
230 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
231 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
232 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
233 if (CE == 0 || !CE->canTrap()) continue;
235 // The only case we have to worry about is when the edge is critical.
236 // Since this block has a PHI Node, we assume it has multiple input
237 // edges: check to see if the pred has multiple successors.
238 BasicBlock *Pred = PN->getIncomingBlock(i);
239 if (Pred->getTerminator()->getNumSuccessors() == 1)
242 // Okay, we have to split this edge.
243 SplitCriticalEdge(Pred->getTerminator(),
244 GetSuccessorNumber(Pred, BB), SDISel, true);
250 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
251 // Do some sanity-checking on the command-line options.
252 assert((!EnableFastISelVerbose || EnableFastISel) &&
253 "-fast-isel-verbose requires -fast-isel");
254 assert((!EnableFastISelAbort || EnableFastISel) &&
255 "-fast-isel-abort requires -fast-isel");
257 const Function &Fn = *mf.getFunction();
258 const TargetInstrInfo &TII = *TM.getInstrInfo();
259 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
262 RegInfo = &MF->getRegInfo();
263 AA = &getAnalysis<AliasAnalysis>();
264 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
266 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
268 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
271 FuncInfo->set(Fn, *MF);
274 SelectAllBasicBlocks(Fn);
276 // If the first basic block in the function has live ins that need to be
277 // copied into vregs, emit the copies into the top of the block before
278 // emitting the code for the block.
279 MachineBasicBlock *EntryMBB = MF->begin();
280 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
282 DenseMap<unsigned, unsigned> LiveInMap;
283 if (!FuncInfo->ArgDbgValues.empty())
284 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
285 E = RegInfo->livein_end(); LI != E; ++LI)
287 LiveInMap.insert(std::make_pair(LI->first, LI->second));
289 // Insert DBG_VALUE instructions for function arguments to the entry block.
290 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
291 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
292 unsigned Reg = MI->getOperand(0).getReg();
293 if (TargetRegisterInfo::isPhysicalRegister(Reg))
294 EntryMBB->insert(EntryMBB->begin(), MI);
296 MachineInstr *Def = RegInfo->getVRegDef(Reg);
297 MachineBasicBlock::iterator InsertPos = Def;
298 // FIXME: VR def may not be in entry block.
299 Def->getParent()->insert(llvm::next(InsertPos), MI);
302 // If Reg is live-in then update debug info to track its copy in a vreg.
303 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
304 if (LDI != LiveInMap.end()) {
305 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
306 MachineBasicBlock::iterator InsertPos = Def;
307 const MDNode *Variable =
308 MI->getOperand(MI->getNumOperands()-1).getMetadata();
309 unsigned Offset = MI->getOperand(1).getImm();
310 // Def is never a terminator here, so it is ok to increment InsertPos.
311 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
312 TII.get(TargetOpcode::DBG_VALUE))
313 .addReg(LDI->second, RegState::Debug)
314 .addImm(Offset).addMetadata(Variable);
316 // If this vreg is directly copied into an exported register then
317 // that COPY instructions also need DBG_VALUE, if it is the only
318 // user of LDI->second.
319 MachineInstr *CopyUseMI = NULL;
320 for (MachineRegisterInfo::use_iterator
321 UI = RegInfo->use_begin(LDI->second);
322 MachineInstr *UseMI = UI.skipInstruction();) {
323 if (UseMI->isDebugValue()) continue;
324 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
325 CopyUseMI = UseMI; continue;
327 // Otherwise this is another use or second copy use.
328 CopyUseMI = NULL; break;
331 MachineInstr *NewMI =
332 BuildMI(*MF, CopyUseMI->getDebugLoc(),
333 TII.get(TargetOpcode::DBG_VALUE))
334 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
335 .addImm(Offset).addMetadata(Variable);
336 EntryMBB->insertAfter(CopyUseMI, NewMI);
341 // Determine if there are any calls in this machine function.
342 MachineFrameInfo *MFI = MF->getFrameInfo();
343 if (!MFI->hasCalls()) {
344 for (MachineFunction::const_iterator
345 I = MF->begin(), E = MF->end(); I != E; ++I) {
346 const MachineBasicBlock *MBB = I;
347 for (MachineBasicBlock::const_iterator
348 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
349 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
351 if ((TID.isCall() && !TID.isReturn()) ||
352 II->isStackAligningInlineAsm()) {
353 MFI->setHasCalls(true);
361 // Determine if there is a call to setjmp in the machine function.
362 MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice());
364 // Replace forward-declared registers with the registers containing
365 // the desired value.
366 MachineRegisterInfo &MRI = MF->getRegInfo();
367 for (DenseMap<unsigned, unsigned>::iterator
368 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
370 unsigned From = I->first;
371 unsigned To = I->second;
372 // If To is also scheduled to be replaced, find what its ultimate
375 DenseMap<unsigned, unsigned>::iterator J =
376 FuncInfo->RegFixups.find(To);
381 MRI.replaceRegWith(From, To);
384 // Release function-specific state. SDB and CurDAG are already cleared
391 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
392 BasicBlock::const_iterator End,
394 // Lower all of the non-terminator instructions. If a call is emitted
395 // as a tail call, cease emitting nodes for this block. Terminators
396 // are handled below.
397 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
400 // Make sure the root of the DAG is up-to-date.
401 CurDAG->setRoot(SDB->getControlRoot());
402 HadTailCall = SDB->HasTailCall;
405 // Final step, emit the lowered DAG as machine code.
409 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
410 SmallPtrSet<SDNode*, 128> VisitedNodes;
411 SmallVector<SDNode*, 128> Worklist;
413 Worklist.push_back(CurDAG->getRoot().getNode());
420 SDNode *N = Worklist.pop_back_val();
422 // If we've already seen this node, ignore it.
423 if (!VisitedNodes.insert(N))
426 // Otherwise, add all chain operands to the worklist.
427 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
428 if (N->getOperand(i).getValueType() == MVT::Other)
429 Worklist.push_back(N->getOperand(i).getNode());
431 // If this is a CopyToReg with a vreg dest, process it.
432 if (N->getOpcode() != ISD::CopyToReg)
435 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
436 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
439 // Ignore non-scalar or non-integer values.
440 SDValue Src = N->getOperand(2);
441 EVT SrcVT = Src.getValueType();
442 if (!SrcVT.isInteger() || SrcVT.isVector())
445 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
446 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
447 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
448 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
449 } while (!Worklist.empty());
452 void SelectionDAGISel::CodeGenAndEmitDAG() {
453 std::string GroupName;
454 if (TimePassesIsEnabled)
455 GroupName = "Instruction Selection and Scheduling";
456 std::string BlockName;
457 int BlockNumber = -1;
459 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
460 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
464 BlockNumber = FuncInfo->MBB->getNumber();
465 BlockName = MF->getFunction()->getNameStr() + ":" +
466 FuncInfo->MBB->getBasicBlock()->getNameStr();
468 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
469 << " '" << BlockName << "'\n"; CurDAG->dump());
471 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
473 // Run the DAG combiner in pre-legalize mode.
475 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
476 CurDAG->Combine(Unrestricted, *AA, OptLevel);
479 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
480 << " '" << BlockName << "'\n"; CurDAG->dump());
482 // Second step, hack on the DAG until it only uses operations and types that
483 // the target supports.
484 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
489 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
490 Changed = CurDAG->LegalizeTypes();
493 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
494 << " '" << BlockName << "'\n"; CurDAG->dump());
497 if (ViewDAGCombineLT)
498 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
500 // Run the DAG combiner in post-type-legalize mode.
502 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
503 TimePassesIsEnabled);
504 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
507 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
508 << " '" << BlockName << "'\n"; CurDAG->dump());
512 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
513 Changed = CurDAG->LegalizeVectors();
518 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
519 CurDAG->LegalizeTypes();
522 if (ViewDAGCombineLT)
523 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
525 // Run the DAG combiner in post-type-legalize mode.
527 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
528 TimePassesIsEnabled);
529 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
532 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
533 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
536 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
539 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
543 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
544 << " '" << BlockName << "'\n"; CurDAG->dump());
546 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
548 // Run the DAG combiner in post-legalize mode.
550 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
551 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
554 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
555 << " '" << BlockName << "'\n"; CurDAG->dump());
557 if (OptLevel != CodeGenOpt::None)
558 ComputeLiveOutVRegInfo();
560 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
562 // Third, instruction select all of the operations to machine code, adding the
563 // code to the MachineBasicBlock.
565 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
566 DoInstructionSelection();
569 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
570 << " '" << BlockName << "'\n"; CurDAG->dump());
572 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
574 // Schedule machine code.
575 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
577 NamedRegionTimer T("Instruction Scheduling", GroupName,
578 TimePassesIsEnabled);
579 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
582 if (ViewSUnitDAGs) Scheduler->viewGraph();
584 // Emit machine code to BB. This can change 'BB' to the last block being
586 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
588 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
590 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
591 FuncInfo->InsertPt = Scheduler->InsertPos;
594 // If the block was split, make sure we update any references that are used to
595 // update PHI nodes later on.
596 if (FirstMBB != LastMBB)
597 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
599 // Free the scheduler state.
601 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
602 TimePassesIsEnabled);
606 // Free the SelectionDAG state, now that we're finished with it.
610 void SelectionDAGISel::DoInstructionSelection() {
611 DEBUG(errs() << "===== Instruction selection begins: BB#"
612 << FuncInfo->MBB->getNumber()
613 << " '" << FuncInfo->MBB->getName() << "'\n");
617 // Select target instructions for the DAG.
619 // Number all nodes with a topological order and set DAGSize.
620 DAGSize = CurDAG->AssignTopologicalOrder();
622 // Create a dummy node (which is not added to allnodes), that adds
623 // a reference to the root node, preventing it from being deleted,
624 // and tracking any changes of the root.
625 HandleSDNode Dummy(CurDAG->getRoot());
626 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
629 // The AllNodes list is now topological-sorted. Visit the
630 // nodes by starting at the end of the list (the root of the
631 // graph) and preceding back toward the beginning (the entry
633 while (ISelPosition != CurDAG->allnodes_begin()) {
634 SDNode *Node = --ISelPosition;
635 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
636 // but there are currently some corner cases that it misses. Also, this
637 // makes it theoretically possible to disable the DAGCombiner.
638 if (Node->use_empty())
641 SDNode *ResNode = Select(Node);
643 // FIXME: This is pretty gross. 'Select' should be changed to not return
644 // anything at all and this code should be nuked with a tactical strike.
646 // If node should not be replaced, continue with the next one.
647 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
651 ReplaceUses(Node, ResNode);
653 // If after the replacement this node is not used any more,
654 // remove this dead node.
655 if (Node->use_empty()) { // Don't delete EntryToken, etc.
656 ISelUpdater ISU(ISelPosition);
657 CurDAG->RemoveDeadNode(Node, &ISU);
661 CurDAG->setRoot(Dummy.getValue());
664 DEBUG(errs() << "===== Instruction selection ends:\n");
666 PostprocessISelDAG();
669 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
670 /// do other setup for EH landing-pad blocks.
671 void SelectionDAGISel::PrepareEHLandingPad() {
672 // Add a label to mark the beginning of the landing pad. Deletion of the
673 // landing pad can thus be detected via the MachineModuleInfo.
674 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
676 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
677 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
680 // Mark exception register as live in.
681 unsigned Reg = TLI.getExceptionAddressRegister();
682 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
684 // Mark exception selector register as live in.
685 Reg = TLI.getExceptionSelectorRegister();
686 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
688 // FIXME: Hack around an exception handling flaw (PR1508): the personality
689 // function and list of typeids logically belong to the invoke (or, if you
690 // like, the basic block containing the invoke), and need to be associated
691 // with it in the dwarf exception handling tables. Currently however the
692 // information is provided by an intrinsic (eh.selector) that can be moved
693 // to unexpected places by the optimizers: if the unwind edge is critical,
694 // then breaking it can result in the intrinsics being in the successor of
695 // the landing pad, not the landing pad itself. This results
696 // in exceptions not being caught because no typeids are associated with
697 // the invoke. This may not be the only way things can go wrong, but it
698 // is the only way we try to work around for the moment.
699 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
700 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
702 if (Br && Br->isUnconditional()) { // Critical edge?
703 BasicBlock::const_iterator I, E;
704 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
705 if (isa<EHSelectorInst>(I))
709 // No catch info found - try to extract some from the successor.
710 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
716 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
717 /// load into the specified FoldInst. Note that we could have a sequence where
718 /// multiple LLVM IR instructions are folded into the same machineinstr. For
719 /// example we could have:
720 /// A: x = load i32 *P
721 /// B: y = icmp A, 42
724 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
725 /// any other folded instructions) because it is between A and C.
727 /// If we succeed in folding the load into the operation, return true.
729 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
730 const Instruction *FoldInst,
732 // We know that the load has a single use, but don't know what it is. If it
733 // isn't one of the folded instructions, then we can't succeed here. Handle
734 // this by scanning the single-use users of the load until we get to FoldInst.
735 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
737 const Instruction *TheUser = LI->use_back();
738 while (TheUser != FoldInst && // Scan up until we find FoldInst.
739 // Stay in the right block.
740 TheUser->getParent() == FoldInst->getParent() &&
741 --MaxUsers) { // Don't scan too far.
742 // If there are multiple or no uses of this instruction, then bail out.
743 if (!TheUser->hasOneUse())
746 TheUser = TheUser->use_back();
749 // Don't try to fold volatile loads. Target has to deal with alignment
751 if (LI->isVolatile()) return false;
753 // Figure out which vreg this is going into. If there is no assigned vreg yet
754 // then there actually was no reference to it. Perhaps the load is referenced
755 // by a dead instruction.
756 unsigned LoadReg = FastIS->getRegForValue(LI);
760 // Check to see what the uses of this vreg are. If it has no uses, or more
761 // than one use (at the machine instr level) then we can't fold it.
762 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
763 if (RI == RegInfo->reg_end())
766 // See if there is exactly one use of the vreg. If there are multiple uses,
767 // then the instruction got lowered to multiple machine instructions or the
768 // use of the loaded value ended up being multiple operands of the result, in
769 // either case, we can't fold this.
770 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
771 if (PostRI != RegInfo->reg_end())
774 assert(RI.getOperand().isUse() &&
775 "The only use of the vreg must be a use, we haven't emitted the def!");
777 MachineInstr *User = &*RI;
779 // Set the insertion point properly. Folding the load can cause generation of
780 // other random instructions (like sign extends) for addressing modes, make
781 // sure they get inserted in a logical place before the new instruction.
782 FuncInfo->InsertPt = User;
783 FuncInfo->MBB = User->getParent();
785 // Ask the target to try folding the load.
786 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
790 /// CheckLineNumbers - Check if basic block instructions follow source order
792 static void CheckLineNumbers(const BasicBlock *BB) {
795 for (BasicBlock::const_iterator BI = BB->begin(),
796 BE = BB->end(); BI != BE; ++BI) {
797 const DebugLoc DL = BI->getDebugLoc();
798 if (DL.isUnknown()) continue;
799 unsigned L = DL.getLine();
800 unsigned C = DL.getCol();
801 if (L < Line || (L == Line && C < Col)) {
802 ++NumBBWithOutOfOrderLineInfo;
810 /// CheckLineNumbers - Check if machine basic block instructions follow source
812 static void CheckLineNumbers(const MachineBasicBlock *MBB) {
815 for (MachineBasicBlock::const_iterator MBI = MBB->begin(),
816 MBE = MBB->end(); MBI != MBE; ++MBI) {
817 const DebugLoc DL = MBI->getDebugLoc();
818 if (DL.isUnknown()) continue;
819 unsigned L = DL.getLine();
820 unsigned C = DL.getCol();
821 if (L < Line || (L == Line && C < Col)) {
822 ++NumMBBWithOutOfOrderLineInfo;
831 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
832 /// side-effect free and is either dead or folded into a generated instruction.
833 /// Return false if it needs to be emitted.
834 static bool isFoldedOrDeadInstruction(const Instruction *I,
835 FunctionLoweringInfo *FuncInfo) {
836 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
837 !isa<TerminatorInst>(I) && // Terminators aren't folded.
838 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
839 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
842 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
843 // Initialize the Fast-ISel state, if needed.
844 FastISel *FastIS = 0;
846 FastIS = TLI.createFastISel(*FuncInfo);
848 // Iterate over all basic blocks in the function.
849 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
850 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
851 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
852 const BasicBlock *LLVMBB = *I;
854 CheckLineNumbers(LLVMBB);
857 if (OptLevel != CodeGenOpt::None) {
858 bool AllPredsVisited = true;
859 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
861 if (!FuncInfo->VisitedBBs.count(*PI)) {
862 AllPredsVisited = false;
867 if (AllPredsVisited) {
868 for (BasicBlock::const_iterator I = LLVMBB->begin();
869 isa<PHINode>(I); ++I)
870 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
872 for (BasicBlock::const_iterator I = LLVMBB->begin();
873 isa<PHINode>(I); ++I)
874 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
877 FuncInfo->VisitedBBs.insert(LLVMBB);
880 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
881 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
883 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
884 BasicBlock::const_iterator const End = LLVMBB->end();
885 BasicBlock::const_iterator BI = End;
887 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
889 // Setup an EH landing-pad block.
890 if (FuncInfo->MBB->isLandingPad())
891 PrepareEHLandingPad();
893 // Lower any arguments needed in this block if this is the entry block.
894 if (LLVMBB == &Fn.getEntryBlock())
895 LowerArguments(LLVMBB);
897 // Before doing SelectionDAG ISel, see if FastISel has been requested.
899 FastIS->startNewBlock();
901 // Emit code for any incoming arguments. This must happen before
902 // beginning FastISel on the entry block.
903 if (LLVMBB == &Fn.getEntryBlock()) {
904 CurDAG->setRoot(SDB->getControlRoot());
908 // If we inserted any instructions at the beginning, make a note of
909 // where they are, so we can be sure to emit subsequent instructions
911 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
912 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
914 FastIS->setLastLocalValue(0);
917 // Do FastISel on as many instructions as possible.
918 for (; BI != Begin; --BI) {
919 const Instruction *Inst = llvm::prior(BI);
921 // If we no longer require this instruction, skip it.
922 if (isFoldedOrDeadInstruction(Inst, FuncInfo))
925 // Bottom-up: reset the insert pos at the top, after any local-value
927 FastIS->recomputeInsertPt();
929 // Try to select the instruction with FastISel.
930 if (FastIS->SelectInstruction(Inst)) {
931 ++NumFastIselSuccess;
932 // If fast isel succeeded, skip over all the folded instructions, and
933 // then see if there is a load right before the selected instructions.
934 // Try to fold the load if so.
935 const Instruction *BeforeInst = Inst;
936 while (BeforeInst != Begin) {
937 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
938 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
941 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
942 BeforeInst->hasOneUse() &&
943 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS))
944 // If we succeeded, don't re-select the load.
945 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
949 // Then handle certain instructions as single-LLVM-Instruction blocks.
950 if (isa<CallInst>(Inst)) {
951 ++NumFastIselFailures;
952 if (EnableFastISelVerbose || EnableFastISelAbort) {
953 dbgs() << "FastISel missed call: ";
957 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
958 unsigned &R = FuncInfo->ValueMap[Inst];
960 R = FuncInfo->CreateRegs(Inst->getType());
963 bool HadTailCall = false;
964 SelectBasicBlock(Inst, BI, HadTailCall);
966 // If the call was emitted as a tail call, we're done with the block.
975 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
976 // Don't abort, and use a different message for terminator misses.
977 ++NumFastIselFailures;
978 if (EnableFastISelVerbose || EnableFastISelAbort) {
979 dbgs() << "FastISel missed terminator: ";
983 ++NumFastIselFailures;
984 if (EnableFastISelVerbose || EnableFastISelAbort) {
985 dbgs() << "FastISel miss: ";
988 if (EnableFastISelAbort)
989 // The "fast" selector couldn't handle something and bailed.
990 // For the purpose of debugging, just abort.
991 llvm_unreachable("FastISel didn't select the entire block");
996 FastIS->recomputeInsertPt();
1002 ++NumFastIselBlocks;
1005 // Run SelectionDAG instruction selection on the remainder of the block
1006 // not handled by FastISel. If FastISel is not run, this is the entire
1009 SelectBasicBlock(Begin, BI, HadTailCall);
1013 FuncInfo->PHINodesToUpdate.clear();
1018 for (MachineFunction::const_iterator MBI = MF->begin(), MBE = MF->end();
1020 CheckLineNumbers(MBI);
1022 SDB->clearDanglingDebugInfo();
1026 SelectionDAGISel::FinishBasicBlock() {
1028 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1029 << FuncInfo->PHINodesToUpdate.size() << "\n";
1030 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1031 dbgs() << "Node " << i << " : ("
1032 << FuncInfo->PHINodesToUpdate[i].first
1033 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1035 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1036 // PHI nodes in successors.
1037 if (SDB->SwitchCases.empty() &&
1038 SDB->JTCases.empty() &&
1039 SDB->BitTestCases.empty()) {
1040 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1041 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1042 assert(PHI->isPHI() &&
1043 "This is not a machine PHI node that we are updating!");
1044 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1047 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1048 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1053 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1054 // Lower header first, if it wasn't already lowered
1055 if (!SDB->BitTestCases[i].Emitted) {
1056 // Set the current basic block to the mbb we wish to insert the code into
1057 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1058 FuncInfo->InsertPt = FuncInfo->MBB->end();
1060 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1061 CurDAG->setRoot(SDB->getRoot());
1063 CodeGenAndEmitDAG();
1066 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1067 // Set the current basic block to the mbb we wish to insert the code into
1068 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1069 FuncInfo->InsertPt = FuncInfo->MBB->end();
1072 SDB->visitBitTestCase(SDB->BitTestCases[i],
1073 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1074 SDB->BitTestCases[i].Reg,
1075 SDB->BitTestCases[i].Cases[j],
1078 SDB->visitBitTestCase(SDB->BitTestCases[i],
1079 SDB->BitTestCases[i].Default,
1080 SDB->BitTestCases[i].Reg,
1081 SDB->BitTestCases[i].Cases[j],
1085 CurDAG->setRoot(SDB->getRoot());
1087 CodeGenAndEmitDAG();
1091 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1093 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1094 MachineBasicBlock *PHIBB = PHI->getParent();
1095 assert(PHI->isPHI() &&
1096 "This is not a machine PHI node that we are updating!");
1097 // This is "default" BB. We have two jumps to it. From "header" BB and
1098 // from last "case" BB.
1099 if (PHIBB == SDB->BitTestCases[i].Default) {
1100 PHI->addOperand(MachineOperand::
1101 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1103 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1104 PHI->addOperand(MachineOperand::
1105 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1107 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1110 // One of "cases" BB.
1111 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1113 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1114 if (cBB->isSuccessor(PHIBB)) {
1115 PHI->addOperand(MachineOperand::
1116 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1118 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1123 SDB->BitTestCases.clear();
1125 // If the JumpTable record is filled in, then we need to emit a jump table.
1126 // Updating the PHI nodes is tricky in this case, since we need to determine
1127 // whether the PHI is a successor of the range check MBB or the jump table MBB
1128 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1129 // Lower header first, if it wasn't already lowered
1130 if (!SDB->JTCases[i].first.Emitted) {
1131 // Set the current basic block to the mbb we wish to insert the code into
1132 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1133 FuncInfo->InsertPt = FuncInfo->MBB->end();
1135 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1137 CurDAG->setRoot(SDB->getRoot());
1139 CodeGenAndEmitDAG();
1142 // Set the current basic block to the mbb we wish to insert the code into
1143 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1144 FuncInfo->InsertPt = FuncInfo->MBB->end();
1146 SDB->visitJumpTable(SDB->JTCases[i].second);
1147 CurDAG->setRoot(SDB->getRoot());
1149 CodeGenAndEmitDAG();
1152 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1154 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1155 MachineBasicBlock *PHIBB = PHI->getParent();
1156 assert(PHI->isPHI() &&
1157 "This is not a machine PHI node that we are updating!");
1158 // "default" BB. We can go there only from header BB.
1159 if (PHIBB == SDB->JTCases[i].second.Default) {
1161 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1164 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1166 // JT BB. Just iterate over successors here
1167 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1169 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1171 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1175 SDB->JTCases.clear();
1177 // If the switch block involved a branch to one of the actual successors, we
1178 // need to update PHI nodes in that block.
1179 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1180 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1181 assert(PHI->isPHI() &&
1182 "This is not a machine PHI node that we are updating!");
1183 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1185 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1186 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1190 // If we generated any switch lowering information, build and codegen any
1191 // additional DAGs necessary.
1192 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1193 // Set the current basic block to the mbb we wish to insert the code into
1194 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1195 FuncInfo->InsertPt = FuncInfo->MBB->end();
1197 // Determine the unique successors.
1198 SmallVector<MachineBasicBlock *, 2> Succs;
1199 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1200 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1201 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1203 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1204 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1205 CurDAG->setRoot(SDB->getRoot());
1207 CodeGenAndEmitDAG();
1209 // Remember the last block, now that any splitting is done, for use in
1210 // populating PHI nodes in successors.
1211 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1213 // Handle any PHI nodes in successors of this chunk, as if we were coming
1214 // from the original BB before switch expansion. Note that PHI nodes can
1215 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1216 // handle them the right number of times.
1217 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1218 FuncInfo->MBB = Succs[i];
1219 FuncInfo->InsertPt = FuncInfo->MBB->end();
1220 // FuncInfo->MBB may have been removed from the CFG if a branch was
1222 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1223 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1224 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1226 // This value for this PHI node is recorded in PHINodesToUpdate.
1227 for (unsigned pn = 0; ; ++pn) {
1228 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1229 "Didn't find PHI entry!");
1230 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1231 Phi->addOperand(MachineOperand::
1232 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1234 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1242 SDB->SwitchCases.clear();
1246 /// Create the scheduler. If a specific scheduler was specified
1247 /// via the SchedulerRegistry, use it, otherwise select the
1248 /// one preferred by the target.
1250 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1251 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1255 RegisterScheduler::setDefault(Ctor);
1258 return Ctor(this, OptLevel);
1261 //===----------------------------------------------------------------------===//
1262 // Helper functions used by the generated instruction selector.
1263 //===----------------------------------------------------------------------===//
1264 // Calls to these methods are generated by tblgen.
1266 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1267 /// the dag combiner simplified the 255, we still want to match. RHS is the
1268 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1269 /// specified in the .td file (e.g. 255).
1270 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1271 int64_t DesiredMaskS) const {
1272 const APInt &ActualMask = RHS->getAPIntValue();
1273 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1275 // If the actual mask exactly matches, success!
1276 if (ActualMask == DesiredMask)
1279 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1280 if (ActualMask.intersects(~DesiredMask))
1283 // Otherwise, the DAG Combiner may have proven that the value coming in is
1284 // either already zero or is not demanded. Check for known zero input bits.
1285 APInt NeededMask = DesiredMask & ~ActualMask;
1286 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1289 // TODO: check to see if missing bits are just not demanded.
1291 // Otherwise, this pattern doesn't match.
1295 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1296 /// the dag combiner simplified the 255, we still want to match. RHS is the
1297 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1298 /// specified in the .td file (e.g. 255).
1299 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1300 int64_t DesiredMaskS) const {
1301 const APInt &ActualMask = RHS->getAPIntValue();
1302 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1304 // If the actual mask exactly matches, success!
1305 if (ActualMask == DesiredMask)
1308 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1309 if (ActualMask.intersects(~DesiredMask))
1312 // Otherwise, the DAG Combiner may have proven that the value coming in is
1313 // either already zero or is not demanded. Check for known zero input bits.
1314 APInt NeededMask = DesiredMask & ~ActualMask;
1316 APInt KnownZero, KnownOne;
1317 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1319 // If all the missing bits in the or are already known to be set, match!
1320 if ((NeededMask & KnownOne) == NeededMask)
1323 // TODO: check to see if missing bits are just not demanded.
1325 // Otherwise, this pattern doesn't match.
1330 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1331 /// by tblgen. Others should not call it.
1332 void SelectionDAGISel::
1333 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1334 std::vector<SDValue> InOps;
1335 std::swap(InOps, Ops);
1337 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1338 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1339 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1340 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1342 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1343 if (InOps[e-1].getValueType() == MVT::Glue)
1344 --e; // Don't process a glue operand if it is here.
1347 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1348 if (!InlineAsm::isMemKind(Flags)) {
1349 // Just skip over this operand, copying the operands verbatim.
1350 Ops.insert(Ops.end(), InOps.begin()+i,
1351 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1352 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1354 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1355 "Memory operand with multiple values?");
1356 // Otherwise, this is a memory operand. Ask the target to select it.
1357 std::vector<SDValue> SelOps;
1358 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1359 report_fatal_error("Could not match memory address. Inline asm"
1362 // Add this to the output node.
1364 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1365 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1366 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1371 // Add the glue input back if present.
1372 if (e != InOps.size())
1373 Ops.push_back(InOps.back());
1376 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1379 static SDNode *findGlueUse(SDNode *N) {
1380 unsigned FlagResNo = N->getNumValues()-1;
1381 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1382 SDUse &Use = I.getUse();
1383 if (Use.getResNo() == FlagResNo)
1384 return Use.getUser();
1389 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1390 /// This function recursively traverses up the operand chain, ignoring
1392 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1393 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1394 bool IgnoreChains) {
1395 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1396 // greater than all of its (recursive) operands. If we scan to a point where
1397 // 'use' is smaller than the node we're scanning for, then we know we will
1400 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1401 // happen because we scan down to newly selected nodes in the case of glue
1403 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1406 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1407 // won't fail if we scan it again.
1408 if (!Visited.insert(Use))
1411 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1412 // Ignore chain uses, they are validated by HandleMergeInputChains.
1413 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1416 SDNode *N = Use->getOperand(i).getNode();
1418 if (Use == ImmedUse || Use == Root)
1419 continue; // We are not looking for immediate use.
1424 // Traverse up the operand chain.
1425 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1431 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1432 /// operand node N of U during instruction selection that starts at Root.
1433 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1434 SDNode *Root) const {
1435 if (OptLevel == CodeGenOpt::None) return false;
1436 return N.hasOneUse();
1439 /// IsLegalToFold - Returns true if the specific operand node N of
1440 /// U can be folded during instruction selection that starts at Root.
1441 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1442 CodeGenOpt::Level OptLevel,
1443 bool IgnoreChains) {
1444 if (OptLevel == CodeGenOpt::None) return false;
1446 // If Root use can somehow reach N through a path that that doesn't contain
1447 // U then folding N would create a cycle. e.g. In the following
1448 // diagram, Root can reach N through X. If N is folded into into Root, then
1449 // X is both a predecessor and a successor of U.
1460 // * indicates nodes to be folded together.
1462 // If Root produces glue, then it gets (even more) interesting. Since it
1463 // will be "glued" together with its glue use in the scheduler, we need to
1464 // check if it might reach N.
1483 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1484 // (call it Fold), then X is a predecessor of GU and a successor of
1485 // Fold. But since Fold and GU are glued together, this will create
1486 // a cycle in the scheduling graph.
1488 // If the node has glue, walk down the graph to the "lowest" node in the
1490 EVT VT = Root->getValueType(Root->getNumValues()-1);
1491 while (VT == MVT::Glue) {
1492 SDNode *GU = findGlueUse(Root);
1496 VT = Root->getValueType(Root->getNumValues()-1);
1498 // If our query node has a glue result with a use, we've walked up it. If
1499 // the user (which has already been selected) has a chain or indirectly uses
1500 // the chain, our WalkChainUsers predicate will not consider it. Because of
1501 // this, we cannot ignore chains in this predicate.
1502 IgnoreChains = false;
1506 SmallPtrSet<SDNode*, 16> Visited;
1507 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1510 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1511 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1512 SelectInlineAsmMemoryOperands(Ops);
1514 std::vector<EVT> VTs;
1515 VTs.push_back(MVT::Other);
1516 VTs.push_back(MVT::Glue);
1517 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1518 VTs, &Ops[0], Ops.size());
1520 return New.getNode();
1523 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1524 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1527 /// GetVBR - decode a vbr encoding whose top bit is set.
1528 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1529 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1530 assert(Val >= 128 && "Not a VBR");
1531 Val &= 127; // Remove first vbr bit.
1536 NextBits = MatcherTable[Idx++];
1537 Val |= (NextBits&127) << Shift;
1539 } while (NextBits & 128);
1545 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1546 /// interior glue and chain results to use the new glue and chain results.
1547 void SelectionDAGISel::
1548 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1549 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1551 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1552 bool isMorphNodeTo) {
1553 SmallVector<SDNode*, 4> NowDeadNodes;
1555 ISelUpdater ISU(ISelPosition);
1557 // Now that all the normal results are replaced, we replace the chain and
1558 // glue results if present.
1559 if (!ChainNodesMatched.empty()) {
1560 assert(InputChain.getNode() != 0 &&
1561 "Matched input chains but didn't produce a chain");
1562 // Loop over all of the nodes we matched that produced a chain result.
1563 // Replace all the chain results with the final chain we ended up with.
1564 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1565 SDNode *ChainNode = ChainNodesMatched[i];
1567 // If this node was already deleted, don't look at it.
1568 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1571 // Don't replace the results of the root node if we're doing a
1573 if (ChainNode == NodeToMatch && isMorphNodeTo)
1576 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1577 if (ChainVal.getValueType() == MVT::Glue)
1578 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1579 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1580 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1582 // If the node became dead and we haven't already seen it, delete it.
1583 if (ChainNode->use_empty() &&
1584 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1585 NowDeadNodes.push_back(ChainNode);
1589 // If the result produces glue, update any glue results in the matched
1590 // pattern with the glue result.
1591 if (InputGlue.getNode() != 0) {
1592 // Handle any interior nodes explicitly marked.
1593 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1594 SDNode *FRN = GlueResultNodesMatched[i];
1596 // If this node was already deleted, don't look at it.
1597 if (FRN->getOpcode() == ISD::DELETED_NODE)
1600 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1601 "Doesn't have a glue result");
1602 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1605 // If the node became dead and we haven't already seen it, delete it.
1606 if (FRN->use_empty() &&
1607 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1608 NowDeadNodes.push_back(FRN);
1612 if (!NowDeadNodes.empty())
1613 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1615 DEBUG(errs() << "ISEL: Match complete!\n");
1621 CR_LeadsToInteriorNode
1624 /// WalkChainUsers - Walk down the users of the specified chained node that is
1625 /// part of the pattern we're matching, looking at all of the users we find.
1626 /// This determines whether something is an interior node, whether we have a
1627 /// non-pattern node in between two pattern nodes (which prevent folding because
1628 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1629 /// between pattern nodes (in which case the TF becomes part of the pattern).
1631 /// The walk we do here is guaranteed to be small because we quickly get down to
1632 /// already selected nodes "below" us.
1634 WalkChainUsers(SDNode *ChainedNode,
1635 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1636 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1637 ChainResult Result = CR_Simple;
1639 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1640 E = ChainedNode->use_end(); UI != E; ++UI) {
1641 // Make sure the use is of the chain, not some other value we produce.
1642 if (UI.getUse().getValueType() != MVT::Other) continue;
1646 // If we see an already-selected machine node, then we've gone beyond the
1647 // pattern that we're selecting down into the already selected chunk of the
1649 if (User->isMachineOpcode() ||
1650 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1653 if (User->getOpcode() == ISD::CopyToReg ||
1654 User->getOpcode() == ISD::CopyFromReg ||
1655 User->getOpcode() == ISD::INLINEASM ||
1656 User->getOpcode() == ISD::EH_LABEL) {
1657 // If their node ID got reset to -1 then they've already been selected.
1658 // Treat them like a MachineOpcode.
1659 if (User->getNodeId() == -1)
1663 // If we have a TokenFactor, we handle it specially.
1664 if (User->getOpcode() != ISD::TokenFactor) {
1665 // If the node isn't a token factor and isn't part of our pattern, then it
1666 // must be a random chained node in between two nodes we're selecting.
1667 // This happens when we have something like:
1672 // Because we structurally match the load/store as a read/modify/write,
1673 // but the call is chained between them. We cannot fold in this case
1674 // because it would induce a cycle in the graph.
1675 if (!std::count(ChainedNodesInPattern.begin(),
1676 ChainedNodesInPattern.end(), User))
1677 return CR_InducesCycle;
1679 // Otherwise we found a node that is part of our pattern. For example in:
1683 // This would happen when we're scanning down from the load and see the
1684 // store as a user. Record that there is a use of ChainedNode that is
1685 // part of the pattern and keep scanning uses.
1686 Result = CR_LeadsToInteriorNode;
1687 InteriorChainedNodes.push_back(User);
1691 // If we found a TokenFactor, there are two cases to consider: first if the
1692 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1693 // uses of the TF are in our pattern) we just want to ignore it. Second,
1694 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1700 // | \ DAG's like cheese
1703 // [TokenFactor] [Op]
1710 // In this case, the TokenFactor becomes part of our match and we rewrite it
1711 // as a new TokenFactor.
1713 // To distinguish these two cases, do a recursive walk down the uses.
1714 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1716 // If the uses of the TokenFactor are just already-selected nodes, ignore
1717 // it, it is "below" our pattern.
1719 case CR_InducesCycle:
1720 // If the uses of the TokenFactor lead to nodes that are not part of our
1721 // pattern that are not selected, folding would turn this into a cycle,
1723 return CR_InducesCycle;
1724 case CR_LeadsToInteriorNode:
1725 break; // Otherwise, keep processing.
1728 // Okay, we know we're in the interesting interior case. The TokenFactor
1729 // is now going to be considered part of the pattern so that we rewrite its
1730 // uses (it may have uses that are not part of the pattern) with the
1731 // ultimate chain result of the generated code. We will also add its chain
1732 // inputs as inputs to the ultimate TokenFactor we create.
1733 Result = CR_LeadsToInteriorNode;
1734 ChainedNodesInPattern.push_back(User);
1735 InteriorChainedNodes.push_back(User);
1742 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1743 /// operation for when the pattern matched at least one node with a chains. The
1744 /// input vector contains a list of all of the chained nodes that we match. We
1745 /// must determine if this is a valid thing to cover (i.e. matching it won't
1746 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1747 /// be used as the input node chain for the generated nodes.
1749 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1750 SelectionDAG *CurDAG) {
1751 // Walk all of the chained nodes we've matched, recursively scanning down the
1752 // users of the chain result. This adds any TokenFactor nodes that are caught
1753 // in between chained nodes to the chained and interior nodes list.
1754 SmallVector<SDNode*, 3> InteriorChainedNodes;
1755 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1756 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1757 InteriorChainedNodes) == CR_InducesCycle)
1758 return SDValue(); // Would induce a cycle.
1761 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1762 // that we are interested in. Form our input TokenFactor node.
1763 SmallVector<SDValue, 3> InputChains;
1764 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1765 // Add the input chain of this node to the InputChains list (which will be
1766 // the operands of the generated TokenFactor) if it's not an interior node.
1767 SDNode *N = ChainNodesMatched[i];
1768 if (N->getOpcode() != ISD::TokenFactor) {
1769 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1772 // Otherwise, add the input chain.
1773 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1774 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1775 InputChains.push_back(InChain);
1779 // If we have a token factor, we want to add all inputs of the token factor
1780 // that are not part of the pattern we're matching.
1781 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1782 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1783 N->getOperand(op).getNode()))
1784 InputChains.push_back(N->getOperand(op));
1789 if (InputChains.size() == 1)
1790 return InputChains[0];
1791 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1792 MVT::Other, &InputChains[0], InputChains.size());
1795 /// MorphNode - Handle morphing a node in place for the selector.
1796 SDNode *SelectionDAGISel::
1797 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1798 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1799 // It is possible we're using MorphNodeTo to replace a node with no
1800 // normal results with one that has a normal result (or we could be
1801 // adding a chain) and the input could have glue and chains as well.
1802 // In this case we need to shift the operands down.
1803 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1804 // than the old isel though.
1805 int OldGlueResultNo = -1, OldChainResultNo = -1;
1807 unsigned NTMNumResults = Node->getNumValues();
1808 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1809 OldGlueResultNo = NTMNumResults-1;
1810 if (NTMNumResults != 1 &&
1811 Node->getValueType(NTMNumResults-2) == MVT::Other)
1812 OldChainResultNo = NTMNumResults-2;
1813 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1814 OldChainResultNo = NTMNumResults-1;
1816 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1817 // that this deletes operands of the old node that become dead.
1818 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1820 // MorphNodeTo can operate in two ways: if an existing node with the
1821 // specified operands exists, it can just return it. Otherwise, it
1822 // updates the node in place to have the requested operands.
1824 // If we updated the node in place, reset the node ID. To the isel,
1825 // this should be just like a newly allocated machine node.
1829 unsigned ResNumResults = Res->getNumValues();
1830 // Move the glue if needed.
1831 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1832 (unsigned)OldGlueResultNo != ResNumResults-1)
1833 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1834 SDValue(Res, ResNumResults-1));
1836 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1839 // Move the chain reference if needed.
1840 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1841 (unsigned)OldChainResultNo != ResNumResults-1)
1842 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1843 SDValue(Res, ResNumResults-1));
1845 // Otherwise, no replacement happened because the node already exists. Replace
1846 // Uses of the old node with the new one.
1848 CurDAG->ReplaceAllUsesWith(Node, Res);
1853 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1854 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1855 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1857 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1858 // Accept if it is exactly the same as a previously recorded node.
1859 unsigned RecNo = MatcherTable[MatcherIndex++];
1860 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1861 return N == RecordedNodes[RecNo].first;
1864 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1865 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1866 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1867 SelectionDAGISel &SDISel) {
1868 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1871 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1872 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1873 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1874 SelectionDAGISel &SDISel, SDNode *N) {
1875 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1878 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1879 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1881 uint16_t Opc = MatcherTable[MatcherIndex++];
1882 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1883 return N->getOpcode() == Opc;
1886 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1887 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1888 SDValue N, const TargetLowering &TLI) {
1889 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1890 if (N.getValueType() == VT) return true;
1892 // Handle the case when VT is iPTR.
1893 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1896 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1897 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1898 SDValue N, const TargetLowering &TLI,
1900 if (ChildNo >= N.getNumOperands())
1901 return false; // Match fails if out of range child #.
1902 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1906 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1907 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1909 return cast<CondCodeSDNode>(N)->get() ==
1910 (ISD::CondCode)MatcherTable[MatcherIndex++];
1913 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1914 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1915 SDValue N, const TargetLowering &TLI) {
1916 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1917 if (cast<VTSDNode>(N)->getVT() == VT)
1920 // Handle the case when VT is iPTR.
1921 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1924 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1925 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1927 int64_t Val = MatcherTable[MatcherIndex++];
1929 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1931 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1932 return C != 0 && C->getSExtValue() == Val;
1935 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1936 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1937 SDValue N, SelectionDAGISel &SDISel) {
1938 int64_t Val = MatcherTable[MatcherIndex++];
1940 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1942 if (N->getOpcode() != ISD::AND) return false;
1944 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1945 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1948 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1949 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1950 SDValue N, SelectionDAGISel &SDISel) {
1951 int64_t Val = MatcherTable[MatcherIndex++];
1953 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1955 if (N->getOpcode() != ISD::OR) return false;
1957 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1958 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1961 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1962 /// scope, evaluate the current node. If the current predicate is known to
1963 /// fail, set Result=true and return anything. If the current predicate is
1964 /// known to pass, set Result=false and return the MatcherIndex to continue
1965 /// with. If the current predicate is unknown, set Result=false and return the
1966 /// MatcherIndex to continue with.
1967 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1968 unsigned Index, SDValue N,
1969 bool &Result, SelectionDAGISel &SDISel,
1970 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1971 switch (Table[Index++]) {
1974 return Index-1; // Could not evaluate this predicate.
1975 case SelectionDAGISel::OPC_CheckSame:
1976 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1978 case SelectionDAGISel::OPC_CheckPatternPredicate:
1979 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1981 case SelectionDAGISel::OPC_CheckPredicate:
1982 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1984 case SelectionDAGISel::OPC_CheckOpcode:
1985 Result = !::CheckOpcode(Table, Index, N.getNode());
1987 case SelectionDAGISel::OPC_CheckType:
1988 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1990 case SelectionDAGISel::OPC_CheckChild0Type:
1991 case SelectionDAGISel::OPC_CheckChild1Type:
1992 case SelectionDAGISel::OPC_CheckChild2Type:
1993 case SelectionDAGISel::OPC_CheckChild3Type:
1994 case SelectionDAGISel::OPC_CheckChild4Type:
1995 case SelectionDAGISel::OPC_CheckChild5Type:
1996 case SelectionDAGISel::OPC_CheckChild6Type:
1997 case SelectionDAGISel::OPC_CheckChild7Type:
1998 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1999 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2001 case SelectionDAGISel::OPC_CheckCondCode:
2002 Result = !::CheckCondCode(Table, Index, N);
2004 case SelectionDAGISel::OPC_CheckValueType:
2005 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2007 case SelectionDAGISel::OPC_CheckInteger:
2008 Result = !::CheckInteger(Table, Index, N);
2010 case SelectionDAGISel::OPC_CheckAndImm:
2011 Result = !::CheckAndImm(Table, Index, N, SDISel);
2013 case SelectionDAGISel::OPC_CheckOrImm:
2014 Result = !::CheckOrImm(Table, Index, N, SDISel);
2022 /// FailIndex - If this match fails, this is the index to continue with.
2025 /// NodeStack - The node stack when the scope was formed.
2026 SmallVector<SDValue, 4> NodeStack;
2028 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2029 unsigned NumRecordedNodes;
2031 /// NumMatchedMemRefs - The number of matched memref entries.
2032 unsigned NumMatchedMemRefs;
2034 /// InputChain/InputGlue - The current chain/glue
2035 SDValue InputChain, InputGlue;
2037 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2038 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2043 SDNode *SelectionDAGISel::
2044 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2045 unsigned TableSize) {
2046 // FIXME: Should these even be selected? Handle these cases in the caller?
2047 switch (NodeToMatch->getOpcode()) {
2050 case ISD::EntryToken: // These nodes remain the same.
2051 case ISD::BasicBlock:
2053 //case ISD::VALUETYPE:
2054 //case ISD::CONDCODE:
2055 case ISD::HANDLENODE:
2056 case ISD::MDNODE_SDNODE:
2057 case ISD::TargetConstant:
2058 case ISD::TargetConstantFP:
2059 case ISD::TargetConstantPool:
2060 case ISD::TargetFrameIndex:
2061 case ISD::TargetExternalSymbol:
2062 case ISD::TargetBlockAddress:
2063 case ISD::TargetJumpTable:
2064 case ISD::TargetGlobalTLSAddress:
2065 case ISD::TargetGlobalAddress:
2066 case ISD::TokenFactor:
2067 case ISD::CopyFromReg:
2068 case ISD::CopyToReg:
2070 NodeToMatch->setNodeId(-1); // Mark selected.
2072 case ISD::AssertSext:
2073 case ISD::AssertZext:
2074 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2075 NodeToMatch->getOperand(0));
2077 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2078 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2081 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2083 // Set up the node stack with NodeToMatch as the only node on the stack.
2084 SmallVector<SDValue, 8> NodeStack;
2085 SDValue N = SDValue(NodeToMatch, 0);
2086 NodeStack.push_back(N);
2088 // MatchScopes - Scopes used when matching, if a match failure happens, this
2089 // indicates where to continue checking.
2090 SmallVector<MatchScope, 8> MatchScopes;
2092 // RecordedNodes - This is the set of nodes that have been recorded by the
2093 // state machine. The second value is the parent of the node, or null if the
2094 // root is recorded.
2095 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2097 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2099 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2101 // These are the current input chain and glue for use when generating nodes.
2102 // Various Emit operations change these. For example, emitting a copytoreg
2103 // uses and updates these.
2104 SDValue InputChain, InputGlue;
2106 // ChainNodesMatched - If a pattern matches nodes that have input/output
2107 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2108 // which ones they are. The result is captured into this list so that we can
2109 // update the chain results when the pattern is complete.
2110 SmallVector<SDNode*, 3> ChainNodesMatched;
2111 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2113 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2114 NodeToMatch->dump(CurDAG);
2117 // Determine where to start the interpreter. Normally we start at opcode #0,
2118 // but if the state machine starts with an OPC_SwitchOpcode, then we
2119 // accelerate the first lookup (which is guaranteed to be hot) with the
2120 // OpcodeOffset table.
2121 unsigned MatcherIndex = 0;
2123 if (!OpcodeOffset.empty()) {
2124 // Already computed the OpcodeOffset table, just index into it.
2125 if (N.getOpcode() < OpcodeOffset.size())
2126 MatcherIndex = OpcodeOffset[N.getOpcode()];
2127 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2129 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2130 // Otherwise, the table isn't computed, but the state machine does start
2131 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2132 // is the first time we're selecting an instruction.
2135 // Get the size of this case.
2136 unsigned CaseSize = MatcherTable[Idx++];
2138 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2139 if (CaseSize == 0) break;
2141 // Get the opcode, add the index to the table.
2142 uint16_t Opc = MatcherTable[Idx++];
2143 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2144 if (Opc >= OpcodeOffset.size())
2145 OpcodeOffset.resize((Opc+1)*2);
2146 OpcodeOffset[Opc] = Idx;
2150 // Okay, do the lookup for the first opcode.
2151 if (N.getOpcode() < OpcodeOffset.size())
2152 MatcherIndex = OpcodeOffset[N.getOpcode()];
2156 assert(MatcherIndex < TableSize && "Invalid index");
2158 unsigned CurrentOpcodeIndex = MatcherIndex;
2160 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2163 // Okay, the semantics of this operation are that we should push a scope
2164 // then evaluate the first child. However, pushing a scope only to have
2165 // the first check fail (which then pops it) is inefficient. If we can
2166 // determine immediately that the first check (or first several) will
2167 // immediately fail, don't even bother pushing a scope for them.
2171 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2172 if (NumToSkip & 128)
2173 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2174 // Found the end of the scope with no match.
2175 if (NumToSkip == 0) {
2180 FailIndex = MatcherIndex+NumToSkip;
2182 unsigned MatcherIndexOfPredicate = MatcherIndex;
2183 (void)MatcherIndexOfPredicate; // silence warning.
2185 // If we can't evaluate this predicate without pushing a scope (e.g. if
2186 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2187 // push the scope and evaluate the full predicate chain.
2189 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2190 Result, *this, RecordedNodes);
2194 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2195 << "index " << MatcherIndexOfPredicate
2196 << ", continuing at " << FailIndex << "\n");
2197 ++NumDAGIselRetries;
2199 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2200 // move to the next case.
2201 MatcherIndex = FailIndex;
2204 // If the whole scope failed to match, bail.
2205 if (FailIndex == 0) break;
2207 // Push a MatchScope which indicates where to go if the first child fails
2209 MatchScope NewEntry;
2210 NewEntry.FailIndex = FailIndex;
2211 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2212 NewEntry.NumRecordedNodes = RecordedNodes.size();
2213 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2214 NewEntry.InputChain = InputChain;
2215 NewEntry.InputGlue = InputGlue;
2216 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2217 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2218 MatchScopes.push_back(NewEntry);
2221 case OPC_RecordNode: {
2222 // Remember this node, it may end up being an operand in the pattern.
2224 if (NodeStack.size() > 1)
2225 Parent = NodeStack[NodeStack.size()-2].getNode();
2226 RecordedNodes.push_back(std::make_pair(N, Parent));
2230 case OPC_RecordChild0: case OPC_RecordChild1:
2231 case OPC_RecordChild2: case OPC_RecordChild3:
2232 case OPC_RecordChild4: case OPC_RecordChild5:
2233 case OPC_RecordChild6: case OPC_RecordChild7: {
2234 unsigned ChildNo = Opcode-OPC_RecordChild0;
2235 if (ChildNo >= N.getNumOperands())
2236 break; // Match fails if out of range child #.
2238 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2242 case OPC_RecordMemRef:
2243 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2246 case OPC_CaptureGlueInput:
2247 // If the current node has an input glue, capture it in InputGlue.
2248 if (N->getNumOperands() != 0 &&
2249 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2250 InputGlue = N->getOperand(N->getNumOperands()-1);
2253 case OPC_MoveChild: {
2254 unsigned ChildNo = MatcherTable[MatcherIndex++];
2255 if (ChildNo >= N.getNumOperands())
2256 break; // Match fails if out of range child #.
2257 N = N.getOperand(ChildNo);
2258 NodeStack.push_back(N);
2262 case OPC_MoveParent:
2263 // Pop the current node off the NodeStack.
2264 NodeStack.pop_back();
2265 assert(!NodeStack.empty() && "Node stack imbalance!");
2266 N = NodeStack.back();
2270 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2272 case OPC_CheckPatternPredicate:
2273 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2275 case OPC_CheckPredicate:
2276 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2280 case OPC_CheckComplexPat: {
2281 unsigned CPNum = MatcherTable[MatcherIndex++];
2282 unsigned RecNo = MatcherTable[MatcherIndex++];
2283 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2284 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2285 RecordedNodes[RecNo].first, CPNum,
2290 case OPC_CheckOpcode:
2291 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2295 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2298 case OPC_SwitchOpcode: {
2299 unsigned CurNodeOpcode = N.getOpcode();
2300 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2303 // Get the size of this case.
2304 CaseSize = MatcherTable[MatcherIndex++];
2306 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2307 if (CaseSize == 0) break;
2309 uint16_t Opc = MatcherTable[MatcherIndex++];
2310 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2312 // If the opcode matches, then we will execute this case.
2313 if (CurNodeOpcode == Opc)
2316 // Otherwise, skip over this case.
2317 MatcherIndex += CaseSize;
2320 // If no cases matched, bail out.
2321 if (CaseSize == 0) break;
2323 // Otherwise, execute the case we found.
2324 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2325 << " to " << MatcherIndex << "\n");
2329 case OPC_SwitchType: {
2330 MVT CurNodeVT = N.getValueType().getSimpleVT();
2331 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2334 // Get the size of this case.
2335 CaseSize = MatcherTable[MatcherIndex++];
2337 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2338 if (CaseSize == 0) break;
2340 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2341 if (CaseVT == MVT::iPTR)
2342 CaseVT = TLI.getPointerTy();
2344 // If the VT matches, then we will execute this case.
2345 if (CurNodeVT == CaseVT)
2348 // Otherwise, skip over this case.
2349 MatcherIndex += CaseSize;
2352 // If no cases matched, bail out.
2353 if (CaseSize == 0) break;
2355 // Otherwise, execute the case we found.
2356 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2357 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2360 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2361 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2362 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2363 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2364 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2365 Opcode-OPC_CheckChild0Type))
2368 case OPC_CheckCondCode:
2369 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2371 case OPC_CheckValueType:
2372 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2374 case OPC_CheckInteger:
2375 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2377 case OPC_CheckAndImm:
2378 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2380 case OPC_CheckOrImm:
2381 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2384 case OPC_CheckFoldableChainNode: {
2385 assert(NodeStack.size() != 1 && "No parent node");
2386 // Verify that all intermediate nodes between the root and this one have
2388 bool HasMultipleUses = false;
2389 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2390 if (!NodeStack[i].hasOneUse()) {
2391 HasMultipleUses = true;
2394 if (HasMultipleUses) break;
2396 // Check to see that the target thinks this is profitable to fold and that
2397 // we can fold it without inducing cycles in the graph.
2398 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2400 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2401 NodeToMatch, OptLevel,
2402 true/*We validate our own chains*/))
2407 case OPC_EmitInteger: {
2408 MVT::SimpleValueType VT =
2409 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2410 int64_t Val = MatcherTable[MatcherIndex++];
2412 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2413 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2414 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2417 case OPC_EmitRegister: {
2418 MVT::SimpleValueType VT =
2419 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2420 unsigned RegNo = MatcherTable[MatcherIndex++];
2421 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2422 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2425 case OPC_EmitRegister2: {
2426 // For targets w/ more than 256 register names, the register enum
2427 // values are stored in two bytes in the matcher table (just like
2429 MVT::SimpleValueType VT =
2430 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2431 unsigned RegNo = MatcherTable[MatcherIndex++];
2432 RegNo |= MatcherTable[MatcherIndex++] << 8;
2433 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2434 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2438 case OPC_EmitConvertToTarget: {
2439 // Convert from IMM/FPIMM to target version.
2440 unsigned RecNo = MatcherTable[MatcherIndex++];
2441 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2442 SDValue Imm = RecordedNodes[RecNo].first;
2444 if (Imm->getOpcode() == ISD::Constant) {
2445 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2446 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2447 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2448 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2449 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2452 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2456 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2457 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2458 // These are space-optimized forms of OPC_EmitMergeInputChains.
2459 assert(InputChain.getNode() == 0 &&
2460 "EmitMergeInputChains should be the first chain producing node");
2461 assert(ChainNodesMatched.empty() &&
2462 "Should only have one EmitMergeInputChains per match");
2464 // Read all of the chained nodes.
2465 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2466 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2467 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2469 // FIXME: What if other value results of the node have uses not matched
2471 if (ChainNodesMatched.back() != NodeToMatch &&
2472 !RecordedNodes[RecNo].first.hasOneUse()) {
2473 ChainNodesMatched.clear();
2477 // Merge the input chains if they are not intra-pattern references.
2478 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2480 if (InputChain.getNode() == 0)
2481 break; // Failed to merge.
2485 case OPC_EmitMergeInputChains: {
2486 assert(InputChain.getNode() == 0 &&
2487 "EmitMergeInputChains should be the first chain producing node");
2488 // This node gets a list of nodes we matched in the input that have
2489 // chains. We want to token factor all of the input chains to these nodes
2490 // together. However, if any of the input chains is actually one of the
2491 // nodes matched in this pattern, then we have an intra-match reference.
2492 // Ignore these because the newly token factored chain should not refer to
2494 unsigned NumChains = MatcherTable[MatcherIndex++];
2495 assert(NumChains != 0 && "Can't TF zero chains");
2497 assert(ChainNodesMatched.empty() &&
2498 "Should only have one EmitMergeInputChains per match");
2500 // Read all of the chained nodes.
2501 for (unsigned i = 0; i != NumChains; ++i) {
2502 unsigned RecNo = MatcherTable[MatcherIndex++];
2503 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2504 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2506 // FIXME: What if other value results of the node have uses not matched
2508 if (ChainNodesMatched.back() != NodeToMatch &&
2509 !RecordedNodes[RecNo].first.hasOneUse()) {
2510 ChainNodesMatched.clear();
2515 // If the inner loop broke out, the match fails.
2516 if (ChainNodesMatched.empty())
2519 // Merge the input chains if they are not intra-pattern references.
2520 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2522 if (InputChain.getNode() == 0)
2523 break; // Failed to merge.
2528 case OPC_EmitCopyToReg: {
2529 unsigned RecNo = MatcherTable[MatcherIndex++];
2530 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2531 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2533 if (InputChain.getNode() == 0)
2534 InputChain = CurDAG->getEntryNode();
2536 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2537 DestPhysReg, RecordedNodes[RecNo].first,
2540 InputGlue = InputChain.getValue(1);
2544 case OPC_EmitNodeXForm: {
2545 unsigned XFormNo = MatcherTable[MatcherIndex++];
2546 unsigned RecNo = MatcherTable[MatcherIndex++];
2547 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2548 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2549 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2554 case OPC_MorphNodeTo: {
2555 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2556 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2557 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2558 // Get the result VT list.
2559 unsigned NumVTs = MatcherTable[MatcherIndex++];
2560 SmallVector<EVT, 4> VTs;
2561 for (unsigned i = 0; i != NumVTs; ++i) {
2562 MVT::SimpleValueType VT =
2563 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2564 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2568 if (EmitNodeInfo & OPFL_Chain)
2569 VTs.push_back(MVT::Other);
2570 if (EmitNodeInfo & OPFL_GlueOutput)
2571 VTs.push_back(MVT::Glue);
2573 // This is hot code, so optimize the two most common cases of 1 and 2
2576 if (VTs.size() == 1)
2577 VTList = CurDAG->getVTList(VTs[0]);
2578 else if (VTs.size() == 2)
2579 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2581 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2583 // Get the operand list.
2584 unsigned NumOps = MatcherTable[MatcherIndex++];
2585 SmallVector<SDValue, 8> Ops;
2586 for (unsigned i = 0; i != NumOps; ++i) {
2587 unsigned RecNo = MatcherTable[MatcherIndex++];
2589 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2591 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2592 Ops.push_back(RecordedNodes[RecNo].first);
2595 // If there are variadic operands to add, handle them now.
2596 if (EmitNodeInfo & OPFL_VariadicInfo) {
2597 // Determine the start index to copy from.
2598 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2599 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2600 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2601 "Invalid variadic node");
2602 // Copy all of the variadic operands, not including a potential glue
2604 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2606 SDValue V = NodeToMatch->getOperand(i);
2607 if (V.getValueType() == MVT::Glue) break;
2612 // If this has chain/glue inputs, add them.
2613 if (EmitNodeInfo & OPFL_Chain)
2614 Ops.push_back(InputChain);
2615 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2616 Ops.push_back(InputGlue);
2620 if (Opcode != OPC_MorphNodeTo) {
2621 // If this is a normal EmitNode command, just create the new node and
2622 // add the results to the RecordedNodes list.
2623 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2624 VTList, Ops.data(), Ops.size());
2626 // Add all the non-glue/non-chain results to the RecordedNodes list.
2627 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2628 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2629 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2634 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2638 // If the node had chain/glue results, update our notion of the current
2640 if (EmitNodeInfo & OPFL_GlueOutput) {
2641 InputGlue = SDValue(Res, VTs.size()-1);
2642 if (EmitNodeInfo & OPFL_Chain)
2643 InputChain = SDValue(Res, VTs.size()-2);
2644 } else if (EmitNodeInfo & OPFL_Chain)
2645 InputChain = SDValue(Res, VTs.size()-1);
2647 // If the OPFL_MemRefs glue is set on this node, slap all of the
2648 // accumulated memrefs onto it.
2650 // FIXME: This is vastly incorrect for patterns with multiple outputs
2651 // instructions that access memory and for ComplexPatterns that match
2653 if (EmitNodeInfo & OPFL_MemRefs) {
2654 // Only attach load or store memory operands if the generated
2655 // instruction may load or store.
2656 const TargetInstrDesc &TID = TM.getInstrInfo()->get(TargetOpc);
2657 bool mayLoad = TID.mayLoad();
2658 bool mayStore = TID.mayStore();
2660 unsigned NumMemRefs = 0;
2661 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2662 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2663 if ((*I)->isLoad()) {
2666 } else if ((*I)->isStore()) {
2674 MachineSDNode::mmo_iterator MemRefs =
2675 MF->allocateMemRefsArray(NumMemRefs);
2677 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2678 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2679 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2680 if ((*I)->isLoad()) {
2683 } else if ((*I)->isStore()) {
2691 cast<MachineSDNode>(Res)
2692 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2696 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2697 << " node: "; Res->dump(CurDAG); errs() << "\n");
2699 // If this was a MorphNodeTo then we're completely done!
2700 if (Opcode == OPC_MorphNodeTo) {
2701 // Update chain and glue uses.
2702 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2703 InputGlue, GlueResultNodesMatched, true);
2710 case OPC_MarkGlueResults: {
2711 unsigned NumNodes = MatcherTable[MatcherIndex++];
2713 // Read and remember all the glue-result nodes.
2714 for (unsigned i = 0; i != NumNodes; ++i) {
2715 unsigned RecNo = MatcherTable[MatcherIndex++];
2717 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2719 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2720 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2725 case OPC_CompleteMatch: {
2726 // The match has been completed, and any new nodes (if any) have been
2727 // created. Patch up references to the matched dag to use the newly
2729 unsigned NumResults = MatcherTable[MatcherIndex++];
2731 for (unsigned i = 0; i != NumResults; ++i) {
2732 unsigned ResSlot = MatcherTable[MatcherIndex++];
2734 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2736 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2737 SDValue Res = RecordedNodes[ResSlot].first;
2739 assert(i < NodeToMatch->getNumValues() &&
2740 NodeToMatch->getValueType(i) != MVT::Other &&
2741 NodeToMatch->getValueType(i) != MVT::Glue &&
2742 "Invalid number of results to complete!");
2743 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2744 NodeToMatch->getValueType(i) == MVT::iPTR ||
2745 Res.getValueType() == MVT::iPTR ||
2746 NodeToMatch->getValueType(i).getSizeInBits() ==
2747 Res.getValueType().getSizeInBits()) &&
2748 "invalid replacement");
2749 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2752 // If the root node defines glue, add it to the glue nodes to update list.
2753 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2754 GlueResultNodesMatched.push_back(NodeToMatch);
2756 // Update chain and glue uses.
2757 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2758 InputGlue, GlueResultNodesMatched, false);
2760 assert(NodeToMatch->use_empty() &&
2761 "Didn't replace all uses of the node?");
2763 // FIXME: We just return here, which interacts correctly with SelectRoot
2764 // above. We should fix this to not return an SDNode* anymore.
2769 // If the code reached this point, then the match failed. See if there is
2770 // another child to try in the current 'Scope', otherwise pop it until we
2771 // find a case to check.
2772 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2773 ++NumDAGIselRetries;
2775 if (MatchScopes.empty()) {
2776 CannotYetSelect(NodeToMatch);
2780 // Restore the interpreter state back to the point where the scope was
2782 MatchScope &LastScope = MatchScopes.back();
2783 RecordedNodes.resize(LastScope.NumRecordedNodes);
2785 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2786 N = NodeStack.back();
2788 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2789 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2790 MatcherIndex = LastScope.FailIndex;
2792 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2794 InputChain = LastScope.InputChain;
2795 InputGlue = LastScope.InputGlue;
2796 if (!LastScope.HasChainNodesMatched)
2797 ChainNodesMatched.clear();
2798 if (!LastScope.HasGlueResultNodesMatched)
2799 GlueResultNodesMatched.clear();
2801 // Check to see what the offset is at the new MatcherIndex. If it is zero
2802 // we have reached the end of this scope, otherwise we have another child
2803 // in the current scope to try.
2804 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2805 if (NumToSkip & 128)
2806 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2808 // If we have another child in this scope to match, update FailIndex and
2810 if (NumToSkip != 0) {
2811 LastScope.FailIndex = MatcherIndex+NumToSkip;
2815 // End of this scope, pop it and try the next child in the containing
2817 MatchScopes.pop_back();
2824 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2826 raw_string_ostream Msg(msg);
2827 Msg << "Cannot select: ";
2829 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2830 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2831 N->getOpcode() != ISD::INTRINSIC_VOID) {
2832 N->printrFull(Msg, CurDAG);
2834 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2836 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2837 if (iid < Intrinsic::num_intrinsics)
2838 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2839 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2840 Msg << "target intrinsic %" << TII->getName(iid);
2842 Msg << "unknown intrinsic #" << iid;
2844 report_fatal_error(Msg.str());
2847 char SelectionDAGISel::ID = 0;