1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAGISel.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DebugInfo.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/Timer.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLibraryInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Target/TargetRegisterInfo.h"
57 #include "llvm/Target/TargetSubtargetInfo.h"
58 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
62 #define DEBUG_TYPE "isel"
64 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
65 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
66 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
67 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
68 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
69 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
70 STATISTIC(NumFastIselFailLowerArguments,
71 "Number of entry blocks where fast isel failed to lower arguments");
75 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
76 cl::desc("Enable extra verbose messages in the \"fast\" "
77 "instruction selector"));
80 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
81 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
82 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
83 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
84 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
85 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
86 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
88 // Standard binary operators...
89 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
90 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
91 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
92 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
93 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
94 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
95 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
96 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
97 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
98 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
99 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
100 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
102 // Logical operators...
103 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
104 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
105 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
107 // Memory instructions...
108 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
109 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
110 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
111 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
112 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
113 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
114 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
116 // Convert instructions...
117 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
118 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
119 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
120 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
121 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
122 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
123 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
124 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
125 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
126 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
127 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
128 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
130 // Other instructions...
131 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
132 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
133 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
134 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
135 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
136 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
137 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
138 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
139 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
140 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
141 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
142 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
143 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
144 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
145 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 // Intrinsic instructions...
148 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
149 STATISTIC(NumFastIselFailSAddWithOverflow,
150 "Fast isel fails on sadd.with.overflow");
151 STATISTIC(NumFastIselFailUAddWithOverflow,
152 "Fast isel fails on uadd.with.overflow");
153 STATISTIC(NumFastIselFailSSubWithOverflow,
154 "Fast isel fails on ssub.with.overflow");
155 STATISTIC(NumFastIselFailUSubWithOverflow,
156 "Fast isel fails on usub.with.overflow");
157 STATISTIC(NumFastIselFailSMulWithOverflow,
158 "Fast isel fails on smul.with.overflow");
159 STATISTIC(NumFastIselFailUMulWithOverflow,
160 "Fast isel fails on umul.with.overflow");
161 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
162 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
163 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
164 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
168 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
169 cl::desc("Enable verbose messages in the \"fast\" "
170 "instruction selector"));
172 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
173 cl::desc("Enable abort calls when \"fast\" instruction selection "
174 "fails to lower an instruction"));
176 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
177 cl::desc("Enable abort calls when \"fast\" instruction selection "
178 "fails to lower a formal argument"));
182 cl::desc("use Machine Branch Probability Info"),
183 cl::init(true), cl::Hidden);
186 static cl::opt<std::string>
187 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
188 cl::desc("Only display the basic block whose name "
189 "matches this for all view-*-dags options"));
191 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
192 cl::desc("Pop up a window to show dags before the first "
193 "dag combine pass"));
195 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before legalize types"));
198 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
199 cl::desc("Pop up a window to show dags before legalize"));
201 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
202 cl::desc("Pop up a window to show dags before the second "
203 "dag combine pass"));
205 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
206 cl::desc("Pop up a window to show dags before the post legalize types"
207 " dag combine pass"));
209 ViewISelDAGs("view-isel-dags", cl::Hidden,
210 cl::desc("Pop up a window to show isel dags as they are selected"));
212 ViewSchedDAGs("view-sched-dags", cl::Hidden,
213 cl::desc("Pop up a window to show sched dags as they are processed"));
215 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
216 cl::desc("Pop up a window to show SUnit dags after they are processed"));
218 static const bool ViewDAGCombine1 = false,
219 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
220 ViewDAGCombine2 = false,
221 ViewDAGCombineLT = false,
222 ViewISelDAGs = false, ViewSchedDAGs = false,
223 ViewSUnitDAGs = false;
226 //===---------------------------------------------------------------------===//
228 /// RegisterScheduler class - Track the registration of instruction schedulers.
230 //===---------------------------------------------------------------------===//
231 MachinePassRegistry RegisterScheduler::Registry;
233 //===---------------------------------------------------------------------===//
235 /// ISHeuristic command line option for instruction schedulers.
237 //===---------------------------------------------------------------------===//
238 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
239 RegisterPassParser<RegisterScheduler> >
240 ISHeuristic("pre-RA-sched",
241 cl::init(&createDefaultScheduler), cl::Hidden,
242 cl::desc("Instruction schedulers available (before register"
245 static RegisterScheduler
246 defaultListDAGScheduler("default", "Best scheduler for the target",
247 createDefaultScheduler);
250 //===--------------------------------------------------------------------===//
251 /// \brief This class is used by SelectionDAGISel to temporarily override
252 /// the optimization level on a per-function basis.
253 class OptLevelChanger {
254 SelectionDAGISel &IS;
255 CodeGenOpt::Level SavedOptLevel;
259 OptLevelChanger(SelectionDAGISel &ISel,
260 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
261 SavedOptLevel = IS.OptLevel;
262 if (NewOptLevel == SavedOptLevel)
264 IS.OptLevel = NewOptLevel;
265 IS.TM.setOptLevel(NewOptLevel);
266 SavedFastISel = IS.TM.Options.EnableFastISel;
267 if (NewOptLevel == CodeGenOpt::None)
268 IS.TM.setFastISel(true);
269 DEBUG(dbgs() << "\nChanging optimization level for Function "
270 << IS.MF->getFunction()->getName() << "\n");
271 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
272 << " ; After: -O" << NewOptLevel << "\n");
276 if (IS.OptLevel == SavedOptLevel)
278 DEBUG(dbgs() << "\nRestoring optimization level for Function "
279 << IS.MF->getFunction()->getName() << "\n");
280 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
281 << " ; After: -O" << SavedOptLevel << "\n");
282 IS.OptLevel = SavedOptLevel;
283 IS.TM.setOptLevel(SavedOptLevel);
284 IS.TM.setFastISel(SavedFastISel);
288 //===--------------------------------------------------------------------===//
289 /// createDefaultScheduler - This creates an instruction scheduler appropriate
291 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
292 CodeGenOpt::Level OptLevel) {
293 const TargetLowering *TLI = IS->TLI;
294 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
296 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
297 TLI->getSchedulingPreference() == Sched::Source)
298 return createSourceListDAGScheduler(IS, OptLevel);
299 if (TLI->getSchedulingPreference() == Sched::RegPressure)
300 return createBURRListDAGScheduler(IS, OptLevel);
301 if (TLI->getSchedulingPreference() == Sched::Hybrid)
302 return createHybridListDAGScheduler(IS, OptLevel);
303 if (TLI->getSchedulingPreference() == Sched::VLIW)
304 return createVLIWDAGScheduler(IS, OptLevel);
305 assert(TLI->getSchedulingPreference() == Sched::ILP &&
306 "Unknown sched type!");
307 return createILPListDAGScheduler(IS, OptLevel);
311 // EmitInstrWithCustomInserter - This method should be implemented by targets
312 // that mark instructions with the 'usesCustomInserter' flag. These
313 // instructions are special in various ways, which require special support to
314 // insert. The specified MachineInstr is created but not inserted into any
315 // basic blocks, and this method is called to expand it into a sequence of
316 // instructions, potentially also creating new basic blocks and control flow.
317 // When new basic blocks are inserted and the edges from MBB to its successors
318 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
321 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
322 MachineBasicBlock *MBB) const {
324 dbgs() << "If a target marks an instruction with "
325 "'usesCustomInserter', it must implement "
326 "TargetLowering::EmitInstrWithCustomInserter!";
328 llvm_unreachable(nullptr);
331 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
332 SDNode *Node) const {
333 assert(!MI->hasPostISelHook() &&
334 "If a target marks an instruction with 'hasPostISelHook', "
335 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
338 //===----------------------------------------------------------------------===//
339 // SelectionDAGISel code
340 //===----------------------------------------------------------------------===//
342 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
343 CodeGenOpt::Level OL) :
344 MachineFunctionPass(ID), TM(tm),
345 FuncInfo(new FunctionLoweringInfo()),
346 CurDAG(new SelectionDAG(tm, OL)),
347 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
351 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
352 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
353 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
354 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
357 SelectionDAGISel::~SelectionDAGISel() {
363 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
364 AU.addRequired<AliasAnalysis>();
365 AU.addPreserved<AliasAnalysis>();
366 AU.addRequired<GCModuleInfo>();
367 AU.addPreserved<GCModuleInfo>();
368 AU.addRequired<TargetLibraryInfo>();
369 if (UseMBPI && OptLevel != CodeGenOpt::None)
370 AU.addRequired<BranchProbabilityInfo>();
371 MachineFunctionPass::getAnalysisUsage(AU);
374 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
375 /// may trap on it. In this case we have to split the edge so that the path
376 /// through the predecessor block that doesn't go to the phi block doesn't
377 /// execute the possibly trapping instruction.
379 /// This is required for correctness, so it must be done at -O0.
381 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
382 // Loop for blocks with phi nodes.
383 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
384 PHINode *PN = dyn_cast<PHINode>(BB->begin());
388 // For each block with a PHI node, check to see if any of the input values
389 // are potentially trapping constant expressions. Constant expressions are
390 // the only potentially trapping value that can occur as the argument to a
392 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
393 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
394 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
395 if (!CE || !CE->canTrap()) continue;
397 // The only case we have to worry about is when the edge is critical.
398 // Since this block has a PHI Node, we assume it has multiple input
399 // edges: check to see if the pred has multiple successors.
400 BasicBlock *Pred = PN->getIncomingBlock(i);
401 if (Pred->getTerminator()->getNumSuccessors() == 1)
404 // Okay, we have to split this edge.
405 SplitCriticalEdge(Pred->getTerminator(),
406 GetSuccessorNumber(Pred, BB), SDISel, true);
412 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
413 // Do some sanity-checking on the command-line options.
414 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
415 "-fast-isel-verbose requires -fast-isel");
416 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
417 "-fast-isel-abort requires -fast-isel");
419 const Function &Fn = *mf.getFunction();
422 // Reset the target options before resetting the optimization
424 // FIXME: This is a horrible hack and should be processed via
425 // codegen looking at the optimization level explicitly when
426 // it wants to look at it.
427 TM.resetTargetOptions(Fn);
428 // Reset OptLevel to None for optnone functions.
429 CodeGenOpt::Level NewOptLevel = OptLevel;
430 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
431 NewOptLevel = CodeGenOpt::None;
432 OptLevelChanger OLC(*this, NewOptLevel);
434 TII = MF->getSubtarget().getInstrInfo();
435 TLI = MF->getSubtarget().getTargetLowering();
436 RegInfo = &MF->getRegInfo();
437 AA = &getAnalysis<AliasAnalysis>();
438 LibInfo = &getAnalysis<TargetLibraryInfo>();
439 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
441 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
443 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
446 FuncInfo->set(Fn, *MF, CurDAG);
448 if (UseMBPI && OptLevel != CodeGenOpt::None)
449 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
451 FuncInfo->BPI = nullptr;
453 SDB->init(GFI, *AA, LibInfo);
455 MF->setHasInlineAsm(false);
457 SelectAllBasicBlocks(Fn);
459 // If the first basic block in the function has live ins that need to be
460 // copied into vregs, emit the copies into the top of the block before
461 // emitting the code for the block.
462 MachineBasicBlock *EntryMBB = MF->begin();
463 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
464 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
466 DenseMap<unsigned, unsigned> LiveInMap;
467 if (!FuncInfo->ArgDbgValues.empty())
468 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
469 E = RegInfo->livein_end(); LI != E; ++LI)
471 LiveInMap.insert(std::make_pair(LI->first, LI->second));
473 // Insert DBG_VALUE instructions for function arguments to the entry block.
474 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
475 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
476 bool hasFI = MI->getOperand(0).isFI();
478 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
479 if (TargetRegisterInfo::isPhysicalRegister(Reg))
480 EntryMBB->insert(EntryMBB->begin(), MI);
482 MachineInstr *Def = RegInfo->getVRegDef(Reg);
484 MachineBasicBlock::iterator InsertPos = Def;
485 // FIXME: VR def may not be in entry block.
486 Def->getParent()->insert(std::next(InsertPos), MI);
488 DEBUG(dbgs() << "Dropping debug info for dead vreg"
489 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
492 // If Reg is live-in then update debug info to track its copy in a vreg.
493 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
494 if (LDI != LiveInMap.end()) {
495 assert(!hasFI && "There's no handling of frame pointer updating here yet "
497 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
498 MachineBasicBlock::iterator InsertPos = Def;
499 const MDNode *Variable = MI->getDebugVariable();
500 const MDNode *Expr = MI->getDebugExpression();
501 bool IsIndirect = MI->isIndirectDebugValue();
502 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
503 // Def is never a terminator here, so it is ok to increment InsertPos.
504 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
505 TII->get(TargetOpcode::DBG_VALUE), IsIndirect, LDI->second, Offset,
508 // If this vreg is directly copied into an exported register then
509 // that COPY instructions also need DBG_VALUE, if it is the only
510 // user of LDI->second.
511 MachineInstr *CopyUseMI = nullptr;
512 for (MachineRegisterInfo::use_instr_iterator
513 UI = RegInfo->use_instr_begin(LDI->second),
514 E = RegInfo->use_instr_end(); UI != E; ) {
515 MachineInstr *UseMI = &*(UI++);
516 if (UseMI->isDebugValue()) continue;
517 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
518 CopyUseMI = UseMI; continue;
520 // Otherwise this is another use or second copy use.
521 CopyUseMI = nullptr; break;
524 MachineInstr *NewMI =
525 BuildMI(*MF, CopyUseMI->getDebugLoc(),
526 TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
527 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
528 MachineBasicBlock::iterator Pos = CopyUseMI;
529 EntryMBB->insertAfter(Pos, NewMI);
534 // Determine if there are any calls in this machine function.
535 MachineFrameInfo *MFI = MF->getFrameInfo();
536 for (const auto &MBB : *MF) {
537 if (MFI->hasCalls() && MF->hasInlineAsm())
540 for (const auto &MI : MBB) {
541 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
542 if ((MCID.isCall() && !MCID.isReturn()) ||
543 MI.isStackAligningInlineAsm()) {
544 MFI->setHasCalls(true);
546 if (MI.isInlineAsm()) {
547 MF->setHasInlineAsm(true);
552 // Determine if there is a call to setjmp in the machine function.
553 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
555 // Replace forward-declared registers with the registers containing
556 // the desired value.
557 MachineRegisterInfo &MRI = MF->getRegInfo();
558 for (DenseMap<unsigned, unsigned>::iterator
559 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
561 unsigned From = I->first;
562 unsigned To = I->second;
563 // If To is also scheduled to be replaced, find what its ultimate
566 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
570 // Make sure the new register has a sufficiently constrained register class.
571 if (TargetRegisterInfo::isVirtualRegister(From) &&
572 TargetRegisterInfo::isVirtualRegister(To))
573 MRI.constrainRegClass(To, MRI.getRegClass(From));
575 MRI.replaceRegWith(From, To);
578 // Freeze the set of reserved registers now that MachineFrameInfo has been
579 // set up. All the information required by getReservedRegs() should be
581 MRI.freezeReservedRegs(*MF);
583 // Release function-specific state. SDB and CurDAG are already cleared
587 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
588 DEBUG(MF->print(dbgs()));
593 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
594 BasicBlock::const_iterator End,
596 // Lower all of the non-terminator instructions. If a call is emitted
597 // as a tail call, cease emitting nodes for this block. Terminators
598 // are handled below.
599 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
602 // Make sure the root of the DAG is up-to-date.
603 CurDAG->setRoot(SDB->getControlRoot());
604 HadTailCall = SDB->HasTailCall;
607 // Final step, emit the lowered DAG as machine code.
611 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
612 SmallPtrSet<SDNode*, 128> VisitedNodes;
613 SmallVector<SDNode*, 128> Worklist;
615 Worklist.push_back(CurDAG->getRoot().getNode());
621 SDNode *N = Worklist.pop_back_val();
623 // If we've already seen this node, ignore it.
624 if (!VisitedNodes.insert(N).second)
627 // Otherwise, add all chain operands to the worklist.
628 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
629 if (N->getOperand(i).getValueType() == MVT::Other)
630 Worklist.push_back(N->getOperand(i).getNode());
632 // If this is a CopyToReg with a vreg dest, process it.
633 if (N->getOpcode() != ISD::CopyToReg)
636 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
637 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
640 // Ignore non-scalar or non-integer values.
641 SDValue Src = N->getOperand(2);
642 EVT SrcVT = Src.getValueType();
643 if (!SrcVT.isInteger() || SrcVT.isVector())
646 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
647 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
648 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
649 } while (!Worklist.empty());
652 void SelectionDAGISel::CodeGenAndEmitDAG() {
653 std::string GroupName;
654 if (TimePassesIsEnabled)
655 GroupName = "Instruction Selection and Scheduling";
656 std::string BlockName;
657 int BlockNumber = -1;
659 bool MatchFilterBB = false; (void)MatchFilterBB;
661 MatchFilterBB = (!FilterDAGBasicBlockName.empty() &&
662 FilterDAGBasicBlockName ==
663 FuncInfo->MBB->getBasicBlock()->getName().str());
666 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
667 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
671 BlockNumber = FuncInfo->MBB->getNumber();
672 BlockName = MF->getName().str() + ":" +
673 FuncInfo->MBB->getBasicBlock()->getName().str();
675 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
676 << " '" << BlockName << "'\n"; CurDAG->dump());
678 if (ViewDAGCombine1 && MatchFilterBB)
679 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
681 // Run the DAG combiner in pre-legalize mode.
683 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
684 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
687 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
688 << " '" << BlockName << "'\n"; CurDAG->dump());
690 // Second step, hack on the DAG until it only uses operations and types that
691 // the target supports.
692 if (ViewLegalizeTypesDAGs && MatchFilterBB)
693 CurDAG->viewGraph("legalize-types input for " + BlockName);
697 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
698 Changed = CurDAG->LegalizeTypes();
701 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
702 << " '" << BlockName << "'\n"; CurDAG->dump());
704 CurDAG->NewNodesMustHaveLegalTypes = true;
707 if (ViewDAGCombineLT && MatchFilterBB)
708 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
710 // Run the DAG combiner in post-type-legalize mode.
712 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
713 TimePassesIsEnabled);
714 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
717 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
718 << " '" << BlockName << "'\n"; CurDAG->dump());
723 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
724 Changed = CurDAG->LegalizeVectors();
729 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
730 CurDAG->LegalizeTypes();
733 if (ViewDAGCombineLT && MatchFilterBB)
734 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
736 // Run the DAG combiner in post-type-legalize mode.
738 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
739 TimePassesIsEnabled);
740 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
743 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
744 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
747 if (ViewLegalizeDAGs && MatchFilterBB)
748 CurDAG->viewGraph("legalize input for " + BlockName);
751 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
755 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
756 << " '" << BlockName << "'\n"; CurDAG->dump());
758 if (ViewDAGCombine2 && MatchFilterBB)
759 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
761 // Run the DAG combiner in post-legalize mode.
763 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
764 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
767 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
768 << " '" << BlockName << "'\n"; CurDAG->dump());
770 if (OptLevel != CodeGenOpt::None)
771 ComputeLiveOutVRegInfo();
773 if (ViewISelDAGs && MatchFilterBB)
774 CurDAG->viewGraph("isel input for " + BlockName);
776 // Third, instruction select all of the operations to machine code, adding the
777 // code to the MachineBasicBlock.
779 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
780 DoInstructionSelection();
783 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
784 << " '" << BlockName << "'\n"; CurDAG->dump());
786 if (ViewSchedDAGs && MatchFilterBB)
787 CurDAG->viewGraph("scheduler input for " + BlockName);
789 // Schedule machine code.
790 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
792 NamedRegionTimer T("Instruction Scheduling", GroupName,
793 TimePassesIsEnabled);
794 Scheduler->Run(CurDAG, FuncInfo->MBB);
797 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
799 // Emit machine code to BB. This can change 'BB' to the last block being
801 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
803 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
805 // FuncInfo->InsertPt is passed by reference and set to the end of the
806 // scheduled instructions.
807 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
810 // If the block was split, make sure we update any references that are used to
811 // update PHI nodes later on.
812 if (FirstMBB != LastMBB)
813 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
815 // Free the scheduler state.
817 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
818 TimePassesIsEnabled);
822 // Free the SelectionDAG state, now that we're finished with it.
827 /// ISelUpdater - helper class to handle updates of the instruction selection
829 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
830 SelectionDAG::allnodes_iterator &ISelPosition;
832 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
833 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
835 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
836 /// deleted is the current ISelPosition node, update ISelPosition.
838 void NodeDeleted(SDNode *N, SDNode *E) override {
839 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
843 } // end anonymous namespace
845 void SelectionDAGISel::DoInstructionSelection() {
846 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
847 << FuncInfo->MBB->getNumber()
848 << " '" << FuncInfo->MBB->getName() << "'\n");
852 // Select target instructions for the DAG.
854 // Number all nodes with a topological order and set DAGSize.
855 DAGSize = CurDAG->AssignTopologicalOrder();
857 // Create a dummy node (which is not added to allnodes), that adds
858 // a reference to the root node, preventing it from being deleted,
859 // and tracking any changes of the root.
860 HandleSDNode Dummy(CurDAG->getRoot());
861 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
864 // Make sure that ISelPosition gets properly updated when nodes are deleted
865 // in calls made from this function.
866 ISelUpdater ISU(*CurDAG, ISelPosition);
868 // The AllNodes list is now topological-sorted. Visit the
869 // nodes by starting at the end of the list (the root of the
870 // graph) and preceding back toward the beginning (the entry
872 while (ISelPosition != CurDAG->allnodes_begin()) {
873 SDNode *Node = --ISelPosition;
874 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
875 // but there are currently some corner cases that it misses. Also, this
876 // makes it theoretically possible to disable the DAGCombiner.
877 if (Node->use_empty())
880 SDNode *ResNode = Select(Node);
882 // FIXME: This is pretty gross. 'Select' should be changed to not return
883 // anything at all and this code should be nuked with a tactical strike.
885 // If node should not be replaced, continue with the next one.
886 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
890 ReplaceUses(Node, ResNode);
893 // If after the replacement this node is not used any more,
894 // remove this dead node.
895 if (Node->use_empty()) // Don't delete EntryToken, etc.
896 CurDAG->RemoveDeadNode(Node);
899 CurDAG->setRoot(Dummy.getValue());
902 DEBUG(dbgs() << "===== Instruction selection ends:\n");
904 PostprocessISelDAG();
907 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
908 /// do other setup for EH landing-pad blocks.
909 void SelectionDAGISel::PrepareEHLandingPad() {
910 MachineBasicBlock *MBB = FuncInfo->MBB;
912 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
914 // Add a label to mark the beginning of the landing pad. Deletion of the
915 // landing pad can thus be detected via the MachineModuleInfo.
916 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
918 // Assign the call site to the landing pad's begin label.
919 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
921 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
922 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
925 if (TM.getMCAsmInfo()->getExceptionHandlingType() ==
926 ExceptionHandling::MSVC) {
927 // Make virtual registers and a series of labels that fill in values for the
929 auto &RI = MF->getRegInfo();
930 FuncInfo->ExceptionSelectorVirtReg = RI.createVirtualRegister(PtrRC);
932 // Get all invoke BBs that will unwind into the clause BBs.
933 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
936 // Emit separate machine basic blocks with separate labels for each clause
937 // before the main landing pad block.
938 const BasicBlock *LLVMBB = MBB->getBasicBlock();
939 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
940 MachineInstrBuilder SelectorPHI = BuildMI(
941 *MBB, MBB->begin(), SDB->getCurDebugLoc(), TII->get(TargetOpcode::PHI),
942 FuncInfo->ExceptionSelectorVirtReg);
943 for (unsigned I = 0, E = LPadInst->getNumClauses(); I != E; ++I) {
944 // Skip filter clauses, we can't implement them yet.
945 if (LPadInst->isFilter(I))
948 MachineBasicBlock *ClauseBB = MF->CreateMachineBasicBlock(LLVMBB);
949 MF->insert(MBB, ClauseBB);
951 // Add the edge from the invoke to the clause.
952 for (MachineBasicBlock *InvokeBB : InvokeBBs)
953 InvokeBB->addSuccessor(ClauseBB);
955 // Mark the clause as a landing pad or MI passes will delete it.
956 ClauseBB->setIsLandingPad();
958 GlobalValue *ClauseGV = ExtractTypeInfo(LPadInst->getClause(I));
960 // Start the BB with a label.
961 MCSymbol *ClauseLabel = MF->getMMI().addClauseForLandingPad(MBB);
962 BuildMI(*ClauseBB, ClauseBB->begin(), SDB->getCurDebugLoc(), II)
963 .addSym(ClauseLabel);
965 // Construct a simple BB that defines a register with the typeid constant.
966 FuncInfo->MBB = ClauseBB;
967 FuncInfo->InsertPt = ClauseBB->end();
968 unsigned VReg = SDB->visitLandingPadClauseBB(ClauseGV, MBB);
969 CurDAG->setRoot(SDB->getRoot());
973 // Add the typeid virtual register to the phi in the main landing pad.
974 SelectorPHI.addReg(VReg).addMBB(ClauseBB);
977 // Remove the edge from the invoke to the lpad.
978 for (MachineBasicBlock *InvokeBB : InvokeBBs)
979 InvokeBB->removeSuccessor(MBB);
981 // Restore FuncInfo back to its previous state and select the main landing
984 FuncInfo->InsertPt = MBB->end();
988 // Mark exception register as live in.
989 if (unsigned Reg = TLI->getExceptionPointerRegister())
990 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
992 // Mark exception selector register as live in.
993 if (unsigned Reg = TLI->getExceptionSelectorRegister())
994 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
997 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
998 /// side-effect free and is either dead or folded into a generated instruction.
999 /// Return false if it needs to be emitted.
1000 static bool isFoldedOrDeadInstruction(const Instruction *I,
1001 FunctionLoweringInfo *FuncInfo) {
1002 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
1003 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1004 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1005 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
1006 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1010 // Collect per Instruction statistics for fast-isel misses. Only those
1011 // instructions that cause the bail are accounted for. It does not account for
1012 // instructions higher in the block. Thus, summing the per instructions stats
1013 // will not add up to what is reported by NumFastIselFailures.
1014 static void collectFailStats(const Instruction *I) {
1015 switch (I->getOpcode()) {
1016 default: assert (0 && "<Invalid operator> ");
1019 case Instruction::Ret: NumFastIselFailRet++; return;
1020 case Instruction::Br: NumFastIselFailBr++; return;
1021 case Instruction::Switch: NumFastIselFailSwitch++; return;
1022 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1023 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1024 case Instruction::Resume: NumFastIselFailResume++; return;
1025 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1027 // Standard binary operators...
1028 case Instruction::Add: NumFastIselFailAdd++; return;
1029 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1030 case Instruction::Sub: NumFastIselFailSub++; return;
1031 case Instruction::FSub: NumFastIselFailFSub++; return;
1032 case Instruction::Mul: NumFastIselFailMul++; return;
1033 case Instruction::FMul: NumFastIselFailFMul++; return;
1034 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1035 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1036 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1037 case Instruction::URem: NumFastIselFailURem++; return;
1038 case Instruction::SRem: NumFastIselFailSRem++; return;
1039 case Instruction::FRem: NumFastIselFailFRem++; return;
1041 // Logical operators...
1042 case Instruction::And: NumFastIselFailAnd++; return;
1043 case Instruction::Or: NumFastIselFailOr++; return;
1044 case Instruction::Xor: NumFastIselFailXor++; return;
1046 // Memory instructions...
1047 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1048 case Instruction::Load: NumFastIselFailLoad++; return;
1049 case Instruction::Store: NumFastIselFailStore++; return;
1050 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1051 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1052 case Instruction::Fence: NumFastIselFailFence++; return;
1053 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1055 // Convert instructions...
1056 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1057 case Instruction::ZExt: NumFastIselFailZExt++; return;
1058 case Instruction::SExt: NumFastIselFailSExt++; return;
1059 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1060 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1061 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1062 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1063 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1064 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1065 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1066 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1067 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1069 // Other instructions...
1070 case Instruction::ICmp: NumFastIselFailICmp++; return;
1071 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1072 case Instruction::PHI: NumFastIselFailPHI++; return;
1073 case Instruction::Select: NumFastIselFailSelect++; return;
1074 case Instruction::Call: {
1075 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1076 switch (Intrinsic->getIntrinsicID()) {
1078 NumFastIselFailIntrinsicCall++; return;
1079 case Intrinsic::sadd_with_overflow:
1080 NumFastIselFailSAddWithOverflow++; return;
1081 case Intrinsic::uadd_with_overflow:
1082 NumFastIselFailUAddWithOverflow++; return;
1083 case Intrinsic::ssub_with_overflow:
1084 NumFastIselFailSSubWithOverflow++; return;
1085 case Intrinsic::usub_with_overflow:
1086 NumFastIselFailUSubWithOverflow++; return;
1087 case Intrinsic::smul_with_overflow:
1088 NumFastIselFailSMulWithOverflow++; return;
1089 case Intrinsic::umul_with_overflow:
1090 NumFastIselFailUMulWithOverflow++; return;
1091 case Intrinsic::frameaddress:
1092 NumFastIselFailFrameaddress++; return;
1093 case Intrinsic::sqrt:
1094 NumFastIselFailSqrt++; return;
1095 case Intrinsic::experimental_stackmap:
1096 NumFastIselFailStackMap++; return;
1097 case Intrinsic::experimental_patchpoint_void: // fall-through
1098 case Intrinsic::experimental_patchpoint_i64:
1099 NumFastIselFailPatchPoint++; return;
1102 NumFastIselFailCall++;
1105 case Instruction::Shl: NumFastIselFailShl++; return;
1106 case Instruction::LShr: NumFastIselFailLShr++; return;
1107 case Instruction::AShr: NumFastIselFailAShr++; return;
1108 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1109 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1110 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1111 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1112 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1113 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1114 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1119 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1120 // Initialize the Fast-ISel state, if needed.
1121 FastISel *FastIS = nullptr;
1122 if (TM.Options.EnableFastISel)
1123 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1125 // Iterate over all basic blocks in the function.
1126 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1127 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1128 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1129 const BasicBlock *LLVMBB = *I;
1131 if (OptLevel != CodeGenOpt::None) {
1132 bool AllPredsVisited = true;
1133 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1135 if (!FuncInfo->VisitedBBs.count(*PI)) {
1136 AllPredsVisited = false;
1141 if (AllPredsVisited) {
1142 for (BasicBlock::const_iterator I = LLVMBB->begin();
1143 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1144 FuncInfo->ComputePHILiveOutRegInfo(PN);
1146 for (BasicBlock::const_iterator I = LLVMBB->begin();
1147 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1148 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1151 FuncInfo->VisitedBBs.insert(LLVMBB);
1154 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1155 BasicBlock::const_iterator const End = LLVMBB->end();
1156 BasicBlock::const_iterator BI = End;
1158 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1159 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1161 // Setup an EH landing-pad block.
1162 FuncInfo->ExceptionPointerVirtReg = 0;
1163 FuncInfo->ExceptionSelectorVirtReg = 0;
1164 if (FuncInfo->MBB->isLandingPad())
1165 PrepareEHLandingPad();
1167 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1169 FastIS->startNewBlock();
1171 // Emit code for any incoming arguments. This must happen before
1172 // beginning FastISel on the entry block.
1173 if (LLVMBB == &Fn.getEntryBlock()) {
1176 // Lower any arguments needed in this block if this is the entry block.
1177 if (!FastIS->lowerArguments()) {
1178 // Fast isel failed to lower these arguments
1179 ++NumFastIselFailLowerArguments;
1180 if (EnableFastISelAbortArgs)
1181 llvm_unreachable("FastISel didn't lower all arguments");
1183 // Use SelectionDAG argument lowering
1185 CurDAG->setRoot(SDB->getControlRoot());
1187 CodeGenAndEmitDAG();
1190 // If we inserted any instructions at the beginning, make a note of
1191 // where they are, so we can be sure to emit subsequent instructions
1193 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1194 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1196 FastIS->setLastLocalValue(nullptr);
1199 unsigned NumFastIselRemaining = std::distance(Begin, End);
1200 // Do FastISel on as many instructions as possible.
1201 for (; BI != Begin; --BI) {
1202 const Instruction *Inst = std::prev(BI);
1204 // If we no longer require this instruction, skip it.
1205 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1206 --NumFastIselRemaining;
1210 // Bottom-up: reset the insert pos at the top, after any local-value
1212 FastIS->recomputeInsertPt();
1214 // Try to select the instruction with FastISel.
1215 if (FastIS->selectInstruction(Inst)) {
1216 --NumFastIselRemaining;
1217 ++NumFastIselSuccess;
1218 // If fast isel succeeded, skip over all the folded instructions, and
1219 // then see if there is a load right before the selected instructions.
1220 // Try to fold the load if so.
1221 const Instruction *BeforeInst = Inst;
1222 while (BeforeInst != Begin) {
1223 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1224 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1227 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1228 BeforeInst->hasOneUse() &&
1229 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1230 // If we succeeded, don't re-select the load.
1231 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1232 --NumFastIselRemaining;
1233 ++NumFastIselSuccess;
1239 if (EnableFastISelVerbose2)
1240 collectFailStats(Inst);
1243 // Then handle certain instructions as single-LLVM-Instruction blocks.
1244 if (isa<CallInst>(Inst)) {
1246 if (EnableFastISelVerbose || EnableFastISelAbort) {
1247 dbgs() << "FastISel missed call: ";
1251 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1252 unsigned &R = FuncInfo->ValueMap[Inst];
1254 R = FuncInfo->CreateRegs(Inst->getType());
1257 bool HadTailCall = false;
1258 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1259 SelectBasicBlock(Inst, BI, HadTailCall);
1261 // If the call was emitted as a tail call, we're done with the block.
1262 // We also need to delete any previously emitted instructions.
1264 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1269 // Recompute NumFastIselRemaining as Selection DAG instruction
1270 // selection may have handled the call, input args, etc.
1271 unsigned RemainingNow = std::distance(Begin, BI);
1272 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1273 NumFastIselRemaining = RemainingNow;
1277 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1278 // Don't abort, and use a different message for terminator misses.
1279 NumFastIselFailures += NumFastIselRemaining;
1280 if (EnableFastISelVerbose || EnableFastISelAbort) {
1281 dbgs() << "FastISel missed terminator: ";
1285 NumFastIselFailures += NumFastIselRemaining;
1286 if (EnableFastISelVerbose || EnableFastISelAbort) {
1287 dbgs() << "FastISel miss: ";
1290 if (EnableFastISelAbort)
1291 // The "fast" selector couldn't handle something and bailed.
1292 // For the purpose of debugging, just abort.
1293 llvm_unreachable("FastISel didn't select the entire block");
1298 FastIS->recomputeInsertPt();
1300 // Lower any arguments needed in this block if this is the entry block.
1301 if (LLVMBB == &Fn.getEntryBlock()) {
1310 ++NumFastIselBlocks;
1313 // Run SelectionDAG instruction selection on the remainder of the block
1314 // not handled by FastISel. If FastISel is not run, this is the entire
1317 SelectBasicBlock(Begin, BI, HadTailCall);
1321 FuncInfo->PHINodesToUpdate.clear();
1325 SDB->clearDanglingDebugInfo();
1326 SDB->SPDescriptor.resetPerFunctionState();
1329 /// Given that the input MI is before a partial terminator sequence TSeq, return
1330 /// true if M + TSeq also a partial terminator sequence.
1332 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1333 /// lowering copy vregs into physical registers, which are then passed into
1334 /// terminator instructors so we can satisfy ABI constraints. A partial
1335 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1336 /// may be the whole terminator sequence).
1337 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1338 // If we do not have a copy or an implicit def, we return true if and only if
1339 // MI is a debug value.
1340 if (!MI->isCopy() && !MI->isImplicitDef())
1341 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1342 // physical registers if there is debug info associated with the terminator
1343 // of our mbb. We want to include said debug info in our terminator
1344 // sequence, so we return true in that case.
1345 return MI->isDebugValue();
1347 // We have left the terminator sequence if we are not doing one of the
1350 // 1. Copying a vreg into a physical register.
1351 // 2. Copying a vreg into a vreg.
1352 // 3. Defining a register via an implicit def.
1354 // OPI should always be a register definition...
1355 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1356 if (!OPI->isReg() || !OPI->isDef())
1359 // Defining any register via an implicit def is always ok.
1360 if (MI->isImplicitDef())
1363 // Grab the copy source...
1364 MachineInstr::const_mop_iterator OPI2 = OPI;
1366 assert(OPI2 != MI->operands_end()
1367 && "Should have a copy implying we should have 2 arguments.");
1369 // Make sure that the copy dest is not a vreg when the copy source is a
1370 // physical register.
1371 if (!OPI2->isReg() ||
1372 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1373 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1379 /// Find the split point at which to splice the end of BB into its success stack
1380 /// protector check machine basic block.
1382 /// On many platforms, due to ABI constraints, terminators, even before register
1383 /// allocation, use physical registers. This creates an issue for us since
1384 /// physical registers at this point can not travel across basic
1385 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1386 /// when they enter functions and moves them through a sequence of copies back
1387 /// into the physical registers right before the terminator creating a
1388 /// ``Terminator Sequence''. This function is searching for the beginning of the
1389 /// terminator sequence so that we can ensure that we splice off not just the
1390 /// terminator, but additionally the copies that move the vregs into the
1391 /// physical registers.
1392 static MachineBasicBlock::iterator
1393 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1394 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1396 if (SplitPoint == BB->begin())
1399 MachineBasicBlock::iterator Start = BB->begin();
1400 MachineBasicBlock::iterator Previous = SplitPoint;
1403 while (MIIsInTerminatorSequence(Previous)) {
1404 SplitPoint = Previous;
1405 if (Previous == Start)
1414 SelectionDAGISel::FinishBasicBlock() {
1416 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1417 << FuncInfo->PHINodesToUpdate.size() << "\n";
1418 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1419 dbgs() << "Node " << i << " : ("
1420 << FuncInfo->PHINodesToUpdate[i].first
1421 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1423 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1424 SDB->JTCases.empty() &&
1425 SDB->BitTestCases.empty();
1427 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1428 // PHI nodes in successors.
1429 if (MustUpdatePHINodes) {
1430 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1431 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1432 assert(PHI->isPHI() &&
1433 "This is not a machine PHI node that we are updating!");
1434 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1436 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1440 // Handle stack protector.
1441 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1442 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1443 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1445 // Find the split point to split the parent mbb. At the same time copy all
1446 // physical registers used in the tail of parent mbb into virtual registers
1447 // before the split point and back into physical registers after the split
1448 // point. This prevents us needing to deal with Live-ins and many other
1449 // register allocation issues caused by us splitting the parent mbb. The
1450 // register allocator will clean up said virtual copies later on.
1451 MachineBasicBlock::iterator SplitPoint =
1452 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1454 // Splice the terminator of ParentMBB into SuccessMBB.
1455 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1459 // Add compare/jump on neq/jump to the parent BB.
1460 FuncInfo->MBB = ParentMBB;
1461 FuncInfo->InsertPt = ParentMBB->end();
1462 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1463 CurDAG->setRoot(SDB->getRoot());
1465 CodeGenAndEmitDAG();
1467 // CodeGen Failure MBB if we have not codegened it yet.
1468 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1469 if (!FailureMBB->size()) {
1470 FuncInfo->MBB = FailureMBB;
1471 FuncInfo->InsertPt = FailureMBB->end();
1472 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1473 CurDAG->setRoot(SDB->getRoot());
1475 CodeGenAndEmitDAG();
1478 // Clear the Per-BB State.
1479 SDB->SPDescriptor.resetPerBBState();
1482 // If we updated PHI Nodes, return early.
1483 if (MustUpdatePHINodes)
1486 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1487 // Lower header first, if it wasn't already lowered
1488 if (!SDB->BitTestCases[i].Emitted) {
1489 // Set the current basic block to the mbb we wish to insert the code into
1490 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1491 FuncInfo->InsertPt = FuncInfo->MBB->end();
1493 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1494 CurDAG->setRoot(SDB->getRoot());
1496 CodeGenAndEmitDAG();
1499 uint32_t UnhandledWeight = 0;
1500 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1501 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1503 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1504 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1505 // Set the current basic block to the mbb we wish to insert the code into
1506 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1507 FuncInfo->InsertPt = FuncInfo->MBB->end();
1510 SDB->visitBitTestCase(SDB->BitTestCases[i],
1511 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1513 SDB->BitTestCases[i].Reg,
1514 SDB->BitTestCases[i].Cases[j],
1517 SDB->visitBitTestCase(SDB->BitTestCases[i],
1518 SDB->BitTestCases[i].Default,
1520 SDB->BitTestCases[i].Reg,
1521 SDB->BitTestCases[i].Cases[j],
1525 CurDAG->setRoot(SDB->getRoot());
1527 CodeGenAndEmitDAG();
1531 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1533 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1534 MachineBasicBlock *PHIBB = PHI->getParent();
1535 assert(PHI->isPHI() &&
1536 "This is not a machine PHI node that we are updating!");
1537 // This is "default" BB. We have two jumps to it. From "header" BB and
1538 // from last "case" BB.
1539 if (PHIBB == SDB->BitTestCases[i].Default)
1540 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1541 .addMBB(SDB->BitTestCases[i].Parent)
1542 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1543 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1544 // One of "cases" BB.
1545 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1547 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1548 if (cBB->isSuccessor(PHIBB))
1549 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1553 SDB->BitTestCases.clear();
1555 // If the JumpTable record is filled in, then we need to emit a jump table.
1556 // Updating the PHI nodes is tricky in this case, since we need to determine
1557 // whether the PHI is a successor of the range check MBB or the jump table MBB
1558 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1559 // Lower header first, if it wasn't already lowered
1560 if (!SDB->JTCases[i].first.Emitted) {
1561 // Set the current basic block to the mbb we wish to insert the code into
1562 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1563 FuncInfo->InsertPt = FuncInfo->MBB->end();
1565 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1567 CurDAG->setRoot(SDB->getRoot());
1569 CodeGenAndEmitDAG();
1572 // Set the current basic block to the mbb we wish to insert the code into
1573 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1574 FuncInfo->InsertPt = FuncInfo->MBB->end();
1576 SDB->visitJumpTable(SDB->JTCases[i].second);
1577 CurDAG->setRoot(SDB->getRoot());
1579 CodeGenAndEmitDAG();
1582 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1584 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1585 MachineBasicBlock *PHIBB = PHI->getParent();
1586 assert(PHI->isPHI() &&
1587 "This is not a machine PHI node that we are updating!");
1588 // "default" BB. We can go there only from header BB.
1589 if (PHIBB == SDB->JTCases[i].second.Default)
1590 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1591 .addMBB(SDB->JTCases[i].first.HeaderBB);
1592 // JT BB. Just iterate over successors here
1593 if (FuncInfo->MBB->isSuccessor(PHIBB))
1594 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1597 SDB->JTCases.clear();
1599 // If the switch block involved a branch to one of the actual successors, we
1600 // need to update PHI nodes in that block.
1601 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1602 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1603 assert(PHI->isPHI() &&
1604 "This is not a machine PHI node that we are updating!");
1605 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1606 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1609 // If we generated any switch lowering information, build and codegen any
1610 // additional DAGs necessary.
1611 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1612 // Set the current basic block to the mbb we wish to insert the code into
1613 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1614 FuncInfo->InsertPt = FuncInfo->MBB->end();
1616 // Determine the unique successors.
1617 SmallVector<MachineBasicBlock *, 2> Succs;
1618 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1619 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1620 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1622 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1623 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1624 CurDAG->setRoot(SDB->getRoot());
1626 CodeGenAndEmitDAG();
1628 // Remember the last block, now that any splitting is done, for use in
1629 // populating PHI nodes in successors.
1630 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1632 // Handle any PHI nodes in successors of this chunk, as if we were coming
1633 // from the original BB before switch expansion. Note that PHI nodes can
1634 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1635 // handle them the right number of times.
1636 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1637 FuncInfo->MBB = Succs[i];
1638 FuncInfo->InsertPt = FuncInfo->MBB->end();
1639 // FuncInfo->MBB may have been removed from the CFG if a branch was
1641 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1642 for (MachineBasicBlock::iterator
1643 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1644 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1645 MachineInstrBuilder PHI(*MF, MBBI);
1646 // This value for this PHI node is recorded in PHINodesToUpdate.
1647 for (unsigned pn = 0; ; ++pn) {
1648 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1649 "Didn't find PHI entry!");
1650 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1651 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1659 SDB->SwitchCases.clear();
1663 /// Create the scheduler. If a specific scheduler was specified
1664 /// via the SchedulerRegistry, use it, otherwise select the
1665 /// one preferred by the target.
1667 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1668 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1672 RegisterScheduler::setDefault(Ctor);
1675 return Ctor(this, OptLevel);
1678 //===----------------------------------------------------------------------===//
1679 // Helper functions used by the generated instruction selector.
1680 //===----------------------------------------------------------------------===//
1681 // Calls to these methods are generated by tblgen.
1683 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1684 /// the dag combiner simplified the 255, we still want to match. RHS is the
1685 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1686 /// specified in the .td file (e.g. 255).
1687 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1688 int64_t DesiredMaskS) const {
1689 const APInt &ActualMask = RHS->getAPIntValue();
1690 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1692 // If the actual mask exactly matches, success!
1693 if (ActualMask == DesiredMask)
1696 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1697 if (ActualMask.intersects(~DesiredMask))
1700 // Otherwise, the DAG Combiner may have proven that the value coming in is
1701 // either already zero or is not demanded. Check for known zero input bits.
1702 APInt NeededMask = DesiredMask & ~ActualMask;
1703 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1706 // TODO: check to see if missing bits are just not demanded.
1708 // Otherwise, this pattern doesn't match.
1712 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1713 /// the dag combiner simplified the 255, we still want to match. RHS is the
1714 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1715 /// specified in the .td file (e.g. 255).
1716 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1717 int64_t DesiredMaskS) const {
1718 const APInt &ActualMask = RHS->getAPIntValue();
1719 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1721 // If the actual mask exactly matches, success!
1722 if (ActualMask == DesiredMask)
1725 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1726 if (ActualMask.intersects(~DesiredMask))
1729 // Otherwise, the DAG Combiner may have proven that the value coming in is
1730 // either already zero or is not demanded. Check for known zero input bits.
1731 APInt NeededMask = DesiredMask & ~ActualMask;
1733 APInt KnownZero, KnownOne;
1734 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1736 // If all the missing bits in the or are already known to be set, match!
1737 if ((NeededMask & KnownOne) == NeededMask)
1740 // TODO: check to see if missing bits are just not demanded.
1742 // Otherwise, this pattern doesn't match.
1747 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1748 /// by tblgen. Others should not call it.
1749 void SelectionDAGISel::
1750 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1751 std::vector<SDValue> InOps;
1752 std::swap(InOps, Ops);
1754 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1755 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1756 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1757 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1759 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1760 if (InOps[e-1].getValueType() == MVT::Glue)
1761 --e; // Don't process a glue operand if it is here.
1764 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1765 if (!InlineAsm::isMemKind(Flags)) {
1766 // Just skip over this operand, copying the operands verbatim.
1767 Ops.insert(Ops.end(), InOps.begin()+i,
1768 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1769 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1771 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1772 "Memory operand with multiple values?");
1773 // Otherwise, this is a memory operand. Ask the target to select it.
1774 std::vector<SDValue> SelOps;
1775 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1776 report_fatal_error("Could not match memory address. Inline asm"
1779 // Add this to the output node.
1781 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1782 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1783 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1788 // Add the glue input back if present.
1789 if (e != InOps.size())
1790 Ops.push_back(InOps.back());
1793 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1796 static SDNode *findGlueUse(SDNode *N) {
1797 unsigned FlagResNo = N->getNumValues()-1;
1798 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1799 SDUse &Use = I.getUse();
1800 if (Use.getResNo() == FlagResNo)
1801 return Use.getUser();
1806 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1807 /// This function recursively traverses up the operand chain, ignoring
1809 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1810 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1811 bool IgnoreChains) {
1812 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1813 // greater than all of its (recursive) operands. If we scan to a point where
1814 // 'use' is smaller than the node we're scanning for, then we know we will
1817 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1818 // happen because we scan down to newly selected nodes in the case of glue
1820 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1823 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1824 // won't fail if we scan it again.
1825 if (!Visited.insert(Use).second)
1828 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1829 // Ignore chain uses, they are validated by HandleMergeInputChains.
1830 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1833 SDNode *N = Use->getOperand(i).getNode();
1835 if (Use == ImmedUse || Use == Root)
1836 continue; // We are not looking for immediate use.
1841 // Traverse up the operand chain.
1842 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1848 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1849 /// operand node N of U during instruction selection that starts at Root.
1850 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1851 SDNode *Root) const {
1852 if (OptLevel == CodeGenOpt::None) return false;
1853 return N.hasOneUse();
1856 /// IsLegalToFold - Returns true if the specific operand node N of
1857 /// U can be folded during instruction selection that starts at Root.
1858 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1859 CodeGenOpt::Level OptLevel,
1860 bool IgnoreChains) {
1861 if (OptLevel == CodeGenOpt::None) return false;
1863 // If Root use can somehow reach N through a path that that doesn't contain
1864 // U then folding N would create a cycle. e.g. In the following
1865 // diagram, Root can reach N through X. If N is folded into into Root, then
1866 // X is both a predecessor and a successor of U.
1877 // * indicates nodes to be folded together.
1879 // If Root produces glue, then it gets (even more) interesting. Since it
1880 // will be "glued" together with its glue use in the scheduler, we need to
1881 // check if it might reach N.
1900 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1901 // (call it Fold), then X is a predecessor of GU and a successor of
1902 // Fold. But since Fold and GU are glued together, this will create
1903 // a cycle in the scheduling graph.
1905 // If the node has glue, walk down the graph to the "lowest" node in the
1907 EVT VT = Root->getValueType(Root->getNumValues()-1);
1908 while (VT == MVT::Glue) {
1909 SDNode *GU = findGlueUse(Root);
1913 VT = Root->getValueType(Root->getNumValues()-1);
1915 // If our query node has a glue result with a use, we've walked up it. If
1916 // the user (which has already been selected) has a chain or indirectly uses
1917 // the chain, our WalkChainUsers predicate will not consider it. Because of
1918 // this, we cannot ignore chains in this predicate.
1919 IgnoreChains = false;
1923 SmallPtrSet<SDNode*, 16> Visited;
1924 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1927 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1928 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1929 SelectInlineAsmMemoryOperands(Ops);
1931 EVT VTs[] = { MVT::Other, MVT::Glue };
1932 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
1934 return New.getNode();
1938 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1940 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
1941 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1943 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
1944 SDValue New = CurDAG->getCopyFromReg(
1945 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
1947 return New.getNode();
1951 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1953 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1954 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1955 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1956 Op->getOperand(2).getValueType());
1957 SDValue New = CurDAG->getCopyToReg(
1958 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
1960 return New.getNode();
1965 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1966 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1969 /// GetVBR - decode a vbr encoding whose top bit is set.
1970 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1971 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1972 assert(Val >= 128 && "Not a VBR");
1973 Val &= 127; // Remove first vbr bit.
1978 NextBits = MatcherTable[Idx++];
1979 Val |= (NextBits&127) << Shift;
1981 } while (NextBits & 128);
1987 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1988 /// interior glue and chain results to use the new glue and chain results.
1989 void SelectionDAGISel::
1990 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1991 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1993 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1994 bool isMorphNodeTo) {
1995 SmallVector<SDNode*, 4> NowDeadNodes;
1997 // Now that all the normal results are replaced, we replace the chain and
1998 // glue results if present.
1999 if (!ChainNodesMatched.empty()) {
2000 assert(InputChain.getNode() &&
2001 "Matched input chains but didn't produce a chain");
2002 // Loop over all of the nodes we matched that produced a chain result.
2003 // Replace all the chain results with the final chain we ended up with.
2004 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2005 SDNode *ChainNode = ChainNodesMatched[i];
2007 // If this node was already deleted, don't look at it.
2008 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2011 // Don't replace the results of the root node if we're doing a
2013 if (ChainNode == NodeToMatch && isMorphNodeTo)
2016 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2017 if (ChainVal.getValueType() == MVT::Glue)
2018 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2019 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2020 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2022 // If the node became dead and we haven't already seen it, delete it.
2023 if (ChainNode->use_empty() &&
2024 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2025 NowDeadNodes.push_back(ChainNode);
2029 // If the result produces glue, update any glue results in the matched
2030 // pattern with the glue result.
2031 if (InputGlue.getNode()) {
2032 // Handle any interior nodes explicitly marked.
2033 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2034 SDNode *FRN = GlueResultNodesMatched[i];
2036 // If this node was already deleted, don't look at it.
2037 if (FRN->getOpcode() == ISD::DELETED_NODE)
2040 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2041 "Doesn't have a glue result");
2042 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2045 // If the node became dead and we haven't already seen it, delete it.
2046 if (FRN->use_empty() &&
2047 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2048 NowDeadNodes.push_back(FRN);
2052 if (!NowDeadNodes.empty())
2053 CurDAG->RemoveDeadNodes(NowDeadNodes);
2055 DEBUG(dbgs() << "ISEL: Match complete!\n");
2061 CR_LeadsToInteriorNode
2064 /// WalkChainUsers - Walk down the users of the specified chained node that is
2065 /// part of the pattern we're matching, looking at all of the users we find.
2066 /// This determines whether something is an interior node, whether we have a
2067 /// non-pattern node in between two pattern nodes (which prevent folding because
2068 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2069 /// between pattern nodes (in which case the TF becomes part of the pattern).
2071 /// The walk we do here is guaranteed to be small because we quickly get down to
2072 /// already selected nodes "below" us.
2074 WalkChainUsers(const SDNode *ChainedNode,
2075 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2076 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2077 ChainResult Result = CR_Simple;
2079 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2080 E = ChainedNode->use_end(); UI != E; ++UI) {
2081 // Make sure the use is of the chain, not some other value we produce.
2082 if (UI.getUse().getValueType() != MVT::Other) continue;
2086 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2089 // If we see an already-selected machine node, then we've gone beyond the
2090 // pattern that we're selecting down into the already selected chunk of the
2092 unsigned UserOpcode = User->getOpcode();
2093 if (User->isMachineOpcode() ||
2094 UserOpcode == ISD::CopyToReg ||
2095 UserOpcode == ISD::CopyFromReg ||
2096 UserOpcode == ISD::INLINEASM ||
2097 UserOpcode == ISD::EH_LABEL ||
2098 UserOpcode == ISD::LIFETIME_START ||
2099 UserOpcode == ISD::LIFETIME_END) {
2100 // If their node ID got reset to -1 then they've already been selected.
2101 // Treat them like a MachineOpcode.
2102 if (User->getNodeId() == -1)
2106 // If we have a TokenFactor, we handle it specially.
2107 if (User->getOpcode() != ISD::TokenFactor) {
2108 // If the node isn't a token factor and isn't part of our pattern, then it
2109 // must be a random chained node in between two nodes we're selecting.
2110 // This happens when we have something like:
2115 // Because we structurally match the load/store as a read/modify/write,
2116 // but the call is chained between them. We cannot fold in this case
2117 // because it would induce a cycle in the graph.
2118 if (!std::count(ChainedNodesInPattern.begin(),
2119 ChainedNodesInPattern.end(), User))
2120 return CR_InducesCycle;
2122 // Otherwise we found a node that is part of our pattern. For example in:
2126 // This would happen when we're scanning down from the load and see the
2127 // store as a user. Record that there is a use of ChainedNode that is
2128 // part of the pattern and keep scanning uses.
2129 Result = CR_LeadsToInteriorNode;
2130 InteriorChainedNodes.push_back(User);
2134 // If we found a TokenFactor, there are two cases to consider: first if the
2135 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2136 // uses of the TF are in our pattern) we just want to ignore it. Second,
2137 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2143 // | \ DAG's like cheese
2146 // [TokenFactor] [Op]
2153 // In this case, the TokenFactor becomes part of our match and we rewrite it
2154 // as a new TokenFactor.
2156 // To distinguish these two cases, do a recursive walk down the uses.
2157 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2159 // If the uses of the TokenFactor are just already-selected nodes, ignore
2160 // it, it is "below" our pattern.
2162 case CR_InducesCycle:
2163 // If the uses of the TokenFactor lead to nodes that are not part of our
2164 // pattern that are not selected, folding would turn this into a cycle,
2166 return CR_InducesCycle;
2167 case CR_LeadsToInteriorNode:
2168 break; // Otherwise, keep processing.
2171 // Okay, we know we're in the interesting interior case. The TokenFactor
2172 // is now going to be considered part of the pattern so that we rewrite its
2173 // uses (it may have uses that are not part of the pattern) with the
2174 // ultimate chain result of the generated code. We will also add its chain
2175 // inputs as inputs to the ultimate TokenFactor we create.
2176 Result = CR_LeadsToInteriorNode;
2177 ChainedNodesInPattern.push_back(User);
2178 InteriorChainedNodes.push_back(User);
2185 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2186 /// operation for when the pattern matched at least one node with a chains. The
2187 /// input vector contains a list of all of the chained nodes that we match. We
2188 /// must determine if this is a valid thing to cover (i.e. matching it won't
2189 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2190 /// be used as the input node chain for the generated nodes.
2192 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2193 SelectionDAG *CurDAG) {
2194 // Walk all of the chained nodes we've matched, recursively scanning down the
2195 // users of the chain result. This adds any TokenFactor nodes that are caught
2196 // in between chained nodes to the chained and interior nodes list.
2197 SmallVector<SDNode*, 3> InteriorChainedNodes;
2198 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2199 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2200 InteriorChainedNodes) == CR_InducesCycle)
2201 return SDValue(); // Would induce a cycle.
2204 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2205 // that we are interested in. Form our input TokenFactor node.
2206 SmallVector<SDValue, 3> InputChains;
2207 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2208 // Add the input chain of this node to the InputChains list (which will be
2209 // the operands of the generated TokenFactor) if it's not an interior node.
2210 SDNode *N = ChainNodesMatched[i];
2211 if (N->getOpcode() != ISD::TokenFactor) {
2212 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2215 // Otherwise, add the input chain.
2216 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2217 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2218 InputChains.push_back(InChain);
2222 // If we have a token factor, we want to add all inputs of the token factor
2223 // that are not part of the pattern we're matching.
2224 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2225 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2226 N->getOperand(op).getNode()))
2227 InputChains.push_back(N->getOperand(op));
2231 if (InputChains.size() == 1)
2232 return InputChains[0];
2233 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2234 MVT::Other, InputChains);
2237 /// MorphNode - Handle morphing a node in place for the selector.
2238 SDNode *SelectionDAGISel::
2239 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2240 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2241 // It is possible we're using MorphNodeTo to replace a node with no
2242 // normal results with one that has a normal result (or we could be
2243 // adding a chain) and the input could have glue and chains as well.
2244 // In this case we need to shift the operands down.
2245 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2246 // than the old isel though.
2247 int OldGlueResultNo = -1, OldChainResultNo = -1;
2249 unsigned NTMNumResults = Node->getNumValues();
2250 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2251 OldGlueResultNo = NTMNumResults-1;
2252 if (NTMNumResults != 1 &&
2253 Node->getValueType(NTMNumResults-2) == MVT::Other)
2254 OldChainResultNo = NTMNumResults-2;
2255 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2256 OldChainResultNo = NTMNumResults-1;
2258 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2259 // that this deletes operands of the old node that become dead.
2260 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2262 // MorphNodeTo can operate in two ways: if an existing node with the
2263 // specified operands exists, it can just return it. Otherwise, it
2264 // updates the node in place to have the requested operands.
2266 // If we updated the node in place, reset the node ID. To the isel,
2267 // this should be just like a newly allocated machine node.
2271 unsigned ResNumResults = Res->getNumValues();
2272 // Move the glue if needed.
2273 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2274 (unsigned)OldGlueResultNo != ResNumResults-1)
2275 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2276 SDValue(Res, ResNumResults-1));
2278 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2281 // Move the chain reference if needed.
2282 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2283 (unsigned)OldChainResultNo != ResNumResults-1)
2284 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2285 SDValue(Res, ResNumResults-1));
2287 // Otherwise, no replacement happened because the node already exists. Replace
2288 // Uses of the old node with the new one.
2290 CurDAG->ReplaceAllUsesWith(Node, Res);
2295 /// CheckSame - Implements OP_CheckSame.
2296 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2297 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2299 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2300 // Accept if it is exactly the same as a previously recorded node.
2301 unsigned RecNo = MatcherTable[MatcherIndex++];
2302 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2303 return N == RecordedNodes[RecNo].first;
2306 /// CheckChildSame - Implements OP_CheckChildXSame.
2307 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2308 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2310 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2312 if (ChildNo >= N.getNumOperands())
2313 return false; // Match fails if out of range child #.
2314 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2318 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2319 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2320 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2321 const SelectionDAGISel &SDISel) {
2322 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2325 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2326 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2327 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2328 const SelectionDAGISel &SDISel, SDNode *N) {
2329 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2332 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2333 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2335 uint16_t Opc = MatcherTable[MatcherIndex++];
2336 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2337 return N->getOpcode() == Opc;
2340 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2341 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2342 SDValue N, const TargetLowering *TLI) {
2343 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2344 if (N.getValueType() == VT) return true;
2346 // Handle the case when VT is iPTR.
2347 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2350 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2351 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2352 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2353 if (ChildNo >= N.getNumOperands())
2354 return false; // Match fails if out of range child #.
2355 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2358 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2359 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2361 return cast<CondCodeSDNode>(N)->get() ==
2362 (ISD::CondCode)MatcherTable[MatcherIndex++];
2365 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2366 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2367 SDValue N, const TargetLowering *TLI) {
2368 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2369 if (cast<VTSDNode>(N)->getVT() == VT)
2372 // Handle the case when VT is iPTR.
2373 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2376 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2377 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2379 int64_t Val = MatcherTable[MatcherIndex++];
2381 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2383 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2384 return C && C->getSExtValue() == Val;
2387 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2388 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2389 SDValue N, unsigned ChildNo) {
2390 if (ChildNo >= N.getNumOperands())
2391 return false; // Match fails if out of range child #.
2392 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2395 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2396 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2397 SDValue N, const SelectionDAGISel &SDISel) {
2398 int64_t Val = MatcherTable[MatcherIndex++];
2400 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2402 if (N->getOpcode() != ISD::AND) return false;
2404 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2405 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2408 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2409 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2410 SDValue N, const SelectionDAGISel &SDISel) {
2411 int64_t Val = MatcherTable[MatcherIndex++];
2413 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2415 if (N->getOpcode() != ISD::OR) return false;
2417 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2418 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2421 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2422 /// scope, evaluate the current node. If the current predicate is known to
2423 /// fail, set Result=true and return anything. If the current predicate is
2424 /// known to pass, set Result=false and return the MatcherIndex to continue
2425 /// with. If the current predicate is unknown, set Result=false and return the
2426 /// MatcherIndex to continue with.
2427 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2428 unsigned Index, SDValue N,
2430 const SelectionDAGISel &SDISel,
2431 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2432 switch (Table[Index++]) {
2435 return Index-1; // Could not evaluate this predicate.
2436 case SelectionDAGISel::OPC_CheckSame:
2437 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2439 case SelectionDAGISel::OPC_CheckChild0Same:
2440 case SelectionDAGISel::OPC_CheckChild1Same:
2441 case SelectionDAGISel::OPC_CheckChild2Same:
2442 case SelectionDAGISel::OPC_CheckChild3Same:
2443 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2444 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2446 case SelectionDAGISel::OPC_CheckPatternPredicate:
2447 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2449 case SelectionDAGISel::OPC_CheckPredicate:
2450 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2452 case SelectionDAGISel::OPC_CheckOpcode:
2453 Result = !::CheckOpcode(Table, Index, N.getNode());
2455 case SelectionDAGISel::OPC_CheckType:
2456 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2458 case SelectionDAGISel::OPC_CheckChild0Type:
2459 case SelectionDAGISel::OPC_CheckChild1Type:
2460 case SelectionDAGISel::OPC_CheckChild2Type:
2461 case SelectionDAGISel::OPC_CheckChild3Type:
2462 case SelectionDAGISel::OPC_CheckChild4Type:
2463 case SelectionDAGISel::OPC_CheckChild5Type:
2464 case SelectionDAGISel::OPC_CheckChild6Type:
2465 case SelectionDAGISel::OPC_CheckChild7Type:
2466 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2468 SelectionDAGISel::OPC_CheckChild0Type);
2470 case SelectionDAGISel::OPC_CheckCondCode:
2471 Result = !::CheckCondCode(Table, Index, N);
2473 case SelectionDAGISel::OPC_CheckValueType:
2474 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2476 case SelectionDAGISel::OPC_CheckInteger:
2477 Result = !::CheckInteger(Table, Index, N);
2479 case SelectionDAGISel::OPC_CheckChild0Integer:
2480 case SelectionDAGISel::OPC_CheckChild1Integer:
2481 case SelectionDAGISel::OPC_CheckChild2Integer:
2482 case SelectionDAGISel::OPC_CheckChild3Integer:
2483 case SelectionDAGISel::OPC_CheckChild4Integer:
2484 Result = !::CheckChildInteger(Table, Index, N,
2485 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2487 case SelectionDAGISel::OPC_CheckAndImm:
2488 Result = !::CheckAndImm(Table, Index, N, SDISel);
2490 case SelectionDAGISel::OPC_CheckOrImm:
2491 Result = !::CheckOrImm(Table, Index, N, SDISel);
2499 /// FailIndex - If this match fails, this is the index to continue with.
2502 /// NodeStack - The node stack when the scope was formed.
2503 SmallVector<SDValue, 4> NodeStack;
2505 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2506 unsigned NumRecordedNodes;
2508 /// NumMatchedMemRefs - The number of matched memref entries.
2509 unsigned NumMatchedMemRefs;
2511 /// InputChain/InputGlue - The current chain/glue
2512 SDValue InputChain, InputGlue;
2514 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2515 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2518 /// \\brief A DAG update listener to keep the matching state
2519 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2520 /// change the DAG while matching. X86 addressing mode matcher is an example
2522 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2524 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2525 SmallVectorImpl<MatchScope> &MatchScopes;
2527 MatchStateUpdater(SelectionDAG &DAG,
2528 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2529 SmallVectorImpl<MatchScope> &MS) :
2530 SelectionDAG::DAGUpdateListener(DAG),
2531 RecordedNodes(RN), MatchScopes(MS) { }
2533 void NodeDeleted(SDNode *N, SDNode *E) {
2534 // Some early-returns here to avoid the search if we deleted the node or
2535 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2536 // do, so it's unnecessary to update matching state at that point).
2537 // Neither of these can occur currently because we only install this
2538 // update listener during matching a complex patterns.
2539 if (!E || E->isMachineOpcode())
2541 // Performing linear search here does not matter because we almost never
2542 // run this code. You'd have to have a CSE during complex pattern
2544 for (auto &I : RecordedNodes)
2545 if (I.first.getNode() == N)
2548 for (auto &I : MatchScopes)
2549 for (auto &J : I.NodeStack)
2550 if (J.getNode() == N)
2556 SDNode *SelectionDAGISel::
2557 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2558 unsigned TableSize) {
2559 // FIXME: Should these even be selected? Handle these cases in the caller?
2560 switch (NodeToMatch->getOpcode()) {
2563 case ISD::EntryToken: // These nodes remain the same.
2564 case ISD::BasicBlock:
2566 case ISD::RegisterMask:
2567 case ISD::HANDLENODE:
2568 case ISD::MDNODE_SDNODE:
2569 case ISD::TargetConstant:
2570 case ISD::TargetConstantFP:
2571 case ISD::TargetConstantPool:
2572 case ISD::TargetFrameIndex:
2573 case ISD::TargetExternalSymbol:
2574 case ISD::TargetBlockAddress:
2575 case ISD::TargetJumpTable:
2576 case ISD::TargetGlobalTLSAddress:
2577 case ISD::TargetGlobalAddress:
2578 case ISD::TokenFactor:
2579 case ISD::CopyFromReg:
2580 case ISD::CopyToReg:
2582 case ISD::LIFETIME_START:
2583 case ISD::LIFETIME_END:
2584 NodeToMatch->setNodeId(-1); // Mark selected.
2586 case ISD::AssertSext:
2587 case ISD::AssertZext:
2588 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2589 NodeToMatch->getOperand(0));
2591 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2592 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2593 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2594 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2597 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2599 // Set up the node stack with NodeToMatch as the only node on the stack.
2600 SmallVector<SDValue, 8> NodeStack;
2601 SDValue N = SDValue(NodeToMatch, 0);
2602 NodeStack.push_back(N);
2604 // MatchScopes - Scopes used when matching, if a match failure happens, this
2605 // indicates where to continue checking.
2606 SmallVector<MatchScope, 8> MatchScopes;
2608 // RecordedNodes - This is the set of nodes that have been recorded by the
2609 // state machine. The second value is the parent of the node, or null if the
2610 // root is recorded.
2611 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2613 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2615 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2617 // These are the current input chain and glue for use when generating nodes.
2618 // Various Emit operations change these. For example, emitting a copytoreg
2619 // uses and updates these.
2620 SDValue InputChain, InputGlue;
2622 // ChainNodesMatched - If a pattern matches nodes that have input/output
2623 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2624 // which ones they are. The result is captured into this list so that we can
2625 // update the chain results when the pattern is complete.
2626 SmallVector<SDNode*, 3> ChainNodesMatched;
2627 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2629 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2630 NodeToMatch->dump(CurDAG);
2633 // Determine where to start the interpreter. Normally we start at opcode #0,
2634 // but if the state machine starts with an OPC_SwitchOpcode, then we
2635 // accelerate the first lookup (which is guaranteed to be hot) with the
2636 // OpcodeOffset table.
2637 unsigned MatcherIndex = 0;
2639 if (!OpcodeOffset.empty()) {
2640 // Already computed the OpcodeOffset table, just index into it.
2641 if (N.getOpcode() < OpcodeOffset.size())
2642 MatcherIndex = OpcodeOffset[N.getOpcode()];
2643 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2645 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2646 // Otherwise, the table isn't computed, but the state machine does start
2647 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2648 // is the first time we're selecting an instruction.
2651 // Get the size of this case.
2652 unsigned CaseSize = MatcherTable[Idx++];
2654 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2655 if (CaseSize == 0) break;
2657 // Get the opcode, add the index to the table.
2658 uint16_t Opc = MatcherTable[Idx++];
2659 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2660 if (Opc >= OpcodeOffset.size())
2661 OpcodeOffset.resize((Opc+1)*2);
2662 OpcodeOffset[Opc] = Idx;
2666 // Okay, do the lookup for the first opcode.
2667 if (N.getOpcode() < OpcodeOffset.size())
2668 MatcherIndex = OpcodeOffset[N.getOpcode()];
2672 assert(MatcherIndex < TableSize && "Invalid index");
2674 unsigned CurrentOpcodeIndex = MatcherIndex;
2676 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2679 // Okay, the semantics of this operation are that we should push a scope
2680 // then evaluate the first child. However, pushing a scope only to have
2681 // the first check fail (which then pops it) is inefficient. If we can
2682 // determine immediately that the first check (or first several) will
2683 // immediately fail, don't even bother pushing a scope for them.
2687 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2688 if (NumToSkip & 128)
2689 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2690 // Found the end of the scope with no match.
2691 if (NumToSkip == 0) {
2696 FailIndex = MatcherIndex+NumToSkip;
2698 unsigned MatcherIndexOfPredicate = MatcherIndex;
2699 (void)MatcherIndexOfPredicate; // silence warning.
2701 // If we can't evaluate this predicate without pushing a scope (e.g. if
2702 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2703 // push the scope and evaluate the full predicate chain.
2705 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2706 Result, *this, RecordedNodes);
2710 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2711 << "index " << MatcherIndexOfPredicate
2712 << ", continuing at " << FailIndex << "\n");
2713 ++NumDAGIselRetries;
2715 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2716 // move to the next case.
2717 MatcherIndex = FailIndex;
2720 // If the whole scope failed to match, bail.
2721 if (FailIndex == 0) break;
2723 // Push a MatchScope which indicates where to go if the first child fails
2725 MatchScope NewEntry;
2726 NewEntry.FailIndex = FailIndex;
2727 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2728 NewEntry.NumRecordedNodes = RecordedNodes.size();
2729 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2730 NewEntry.InputChain = InputChain;
2731 NewEntry.InputGlue = InputGlue;
2732 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2733 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2734 MatchScopes.push_back(NewEntry);
2737 case OPC_RecordNode: {
2738 // Remember this node, it may end up being an operand in the pattern.
2739 SDNode *Parent = nullptr;
2740 if (NodeStack.size() > 1)
2741 Parent = NodeStack[NodeStack.size()-2].getNode();
2742 RecordedNodes.push_back(std::make_pair(N, Parent));
2746 case OPC_RecordChild0: case OPC_RecordChild1:
2747 case OPC_RecordChild2: case OPC_RecordChild3:
2748 case OPC_RecordChild4: case OPC_RecordChild5:
2749 case OPC_RecordChild6: case OPC_RecordChild7: {
2750 unsigned ChildNo = Opcode-OPC_RecordChild0;
2751 if (ChildNo >= N.getNumOperands())
2752 break; // Match fails if out of range child #.
2754 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2758 case OPC_RecordMemRef:
2759 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2762 case OPC_CaptureGlueInput:
2763 // If the current node has an input glue, capture it in InputGlue.
2764 if (N->getNumOperands() != 0 &&
2765 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2766 InputGlue = N->getOperand(N->getNumOperands()-1);
2769 case OPC_MoveChild: {
2770 unsigned ChildNo = MatcherTable[MatcherIndex++];
2771 if (ChildNo >= N.getNumOperands())
2772 break; // Match fails if out of range child #.
2773 N = N.getOperand(ChildNo);
2774 NodeStack.push_back(N);
2778 case OPC_MoveParent:
2779 // Pop the current node off the NodeStack.
2780 NodeStack.pop_back();
2781 assert(!NodeStack.empty() && "Node stack imbalance!");
2782 N = NodeStack.back();
2786 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2789 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2790 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2791 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2792 Opcode-OPC_CheckChild0Same))
2796 case OPC_CheckPatternPredicate:
2797 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2799 case OPC_CheckPredicate:
2800 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2804 case OPC_CheckComplexPat: {
2805 unsigned CPNum = MatcherTable[MatcherIndex++];
2806 unsigned RecNo = MatcherTable[MatcherIndex++];
2807 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2809 // If target can modify DAG during matching, keep the matching state
2811 std::unique_ptr<MatchStateUpdater> MSU;
2812 if (ComplexPatternFuncMutatesDAG())
2813 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2816 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2817 RecordedNodes[RecNo].first, CPNum,
2822 case OPC_CheckOpcode:
2823 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2827 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2831 case OPC_SwitchOpcode: {
2832 unsigned CurNodeOpcode = N.getOpcode();
2833 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2836 // Get the size of this case.
2837 CaseSize = MatcherTable[MatcherIndex++];
2839 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2840 if (CaseSize == 0) break;
2842 uint16_t Opc = MatcherTable[MatcherIndex++];
2843 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2845 // If the opcode matches, then we will execute this case.
2846 if (CurNodeOpcode == Opc)
2849 // Otherwise, skip over this case.
2850 MatcherIndex += CaseSize;
2853 // If no cases matched, bail out.
2854 if (CaseSize == 0) break;
2856 // Otherwise, execute the case we found.
2857 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2858 << " to " << MatcherIndex << "\n");
2862 case OPC_SwitchType: {
2863 MVT CurNodeVT = N.getSimpleValueType();
2864 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2867 // Get the size of this case.
2868 CaseSize = MatcherTable[MatcherIndex++];
2870 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2871 if (CaseSize == 0) break;
2873 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2874 if (CaseVT == MVT::iPTR)
2875 CaseVT = TLI->getPointerTy();
2877 // If the VT matches, then we will execute this case.
2878 if (CurNodeVT == CaseVT)
2881 // Otherwise, skip over this case.
2882 MatcherIndex += CaseSize;
2885 // If no cases matched, bail out.
2886 if (CaseSize == 0) break;
2888 // Otherwise, execute the case we found.
2889 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2890 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2893 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2894 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2895 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2896 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2897 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2898 Opcode-OPC_CheckChild0Type))
2901 case OPC_CheckCondCode:
2902 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2904 case OPC_CheckValueType:
2905 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2908 case OPC_CheckInteger:
2909 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2911 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2912 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2913 case OPC_CheckChild4Integer:
2914 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2915 Opcode-OPC_CheckChild0Integer)) break;
2917 case OPC_CheckAndImm:
2918 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2920 case OPC_CheckOrImm:
2921 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2924 case OPC_CheckFoldableChainNode: {
2925 assert(NodeStack.size() != 1 && "No parent node");
2926 // Verify that all intermediate nodes between the root and this one have
2928 bool HasMultipleUses = false;
2929 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2930 if (!NodeStack[i].hasOneUse()) {
2931 HasMultipleUses = true;
2934 if (HasMultipleUses) break;
2936 // Check to see that the target thinks this is profitable to fold and that
2937 // we can fold it without inducing cycles in the graph.
2938 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2940 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2941 NodeToMatch, OptLevel,
2942 true/*We validate our own chains*/))
2947 case OPC_EmitInteger: {
2948 MVT::SimpleValueType VT =
2949 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2950 int64_t Val = MatcherTable[MatcherIndex++];
2952 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2953 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2954 CurDAG->getTargetConstant(Val, VT), nullptr));
2957 case OPC_EmitRegister: {
2958 MVT::SimpleValueType VT =
2959 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2960 unsigned RegNo = MatcherTable[MatcherIndex++];
2961 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2962 CurDAG->getRegister(RegNo, VT), nullptr));
2965 case OPC_EmitRegister2: {
2966 // For targets w/ more than 256 register names, the register enum
2967 // values are stored in two bytes in the matcher table (just like
2969 MVT::SimpleValueType VT =
2970 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2971 unsigned RegNo = MatcherTable[MatcherIndex++];
2972 RegNo |= MatcherTable[MatcherIndex++] << 8;
2973 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2974 CurDAG->getRegister(RegNo, VT), nullptr));
2978 case OPC_EmitConvertToTarget: {
2979 // Convert from IMM/FPIMM to target version.
2980 unsigned RecNo = MatcherTable[MatcherIndex++];
2981 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2982 SDValue Imm = RecordedNodes[RecNo].first;
2984 if (Imm->getOpcode() == ISD::Constant) {
2985 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2986 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2987 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2988 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2989 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2992 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2996 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2997 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2998 // These are space-optimized forms of OPC_EmitMergeInputChains.
2999 assert(!InputChain.getNode() &&
3000 "EmitMergeInputChains should be the first chain producing node");
3001 assert(ChainNodesMatched.empty() &&
3002 "Should only have one EmitMergeInputChains per match");
3004 // Read all of the chained nodes.
3005 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3006 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3007 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3009 // FIXME: What if other value results of the node have uses not matched
3011 if (ChainNodesMatched.back() != NodeToMatch &&
3012 !RecordedNodes[RecNo].first.hasOneUse()) {
3013 ChainNodesMatched.clear();
3017 // Merge the input chains if they are not intra-pattern references.
3018 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3020 if (!InputChain.getNode())
3021 break; // Failed to merge.
3025 case OPC_EmitMergeInputChains: {
3026 assert(!InputChain.getNode() &&
3027 "EmitMergeInputChains should be the first chain producing node");
3028 // This node gets a list of nodes we matched in the input that have
3029 // chains. We want to token factor all of the input chains to these nodes
3030 // together. However, if any of the input chains is actually one of the
3031 // nodes matched in this pattern, then we have an intra-match reference.
3032 // Ignore these because the newly token factored chain should not refer to
3034 unsigned NumChains = MatcherTable[MatcherIndex++];
3035 assert(NumChains != 0 && "Can't TF zero chains");
3037 assert(ChainNodesMatched.empty() &&
3038 "Should only have one EmitMergeInputChains per match");
3040 // Read all of the chained nodes.
3041 for (unsigned i = 0; i != NumChains; ++i) {
3042 unsigned RecNo = MatcherTable[MatcherIndex++];
3043 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3044 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3046 // FIXME: What if other value results of the node have uses not matched
3048 if (ChainNodesMatched.back() != NodeToMatch &&
3049 !RecordedNodes[RecNo].first.hasOneUse()) {
3050 ChainNodesMatched.clear();
3055 // If the inner loop broke out, the match fails.
3056 if (ChainNodesMatched.empty())
3059 // Merge the input chains if they are not intra-pattern references.
3060 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3062 if (!InputChain.getNode())
3063 break; // Failed to merge.
3068 case OPC_EmitCopyToReg: {
3069 unsigned RecNo = MatcherTable[MatcherIndex++];
3070 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3071 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3073 if (!InputChain.getNode())
3074 InputChain = CurDAG->getEntryNode();
3076 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3077 DestPhysReg, RecordedNodes[RecNo].first,
3080 InputGlue = InputChain.getValue(1);
3084 case OPC_EmitNodeXForm: {
3085 unsigned XFormNo = MatcherTable[MatcherIndex++];
3086 unsigned RecNo = MatcherTable[MatcherIndex++];
3087 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3088 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3089 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3094 case OPC_MorphNodeTo: {
3095 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3096 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3097 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3098 // Get the result VT list.
3099 unsigned NumVTs = MatcherTable[MatcherIndex++];
3100 SmallVector<EVT, 4> VTs;
3101 for (unsigned i = 0; i != NumVTs; ++i) {
3102 MVT::SimpleValueType VT =
3103 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3104 if (VT == MVT::iPTR)
3105 VT = TLI->getPointerTy().SimpleTy;
3109 if (EmitNodeInfo & OPFL_Chain)
3110 VTs.push_back(MVT::Other);
3111 if (EmitNodeInfo & OPFL_GlueOutput)
3112 VTs.push_back(MVT::Glue);
3114 // This is hot code, so optimize the two most common cases of 1 and 2
3117 if (VTs.size() == 1)
3118 VTList = CurDAG->getVTList(VTs[0]);
3119 else if (VTs.size() == 2)
3120 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3122 VTList = CurDAG->getVTList(VTs);
3124 // Get the operand list.
3125 unsigned NumOps = MatcherTable[MatcherIndex++];
3126 SmallVector<SDValue, 8> Ops;
3127 for (unsigned i = 0; i != NumOps; ++i) {
3128 unsigned RecNo = MatcherTable[MatcherIndex++];
3130 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3132 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3133 Ops.push_back(RecordedNodes[RecNo].first);
3136 // If there are variadic operands to add, handle them now.
3137 if (EmitNodeInfo & OPFL_VariadicInfo) {
3138 // Determine the start index to copy from.
3139 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3140 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3141 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3142 "Invalid variadic node");
3143 // Copy all of the variadic operands, not including a potential glue
3145 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3147 SDValue V = NodeToMatch->getOperand(i);
3148 if (V.getValueType() == MVT::Glue) break;
3153 // If this has chain/glue inputs, add them.
3154 if (EmitNodeInfo & OPFL_Chain)
3155 Ops.push_back(InputChain);
3156 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3157 Ops.push_back(InputGlue);
3160 SDNode *Res = nullptr;
3161 if (Opcode != OPC_MorphNodeTo) {
3162 // If this is a normal EmitNode command, just create the new node and
3163 // add the results to the RecordedNodes list.
3164 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3167 // Add all the non-glue/non-chain results to the RecordedNodes list.
3168 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3169 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3170 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3174 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3175 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3177 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3178 // We will visit the equivalent node later.
3179 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3183 // If the node had chain/glue results, update our notion of the current
3185 if (EmitNodeInfo & OPFL_GlueOutput) {
3186 InputGlue = SDValue(Res, VTs.size()-1);
3187 if (EmitNodeInfo & OPFL_Chain)
3188 InputChain = SDValue(Res, VTs.size()-2);
3189 } else if (EmitNodeInfo & OPFL_Chain)
3190 InputChain = SDValue(Res, VTs.size()-1);
3192 // If the OPFL_MemRefs glue is set on this node, slap all of the
3193 // accumulated memrefs onto it.
3195 // FIXME: This is vastly incorrect for patterns with multiple outputs
3196 // instructions that access memory and for ComplexPatterns that match
3198 if (EmitNodeInfo & OPFL_MemRefs) {
3199 // Only attach load or store memory operands if the generated
3200 // instruction may load or store.
3201 const MCInstrDesc &MCID = TII->get(TargetOpc);
3202 bool mayLoad = MCID.mayLoad();
3203 bool mayStore = MCID.mayStore();
3205 unsigned NumMemRefs = 0;
3206 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3207 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3208 if ((*I)->isLoad()) {
3211 } else if ((*I)->isStore()) {
3219 MachineSDNode::mmo_iterator MemRefs =
3220 MF->allocateMemRefsArray(NumMemRefs);
3222 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3223 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3224 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3225 if ((*I)->isLoad()) {
3228 } else if ((*I)->isStore()) {
3236 cast<MachineSDNode>(Res)
3237 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3241 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3242 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3244 // If this was a MorphNodeTo then we're completely done!
3245 if (Opcode == OPC_MorphNodeTo) {
3246 // Update chain and glue uses.
3247 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3248 InputGlue, GlueResultNodesMatched, true);
3255 case OPC_MarkGlueResults: {
3256 unsigned NumNodes = MatcherTable[MatcherIndex++];
3258 // Read and remember all the glue-result nodes.
3259 for (unsigned i = 0; i != NumNodes; ++i) {
3260 unsigned RecNo = MatcherTable[MatcherIndex++];
3262 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3264 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3265 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3270 case OPC_CompleteMatch: {
3271 // The match has been completed, and any new nodes (if any) have been
3272 // created. Patch up references to the matched dag to use the newly
3274 unsigned NumResults = MatcherTable[MatcherIndex++];
3276 for (unsigned i = 0; i != NumResults; ++i) {
3277 unsigned ResSlot = MatcherTable[MatcherIndex++];
3279 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3281 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3282 SDValue Res = RecordedNodes[ResSlot].first;
3284 assert(i < NodeToMatch->getNumValues() &&
3285 NodeToMatch->getValueType(i) != MVT::Other &&
3286 NodeToMatch->getValueType(i) != MVT::Glue &&
3287 "Invalid number of results to complete!");
3288 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3289 NodeToMatch->getValueType(i) == MVT::iPTR ||
3290 Res.getValueType() == MVT::iPTR ||
3291 NodeToMatch->getValueType(i).getSizeInBits() ==
3292 Res.getValueType().getSizeInBits()) &&
3293 "invalid replacement");
3294 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3297 // If the root node defines glue, add it to the glue nodes to update list.
3298 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3299 GlueResultNodesMatched.push_back(NodeToMatch);
3301 // Update chain and glue uses.
3302 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3303 InputGlue, GlueResultNodesMatched, false);
3305 assert(NodeToMatch->use_empty() &&
3306 "Didn't replace all uses of the node?");
3308 // FIXME: We just return here, which interacts correctly with SelectRoot
3309 // above. We should fix this to not return an SDNode* anymore.
3314 // If the code reached this point, then the match failed. See if there is
3315 // another child to try in the current 'Scope', otherwise pop it until we
3316 // find a case to check.
3317 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3318 ++NumDAGIselRetries;
3320 if (MatchScopes.empty()) {
3321 CannotYetSelect(NodeToMatch);
3325 // Restore the interpreter state back to the point where the scope was
3327 MatchScope &LastScope = MatchScopes.back();
3328 RecordedNodes.resize(LastScope.NumRecordedNodes);
3330 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3331 N = NodeStack.back();
3333 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3334 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3335 MatcherIndex = LastScope.FailIndex;
3337 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3339 InputChain = LastScope.InputChain;
3340 InputGlue = LastScope.InputGlue;
3341 if (!LastScope.HasChainNodesMatched)
3342 ChainNodesMatched.clear();
3343 if (!LastScope.HasGlueResultNodesMatched)
3344 GlueResultNodesMatched.clear();
3346 // Check to see what the offset is at the new MatcherIndex. If it is zero
3347 // we have reached the end of this scope, otherwise we have another child
3348 // in the current scope to try.
3349 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3350 if (NumToSkip & 128)
3351 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3353 // If we have another child in this scope to match, update FailIndex and
3355 if (NumToSkip != 0) {
3356 LastScope.FailIndex = MatcherIndex+NumToSkip;
3360 // End of this scope, pop it and try the next child in the containing
3362 MatchScopes.pop_back();
3369 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3371 raw_string_ostream Msg(msg);
3372 Msg << "Cannot select: ";
3374 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3375 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3376 N->getOpcode() != ISD::INTRINSIC_VOID) {
3377 N->printrFull(Msg, CurDAG);
3378 Msg << "\nIn function: " << MF->getName();
3380 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3382 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3383 if (iid < Intrinsic::num_intrinsics)
3384 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3385 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3386 Msg << "target intrinsic %" << TII->getName(iid);
3388 Msg << "unknown intrinsic #" << iid;
3390 report_fatal_error(Msg.str());
3393 char SelectionDAGISel::ID = 0;