1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "SelectionDAGBuild.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleDAG.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetData.h"
42 #include "llvm/Target/TargetFrameInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/Timer.h"
55 EnableValueProp("enable-value-prop", cl::Hidden);
57 EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
59 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
60 cl::desc("Enable verbose messages in the \"fast\" "
61 "instruction selector"));
63 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
64 cl::desc("Enable abort calls when \"fast\" instruction fails"));
66 SchedLiveInCopies("schedule-livein-copies",
67 cl::desc("Schedule copies of livein registers"),
72 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before the first "
76 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before legalize types"));
79 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
80 cl::desc("Pop up a window to show dags before legalize"));
82 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before the second "
86 ViewISelDAGs("view-isel-dags", cl::Hidden,
87 cl::desc("Pop up a window to show isel dags as they are selected"));
89 ViewSchedDAGs("view-sched-dags", cl::Hidden,
90 cl::desc("Pop up a window to show sched dags as they are processed"));
92 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
93 cl::desc("Pop up a window to show SUnit dags after they are processed"));
95 static const bool ViewDAGCombine1 = false,
96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
97 ViewDAGCombine2 = false,
98 ViewISelDAGs = false, ViewSchedDAGs = false,
99 ViewSUnitDAGs = false;
102 //===---------------------------------------------------------------------===//
104 /// RegisterScheduler class - Track the registration of instruction schedulers.
106 //===---------------------------------------------------------------------===//
107 MachinePassRegistry RegisterScheduler::Registry;
109 //===---------------------------------------------------------------------===//
111 /// ISHeuristic command line option for instruction schedulers.
113 //===---------------------------------------------------------------------===//
114 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
115 RegisterPassParser<RegisterScheduler> >
116 ISHeuristic("pre-RA-sched",
117 cl::init(&createDefaultScheduler),
118 cl::desc("Instruction schedulers available (before register"
121 static RegisterScheduler
122 defaultListDAGScheduler("default", "Best scheduler for the target",
123 createDefaultScheduler);
126 //===--------------------------------------------------------------------===//
127 /// createDefaultScheduler - This creates an instruction scheduler appropriate
129 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
131 MachineBasicBlock *BB,
133 TargetLowering &TLI = IS->getTargetLowering();
135 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
136 return createTDListDAGScheduler(IS, DAG, BB, Fast);
138 assert(TLI.getSchedulingPreference() ==
139 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
140 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
145 // EmitInstrWithCustomInserter - This method should be implemented by targets
146 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
147 // instructions are special in various ways, which require special support to
148 // insert. The specified MachineInstr is created but not inserted into any
149 // basic blocks, and the scheduler passes ownership of it to this method.
150 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
151 MachineBasicBlock *MBB) {
152 cerr << "If a target marks an instruction with "
153 << "'usesCustomDAGSchedInserter', it must implement "
154 << "TargetLowering::EmitInstrWithCustomInserter!\n";
159 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
160 /// physical register has only a single copy use, then coalesced the copy
162 static void EmitLiveInCopy(MachineBasicBlock *MBB,
163 MachineBasicBlock::iterator &InsertPos,
164 unsigned VirtReg, unsigned PhysReg,
165 const TargetRegisterClass *RC,
166 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
167 const MachineRegisterInfo &MRI,
168 const TargetRegisterInfo &TRI,
169 const TargetInstrInfo &TII) {
170 unsigned NumUses = 0;
171 MachineInstr *UseMI = NULL;
172 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
173 UE = MRI.use_end(); UI != UE; ++UI) {
179 // If the number of uses is not one, or the use is not a move instruction,
180 // don't coalesce. Also, only coalesce away a virtual register to virtual
182 bool Coalesced = false;
183 unsigned SrcReg, DstReg;
185 TII.isMoveInstr(*UseMI, SrcReg, DstReg) &&
186 TargetRegisterInfo::isVirtualRegister(DstReg)) {
191 // Now find an ideal location to insert the copy.
192 MachineBasicBlock::iterator Pos = InsertPos;
193 while (Pos != MBB->begin()) {
194 MachineInstr *PrevMI = prior(Pos);
195 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
196 // copyRegToReg might emit multiple instructions to do a copy.
197 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
198 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
199 // This is what the BB looks like right now:
204 // We want to insert "r1025 = mov r1". Inserting this copy below the
205 // move to r1024 makes it impossible for that move to be coalesced.
212 break; // Woot! Found a good location.
216 TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
217 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
219 if (&*InsertPos == UseMI) ++InsertPos;
224 /// EmitLiveInCopies - If this is the first basic block in the function,
225 /// and if it has live ins that need to be copied into vregs, emit the
226 /// copies into the block.
227 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
228 const MachineRegisterInfo &MRI,
229 const TargetRegisterInfo &TRI,
230 const TargetInstrInfo &TII) {
231 if (SchedLiveInCopies) {
232 // Emit the copies at a heuristically-determined location in the block.
233 DenseMap<MachineInstr*, unsigned> CopyRegMap;
234 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
235 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
236 E = MRI.livein_end(); LI != E; ++LI)
238 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
239 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
240 RC, CopyRegMap, MRI, TRI, TII);
243 // Emit the copies into the top of the block.
244 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
245 E = MRI.livein_end(); LI != E; ++LI)
247 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
248 TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
249 LI->second, LI->first, RC, RC);
254 //===----------------------------------------------------------------------===//
255 // SelectionDAGISel code
256 //===----------------------------------------------------------------------===//
258 SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) :
259 FunctionPass(&ID), TLI(tli),
260 FuncInfo(new FunctionLoweringInfo(TLI)),
261 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
262 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)),
268 SelectionDAGISel::~SelectionDAGISel() {
274 unsigned SelectionDAGISel::MakeReg(MVT VT) {
275 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
278 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
279 AU.addRequired<AliasAnalysis>();
280 AU.addRequired<GCModuleInfo>();
281 AU.setPreservesAll();
284 bool SelectionDAGISel::runOnFunction(Function &Fn) {
285 // Do some sanity-checking on the command-line options.
286 assert((!EnableFastISelVerbose || EnableFastISel) &&
287 "-fast-isel-verbose requires -fast-isel");
288 assert((!EnableFastISelAbort || EnableFastISel) &&
289 "-fast-isel-abort requires -fast-isel");
291 // Get alias analysis for load/store combining.
292 AA = &getAnalysis<AliasAnalysis>();
294 TargetMachine &TM = TLI.getTargetMachine();
295 MachineFunction &MF = MachineFunction::construct(&Fn, TM);
296 const MachineRegisterInfo &MRI = MF.getRegInfo();
297 const TargetInstrInfo &TII = *TM.getInstrInfo();
298 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
300 if (MF.getFunction()->hasGC())
301 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction());
304 RegInfo = &MF.getRegInfo();
305 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
307 FuncInfo->set(Fn, MF, EnableFastISel);
308 MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>();
309 CurDAG->init(MF, MMI);
312 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
313 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
315 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
317 SelectAllBasicBlocks(Fn, MF, MMI, TII);
319 // If the first basic block in the function has live ins that need to be
320 // copied into vregs, emit the copies into the top of the block before
321 // emitting the code for the block.
322 EmitLiveInCopies(MF.begin(), MRI, TRI, TII);
324 // Add function live-ins to entry block live-in set.
325 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
326 E = RegInfo->livein_end(); I != E; ++I)
327 MF.begin()->addLiveIn(I->first);
330 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
331 "Not all catch info was assigned to a landing pad!");
339 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
340 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
341 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
342 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) {
343 // Apply the catch info to DestBB.
344 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]);
346 if (!FLI.MBBMap[SrcBB]->isLandingPad())
347 FLI.CatchInfoFound.insert(EHSel);
352 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
353 /// whether object offset >= 0.
355 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
356 if (!isa<FrameIndexSDNode>(Op)) return false;
358 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
359 int FrameIdx = FrameIdxNode->getIndex();
360 return MFI->isFixedObjectIndex(FrameIdx) &&
361 MFI->getObjectOffset(FrameIdx) >= 0;
364 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
365 /// possibly be overwritten when lowering the outgoing arguments in a tail
366 /// call. Currently the implementation of this call is very conservative and
367 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
368 /// virtual registers would be overwritten by direct lowering.
369 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
370 MachineFrameInfo * MFI) {
371 RegisterSDNode * OpReg = NULL;
372 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
373 (Op.getOpcode()== ISD::CopyFromReg &&
374 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
375 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
376 (Op.getOpcode() == ISD::LOAD &&
377 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
378 (Op.getOpcode() == ISD::MERGE_VALUES &&
379 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD &&
380 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()).
386 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
387 /// DAG and fixes their tailcall attribute operand.
388 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
389 TargetLowering& TLI) {
391 SDValue Terminator = DAG.getRoot();
394 if (Terminator.getOpcode() == ISD::RET) {
395 Ret = Terminator.getNode();
398 // Fix tail call attribute of CALL nodes.
399 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
400 BI = DAG.allnodes_end(); BI != BE; ) {
402 if (CallSDNode *TheCall = dyn_cast<CallSDNode>(BI)) {
403 SDValue OpRet(Ret, 0);
404 SDValue OpCall(BI, 0);
405 bool isMarkedTailCall = TheCall->isTailCall();
406 // If CALL node has tail call attribute set to true and the call is not
407 // eligible (no RET or the target rejects) the attribute is fixed to
408 // false. The TargetLowering::IsEligibleForTailCallOptimization function
409 // must correctly identify tail call optimizable calls.
410 if (!isMarkedTailCall) continue;
412 !TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) {
413 // Not eligible. Mark CALL node as non tail call. Note that we
414 // can modify the call node in place since calls are not CSE'd.
415 TheCall->setNotTailCall();
417 // Look for tail call clobbered arguments. Emit a series of
418 // copyto/copyfrom virtual register nodes to protect them.
419 SmallVector<SDValue, 32> Ops;
420 SDValue Chain = TheCall->getChain(), InFlag;
421 Ops.push_back(Chain);
422 Ops.push_back(TheCall->getCallee());
423 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
424 SDValue Arg = TheCall->getArg(i);
425 bool isByVal = TheCall->getArgFlags(i).isByVal();
426 MachineFunction &MF = DAG.getMachineFunction();
427 MachineFrameInfo *MFI = MF.getFrameInfo();
429 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
430 MVT VT = Arg.getValueType();
431 unsigned VReg = MF.getRegInfo().
432 createVirtualRegister(TLI.getRegClassFor(VT));
433 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
434 InFlag = Chain.getValue(1);
435 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
436 Chain = Arg.getValue(1);
437 InFlag = Arg.getValue(2);
440 Ops.push_back(TheCall->getArgFlagsVal(i));
442 // Link in chain of CopyTo/CopyFromReg.
444 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
450 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
451 BasicBlock::iterator Begin,
452 BasicBlock::iterator End) {
453 SDL->setCurrentBasicBlock(BB);
455 // Lower all of the non-terminator instructions.
456 for (BasicBlock::iterator I = Begin; I != End; ++I)
457 if (!isa<TerminatorInst>(I))
460 // Ensure that all instructions which are used outside of their defining
461 // blocks are available as virtual registers. Invoke is handled elsewhere.
462 for (BasicBlock::iterator I = Begin; I != End; ++I)
463 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
464 DenseMap<const Value*,unsigned>::iterator VMI =FuncInfo->ValueMap.find(I);
465 if (VMI != FuncInfo->ValueMap.end())
466 SDL->CopyValueToVirtualRegister(I, VMI->second);
469 // Handle PHI nodes in successor blocks.
470 if (End == LLVMBB->end()) {
471 HandlePHINodesInSuccessorBlocks(LLVMBB);
473 // Lower the terminator after the copies are emitted.
474 SDL->visit(*LLVMBB->getTerminator());
477 // Make sure the root of the DAG is up-to-date.
478 CurDAG->setRoot(SDL->getControlRoot());
480 // Check whether calls in this block are real tail calls. Fix up CALL nodes
481 // with correct tailcall attribute so that the target can rely on the tailcall
482 // attribute indicating whether the call is really eligible for tail call
484 if (PerformTailCallOpt)
485 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI);
487 // Final step, emit the lowered DAG as machine code.
492 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
493 SmallPtrSet<SDNode*, 128> VisitedNodes;
494 SmallVector<SDNode*, 128> Worklist;
496 Worklist.push_back(CurDAG->getRoot().getNode());
502 while (!Worklist.empty()) {
503 SDNode *N = Worklist.back();
506 // If we've already seen this node, ignore it.
507 if (!VisitedNodes.insert(N))
510 // Otherwise, add all chain operands to the worklist.
511 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
512 if (N->getOperand(i).getValueType() == MVT::Other)
513 Worklist.push_back(N->getOperand(i).getNode());
515 // If this is a CopyToReg with a vreg dest, process it.
516 if (N->getOpcode() != ISD::CopyToReg)
519 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
520 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
523 // Ignore non-scalar or non-integer values.
524 SDValue Src = N->getOperand(2);
525 MVT SrcVT = Src.getValueType();
526 if (!SrcVT.isInteger() || SrcVT.isVector())
529 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
530 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
531 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
533 // Only install this information if it tells us something.
534 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
535 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
536 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo();
537 if (DestReg >= FLI.LiveOutRegInfo.size())
538 FLI.LiveOutRegInfo.resize(DestReg+1);
539 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
540 LOI.NumSignBits = NumSignBits;
541 LOI.KnownOne = NumSignBits;
542 LOI.KnownZero = NumSignBits;
547 void SelectionDAGISel::CodeGenAndEmitDAG() {
548 std::string GroupName;
549 if (TimePassesIsEnabled)
550 GroupName = "Instruction Selection and Scheduling";
551 std::string BlockName;
552 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
553 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
554 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' +
555 BB->getBasicBlock()->getName();
557 DOUT << "Initial selection DAG:\n";
558 DEBUG(CurDAG->dump());
560 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
562 // Run the DAG combiner in pre-legalize mode.
563 if (TimePassesIsEnabled) {
564 NamedRegionTimer T("DAG Combining 1", GroupName);
565 CurDAG->Combine(false, *AA, Fast);
567 CurDAG->Combine(false, *AA, Fast);
570 DOUT << "Optimized lowered selection DAG:\n";
571 DEBUG(CurDAG->dump());
573 // Second step, hack on the DAG until it only uses operations and types that
574 // the target supports.
575 if (EnableLegalizeTypes) {// Enable this some day.
576 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
579 if (TimePassesIsEnabled) {
580 NamedRegionTimer T("Type Legalization", GroupName);
581 CurDAG->LegalizeTypes();
583 CurDAG->LegalizeTypes();
586 DOUT << "Type-legalized selection DAG:\n";
587 DEBUG(CurDAG->dump());
589 // TODO: enable a dag combine pass here.
592 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
594 if (TimePassesIsEnabled) {
595 NamedRegionTimer T("DAG Legalization", GroupName);
601 DOUT << "Legalized selection DAG:\n";
602 DEBUG(CurDAG->dump());
604 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
606 // Run the DAG combiner in post-legalize mode.
607 if (TimePassesIsEnabled) {
608 NamedRegionTimer T("DAG Combining 2", GroupName);
609 CurDAG->Combine(true, *AA, Fast);
611 CurDAG->Combine(true, *AA, Fast);
614 DOUT << "Optimized legalized selection DAG:\n";
615 DEBUG(CurDAG->dump());
617 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
619 if (!Fast && EnableValueProp)
620 ComputeLiveOutVRegInfo();
622 // Third, instruction select all of the operations to machine code, adding the
623 // code to the MachineBasicBlock.
624 if (TimePassesIsEnabled) {
625 NamedRegionTimer T("Instruction Selection", GroupName);
631 DOUT << "Selected selection DAG:\n";
632 DEBUG(CurDAG->dump());
634 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
636 // Schedule machine code.
637 ScheduleDAG *Scheduler;
638 if (TimePassesIsEnabled) {
639 NamedRegionTimer T("Instruction Scheduling", GroupName);
640 Scheduler = Schedule();
642 Scheduler = Schedule();
645 if (ViewSUnitDAGs) Scheduler->viewGraph();
647 // Emit machine code to BB. This can change 'BB' to the last block being
649 if (TimePassesIsEnabled) {
650 NamedRegionTimer T("Instruction Creation", GroupName);
651 BB = Scheduler->EmitSchedule();
653 BB = Scheduler->EmitSchedule();
656 // Free the scheduler state.
657 if (TimePassesIsEnabled) {
658 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
664 DOUT << "Selected machine code:\n";
668 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
669 MachineModuleInfo *MMI,
670 const TargetInstrInfo &TII) {
671 // Initialize the Fast-ISel state, if needed.
672 FastISel *FastIS = 0;
674 FastIS = TLI.createFastISel(*FuncInfo->MF, MMI,
677 FuncInfo->StaticAllocaMap
679 , FuncInfo->CatchInfoLost
683 // Iterate over all basic blocks in the function.
684 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
685 BasicBlock *LLVMBB = &*I;
686 BB = FuncInfo->MBBMap[LLVMBB];
688 BasicBlock::iterator const Begin = LLVMBB->begin();
689 BasicBlock::iterator const End = LLVMBB->end();
690 BasicBlock::iterator BI = Begin;
692 // Lower any arguments needed in this block if this is the entry block.
693 bool SuppressFastISel = false;
694 if (LLVMBB == &Fn.getEntryBlock()) {
695 LowerArguments(LLVMBB);
697 // If any of the arguments has the byval attribute, forgo
698 // fast-isel in the entry block.
701 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
703 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
704 if (EnableFastISelVerbose || EnableFastISelAbort)
705 cerr << "FastISel skips entry block due to byval argument\n";
706 SuppressFastISel = true;
712 if (MMI && BB->isLandingPad()) {
713 // Add a label to mark the beginning of the landing pad. Deletion of the
714 // landing pad can thus be detected via the MachineModuleInfo.
715 unsigned LabelID = MMI->addLandingPad(BB);
717 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL);
718 BuildMI(BB, II).addImm(LabelID);
720 // Mark exception register as live in.
721 unsigned Reg = TLI.getExceptionAddressRegister();
722 if (Reg) BB->addLiveIn(Reg);
724 // Mark exception selector register as live in.
725 Reg = TLI.getExceptionSelectorRegister();
726 if (Reg) BB->addLiveIn(Reg);
728 // FIXME: Hack around an exception handling flaw (PR1508): the personality
729 // function and list of typeids logically belong to the invoke (or, if you
730 // like, the basic block containing the invoke), and need to be associated
731 // with it in the dwarf exception handling tables. Currently however the
732 // information is provided by an intrinsic (eh.selector) that can be moved
733 // to unexpected places by the optimizers: if the unwind edge is critical,
734 // then breaking it can result in the intrinsics being in the successor of
735 // the landing pad, not the landing pad itself. This results in exceptions
736 // not being caught because no typeids are associated with the invoke.
737 // This may not be the only way things can go wrong, but it is the only way
738 // we try to work around for the moment.
739 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
741 if (Br && Br->isUnconditional()) { // Critical edge?
742 BasicBlock::iterator I, E;
743 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
744 if (isa<EHSelectorInst>(I))
748 // No catch info found - try to extract some from the successor.
749 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
753 // Before doing SelectionDAG ISel, see if FastISel has been requested.
754 if (FastIS && !SuppressFastISel) {
755 // Emit code for any incoming arguments. This must happen before
756 // beginning FastISel on the entry block.
757 if (LLVMBB == &Fn.getEntryBlock()) {
758 CurDAG->setRoot(SDL->getControlRoot());
762 FastIS->startNewBlock(BB);
763 // Do FastISel on as many instructions as possible.
764 for (; BI != End; ++BI) {
765 // Just before the terminator instruction, insert instructions to
766 // feed PHI nodes in successor blocks.
767 if (isa<TerminatorInst>(BI))
768 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
769 if (EnableFastISelVerbose || EnableFastISelAbort) {
770 cerr << "FastISel miss: ";
773 if (EnableFastISelAbort)
774 assert(0 && "FastISel didn't handle a PHI in a successor");
778 // First try normal tablegen-generated "fast" selection.
779 if (FastIS->SelectInstruction(BI))
782 // Next, try calling the target to attempt to handle the instruction.
783 if (FastIS->TargetSelectInstruction(BI))
786 // Then handle certain instructions as single-LLVM-Instruction blocks.
787 if (isa<CallInst>(BI)) {
788 if (EnableFastISelVerbose || EnableFastISelAbort) {
789 cerr << "FastISel missed call: ";
793 if (BI->getType() != Type::VoidTy) {
794 unsigned &R = FuncInfo->ValueMap[BI];
796 R = FuncInfo->CreateRegForValue(BI);
799 SelectBasicBlock(LLVMBB, BI, next(BI));
800 // If the instruction was codegen'd with multiple blocks,
801 // inform the FastISel object where to resume inserting.
802 FastIS->setCurrentBlock(BB);
806 // Otherwise, give up on FastISel for the rest of the block.
807 // For now, be a little lenient about non-branch terminators.
808 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
809 if (EnableFastISelVerbose || EnableFastISelAbort) {
810 cerr << "FastISel miss: ";
813 if (EnableFastISelAbort)
814 // The "fast" selector couldn't handle something and bailed.
815 // For the purpose of debugging, just abort.
816 assert(0 && "FastISel didn't select the entire block");
822 // Run SelectionDAG instruction selection on the remainder of the block
823 // not handled by FastISel. If FastISel is not run, this is the entire
826 SelectBasicBlock(LLVMBB, BI, End);
835 SelectionDAGISel::FinishBasicBlock() {
837 // Perform target specific isel post processing.
838 InstructionSelectPostProcessing();
840 DOUT << "Target-post-processed machine code:\n";
843 DOUT << "Total amount of phi nodes to update: "
844 << SDL->PHINodesToUpdate.size() << "\n";
845 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i)
846 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first
847 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";);
849 // Next, now that we know what the last MBB the LLVM BB expanded is, update
850 // PHI nodes in successors.
851 if (SDL->SwitchCases.empty() &&
852 SDL->JTCases.empty() &&
853 SDL->BitTestCases.empty()) {
854 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
855 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
856 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
857 "This is not a machine PHI node that we are updating!");
858 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
860 PHI->addOperand(MachineOperand::CreateMBB(BB));
862 SDL->PHINodesToUpdate.clear();
866 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) {
867 // Lower header first, if it wasn't already lowered
868 if (!SDL->BitTestCases[i].Emitted) {
869 // Set the current basic block to the mbb we wish to insert the code into
870 BB = SDL->BitTestCases[i].Parent;
871 SDL->setCurrentBasicBlock(BB);
873 SDL->visitBitTestHeader(SDL->BitTestCases[i]);
874 CurDAG->setRoot(SDL->getRoot());
879 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
880 // Set the current basic block to the mbb we wish to insert the code into
881 BB = SDL->BitTestCases[i].Cases[j].ThisBB;
882 SDL->setCurrentBasicBlock(BB);
885 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB,
886 SDL->BitTestCases[i].Reg,
887 SDL->BitTestCases[i].Cases[j]);
889 SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
890 SDL->BitTestCases[i].Reg,
891 SDL->BitTestCases[i].Cases[j]);
894 CurDAG->setRoot(SDL->getRoot());
900 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
901 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
902 MachineBasicBlock *PHIBB = PHI->getParent();
903 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
904 "This is not a machine PHI node that we are updating!");
905 // This is "default" BB. We have two jumps to it. From "header" BB and
906 // from last "case" BB.
907 if (PHIBB == SDL->BitTestCases[i].Default) {
908 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
910 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent));
911 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
913 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases.
916 // One of "cases" BB.
917 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size();
919 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB;
920 if (cBB->succ_end() !=
921 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
922 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
924 PHI->addOperand(MachineOperand::CreateMBB(cBB));
929 SDL->BitTestCases.clear();
931 // If the JumpTable record is filled in, then we need to emit a jump table.
932 // Updating the PHI nodes is tricky in this case, since we need to determine
933 // whether the PHI is a successor of the range check MBB or the jump table MBB
934 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) {
935 // Lower header first, if it wasn't already lowered
936 if (!SDL->JTCases[i].first.Emitted) {
937 // Set the current basic block to the mbb we wish to insert the code into
938 BB = SDL->JTCases[i].first.HeaderBB;
939 SDL->setCurrentBasicBlock(BB);
941 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first);
942 CurDAG->setRoot(SDL->getRoot());
947 // Set the current basic block to the mbb we wish to insert the code into
948 BB = SDL->JTCases[i].second.MBB;
949 SDL->setCurrentBasicBlock(BB);
951 SDL->visitJumpTable(SDL->JTCases[i].second);
952 CurDAG->setRoot(SDL->getRoot());
957 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
958 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
959 MachineBasicBlock *PHIBB = PHI->getParent();
960 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
961 "This is not a machine PHI node that we are updating!");
962 // "default" BB. We can go there only from header BB.
963 if (PHIBB == SDL->JTCases[i].second.Default) {
964 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
966 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
968 // JT BB. Just iterate over successors here
969 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
970 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
972 PHI->addOperand(MachineOperand::CreateMBB(BB));
976 SDL->JTCases.clear();
978 // If the switch block involved a branch to one of the actual successors, we
979 // need to update PHI nodes in that block.
980 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
981 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
982 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
983 "This is not a machine PHI node that we are updating!");
984 if (BB->isSuccessor(PHI->getParent())) {
985 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
987 PHI->addOperand(MachineOperand::CreateMBB(BB));
991 // If we generated any switch lowering information, build and codegen any
992 // additional DAGs necessary.
993 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
994 // Set the current basic block to the mbb we wish to insert the code into
995 BB = SDL->SwitchCases[i].ThisBB;
996 SDL->setCurrentBasicBlock(BB);
999 SDL->visitSwitchCase(SDL->SwitchCases[i]);
1000 CurDAG->setRoot(SDL->getRoot());
1001 CodeGenAndEmitDAG();
1004 // Handle any PHI nodes in successors of this chunk, as if we were coming
1005 // from the original BB before switch expansion. Note that PHI nodes can
1006 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1007 // handle them the right number of times.
1008 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1009 for (MachineBasicBlock::iterator Phi = BB->begin();
1010 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
1011 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
1012 for (unsigned pn = 0; ; ++pn) {
1013 assert(pn != SDL->PHINodesToUpdate.size() &&
1014 "Didn't find PHI entry!");
1015 if (SDL->PHINodesToUpdate[pn].first == Phi) {
1016 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
1018 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
1024 // Don't process RHS if same block as LHS.
1025 if (BB == SDL->SwitchCases[i].FalseBB)
1026 SDL->SwitchCases[i].FalseBB = 0;
1028 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1029 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
1030 SDL->SwitchCases[i].FalseBB = 0;
1032 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0);
1034 SDL->SwitchCases.clear();
1036 SDL->PHINodesToUpdate.clear();
1040 /// Schedule - Pick a safe ordering for instructions for each
1041 /// target node in the graph.
1043 ScheduleDAG *SelectionDAGISel::Schedule() {
1044 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1048 RegisterScheduler::setDefault(Ctor);
1051 ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast);
1058 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1059 return new HazardRecognizer();
1062 //===----------------------------------------------------------------------===//
1063 // Helper functions used by the generated instruction selector.
1064 //===----------------------------------------------------------------------===//
1065 // Calls to these methods are generated by tblgen.
1067 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1068 /// the dag combiner simplified the 255, we still want to match. RHS is the
1069 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1070 /// specified in the .td file (e.g. 255).
1071 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1072 int64_t DesiredMaskS) const {
1073 const APInt &ActualMask = RHS->getAPIntValue();
1074 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1076 // If the actual mask exactly matches, success!
1077 if (ActualMask == DesiredMask)
1080 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1081 if (ActualMask.intersects(~DesiredMask))
1084 // Otherwise, the DAG Combiner may have proven that the value coming in is
1085 // either already zero or is not demanded. Check for known zero input bits.
1086 APInt NeededMask = DesiredMask & ~ActualMask;
1087 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1090 // TODO: check to see if missing bits are just not demanded.
1092 // Otherwise, this pattern doesn't match.
1096 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1097 /// the dag combiner simplified the 255, we still want to match. RHS is the
1098 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1099 /// specified in the .td file (e.g. 255).
1100 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1101 int64_t DesiredMaskS) const {
1102 const APInt &ActualMask = RHS->getAPIntValue();
1103 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1105 // If the actual mask exactly matches, success!
1106 if (ActualMask == DesiredMask)
1109 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1110 if (ActualMask.intersects(~DesiredMask))
1113 // Otherwise, the DAG Combiner may have proven that the value coming in is
1114 // either already zero or is not demanded. Check for known zero input bits.
1115 APInt NeededMask = DesiredMask & ~ActualMask;
1117 APInt KnownZero, KnownOne;
1118 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1120 // If all the missing bits in the or are already known to be set, match!
1121 if ((NeededMask & KnownOne) == NeededMask)
1124 // TODO: check to see if missing bits are just not demanded.
1126 // Otherwise, this pattern doesn't match.
1131 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1132 /// by tblgen. Others should not call it.
1133 void SelectionDAGISel::
1134 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1135 std::vector<SDValue> InOps;
1136 std::swap(InOps, Ops);
1138 Ops.push_back(InOps[0]); // input chain.
1139 Ops.push_back(InOps[1]); // input asm string.
1141 unsigned i = 2, e = InOps.size();
1142 if (InOps[e-1].getValueType() == MVT::Flag)
1143 --e; // Don't process a flag operand if it is here.
1146 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1147 if ((Flags & 7) != 4 /*MEM*/) {
1148 // Just skip over this operand, copying the operands verbatim.
1149 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
1150 i += (Flags >> 3) + 1;
1152 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
1153 // Otherwise, this is a memory operand. Ask the target to select it.
1154 std::vector<SDValue> SelOps;
1155 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1156 cerr << "Could not match memory address. Inline asm failure!\n";
1160 // Add this to the output node.
1161 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
1162 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1164 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1169 // Add the flag input back if present.
1170 if (e != InOps.size())
1171 Ops.push_back(InOps.back());
1174 char SelectionDAGISel::ID = 0;