1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
52 EnableValueProp("enable-value-prop", cl::Hidden, cl::init(false));
57 ViewISelDAGs("view-isel-dags", cl::Hidden,
58 cl::desc("Pop up a window to show isel dags as they are selected"));
60 ViewSchedDAGs("view-sched-dags", cl::Hidden,
61 cl::desc("Pop up a window to show sched dags as they are processed"));
63 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
64 cl::desc("Pop up a window to show SUnit dags after they are processed"));
66 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
69 //===---------------------------------------------------------------------===//
71 /// RegisterScheduler class - Track the registration of instruction schedulers.
73 //===---------------------------------------------------------------------===//
74 MachinePassRegistry RegisterScheduler::Registry;
76 //===---------------------------------------------------------------------===//
78 /// ISHeuristic command line option for instruction schedulers.
80 //===---------------------------------------------------------------------===//
81 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
82 RegisterPassParser<RegisterScheduler> >
83 ISHeuristic("pre-RA-sched",
84 cl::init(&createDefaultScheduler),
85 cl::desc("Instruction schedulers available (before register"
88 static RegisterScheduler
89 defaultListDAGScheduler("default", " Best scheduler for the target",
90 createDefaultScheduler);
92 namespace { struct SDISelAsmOperandInfo; }
94 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
95 /// insertvalue or extractvalue indices that identify a member, return
96 /// the linearized index of the start of the member.
98 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
99 const unsigned *Indices,
100 const unsigned *IndicesEnd,
101 unsigned CurIndex = 0) {
102 // Base case: We're done.
103 if (Indices && Indices == IndicesEnd)
106 // Given a struct type, recursively traverse the elements.
107 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
108 for (StructType::element_iterator EB = STy->element_begin(),
110 EE = STy->element_end();
112 if (Indices && *Indices == unsigned(EI - EB))
113 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
114 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
117 // Given an array type, recursively traverse the elements.
118 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
119 const Type *EltTy = ATy->getElementType();
120 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
121 if (Indices && *Indices == i)
122 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
123 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
126 // We haven't found the type we're looking for, so keep searching.
130 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
131 /// MVTs that represent all the individual underlying
132 /// non-aggregate types that comprise it.
134 /// If Offsets is non-null, it points to a vector to be filled in
135 /// with the in-memory offsets of each of the individual values.
137 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
138 SmallVectorImpl<MVT> &ValueVTs,
139 SmallVectorImpl<uint64_t> *Offsets = 0,
140 uint64_t StartingOffset = 0) {
141 // Given a struct type, recursively traverse the elements.
142 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
143 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
144 for (StructType::element_iterator EB = STy->element_begin(),
146 EE = STy->element_end();
148 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
149 StartingOffset + SL->getElementOffset(EI - EB));
152 // Given an array type, recursively traverse the elements.
153 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
154 const Type *EltTy = ATy->getElementType();
155 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
156 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
157 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
158 StartingOffset + i * EltSize);
161 // Base case: we can get an MVT for this LLVM IR type.
162 ValueVTs.push_back(TLI.getValueType(Ty));
164 Offsets->push_back(StartingOffset);
168 /// RegsForValue - This struct represents the registers (physical or virtual)
169 /// that a particular set of values is assigned, and the type information about
170 /// the value. The most common situation is to represent one value at a time,
171 /// but struct or array values are handled element-wise as multiple values.
172 /// The splitting of aggregates is performed recursively, so that we never
173 /// have aggregate-typed registers. The values at this point do not necessarily
174 /// have legal types, so each value may require one or more registers of some
177 struct VISIBILITY_HIDDEN RegsForValue {
178 /// TLI - The TargetLowering object.
180 const TargetLowering *TLI;
182 /// ValueVTs - The value types of the values, which may not be legal, and
183 /// may need be promoted or synthesized from one or more registers.
185 SmallVector<MVT, 4> ValueVTs;
187 /// RegVTs - The value types of the registers. This is the same size as
188 /// ValueVTs and it records, for each value, what the type of the assigned
189 /// register or registers are. (Individual values are never synthesized
190 /// from more than one type of register.)
192 /// With virtual registers, the contents of RegVTs is redundant with TLI's
193 /// getRegisterType member function, however when with physical registers
194 /// it is necessary to have a separate record of the types.
196 SmallVector<MVT, 4> RegVTs;
198 /// Regs - This list holds the registers assigned to the values.
199 /// Each legal or promoted value requires one register, and each
200 /// expanded value requires multiple registers.
202 SmallVector<unsigned, 4> Regs;
204 RegsForValue() : TLI(0) {}
206 RegsForValue(const TargetLowering &tli,
207 const SmallVector<unsigned, 4> ®s,
208 MVT regvt, MVT valuevt)
209 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
210 RegsForValue(const TargetLowering &tli,
211 const SmallVector<unsigned, 4> ®s,
212 const SmallVector<MVT, 4> ®vts,
213 const SmallVector<MVT, 4> &valuevts)
214 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
215 RegsForValue(const TargetLowering &tli,
216 unsigned Reg, const Type *Ty) : TLI(&tli) {
217 ComputeValueVTs(tli, Ty, ValueVTs);
219 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
220 MVT ValueVT = ValueVTs[Value];
221 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
222 MVT RegisterVT = TLI->getRegisterType(ValueVT);
223 for (unsigned i = 0; i != NumRegs; ++i)
224 Regs.push_back(Reg + i);
225 RegVTs.push_back(RegisterVT);
230 /// append - Add the specified values to this one.
231 void append(const RegsForValue &RHS) {
233 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
234 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
235 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
239 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
240 /// this value and returns the result as a ValueVTs value. This uses
241 /// Chain/Flag as the input and updates them for the output Chain/Flag.
242 /// If the Flag pointer is NULL, no flag is used.
243 SDOperand getCopyFromRegs(SelectionDAG &DAG,
244 SDOperand &Chain, SDOperand *Flag) const;
246 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
247 /// specified value into the registers specified by this object. This uses
248 /// Chain/Flag as the input and updates them for the output Chain/Flag.
249 /// If the Flag pointer is NULL, no flag is used.
250 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
251 SDOperand &Chain, SDOperand *Flag) const;
253 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
254 /// operand list. This adds the code marker and includes the number of
255 /// values added into it.
256 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
257 std::vector<SDOperand> &Ops) const;
262 //===--------------------------------------------------------------------===//
263 /// createDefaultScheduler - This creates an instruction scheduler appropriate
265 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
267 MachineBasicBlock *BB) {
268 TargetLowering &TLI = IS->getTargetLowering();
270 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
271 return createTDListDAGScheduler(IS, DAG, BB);
273 assert(TLI.getSchedulingPreference() ==
274 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
275 return createBURRListDAGScheduler(IS, DAG, BB);
280 //===--------------------------------------------------------------------===//
281 /// FunctionLoweringInfo - This contains information that is global to a
282 /// function that is used when lowering a region of the function.
283 class FunctionLoweringInfo {
288 MachineRegisterInfo &RegInfo;
290 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
292 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
293 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
295 /// ValueMap - Since we emit code for the function a basic block at a time,
296 /// we must remember which virtual registers hold the values for
297 /// cross-basic-block values.
298 DenseMap<const Value*, unsigned> ValueMap;
300 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
301 /// the entry block. This allows the allocas to be efficiently referenced
302 /// anywhere in the function.
303 std::map<const AllocaInst*, int> StaticAllocaMap;
306 SmallSet<Instruction*, 8> CatchInfoLost;
307 SmallSet<Instruction*, 8> CatchInfoFound;
310 unsigned MakeReg(MVT VT) {
311 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
314 /// isExportedInst - Return true if the specified value is an instruction
315 /// exported from its block.
316 bool isExportedInst(const Value *V) {
317 return ValueMap.count(V);
320 unsigned CreateRegForValue(const Value *V);
322 unsigned InitializeRegForValue(const Value *V) {
323 unsigned &R = ValueMap[V];
324 assert(R == 0 && "Already initialized this value register!");
325 return R = CreateRegForValue(V);
329 unsigned NumSignBits;
330 APInt KnownOne, KnownZero;
331 LiveOutInfo() : NumSignBits(0) {}
334 /// LiveOutRegInfo - Information about live out vregs, indexed by their
335 /// register number offset by 'FirstVirtualRegister'.
336 std::vector<LiveOutInfo> LiveOutRegInfo;
340 /// isSelector - Return true if this instruction is a call to the
341 /// eh.selector intrinsic.
342 static bool isSelector(Instruction *I) {
343 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
344 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
345 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
349 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
350 /// PHI nodes or outside of the basic block that defines it, or used by a
351 /// switch or atomic instruction, which may expand to multiple basic blocks.
352 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
353 if (isa<PHINode>(I)) return true;
354 BasicBlock *BB = I->getParent();
355 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
356 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
357 // FIXME: Remove switchinst special case.
358 isa<SwitchInst>(*UI))
363 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
364 /// entry block, return true. This includes arguments used by switches, since
365 /// the switch may expand into multiple basic blocks.
366 static bool isOnlyUsedInEntryBlock(Argument *A) {
367 BasicBlock *Entry = A->getParent()->begin();
368 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
369 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
370 return false; // Use not in entry block.
374 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
375 Function &fn, MachineFunction &mf)
376 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
378 // Create a vreg for each argument register that is not dead and is used
379 // outside of the entry block for the function.
380 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
382 if (!isOnlyUsedInEntryBlock(AI))
383 InitializeRegForValue(AI);
385 // Initialize the mapping of values to registers. This is only set up for
386 // instruction values that are used outside of the block that defines
388 Function::iterator BB = Fn.begin(), EB = Fn.end();
389 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
390 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
391 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
392 const Type *Ty = AI->getAllocatedType();
393 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
395 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
398 TySize *= CUI->getZExtValue(); // Get total allocated size.
399 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
400 StaticAllocaMap[AI] =
401 MF.getFrameInfo()->CreateStackObject(TySize, Align);
404 for (; BB != EB; ++BB)
405 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
406 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
407 if (!isa<AllocaInst>(I) ||
408 !StaticAllocaMap.count(cast<AllocaInst>(I)))
409 InitializeRegForValue(I);
411 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
412 // also creates the initial PHI MachineInstrs, though none of the input
413 // operands are populated.
414 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
415 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
417 MF.getBasicBlockList().push_back(MBB);
419 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
422 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
423 if (PN->use_empty()) continue;
425 MVT VT = TLI.getValueType(PN->getType());
426 unsigned NumRegisters = TLI.getNumRegisters(VT);
427 unsigned PHIReg = ValueMap[PN];
428 assert(PHIReg && "PHI node does not have an assigned virtual register!");
429 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
430 for (unsigned i = 0; i != NumRegisters; ++i)
431 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
436 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
437 /// the correctly promoted or expanded types. Assign these registers
438 /// consecutive vreg numbers and return the first assigned number.
440 /// In the case that the given value has struct or array type, this function
441 /// will assign registers for each member or element.
443 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
444 SmallVector<MVT, 4> ValueVTs;
445 ComputeValueVTs(TLI, V->getType(), ValueVTs);
447 unsigned FirstReg = 0;
448 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
449 MVT ValueVT = ValueVTs[Value];
450 MVT RegisterVT = TLI.getRegisterType(ValueVT);
452 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
453 for (unsigned i = 0; i != NumRegs; ++i) {
454 unsigned R = MakeReg(RegisterVT);
455 if (!FirstReg) FirstReg = R;
461 //===----------------------------------------------------------------------===//
462 /// SelectionDAGLowering - This is the common target-independent lowering
463 /// implementation that is parameterized by a TargetLowering object.
464 /// Also, targets can overload any lowering method.
467 class SelectionDAGLowering {
468 MachineBasicBlock *CurMBB;
470 DenseMap<const Value*, SDOperand> NodeMap;
472 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
473 /// them up and then emit token factor nodes when possible. This allows us to
474 /// get simple disambiguation between loads without worrying about alias
476 std::vector<SDOperand> PendingLoads;
478 /// PendingExports - CopyToReg nodes that copy values to virtual registers
479 /// for export to other blocks need to be emitted before any terminator
480 /// instruction, but they have no other ordering requirements. We bunch them
481 /// up and the emit a single tokenfactor for them just before terminator
483 std::vector<SDOperand> PendingExports;
485 /// Case - A struct to record the Value for a switch case, and the
486 /// case's target basic block.
490 MachineBasicBlock* BB;
492 Case() : Low(0), High(0), BB(0) { }
493 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
494 Low(low), High(high), BB(bb) { }
495 uint64_t size() const {
496 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
497 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
498 return (rHigh - rLow + 1ULL);
504 MachineBasicBlock* BB;
507 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
508 Mask(mask), BB(bb), Bits(bits) { }
511 typedef std::vector<Case> CaseVector;
512 typedef std::vector<CaseBits> CaseBitsVector;
513 typedef CaseVector::iterator CaseItr;
514 typedef std::pair<CaseItr, CaseItr> CaseRange;
516 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
517 /// of conditional branches.
519 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
520 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
522 /// CaseBB - The MBB in which to emit the compare and branch
523 MachineBasicBlock *CaseBB;
524 /// LT, GE - If nonzero, we know the current case value must be less-than or
525 /// greater-than-or-equal-to these Constants.
528 /// Range - A pair of iterators representing the range of case values to be
529 /// processed at this point in the binary search tree.
533 typedef std::vector<CaseRec> CaseRecVector;
535 /// The comparison function for sorting the switch case values in the vector.
536 /// WARNING: Case ranges should be disjoint!
538 bool operator () (const Case& C1, const Case& C2) {
539 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
540 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
541 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
542 return CI1->getValue().slt(CI2->getValue());
547 bool operator () (const CaseBits& C1, const CaseBits& C2) {
548 return C1.Bits > C2.Bits;
552 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
555 // TLI - This is information that describes the available target features we
556 // need for lowering. This indicates when operations are unavailable,
557 // implemented with a libcall, etc.
560 const TargetData *TD;
563 /// SwitchCases - Vector of CaseBlock structures used to communicate
564 /// SwitchInst code generation information.
565 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
566 /// JTCases - Vector of JumpTable structures used to communicate
567 /// SwitchInst code generation information.
568 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
569 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
571 /// FuncInfo - Information about the function as a whole.
573 FunctionLoweringInfo &FuncInfo;
575 /// GCI - Garbage collection metadata for the function.
576 CollectorMetadata *GCI;
578 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
580 FunctionLoweringInfo &funcinfo,
581 CollectorMetadata *gci)
582 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
583 FuncInfo(funcinfo), GCI(gci) {
586 /// getRoot - Return the current virtual root of the Selection DAG,
587 /// flushing any PendingLoad items. This must be done before emitting
588 /// a store or any other node that may need to be ordered after any
589 /// prior load instructions.
591 SDOperand getRoot() {
592 if (PendingLoads.empty())
593 return DAG.getRoot();
595 if (PendingLoads.size() == 1) {
596 SDOperand Root = PendingLoads[0];
598 PendingLoads.clear();
602 // Otherwise, we have to make a token factor node.
603 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
604 &PendingLoads[0], PendingLoads.size());
605 PendingLoads.clear();
610 /// getControlRoot - Similar to getRoot, but instead of flushing all the
611 /// PendingLoad items, flush all the PendingExports items. It is necessary
612 /// to do this before emitting a terminator instruction.
614 SDOperand getControlRoot() {
615 SDOperand Root = DAG.getRoot();
617 if (PendingExports.empty())
620 // Turn all of the CopyToReg chains into one factored node.
621 if (Root.getOpcode() != ISD::EntryToken) {
622 unsigned i = 0, e = PendingExports.size();
623 for (; i != e; ++i) {
624 assert(PendingExports[i].Val->getNumOperands() > 1);
625 if (PendingExports[i].Val->getOperand(0) == Root)
626 break; // Don't add the root if we already indirectly depend on it.
630 PendingExports.push_back(Root);
633 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
635 PendingExports.size());
636 PendingExports.clear();
641 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
643 void visit(Instruction &I) { visit(I.getOpcode(), I); }
645 void visit(unsigned Opcode, User &I) {
646 // Note: this doesn't use InstVisitor, because it has to work with
647 // ConstantExpr's in addition to instructions.
649 default: assert(0 && "Unknown instruction type encountered!");
651 // Build the switch statement using the Instruction.def file.
652 #define HANDLE_INST(NUM, OPCODE, CLASS) \
653 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
654 #include "llvm/Instruction.def"
658 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
660 SDOperand getValue(const Value *V);
662 void setValue(const Value *V, SDOperand NewN) {
663 SDOperand &N = NodeMap[V];
664 assert(N.Val == 0 && "Already set a value for this node!");
668 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
669 std::set<unsigned> &OutputRegs,
670 std::set<unsigned> &InputRegs);
672 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
673 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
675 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
676 void ExportFromCurrentBlock(Value *V);
677 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
678 MachineBasicBlock *LandingPad = NULL);
680 // Terminator instructions.
681 void visitRet(ReturnInst &I);
682 void visitBr(BranchInst &I);
683 void visitSwitch(SwitchInst &I);
684 void visitUnreachable(UnreachableInst &I) { /* noop */ }
686 // Helpers for visitSwitch
687 bool handleSmallSwitchRange(CaseRec& CR,
688 CaseRecVector& WorkList,
690 MachineBasicBlock* Default);
691 bool handleJTSwitchCase(CaseRec& CR,
692 CaseRecVector& WorkList,
694 MachineBasicBlock* Default);
695 bool handleBTSplitSwitchCase(CaseRec& CR,
696 CaseRecVector& WorkList,
698 MachineBasicBlock* Default);
699 bool handleBitTestsSwitchCase(CaseRec& CR,
700 CaseRecVector& WorkList,
702 MachineBasicBlock* Default);
703 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
704 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
705 void visitBitTestCase(MachineBasicBlock* NextMBB,
707 SelectionDAGISel::BitTestCase &B);
708 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
709 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
710 SelectionDAGISel::JumpTableHeader &JTH);
712 // These all get lowered before this pass.
713 void visitInvoke(InvokeInst &I);
714 void visitUnwind(UnwindInst &I);
716 void visitBinary(User &I, unsigned OpCode);
717 void visitShift(User &I, unsigned Opcode);
718 void visitAdd(User &I) {
719 if (I.getType()->isFPOrFPVector())
720 visitBinary(I, ISD::FADD);
722 visitBinary(I, ISD::ADD);
724 void visitSub(User &I);
725 void visitMul(User &I) {
726 if (I.getType()->isFPOrFPVector())
727 visitBinary(I, ISD::FMUL);
729 visitBinary(I, ISD::MUL);
731 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
732 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
733 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
734 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
735 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
736 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
737 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
738 void visitOr (User &I) { visitBinary(I, ISD::OR); }
739 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
740 void visitShl (User &I) { visitShift(I, ISD::SHL); }
741 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
742 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
743 void visitICmp(User &I);
744 void visitFCmp(User &I);
745 void visitVICmp(User &I);
746 void visitVFCmp(User &I);
747 // Visit the conversion instructions
748 void visitTrunc(User &I);
749 void visitZExt(User &I);
750 void visitSExt(User &I);
751 void visitFPTrunc(User &I);
752 void visitFPExt(User &I);
753 void visitFPToUI(User &I);
754 void visitFPToSI(User &I);
755 void visitUIToFP(User &I);
756 void visitSIToFP(User &I);
757 void visitPtrToInt(User &I);
758 void visitIntToPtr(User &I);
759 void visitBitCast(User &I);
761 void visitExtractElement(User &I);
762 void visitInsertElement(User &I);
763 void visitShuffleVector(User &I);
765 void visitExtractValue(ExtractValueInst &I);
766 void visitInsertValue(InsertValueInst &I);
768 void visitGetElementPtr(User &I);
769 void visitSelect(User &I);
771 void visitMalloc(MallocInst &I);
772 void visitFree(FreeInst &I);
773 void visitAlloca(AllocaInst &I);
774 void visitLoad(LoadInst &I);
775 void visitStore(StoreInst &I);
776 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
777 void visitCall(CallInst &I);
778 void visitInlineAsm(CallSite CS);
779 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
780 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
782 void visitVAStart(CallInst &I);
783 void visitVAArg(VAArgInst &I);
784 void visitVAEnd(CallInst &I);
785 void visitVACopy(CallInst &I);
787 void visitGetResult(GetResultInst &I);
789 void visitUserOp1(Instruction &I) {
790 assert(0 && "UserOp1 should not exist at instruction selection time!");
793 void visitUserOp2(Instruction &I) {
794 assert(0 && "UserOp2 should not exist at instruction selection time!");
799 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
802 } // end namespace llvm
805 /// getCopyFromParts - Create a value that contains the specified legal parts
806 /// combined into the value they represent. If the parts combine to a type
807 /// larger then ValueVT then AssertOp can be used to specify whether the extra
808 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
809 /// (ISD::AssertSext).
810 static SDOperand getCopyFromParts(SelectionDAG &DAG,
811 const SDOperand *Parts,
815 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
816 assert(NumParts > 0 && "No parts to assemble!");
817 TargetLowering &TLI = DAG.getTargetLoweringInfo();
818 SDOperand Val = Parts[0];
821 // Assemble the value from multiple parts.
822 if (!ValueVT.isVector()) {
823 unsigned PartBits = PartVT.getSizeInBits();
824 unsigned ValueBits = ValueVT.getSizeInBits();
826 // Assemble the power of 2 part.
827 unsigned RoundParts = NumParts & (NumParts - 1) ?
828 1 << Log2_32(NumParts) : NumParts;
829 unsigned RoundBits = PartBits * RoundParts;
830 MVT RoundVT = RoundBits == ValueBits ?
831 ValueVT : MVT::getIntegerVT(RoundBits);
834 if (RoundParts > 2) {
835 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
836 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
837 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
843 if (TLI.isBigEndian())
845 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
847 if (RoundParts < NumParts) {
848 // Assemble the trailing non-power-of-2 part.
849 unsigned OddParts = NumParts - RoundParts;
850 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
851 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
853 // Combine the round and odd parts.
855 if (TLI.isBigEndian())
857 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
858 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
859 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
860 DAG.getConstant(Lo.getValueType().getSizeInBits(),
861 TLI.getShiftAmountTy()));
862 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
863 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
866 // Handle a multi-element vector.
867 MVT IntermediateVT, RegisterVT;
868 unsigned NumIntermediates;
870 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
872 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
873 NumParts = NumRegs; // Silence a compiler warning.
874 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
875 assert(RegisterVT == Parts[0].getValueType() &&
876 "Part type doesn't match part!");
878 // Assemble the parts into intermediate operands.
879 SmallVector<SDOperand, 8> Ops(NumIntermediates);
880 if (NumIntermediates == NumParts) {
881 // If the register was not expanded, truncate or copy the value,
883 for (unsigned i = 0; i != NumParts; ++i)
884 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
885 PartVT, IntermediateVT);
886 } else if (NumParts > 0) {
887 // If the intermediate type was expanded, build the intermediate operands
889 assert(NumParts % NumIntermediates == 0 &&
890 "Must expand into a divisible number of parts!");
891 unsigned Factor = NumParts / NumIntermediates;
892 for (unsigned i = 0; i != NumIntermediates; ++i)
893 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
894 PartVT, IntermediateVT);
897 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
899 Val = DAG.getNode(IntermediateVT.isVector() ?
900 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
901 ValueVT, &Ops[0], NumIntermediates);
905 // There is now one part, held in Val. Correct it to match ValueVT.
906 PartVT = Val.getValueType();
908 if (PartVT == ValueVT)
911 if (PartVT.isVector()) {
912 assert(ValueVT.isVector() && "Unknown vector conversion!");
913 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
916 if (ValueVT.isVector()) {
917 assert(ValueVT.getVectorElementType() == PartVT &&
918 ValueVT.getVectorNumElements() == 1 &&
919 "Only trivial scalar-to-vector conversions should get here!");
920 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
923 if (PartVT.isInteger() &&
924 ValueVT.isInteger()) {
925 if (ValueVT.bitsLT(PartVT)) {
926 // For a truncate, see if we have any information to
927 // indicate whether the truncated bits will always be
928 // zero or sign-extension.
929 if (AssertOp != ISD::DELETED_NODE)
930 Val = DAG.getNode(AssertOp, PartVT, Val,
931 DAG.getValueType(ValueVT));
932 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
934 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
938 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
939 if (ValueVT.bitsLT(Val.getValueType()))
940 // FP_ROUND's are always exact here.
941 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
942 DAG.getIntPtrConstant(1));
943 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
946 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
947 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
949 assert(0 && "Unknown mismatch!");
953 /// getCopyToParts - Create a series of nodes that contain the specified value
954 /// split into legal parts. If the parts contain more bits than Val, then, for
955 /// integers, ExtendKind can be used to specify how to generate the extra bits.
956 static void getCopyToParts(SelectionDAG &DAG,
961 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
962 TargetLowering &TLI = DAG.getTargetLoweringInfo();
963 MVT PtrVT = TLI.getPointerTy();
964 MVT ValueVT = Val.getValueType();
965 unsigned PartBits = PartVT.getSizeInBits();
966 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
971 if (!ValueVT.isVector()) {
972 if (PartVT == ValueVT) {
973 assert(NumParts == 1 && "No-op copy with multiple parts!");
978 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
979 // If the parts cover more bits than the value has, promote the value.
980 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
981 assert(NumParts == 1 && "Do not know what to promote to!");
982 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
983 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
984 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
985 Val = DAG.getNode(ExtendKind, ValueVT, Val);
987 assert(0 && "Unknown mismatch!");
989 } else if (PartBits == ValueVT.getSizeInBits()) {
990 // Different types of the same size.
991 assert(NumParts == 1 && PartVT != ValueVT);
992 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
993 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
994 // If the parts cover less bits than value has, truncate the value.
995 if (PartVT.isInteger() && ValueVT.isInteger()) {
996 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
997 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
999 assert(0 && "Unknown mismatch!");
1003 // The value may have changed - recompute ValueVT.
1004 ValueVT = Val.getValueType();
1005 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
1006 "Failed to tile the value with PartVT!");
1008 if (NumParts == 1) {
1009 assert(PartVT == ValueVT && "Type conversion failed!");
1014 // Expand the value into multiple parts.
1015 if (NumParts & (NumParts - 1)) {
1016 // The number of parts is not a power of 2. Split off and copy the tail.
1017 assert(PartVT.isInteger() && ValueVT.isInteger() &&
1018 "Do not know what to expand to!");
1019 unsigned RoundParts = 1 << Log2_32(NumParts);
1020 unsigned RoundBits = RoundParts * PartBits;
1021 unsigned OddParts = NumParts - RoundParts;
1022 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
1023 DAG.getConstant(RoundBits,
1024 TLI.getShiftAmountTy()));
1025 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1026 if (TLI.isBigEndian())
1027 // The odd parts were reversed by getCopyToParts - unreverse them.
1028 std::reverse(Parts + RoundParts, Parts + NumParts);
1029 NumParts = RoundParts;
1030 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1031 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1034 // The number of parts is a power of 2. Repeatedly bisect the value using
1036 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
1037 MVT::getIntegerVT(ValueVT.getSizeInBits()),
1039 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1040 for (unsigned i = 0; i < NumParts; i += StepSize) {
1041 unsigned ThisBits = StepSize * PartBits / 2;
1042 MVT ThisVT = MVT::getIntegerVT (ThisBits);
1043 SDOperand &Part0 = Parts[i];
1044 SDOperand &Part1 = Parts[i+StepSize/2];
1046 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1047 DAG.getConstant(1, PtrVT));
1048 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1049 DAG.getConstant(0, PtrVT));
1051 if (ThisBits == PartBits && ThisVT != PartVT) {
1052 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1053 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1058 if (TLI.isBigEndian())
1059 std::reverse(Parts, Parts + NumParts);
1065 if (NumParts == 1) {
1066 if (PartVT != ValueVT) {
1067 if (PartVT.isVector()) {
1068 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1070 assert(ValueVT.getVectorElementType() == PartVT &&
1071 ValueVT.getVectorNumElements() == 1 &&
1072 "Only trivial vector-to-scalar conversions should get here!");
1073 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1074 DAG.getConstant(0, PtrVT));
1082 // Handle a multi-element vector.
1083 MVT IntermediateVT, RegisterVT;
1084 unsigned NumIntermediates;
1086 DAG.getTargetLoweringInfo()
1087 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1089 unsigned NumElements = ValueVT.getVectorNumElements();
1091 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1092 NumParts = NumRegs; // Silence a compiler warning.
1093 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1095 // Split the vector into intermediate operands.
1096 SmallVector<SDOperand, 8> Ops(NumIntermediates);
1097 for (unsigned i = 0; i != NumIntermediates; ++i)
1098 if (IntermediateVT.isVector())
1099 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1100 IntermediateVT, Val,
1101 DAG.getConstant(i * (NumElements / NumIntermediates),
1104 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1105 IntermediateVT, Val,
1106 DAG.getConstant(i, PtrVT));
1108 // Split the intermediate operands into legal parts.
1109 if (NumParts == NumIntermediates) {
1110 // If the register was not expanded, promote or copy the value,
1112 for (unsigned i = 0; i != NumParts; ++i)
1113 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1114 } else if (NumParts > 0) {
1115 // If the intermediate type was expanded, split each the value into
1117 assert(NumParts % NumIntermediates == 0 &&
1118 "Must expand into a divisible number of parts!");
1119 unsigned Factor = NumParts / NumIntermediates;
1120 for (unsigned i = 0; i != NumIntermediates; ++i)
1121 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1126 SDOperand SelectionDAGLowering::getValue(const Value *V) {
1127 SDOperand &N = NodeMap[V];
1128 if (N.Val) return N;
1130 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1131 MVT VT = TLI.getValueType(V->getType(), true);
1133 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1134 return N = DAG.getConstant(CI->getValue(), VT);
1136 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1137 return N = DAG.getGlobalAddress(GV, VT);
1139 if (isa<ConstantPointerNull>(C))
1140 return N = DAG.getConstant(0, TLI.getPointerTy());
1142 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1143 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1145 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1146 !V->getType()->isAggregateType())
1147 return N = DAG.getNode(ISD::UNDEF, VT);
1149 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1150 visit(CE->getOpcode(), *CE);
1151 SDOperand N1 = NodeMap[V];
1152 assert(N1.Val && "visit didn't populate the ValueMap!");
1156 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1157 SmallVector<SDOperand, 4> Constants;
1158 SmallVector<MVT, 4> ValueVTs;
1159 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1161 SDNode *Val = getValue(*OI).Val;
1162 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) {
1163 Constants.push_back(SDOperand(Val, i));
1164 ValueVTs.push_back(Val->getValueType(i));
1167 return DAG.getNode(ISD::MERGE_VALUES,
1168 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1169 &Constants[0], Constants.size());
1172 if (const ArrayType *ATy = dyn_cast<ArrayType>(C->getType())) {
1173 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1174 "Unknown array constant!");
1175 unsigned NumElts = ATy->getNumElements();
1177 return SDOperand(); // empty array
1178 MVT EltVT = TLI.getValueType(ATy->getElementType());
1179 SmallVector<SDOperand, 4> Constants(NumElts);
1180 SmallVector<MVT, 4> ValueVTs(NumElts, EltVT);
1181 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1182 if (isa<UndefValue>(C))
1183 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1184 else if (EltVT.isFloatingPoint())
1185 Constants[i] = DAG.getConstantFP(0, EltVT);
1187 Constants[i] = DAG.getConstant(0, EltVT);
1189 return DAG.getNode(ISD::MERGE_VALUES,
1190 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1191 &Constants[0], Constants.size());
1194 if (const StructType *STy = dyn_cast<StructType>(C->getType())) {
1195 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1196 "Unknown struct constant!");
1197 unsigned NumElts = STy->getNumElements();
1199 return SDOperand(); // empty struct
1200 SmallVector<SDOperand, 4> Constants(NumElts);
1201 SmallVector<MVT, 4> ValueVTs(NumElts);
1202 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1203 MVT EltVT = TLI.getValueType(STy->getElementType(i));
1204 ValueVTs[i] = EltVT;
1205 if (isa<UndefValue>(C))
1206 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1207 else if (EltVT.isFloatingPoint())
1208 Constants[i] = DAG.getConstantFP(0, EltVT);
1210 Constants[i] = DAG.getConstant(0, EltVT);
1212 return DAG.getNode(ISD::MERGE_VALUES,
1213 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1214 &Constants[0], Constants.size());
1217 const VectorType *VecTy = cast<VectorType>(V->getType());
1218 unsigned NumElements = VecTy->getNumElements();
1220 // Now that we know the number and type of the elements, get that number of
1221 // elements into the Ops array based on what kind of constant it is.
1222 SmallVector<SDOperand, 16> Ops;
1223 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1224 for (unsigned i = 0; i != NumElements; ++i)
1225 Ops.push_back(getValue(CP->getOperand(i)));
1227 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1228 "Unknown vector constant!");
1229 MVT EltVT = TLI.getValueType(VecTy->getElementType());
1232 if (isa<UndefValue>(C))
1233 Op = DAG.getNode(ISD::UNDEF, EltVT);
1234 else if (EltVT.isFloatingPoint())
1235 Op = DAG.getConstantFP(0, EltVT);
1237 Op = DAG.getConstant(0, EltVT);
1238 Ops.assign(NumElements, Op);
1241 // Create a BUILD_VECTOR node.
1242 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1245 // If this is a static alloca, generate it as the frameindex instead of
1247 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1248 std::map<const AllocaInst*, int>::iterator SI =
1249 FuncInfo.StaticAllocaMap.find(AI);
1250 if (SI != FuncInfo.StaticAllocaMap.end())
1251 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1254 unsigned InReg = FuncInfo.ValueMap[V];
1255 assert(InReg && "Value not in map!");
1257 RegsForValue RFV(TLI, InReg, V->getType());
1258 SDOperand Chain = DAG.getEntryNode();
1259 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1263 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1264 if (I.getNumOperands() == 0) {
1265 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1269 SmallVector<SDOperand, 8> NewValues;
1270 NewValues.push_back(getControlRoot());
1271 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1272 SDOperand RetOp = getValue(I.getOperand(i));
1273 MVT VT = RetOp.getValueType();
1275 // FIXME: C calling convention requires the return type to be promoted to
1276 // at least 32-bit. But this is not necessary for non-C calling conventions.
1277 if (VT.isInteger()) {
1278 MVT MinVT = TLI.getRegisterType(MVT::i32);
1279 if (VT.bitsLT(MinVT))
1283 unsigned NumParts = TLI.getNumRegisters(VT);
1284 MVT PartVT = TLI.getRegisterType(VT);
1285 SmallVector<SDOperand, 4> Parts(NumParts);
1286 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1288 const Function *F = I.getParent()->getParent();
1289 if (F->paramHasAttr(0, ParamAttr::SExt))
1290 ExtendKind = ISD::SIGN_EXTEND;
1291 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1292 ExtendKind = ISD::ZERO_EXTEND;
1294 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind);
1296 for (unsigned i = 0; i < NumParts; ++i) {
1297 NewValues.push_back(Parts[i]);
1298 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1301 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1302 &NewValues[0], NewValues.size()));
1305 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1306 /// the current basic block, add it to ValueMap now so that we'll get a
1308 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1309 // No need to export constants.
1310 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1312 // Already exported?
1313 if (FuncInfo.isExportedInst(V)) return;
1315 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1316 CopyValueToVirtualRegister(V, Reg);
1319 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1320 const BasicBlock *FromBB) {
1321 // The operands of the setcc have to be in this block. We don't know
1322 // how to export them from some other block.
1323 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1324 // Can export from current BB.
1325 if (VI->getParent() == FromBB)
1328 // Is already exported, noop.
1329 return FuncInfo.isExportedInst(V);
1332 // If this is an argument, we can export it if the BB is the entry block or
1333 // if it is already exported.
1334 if (isa<Argument>(V)) {
1335 if (FromBB == &FromBB->getParent()->getEntryBlock())
1338 // Otherwise, can only export this if it is already exported.
1339 return FuncInfo.isExportedInst(V);
1342 // Otherwise, constants can always be exported.
1346 static bool InBlock(const Value *V, const BasicBlock *BB) {
1347 if (const Instruction *I = dyn_cast<Instruction>(V))
1348 return I->getParent() == BB;
1352 /// FindMergedConditions - If Cond is an expression like
1353 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1354 MachineBasicBlock *TBB,
1355 MachineBasicBlock *FBB,
1356 MachineBasicBlock *CurBB,
1358 // If this node is not part of the or/and tree, emit it as a branch.
1359 Instruction *BOp = dyn_cast<Instruction>(Cond);
1361 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1362 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1363 BOp->getParent() != CurBB->getBasicBlock() ||
1364 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1365 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1366 const BasicBlock *BB = CurBB->getBasicBlock();
1368 // If the leaf of the tree is a comparison, merge the condition into
1370 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1371 // The operands of the cmp have to be in this block. We don't know
1372 // how to export them from some other block. If this is the first block
1373 // of the sequence, no exporting is needed.
1375 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1376 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1377 BOp = cast<Instruction>(Cond);
1378 ISD::CondCode Condition;
1379 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1380 switch (IC->getPredicate()) {
1381 default: assert(0 && "Unknown icmp predicate opcode!");
1382 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1383 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1384 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1385 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1386 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1387 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1388 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1389 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1390 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1391 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1393 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1394 ISD::CondCode FPC, FOC;
1395 switch (FC->getPredicate()) {
1396 default: assert(0 && "Unknown fcmp predicate opcode!");
1397 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1398 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1399 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1400 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1401 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1402 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1403 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1404 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1405 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1406 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1407 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1408 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1409 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1410 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1411 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1412 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1414 if (FiniteOnlyFPMath())
1419 Condition = ISD::SETEQ; // silence warning.
1420 assert(0 && "Unknown compare instruction");
1423 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1424 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1425 SwitchCases.push_back(CB);
1429 // Create a CaseBlock record representing this branch.
1430 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1431 NULL, TBB, FBB, CurBB);
1432 SwitchCases.push_back(CB);
1437 // Create TmpBB after CurBB.
1438 MachineFunction::iterator BBI = CurBB;
1439 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1440 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1442 if (Opc == Instruction::Or) {
1443 // Codegen X | Y as:
1451 // Emit the LHS condition.
1452 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1454 // Emit the RHS condition into TmpBB.
1455 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1457 assert(Opc == Instruction::And && "Unknown merge op!");
1458 // Codegen X & Y as:
1465 // This requires creation of TmpBB after CurBB.
1467 // Emit the LHS condition.
1468 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1470 // Emit the RHS condition into TmpBB.
1471 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1475 /// If the set of cases should be emitted as a series of branches, return true.
1476 /// If we should emit this as a bunch of and/or'd together conditions, return
1479 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1480 if (Cases.size() != 2) return true;
1482 // If this is two comparisons of the same values or'd or and'd together, they
1483 // will get folded into a single comparison, so don't emit two blocks.
1484 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1485 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1486 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1487 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1494 void SelectionDAGLowering::visitBr(BranchInst &I) {
1495 // Update machine-CFG edges.
1496 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1498 // Figure out which block is immediately after the current one.
1499 MachineBasicBlock *NextBlock = 0;
1500 MachineFunction::iterator BBI = CurMBB;
1501 if (++BBI != CurMBB->getParent()->end())
1504 if (I.isUnconditional()) {
1505 // Update machine-CFG edges.
1506 CurMBB->addSuccessor(Succ0MBB);
1508 // If this is not a fall-through branch, emit the branch.
1509 if (Succ0MBB != NextBlock)
1510 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1511 DAG.getBasicBlock(Succ0MBB)));
1515 // If this condition is one of the special cases we handle, do special stuff
1517 Value *CondVal = I.getCondition();
1518 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1520 // If this is a series of conditions that are or'd or and'd together, emit
1521 // this as a sequence of branches instead of setcc's with and/or operations.
1522 // For example, instead of something like:
1535 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1536 if (BOp->hasOneUse() &&
1537 (BOp->getOpcode() == Instruction::And ||
1538 BOp->getOpcode() == Instruction::Or)) {
1539 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1540 // If the compares in later blocks need to use values not currently
1541 // exported from this block, export them now. This block should always
1542 // be the first entry.
1543 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1545 // Allow some cases to be rejected.
1546 if (ShouldEmitAsBranches(SwitchCases)) {
1547 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1548 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1549 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1552 // Emit the branch for this block.
1553 visitSwitchCase(SwitchCases[0]);
1554 SwitchCases.erase(SwitchCases.begin());
1558 // Okay, we decided not to do this, remove any inserted MBB's and clear
1560 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1561 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1563 SwitchCases.clear();
1567 // Create a CaseBlock record representing this branch.
1568 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1569 NULL, Succ0MBB, Succ1MBB, CurMBB);
1570 // Use visitSwitchCase to actually insert the fast branch sequence for this
1572 visitSwitchCase(CB);
1575 /// visitSwitchCase - Emits the necessary code to represent a single node in
1576 /// the binary search tree resulting from lowering a switch instruction.
1577 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1579 SDOperand CondLHS = getValue(CB.CmpLHS);
1581 // Build the setcc now.
1582 if (CB.CmpMHS == NULL) {
1583 // Fold "(X == true)" to X and "(X == false)" to !X to
1584 // handle common cases produced by branch lowering.
1585 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1587 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1588 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1589 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1591 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1593 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1595 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1596 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1598 SDOperand CmpOp = getValue(CB.CmpMHS);
1599 MVT VT = CmpOp.getValueType();
1601 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1602 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1604 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1605 Cond = DAG.getSetCC(MVT::i1, SUB,
1606 DAG.getConstant(High-Low, VT), ISD::SETULE);
1610 // Update successor info
1611 CurMBB->addSuccessor(CB.TrueBB);
1612 CurMBB->addSuccessor(CB.FalseBB);
1614 // Set NextBlock to be the MBB immediately after the current one, if any.
1615 // This is used to avoid emitting unnecessary branches to the next block.
1616 MachineBasicBlock *NextBlock = 0;
1617 MachineFunction::iterator BBI = CurMBB;
1618 if (++BBI != CurMBB->getParent()->end())
1621 // If the lhs block is the next block, invert the condition so that we can
1622 // fall through to the lhs instead of the rhs block.
1623 if (CB.TrueBB == NextBlock) {
1624 std::swap(CB.TrueBB, CB.FalseBB);
1625 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1626 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1628 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1629 DAG.getBasicBlock(CB.TrueBB));
1630 if (CB.FalseBB == NextBlock)
1631 DAG.setRoot(BrCond);
1633 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1634 DAG.getBasicBlock(CB.FalseBB)));
1637 /// visitJumpTable - Emit JumpTable node in the current MBB
1638 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1639 // Emit the code for the jump table
1640 assert(JT.Reg != -1U && "Should lower JT Header first!");
1641 MVT PTy = TLI.getPointerTy();
1642 SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1643 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1644 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1649 /// visitJumpTableHeader - This function emits necessary code to produce index
1650 /// in the JumpTable from switch case.
1651 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1652 SelectionDAGISel::JumpTableHeader &JTH) {
1653 // Subtract the lowest switch case value from the value being switched on
1654 // and conditional branch to default mbb if the result is greater than the
1655 // difference between smallest and largest cases.
1656 SDOperand SwitchOp = getValue(JTH.SValue);
1657 MVT VT = SwitchOp.getValueType();
1658 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1659 DAG.getConstant(JTH.First, VT));
1661 // The SDNode we just created, which holds the value being switched on
1662 // minus the the smallest case value, needs to be copied to a virtual
1663 // register so it can be used as an index into the jump table in a
1664 // subsequent basic block. This value may be smaller or larger than the
1665 // target's pointer type, and therefore require extension or truncating.
1666 if (VT.bitsGT(TLI.getPointerTy()))
1667 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1669 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1671 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1672 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1673 JT.Reg = JumpTableReg;
1675 // Emit the range check for the jump table, and branch to the default
1676 // block for the switch statement if the value being switched on exceeds
1677 // the largest case in the switch.
1678 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1679 DAG.getConstant(JTH.Last-JTH.First,VT),
1682 // Set NextBlock to be the MBB immediately after the current one, if any.
1683 // This is used to avoid emitting unnecessary branches to the next block.
1684 MachineBasicBlock *NextBlock = 0;
1685 MachineFunction::iterator BBI = CurMBB;
1686 if (++BBI != CurMBB->getParent()->end())
1689 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1690 DAG.getBasicBlock(JT.Default));
1692 if (JT.MBB == NextBlock)
1693 DAG.setRoot(BrCond);
1695 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1696 DAG.getBasicBlock(JT.MBB)));
1701 /// visitBitTestHeader - This function emits necessary code to produce value
1702 /// suitable for "bit tests"
1703 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1704 // Subtract the minimum value
1705 SDOperand SwitchOp = getValue(B.SValue);
1706 MVT VT = SwitchOp.getValueType();
1707 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1708 DAG.getConstant(B.First, VT));
1711 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1712 DAG.getConstant(B.Range, VT),
1716 if (VT.bitsGT(TLI.getShiftAmountTy()))
1717 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1719 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1721 // Make desired shift
1722 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1723 DAG.getConstant(1, TLI.getPointerTy()),
1726 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1727 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1730 // Set NextBlock to be the MBB immediately after the current one, if any.
1731 // This is used to avoid emitting unnecessary branches to the next block.
1732 MachineBasicBlock *NextBlock = 0;
1733 MachineFunction::iterator BBI = CurMBB;
1734 if (++BBI != CurMBB->getParent()->end())
1737 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1739 CurMBB->addSuccessor(B.Default);
1740 CurMBB->addSuccessor(MBB);
1742 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1743 DAG.getBasicBlock(B.Default));
1745 if (MBB == NextBlock)
1746 DAG.setRoot(BrRange);
1748 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1749 DAG.getBasicBlock(MBB)));
1754 /// visitBitTestCase - this function produces one "bit test"
1755 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1757 SelectionDAGISel::BitTestCase &B) {
1758 // Emit bit tests and jumps
1759 SDOperand SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1760 TLI.getPointerTy());
1762 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1763 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1764 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1765 DAG.getConstant(0, TLI.getPointerTy()),
1768 CurMBB->addSuccessor(B.TargetBB);
1769 CurMBB->addSuccessor(NextMBB);
1771 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1772 AndCmp, DAG.getBasicBlock(B.TargetBB));
1774 // Set NextBlock to be the MBB immediately after the current one, if any.
1775 // This is used to avoid emitting unnecessary branches to the next block.
1776 MachineBasicBlock *NextBlock = 0;
1777 MachineFunction::iterator BBI = CurMBB;
1778 if (++BBI != CurMBB->getParent()->end())
1781 if (NextMBB == NextBlock)
1784 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1785 DAG.getBasicBlock(NextMBB)));
1790 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1791 // Retrieve successors.
1792 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1793 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1795 if (isa<InlineAsm>(I.getCalledValue()))
1798 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1800 // If the value of the invoke is used outside of its defining block, make it
1801 // available as a virtual register.
1802 if (!I.use_empty()) {
1803 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1804 if (VMI != FuncInfo.ValueMap.end())
1805 CopyValueToVirtualRegister(&I, VMI->second);
1808 // Update successor info
1809 CurMBB->addSuccessor(Return);
1810 CurMBB->addSuccessor(LandingPad);
1812 // Drop into normal successor.
1813 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1814 DAG.getBasicBlock(Return)));
1817 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1820 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1821 /// small case ranges).
1822 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1823 CaseRecVector& WorkList,
1825 MachineBasicBlock* Default) {
1826 Case& BackCase = *(CR.Range.second-1);
1828 // Size is the number of Cases represented by this range.
1829 unsigned Size = CR.Range.second - CR.Range.first;
1833 // Get the MachineFunction which holds the current MBB. This is used when
1834 // inserting any additional MBBs necessary to represent the switch.
1835 MachineFunction *CurMF = CurMBB->getParent();
1837 // Figure out which block is immediately after the current one.
1838 MachineBasicBlock *NextBlock = 0;
1839 MachineFunction::iterator BBI = CR.CaseBB;
1841 if (++BBI != CurMBB->getParent()->end())
1844 // TODO: If any two of the cases has the same destination, and if one value
1845 // is the same as the other, but has one bit unset that the other has set,
1846 // use bit manipulation to do two compares at once. For example:
1847 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1849 // Rearrange the case blocks so that the last one falls through if possible.
1850 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1851 // The last case block won't fall through into 'NextBlock' if we emit the
1852 // branches in this order. See if rearranging a case value would help.
1853 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1854 if (I->BB == NextBlock) {
1855 std::swap(*I, BackCase);
1861 // Create a CaseBlock record representing a conditional branch to
1862 // the Case's target mbb if the value being switched on SV is equal
1864 MachineBasicBlock *CurBlock = CR.CaseBB;
1865 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1866 MachineBasicBlock *FallThrough;
1868 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1869 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1871 // If the last case doesn't match, go to the default block.
1872 FallThrough = Default;
1875 Value *RHS, *LHS, *MHS;
1877 if (I->High == I->Low) {
1878 // This is just small small case range :) containing exactly 1 case
1880 LHS = SV; RHS = I->High; MHS = NULL;
1883 LHS = I->Low; MHS = SV; RHS = I->High;
1885 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1886 I->BB, FallThrough, CurBlock);
1888 // If emitting the first comparison, just call visitSwitchCase to emit the
1889 // code into the current block. Otherwise, push the CaseBlock onto the
1890 // vector to be later processed by SDISel, and insert the node's MBB
1891 // before the next MBB.
1892 if (CurBlock == CurMBB)
1893 visitSwitchCase(CB);
1895 SwitchCases.push_back(CB);
1897 CurBlock = FallThrough;
1903 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1904 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1905 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1908 /// handleJTSwitchCase - Emit jumptable for current switch case range
1909 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1910 CaseRecVector& WorkList,
1912 MachineBasicBlock* Default) {
1913 Case& FrontCase = *CR.Range.first;
1914 Case& BackCase = *(CR.Range.second-1);
1916 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1917 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1920 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1924 if (!areJTsAllowed(TLI) || TSize <= 3)
1927 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1931 DOUT << "Lowering jump table\n"
1932 << "First entry: " << First << ". Last entry: " << Last << "\n"
1933 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1935 // Get the MachineFunction which holds the current MBB. This is used when
1936 // inserting any additional MBBs necessary to represent the switch.
1937 MachineFunction *CurMF = CurMBB->getParent();
1939 // Figure out which block is immediately after the current one.
1940 MachineBasicBlock *NextBlock = 0;
1941 MachineFunction::iterator BBI = CR.CaseBB;
1943 if (++BBI != CurMBB->getParent()->end())
1946 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1948 // Create a new basic block to hold the code for loading the address
1949 // of the jump table, and jumping to it. Update successor information;
1950 // we will either branch to the default case for the switch, or the jump
1952 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1953 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1954 CR.CaseBB->addSuccessor(Default);
1955 CR.CaseBB->addSuccessor(JumpTableBB);
1957 // Build a vector of destination BBs, corresponding to each target
1958 // of the jump table. If the value of the jump table slot corresponds to
1959 // a case statement, push the case's BB onto the vector, otherwise, push
1961 std::vector<MachineBasicBlock*> DestBBs;
1962 int64_t TEI = First;
1963 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1964 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1965 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1967 if ((Low <= TEI) && (TEI <= High)) {
1968 DestBBs.push_back(I->BB);
1972 DestBBs.push_back(Default);
1976 // Update successor info. Add one edge to each unique successor.
1977 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1978 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1979 E = DestBBs.end(); I != E; ++I) {
1980 if (!SuccsHandled[(*I)->getNumber()]) {
1981 SuccsHandled[(*I)->getNumber()] = true;
1982 JumpTableBB->addSuccessor(*I);
1986 // Create a jump table index for this jump table, or return an existing
1988 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1990 // Set the jump table information so that we can codegen it as a second
1991 // MachineBasicBlock
1992 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1993 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1994 (CR.CaseBB == CurMBB));
1995 if (CR.CaseBB == CurMBB)
1996 visitJumpTableHeader(JT, JTH);
1998 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
2003 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2005 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
2006 CaseRecVector& WorkList,
2008 MachineBasicBlock* Default) {
2009 // Get the MachineFunction which holds the current MBB. This is used when
2010 // inserting any additional MBBs necessary to represent the switch.
2011 MachineFunction *CurMF = CurMBB->getParent();
2013 // Figure out which block is immediately after the current one.
2014 MachineBasicBlock *NextBlock = 0;
2015 MachineFunction::iterator BBI = CR.CaseBB;
2017 if (++BBI != CurMBB->getParent()->end())
2020 Case& FrontCase = *CR.Range.first;
2021 Case& BackCase = *(CR.Range.second-1);
2022 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2024 // Size is the number of Cases represented by this range.
2025 unsigned Size = CR.Range.second - CR.Range.first;
2027 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2028 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2030 CaseItr Pivot = CR.Range.first + Size/2;
2032 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2033 // (heuristically) allow us to emit JumpTable's later.
2035 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2039 uint64_t LSize = FrontCase.size();
2040 uint64_t RSize = TSize-LSize;
2041 DOUT << "Selecting best pivot: \n"
2042 << "First: " << First << ", Last: " << Last <<"\n"
2043 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
2044 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2046 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2047 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
2048 assert((RBegin-LEnd>=1) && "Invalid case distance");
2049 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2050 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
2051 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
2052 // Should always split in some non-trivial place
2054 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2055 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2056 << "Metric: " << Metric << "\n";
2057 if (FMetric < Metric) {
2060 DOUT << "Current metric set to: " << FMetric << "\n";
2066 if (areJTsAllowed(TLI)) {
2067 // If our case is dense we *really* should handle it earlier!
2068 assert((FMetric > 0) && "Should handle dense range earlier!");
2070 Pivot = CR.Range.first + Size/2;
2073 CaseRange LHSR(CR.Range.first, Pivot);
2074 CaseRange RHSR(Pivot, CR.Range.second);
2075 Constant *C = Pivot->Low;
2076 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2078 // We know that we branch to the LHS if the Value being switched on is
2079 // less than the Pivot value, C. We use this to optimize our binary
2080 // tree a bit, by recognizing that if SV is greater than or equal to the
2081 // LHS's Case Value, and that Case Value is exactly one less than the
2082 // Pivot's Value, then we can branch directly to the LHS's Target,
2083 // rather than creating a leaf node for it.
2084 if ((LHSR.second - LHSR.first) == 1 &&
2085 LHSR.first->High == CR.GE &&
2086 cast<ConstantInt>(C)->getSExtValue() ==
2087 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2088 TrueBB = LHSR.first->BB;
2090 TrueBB = new MachineBasicBlock(LLVMBB);
2091 CurMF->getBasicBlockList().insert(BBI, TrueBB);
2092 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2095 // Similar to the optimization above, if the Value being switched on is
2096 // known to be less than the Constant CR.LT, and the current Case Value
2097 // is CR.LT - 1, then we can branch directly to the target block for
2098 // the current Case Value, rather than emitting a RHS leaf node for it.
2099 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2100 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2101 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2102 FalseBB = RHSR.first->BB;
2104 FalseBB = new MachineBasicBlock(LLVMBB);
2105 CurMF->getBasicBlockList().insert(BBI, FalseBB);
2106 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2109 // Create a CaseBlock record representing a conditional branch to
2110 // the LHS node if the value being switched on SV is less than C.
2111 // Otherwise, branch to LHS.
2112 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
2113 TrueBB, FalseBB, CR.CaseBB);
2115 if (CR.CaseBB == CurMBB)
2116 visitSwitchCase(CB);
2118 SwitchCases.push_back(CB);
2123 /// handleBitTestsSwitchCase - if current case range has few destination and
2124 /// range span less, than machine word bitwidth, encode case range into series
2125 /// of masks and emit bit tests with these masks.
2126 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2127 CaseRecVector& WorkList,
2129 MachineBasicBlock* Default){
2130 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
2132 Case& FrontCase = *CR.Range.first;
2133 Case& BackCase = *(CR.Range.second-1);
2135 // Get the MachineFunction which holds the current MBB. This is used when
2136 // inserting any additional MBBs necessary to represent the switch.
2137 MachineFunction *CurMF = CurMBB->getParent();
2139 unsigned numCmps = 0;
2140 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2142 // Single case counts one, case range - two.
2143 if (I->Low == I->High)
2149 // Count unique destinations
2150 SmallSet<MachineBasicBlock*, 4> Dests;
2151 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2152 Dests.insert(I->BB);
2153 if (Dests.size() > 3)
2154 // Don't bother the code below, if there are too much unique destinations
2157 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2158 << "Total number of comparisons: " << numCmps << "\n";
2160 // Compute span of values.
2161 Constant* minValue = FrontCase.Low;
2162 Constant* maxValue = BackCase.High;
2163 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2164 cast<ConstantInt>(minValue)->getSExtValue();
2165 DOUT << "Compare range: " << range << "\n"
2166 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2167 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2169 if (range>=IntPtrBits ||
2170 (!(Dests.size() == 1 && numCmps >= 3) &&
2171 !(Dests.size() == 2 && numCmps >= 5) &&
2172 !(Dests.size() >= 3 && numCmps >= 6)))
2175 DOUT << "Emitting bit tests\n";
2176 int64_t lowBound = 0;
2178 // Optimize the case where all the case values fit in a
2179 // word without having to subtract minValue. In this case,
2180 // we can optimize away the subtraction.
2181 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2182 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2183 range = cast<ConstantInt>(maxValue)->getSExtValue();
2185 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2188 CaseBitsVector CasesBits;
2189 unsigned i, count = 0;
2191 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2192 MachineBasicBlock* Dest = I->BB;
2193 for (i = 0; i < count; ++i)
2194 if (Dest == CasesBits[i].BB)
2198 assert((count < 3) && "Too much destinations to test!");
2199 CasesBits.push_back(CaseBits(0, Dest, 0));
2203 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2204 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2206 for (uint64_t j = lo; j <= hi; j++) {
2207 CasesBits[i].Mask |= 1ULL << j;
2208 CasesBits[i].Bits++;
2212 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2214 SelectionDAGISel::BitTestInfo BTC;
2216 // Figure out which block is immediately after the current one.
2217 MachineFunction::iterator BBI = CR.CaseBB;
2220 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2223 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2224 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2225 << ", BB: " << CasesBits[i].BB << "\n";
2227 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
2228 CurMF->getBasicBlockList().insert(BBI, CaseBB);
2229 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2234 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2235 -1U, (CR.CaseBB == CurMBB),
2236 CR.CaseBB, Default, BTC);
2238 if (CR.CaseBB == CurMBB)
2239 visitBitTestHeader(BTB);
2241 BitTestCases.push_back(BTB);
2247 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2248 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2249 const SwitchInst& SI) {
2250 unsigned numCmps = 0;
2252 // Start with "simple" cases
2253 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2254 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2255 Cases.push_back(Case(SI.getSuccessorValue(i),
2256 SI.getSuccessorValue(i),
2259 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2261 // Merge case into clusters
2262 if (Cases.size()>=2)
2263 // Must recompute end() each iteration because it may be
2264 // invalidated by erase if we hold on to it
2265 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2266 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2267 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2268 MachineBasicBlock* nextBB = J->BB;
2269 MachineBasicBlock* currentBB = I->BB;
2271 // If the two neighboring cases go to the same destination, merge them
2272 // into a single case.
2273 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2281 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2282 if (I->Low != I->High)
2283 // A range counts double, since it requires two compares.
2290 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2291 // Figure out which block is immediately after the current one.
2292 MachineBasicBlock *NextBlock = 0;
2293 MachineFunction::iterator BBI = CurMBB;
2295 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2297 // If there is only the default destination, branch to it if it is not the
2298 // next basic block. Otherwise, just fall through.
2299 if (SI.getNumOperands() == 2) {
2300 // Update machine-CFG edges.
2302 // If this is not a fall-through branch, emit the branch.
2303 CurMBB->addSuccessor(Default);
2304 if (Default != NextBlock)
2305 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2306 DAG.getBasicBlock(Default)));
2311 // If there are any non-default case statements, create a vector of Cases
2312 // representing each one, and sort the vector so that we can efficiently
2313 // create a binary search tree from them.
2315 unsigned numCmps = Clusterify(Cases, SI);
2316 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2317 << ". Total compares: " << numCmps << "\n";
2319 // Get the Value to be switched on and default basic blocks, which will be
2320 // inserted into CaseBlock records, representing basic blocks in the binary
2322 Value *SV = SI.getOperand(0);
2324 // Push the initial CaseRec onto the worklist
2325 CaseRecVector WorkList;
2326 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2328 while (!WorkList.empty()) {
2329 // Grab a record representing a case range to process off the worklist
2330 CaseRec CR = WorkList.back();
2331 WorkList.pop_back();
2333 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2336 // If the range has few cases (two or less) emit a series of specific
2338 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2341 // If the switch has more than 5 blocks, and at least 40% dense, and the
2342 // target supports indirect branches, then emit a jump table rather than
2343 // lowering the switch to a binary tree of conditional branches.
2344 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2347 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2348 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2349 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2354 void SelectionDAGLowering::visitSub(User &I) {
2355 // -0.0 - X --> fneg
2356 const Type *Ty = I.getType();
2357 if (isa<VectorType>(Ty)) {
2358 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2359 const VectorType *DestTy = cast<VectorType>(I.getType());
2360 const Type *ElTy = DestTy->getElementType();
2361 if (ElTy->isFloatingPoint()) {
2362 unsigned VL = DestTy->getNumElements();
2363 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2364 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2366 SDOperand Op2 = getValue(I.getOperand(1));
2367 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2373 if (Ty->isFloatingPoint()) {
2374 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2375 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2376 SDOperand Op2 = getValue(I.getOperand(1));
2377 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2382 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2385 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2386 SDOperand Op1 = getValue(I.getOperand(0));
2387 SDOperand Op2 = getValue(I.getOperand(1));
2389 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2392 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2393 SDOperand Op1 = getValue(I.getOperand(0));
2394 SDOperand Op2 = getValue(I.getOperand(1));
2396 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2397 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2398 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2399 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2401 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2404 void SelectionDAGLowering::visitICmp(User &I) {
2405 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2406 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2407 predicate = IC->getPredicate();
2408 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2409 predicate = ICmpInst::Predicate(IC->getPredicate());
2410 SDOperand Op1 = getValue(I.getOperand(0));
2411 SDOperand Op2 = getValue(I.getOperand(1));
2412 ISD::CondCode Opcode;
2413 switch (predicate) {
2414 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2415 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2416 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2417 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2418 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2419 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2420 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2421 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2422 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2423 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2425 assert(!"Invalid ICmp predicate value");
2426 Opcode = ISD::SETEQ;
2429 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2432 void SelectionDAGLowering::visitFCmp(User &I) {
2433 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2434 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2435 predicate = FC->getPredicate();
2436 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2437 predicate = FCmpInst::Predicate(FC->getPredicate());
2438 SDOperand Op1 = getValue(I.getOperand(0));
2439 SDOperand Op2 = getValue(I.getOperand(1));
2440 ISD::CondCode Condition, FOC, FPC;
2441 switch (predicate) {
2442 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2443 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2444 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2445 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2446 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2447 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2448 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2449 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2450 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2451 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2452 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2453 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2454 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2455 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2456 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2457 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2459 assert(!"Invalid FCmp predicate value");
2460 FOC = FPC = ISD::SETFALSE;
2463 if (FiniteOnlyFPMath())
2467 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2470 void SelectionDAGLowering::visitVICmp(User &I) {
2471 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2472 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2473 predicate = IC->getPredicate();
2474 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2475 predicate = ICmpInst::Predicate(IC->getPredicate());
2476 SDOperand Op1 = getValue(I.getOperand(0));
2477 SDOperand Op2 = getValue(I.getOperand(1));
2478 ISD::CondCode Opcode;
2479 switch (predicate) {
2480 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2481 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2482 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2483 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2484 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2485 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2486 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2487 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2488 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2489 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2491 assert(!"Invalid ICmp predicate value");
2492 Opcode = ISD::SETEQ;
2495 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2498 void SelectionDAGLowering::visitVFCmp(User &I) {
2499 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2500 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2501 predicate = FC->getPredicate();
2502 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2503 predicate = FCmpInst::Predicate(FC->getPredicate());
2504 SDOperand Op1 = getValue(I.getOperand(0));
2505 SDOperand Op2 = getValue(I.getOperand(1));
2506 ISD::CondCode Condition, FOC, FPC;
2507 switch (predicate) {
2508 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2509 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2510 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2511 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2512 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2513 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2514 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2515 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2516 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2517 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2518 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2519 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2520 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2521 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2522 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2523 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2525 assert(!"Invalid VFCmp predicate value");
2526 FOC = FPC = ISD::SETFALSE;
2529 if (FiniteOnlyFPMath())
2534 MVT DestVT = TLI.getValueType(I.getType());
2536 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2539 void SelectionDAGLowering::visitSelect(User &I) {
2540 SDOperand Cond = getValue(I.getOperand(0));
2541 SDOperand TrueVal = getValue(I.getOperand(1));
2542 SDOperand FalseVal = getValue(I.getOperand(2));
2543 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2544 TrueVal, FalseVal));
2548 void SelectionDAGLowering::visitTrunc(User &I) {
2549 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2550 SDOperand N = getValue(I.getOperand(0));
2551 MVT DestVT = TLI.getValueType(I.getType());
2552 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2555 void SelectionDAGLowering::visitZExt(User &I) {
2556 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2557 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2558 SDOperand N = getValue(I.getOperand(0));
2559 MVT DestVT = TLI.getValueType(I.getType());
2560 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2563 void SelectionDAGLowering::visitSExt(User &I) {
2564 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2565 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2566 SDOperand N = getValue(I.getOperand(0));
2567 MVT DestVT = TLI.getValueType(I.getType());
2568 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2571 void SelectionDAGLowering::visitFPTrunc(User &I) {
2572 // FPTrunc is never a no-op cast, no need to check
2573 SDOperand N = getValue(I.getOperand(0));
2574 MVT DestVT = TLI.getValueType(I.getType());
2575 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2578 void SelectionDAGLowering::visitFPExt(User &I){
2579 // FPTrunc is never a no-op cast, no need to check
2580 SDOperand N = getValue(I.getOperand(0));
2581 MVT DestVT = TLI.getValueType(I.getType());
2582 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2585 void SelectionDAGLowering::visitFPToUI(User &I) {
2586 // FPToUI is never a no-op cast, no need to check
2587 SDOperand N = getValue(I.getOperand(0));
2588 MVT DestVT = TLI.getValueType(I.getType());
2589 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2592 void SelectionDAGLowering::visitFPToSI(User &I) {
2593 // FPToSI is never a no-op cast, no need to check
2594 SDOperand N = getValue(I.getOperand(0));
2595 MVT DestVT = TLI.getValueType(I.getType());
2596 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2599 void SelectionDAGLowering::visitUIToFP(User &I) {
2600 // UIToFP is never a no-op cast, no need to check
2601 SDOperand N = getValue(I.getOperand(0));
2602 MVT DestVT = TLI.getValueType(I.getType());
2603 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2606 void SelectionDAGLowering::visitSIToFP(User &I){
2607 // UIToFP is never a no-op cast, no need to check
2608 SDOperand N = getValue(I.getOperand(0));
2609 MVT DestVT = TLI.getValueType(I.getType());
2610 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2613 void SelectionDAGLowering::visitPtrToInt(User &I) {
2614 // What to do depends on the size of the integer and the size of the pointer.
2615 // We can either truncate, zero extend, or no-op, accordingly.
2616 SDOperand N = getValue(I.getOperand(0));
2617 MVT SrcVT = N.getValueType();
2618 MVT DestVT = TLI.getValueType(I.getType());
2620 if (DestVT.bitsLT(SrcVT))
2621 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2623 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2624 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2625 setValue(&I, Result);
2628 void SelectionDAGLowering::visitIntToPtr(User &I) {
2629 // What to do depends on the size of the integer and the size of the pointer.
2630 // We can either truncate, zero extend, or no-op, accordingly.
2631 SDOperand N = getValue(I.getOperand(0));
2632 MVT SrcVT = N.getValueType();
2633 MVT DestVT = TLI.getValueType(I.getType());
2634 if (DestVT.bitsLT(SrcVT))
2635 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2637 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2638 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2641 void SelectionDAGLowering::visitBitCast(User &I) {
2642 SDOperand N = getValue(I.getOperand(0));
2643 MVT DestVT = TLI.getValueType(I.getType());
2645 // BitCast assures us that source and destination are the same size so this
2646 // is either a BIT_CONVERT or a no-op.
2647 if (DestVT != N.getValueType())
2648 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2650 setValue(&I, N); // noop cast.
2653 void SelectionDAGLowering::visitInsertElement(User &I) {
2654 SDOperand InVec = getValue(I.getOperand(0));
2655 SDOperand InVal = getValue(I.getOperand(1));
2656 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2657 getValue(I.getOperand(2)));
2659 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2660 TLI.getValueType(I.getType()),
2661 InVec, InVal, InIdx));
2664 void SelectionDAGLowering::visitExtractElement(User &I) {
2665 SDOperand InVec = getValue(I.getOperand(0));
2666 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2667 getValue(I.getOperand(1)));
2668 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2669 TLI.getValueType(I.getType()), InVec, InIdx));
2672 void SelectionDAGLowering::visitShuffleVector(User &I) {
2673 SDOperand V1 = getValue(I.getOperand(0));
2674 SDOperand V2 = getValue(I.getOperand(1));
2675 SDOperand Mask = getValue(I.getOperand(2));
2677 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2678 TLI.getValueType(I.getType()),
2682 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2683 const Value *Op0 = I.getOperand(0);
2684 const Value *Op1 = I.getOperand(1);
2685 const Type *AggTy = I.getType();
2686 const Type *ValTy = Op1->getType();
2687 bool IntoUndef = isa<UndefValue>(Op0);
2688 bool FromUndef = isa<UndefValue>(Op1);
2690 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2691 I.idx_begin(), I.idx_end());
2693 SmallVector<MVT, 4> AggValueVTs;
2694 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2695 SmallVector<MVT, 4> ValValueVTs;
2696 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2698 unsigned NumAggValues = AggValueVTs.size();
2699 unsigned NumValValues = ValValueVTs.size();
2700 SmallVector<SDOperand, 4> Values(NumAggValues);
2702 SDOperand Agg = getValue(Op0);
2703 SDOperand Val = getValue(Op1);
2705 // Copy the beginning value(s) from the original aggregate.
2706 for (; i != LinearIndex; ++i)
2707 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2708 SDOperand(Agg.Val, Agg.ResNo + i);
2709 // Copy values from the inserted value(s).
2710 for (; i != LinearIndex + NumValValues; ++i)
2711 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2712 SDOperand(Val.Val, Val.ResNo + i - LinearIndex);
2713 // Copy remaining value(s) from the original aggregate.
2714 for (; i != NumAggValues; ++i)
2715 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2716 SDOperand(Agg.Val, Agg.ResNo + i);
2718 setValue(&I, DAG.getNode(ISD::MERGE_VALUES,
2719 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2720 &Values[0], NumAggValues));
2723 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2724 const Value *Op0 = I.getOperand(0);
2725 const Type *AggTy = Op0->getType();
2726 const Type *ValTy = I.getType();
2727 bool OutOfUndef = isa<UndefValue>(Op0);
2729 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2730 I.idx_begin(), I.idx_end());
2732 SmallVector<MVT, 4> ValValueVTs;
2733 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2735 unsigned NumValValues = ValValueVTs.size();
2736 SmallVector<SDOperand, 4> Values(NumValValues);
2738 SDOperand Agg = getValue(Op0);
2739 // Copy out the selected value(s).
2740 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2741 Values[i - LinearIndex] =
2742 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
2743 SDOperand(Agg.Val, Agg.ResNo + i);
2745 setValue(&I, DAG.getNode(ISD::MERGE_VALUES,
2746 DAG.getVTList(&ValValueVTs[0], NumValValues),
2747 &Values[0], NumValValues));
2751 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2752 SDOperand N = getValue(I.getOperand(0));
2753 const Type *Ty = I.getOperand(0)->getType();
2755 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2758 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2759 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2762 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2763 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2764 DAG.getIntPtrConstant(Offset));
2766 Ty = StTy->getElementType(Field);
2768 Ty = cast<SequentialType>(Ty)->getElementType();
2770 // If this is a constant subscript, handle it quickly.
2771 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2772 if (CI->getZExtValue() == 0) continue;
2774 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2775 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2776 DAG.getIntPtrConstant(Offs));
2780 // N = N + Idx * ElementSize;
2781 uint64_t ElementSize = TD->getABITypeSize(Ty);
2782 SDOperand IdxN = getValue(Idx);
2784 // If the index is smaller or larger than intptr_t, truncate or extend
2786 if (IdxN.getValueType().bitsLT(N.getValueType())) {
2787 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2788 } else if (IdxN.getValueType().bitsGT(N.getValueType()))
2789 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2791 // If this is a multiply by a power of two, turn it into a shl
2792 // immediately. This is a very common case.
2793 if (isPowerOf2_64(ElementSize)) {
2794 unsigned Amt = Log2_64(ElementSize);
2795 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2796 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2797 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2801 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2802 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2803 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2809 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2810 // If this is a fixed sized alloca in the entry block of the function,
2811 // allocate it statically on the stack.
2812 if (FuncInfo.StaticAllocaMap.count(&I))
2813 return; // getValue will auto-populate this.
2815 const Type *Ty = I.getAllocatedType();
2816 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2818 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2821 SDOperand AllocSize = getValue(I.getArraySize());
2822 MVT IntPtr = TLI.getPointerTy();
2823 if (IntPtr.bitsLT(AllocSize.getValueType()))
2824 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2825 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2826 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2828 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2829 DAG.getIntPtrConstant(TySize));
2831 // Handle alignment. If the requested alignment is less than or equal to
2832 // the stack alignment, ignore it. If the size is greater than or equal to
2833 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2834 unsigned StackAlign =
2835 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2836 if (Align <= StackAlign)
2839 // Round the size of the allocation up to the stack alignment size
2840 // by add SA-1 to the size.
2841 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2842 DAG.getIntPtrConstant(StackAlign-1));
2843 // Mask out the low bits for alignment purposes.
2844 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2845 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2847 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2848 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2850 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2852 DAG.setRoot(DSA.getValue(1));
2854 // Inform the Frame Information that we have just allocated a variable-sized
2856 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2859 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2860 const Value *SV = I.getOperand(0);
2861 SDOperand Ptr = getValue(SV);
2863 const Type *Ty = I.getType();
2864 bool isVolatile = I.isVolatile();
2865 unsigned Alignment = I.getAlignment();
2867 SmallVector<MVT, 4> ValueVTs;
2868 SmallVector<uint64_t, 4> Offsets;
2869 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2870 unsigned NumValues = ValueVTs.size();
2878 // Do not serialize non-volatile loads against each other.
2879 Root = DAG.getRoot();
2882 SmallVector<SDOperand, 4> Values(NumValues);
2883 SmallVector<SDOperand, 4> Chains(NumValues);
2884 MVT PtrVT = Ptr.getValueType();
2885 for (unsigned i = 0; i != NumValues; ++i) {
2886 SDOperand L = DAG.getLoad(ValueVTs[i], Root,
2887 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2888 DAG.getConstant(Offsets[i], PtrVT)),
2890 isVolatile, Alignment);
2892 Chains[i] = L.getValue(1);
2895 SDOperand Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2896 &Chains[0], NumValues);
2900 PendingLoads.push_back(Chain);
2902 setValue(&I, DAG.getNode(ISD::MERGE_VALUES,
2903 DAG.getVTList(&ValueVTs[0], NumValues),
2904 &Values[0], NumValues));
2908 void SelectionDAGLowering::visitStore(StoreInst &I) {
2909 Value *SrcV = I.getOperand(0);
2910 SDOperand Src = getValue(SrcV);
2911 Value *PtrV = I.getOperand(1);
2912 SDOperand Ptr = getValue(PtrV);
2914 SmallVector<MVT, 4> ValueVTs;
2915 SmallVector<uint64_t, 4> Offsets;
2916 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2917 unsigned NumValues = ValueVTs.size();
2921 SDOperand Root = getRoot();
2922 SmallVector<SDOperand, 4> Chains(NumValues);
2923 MVT PtrVT = Ptr.getValueType();
2924 bool isVolatile = I.isVolatile();
2925 unsigned Alignment = I.getAlignment();
2926 for (unsigned i = 0; i != NumValues; ++i)
2927 Chains[i] = DAG.getStore(Root, SDOperand(Src.Val, Src.ResNo + i),
2928 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2929 DAG.getConstant(Offsets[i], PtrVT)),
2931 isVolatile, Alignment);
2933 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2936 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2938 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2939 unsigned Intrinsic) {
2940 bool HasChain = !I.doesNotAccessMemory();
2941 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2943 // Build the operand list.
2944 SmallVector<SDOperand, 8> Ops;
2945 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2947 // We don't need to serialize loads against other loads.
2948 Ops.push_back(DAG.getRoot());
2950 Ops.push_back(getRoot());
2954 // Add the intrinsic ID as an integer operand.
2955 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2957 // Add all operands of the call to the operand list.
2958 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2959 SDOperand Op = getValue(I.getOperand(i));
2960 assert(TLI.isTypeLegal(Op.getValueType()) &&
2961 "Intrinsic uses a non-legal type?");
2965 std::vector<MVT> VTs;
2966 if (I.getType() != Type::VoidTy) {
2967 MVT VT = TLI.getValueType(I.getType());
2968 if (VT.isVector()) {
2969 const VectorType *DestTy = cast<VectorType>(I.getType());
2970 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2972 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2973 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2976 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2980 VTs.push_back(MVT::Other);
2982 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2987 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2988 &Ops[0], Ops.size());
2989 else if (I.getType() != Type::VoidTy)
2990 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2991 &Ops[0], Ops.size());
2993 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2994 &Ops[0], Ops.size());
2997 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2999 PendingLoads.push_back(Chain);
3003 if (I.getType() != Type::VoidTy) {
3004 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3005 MVT VT = TLI.getValueType(PTy);
3006 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
3008 setValue(&I, Result);
3012 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3013 static GlobalVariable *ExtractTypeInfo (Value *V) {
3014 V = V->stripPointerCasts();
3015 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3016 assert ((GV || isa<ConstantPointerNull>(V)) &&
3017 "TypeInfo must be a global variable or NULL");
3021 /// addCatchInfo - Extract the personality and type infos from an eh.selector
3022 /// call, and add them to the specified machine basic block.
3023 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3024 MachineBasicBlock *MBB) {
3025 // Inform the MachineModuleInfo of the personality for this landing pad.
3026 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3027 assert(CE->getOpcode() == Instruction::BitCast &&
3028 isa<Function>(CE->getOperand(0)) &&
3029 "Personality should be a function");
3030 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3032 // Gather all the type infos for this landing pad and pass them along to
3033 // MachineModuleInfo.
3034 std::vector<GlobalVariable *> TyInfo;
3035 unsigned N = I.getNumOperands();
3037 for (unsigned i = N - 1; i > 2; --i) {
3038 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3039 unsigned FilterLength = CI->getZExtValue();
3040 unsigned FirstCatch = i + FilterLength + !FilterLength;
3041 assert (FirstCatch <= N && "Invalid filter length");
3043 if (FirstCatch < N) {
3044 TyInfo.reserve(N - FirstCatch);
3045 for (unsigned j = FirstCatch; j < N; ++j)
3046 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3047 MMI->addCatchTypeInfo(MBB, TyInfo);
3051 if (!FilterLength) {
3053 MMI->addCleanup(MBB);
3056 TyInfo.reserve(FilterLength - 1);
3057 for (unsigned j = i + 1; j < FirstCatch; ++j)
3058 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3059 MMI->addFilterTypeInfo(MBB, TyInfo);
3068 TyInfo.reserve(N - 3);
3069 for (unsigned j = 3; j < N; ++j)
3070 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3071 MMI->addCatchTypeInfo(MBB, TyInfo);
3076 /// Inlined utility function to implement binary input atomic intrinsics for
3077 // visitIntrinsicCall: I is a call instruction
3078 // Op is the associated NodeType for I
3080 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3081 SDOperand Root = getRoot();
3082 SDOperand O2 = getValue(I.getOperand(2));
3083 SDOperand L = DAG.getAtomic(Op, Root,
3084 getValue(I.getOperand(1)),
3085 O2, O2.getValueType());
3087 DAG.setRoot(L.getValue(1));
3091 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3092 /// we want to emit this as a call to a named external function, return the name
3093 /// otherwise lower it and return null.
3095 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3096 switch (Intrinsic) {
3098 // By default, turn this into a target intrinsic node.
3099 visitTargetIntrinsic(I, Intrinsic);
3101 case Intrinsic::vastart: visitVAStart(I); return 0;
3102 case Intrinsic::vaend: visitVAEnd(I); return 0;
3103 case Intrinsic::vacopy: visitVACopy(I); return 0;
3104 case Intrinsic::returnaddress:
3105 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3106 getValue(I.getOperand(1))));
3108 case Intrinsic::frameaddress:
3109 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3110 getValue(I.getOperand(1))));
3112 case Intrinsic::setjmp:
3113 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3115 case Intrinsic::longjmp:
3116 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3118 case Intrinsic::memcpy_i32:
3119 case Intrinsic::memcpy_i64: {
3120 SDOperand Op1 = getValue(I.getOperand(1));
3121 SDOperand Op2 = getValue(I.getOperand(2));
3122 SDOperand Op3 = getValue(I.getOperand(3));
3123 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3124 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3125 I.getOperand(1), 0, I.getOperand(2), 0));
3128 case Intrinsic::memset_i32:
3129 case Intrinsic::memset_i64: {
3130 SDOperand Op1 = getValue(I.getOperand(1));
3131 SDOperand Op2 = getValue(I.getOperand(2));
3132 SDOperand Op3 = getValue(I.getOperand(3));
3133 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3134 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3135 I.getOperand(1), 0));
3138 case Intrinsic::memmove_i32:
3139 case Intrinsic::memmove_i64: {
3140 SDOperand Op1 = getValue(I.getOperand(1));
3141 SDOperand Op2 = getValue(I.getOperand(2));
3142 SDOperand Op3 = getValue(I.getOperand(3));
3143 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3145 // If the source and destination are known to not be aliases, we can
3146 // lower memmove as memcpy.
3147 uint64_t Size = -1ULL;
3148 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3149 Size = C->getValue();
3150 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3151 AliasAnalysis::NoAlias) {
3152 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3153 I.getOperand(1), 0, I.getOperand(2), 0));
3157 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3158 I.getOperand(1), 0, I.getOperand(2), 0));
3161 case Intrinsic::dbg_stoppoint: {
3162 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3163 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3164 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3168 Ops[1] = getValue(SPI.getLineValue());
3169 Ops[2] = getValue(SPI.getColumnValue());
3171 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3172 assert(DD && "Not a debug information descriptor");
3173 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
3175 Ops[3] = DAG.getString(CompileUnit->getFileName());
3176 Ops[4] = DAG.getString(CompileUnit->getDirectory());
3178 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
3183 case Intrinsic::dbg_region_start: {
3184 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3185 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3186 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3187 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3188 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3189 DAG.getConstant(LabelID, MVT::i32),
3190 DAG.getConstant(0, MVT::i32)));
3195 case Intrinsic::dbg_region_end: {
3196 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3197 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3198 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3199 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3200 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3201 DAG.getConstant(LabelID, MVT::i32),
3202 DAG.getConstant(0, MVT::i32)));
3207 case Intrinsic::dbg_func_start: {
3208 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3210 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3211 Value *SP = FSI.getSubprogram();
3212 if (SP && MMI->Verify(SP)) {
3213 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3214 // what (most?) gdb expects.
3215 DebugInfoDesc *DD = MMI->getDescFor(SP);
3216 assert(DD && "Not a debug information descriptor");
3217 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3218 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3219 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(),
3220 CompileUnit->getFileName());
3221 // Record the source line but does create a label. It will be emitted
3222 // at asm emission time.
3223 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3228 case Intrinsic::dbg_declare: {
3229 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3230 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3231 Value *Variable = DI.getVariable();
3232 if (MMI && Variable && MMI->Verify(Variable))
3233 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3234 getValue(DI.getAddress()), getValue(Variable)));
3238 case Intrinsic::eh_exception: {
3239 if (!CurMBB->isLandingPad()) {
3240 // FIXME: Mark exception register as live in. Hack for PR1508.
3241 unsigned Reg = TLI.getExceptionAddressRegister();
3242 if (Reg) CurMBB->addLiveIn(Reg);
3244 // Insert the EXCEPTIONADDR instruction.
3245 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3247 Ops[0] = DAG.getRoot();
3248 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3250 DAG.setRoot(Op.getValue(1));
3254 case Intrinsic::eh_selector_i32:
3255 case Intrinsic::eh_selector_i64: {
3256 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3257 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3258 MVT::i32 : MVT::i64);
3261 if (CurMBB->isLandingPad())
3262 addCatchInfo(I, MMI, CurMBB);
3265 FuncInfo.CatchInfoLost.insert(&I);
3267 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3268 unsigned Reg = TLI.getExceptionSelectorRegister();
3269 if (Reg) CurMBB->addLiveIn(Reg);
3272 // Insert the EHSELECTION instruction.
3273 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3275 Ops[0] = getValue(I.getOperand(1));
3277 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3279 DAG.setRoot(Op.getValue(1));
3281 setValue(&I, DAG.getConstant(0, VT));
3287 case Intrinsic::eh_typeid_for_i32:
3288 case Intrinsic::eh_typeid_for_i64: {
3289 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3290 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3291 MVT::i32 : MVT::i64);
3294 // Find the type id for the given typeinfo.
3295 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3297 unsigned TypeID = MMI->getTypeIDFor(GV);
3298 setValue(&I, DAG.getConstant(TypeID, VT));
3300 // Return something different to eh_selector.
3301 setValue(&I, DAG.getConstant(1, VT));
3307 case Intrinsic::eh_return: {
3308 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3311 MMI->setCallsEHReturn(true);
3312 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3315 getValue(I.getOperand(1)),
3316 getValue(I.getOperand(2))));
3318 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3324 case Intrinsic::eh_unwind_init: {
3325 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3326 MMI->setCallsUnwindInit(true);
3332 case Intrinsic::eh_dwarf_cfa: {
3333 MVT VT = getValue(I.getOperand(1)).getValueType();
3335 if (VT.bitsGT(TLI.getPointerTy()))
3336 CfaArg = DAG.getNode(ISD::TRUNCATE,
3337 TLI.getPointerTy(), getValue(I.getOperand(1)));
3339 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3340 TLI.getPointerTy(), getValue(I.getOperand(1)));
3342 SDOperand Offset = DAG.getNode(ISD::ADD,
3344 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3345 TLI.getPointerTy()),
3347 setValue(&I, DAG.getNode(ISD::ADD,
3349 DAG.getNode(ISD::FRAMEADDR,
3352 TLI.getPointerTy())),
3357 case Intrinsic::sqrt:
3358 setValue(&I, DAG.getNode(ISD::FSQRT,
3359 getValue(I.getOperand(1)).getValueType(),
3360 getValue(I.getOperand(1))));
3362 case Intrinsic::powi:
3363 setValue(&I, DAG.getNode(ISD::FPOWI,
3364 getValue(I.getOperand(1)).getValueType(),
3365 getValue(I.getOperand(1)),
3366 getValue(I.getOperand(2))));
3368 case Intrinsic::sin:
3369 setValue(&I, DAG.getNode(ISD::FSIN,
3370 getValue(I.getOperand(1)).getValueType(),
3371 getValue(I.getOperand(1))));
3373 case Intrinsic::cos:
3374 setValue(&I, DAG.getNode(ISD::FCOS,
3375 getValue(I.getOperand(1)).getValueType(),
3376 getValue(I.getOperand(1))));
3378 case Intrinsic::pow:
3379 setValue(&I, DAG.getNode(ISD::FPOW,
3380 getValue(I.getOperand(1)).getValueType(),
3381 getValue(I.getOperand(1)),
3382 getValue(I.getOperand(2))));
3384 case Intrinsic::pcmarker: {
3385 SDOperand Tmp = getValue(I.getOperand(1));
3386 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3389 case Intrinsic::readcyclecounter: {
3390 SDOperand Op = getRoot();
3391 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3392 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3395 DAG.setRoot(Tmp.getValue(1));
3398 case Intrinsic::part_select: {
3399 // Currently not implemented: just abort
3400 assert(0 && "part_select intrinsic not implemented");
3403 case Intrinsic::part_set: {
3404 // Currently not implemented: just abort
3405 assert(0 && "part_set intrinsic not implemented");
3408 case Intrinsic::bswap:
3409 setValue(&I, DAG.getNode(ISD::BSWAP,
3410 getValue(I.getOperand(1)).getValueType(),
3411 getValue(I.getOperand(1))));
3413 case Intrinsic::cttz: {
3414 SDOperand Arg = getValue(I.getOperand(1));
3415 MVT Ty = Arg.getValueType();
3416 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3417 setValue(&I, result);
3420 case Intrinsic::ctlz: {
3421 SDOperand Arg = getValue(I.getOperand(1));
3422 MVT Ty = Arg.getValueType();
3423 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3424 setValue(&I, result);
3427 case Intrinsic::ctpop: {
3428 SDOperand Arg = getValue(I.getOperand(1));
3429 MVT Ty = Arg.getValueType();
3430 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3431 setValue(&I, result);
3434 case Intrinsic::stacksave: {
3435 SDOperand Op = getRoot();
3436 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
3437 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3439 DAG.setRoot(Tmp.getValue(1));
3442 case Intrinsic::stackrestore: {
3443 SDOperand Tmp = getValue(I.getOperand(1));
3444 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3447 case Intrinsic::var_annotation:
3448 // Discard annotate attributes
3451 case Intrinsic::init_trampoline: {
3452 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3456 Ops[1] = getValue(I.getOperand(1));
3457 Ops[2] = getValue(I.getOperand(2));
3458 Ops[3] = getValue(I.getOperand(3));
3459 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3460 Ops[5] = DAG.getSrcValue(F);
3462 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
3463 DAG.getNodeValueTypes(TLI.getPointerTy(),
3468 DAG.setRoot(Tmp.getValue(1));
3472 case Intrinsic::gcroot:
3474 Value *Alloca = I.getOperand(1);
3475 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3477 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3478 GCI->addStackRoot(FI->getIndex(), TypeMap);
3482 case Intrinsic::gcread:
3483 case Intrinsic::gcwrite:
3484 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3487 case Intrinsic::flt_rounds: {
3488 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3492 case Intrinsic::trap: {
3493 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3496 case Intrinsic::prefetch: {
3499 Ops[1] = getValue(I.getOperand(1));
3500 Ops[2] = getValue(I.getOperand(2));
3501 Ops[3] = getValue(I.getOperand(3));
3502 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3506 case Intrinsic::memory_barrier: {
3509 for (int x = 1; x < 6; ++x)
3510 Ops[x] = getValue(I.getOperand(x));
3512 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3515 case Intrinsic::atomic_lcs: {
3516 SDOperand Root = getRoot();
3517 SDOperand O3 = getValue(I.getOperand(3));
3518 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LCS, Root,
3519 getValue(I.getOperand(1)),
3520 getValue(I.getOperand(2)),
3521 O3, O3.getValueType());
3523 DAG.setRoot(L.getValue(1));
3526 case Intrinsic::atomic_las:
3527 return implVisitBinaryAtomic(I, ISD::ATOMIC_LAS);
3528 case Intrinsic::atomic_lss:
3529 return implVisitBinaryAtomic(I, ISD::ATOMIC_LSS);
3530 case Intrinsic::atomic_load_and:
3531 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3532 case Intrinsic::atomic_load_or:
3533 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3534 case Intrinsic::atomic_load_xor:
3535 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
3536 case Intrinsic::atomic_load_nand:
3537 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
3538 case Intrinsic::atomic_load_min:
3539 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3540 case Intrinsic::atomic_load_max:
3541 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3542 case Intrinsic::atomic_load_umin:
3543 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3544 case Intrinsic::atomic_load_umax:
3545 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3546 case Intrinsic::atomic_swap:
3547 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
3552 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
3554 MachineBasicBlock *LandingPad) {
3555 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3556 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3557 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3558 unsigned BeginLabel = 0, EndLabel = 0;
3560 TargetLowering::ArgListTy Args;
3561 TargetLowering::ArgListEntry Entry;
3562 Args.reserve(CS.arg_size());
3563 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3565 SDOperand ArgNode = getValue(*i);
3566 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3568 unsigned attrInd = i - CS.arg_begin() + 1;
3569 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3570 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3571 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3572 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3573 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3574 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3575 Entry.Alignment = CS.getParamAlignment(attrInd);
3576 Args.push_back(Entry);
3579 if (LandingPad && MMI) {
3580 // Insert a label before the invoke call to mark the try range. This can be
3581 // used to detect deletion of the invoke via the MachineModuleInfo.
3582 BeginLabel = MMI->NextLabelID();
3583 // Both PendingLoads and PendingExports must be flushed here;
3584 // this call might not return.
3586 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getControlRoot(),
3587 DAG.getConstant(BeginLabel, MVT::i32),
3588 DAG.getConstant(1, MVT::i32)));
3591 std::pair<SDOperand,SDOperand> Result =
3592 TLI.LowerCallTo(getRoot(), CS.getType(),
3593 CS.paramHasAttr(0, ParamAttr::SExt),
3594 CS.paramHasAttr(0, ParamAttr::ZExt),
3595 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3597 if (CS.getType() != Type::VoidTy)
3598 setValue(CS.getInstruction(), Result.first);
3599 DAG.setRoot(Result.second);
3601 if (LandingPad && MMI) {
3602 // Insert a label at the end of the invoke call to mark the try range. This
3603 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3604 EndLabel = MMI->NextLabelID();
3605 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3606 DAG.getConstant(EndLabel, MVT::i32),
3607 DAG.getConstant(1, MVT::i32)));
3609 // Inform MachineModuleInfo of range.
3610 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3615 void SelectionDAGLowering::visitCall(CallInst &I) {
3616 const char *RenameFn = 0;
3617 if (Function *F = I.getCalledFunction()) {
3618 if (F->isDeclaration()) {
3619 if (unsigned IID = F->getIntrinsicID()) {
3620 RenameFn = visitIntrinsicCall(I, IID);
3626 // Check for well-known libc/libm calls. If the function is internal, it
3627 // can't be a library call.
3628 unsigned NameLen = F->getNameLen();
3629 if (!F->hasInternalLinkage() && NameLen) {
3630 const char *NameStr = F->getNameStart();
3631 if (NameStr[0] == 'c' &&
3632 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3633 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3634 if (I.getNumOperands() == 3 && // Basic sanity checks.
3635 I.getOperand(1)->getType()->isFloatingPoint() &&
3636 I.getType() == I.getOperand(1)->getType() &&
3637 I.getType() == I.getOperand(2)->getType()) {
3638 SDOperand LHS = getValue(I.getOperand(1));
3639 SDOperand RHS = getValue(I.getOperand(2));
3640 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3644 } else if (NameStr[0] == 'f' &&
3645 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3646 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3647 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3648 if (I.getNumOperands() == 2 && // Basic sanity checks.
3649 I.getOperand(1)->getType()->isFloatingPoint() &&
3650 I.getType() == I.getOperand(1)->getType()) {
3651 SDOperand Tmp = getValue(I.getOperand(1));
3652 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3655 } else if (NameStr[0] == 's' &&
3656 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3657 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3658 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3659 if (I.getNumOperands() == 2 && // Basic sanity checks.
3660 I.getOperand(1)->getType()->isFloatingPoint() &&
3661 I.getType() == I.getOperand(1)->getType()) {
3662 SDOperand Tmp = getValue(I.getOperand(1));
3663 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3666 } else if (NameStr[0] == 'c' &&
3667 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3668 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3669 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3670 if (I.getNumOperands() == 2 && // Basic sanity checks.
3671 I.getOperand(1)->getType()->isFloatingPoint() &&
3672 I.getType() == I.getOperand(1)->getType()) {
3673 SDOperand Tmp = getValue(I.getOperand(1));
3674 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3679 } else if (isa<InlineAsm>(I.getOperand(0))) {
3686 Callee = getValue(I.getOperand(0));
3688 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3690 LowerCallTo(&I, Callee, I.isTailCall());
3694 void SelectionDAGLowering::visitGetResult(GetResultInst &I) {
3695 if (isa<UndefValue>(I.getOperand(0))) {
3696 SDOperand Undef = DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType()));
3697 setValue(&I, Undef);
3701 // To add support for individual return values with aggregate types,
3702 // we'd need a way to take a getresult index and determine which
3703 // values of the Call SDNode are associated with it.
3704 assert(TLI.getValueType(I.getType(), true) != MVT::Other &&
3705 "Individual return values must not be aggregates!");
3707 SDOperand Call = getValue(I.getOperand(0));
3708 setValue(&I, SDOperand(Call.Val, I.getIndex()));
3712 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3713 /// this value and returns the result as a ValueVT value. This uses
3714 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3715 /// If the Flag pointer is NULL, no flag is used.
3716 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3718 SDOperand *Flag) const {
3719 // Assemble the legal parts into the final values.
3720 SmallVector<SDOperand, 4> Values(ValueVTs.size());
3721 SmallVector<SDOperand, 8> Parts;
3722 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3723 // Copy the legal parts from the registers.
3724 MVT ValueVT = ValueVTs[Value];
3725 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3726 MVT RegisterVT = RegVTs[Value];
3728 Parts.resize(NumRegs);
3729 for (unsigned i = 0; i != NumRegs; ++i) {
3732 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3734 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3735 *Flag = P.getValue(2);
3737 Chain = P.getValue(1);
3739 // If the source register was virtual and if we know something about it,
3740 // add an assert node.
3741 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
3742 RegisterVT.isInteger() && !RegisterVT.isVector()) {
3743 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
3744 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
3745 if (FLI.LiveOutRegInfo.size() > SlotNo) {
3746 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
3748 unsigned RegSize = RegisterVT.getSizeInBits();
3749 unsigned NumSignBits = LOI.NumSignBits;
3750 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
3752 // FIXME: We capture more information than the dag can represent. For
3753 // now, just use the tightest assertzext/assertsext possible.
3755 MVT FromVT(MVT::Other);
3756 if (NumSignBits == RegSize)
3757 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
3758 else if (NumZeroBits >= RegSize-1)
3759 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
3760 else if (NumSignBits > RegSize-8)
3761 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
3762 else if (NumZeroBits >= RegSize-9)
3763 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
3764 else if (NumSignBits > RegSize-16)
3765 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
3766 else if (NumZeroBits >= RegSize-17)
3767 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
3768 else if (NumSignBits > RegSize-32)
3769 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
3770 else if (NumZeroBits >= RegSize-33)
3771 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
3773 if (FromVT != MVT::Other) {
3774 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
3775 RegisterVT, P, DAG.getValueType(FromVT));
3784 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3789 if (ValueVTs.size() == 1)
3792 return DAG.getNode(ISD::MERGE_VALUES,
3793 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3794 &Values[0], ValueVTs.size());
3797 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3798 /// specified value into the registers specified by this object. This uses
3799 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3800 /// If the Flag pointer is NULL, no flag is used.
3801 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3802 SDOperand &Chain, SDOperand *Flag) const {
3803 // Get the list of the values's legal parts.
3804 unsigned NumRegs = Regs.size();
3805 SmallVector<SDOperand, 8> Parts(NumRegs);
3806 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3807 MVT ValueVT = ValueVTs[Value];
3808 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3809 MVT RegisterVT = RegVTs[Value];
3811 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3812 &Parts[Part], NumParts, RegisterVT);
3816 // Copy the parts into the registers.
3817 SmallVector<SDOperand, 8> Chains(NumRegs);
3818 for (unsigned i = 0; i != NumRegs; ++i) {
3821 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3823 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3824 *Flag = Part.getValue(1);
3826 Chains[i] = Part.getValue(0);
3829 if (NumRegs == 1 || Flag)
3830 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3831 // flagged to it. That is the CopyToReg nodes and the user are considered
3832 // a single scheduling unit. If we create a TokenFactor and return it as
3833 // chain, then the TokenFactor is both a predecessor (operand) of the
3834 // user as well as a successor (the TF operands are flagged to the user).
3835 // c1, f1 = CopyToReg
3836 // c2, f2 = CopyToReg
3837 // c3 = TokenFactor c1, c2
3840 Chain = Chains[NumRegs-1];
3842 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3845 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3846 /// operand list. This adds the code marker and includes the number of
3847 /// values added into it.
3848 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3849 std::vector<SDOperand> &Ops) const {
3850 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3851 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3852 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3853 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3854 MVT RegisterVT = RegVTs[Value];
3855 for (unsigned i = 0; i != NumRegs; ++i)
3856 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3860 /// isAllocatableRegister - If the specified register is safe to allocate,
3861 /// i.e. it isn't a stack pointer or some other special register, return the
3862 /// register class for the register. Otherwise, return null.
3863 static const TargetRegisterClass *
3864 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3865 const TargetLowering &TLI,
3866 const TargetRegisterInfo *TRI) {
3867 MVT FoundVT = MVT::Other;
3868 const TargetRegisterClass *FoundRC = 0;
3869 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3870 E = TRI->regclass_end(); RCI != E; ++RCI) {
3871 MVT ThisVT = MVT::Other;
3873 const TargetRegisterClass *RC = *RCI;
3874 // If none of the the value types for this register class are valid, we
3875 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3876 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3878 if (TLI.isTypeLegal(*I)) {
3879 // If we have already found this register in a different register class,
3880 // choose the one with the largest VT specified. For example, on
3881 // PowerPC, we favor f64 register classes over f32.
3882 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
3889 if (ThisVT == MVT::Other) continue;
3891 // NOTE: This isn't ideal. In particular, this might allocate the
3892 // frame pointer in functions that need it (due to them not being taken
3893 // out of allocation, because a variable sized allocation hasn't been seen
3894 // yet). This is a slight code pessimization, but should still work.
3895 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3896 E = RC->allocation_order_end(MF); I != E; ++I)
3898 // We found a matching register class. Keep looking at others in case
3899 // we find one with larger registers that this physreg is also in.
3910 /// AsmOperandInfo - This contains information for each constraint that we are
3912 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3913 /// CallOperand - If this is the result output operand or a clobber
3914 /// this is null, otherwise it is the incoming operand to the CallInst.
3915 /// This gets modified as the asm is processed.
3916 SDOperand CallOperand;
3918 /// AssignedRegs - If this is a register or register class operand, this
3919 /// contains the set of register corresponding to the operand.
3920 RegsForValue AssignedRegs;
3922 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3923 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3926 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3927 /// busy in OutputRegs/InputRegs.
3928 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3929 std::set<unsigned> &OutputRegs,
3930 std::set<unsigned> &InputRegs,
3931 const TargetRegisterInfo &TRI) const {
3933 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3934 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3937 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3938 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3943 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3945 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3946 const TargetRegisterInfo &TRI) {
3947 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3949 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3950 for (; *Aliases; ++Aliases)
3951 Regs.insert(*Aliases);
3954 } // end anon namespace.
3957 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3958 /// specified operand. We prefer to assign virtual registers, to allow the
3959 /// register allocator handle the assignment process. However, if the asm uses
3960 /// features that we can't model on machineinstrs, we have SDISel do the
3961 /// allocation. This produces generally horrible, but correct, code.
3963 /// OpInfo describes the operand.
3964 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3965 /// or any explicitly clobbered registers.
3966 /// Input and OutputRegs are the set of already allocated physical registers.
3968 void SelectionDAGLowering::
3969 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3970 std::set<unsigned> &OutputRegs,
3971 std::set<unsigned> &InputRegs) {
3972 // Compute whether this value requires an input register, an output register,
3974 bool isOutReg = false;
3975 bool isInReg = false;
3976 switch (OpInfo.Type) {
3977 case InlineAsm::isOutput:
3980 // If this is an early-clobber output, or if there is an input
3981 // constraint that matches this, we need to reserve the input register
3982 // so no other inputs allocate to it.
3983 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3985 case InlineAsm::isInput:
3989 case InlineAsm::isClobber:
3996 MachineFunction &MF = DAG.getMachineFunction();
3997 SmallVector<unsigned, 4> Regs;
3999 // If this is a constraint for a single physreg, or a constraint for a
4000 // register class, find it.
4001 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4002 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4003 OpInfo.ConstraintVT);
4005 unsigned NumRegs = 1;
4006 if (OpInfo.ConstraintVT != MVT::Other)
4007 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4009 MVT ValueVT = OpInfo.ConstraintVT;
4012 // If this is a constraint for a specific physical register, like {r17},
4014 if (PhysReg.first) {
4015 if (OpInfo.ConstraintVT == MVT::Other)
4016 ValueVT = *PhysReg.second->vt_begin();
4018 // Get the actual register value type. This is important, because the user
4019 // may have asked for (e.g.) the AX register in i32 type. We need to
4020 // remember that AX is actually i16 to get the right extension.
4021 RegVT = *PhysReg.second->vt_begin();
4023 // This is a explicit reference to a physical register.
4024 Regs.push_back(PhysReg.first);
4026 // If this is an expanded reference, add the rest of the regs to Regs.
4028 TargetRegisterClass::iterator I = PhysReg.second->begin();
4029 for (; *I != PhysReg.first; ++I)
4030 assert(I != PhysReg.second->end() && "Didn't find reg!");
4032 // Already added the first reg.
4034 for (; NumRegs; --NumRegs, ++I) {
4035 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4039 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4040 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4041 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4045 // Otherwise, if this was a reference to an LLVM register class, create vregs
4046 // for this reference.
4047 std::vector<unsigned> RegClassRegs;
4048 const TargetRegisterClass *RC = PhysReg.second;
4050 // If this is an early clobber or tied register, our regalloc doesn't know
4051 // how to maintain the constraint. If it isn't, go ahead and create vreg
4052 // and let the regalloc do the right thing.
4053 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4054 // If there is some other early clobber and this is an input register,
4055 // then we are forced to pre-allocate the input reg so it doesn't
4056 // conflict with the earlyclobber.
4057 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
4058 RegVT = *PhysReg.second->vt_begin();
4060 if (OpInfo.ConstraintVT == MVT::Other)
4063 // Create the appropriate number of virtual registers.
4064 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4065 for (; NumRegs; --NumRegs)
4066 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4068 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4072 // Otherwise, we can't allocate it. Let the code below figure out how to
4073 // maintain these constraints.
4074 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4077 // This is a reference to a register class that doesn't directly correspond
4078 // to an LLVM register class. Allocate NumRegs consecutive, available,
4079 // registers from the class.
4080 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4081 OpInfo.ConstraintVT);
4084 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4085 unsigned NumAllocated = 0;
4086 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4087 unsigned Reg = RegClassRegs[i];
4088 // See if this register is available.
4089 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4090 (isInReg && InputRegs.count(Reg))) { // Already used.
4091 // Make sure we find consecutive registers.
4096 // Check to see if this register is allocatable (i.e. don't give out the
4099 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4100 if (!RC) { // Couldn't allocate this register.
4101 // Reset NumAllocated to make sure we return consecutive registers.
4107 // Okay, this register is good, we can use it.
4110 // If we allocated enough consecutive registers, succeed.
4111 if (NumAllocated == NumRegs) {
4112 unsigned RegStart = (i-NumAllocated)+1;
4113 unsigned RegEnd = i+1;
4114 // Mark all of the allocated registers used.
4115 for (unsigned i = RegStart; i != RegEnd; ++i)
4116 Regs.push_back(RegClassRegs[i]);
4118 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4119 OpInfo.ConstraintVT);
4120 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4125 // Otherwise, we couldn't allocate enough registers for this.
4129 /// visitInlineAsm - Handle a call to an InlineAsm object.
4131 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4132 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4134 /// ConstraintOperands - Information about all of the constraints.
4135 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4137 SDOperand Chain = getRoot();
4140 std::set<unsigned> OutputRegs, InputRegs;
4142 // Do a prepass over the constraints, canonicalizing them, and building up the
4143 // ConstraintOperands list.
4144 std::vector<InlineAsm::ConstraintInfo>
4145 ConstraintInfos = IA->ParseConstraints();
4147 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4148 // constraint. If so, we can't let the register allocator allocate any input
4149 // registers, because it will not know to avoid the earlyclobbered output reg.
4150 bool SawEarlyClobber = false;
4152 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4153 unsigned ResNo = 0; // ResNo - The result number of the next output.
4154 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4155 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4156 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4158 MVT OpVT = MVT::Other;
4160 // Compute the value type for each operand.
4161 switch (OpInfo.Type) {
4162 case InlineAsm::isOutput:
4163 // Indirect outputs just consume an argument.
4164 if (OpInfo.isIndirect) {
4165 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4168 // The return value of the call is this value. As such, there is no
4169 // corresponding argument.
4170 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4171 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4172 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4174 assert(ResNo == 0 && "Asm only has one result!");
4175 OpVT = TLI.getValueType(CS.getType());
4179 case InlineAsm::isInput:
4180 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4182 case InlineAsm::isClobber:
4187 // If this is an input or an indirect output, process the call argument.
4188 // BasicBlocks are labels, currently appearing only in asm's.
4189 if (OpInfo.CallOperandVal) {
4190 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4191 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4193 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4194 const Type *OpTy = OpInfo.CallOperandVal->getType();
4195 // If this is an indirect operand, the operand is a pointer to the
4197 if (OpInfo.isIndirect)
4198 OpTy = cast<PointerType>(OpTy)->getElementType();
4200 // If OpTy is not a single value, it may be a struct/union that we
4201 // can tile with integers.
4202 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4203 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4211 OpTy = IntegerType::get(BitSize);
4216 OpVT = TLI.getValueType(OpTy, true);
4220 OpInfo.ConstraintVT = OpVT;
4222 // Compute the constraint code and ConstraintType to use.
4223 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
4225 // Keep track of whether we see an earlyclobber.
4226 SawEarlyClobber |= OpInfo.isEarlyClobber;
4228 // If we see a clobber of a register, it is an early clobber.
4229 if (!SawEarlyClobber &&
4230 OpInfo.Type == InlineAsm::isClobber &&
4231 OpInfo.ConstraintType == TargetLowering::C_Register) {
4232 // Note that we want to ignore things that we don't trick here, like
4233 // dirflag, fpsr, flags, etc.
4234 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4235 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4236 OpInfo.ConstraintVT);
4237 if (PhysReg.first || PhysReg.second) {
4238 // This is a register we know of.
4239 SawEarlyClobber = true;
4243 // If this is a memory input, and if the operand is not indirect, do what we
4244 // need to to provide an address for the memory input.
4245 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4246 !OpInfo.isIndirect) {
4247 assert(OpInfo.Type == InlineAsm::isInput &&
4248 "Can only indirectify direct input operands!");
4250 // Memory operands really want the address of the value. If we don't have
4251 // an indirect input, put it in the constpool if we can, otherwise spill
4252 // it to a stack slot.
4254 // If the operand is a float, integer, or vector constant, spill to a
4255 // constant pool entry to get its address.
4256 Value *OpVal = OpInfo.CallOperandVal;
4257 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4258 isa<ConstantVector>(OpVal)) {
4259 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4260 TLI.getPointerTy());
4262 // Otherwise, create a stack slot and emit a store to it before the
4264 const Type *Ty = OpVal->getType();
4265 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4266 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4267 MachineFunction &MF = DAG.getMachineFunction();
4268 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4269 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4270 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4271 OpInfo.CallOperand = StackSlot;
4274 // There is no longer a Value* corresponding to this operand.
4275 OpInfo.CallOperandVal = 0;
4276 // It is now an indirect operand.
4277 OpInfo.isIndirect = true;
4280 // If this constraint is for a specific register, allocate it before
4282 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4283 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4285 ConstraintInfos.clear();
4288 // Second pass - Loop over all of the operands, assigning virtual or physregs
4289 // to registerclass operands.
4290 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4291 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4293 // C_Register operands have already been allocated, Other/Memory don't need
4295 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4296 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4299 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4300 std::vector<SDOperand> AsmNodeOperands;
4301 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
4302 AsmNodeOperands.push_back(
4303 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4306 // Loop over all of the inputs, copying the operand values into the
4307 // appropriate registers and processing the output regs.
4308 RegsForValue RetValRegs;
4310 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4311 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4313 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4314 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4316 switch (OpInfo.Type) {
4317 case InlineAsm::isOutput: {
4318 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4319 OpInfo.ConstraintType != TargetLowering::C_Register) {
4320 // Memory output, or 'other' output (e.g. 'X' constraint).
4321 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4323 // Add information to the INLINEASM node to know about this output.
4324 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4325 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4326 TLI.getPointerTy()));
4327 AsmNodeOperands.push_back(OpInfo.CallOperand);
4331 // Otherwise, this is a register or register class output.
4333 // Copy the output from the appropriate register. Find a register that
4335 if (OpInfo.AssignedRegs.Regs.empty()) {
4336 cerr << "Couldn't allocate output reg for constraint '"
4337 << OpInfo.ConstraintCode << "'!\n";
4341 // If this is an indirect operand, store through the pointer after the
4343 if (OpInfo.isIndirect) {
4344 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4345 OpInfo.CallOperandVal));
4347 // This is the result value of the call.
4348 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4349 // Concatenate this output onto the outputs list.
4350 RetValRegs.append(OpInfo.AssignedRegs);
4353 // Add information to the INLINEASM node to know that this register is
4355 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4359 case InlineAsm::isInput: {
4360 SDOperand InOperandVal = OpInfo.CallOperand;
4362 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4363 // If this is required to match an output register we have already set,
4364 // just use its register.
4365 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4367 // Scan until we find the definition we already emitted of this operand.
4368 // When we find it, create a RegsForValue operand.
4369 unsigned CurOp = 2; // The first operand.
4370 for (; OperandNo; --OperandNo) {
4371 // Advance to the next operand.
4373 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4374 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4375 (NumOps & 7) == 4 /*MEM*/) &&
4376 "Skipped past definitions?");
4377 CurOp += (NumOps>>3)+1;
4381 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4382 if ((NumOps & 7) == 2 /*REGDEF*/) {
4383 // Add NumOps>>3 registers to MatchedRegs.
4384 RegsForValue MatchedRegs;
4385 MatchedRegs.TLI = &TLI;
4386 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4387 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4388 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4390 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4391 MatchedRegs.Regs.push_back(Reg);
4394 // Use the produced MatchedRegs object to
4395 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4396 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4399 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4400 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4401 // Add information to the INLINEASM node to know about this input.
4402 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4403 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4404 TLI.getPointerTy()));
4405 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4410 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4411 assert(!OpInfo.isIndirect &&
4412 "Don't know how to handle indirect other inputs yet!");
4414 std::vector<SDOperand> Ops;
4415 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4418 cerr << "Invalid operand for inline asm constraint '"
4419 << OpInfo.ConstraintCode << "'!\n";
4423 // Add information to the INLINEASM node to know about this input.
4424 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4425 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4426 TLI.getPointerTy()));
4427 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4429 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4430 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4431 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4432 "Memory operands expect pointer values");
4434 // Add information to the INLINEASM node to know about this input.
4435 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4436 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4437 TLI.getPointerTy()));
4438 AsmNodeOperands.push_back(InOperandVal);
4442 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4443 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4444 "Unknown constraint type!");
4445 assert(!OpInfo.isIndirect &&
4446 "Don't know how to handle indirect register inputs yet!");
4448 // Copy the input into the appropriate registers.
4449 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4450 "Couldn't allocate input reg!");
4452 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4454 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4458 case InlineAsm::isClobber: {
4459 // Add the clobbered value to the operand list, so that the register
4460 // allocator is aware that the physreg got clobbered.
4461 if (!OpInfo.AssignedRegs.Regs.empty())
4462 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4469 // Finish up input operands.
4470 AsmNodeOperands[0] = Chain;
4471 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4473 Chain = DAG.getNode(ISD::INLINEASM,
4474 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4475 &AsmNodeOperands[0], AsmNodeOperands.size());
4476 Flag = Chain.getValue(1);
4478 // If this asm returns a register value, copy the result from that register
4479 // and set it as the value of the call.
4480 if (!RetValRegs.Regs.empty()) {
4481 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4483 // If any of the results of the inline asm is a vector, it may have the
4484 // wrong width/num elts. This can happen for register classes that can
4485 // contain multiple different value types. The preg or vreg allocated may
4486 // not have the same VT as was expected. Convert it to the right type with
4488 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4489 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4490 if (Val.Val->getValueType(i).isVector())
4491 Val = DAG.getNode(ISD::BIT_CONVERT,
4492 TLI.getValueType(ResSTy->getElementType(i)), Val);
4495 if (Val.getValueType().isVector())
4496 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4500 setValue(CS.getInstruction(), Val);
4503 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
4505 // Process indirect outputs, first output all of the flagged copies out of
4507 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4508 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4509 Value *Ptr = IndirectStoresToEmit[i].second;
4510 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4511 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4514 // Emit the non-flagged stores from the physregs.
4515 SmallVector<SDOperand, 8> OutChains;
4516 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4517 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4518 getValue(StoresToEmit[i].second),
4519 StoresToEmit[i].second, 0));
4520 if (!OutChains.empty())
4521 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4522 &OutChains[0], OutChains.size());
4527 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4528 SDOperand Src = getValue(I.getOperand(0));
4530 MVT IntPtr = TLI.getPointerTy();
4532 if (IntPtr.bitsLT(Src.getValueType()))
4533 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4534 else if (IntPtr.bitsGT(Src.getValueType()))
4535 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4537 // Scale the source by the type size.
4538 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4539 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4540 Src, DAG.getIntPtrConstant(ElementSize));
4542 TargetLowering::ArgListTy Args;
4543 TargetLowering::ArgListEntry Entry;
4545 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4546 Args.push_back(Entry);
4548 std::pair<SDOperand,SDOperand> Result =
4549 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4550 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4551 setValue(&I, Result.first); // Pointers always fit in registers
4552 DAG.setRoot(Result.second);
4555 void SelectionDAGLowering::visitFree(FreeInst &I) {
4556 TargetLowering::ArgListTy Args;
4557 TargetLowering::ArgListEntry Entry;
4558 Entry.Node = getValue(I.getOperand(0));
4559 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4560 Args.push_back(Entry);
4561 MVT IntPtr = TLI.getPointerTy();
4562 std::pair<SDOperand,SDOperand> Result =
4563 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4564 CallingConv::C, true,
4565 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4566 DAG.setRoot(Result.second);
4569 // EmitInstrWithCustomInserter - This method should be implemented by targets
4570 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4571 // instructions are special in various ways, which require special support to
4572 // insert. The specified MachineInstr is created but not inserted into any
4573 // basic blocks, and the scheduler passes ownership of it to this method.
4574 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4575 MachineBasicBlock *MBB) {
4576 cerr << "If a target marks an instruction with "
4577 << "'usesCustomDAGSchedInserter', it must implement "
4578 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4583 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4584 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4585 getValue(I.getOperand(1)),
4586 DAG.getSrcValue(I.getOperand(1))));
4589 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4590 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4591 getValue(I.getOperand(0)),
4592 DAG.getSrcValue(I.getOperand(0)));
4594 DAG.setRoot(V.getValue(1));
4597 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4598 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4599 getValue(I.getOperand(1)),
4600 DAG.getSrcValue(I.getOperand(1))));
4603 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4604 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4605 getValue(I.getOperand(1)),
4606 getValue(I.getOperand(2)),
4607 DAG.getSrcValue(I.getOperand(1)),
4608 DAG.getSrcValue(I.getOperand(2))));
4611 /// TargetLowering::LowerArguments - This is the default LowerArguments
4612 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4613 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4614 /// integrated into SDISel.
4615 std::vector<SDOperand>
4616 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
4617 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4618 std::vector<SDOperand> Ops;
4619 Ops.push_back(DAG.getRoot());
4620 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4621 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4623 // Add one result value for each formal argument.
4624 std::vector<MVT> RetVals;
4626 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4628 SmallVector<MVT, 4> ValueVTs;
4629 ComputeValueVTs(*this, I->getType(), ValueVTs);
4630 for (unsigned Value = 0, NumValues = ValueVTs.size();
4631 Value != NumValues; ++Value) {
4632 MVT VT = ValueVTs[Value];
4633 const Type *ArgTy = VT.getTypeForMVT();
4634 ISD::ArgFlagsTy Flags;
4635 unsigned OriginalAlignment =
4636 getTargetData()->getABITypeAlignment(ArgTy);
4638 if (F.paramHasAttr(j, ParamAttr::ZExt))
4640 if (F.paramHasAttr(j, ParamAttr::SExt))
4642 if (F.paramHasAttr(j, ParamAttr::InReg))
4644 if (F.paramHasAttr(j, ParamAttr::StructRet))
4646 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4648 const PointerType *Ty = cast<PointerType>(I->getType());
4649 const Type *ElementTy = Ty->getElementType();
4650 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4651 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4652 // For ByVal, alignment should be passed from FE. BE will guess if
4653 // this info is not there but there are cases it cannot get right.
4654 if (F.getParamAlignment(j))
4655 FrameAlign = F.getParamAlignment(j);
4656 Flags.setByValAlign(FrameAlign);
4657 Flags.setByValSize(FrameSize);
4659 if (F.paramHasAttr(j, ParamAttr::Nest))
4661 Flags.setOrigAlign(OriginalAlignment);
4663 MVT RegisterVT = getRegisterType(VT);
4664 unsigned NumRegs = getNumRegisters(VT);
4665 for (unsigned i = 0; i != NumRegs; ++i) {
4666 RetVals.push_back(RegisterVT);
4667 ISD::ArgFlagsTy MyFlags = Flags;
4668 if (NumRegs > 1 && i == 0)
4670 // if it isn't first piece, alignment must be 1
4672 MyFlags.setOrigAlign(1);
4673 Ops.push_back(DAG.getArgFlags(MyFlags));
4678 RetVals.push_back(MVT::Other);
4681 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4682 DAG.getVTList(&RetVals[0], RetVals.size()),
4683 &Ops[0], Ops.size()).Val;
4685 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4686 // allows exposing the loads that may be part of the argument access to the
4687 // first DAGCombiner pass.
4688 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
4690 // The number of results should match up, except that the lowered one may have
4691 // an extra flag result.
4692 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4693 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4694 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4695 && "Lowering produced unexpected number of results!");
4696 Result = TmpRes.Val;
4698 unsigned NumArgRegs = Result->getNumValues() - 1;
4699 DAG.setRoot(SDOperand(Result, NumArgRegs));
4701 // Set up the return result vector.
4705 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4707 SmallVector<MVT, 4> ValueVTs;
4708 ComputeValueVTs(*this, I->getType(), ValueVTs);
4709 for (unsigned Value = 0, NumValues = ValueVTs.size();
4710 Value != NumValues; ++Value) {
4711 MVT VT = ValueVTs[Value];
4712 MVT PartVT = getRegisterType(VT);
4714 unsigned NumParts = getNumRegisters(VT);
4715 SmallVector<SDOperand, 4> Parts(NumParts);
4716 for (unsigned j = 0; j != NumParts; ++j)
4717 Parts[j] = SDOperand(Result, i++);
4719 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4720 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4721 AssertOp = ISD::AssertSext;
4722 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4723 AssertOp = ISD::AssertZext;
4725 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4729 assert(i == NumArgRegs && "Argument register count mismatch!");
4734 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4735 /// implementation, which just inserts an ISD::CALL node, which is later custom
4736 /// lowered by the target to something concrete. FIXME: When all targets are
4737 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4738 std::pair<SDOperand, SDOperand>
4739 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4740 bool RetSExt, bool RetZExt, bool isVarArg,
4741 unsigned CallingConv, bool isTailCall,
4743 ArgListTy &Args, SelectionDAG &DAG) {
4744 SmallVector<SDOperand, 32> Ops;
4745 Ops.push_back(Chain); // Op#0 - Chain
4746 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4747 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4748 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4749 Ops.push_back(Callee);
4751 // Handle all of the outgoing arguments.
4752 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4753 SmallVector<MVT, 4> ValueVTs;
4754 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
4755 for (unsigned Value = 0, NumValues = ValueVTs.size();
4756 Value != NumValues; ++Value) {
4757 MVT VT = ValueVTs[Value];
4758 const Type *ArgTy = VT.getTypeForMVT();
4759 SDOperand Op = SDOperand(Args[i].Node.Val, Args[i].Node.ResNo + Value);
4760 ISD::ArgFlagsTy Flags;
4761 unsigned OriginalAlignment =
4762 getTargetData()->getABITypeAlignment(ArgTy);
4768 if (Args[i].isInReg)
4772 if (Args[i].isByVal) {
4774 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4775 const Type *ElementTy = Ty->getElementType();
4776 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4777 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4778 // For ByVal, alignment should come from FE. BE will guess if this
4779 // info is not there but there are cases it cannot get right.
4780 if (Args[i].Alignment)
4781 FrameAlign = Args[i].Alignment;
4782 Flags.setByValAlign(FrameAlign);
4783 Flags.setByValSize(FrameSize);
4787 Flags.setOrigAlign(OriginalAlignment);
4789 MVT PartVT = getRegisterType(VT);
4790 unsigned NumParts = getNumRegisters(VT);
4791 SmallVector<SDOperand, 4> Parts(NumParts);
4792 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4795 ExtendKind = ISD::SIGN_EXTEND;
4796 else if (Args[i].isZExt)
4797 ExtendKind = ISD::ZERO_EXTEND;
4799 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4801 for (unsigned i = 0; i != NumParts; ++i) {
4802 // if it isn't first piece, alignment must be 1
4803 ISD::ArgFlagsTy MyFlags = Flags;
4804 if (NumParts > 1 && i == 0)
4807 MyFlags.setOrigAlign(1);
4809 Ops.push_back(Parts[i]);
4810 Ops.push_back(DAG.getArgFlags(MyFlags));
4815 // Figure out the result value types. We start by making a list of
4816 // the potentially illegal return value types.
4817 SmallVector<MVT, 4> LoweredRetTys;
4818 SmallVector<MVT, 4> RetTys;
4819 ComputeValueVTs(*this, RetTy, RetTys);
4821 // Then we translate that to a list of legal types.
4822 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4824 MVT RegisterVT = getRegisterType(VT);
4825 unsigned NumRegs = getNumRegisters(VT);
4826 for (unsigned i = 0; i != NumRegs; ++i)
4827 LoweredRetTys.push_back(RegisterVT);
4830 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4832 // Create the CALL node.
4833 SDOperand Res = DAG.getNode(ISD::CALL,
4834 DAG.getVTList(&LoweredRetTys[0],
4835 LoweredRetTys.size()),
4836 &Ops[0], Ops.size());
4837 Chain = Res.getValue(LoweredRetTys.size() - 1);
4839 // Gather up the call result into a single value.
4840 if (RetTy != Type::VoidTy) {
4841 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4844 AssertOp = ISD::AssertSext;
4846 AssertOp = ISD::AssertZext;
4848 SmallVector<SDOperand, 4> ReturnValues;
4850 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4852 MVT RegisterVT = getRegisterType(VT);
4853 unsigned NumRegs = getNumRegisters(VT);
4854 unsigned RegNoEnd = NumRegs + RegNo;
4855 SmallVector<SDOperand, 4> Results;
4856 for (; RegNo != RegNoEnd; ++RegNo)
4857 Results.push_back(Res.getValue(RegNo));
4858 SDOperand ReturnValue =
4859 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4861 ReturnValues.push_back(ReturnValue);
4863 Res = ReturnValues.size() == 1 ? ReturnValues.front() :
4864 DAG.getNode(ISD::MERGE_VALUES,
4865 DAG.getVTList(&RetTys[0], RetTys.size()),
4866 &ReturnValues[0], ReturnValues.size());
4869 return std::make_pair(Res, Chain);
4872 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4873 assert(0 && "LowerOperation not implemented for this target!");
4878 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4879 SelectionDAG &DAG) {
4880 assert(0 && "CustomPromoteOperation not implemented for this target!");
4885 //===----------------------------------------------------------------------===//
4886 // SelectionDAGISel code
4887 //===----------------------------------------------------------------------===//
4889 unsigned SelectionDAGISel::MakeReg(MVT VT) {
4890 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4893 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4894 AU.addRequired<AliasAnalysis>();
4895 AU.addRequired<CollectorModuleMetadata>();
4896 AU.setPreservesAll();
4899 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4900 // Get alias analysis for load/store combining.
4901 AA = &getAnalysis<AliasAnalysis>();
4903 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4904 if (MF.getFunction()->hasCollector())
4905 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4908 RegInfo = &MF.getRegInfo();
4909 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4911 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4913 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4914 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4915 // Mark landing pad.
4916 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4918 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4919 SelectBasicBlock(I, MF, FuncInfo);
4921 // Add function live-ins to entry block live-in set.
4922 BasicBlock *EntryBB = &Fn.getEntryBlock();
4923 BB = FuncInfo.MBBMap[EntryBB];
4924 if (!RegInfo->livein_empty())
4925 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4926 E = RegInfo->livein_end(); I != E; ++I)
4927 BB->addLiveIn(I->first);
4930 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4931 "Not all catch info was assigned to a landing pad!");
4937 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4938 SDOperand Op = getValue(V);
4939 assert((Op.getOpcode() != ISD::CopyFromReg ||
4940 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4941 "Copy from a reg to the same reg!");
4942 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4944 RegsForValue RFV(TLI, Reg, V->getType());
4945 SDOperand Chain = DAG.getEntryNode();
4946 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4947 PendingExports.push_back(Chain);
4950 void SelectionDAGISel::
4951 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4952 // If this is the entry block, emit arguments.
4953 Function &F = *LLVMBB->getParent();
4954 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4955 SDOperand OldRoot = SDL.DAG.getRoot();
4956 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4959 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4961 SmallVector<MVT, 4> ValueVTs;
4962 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
4963 unsigned NumValues = ValueVTs.size();
4964 if (!AI->use_empty()) {
4965 SmallVector<MVT, 4> LegalValueVTs(NumValues);
4966 for (unsigned VI = 0; VI != NumValues; ++VI)
4967 LegalValueVTs[VI] = Args[a + VI].getValueType();
4968 SDL.setValue(AI, SDL.DAG.getNode(ISD::MERGE_VALUES,
4969 SDL.DAG.getVTList(&LegalValueVTs[0],
4971 &Args[a], NumValues));
4972 // If this argument is live outside of the entry block, insert a copy from
4973 // whereever we got it to the vreg that other BB's will reference it as.
4974 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4975 if (VMI != FuncInfo.ValueMap.end()) {
4976 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4982 // Finally, if the target has anything special to do, allow it to do so.
4983 // FIXME: this should insert code into the DAG!
4984 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4987 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4988 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4989 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4990 if (isSelector(I)) {
4991 // Apply the catch info to DestBB.
4992 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4994 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4995 FLI.CatchInfoFound.insert(I);
5000 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
5001 /// whether object offset >= 0.
5003 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDOperand Op) {
5004 if (!isa<FrameIndexSDNode>(Op)) return false;
5006 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
5007 int FrameIdx = FrameIdxNode->getIndex();
5008 return MFI->isFixedObjectIndex(FrameIdx) &&
5009 MFI->getObjectOffset(FrameIdx) >= 0;
5012 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
5013 /// possibly be overwritten when lowering the outgoing arguments in a tail
5014 /// call. Currently the implementation of this call is very conservative and
5015 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
5016 /// virtual registers would be overwritten by direct lowering.
5017 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op,
5018 MachineFrameInfo * MFI) {
5019 RegisterSDNode * OpReg = NULL;
5020 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
5021 (Op.getOpcode()== ISD::CopyFromReg &&
5022 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
5023 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
5024 (Op.getOpcode() == ISD::LOAD &&
5025 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
5026 (Op.getOpcode() == ISD::MERGE_VALUES &&
5027 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
5028 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
5034 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
5035 /// DAG and fixes their tailcall attribute operand.
5036 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
5037 TargetLowering& TLI) {
5038 SDNode * Ret = NULL;
5039 SDOperand Terminator = DAG.getRoot();
5042 if (Terminator.getOpcode() == ISD::RET) {
5043 Ret = Terminator.Val;
5046 // Fix tail call attribute of CALL nodes.
5047 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
5048 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
5049 if (BI->getOpcode() == ISD::CALL) {
5050 SDOperand OpRet(Ret, 0);
5051 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
5052 bool isMarkedTailCall =
5053 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5054 // If CALL node has tail call attribute set to true and the call is not
5055 // eligible (no RET or the target rejects) the attribute is fixed to
5056 // false. The TargetLowering::IsEligibleForTailCallOptimization function
5057 // must correctly identify tail call optimizable calls.
5058 if (!isMarkedTailCall) continue;
5060 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5061 // Not eligible. Mark CALL node as non tail call.
5062 SmallVector<SDOperand, 32> Ops;
5064 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5065 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5069 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5071 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5073 // Look for tail call clobbered arguments. Emit a series of
5074 // copyto/copyfrom virtual register nodes to protect them.
5075 SmallVector<SDOperand, 32> Ops;
5076 SDOperand Chain = OpCall.getOperand(0), InFlag;
5078 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5079 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5081 if (idx > 4 && (idx % 2)) {
5082 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5083 getArgFlags().isByVal();
5084 MachineFunction &MF = DAG.getMachineFunction();
5085 MachineFrameInfo *MFI = MF.getFrameInfo();
5087 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
5088 MVT VT = Arg.getValueType();
5089 unsigned VReg = MF.getRegInfo().
5090 createVirtualRegister(TLI.getRegClassFor(VT));
5091 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5092 InFlag = Chain.getValue(1);
5093 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5094 Chain = Arg.getValue(1);
5095 InFlag = Arg.getValue(2);
5100 // Link in chain of CopyTo/CopyFromReg.
5102 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5108 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
5109 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5110 FunctionLoweringInfo &FuncInfo) {
5111 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
5113 // Lower any arguments needed in this block if this is the entry block.
5114 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
5115 LowerArguments(LLVMBB, SDL);
5117 BB = FuncInfo.MBBMap[LLVMBB];
5118 SDL.setCurrentBasicBlock(BB);
5120 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
5122 if (MMI && BB->isLandingPad()) {
5123 // Add a label to mark the beginning of the landing pad. Deletion of the
5124 // landing pad can thus be detected via the MachineModuleInfo.
5125 unsigned LabelID = MMI->addLandingPad(BB);
5126 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
5127 DAG.getConstant(LabelID, MVT::i32),
5128 DAG.getConstant(1, MVT::i32)));
5130 // Mark exception register as live in.
5131 unsigned Reg = TLI.getExceptionAddressRegister();
5132 if (Reg) BB->addLiveIn(Reg);
5134 // Mark exception selector register as live in.
5135 Reg = TLI.getExceptionSelectorRegister();
5136 if (Reg) BB->addLiveIn(Reg);
5138 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5139 // function and list of typeids logically belong to the invoke (or, if you
5140 // like, the basic block containing the invoke), and need to be associated
5141 // with it in the dwarf exception handling tables. Currently however the
5142 // information is provided by an intrinsic (eh.selector) that can be moved
5143 // to unexpected places by the optimizers: if the unwind edge is critical,
5144 // then breaking it can result in the intrinsics being in the successor of
5145 // the landing pad, not the landing pad itself. This results in exceptions
5146 // not being caught because no typeids are associated with the invoke.
5147 // This may not be the only way things can go wrong, but it is the only way
5148 // we try to work around for the moment.
5149 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5151 if (Br && Br->isUnconditional()) { // Critical edge?
5152 BasicBlock::iterator I, E;
5153 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5158 // No catch info found - try to extract some from the successor.
5159 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5163 // Lower all of the non-terminator instructions.
5164 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
5168 // Ensure that all instructions which are used outside of their defining
5169 // blocks are available as virtual registers. Invoke is handled elsewhere.
5170 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
5171 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
5172 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
5173 if (VMI != FuncInfo.ValueMap.end())
5174 SDL.CopyValueToVirtualRegister(I, VMI->second);
5177 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5178 // ensure constants are generated when needed. Remember the virtual registers
5179 // that need to be added to the Machine PHI nodes as input. We cannot just
5180 // directly add them, because expansion might result in multiple MBB's for one
5181 // BB. As such, the start of the BB might correspond to a different MBB than
5184 TerminatorInst *TI = LLVMBB->getTerminator();
5186 // Emit constants only once even if used by multiple PHI nodes.
5187 std::map<Constant*, unsigned> ConstantsOut;
5189 // Vector bool would be better, but vector<bool> is really slow.
5190 std::vector<unsigned char> SuccsHandled;
5191 if (TI->getNumSuccessors())
5192 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
5194 // Check successor nodes' PHI nodes that expect a constant to be available
5196 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5197 BasicBlock *SuccBB = TI->getSuccessor(succ);
5198 if (!isa<PHINode>(SuccBB->begin())) continue;
5199 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
5201 // If this terminator has multiple identical successors (common for
5202 // switches), only handle each succ once.
5203 unsigned SuccMBBNo = SuccMBB->getNumber();
5204 if (SuccsHandled[SuccMBBNo]) continue;
5205 SuccsHandled[SuccMBBNo] = true;
5207 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5210 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5211 // nodes and Machine PHI nodes, but the incoming operands have not been
5213 for (BasicBlock::iterator I = SuccBB->begin();
5214 (PN = dyn_cast<PHINode>(I)); ++I) {
5215 // Ignore dead phi's.
5216 if (PN->use_empty()) continue;
5219 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5221 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5222 unsigned &RegOut = ConstantsOut[C];
5224 RegOut = FuncInfo.CreateRegForValue(C);
5225 SDL.CopyValueToVirtualRegister(C, RegOut);
5229 Reg = FuncInfo.ValueMap[PHIOp];
5231 assert(isa<AllocaInst>(PHIOp) &&
5232 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5233 "Didn't codegen value into a register!??");
5234 Reg = FuncInfo.CreateRegForValue(PHIOp);
5235 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
5239 // Remember that this register needs to added to the machine PHI node as
5240 // the input for this MBB.
5241 MVT VT = TLI.getValueType(PN->getType());
5242 unsigned NumRegisters = TLI.getNumRegisters(VT);
5243 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5244 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5247 ConstantsOut.clear();
5249 // Lower the terminator after the copies are emitted.
5250 SDL.visit(*LLVMBB->getTerminator());
5252 // Copy over any CaseBlock records that may now exist due to SwitchInst
5253 // lowering, as well as any jump table information.
5254 SwitchCases.clear();
5255 SwitchCases = SDL.SwitchCases;
5257 JTCases = SDL.JTCases;
5258 BitTestCases.clear();
5259 BitTestCases = SDL.BitTestCases;
5261 // Make sure the root of the DAG is up-to-date.
5262 DAG.setRoot(SDL.getControlRoot());
5264 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5265 // with correct tailcall attribute so that the target can rely on the tailcall
5266 // attribute indicating whether the call is really eligible for tail call
5268 CheckDAGForTailCallsAndFixThem(DAG, TLI);
5271 void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
5272 SmallPtrSet<SDNode*, 128> VisitedNodes;
5273 SmallVector<SDNode*, 128> Worklist;
5275 Worklist.push_back(DAG.getRoot().Val);
5281 while (!Worklist.empty()) {
5282 SDNode *N = Worklist.back();
5283 Worklist.pop_back();
5285 // If we've already seen this node, ignore it.
5286 if (!VisitedNodes.insert(N))
5289 // Otherwise, add all chain operands to the worklist.
5290 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5291 if (N->getOperand(i).getValueType() == MVT::Other)
5292 Worklist.push_back(N->getOperand(i).Val);
5294 // If this is a CopyToReg with a vreg dest, process it.
5295 if (N->getOpcode() != ISD::CopyToReg)
5298 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5299 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5302 // Ignore non-scalar or non-integer values.
5303 SDOperand Src = N->getOperand(2);
5304 MVT SrcVT = Src.getValueType();
5305 if (!SrcVT.isInteger() || SrcVT.isVector())
5308 unsigned NumSignBits = DAG.ComputeNumSignBits(Src);
5309 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5310 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5312 // Only install this information if it tells us something.
5313 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5314 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5315 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5316 if (DestReg >= FLI.LiveOutRegInfo.size())
5317 FLI.LiveOutRegInfo.resize(DestReg+1);
5318 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5319 LOI.NumSignBits = NumSignBits;
5320 LOI.KnownOne = NumSignBits;
5321 LOI.KnownZero = NumSignBits;
5326 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
5327 DOUT << "Lowered selection DAG:\n";
5330 // Run the DAG combiner in pre-legalize mode.
5331 DAG.Combine(false, *AA);
5333 DOUT << "Optimized lowered selection DAG:\n";
5336 // Second step, hack on the DAG until it only uses operations and types that
5337 // the target supports.
5338 #if 0 // Enable this some day.
5339 DAG.LegalizeTypes();
5340 // Someday even later, enable a dag combine pass here.
5344 DOUT << "Legalized selection DAG:\n";
5347 // Run the DAG combiner in post-legalize mode.
5348 DAG.Combine(true, *AA);
5350 DOUT << "Optimized legalized selection DAG:\n";
5353 if (ViewISelDAGs) DAG.viewGraph();
5355 if (EnableValueProp) // FIXME: Only do this if !fast.
5356 ComputeLiveOutVRegInfo(DAG);
5358 // Third, instruction select all of the operations to machine code, adding the
5359 // code to the MachineBasicBlock.
5360 InstructionSelectBasicBlock(DAG);
5362 DOUT << "Selected machine code:\n";
5366 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5367 FunctionLoweringInfo &FuncInfo) {
5368 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5370 SelectionDAG DAG(TLI, MF, FuncInfo,
5371 getAnalysisToUpdate<MachineModuleInfo>());
5374 // First step, lower LLVM code to some DAG. This DAG may use operations and
5375 // types that are not supported by the target.
5376 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5378 // Second step, emit the lowered DAG as machine code.
5379 CodeGenAndEmitDAG(DAG);
5382 DOUT << "Total amount of phi nodes to update: "
5383 << PHINodesToUpdate.size() << "\n";
5384 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5385 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5386 << ", " << PHINodesToUpdate[i].second << ")\n";);
5388 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5389 // PHI nodes in successors.
5390 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
5391 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5392 MachineInstr *PHI = PHINodesToUpdate[i].first;
5393 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5394 "This is not a machine PHI node that we are updating!");
5395 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5397 PHI->addOperand(MachineOperand::CreateMBB(BB));
5402 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5403 // Lower header first, if it wasn't already lowered
5404 if (!BitTestCases[i].Emitted) {
5405 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5406 getAnalysisToUpdate<MachineModuleInfo>());
5408 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5409 // Set the current basic block to the mbb we wish to insert the code into
5410 BB = BitTestCases[i].Parent;
5411 HSDL.setCurrentBasicBlock(BB);
5413 HSDL.visitBitTestHeader(BitTestCases[i]);
5414 HSDAG.setRoot(HSDL.getRoot());
5415 CodeGenAndEmitDAG(HSDAG);
5418 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5419 SelectionDAG BSDAG(TLI, MF, FuncInfo,
5420 getAnalysisToUpdate<MachineModuleInfo>());
5422 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
5423 // Set the current basic block to the mbb we wish to insert the code into
5424 BB = BitTestCases[i].Cases[j].ThisBB;
5425 BSDL.setCurrentBasicBlock(BB);
5428 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5429 BitTestCases[i].Reg,
5430 BitTestCases[i].Cases[j]);
5432 BSDL.visitBitTestCase(BitTestCases[i].Default,
5433 BitTestCases[i].Reg,
5434 BitTestCases[i].Cases[j]);
5437 BSDAG.setRoot(BSDL.getRoot());
5438 CodeGenAndEmitDAG(BSDAG);
5442 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5443 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5444 MachineBasicBlock *PHIBB = PHI->getParent();
5445 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5446 "This is not a machine PHI node that we are updating!");
5447 // This is "default" BB. We have two jumps to it. From "header" BB and
5448 // from last "case" BB.
5449 if (PHIBB == BitTestCases[i].Default) {
5450 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5452 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5453 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5455 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5458 // One of "cases" BB.
5459 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5460 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5461 if (cBB->succ_end() !=
5462 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5463 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5465 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5471 // If the JumpTable record is filled in, then we need to emit a jump table.
5472 // Updating the PHI nodes is tricky in this case, since we need to determine
5473 // whether the PHI is a successor of the range check MBB or the jump table MBB
5474 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5475 // Lower header first, if it wasn't already lowered
5476 if (!JTCases[i].first.Emitted) {
5477 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5478 getAnalysisToUpdate<MachineModuleInfo>());
5480 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5481 // Set the current basic block to the mbb we wish to insert the code into
5482 BB = JTCases[i].first.HeaderBB;
5483 HSDL.setCurrentBasicBlock(BB);
5485 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5486 HSDAG.setRoot(HSDL.getRoot());
5487 CodeGenAndEmitDAG(HSDAG);
5490 SelectionDAG JSDAG(TLI, MF, FuncInfo,
5491 getAnalysisToUpdate<MachineModuleInfo>());
5493 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5494 // Set the current basic block to the mbb we wish to insert the code into
5495 BB = JTCases[i].second.MBB;
5496 JSDL.setCurrentBasicBlock(BB);
5498 JSDL.visitJumpTable(JTCases[i].second);
5499 JSDAG.setRoot(JSDL.getRoot());
5500 CodeGenAndEmitDAG(JSDAG);
5503 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5504 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5505 MachineBasicBlock *PHIBB = PHI->getParent();
5506 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5507 "This is not a machine PHI node that we are updating!");
5508 // "default" BB. We can go there only from header BB.
5509 if (PHIBB == JTCases[i].second.Default) {
5510 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5512 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5514 // JT BB. Just iterate over successors here
5515 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5516 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5518 PHI->addOperand(MachineOperand::CreateMBB(BB));
5523 // If the switch block involved a branch to one of the actual successors, we
5524 // need to update PHI nodes in that block.
5525 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5526 MachineInstr *PHI = PHINodesToUpdate[i].first;
5527 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5528 "This is not a machine PHI node that we are updating!");
5529 if (BB->isSuccessor(PHI->getParent())) {
5530 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5532 PHI->addOperand(MachineOperand::CreateMBB(BB));
5536 // If we generated any switch lowering information, build and codegen any
5537 // additional DAGs necessary.
5538 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5539 SelectionDAG SDAG(TLI, MF, FuncInfo,
5540 getAnalysisToUpdate<MachineModuleInfo>());
5542 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5544 // Set the current basic block to the mbb we wish to insert the code into
5545 BB = SwitchCases[i].ThisBB;
5546 SDL.setCurrentBasicBlock(BB);
5549 SDL.visitSwitchCase(SwitchCases[i]);
5550 SDAG.setRoot(SDL.getRoot());
5551 CodeGenAndEmitDAG(SDAG);
5553 // Handle any PHI nodes in successors of this chunk, as if we were coming
5554 // from the original BB before switch expansion. Note that PHI nodes can
5555 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5556 // handle them the right number of times.
5557 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5558 for (MachineBasicBlock::iterator Phi = BB->begin();
5559 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5560 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5561 for (unsigned pn = 0; ; ++pn) {
5562 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5563 if (PHINodesToUpdate[pn].first == Phi) {
5564 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5566 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5572 // Don't process RHS if same block as LHS.
5573 if (BB == SwitchCases[i].FalseBB)
5574 SwitchCases[i].FalseBB = 0;
5576 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5577 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5578 SwitchCases[i].FalseBB = 0;
5580 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5585 //===----------------------------------------------------------------------===//
5586 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
5587 /// target node in the graph.
5588 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
5589 if (ViewSchedDAGs) DAG.viewGraph();
5591 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5595 RegisterScheduler::setDefault(Ctor);
5598 ScheduleDAG *SL = Ctor(this, &DAG, BB);
5601 if (ViewSUnitDAGs) SL->viewGraph();
5607 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5608 return new HazardRecognizer();
5611 //===----------------------------------------------------------------------===//
5612 // Helper functions used by the generated instruction selector.
5613 //===----------------------------------------------------------------------===//
5614 // Calls to these methods are generated by tblgen.
5616 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5617 /// the dag combiner simplified the 255, we still want to match. RHS is the
5618 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5619 /// specified in the .td file (e.g. 255).
5620 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5621 int64_t DesiredMaskS) const {
5622 const APInt &ActualMask = RHS->getAPIntValue();
5623 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5625 // If the actual mask exactly matches, success!
5626 if (ActualMask == DesiredMask)
5629 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5630 if (ActualMask.intersects(~DesiredMask))
5633 // Otherwise, the DAG Combiner may have proven that the value coming in is
5634 // either already zero or is not demanded. Check for known zero input bits.
5635 APInt NeededMask = DesiredMask & ~ActualMask;
5636 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5639 // TODO: check to see if missing bits are just not demanded.
5641 // Otherwise, this pattern doesn't match.
5645 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5646 /// the dag combiner simplified the 255, we still want to match. RHS is the
5647 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5648 /// specified in the .td file (e.g. 255).
5649 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5650 int64_t DesiredMaskS) const {
5651 const APInt &ActualMask = RHS->getAPIntValue();
5652 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5654 // If the actual mask exactly matches, success!
5655 if (ActualMask == DesiredMask)
5658 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5659 if (ActualMask.intersects(~DesiredMask))
5662 // Otherwise, the DAG Combiner may have proven that the value coming in is
5663 // either already zero or is not demanded. Check for known zero input bits.
5664 APInt NeededMask = DesiredMask & ~ActualMask;
5666 APInt KnownZero, KnownOne;
5667 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5669 // If all the missing bits in the or are already known to be set, match!
5670 if ((NeededMask & KnownOne) == NeededMask)
5673 // TODO: check to see if missing bits are just not demanded.
5675 // Otherwise, this pattern doesn't match.
5680 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5681 /// by tblgen. Others should not call it.
5682 void SelectionDAGISel::
5683 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5684 std::vector<SDOperand> InOps;
5685 std::swap(InOps, Ops);
5687 Ops.push_back(InOps[0]); // input chain.
5688 Ops.push_back(InOps[1]); // input asm string.
5690 unsigned i = 2, e = InOps.size();
5691 if (InOps[e-1].getValueType() == MVT::Flag)
5692 --e; // Don't process a flag operand if it is here.
5695 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5696 if ((Flags & 7) != 4 /*MEM*/) {
5697 // Just skip over this operand, copying the operands verbatim.
5698 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5699 i += (Flags >> 3) + 1;
5701 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5702 // Otherwise, this is a memory operand. Ask the target to select it.
5703 std::vector<SDOperand> SelOps;
5704 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5705 cerr << "Could not match memory address. Inline asm failure!\n";
5709 // Add this to the output node.
5710 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5711 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5713 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5718 // Add the flag input back if present.
5719 if (e != InOps.size())
5720 Ops.push_back(InOps.back());
5723 char SelectionDAGISel::ID = 0;