1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAGISel.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DebugInfo.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/Timer.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLibraryInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Target/TargetRegisterInfo.h"
57 #include "llvm/Target/TargetSubtargetInfo.h"
58 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
62 #define DEBUG_TYPE "isel"
64 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
65 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
66 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
67 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
68 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
69 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
70 STATISTIC(NumFastIselFailLowerArguments,
71 "Number of entry blocks where fast isel failed to lower arguments");
75 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
76 cl::desc("Enable extra verbose messages in the \"fast\" "
77 "instruction selector"));
80 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
81 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
82 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
83 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
84 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
85 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
86 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
88 // Standard binary operators...
89 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
90 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
91 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
92 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
93 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
94 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
95 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
96 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
97 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
98 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
99 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
100 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
102 // Logical operators...
103 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
104 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
105 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
107 // Memory instructions...
108 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
109 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
110 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
111 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
112 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
113 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
114 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
116 // Convert instructions...
117 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
118 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
119 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
120 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
121 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
122 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
123 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
124 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
125 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
126 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
127 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
128 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
130 // Other instructions...
131 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
132 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
133 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
134 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
135 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
136 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
137 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
138 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
139 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
140 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
141 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
142 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
143 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
144 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
145 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 // Intrinsic instructions...
148 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
149 STATISTIC(NumFastIselFailSAddWithOverflow,
150 "Fast isel fails on sadd.with.overflow");
151 STATISTIC(NumFastIselFailUAddWithOverflow,
152 "Fast isel fails on uadd.with.overflow");
153 STATISTIC(NumFastIselFailSSubWithOverflow,
154 "Fast isel fails on ssub.with.overflow");
155 STATISTIC(NumFastIselFailUSubWithOverflow,
156 "Fast isel fails on usub.with.overflow");
157 STATISTIC(NumFastIselFailSMulWithOverflow,
158 "Fast isel fails on smul.with.overflow");
159 STATISTIC(NumFastIselFailUMulWithOverflow,
160 "Fast isel fails on umul.with.overflow");
161 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
162 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
163 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
164 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
168 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
169 cl::desc("Enable verbose messages in the \"fast\" "
170 "instruction selector"));
172 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
173 cl::desc("Enable abort calls when \"fast\" instruction selection "
174 "fails to lower an instruction"));
176 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
177 cl::desc("Enable abort calls when \"fast\" instruction selection "
178 "fails to lower a formal argument"));
182 cl::desc("use Machine Branch Probability Info"),
183 cl::init(true), cl::Hidden);
187 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
188 cl::desc("Pop up a window to show dags before the first "
189 "dag combine pass"));
191 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
192 cl::desc("Pop up a window to show dags before legalize types"));
194 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
195 cl::desc("Pop up a window to show dags before legalize"));
197 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
198 cl::desc("Pop up a window to show dags before the second "
199 "dag combine pass"));
201 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
202 cl::desc("Pop up a window to show dags before the post legalize types"
203 " dag combine pass"));
205 ViewISelDAGs("view-isel-dags", cl::Hidden,
206 cl::desc("Pop up a window to show isel dags as they are selected"));
208 ViewSchedDAGs("view-sched-dags", cl::Hidden,
209 cl::desc("Pop up a window to show sched dags as they are processed"));
211 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
212 cl::desc("Pop up a window to show SUnit dags after they are processed"));
214 static const bool ViewDAGCombine1 = false,
215 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
216 ViewDAGCombine2 = false,
217 ViewDAGCombineLT = false,
218 ViewISelDAGs = false, ViewSchedDAGs = false,
219 ViewSUnitDAGs = false;
222 //===---------------------------------------------------------------------===//
224 /// RegisterScheduler class - Track the registration of instruction schedulers.
226 //===---------------------------------------------------------------------===//
227 MachinePassRegistry RegisterScheduler::Registry;
229 //===---------------------------------------------------------------------===//
231 /// ISHeuristic command line option for instruction schedulers.
233 //===---------------------------------------------------------------------===//
234 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
235 RegisterPassParser<RegisterScheduler> >
236 ISHeuristic("pre-RA-sched",
237 cl::init(&createDefaultScheduler), cl::Hidden,
238 cl::desc("Instruction schedulers available (before register"
241 static RegisterScheduler
242 defaultListDAGScheduler("default", "Best scheduler for the target",
243 createDefaultScheduler);
246 //===--------------------------------------------------------------------===//
247 /// \brief This class is used by SelectionDAGISel to temporarily override
248 /// the optimization level on a per-function basis.
249 class OptLevelChanger {
250 SelectionDAGISel &IS;
251 CodeGenOpt::Level SavedOptLevel;
255 OptLevelChanger(SelectionDAGISel &ISel,
256 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
257 SavedOptLevel = IS.OptLevel;
258 if (NewOptLevel == SavedOptLevel)
260 IS.OptLevel = NewOptLevel;
261 IS.TM.setOptLevel(NewOptLevel);
262 SavedFastISel = IS.TM.Options.EnableFastISel;
263 if (NewOptLevel == CodeGenOpt::None)
264 IS.TM.setFastISel(true);
265 DEBUG(dbgs() << "\nChanging optimization level for Function "
266 << IS.MF->getFunction()->getName() << "\n");
267 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
268 << " ; After: -O" << NewOptLevel << "\n");
272 if (IS.OptLevel == SavedOptLevel)
274 DEBUG(dbgs() << "\nRestoring optimization level for Function "
275 << IS.MF->getFunction()->getName() << "\n");
276 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
277 << " ; After: -O" << SavedOptLevel << "\n");
278 IS.OptLevel = SavedOptLevel;
279 IS.TM.setOptLevel(SavedOptLevel);
280 IS.TM.setFastISel(SavedFastISel);
284 //===--------------------------------------------------------------------===//
285 /// createDefaultScheduler - This creates an instruction scheduler appropriate
287 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
288 CodeGenOpt::Level OptLevel) {
289 const TargetLowering *TLI = IS->TLI;
290 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
292 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
293 TLI->getSchedulingPreference() == Sched::Source)
294 return createSourceListDAGScheduler(IS, OptLevel);
295 if (TLI->getSchedulingPreference() == Sched::RegPressure)
296 return createBURRListDAGScheduler(IS, OptLevel);
297 if (TLI->getSchedulingPreference() == Sched::Hybrid)
298 return createHybridListDAGScheduler(IS, OptLevel);
299 if (TLI->getSchedulingPreference() == Sched::VLIW)
300 return createVLIWDAGScheduler(IS, OptLevel);
301 assert(TLI->getSchedulingPreference() == Sched::ILP &&
302 "Unknown sched type!");
303 return createILPListDAGScheduler(IS, OptLevel);
307 // EmitInstrWithCustomInserter - This method should be implemented by targets
308 // that mark instructions with the 'usesCustomInserter' flag. These
309 // instructions are special in various ways, which require special support to
310 // insert. The specified MachineInstr is created but not inserted into any
311 // basic blocks, and this method is called to expand it into a sequence of
312 // instructions, potentially also creating new basic blocks and control flow.
313 // When new basic blocks are inserted and the edges from MBB to its successors
314 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
317 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
318 MachineBasicBlock *MBB) const {
320 dbgs() << "If a target marks an instruction with "
321 "'usesCustomInserter', it must implement "
322 "TargetLowering::EmitInstrWithCustomInserter!";
324 llvm_unreachable(nullptr);
327 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
328 SDNode *Node) const {
329 assert(!MI->hasPostISelHook() &&
330 "If a target marks an instruction with 'hasPostISelHook', "
331 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
334 //===----------------------------------------------------------------------===//
335 // SelectionDAGISel code
336 //===----------------------------------------------------------------------===//
338 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
339 CodeGenOpt::Level OL) :
340 MachineFunctionPass(ID), TM(tm),
341 FuncInfo(new FunctionLoweringInfo()),
342 CurDAG(new SelectionDAG(tm, OL)),
343 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
347 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
348 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
349 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
350 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
353 SelectionDAGISel::~SelectionDAGISel() {
359 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
360 AU.addRequired<AliasAnalysis>();
361 AU.addPreserved<AliasAnalysis>();
362 AU.addRequired<GCModuleInfo>();
363 AU.addPreserved<GCModuleInfo>();
364 AU.addRequired<TargetLibraryInfo>();
365 if (UseMBPI && OptLevel != CodeGenOpt::None)
366 AU.addRequired<BranchProbabilityInfo>();
367 MachineFunctionPass::getAnalysisUsage(AU);
370 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
371 /// may trap on it. In this case we have to split the edge so that the path
372 /// through the predecessor block that doesn't go to the phi block doesn't
373 /// execute the possibly trapping instruction.
375 /// This is required for correctness, so it must be done at -O0.
377 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
378 // Loop for blocks with phi nodes.
379 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
380 PHINode *PN = dyn_cast<PHINode>(BB->begin());
384 // For each block with a PHI node, check to see if any of the input values
385 // are potentially trapping constant expressions. Constant expressions are
386 // the only potentially trapping value that can occur as the argument to a
388 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
389 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
390 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
391 if (!CE || !CE->canTrap()) continue;
393 // The only case we have to worry about is when the edge is critical.
394 // Since this block has a PHI Node, we assume it has multiple input
395 // edges: check to see if the pred has multiple successors.
396 BasicBlock *Pred = PN->getIncomingBlock(i);
397 if (Pred->getTerminator()->getNumSuccessors() == 1)
400 // Okay, we have to split this edge.
401 SplitCriticalEdge(Pred->getTerminator(),
402 GetSuccessorNumber(Pred, BB), SDISel, true);
408 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
409 // Do some sanity-checking on the command-line options.
410 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
411 "-fast-isel-verbose requires -fast-isel");
412 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
413 "-fast-isel-abort requires -fast-isel");
415 const Function &Fn = *mf.getFunction();
418 // Reset the target options before resetting the optimization
420 // FIXME: This is a horrible hack and should be processed via
421 // codegen looking at the optimization level explicitly when
422 // it wants to look at it.
423 TM.resetTargetOptions(Fn);
424 // Reset OptLevel to None for optnone functions.
425 CodeGenOpt::Level NewOptLevel = OptLevel;
426 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
427 NewOptLevel = CodeGenOpt::None;
428 OptLevelChanger OLC(*this, NewOptLevel);
430 TII = MF->getSubtarget().getInstrInfo();
431 TLI = MF->getSubtarget().getTargetLowering();
432 RegInfo = &MF->getRegInfo();
433 AA = &getAnalysis<AliasAnalysis>();
434 LibInfo = &getAnalysis<TargetLibraryInfo>();
435 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
437 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
439 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
442 FuncInfo->set(Fn, *MF, CurDAG);
444 if (UseMBPI && OptLevel != CodeGenOpt::None)
445 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
447 FuncInfo->BPI = nullptr;
449 SDB->init(GFI, *AA, LibInfo);
451 MF->setHasInlineAsm(false);
453 SelectAllBasicBlocks(Fn);
455 // If the first basic block in the function has live ins that need to be
456 // copied into vregs, emit the copies into the top of the block before
457 // emitting the code for the block.
458 MachineBasicBlock *EntryMBB = MF->begin();
459 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
460 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
462 DenseMap<unsigned, unsigned> LiveInMap;
463 if (!FuncInfo->ArgDbgValues.empty())
464 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
465 E = RegInfo->livein_end(); LI != E; ++LI)
467 LiveInMap.insert(std::make_pair(LI->first, LI->second));
469 // Insert DBG_VALUE instructions for function arguments to the entry block.
470 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
471 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
472 bool hasFI = MI->getOperand(0).isFI();
474 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
475 if (TargetRegisterInfo::isPhysicalRegister(Reg))
476 EntryMBB->insert(EntryMBB->begin(), MI);
478 MachineInstr *Def = RegInfo->getVRegDef(Reg);
480 MachineBasicBlock::iterator InsertPos = Def;
481 // FIXME: VR def may not be in entry block.
482 Def->getParent()->insert(std::next(InsertPos), MI);
484 DEBUG(dbgs() << "Dropping debug info for dead vreg"
485 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
488 // If Reg is live-in then update debug info to track its copy in a vreg.
489 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
490 if (LDI != LiveInMap.end()) {
491 assert(!hasFI && "There's no handling of frame pointer updating here yet "
493 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
494 MachineBasicBlock::iterator InsertPos = Def;
495 const MDNode *Variable = MI->getDebugVariable();
496 const MDNode *Expr = MI->getDebugExpression();
497 bool IsIndirect = MI->isIndirectDebugValue();
498 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
499 // Def is never a terminator here, so it is ok to increment InsertPos.
500 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
501 TII->get(TargetOpcode::DBG_VALUE), IsIndirect, LDI->second, Offset,
504 // If this vreg is directly copied into an exported register then
505 // that COPY instructions also need DBG_VALUE, if it is the only
506 // user of LDI->second.
507 MachineInstr *CopyUseMI = nullptr;
508 for (MachineRegisterInfo::use_instr_iterator
509 UI = RegInfo->use_instr_begin(LDI->second),
510 E = RegInfo->use_instr_end(); UI != E; ) {
511 MachineInstr *UseMI = &*(UI++);
512 if (UseMI->isDebugValue()) continue;
513 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
514 CopyUseMI = UseMI; continue;
516 // Otherwise this is another use or second copy use.
517 CopyUseMI = nullptr; break;
520 MachineInstr *NewMI =
521 BuildMI(*MF, CopyUseMI->getDebugLoc(),
522 TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
523 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
524 MachineBasicBlock::iterator Pos = CopyUseMI;
525 EntryMBB->insertAfter(Pos, NewMI);
530 // Determine if there are any calls in this machine function.
531 MachineFrameInfo *MFI = MF->getFrameInfo();
532 for (const auto &MBB : *MF) {
533 if (MFI->hasCalls() && MF->hasInlineAsm())
536 for (const auto &MI : MBB) {
537 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
538 if ((MCID.isCall() && !MCID.isReturn()) ||
539 MI.isStackAligningInlineAsm()) {
540 MFI->setHasCalls(true);
542 if (MI.isInlineAsm()) {
543 MF->setHasInlineAsm(true);
548 // Determine if there is a call to setjmp in the machine function.
549 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
551 // Replace forward-declared registers with the registers containing
552 // the desired value.
553 MachineRegisterInfo &MRI = MF->getRegInfo();
554 for (DenseMap<unsigned, unsigned>::iterator
555 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
557 unsigned From = I->first;
558 unsigned To = I->second;
559 // If To is also scheduled to be replaced, find what its ultimate
562 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
566 // Make sure the new register has a sufficiently constrained register class.
567 if (TargetRegisterInfo::isVirtualRegister(From) &&
568 TargetRegisterInfo::isVirtualRegister(To))
569 MRI.constrainRegClass(To, MRI.getRegClass(From));
571 MRI.replaceRegWith(From, To);
574 // Freeze the set of reserved registers now that MachineFrameInfo has been
575 // set up. All the information required by getReservedRegs() should be
577 MRI.freezeReservedRegs(*MF);
579 // Release function-specific state. SDB and CurDAG are already cleared
583 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
584 DEBUG(MF->print(dbgs()));
589 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
590 BasicBlock::const_iterator End,
592 // Lower all of the non-terminator instructions. If a call is emitted
593 // as a tail call, cease emitting nodes for this block. Terminators
594 // are handled below.
595 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
598 // Make sure the root of the DAG is up-to-date.
599 CurDAG->setRoot(SDB->getControlRoot());
600 HadTailCall = SDB->HasTailCall;
603 // Final step, emit the lowered DAG as machine code.
607 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
608 SmallPtrSet<SDNode*, 128> VisitedNodes;
609 SmallVector<SDNode*, 128> Worklist;
611 Worklist.push_back(CurDAG->getRoot().getNode());
617 SDNode *N = Worklist.pop_back_val();
619 // If we've already seen this node, ignore it.
620 if (!VisitedNodes.insert(N).second)
623 // Otherwise, add all chain operands to the worklist.
624 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
625 if (N->getOperand(i).getValueType() == MVT::Other)
626 Worklist.push_back(N->getOperand(i).getNode());
628 // If this is a CopyToReg with a vreg dest, process it.
629 if (N->getOpcode() != ISD::CopyToReg)
632 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
633 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
636 // Ignore non-scalar or non-integer values.
637 SDValue Src = N->getOperand(2);
638 EVT SrcVT = Src.getValueType();
639 if (!SrcVT.isInteger() || SrcVT.isVector())
642 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
643 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
644 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
645 } while (!Worklist.empty());
648 void SelectionDAGISel::CodeGenAndEmitDAG() {
649 std::string GroupName;
650 if (TimePassesIsEnabled)
651 GroupName = "Instruction Selection and Scheduling";
652 std::string BlockName;
653 int BlockNumber = -1;
656 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
657 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
661 BlockNumber = FuncInfo->MBB->getNumber();
662 BlockName = MF->getName().str() + ":" +
663 FuncInfo->MBB->getBasicBlock()->getName().str();
665 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
666 << " '" << BlockName << "'\n"; CurDAG->dump());
668 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
670 // Run the DAG combiner in pre-legalize mode.
672 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
673 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
676 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
677 << " '" << BlockName << "'\n"; CurDAG->dump());
679 // Second step, hack on the DAG until it only uses operations and types that
680 // the target supports.
681 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
686 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
687 Changed = CurDAG->LegalizeTypes();
690 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
691 << " '" << BlockName << "'\n"; CurDAG->dump());
693 CurDAG->NewNodesMustHaveLegalTypes = true;
696 if (ViewDAGCombineLT)
697 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
699 // Run the DAG combiner in post-type-legalize mode.
701 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
702 TimePassesIsEnabled);
703 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
706 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
707 << " '" << BlockName << "'\n"; CurDAG->dump());
712 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
713 Changed = CurDAG->LegalizeVectors();
718 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
719 CurDAG->LegalizeTypes();
722 if (ViewDAGCombineLT)
723 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
725 // Run the DAG combiner in post-type-legalize mode.
727 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
728 TimePassesIsEnabled);
729 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
732 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
733 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
736 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
739 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
743 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
744 << " '" << BlockName << "'\n"; CurDAG->dump());
746 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
748 // Run the DAG combiner in post-legalize mode.
750 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
751 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
754 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
755 << " '" << BlockName << "'\n"; CurDAG->dump());
757 if (OptLevel != CodeGenOpt::None)
758 ComputeLiveOutVRegInfo();
760 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
762 // Third, instruction select all of the operations to machine code, adding the
763 // code to the MachineBasicBlock.
765 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
766 DoInstructionSelection();
769 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
770 << " '" << BlockName << "'\n"; CurDAG->dump());
772 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
774 // Schedule machine code.
775 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
777 NamedRegionTimer T("Instruction Scheduling", GroupName,
778 TimePassesIsEnabled);
779 Scheduler->Run(CurDAG, FuncInfo->MBB);
782 if (ViewSUnitDAGs) Scheduler->viewGraph();
784 // Emit machine code to BB. This can change 'BB' to the last block being
786 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
788 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
790 // FuncInfo->InsertPt is passed by reference and set to the end of the
791 // scheduled instructions.
792 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
795 // If the block was split, make sure we update any references that are used to
796 // update PHI nodes later on.
797 if (FirstMBB != LastMBB)
798 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
800 // Free the scheduler state.
802 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
803 TimePassesIsEnabled);
807 // Free the SelectionDAG state, now that we're finished with it.
812 /// ISelUpdater - helper class to handle updates of the instruction selection
814 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
815 SelectionDAG::allnodes_iterator &ISelPosition;
817 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
818 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
820 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
821 /// deleted is the current ISelPosition node, update ISelPosition.
823 void NodeDeleted(SDNode *N, SDNode *E) override {
824 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
828 } // end anonymous namespace
830 void SelectionDAGISel::DoInstructionSelection() {
831 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
832 << FuncInfo->MBB->getNumber()
833 << " '" << FuncInfo->MBB->getName() << "'\n");
837 // Select target instructions for the DAG.
839 // Number all nodes with a topological order and set DAGSize.
840 DAGSize = CurDAG->AssignTopologicalOrder();
842 // Create a dummy node (which is not added to allnodes), that adds
843 // a reference to the root node, preventing it from being deleted,
844 // and tracking any changes of the root.
845 HandleSDNode Dummy(CurDAG->getRoot());
846 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
849 // Make sure that ISelPosition gets properly updated when nodes are deleted
850 // in calls made from this function.
851 ISelUpdater ISU(*CurDAG, ISelPosition);
853 // The AllNodes list is now topological-sorted. Visit the
854 // nodes by starting at the end of the list (the root of the
855 // graph) and preceding back toward the beginning (the entry
857 while (ISelPosition != CurDAG->allnodes_begin()) {
858 SDNode *Node = --ISelPosition;
859 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
860 // but there are currently some corner cases that it misses. Also, this
861 // makes it theoretically possible to disable the DAGCombiner.
862 if (Node->use_empty())
865 SDNode *ResNode = Select(Node);
867 // FIXME: This is pretty gross. 'Select' should be changed to not return
868 // anything at all and this code should be nuked with a tactical strike.
870 // If node should not be replaced, continue with the next one.
871 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
875 ReplaceUses(Node, ResNode);
878 // If after the replacement this node is not used any more,
879 // remove this dead node.
880 if (Node->use_empty()) // Don't delete EntryToken, etc.
881 CurDAG->RemoveDeadNode(Node);
884 CurDAG->setRoot(Dummy.getValue());
887 DEBUG(dbgs() << "===== Instruction selection ends:\n");
889 PostprocessISelDAG();
892 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
893 /// do other setup for EH landing-pad blocks.
894 void SelectionDAGISel::PrepareEHLandingPad() {
895 MachineBasicBlock *MBB = FuncInfo->MBB;
897 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
899 // Add a label to mark the beginning of the landing pad. Deletion of the
900 // landing pad can thus be detected via the MachineModuleInfo.
901 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
903 // Assign the call site to the landing pad's begin label.
904 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
906 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
907 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
910 if (TM.getMCAsmInfo()->getExceptionHandlingType() ==
911 ExceptionHandling::MSVC) {
912 // Make virtual registers and a series of labels that fill in values for the
914 auto &RI = MF->getRegInfo();
915 FuncInfo->ExceptionSelectorVirtReg = RI.createVirtualRegister(PtrRC);
917 // Get all invoke BBs that will unwind into the clause BBs.
918 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
921 // Emit separate machine basic blocks with separate labels for each clause
922 // before the main landing pad block.
923 const BasicBlock *LLVMBB = MBB->getBasicBlock();
924 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
925 MachineInstrBuilder SelectorPHI = BuildMI(
926 *MBB, MBB->begin(), SDB->getCurDebugLoc(), TII->get(TargetOpcode::PHI),
927 FuncInfo->ExceptionSelectorVirtReg);
928 for (unsigned I = 0, E = LPadInst->getNumClauses(); I != E; ++I) {
929 MachineBasicBlock *ClauseBB = MF->CreateMachineBasicBlock(LLVMBB);
930 MF->insert(MBB, ClauseBB);
932 // Add the edge from the invoke to the clause.
933 for (MachineBasicBlock *InvokeBB : InvokeBBs)
934 InvokeBB->addSuccessor(ClauseBB);
936 // Mark the clause as a landing pad or MI passes will delete it.
937 ClauseBB->setIsLandingPad();
939 GlobalValue *ClauseGV = ExtractTypeInfo(LPadInst->getClause(I));
941 // Start the BB with a label.
942 MCSymbol *ClauseLabel = MF->getMMI().addClauseForLandingPad(MBB);
943 BuildMI(*ClauseBB, ClauseBB->begin(), SDB->getCurDebugLoc(), II)
944 .addSym(ClauseLabel);
946 // Construct a simple BB that defines a register with the typeid constant.
947 FuncInfo->MBB = ClauseBB;
948 FuncInfo->InsertPt = ClauseBB->end();
949 unsigned VReg = SDB->visitLandingPadClauseBB(ClauseGV, MBB);
950 CurDAG->setRoot(SDB->getRoot());
954 // Add the typeid virtual register to the phi in the main landing pad.
955 SelectorPHI.addReg(VReg).addMBB(ClauseBB);
958 // Remove the edge from the invoke to the lpad.
959 for (MachineBasicBlock *InvokeBB : InvokeBBs)
960 InvokeBB->removeSuccessor(MBB);
962 // Restore FuncInfo back to its previous state and select the main landing
965 FuncInfo->InsertPt = MBB->end();
969 // Mark exception register as live in.
970 if (unsigned Reg = TLI->getExceptionPointerRegister())
971 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
973 // Mark exception selector register as live in.
974 if (unsigned Reg = TLI->getExceptionSelectorRegister())
975 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
978 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
979 /// side-effect free and is either dead or folded into a generated instruction.
980 /// Return false if it needs to be emitted.
981 static bool isFoldedOrDeadInstruction(const Instruction *I,
982 FunctionLoweringInfo *FuncInfo) {
983 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
984 !isa<TerminatorInst>(I) && // Terminators aren't folded.
985 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
986 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
987 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
991 // Collect per Instruction statistics for fast-isel misses. Only those
992 // instructions that cause the bail are accounted for. It does not account for
993 // instructions higher in the block. Thus, summing the per instructions stats
994 // will not add up to what is reported by NumFastIselFailures.
995 static void collectFailStats(const Instruction *I) {
996 switch (I->getOpcode()) {
997 default: assert (0 && "<Invalid operator> ");
1000 case Instruction::Ret: NumFastIselFailRet++; return;
1001 case Instruction::Br: NumFastIselFailBr++; return;
1002 case Instruction::Switch: NumFastIselFailSwitch++; return;
1003 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1004 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1005 case Instruction::Resume: NumFastIselFailResume++; return;
1006 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1008 // Standard binary operators...
1009 case Instruction::Add: NumFastIselFailAdd++; return;
1010 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1011 case Instruction::Sub: NumFastIselFailSub++; return;
1012 case Instruction::FSub: NumFastIselFailFSub++; return;
1013 case Instruction::Mul: NumFastIselFailMul++; return;
1014 case Instruction::FMul: NumFastIselFailFMul++; return;
1015 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1016 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1017 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1018 case Instruction::URem: NumFastIselFailURem++; return;
1019 case Instruction::SRem: NumFastIselFailSRem++; return;
1020 case Instruction::FRem: NumFastIselFailFRem++; return;
1022 // Logical operators...
1023 case Instruction::And: NumFastIselFailAnd++; return;
1024 case Instruction::Or: NumFastIselFailOr++; return;
1025 case Instruction::Xor: NumFastIselFailXor++; return;
1027 // Memory instructions...
1028 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1029 case Instruction::Load: NumFastIselFailLoad++; return;
1030 case Instruction::Store: NumFastIselFailStore++; return;
1031 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1032 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1033 case Instruction::Fence: NumFastIselFailFence++; return;
1034 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1036 // Convert instructions...
1037 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1038 case Instruction::ZExt: NumFastIselFailZExt++; return;
1039 case Instruction::SExt: NumFastIselFailSExt++; return;
1040 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1041 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1042 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1043 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1044 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1045 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1046 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1047 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1048 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1050 // Other instructions...
1051 case Instruction::ICmp: NumFastIselFailICmp++; return;
1052 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1053 case Instruction::PHI: NumFastIselFailPHI++; return;
1054 case Instruction::Select: NumFastIselFailSelect++; return;
1055 case Instruction::Call: {
1056 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1057 switch (Intrinsic->getIntrinsicID()) {
1059 NumFastIselFailIntrinsicCall++; return;
1060 case Intrinsic::sadd_with_overflow:
1061 NumFastIselFailSAddWithOverflow++; return;
1062 case Intrinsic::uadd_with_overflow:
1063 NumFastIselFailUAddWithOverflow++; return;
1064 case Intrinsic::ssub_with_overflow:
1065 NumFastIselFailSSubWithOverflow++; return;
1066 case Intrinsic::usub_with_overflow:
1067 NumFastIselFailUSubWithOverflow++; return;
1068 case Intrinsic::smul_with_overflow:
1069 NumFastIselFailSMulWithOverflow++; return;
1070 case Intrinsic::umul_with_overflow:
1071 NumFastIselFailUMulWithOverflow++; return;
1072 case Intrinsic::frameaddress:
1073 NumFastIselFailFrameaddress++; return;
1074 case Intrinsic::sqrt:
1075 NumFastIselFailSqrt++; return;
1076 case Intrinsic::experimental_stackmap:
1077 NumFastIselFailStackMap++; return;
1078 case Intrinsic::experimental_patchpoint_void: // fall-through
1079 case Intrinsic::experimental_patchpoint_i64:
1080 NumFastIselFailPatchPoint++; return;
1083 NumFastIselFailCall++;
1086 case Instruction::Shl: NumFastIselFailShl++; return;
1087 case Instruction::LShr: NumFastIselFailLShr++; return;
1088 case Instruction::AShr: NumFastIselFailAShr++; return;
1089 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1090 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1091 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1092 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1093 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1094 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1095 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1100 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1101 // Initialize the Fast-ISel state, if needed.
1102 FastISel *FastIS = nullptr;
1103 if (TM.Options.EnableFastISel)
1104 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1106 // Iterate over all basic blocks in the function.
1107 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1108 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1109 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1110 const BasicBlock *LLVMBB = *I;
1112 if (OptLevel != CodeGenOpt::None) {
1113 bool AllPredsVisited = true;
1114 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1116 if (!FuncInfo->VisitedBBs.count(*PI)) {
1117 AllPredsVisited = false;
1122 if (AllPredsVisited) {
1123 for (BasicBlock::const_iterator I = LLVMBB->begin();
1124 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1125 FuncInfo->ComputePHILiveOutRegInfo(PN);
1127 for (BasicBlock::const_iterator I = LLVMBB->begin();
1128 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1129 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1132 FuncInfo->VisitedBBs.insert(LLVMBB);
1135 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1136 BasicBlock::const_iterator const End = LLVMBB->end();
1137 BasicBlock::const_iterator BI = End;
1139 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1140 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1142 // Setup an EH landing-pad block.
1143 FuncInfo->ExceptionPointerVirtReg = 0;
1144 FuncInfo->ExceptionSelectorVirtReg = 0;
1145 if (FuncInfo->MBB->isLandingPad())
1146 PrepareEHLandingPad();
1148 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1150 FastIS->startNewBlock();
1152 // Emit code for any incoming arguments. This must happen before
1153 // beginning FastISel on the entry block.
1154 if (LLVMBB == &Fn.getEntryBlock()) {
1157 // Lower any arguments needed in this block if this is the entry block.
1158 if (!FastIS->lowerArguments()) {
1159 // Fast isel failed to lower these arguments
1160 ++NumFastIselFailLowerArguments;
1161 if (EnableFastISelAbortArgs)
1162 llvm_unreachable("FastISel didn't lower all arguments");
1164 // Use SelectionDAG argument lowering
1166 CurDAG->setRoot(SDB->getControlRoot());
1168 CodeGenAndEmitDAG();
1171 // If we inserted any instructions at the beginning, make a note of
1172 // where they are, so we can be sure to emit subsequent instructions
1174 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1175 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1177 FastIS->setLastLocalValue(nullptr);
1180 unsigned NumFastIselRemaining = std::distance(Begin, End);
1181 // Do FastISel on as many instructions as possible.
1182 for (; BI != Begin; --BI) {
1183 const Instruction *Inst = std::prev(BI);
1185 // If we no longer require this instruction, skip it.
1186 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1187 --NumFastIselRemaining;
1191 // Bottom-up: reset the insert pos at the top, after any local-value
1193 FastIS->recomputeInsertPt();
1195 // Try to select the instruction with FastISel.
1196 if (FastIS->selectInstruction(Inst)) {
1197 --NumFastIselRemaining;
1198 ++NumFastIselSuccess;
1199 // If fast isel succeeded, skip over all the folded instructions, and
1200 // then see if there is a load right before the selected instructions.
1201 // Try to fold the load if so.
1202 const Instruction *BeforeInst = Inst;
1203 while (BeforeInst != Begin) {
1204 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1205 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1208 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1209 BeforeInst->hasOneUse() &&
1210 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1211 // If we succeeded, don't re-select the load.
1212 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1213 --NumFastIselRemaining;
1214 ++NumFastIselSuccess;
1220 if (EnableFastISelVerbose2)
1221 collectFailStats(Inst);
1224 // Then handle certain instructions as single-LLVM-Instruction blocks.
1225 if (isa<CallInst>(Inst)) {
1227 if (EnableFastISelVerbose || EnableFastISelAbort) {
1228 dbgs() << "FastISel missed call: ";
1232 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1233 unsigned &R = FuncInfo->ValueMap[Inst];
1235 R = FuncInfo->CreateRegs(Inst->getType());
1238 bool HadTailCall = false;
1239 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1240 SelectBasicBlock(Inst, BI, HadTailCall);
1242 // If the call was emitted as a tail call, we're done with the block.
1243 // We also need to delete any previously emitted instructions.
1245 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1250 // Recompute NumFastIselRemaining as Selection DAG instruction
1251 // selection may have handled the call, input args, etc.
1252 unsigned RemainingNow = std::distance(Begin, BI);
1253 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1254 NumFastIselRemaining = RemainingNow;
1258 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1259 // Don't abort, and use a different message for terminator misses.
1260 NumFastIselFailures += NumFastIselRemaining;
1261 if (EnableFastISelVerbose || EnableFastISelAbort) {
1262 dbgs() << "FastISel missed terminator: ";
1266 NumFastIselFailures += NumFastIselRemaining;
1267 if (EnableFastISelVerbose || EnableFastISelAbort) {
1268 dbgs() << "FastISel miss: ";
1271 if (EnableFastISelAbort)
1272 // The "fast" selector couldn't handle something and bailed.
1273 // For the purpose of debugging, just abort.
1274 llvm_unreachable("FastISel didn't select the entire block");
1279 FastIS->recomputeInsertPt();
1281 // Lower any arguments needed in this block if this is the entry block.
1282 if (LLVMBB == &Fn.getEntryBlock()) {
1291 ++NumFastIselBlocks;
1294 // Run SelectionDAG instruction selection on the remainder of the block
1295 // not handled by FastISel. If FastISel is not run, this is the entire
1298 SelectBasicBlock(Begin, BI, HadTailCall);
1302 FuncInfo->PHINodesToUpdate.clear();
1306 SDB->clearDanglingDebugInfo();
1307 SDB->SPDescriptor.resetPerFunctionState();
1310 /// Given that the input MI is before a partial terminator sequence TSeq, return
1311 /// true if M + TSeq also a partial terminator sequence.
1313 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1314 /// lowering copy vregs into physical registers, which are then passed into
1315 /// terminator instructors so we can satisfy ABI constraints. A partial
1316 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1317 /// may be the whole terminator sequence).
1318 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1319 // If we do not have a copy or an implicit def, we return true if and only if
1320 // MI is a debug value.
1321 if (!MI->isCopy() && !MI->isImplicitDef())
1322 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1323 // physical registers if there is debug info associated with the terminator
1324 // of our mbb. We want to include said debug info in our terminator
1325 // sequence, so we return true in that case.
1326 return MI->isDebugValue();
1328 // We have left the terminator sequence if we are not doing one of the
1331 // 1. Copying a vreg into a physical register.
1332 // 2. Copying a vreg into a vreg.
1333 // 3. Defining a register via an implicit def.
1335 // OPI should always be a register definition...
1336 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1337 if (!OPI->isReg() || !OPI->isDef())
1340 // Defining any register via an implicit def is always ok.
1341 if (MI->isImplicitDef())
1344 // Grab the copy source...
1345 MachineInstr::const_mop_iterator OPI2 = OPI;
1347 assert(OPI2 != MI->operands_end()
1348 && "Should have a copy implying we should have 2 arguments.");
1350 // Make sure that the copy dest is not a vreg when the copy source is a
1351 // physical register.
1352 if (!OPI2->isReg() ||
1353 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1354 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1360 /// Find the split point at which to splice the end of BB into its success stack
1361 /// protector check machine basic block.
1363 /// On many platforms, due to ABI constraints, terminators, even before register
1364 /// allocation, use physical registers. This creates an issue for us since
1365 /// physical registers at this point can not travel across basic
1366 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1367 /// when they enter functions and moves them through a sequence of copies back
1368 /// into the physical registers right before the terminator creating a
1369 /// ``Terminator Sequence''. This function is searching for the beginning of the
1370 /// terminator sequence so that we can ensure that we splice off not just the
1371 /// terminator, but additionally the copies that move the vregs into the
1372 /// physical registers.
1373 static MachineBasicBlock::iterator
1374 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1375 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1377 if (SplitPoint == BB->begin())
1380 MachineBasicBlock::iterator Start = BB->begin();
1381 MachineBasicBlock::iterator Previous = SplitPoint;
1384 while (MIIsInTerminatorSequence(Previous)) {
1385 SplitPoint = Previous;
1386 if (Previous == Start)
1395 SelectionDAGISel::FinishBasicBlock() {
1397 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1398 << FuncInfo->PHINodesToUpdate.size() << "\n";
1399 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1400 dbgs() << "Node " << i << " : ("
1401 << FuncInfo->PHINodesToUpdate[i].first
1402 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1404 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1405 SDB->JTCases.empty() &&
1406 SDB->BitTestCases.empty();
1408 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1409 // PHI nodes in successors.
1410 if (MustUpdatePHINodes) {
1411 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1412 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1413 assert(PHI->isPHI() &&
1414 "This is not a machine PHI node that we are updating!");
1415 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1417 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1421 // Handle stack protector.
1422 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1423 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1424 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1426 // Find the split point to split the parent mbb. At the same time copy all
1427 // physical registers used in the tail of parent mbb into virtual registers
1428 // before the split point and back into physical registers after the split
1429 // point. This prevents us needing to deal with Live-ins and many other
1430 // register allocation issues caused by us splitting the parent mbb. The
1431 // register allocator will clean up said virtual copies later on.
1432 MachineBasicBlock::iterator SplitPoint =
1433 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1435 // Splice the terminator of ParentMBB into SuccessMBB.
1436 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1440 // Add compare/jump on neq/jump to the parent BB.
1441 FuncInfo->MBB = ParentMBB;
1442 FuncInfo->InsertPt = ParentMBB->end();
1443 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1444 CurDAG->setRoot(SDB->getRoot());
1446 CodeGenAndEmitDAG();
1448 // CodeGen Failure MBB if we have not codegened it yet.
1449 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1450 if (!FailureMBB->size()) {
1451 FuncInfo->MBB = FailureMBB;
1452 FuncInfo->InsertPt = FailureMBB->end();
1453 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1454 CurDAG->setRoot(SDB->getRoot());
1456 CodeGenAndEmitDAG();
1459 // Clear the Per-BB State.
1460 SDB->SPDescriptor.resetPerBBState();
1463 // If we updated PHI Nodes, return early.
1464 if (MustUpdatePHINodes)
1467 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1468 // Lower header first, if it wasn't already lowered
1469 if (!SDB->BitTestCases[i].Emitted) {
1470 // Set the current basic block to the mbb we wish to insert the code into
1471 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1472 FuncInfo->InsertPt = FuncInfo->MBB->end();
1474 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1475 CurDAG->setRoot(SDB->getRoot());
1477 CodeGenAndEmitDAG();
1480 uint32_t UnhandledWeight = 0;
1481 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1482 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1484 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1485 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1486 // Set the current basic block to the mbb we wish to insert the code into
1487 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1488 FuncInfo->InsertPt = FuncInfo->MBB->end();
1491 SDB->visitBitTestCase(SDB->BitTestCases[i],
1492 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1494 SDB->BitTestCases[i].Reg,
1495 SDB->BitTestCases[i].Cases[j],
1498 SDB->visitBitTestCase(SDB->BitTestCases[i],
1499 SDB->BitTestCases[i].Default,
1501 SDB->BitTestCases[i].Reg,
1502 SDB->BitTestCases[i].Cases[j],
1506 CurDAG->setRoot(SDB->getRoot());
1508 CodeGenAndEmitDAG();
1512 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1514 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1515 MachineBasicBlock *PHIBB = PHI->getParent();
1516 assert(PHI->isPHI() &&
1517 "This is not a machine PHI node that we are updating!");
1518 // This is "default" BB. We have two jumps to it. From "header" BB and
1519 // from last "case" BB.
1520 if (PHIBB == SDB->BitTestCases[i].Default)
1521 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1522 .addMBB(SDB->BitTestCases[i].Parent)
1523 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1524 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1525 // One of "cases" BB.
1526 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1528 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1529 if (cBB->isSuccessor(PHIBB))
1530 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1534 SDB->BitTestCases.clear();
1536 // If the JumpTable record is filled in, then we need to emit a jump table.
1537 // Updating the PHI nodes is tricky in this case, since we need to determine
1538 // whether the PHI is a successor of the range check MBB or the jump table MBB
1539 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1540 // Lower header first, if it wasn't already lowered
1541 if (!SDB->JTCases[i].first.Emitted) {
1542 // Set the current basic block to the mbb we wish to insert the code into
1543 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1544 FuncInfo->InsertPt = FuncInfo->MBB->end();
1546 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1548 CurDAG->setRoot(SDB->getRoot());
1550 CodeGenAndEmitDAG();
1553 // Set the current basic block to the mbb we wish to insert the code into
1554 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1555 FuncInfo->InsertPt = FuncInfo->MBB->end();
1557 SDB->visitJumpTable(SDB->JTCases[i].second);
1558 CurDAG->setRoot(SDB->getRoot());
1560 CodeGenAndEmitDAG();
1563 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1565 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1566 MachineBasicBlock *PHIBB = PHI->getParent();
1567 assert(PHI->isPHI() &&
1568 "This is not a machine PHI node that we are updating!");
1569 // "default" BB. We can go there only from header BB.
1570 if (PHIBB == SDB->JTCases[i].second.Default)
1571 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1572 .addMBB(SDB->JTCases[i].first.HeaderBB);
1573 // JT BB. Just iterate over successors here
1574 if (FuncInfo->MBB->isSuccessor(PHIBB))
1575 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1578 SDB->JTCases.clear();
1580 // If the switch block involved a branch to one of the actual successors, we
1581 // need to update PHI nodes in that block.
1582 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1583 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1584 assert(PHI->isPHI() &&
1585 "This is not a machine PHI node that we are updating!");
1586 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1587 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1590 // If we generated any switch lowering information, build and codegen any
1591 // additional DAGs necessary.
1592 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1593 // Set the current basic block to the mbb we wish to insert the code into
1594 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1595 FuncInfo->InsertPt = FuncInfo->MBB->end();
1597 // Determine the unique successors.
1598 SmallVector<MachineBasicBlock *, 2> Succs;
1599 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1600 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1601 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1603 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1604 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1605 CurDAG->setRoot(SDB->getRoot());
1607 CodeGenAndEmitDAG();
1609 // Remember the last block, now that any splitting is done, for use in
1610 // populating PHI nodes in successors.
1611 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1613 // Handle any PHI nodes in successors of this chunk, as if we were coming
1614 // from the original BB before switch expansion. Note that PHI nodes can
1615 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1616 // handle them the right number of times.
1617 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1618 FuncInfo->MBB = Succs[i];
1619 FuncInfo->InsertPt = FuncInfo->MBB->end();
1620 // FuncInfo->MBB may have been removed from the CFG if a branch was
1622 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1623 for (MachineBasicBlock::iterator
1624 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1625 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1626 MachineInstrBuilder PHI(*MF, MBBI);
1627 // This value for this PHI node is recorded in PHINodesToUpdate.
1628 for (unsigned pn = 0; ; ++pn) {
1629 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1630 "Didn't find PHI entry!");
1631 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1632 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1640 SDB->SwitchCases.clear();
1644 /// Create the scheduler. If a specific scheduler was specified
1645 /// via the SchedulerRegistry, use it, otherwise select the
1646 /// one preferred by the target.
1648 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1649 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1653 RegisterScheduler::setDefault(Ctor);
1656 return Ctor(this, OptLevel);
1659 //===----------------------------------------------------------------------===//
1660 // Helper functions used by the generated instruction selector.
1661 //===----------------------------------------------------------------------===//
1662 // Calls to these methods are generated by tblgen.
1664 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1665 /// the dag combiner simplified the 255, we still want to match. RHS is the
1666 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1667 /// specified in the .td file (e.g. 255).
1668 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1669 int64_t DesiredMaskS) const {
1670 const APInt &ActualMask = RHS->getAPIntValue();
1671 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1673 // If the actual mask exactly matches, success!
1674 if (ActualMask == DesiredMask)
1677 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1678 if (ActualMask.intersects(~DesiredMask))
1681 // Otherwise, the DAG Combiner may have proven that the value coming in is
1682 // either already zero or is not demanded. Check for known zero input bits.
1683 APInt NeededMask = DesiredMask & ~ActualMask;
1684 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1687 // TODO: check to see if missing bits are just not demanded.
1689 // Otherwise, this pattern doesn't match.
1693 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1694 /// the dag combiner simplified the 255, we still want to match. RHS is the
1695 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1696 /// specified in the .td file (e.g. 255).
1697 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1698 int64_t DesiredMaskS) const {
1699 const APInt &ActualMask = RHS->getAPIntValue();
1700 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1702 // If the actual mask exactly matches, success!
1703 if (ActualMask == DesiredMask)
1706 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1707 if (ActualMask.intersects(~DesiredMask))
1710 // Otherwise, the DAG Combiner may have proven that the value coming in is
1711 // either already zero or is not demanded. Check for known zero input bits.
1712 APInt NeededMask = DesiredMask & ~ActualMask;
1714 APInt KnownZero, KnownOne;
1715 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1717 // If all the missing bits in the or are already known to be set, match!
1718 if ((NeededMask & KnownOne) == NeededMask)
1721 // TODO: check to see if missing bits are just not demanded.
1723 // Otherwise, this pattern doesn't match.
1728 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1729 /// by tblgen. Others should not call it.
1730 void SelectionDAGISel::
1731 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1732 std::vector<SDValue> InOps;
1733 std::swap(InOps, Ops);
1735 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1736 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1737 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1738 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1740 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1741 if (InOps[e-1].getValueType() == MVT::Glue)
1742 --e; // Don't process a glue operand if it is here.
1745 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1746 if (!InlineAsm::isMemKind(Flags)) {
1747 // Just skip over this operand, copying the operands verbatim.
1748 Ops.insert(Ops.end(), InOps.begin()+i,
1749 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1750 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1752 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1753 "Memory operand with multiple values?");
1754 // Otherwise, this is a memory operand. Ask the target to select it.
1755 std::vector<SDValue> SelOps;
1756 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1757 report_fatal_error("Could not match memory address. Inline asm"
1760 // Add this to the output node.
1762 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1763 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1764 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1769 // Add the glue input back if present.
1770 if (e != InOps.size())
1771 Ops.push_back(InOps.back());
1774 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1777 static SDNode *findGlueUse(SDNode *N) {
1778 unsigned FlagResNo = N->getNumValues()-1;
1779 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1780 SDUse &Use = I.getUse();
1781 if (Use.getResNo() == FlagResNo)
1782 return Use.getUser();
1787 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1788 /// This function recursively traverses up the operand chain, ignoring
1790 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1791 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1792 bool IgnoreChains) {
1793 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1794 // greater than all of its (recursive) operands. If we scan to a point where
1795 // 'use' is smaller than the node we're scanning for, then we know we will
1798 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1799 // happen because we scan down to newly selected nodes in the case of glue
1801 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1804 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1805 // won't fail if we scan it again.
1806 if (!Visited.insert(Use).second)
1809 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1810 // Ignore chain uses, they are validated by HandleMergeInputChains.
1811 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1814 SDNode *N = Use->getOperand(i).getNode();
1816 if (Use == ImmedUse || Use == Root)
1817 continue; // We are not looking for immediate use.
1822 // Traverse up the operand chain.
1823 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1829 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1830 /// operand node N of U during instruction selection that starts at Root.
1831 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1832 SDNode *Root) const {
1833 if (OptLevel == CodeGenOpt::None) return false;
1834 return N.hasOneUse();
1837 /// IsLegalToFold - Returns true if the specific operand node N of
1838 /// U can be folded during instruction selection that starts at Root.
1839 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1840 CodeGenOpt::Level OptLevel,
1841 bool IgnoreChains) {
1842 if (OptLevel == CodeGenOpt::None) return false;
1844 // If Root use can somehow reach N through a path that that doesn't contain
1845 // U then folding N would create a cycle. e.g. In the following
1846 // diagram, Root can reach N through X. If N is folded into into Root, then
1847 // X is both a predecessor and a successor of U.
1858 // * indicates nodes to be folded together.
1860 // If Root produces glue, then it gets (even more) interesting. Since it
1861 // will be "glued" together with its glue use in the scheduler, we need to
1862 // check if it might reach N.
1881 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1882 // (call it Fold), then X is a predecessor of GU and a successor of
1883 // Fold. But since Fold and GU are glued together, this will create
1884 // a cycle in the scheduling graph.
1886 // If the node has glue, walk down the graph to the "lowest" node in the
1888 EVT VT = Root->getValueType(Root->getNumValues()-1);
1889 while (VT == MVT::Glue) {
1890 SDNode *GU = findGlueUse(Root);
1894 VT = Root->getValueType(Root->getNumValues()-1);
1896 // If our query node has a glue result with a use, we've walked up it. If
1897 // the user (which has already been selected) has a chain or indirectly uses
1898 // the chain, our WalkChainUsers predicate will not consider it. Because of
1899 // this, we cannot ignore chains in this predicate.
1900 IgnoreChains = false;
1904 SmallPtrSet<SDNode*, 16> Visited;
1905 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1908 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1909 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1910 SelectInlineAsmMemoryOperands(Ops);
1912 EVT VTs[] = { MVT::Other, MVT::Glue };
1913 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
1915 return New.getNode();
1919 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1921 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
1922 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1924 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
1925 SDValue New = CurDAG->getCopyFromReg(
1926 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
1928 return New.getNode();
1932 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1934 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1935 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1936 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1937 Op->getOperand(2).getValueType());
1938 SDValue New = CurDAG->getCopyToReg(
1939 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
1941 return New.getNode();
1946 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1947 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1950 /// GetVBR - decode a vbr encoding whose top bit is set.
1951 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1952 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1953 assert(Val >= 128 && "Not a VBR");
1954 Val &= 127; // Remove first vbr bit.
1959 NextBits = MatcherTable[Idx++];
1960 Val |= (NextBits&127) << Shift;
1962 } while (NextBits & 128);
1968 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1969 /// interior glue and chain results to use the new glue and chain results.
1970 void SelectionDAGISel::
1971 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1972 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1974 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1975 bool isMorphNodeTo) {
1976 SmallVector<SDNode*, 4> NowDeadNodes;
1978 // Now that all the normal results are replaced, we replace the chain and
1979 // glue results if present.
1980 if (!ChainNodesMatched.empty()) {
1981 assert(InputChain.getNode() &&
1982 "Matched input chains but didn't produce a chain");
1983 // Loop over all of the nodes we matched that produced a chain result.
1984 // Replace all the chain results with the final chain we ended up with.
1985 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1986 SDNode *ChainNode = ChainNodesMatched[i];
1988 // If this node was already deleted, don't look at it.
1989 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1992 // Don't replace the results of the root node if we're doing a
1994 if (ChainNode == NodeToMatch && isMorphNodeTo)
1997 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1998 if (ChainVal.getValueType() == MVT::Glue)
1999 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2000 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2001 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2003 // If the node became dead and we haven't already seen it, delete it.
2004 if (ChainNode->use_empty() &&
2005 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2006 NowDeadNodes.push_back(ChainNode);
2010 // If the result produces glue, update any glue results in the matched
2011 // pattern with the glue result.
2012 if (InputGlue.getNode()) {
2013 // Handle any interior nodes explicitly marked.
2014 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2015 SDNode *FRN = GlueResultNodesMatched[i];
2017 // If this node was already deleted, don't look at it.
2018 if (FRN->getOpcode() == ISD::DELETED_NODE)
2021 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2022 "Doesn't have a glue result");
2023 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2026 // If the node became dead and we haven't already seen it, delete it.
2027 if (FRN->use_empty() &&
2028 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2029 NowDeadNodes.push_back(FRN);
2033 if (!NowDeadNodes.empty())
2034 CurDAG->RemoveDeadNodes(NowDeadNodes);
2036 DEBUG(dbgs() << "ISEL: Match complete!\n");
2042 CR_LeadsToInteriorNode
2045 /// WalkChainUsers - Walk down the users of the specified chained node that is
2046 /// part of the pattern we're matching, looking at all of the users we find.
2047 /// This determines whether something is an interior node, whether we have a
2048 /// non-pattern node in between two pattern nodes (which prevent folding because
2049 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2050 /// between pattern nodes (in which case the TF becomes part of the pattern).
2052 /// The walk we do here is guaranteed to be small because we quickly get down to
2053 /// already selected nodes "below" us.
2055 WalkChainUsers(const SDNode *ChainedNode,
2056 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2057 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2058 ChainResult Result = CR_Simple;
2060 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2061 E = ChainedNode->use_end(); UI != E; ++UI) {
2062 // Make sure the use is of the chain, not some other value we produce.
2063 if (UI.getUse().getValueType() != MVT::Other) continue;
2067 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2070 // If we see an already-selected machine node, then we've gone beyond the
2071 // pattern that we're selecting down into the already selected chunk of the
2073 unsigned UserOpcode = User->getOpcode();
2074 if (User->isMachineOpcode() ||
2075 UserOpcode == ISD::CopyToReg ||
2076 UserOpcode == ISD::CopyFromReg ||
2077 UserOpcode == ISD::INLINEASM ||
2078 UserOpcode == ISD::EH_LABEL ||
2079 UserOpcode == ISD::LIFETIME_START ||
2080 UserOpcode == ISD::LIFETIME_END) {
2081 // If their node ID got reset to -1 then they've already been selected.
2082 // Treat them like a MachineOpcode.
2083 if (User->getNodeId() == -1)
2087 // If we have a TokenFactor, we handle it specially.
2088 if (User->getOpcode() != ISD::TokenFactor) {
2089 // If the node isn't a token factor and isn't part of our pattern, then it
2090 // must be a random chained node in between two nodes we're selecting.
2091 // This happens when we have something like:
2096 // Because we structurally match the load/store as a read/modify/write,
2097 // but the call is chained between them. We cannot fold in this case
2098 // because it would induce a cycle in the graph.
2099 if (!std::count(ChainedNodesInPattern.begin(),
2100 ChainedNodesInPattern.end(), User))
2101 return CR_InducesCycle;
2103 // Otherwise we found a node that is part of our pattern. For example in:
2107 // This would happen when we're scanning down from the load and see the
2108 // store as a user. Record that there is a use of ChainedNode that is
2109 // part of the pattern and keep scanning uses.
2110 Result = CR_LeadsToInteriorNode;
2111 InteriorChainedNodes.push_back(User);
2115 // If we found a TokenFactor, there are two cases to consider: first if the
2116 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2117 // uses of the TF are in our pattern) we just want to ignore it. Second,
2118 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2124 // | \ DAG's like cheese
2127 // [TokenFactor] [Op]
2134 // In this case, the TokenFactor becomes part of our match and we rewrite it
2135 // as a new TokenFactor.
2137 // To distinguish these two cases, do a recursive walk down the uses.
2138 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2140 // If the uses of the TokenFactor are just already-selected nodes, ignore
2141 // it, it is "below" our pattern.
2143 case CR_InducesCycle:
2144 // If the uses of the TokenFactor lead to nodes that are not part of our
2145 // pattern that are not selected, folding would turn this into a cycle,
2147 return CR_InducesCycle;
2148 case CR_LeadsToInteriorNode:
2149 break; // Otherwise, keep processing.
2152 // Okay, we know we're in the interesting interior case. The TokenFactor
2153 // is now going to be considered part of the pattern so that we rewrite its
2154 // uses (it may have uses that are not part of the pattern) with the
2155 // ultimate chain result of the generated code. We will also add its chain
2156 // inputs as inputs to the ultimate TokenFactor we create.
2157 Result = CR_LeadsToInteriorNode;
2158 ChainedNodesInPattern.push_back(User);
2159 InteriorChainedNodes.push_back(User);
2166 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2167 /// operation for when the pattern matched at least one node with a chains. The
2168 /// input vector contains a list of all of the chained nodes that we match. We
2169 /// must determine if this is a valid thing to cover (i.e. matching it won't
2170 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2171 /// be used as the input node chain for the generated nodes.
2173 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2174 SelectionDAG *CurDAG) {
2175 // Walk all of the chained nodes we've matched, recursively scanning down the
2176 // users of the chain result. This adds any TokenFactor nodes that are caught
2177 // in between chained nodes to the chained and interior nodes list.
2178 SmallVector<SDNode*, 3> InteriorChainedNodes;
2179 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2180 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2181 InteriorChainedNodes) == CR_InducesCycle)
2182 return SDValue(); // Would induce a cycle.
2185 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2186 // that we are interested in. Form our input TokenFactor node.
2187 SmallVector<SDValue, 3> InputChains;
2188 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2189 // Add the input chain of this node to the InputChains list (which will be
2190 // the operands of the generated TokenFactor) if it's not an interior node.
2191 SDNode *N = ChainNodesMatched[i];
2192 if (N->getOpcode() != ISD::TokenFactor) {
2193 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2196 // Otherwise, add the input chain.
2197 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2198 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2199 InputChains.push_back(InChain);
2203 // If we have a token factor, we want to add all inputs of the token factor
2204 // that are not part of the pattern we're matching.
2205 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2206 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2207 N->getOperand(op).getNode()))
2208 InputChains.push_back(N->getOperand(op));
2212 if (InputChains.size() == 1)
2213 return InputChains[0];
2214 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2215 MVT::Other, InputChains);
2218 /// MorphNode - Handle morphing a node in place for the selector.
2219 SDNode *SelectionDAGISel::
2220 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2221 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2222 // It is possible we're using MorphNodeTo to replace a node with no
2223 // normal results with one that has a normal result (or we could be
2224 // adding a chain) and the input could have glue and chains as well.
2225 // In this case we need to shift the operands down.
2226 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2227 // than the old isel though.
2228 int OldGlueResultNo = -1, OldChainResultNo = -1;
2230 unsigned NTMNumResults = Node->getNumValues();
2231 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2232 OldGlueResultNo = NTMNumResults-1;
2233 if (NTMNumResults != 1 &&
2234 Node->getValueType(NTMNumResults-2) == MVT::Other)
2235 OldChainResultNo = NTMNumResults-2;
2236 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2237 OldChainResultNo = NTMNumResults-1;
2239 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2240 // that this deletes operands of the old node that become dead.
2241 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2243 // MorphNodeTo can operate in two ways: if an existing node with the
2244 // specified operands exists, it can just return it. Otherwise, it
2245 // updates the node in place to have the requested operands.
2247 // If we updated the node in place, reset the node ID. To the isel,
2248 // this should be just like a newly allocated machine node.
2252 unsigned ResNumResults = Res->getNumValues();
2253 // Move the glue if needed.
2254 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2255 (unsigned)OldGlueResultNo != ResNumResults-1)
2256 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2257 SDValue(Res, ResNumResults-1));
2259 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2262 // Move the chain reference if needed.
2263 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2264 (unsigned)OldChainResultNo != ResNumResults-1)
2265 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2266 SDValue(Res, ResNumResults-1));
2268 // Otherwise, no replacement happened because the node already exists. Replace
2269 // Uses of the old node with the new one.
2271 CurDAG->ReplaceAllUsesWith(Node, Res);
2276 /// CheckSame - Implements OP_CheckSame.
2277 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2278 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2280 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2281 // Accept if it is exactly the same as a previously recorded node.
2282 unsigned RecNo = MatcherTable[MatcherIndex++];
2283 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2284 return N == RecordedNodes[RecNo].first;
2287 /// CheckChildSame - Implements OP_CheckChildXSame.
2288 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2289 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2291 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2293 if (ChildNo >= N.getNumOperands())
2294 return false; // Match fails if out of range child #.
2295 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2299 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2300 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2301 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2302 const SelectionDAGISel &SDISel) {
2303 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2306 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2307 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2308 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2309 const SelectionDAGISel &SDISel, SDNode *N) {
2310 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2313 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2314 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2316 uint16_t Opc = MatcherTable[MatcherIndex++];
2317 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2318 return N->getOpcode() == Opc;
2321 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2322 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2323 SDValue N, const TargetLowering *TLI) {
2324 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2325 if (N.getValueType() == VT) return true;
2327 // Handle the case when VT is iPTR.
2328 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2331 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2332 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2333 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2334 if (ChildNo >= N.getNumOperands())
2335 return false; // Match fails if out of range child #.
2336 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2339 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2340 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2342 return cast<CondCodeSDNode>(N)->get() ==
2343 (ISD::CondCode)MatcherTable[MatcherIndex++];
2346 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2347 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2348 SDValue N, const TargetLowering *TLI) {
2349 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2350 if (cast<VTSDNode>(N)->getVT() == VT)
2353 // Handle the case when VT is iPTR.
2354 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2357 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2358 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2360 int64_t Val = MatcherTable[MatcherIndex++];
2362 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2364 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2365 return C && C->getSExtValue() == Val;
2368 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2369 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2370 SDValue N, unsigned ChildNo) {
2371 if (ChildNo >= N.getNumOperands())
2372 return false; // Match fails if out of range child #.
2373 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2376 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2377 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2378 SDValue N, const SelectionDAGISel &SDISel) {
2379 int64_t Val = MatcherTable[MatcherIndex++];
2381 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2383 if (N->getOpcode() != ISD::AND) return false;
2385 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2386 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2389 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2390 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2391 SDValue N, const SelectionDAGISel &SDISel) {
2392 int64_t Val = MatcherTable[MatcherIndex++];
2394 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2396 if (N->getOpcode() != ISD::OR) return false;
2398 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2399 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2402 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2403 /// scope, evaluate the current node. If the current predicate is known to
2404 /// fail, set Result=true and return anything. If the current predicate is
2405 /// known to pass, set Result=false and return the MatcherIndex to continue
2406 /// with. If the current predicate is unknown, set Result=false and return the
2407 /// MatcherIndex to continue with.
2408 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2409 unsigned Index, SDValue N,
2411 const SelectionDAGISel &SDISel,
2412 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2413 switch (Table[Index++]) {
2416 return Index-1; // Could not evaluate this predicate.
2417 case SelectionDAGISel::OPC_CheckSame:
2418 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2420 case SelectionDAGISel::OPC_CheckChild0Same:
2421 case SelectionDAGISel::OPC_CheckChild1Same:
2422 case SelectionDAGISel::OPC_CheckChild2Same:
2423 case SelectionDAGISel::OPC_CheckChild3Same:
2424 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2425 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2427 case SelectionDAGISel::OPC_CheckPatternPredicate:
2428 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2430 case SelectionDAGISel::OPC_CheckPredicate:
2431 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2433 case SelectionDAGISel::OPC_CheckOpcode:
2434 Result = !::CheckOpcode(Table, Index, N.getNode());
2436 case SelectionDAGISel::OPC_CheckType:
2437 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2439 case SelectionDAGISel::OPC_CheckChild0Type:
2440 case SelectionDAGISel::OPC_CheckChild1Type:
2441 case SelectionDAGISel::OPC_CheckChild2Type:
2442 case SelectionDAGISel::OPC_CheckChild3Type:
2443 case SelectionDAGISel::OPC_CheckChild4Type:
2444 case SelectionDAGISel::OPC_CheckChild5Type:
2445 case SelectionDAGISel::OPC_CheckChild6Type:
2446 case SelectionDAGISel::OPC_CheckChild7Type:
2447 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2449 SelectionDAGISel::OPC_CheckChild0Type);
2451 case SelectionDAGISel::OPC_CheckCondCode:
2452 Result = !::CheckCondCode(Table, Index, N);
2454 case SelectionDAGISel::OPC_CheckValueType:
2455 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2457 case SelectionDAGISel::OPC_CheckInteger:
2458 Result = !::CheckInteger(Table, Index, N);
2460 case SelectionDAGISel::OPC_CheckChild0Integer:
2461 case SelectionDAGISel::OPC_CheckChild1Integer:
2462 case SelectionDAGISel::OPC_CheckChild2Integer:
2463 case SelectionDAGISel::OPC_CheckChild3Integer:
2464 case SelectionDAGISel::OPC_CheckChild4Integer:
2465 Result = !::CheckChildInteger(Table, Index, N,
2466 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2468 case SelectionDAGISel::OPC_CheckAndImm:
2469 Result = !::CheckAndImm(Table, Index, N, SDISel);
2471 case SelectionDAGISel::OPC_CheckOrImm:
2472 Result = !::CheckOrImm(Table, Index, N, SDISel);
2480 /// FailIndex - If this match fails, this is the index to continue with.
2483 /// NodeStack - The node stack when the scope was formed.
2484 SmallVector<SDValue, 4> NodeStack;
2486 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2487 unsigned NumRecordedNodes;
2489 /// NumMatchedMemRefs - The number of matched memref entries.
2490 unsigned NumMatchedMemRefs;
2492 /// InputChain/InputGlue - The current chain/glue
2493 SDValue InputChain, InputGlue;
2495 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2496 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2499 /// \\brief A DAG update listener to keep the matching state
2500 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2501 /// change the DAG while matching. X86 addressing mode matcher is an example
2503 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2505 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2506 SmallVectorImpl<MatchScope> &MatchScopes;
2508 MatchStateUpdater(SelectionDAG &DAG,
2509 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2510 SmallVectorImpl<MatchScope> &MS) :
2511 SelectionDAG::DAGUpdateListener(DAG),
2512 RecordedNodes(RN), MatchScopes(MS) { }
2514 void NodeDeleted(SDNode *N, SDNode *E) {
2515 // Some early-returns here to avoid the search if we deleted the node or
2516 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2517 // do, so it's unnecessary to update matching state at that point).
2518 // Neither of these can occur currently because we only install this
2519 // update listener during matching a complex patterns.
2520 if (!E || E->isMachineOpcode())
2522 // Performing linear search here does not matter because we almost never
2523 // run this code. You'd have to have a CSE during complex pattern
2525 for (auto &I : RecordedNodes)
2526 if (I.first.getNode() == N)
2529 for (auto &I : MatchScopes)
2530 for (auto &J : I.NodeStack)
2531 if (J.getNode() == N)
2537 SDNode *SelectionDAGISel::
2538 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2539 unsigned TableSize) {
2540 // FIXME: Should these even be selected? Handle these cases in the caller?
2541 switch (NodeToMatch->getOpcode()) {
2544 case ISD::EntryToken: // These nodes remain the same.
2545 case ISD::BasicBlock:
2547 case ISD::RegisterMask:
2548 case ISD::HANDLENODE:
2549 case ISD::MDNODE_SDNODE:
2550 case ISD::TargetConstant:
2551 case ISD::TargetConstantFP:
2552 case ISD::TargetConstantPool:
2553 case ISD::TargetFrameIndex:
2554 case ISD::TargetExternalSymbol:
2555 case ISD::TargetBlockAddress:
2556 case ISD::TargetJumpTable:
2557 case ISD::TargetGlobalTLSAddress:
2558 case ISD::TargetGlobalAddress:
2559 case ISD::TokenFactor:
2560 case ISD::CopyFromReg:
2561 case ISD::CopyToReg:
2563 case ISD::LIFETIME_START:
2564 case ISD::LIFETIME_END:
2565 NodeToMatch->setNodeId(-1); // Mark selected.
2567 case ISD::AssertSext:
2568 case ISD::AssertZext:
2569 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2570 NodeToMatch->getOperand(0));
2572 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2573 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2574 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2575 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2578 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2580 // Set up the node stack with NodeToMatch as the only node on the stack.
2581 SmallVector<SDValue, 8> NodeStack;
2582 SDValue N = SDValue(NodeToMatch, 0);
2583 NodeStack.push_back(N);
2585 // MatchScopes - Scopes used when matching, if a match failure happens, this
2586 // indicates where to continue checking.
2587 SmallVector<MatchScope, 8> MatchScopes;
2589 // RecordedNodes - This is the set of nodes that have been recorded by the
2590 // state machine. The second value is the parent of the node, or null if the
2591 // root is recorded.
2592 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2594 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2596 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2598 // These are the current input chain and glue for use when generating nodes.
2599 // Various Emit operations change these. For example, emitting a copytoreg
2600 // uses and updates these.
2601 SDValue InputChain, InputGlue;
2603 // ChainNodesMatched - If a pattern matches nodes that have input/output
2604 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2605 // which ones they are. The result is captured into this list so that we can
2606 // update the chain results when the pattern is complete.
2607 SmallVector<SDNode*, 3> ChainNodesMatched;
2608 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2610 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2611 NodeToMatch->dump(CurDAG);
2614 // Determine where to start the interpreter. Normally we start at opcode #0,
2615 // but if the state machine starts with an OPC_SwitchOpcode, then we
2616 // accelerate the first lookup (which is guaranteed to be hot) with the
2617 // OpcodeOffset table.
2618 unsigned MatcherIndex = 0;
2620 if (!OpcodeOffset.empty()) {
2621 // Already computed the OpcodeOffset table, just index into it.
2622 if (N.getOpcode() < OpcodeOffset.size())
2623 MatcherIndex = OpcodeOffset[N.getOpcode()];
2624 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2626 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2627 // Otherwise, the table isn't computed, but the state machine does start
2628 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2629 // is the first time we're selecting an instruction.
2632 // Get the size of this case.
2633 unsigned CaseSize = MatcherTable[Idx++];
2635 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2636 if (CaseSize == 0) break;
2638 // Get the opcode, add the index to the table.
2639 uint16_t Opc = MatcherTable[Idx++];
2640 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2641 if (Opc >= OpcodeOffset.size())
2642 OpcodeOffset.resize((Opc+1)*2);
2643 OpcodeOffset[Opc] = Idx;
2647 // Okay, do the lookup for the first opcode.
2648 if (N.getOpcode() < OpcodeOffset.size())
2649 MatcherIndex = OpcodeOffset[N.getOpcode()];
2653 assert(MatcherIndex < TableSize && "Invalid index");
2655 unsigned CurrentOpcodeIndex = MatcherIndex;
2657 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2660 // Okay, the semantics of this operation are that we should push a scope
2661 // then evaluate the first child. However, pushing a scope only to have
2662 // the first check fail (which then pops it) is inefficient. If we can
2663 // determine immediately that the first check (or first several) will
2664 // immediately fail, don't even bother pushing a scope for them.
2668 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2669 if (NumToSkip & 128)
2670 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2671 // Found the end of the scope with no match.
2672 if (NumToSkip == 0) {
2677 FailIndex = MatcherIndex+NumToSkip;
2679 unsigned MatcherIndexOfPredicate = MatcherIndex;
2680 (void)MatcherIndexOfPredicate; // silence warning.
2682 // If we can't evaluate this predicate without pushing a scope (e.g. if
2683 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2684 // push the scope and evaluate the full predicate chain.
2686 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2687 Result, *this, RecordedNodes);
2691 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2692 << "index " << MatcherIndexOfPredicate
2693 << ", continuing at " << FailIndex << "\n");
2694 ++NumDAGIselRetries;
2696 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2697 // move to the next case.
2698 MatcherIndex = FailIndex;
2701 // If the whole scope failed to match, bail.
2702 if (FailIndex == 0) break;
2704 // Push a MatchScope which indicates where to go if the first child fails
2706 MatchScope NewEntry;
2707 NewEntry.FailIndex = FailIndex;
2708 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2709 NewEntry.NumRecordedNodes = RecordedNodes.size();
2710 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2711 NewEntry.InputChain = InputChain;
2712 NewEntry.InputGlue = InputGlue;
2713 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2714 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2715 MatchScopes.push_back(NewEntry);
2718 case OPC_RecordNode: {
2719 // Remember this node, it may end up being an operand in the pattern.
2720 SDNode *Parent = nullptr;
2721 if (NodeStack.size() > 1)
2722 Parent = NodeStack[NodeStack.size()-2].getNode();
2723 RecordedNodes.push_back(std::make_pair(N, Parent));
2727 case OPC_RecordChild0: case OPC_RecordChild1:
2728 case OPC_RecordChild2: case OPC_RecordChild3:
2729 case OPC_RecordChild4: case OPC_RecordChild5:
2730 case OPC_RecordChild6: case OPC_RecordChild7: {
2731 unsigned ChildNo = Opcode-OPC_RecordChild0;
2732 if (ChildNo >= N.getNumOperands())
2733 break; // Match fails if out of range child #.
2735 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2739 case OPC_RecordMemRef:
2740 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2743 case OPC_CaptureGlueInput:
2744 // If the current node has an input glue, capture it in InputGlue.
2745 if (N->getNumOperands() != 0 &&
2746 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2747 InputGlue = N->getOperand(N->getNumOperands()-1);
2750 case OPC_MoveChild: {
2751 unsigned ChildNo = MatcherTable[MatcherIndex++];
2752 if (ChildNo >= N.getNumOperands())
2753 break; // Match fails if out of range child #.
2754 N = N.getOperand(ChildNo);
2755 NodeStack.push_back(N);
2759 case OPC_MoveParent:
2760 // Pop the current node off the NodeStack.
2761 NodeStack.pop_back();
2762 assert(!NodeStack.empty() && "Node stack imbalance!");
2763 N = NodeStack.back();
2767 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2770 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2771 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2772 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2773 Opcode-OPC_CheckChild0Same))
2777 case OPC_CheckPatternPredicate:
2778 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2780 case OPC_CheckPredicate:
2781 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2785 case OPC_CheckComplexPat: {
2786 unsigned CPNum = MatcherTable[MatcherIndex++];
2787 unsigned RecNo = MatcherTable[MatcherIndex++];
2788 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2790 // If target can modify DAG during matching, keep the matching state
2792 std::unique_ptr<MatchStateUpdater> MSU;
2793 if (ComplexPatternFuncMutatesDAG())
2794 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2797 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2798 RecordedNodes[RecNo].first, CPNum,
2803 case OPC_CheckOpcode:
2804 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2808 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2812 case OPC_SwitchOpcode: {
2813 unsigned CurNodeOpcode = N.getOpcode();
2814 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2817 // Get the size of this case.
2818 CaseSize = MatcherTable[MatcherIndex++];
2820 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2821 if (CaseSize == 0) break;
2823 uint16_t Opc = MatcherTable[MatcherIndex++];
2824 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2826 // If the opcode matches, then we will execute this case.
2827 if (CurNodeOpcode == Opc)
2830 // Otherwise, skip over this case.
2831 MatcherIndex += CaseSize;
2834 // If no cases matched, bail out.
2835 if (CaseSize == 0) break;
2837 // Otherwise, execute the case we found.
2838 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2839 << " to " << MatcherIndex << "\n");
2843 case OPC_SwitchType: {
2844 MVT CurNodeVT = N.getSimpleValueType();
2845 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2848 // Get the size of this case.
2849 CaseSize = MatcherTable[MatcherIndex++];
2851 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2852 if (CaseSize == 0) break;
2854 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2855 if (CaseVT == MVT::iPTR)
2856 CaseVT = TLI->getPointerTy();
2858 // If the VT matches, then we will execute this case.
2859 if (CurNodeVT == CaseVT)
2862 // Otherwise, skip over this case.
2863 MatcherIndex += CaseSize;
2866 // If no cases matched, bail out.
2867 if (CaseSize == 0) break;
2869 // Otherwise, execute the case we found.
2870 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2871 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2874 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2875 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2876 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2877 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2878 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2879 Opcode-OPC_CheckChild0Type))
2882 case OPC_CheckCondCode:
2883 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2885 case OPC_CheckValueType:
2886 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2889 case OPC_CheckInteger:
2890 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2892 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2893 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2894 case OPC_CheckChild4Integer:
2895 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2896 Opcode-OPC_CheckChild0Integer)) break;
2898 case OPC_CheckAndImm:
2899 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2901 case OPC_CheckOrImm:
2902 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2905 case OPC_CheckFoldableChainNode: {
2906 assert(NodeStack.size() != 1 && "No parent node");
2907 // Verify that all intermediate nodes between the root and this one have
2909 bool HasMultipleUses = false;
2910 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2911 if (!NodeStack[i].hasOneUse()) {
2912 HasMultipleUses = true;
2915 if (HasMultipleUses) break;
2917 // Check to see that the target thinks this is profitable to fold and that
2918 // we can fold it without inducing cycles in the graph.
2919 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2921 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2922 NodeToMatch, OptLevel,
2923 true/*We validate our own chains*/))
2928 case OPC_EmitInteger: {
2929 MVT::SimpleValueType VT =
2930 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2931 int64_t Val = MatcherTable[MatcherIndex++];
2933 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2934 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2935 CurDAG->getTargetConstant(Val, VT), nullptr));
2938 case OPC_EmitRegister: {
2939 MVT::SimpleValueType VT =
2940 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2941 unsigned RegNo = MatcherTable[MatcherIndex++];
2942 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2943 CurDAG->getRegister(RegNo, VT), nullptr));
2946 case OPC_EmitRegister2: {
2947 // For targets w/ more than 256 register names, the register enum
2948 // values are stored in two bytes in the matcher table (just like
2950 MVT::SimpleValueType VT =
2951 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2952 unsigned RegNo = MatcherTable[MatcherIndex++];
2953 RegNo |= MatcherTable[MatcherIndex++] << 8;
2954 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2955 CurDAG->getRegister(RegNo, VT), nullptr));
2959 case OPC_EmitConvertToTarget: {
2960 // Convert from IMM/FPIMM to target version.
2961 unsigned RecNo = MatcherTable[MatcherIndex++];
2962 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2963 SDValue Imm = RecordedNodes[RecNo].first;
2965 if (Imm->getOpcode() == ISD::Constant) {
2966 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2967 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2968 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2969 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2970 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2973 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2977 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2978 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2979 // These are space-optimized forms of OPC_EmitMergeInputChains.
2980 assert(!InputChain.getNode() &&
2981 "EmitMergeInputChains should be the first chain producing node");
2982 assert(ChainNodesMatched.empty() &&
2983 "Should only have one EmitMergeInputChains per match");
2985 // Read all of the chained nodes.
2986 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2987 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2988 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2990 // FIXME: What if other value results of the node have uses not matched
2992 if (ChainNodesMatched.back() != NodeToMatch &&
2993 !RecordedNodes[RecNo].first.hasOneUse()) {
2994 ChainNodesMatched.clear();
2998 // Merge the input chains if they are not intra-pattern references.
2999 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3001 if (!InputChain.getNode())
3002 break; // Failed to merge.
3006 case OPC_EmitMergeInputChains: {
3007 assert(!InputChain.getNode() &&
3008 "EmitMergeInputChains should be the first chain producing node");
3009 // This node gets a list of nodes we matched in the input that have
3010 // chains. We want to token factor all of the input chains to these nodes
3011 // together. However, if any of the input chains is actually one of the
3012 // nodes matched in this pattern, then we have an intra-match reference.
3013 // Ignore these because the newly token factored chain should not refer to
3015 unsigned NumChains = MatcherTable[MatcherIndex++];
3016 assert(NumChains != 0 && "Can't TF zero chains");
3018 assert(ChainNodesMatched.empty() &&
3019 "Should only have one EmitMergeInputChains per match");
3021 // Read all of the chained nodes.
3022 for (unsigned i = 0; i != NumChains; ++i) {
3023 unsigned RecNo = MatcherTable[MatcherIndex++];
3024 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3025 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3027 // FIXME: What if other value results of the node have uses not matched
3029 if (ChainNodesMatched.back() != NodeToMatch &&
3030 !RecordedNodes[RecNo].first.hasOneUse()) {
3031 ChainNodesMatched.clear();
3036 // If the inner loop broke out, the match fails.
3037 if (ChainNodesMatched.empty())
3040 // Merge the input chains if they are not intra-pattern references.
3041 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3043 if (!InputChain.getNode())
3044 break; // Failed to merge.
3049 case OPC_EmitCopyToReg: {
3050 unsigned RecNo = MatcherTable[MatcherIndex++];
3051 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3052 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3054 if (!InputChain.getNode())
3055 InputChain = CurDAG->getEntryNode();
3057 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3058 DestPhysReg, RecordedNodes[RecNo].first,
3061 InputGlue = InputChain.getValue(1);
3065 case OPC_EmitNodeXForm: {
3066 unsigned XFormNo = MatcherTable[MatcherIndex++];
3067 unsigned RecNo = MatcherTable[MatcherIndex++];
3068 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3069 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3070 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3075 case OPC_MorphNodeTo: {
3076 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3077 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3078 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3079 // Get the result VT list.
3080 unsigned NumVTs = MatcherTable[MatcherIndex++];
3081 SmallVector<EVT, 4> VTs;
3082 for (unsigned i = 0; i != NumVTs; ++i) {
3083 MVT::SimpleValueType VT =
3084 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3085 if (VT == MVT::iPTR)
3086 VT = TLI->getPointerTy().SimpleTy;
3090 if (EmitNodeInfo & OPFL_Chain)
3091 VTs.push_back(MVT::Other);
3092 if (EmitNodeInfo & OPFL_GlueOutput)
3093 VTs.push_back(MVT::Glue);
3095 // This is hot code, so optimize the two most common cases of 1 and 2
3098 if (VTs.size() == 1)
3099 VTList = CurDAG->getVTList(VTs[0]);
3100 else if (VTs.size() == 2)
3101 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3103 VTList = CurDAG->getVTList(VTs);
3105 // Get the operand list.
3106 unsigned NumOps = MatcherTable[MatcherIndex++];
3107 SmallVector<SDValue, 8> Ops;
3108 for (unsigned i = 0; i != NumOps; ++i) {
3109 unsigned RecNo = MatcherTable[MatcherIndex++];
3111 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3113 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3114 Ops.push_back(RecordedNodes[RecNo].first);
3117 // If there are variadic operands to add, handle them now.
3118 if (EmitNodeInfo & OPFL_VariadicInfo) {
3119 // Determine the start index to copy from.
3120 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3121 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3122 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3123 "Invalid variadic node");
3124 // Copy all of the variadic operands, not including a potential glue
3126 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3128 SDValue V = NodeToMatch->getOperand(i);
3129 if (V.getValueType() == MVT::Glue) break;
3134 // If this has chain/glue inputs, add them.
3135 if (EmitNodeInfo & OPFL_Chain)
3136 Ops.push_back(InputChain);
3137 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3138 Ops.push_back(InputGlue);
3141 SDNode *Res = nullptr;
3142 if (Opcode != OPC_MorphNodeTo) {
3143 // If this is a normal EmitNode command, just create the new node and
3144 // add the results to the RecordedNodes list.
3145 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3148 // Add all the non-glue/non-chain results to the RecordedNodes list.
3149 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3150 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3151 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3155 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3156 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3158 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3159 // We will visit the equivalent node later.
3160 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3164 // If the node had chain/glue results, update our notion of the current
3166 if (EmitNodeInfo & OPFL_GlueOutput) {
3167 InputGlue = SDValue(Res, VTs.size()-1);
3168 if (EmitNodeInfo & OPFL_Chain)
3169 InputChain = SDValue(Res, VTs.size()-2);
3170 } else if (EmitNodeInfo & OPFL_Chain)
3171 InputChain = SDValue(Res, VTs.size()-1);
3173 // If the OPFL_MemRefs glue is set on this node, slap all of the
3174 // accumulated memrefs onto it.
3176 // FIXME: This is vastly incorrect for patterns with multiple outputs
3177 // instructions that access memory and for ComplexPatterns that match
3179 if (EmitNodeInfo & OPFL_MemRefs) {
3180 // Only attach load or store memory operands if the generated
3181 // instruction may load or store.
3182 const MCInstrDesc &MCID = TII->get(TargetOpc);
3183 bool mayLoad = MCID.mayLoad();
3184 bool mayStore = MCID.mayStore();
3186 unsigned NumMemRefs = 0;
3187 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3188 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3189 if ((*I)->isLoad()) {
3192 } else if ((*I)->isStore()) {
3200 MachineSDNode::mmo_iterator MemRefs =
3201 MF->allocateMemRefsArray(NumMemRefs);
3203 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3204 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3205 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3206 if ((*I)->isLoad()) {
3209 } else if ((*I)->isStore()) {
3217 cast<MachineSDNode>(Res)
3218 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3222 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3223 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3225 // If this was a MorphNodeTo then we're completely done!
3226 if (Opcode == OPC_MorphNodeTo) {
3227 // Update chain and glue uses.
3228 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3229 InputGlue, GlueResultNodesMatched, true);
3236 case OPC_MarkGlueResults: {
3237 unsigned NumNodes = MatcherTable[MatcherIndex++];
3239 // Read and remember all the glue-result nodes.
3240 for (unsigned i = 0; i != NumNodes; ++i) {
3241 unsigned RecNo = MatcherTable[MatcherIndex++];
3243 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3245 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3246 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3251 case OPC_CompleteMatch: {
3252 // The match has been completed, and any new nodes (if any) have been
3253 // created. Patch up references to the matched dag to use the newly
3255 unsigned NumResults = MatcherTable[MatcherIndex++];
3257 for (unsigned i = 0; i != NumResults; ++i) {
3258 unsigned ResSlot = MatcherTable[MatcherIndex++];
3260 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3262 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3263 SDValue Res = RecordedNodes[ResSlot].first;
3265 assert(i < NodeToMatch->getNumValues() &&
3266 NodeToMatch->getValueType(i) != MVT::Other &&
3267 NodeToMatch->getValueType(i) != MVT::Glue &&
3268 "Invalid number of results to complete!");
3269 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3270 NodeToMatch->getValueType(i) == MVT::iPTR ||
3271 Res.getValueType() == MVT::iPTR ||
3272 NodeToMatch->getValueType(i).getSizeInBits() ==
3273 Res.getValueType().getSizeInBits()) &&
3274 "invalid replacement");
3275 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3278 // If the root node defines glue, add it to the glue nodes to update list.
3279 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3280 GlueResultNodesMatched.push_back(NodeToMatch);
3282 // Update chain and glue uses.
3283 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3284 InputGlue, GlueResultNodesMatched, false);
3286 assert(NodeToMatch->use_empty() &&
3287 "Didn't replace all uses of the node?");
3289 // FIXME: We just return here, which interacts correctly with SelectRoot
3290 // above. We should fix this to not return an SDNode* anymore.
3295 // If the code reached this point, then the match failed. See if there is
3296 // another child to try in the current 'Scope', otherwise pop it until we
3297 // find a case to check.
3298 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3299 ++NumDAGIselRetries;
3301 if (MatchScopes.empty()) {
3302 CannotYetSelect(NodeToMatch);
3306 // Restore the interpreter state back to the point where the scope was
3308 MatchScope &LastScope = MatchScopes.back();
3309 RecordedNodes.resize(LastScope.NumRecordedNodes);
3311 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3312 N = NodeStack.back();
3314 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3315 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3316 MatcherIndex = LastScope.FailIndex;
3318 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3320 InputChain = LastScope.InputChain;
3321 InputGlue = LastScope.InputGlue;
3322 if (!LastScope.HasChainNodesMatched)
3323 ChainNodesMatched.clear();
3324 if (!LastScope.HasGlueResultNodesMatched)
3325 GlueResultNodesMatched.clear();
3327 // Check to see what the offset is at the new MatcherIndex. If it is zero
3328 // we have reached the end of this scope, otherwise we have another child
3329 // in the current scope to try.
3330 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3331 if (NumToSkip & 128)
3332 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3334 // If we have another child in this scope to match, update FailIndex and
3336 if (NumToSkip != 0) {
3337 LastScope.FailIndex = MatcherIndex+NumToSkip;
3341 // End of this scope, pop it and try the next child in the containing
3343 MatchScopes.pop_back();
3350 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3352 raw_string_ostream Msg(msg);
3353 Msg << "Cannot select: ";
3355 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3356 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3357 N->getOpcode() != ISD::INTRINSIC_VOID) {
3358 N->printrFull(Msg, CurDAG);
3359 Msg << "\nIn function: " << MF->getName();
3361 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3363 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3364 if (iid < Intrinsic::num_intrinsics)
3365 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3366 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3367 Msg << "target intrinsic %" << TII->getName(iid);
3369 Msg << "unknown intrinsic #" << iid;
3371 report_fatal_error(Msg.str());
3374 char SelectionDAGISel::ID = 0;