1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLibraryInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
61 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
62 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
63 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
64 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
69 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
70 cl::desc("Enable extra verbose messages in the \"fast\" "
71 "instruction selector"));
73 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
74 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
75 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
76 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
77 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
78 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
79 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
81 // Standard binary operators...
82 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
83 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
84 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
85 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
86 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
87 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
88 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
89 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
90 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
91 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
92 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
93 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
95 // Logical operators...
96 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
97 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
98 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
100 // Memory instructions...
101 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
102 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
103 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
104 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
105 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
106 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
107 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
109 // Convert instructions...
110 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
111 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
112 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
113 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
114 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
115 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
116 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
117 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
118 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
119 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
120 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
121 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
123 // Other instructions...
124 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
125 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
126 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
127 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
128 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
129 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
130 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
131 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
132 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
133 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
134 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
135 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
136 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
137 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
138 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
142 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
143 cl::desc("Enable verbose messages in the \"fast\" "
144 "instruction selector"));
146 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
147 cl::desc("Enable abort calls when \"fast\" instruction fails"));
151 cl::desc("use Machine Branch Probability Info"),
152 cl::init(true), cl::Hidden);
156 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
157 cl::desc("Pop up a window to show dags before the first "
158 "dag combine pass"));
160 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
161 cl::desc("Pop up a window to show dags before legalize types"));
163 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
164 cl::desc("Pop up a window to show dags before legalize"));
166 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
167 cl::desc("Pop up a window to show dags before the second "
168 "dag combine pass"));
170 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
171 cl::desc("Pop up a window to show dags before the post legalize types"
172 " dag combine pass"));
174 ViewISelDAGs("view-isel-dags", cl::Hidden,
175 cl::desc("Pop up a window to show isel dags as they are selected"));
177 ViewSchedDAGs("view-sched-dags", cl::Hidden,
178 cl::desc("Pop up a window to show sched dags as they are processed"));
180 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
181 cl::desc("Pop up a window to show SUnit dags after they are processed"));
183 static const bool ViewDAGCombine1 = false,
184 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
185 ViewDAGCombine2 = false,
186 ViewDAGCombineLT = false,
187 ViewISelDAGs = false, ViewSchedDAGs = false,
188 ViewSUnitDAGs = false;
191 //===---------------------------------------------------------------------===//
193 /// RegisterScheduler class - Track the registration of instruction schedulers.
195 //===---------------------------------------------------------------------===//
196 MachinePassRegistry RegisterScheduler::Registry;
198 //===---------------------------------------------------------------------===//
200 /// ISHeuristic command line option for instruction schedulers.
202 //===---------------------------------------------------------------------===//
203 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
204 RegisterPassParser<RegisterScheduler> >
205 ISHeuristic("pre-RA-sched",
206 cl::init(&createDefaultScheduler),
207 cl::desc("Instruction schedulers available (before register"
210 static RegisterScheduler
211 defaultListDAGScheduler("default", "Best scheduler for the target",
212 createDefaultScheduler);
215 //===--------------------------------------------------------------------===//
216 /// createDefaultScheduler - This creates an instruction scheduler appropriate
218 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
219 CodeGenOpt::Level OptLevel) {
220 const TargetLowering &TLI = IS->getTargetLowering();
221 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
223 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
224 TLI.getSchedulingPreference() == Sched::Source)
225 return createSourceListDAGScheduler(IS, OptLevel);
226 if (TLI.getSchedulingPreference() == Sched::RegPressure)
227 return createBURRListDAGScheduler(IS, OptLevel);
228 if (TLI.getSchedulingPreference() == Sched::Hybrid)
229 return createHybridListDAGScheduler(IS, OptLevel);
230 if (TLI.getSchedulingPreference() == Sched::VLIW)
231 return createVLIWDAGScheduler(IS, OptLevel);
232 assert(TLI.getSchedulingPreference() == Sched::ILP &&
233 "Unknown sched type!");
234 return createILPListDAGScheduler(IS, OptLevel);
238 // EmitInstrWithCustomInserter - This method should be implemented by targets
239 // that mark instructions with the 'usesCustomInserter' flag. These
240 // instructions are special in various ways, which require special support to
241 // insert. The specified MachineInstr is created but not inserted into any
242 // basic blocks, and this method is called to expand it into a sequence of
243 // instructions, potentially also creating new basic blocks and control flow.
244 // When new basic blocks are inserted and the edges from MBB to its successors
245 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
248 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
249 MachineBasicBlock *MBB) const {
251 dbgs() << "If a target marks an instruction with "
252 "'usesCustomInserter', it must implement "
253 "TargetLowering::EmitInstrWithCustomInserter!";
258 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
259 SDNode *Node) const {
260 assert(!MI->hasPostISelHook() &&
261 "If a target marks an instruction with 'hasPostISelHook', "
262 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
265 //===----------------------------------------------------------------------===//
266 // SelectionDAGISel code
267 //===----------------------------------------------------------------------===//
269 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
270 CodeGenOpt::Level OL) :
271 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
272 FuncInfo(new FunctionLoweringInfo(TLI)),
273 CurDAG(new SelectionDAG(tm, OL)),
274 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
278 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
279 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
280 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
281 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
284 SelectionDAGISel::~SelectionDAGISel() {
290 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
291 AU.addRequired<AliasAnalysis>();
292 AU.addPreserved<AliasAnalysis>();
293 AU.addRequired<GCModuleInfo>();
294 AU.addPreserved<GCModuleInfo>();
295 AU.addRequired<TargetLibraryInfo>();
296 if (UseMBPI && OptLevel != CodeGenOpt::None)
297 AU.addRequired<BranchProbabilityInfo>();
298 MachineFunctionPass::getAnalysisUsage(AU);
301 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
302 /// may trap on it. In this case we have to split the edge so that the path
303 /// through the predecessor block that doesn't go to the phi block doesn't
304 /// execute the possibly trapping instruction.
306 /// This is required for correctness, so it must be done at -O0.
308 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
309 // Loop for blocks with phi nodes.
310 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
311 PHINode *PN = dyn_cast<PHINode>(BB->begin());
312 if (PN == 0) continue;
315 // For each block with a PHI node, check to see if any of the input values
316 // are potentially trapping constant expressions. Constant expressions are
317 // the only potentially trapping value that can occur as the argument to a
319 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
320 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
321 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
322 if (CE == 0 || !CE->canTrap()) continue;
324 // The only case we have to worry about is when the edge is critical.
325 // Since this block has a PHI Node, we assume it has multiple input
326 // edges: check to see if the pred has multiple successors.
327 BasicBlock *Pred = PN->getIncomingBlock(i);
328 if (Pred->getTerminator()->getNumSuccessors() == 1)
331 // Okay, we have to split this edge.
332 SplitCriticalEdge(Pred->getTerminator(),
333 GetSuccessorNumber(Pred, BB), SDISel, true);
339 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
340 // Do some sanity-checking on the command-line options.
341 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
342 "-fast-isel-verbose requires -fast-isel");
343 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
344 "-fast-isel-abort requires -fast-isel");
346 const Function &Fn = *mf.getFunction();
347 const TargetInstrInfo &TII = *TM.getInstrInfo();
348 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
351 RegInfo = &MF->getRegInfo();
352 AA = &getAnalysis<AliasAnalysis>();
353 LibInfo = &getAnalysis<TargetLibraryInfo>();
354 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
355 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
357 TargetSubtargetInfo &ST =
358 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
359 ST.resetSubtargetFeatures(MF);
361 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
363 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
365 CurDAG->init(*MF, TTI);
366 FuncInfo->set(Fn, *MF);
368 if (UseMBPI && OptLevel != CodeGenOpt::None)
369 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
373 SDB->init(GFI, *AA, LibInfo);
375 MF->setHasMSInlineAsm(false);
376 SelectAllBasicBlocks(Fn);
378 // If the first basic block in the function has live ins that need to be
379 // copied into vregs, emit the copies into the top of the block before
380 // emitting the code for the block.
381 MachineBasicBlock *EntryMBB = MF->begin();
382 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
384 DenseMap<unsigned, unsigned> LiveInMap;
385 if (!FuncInfo->ArgDbgValues.empty())
386 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
387 E = RegInfo->livein_end(); LI != E; ++LI)
389 LiveInMap.insert(std::make_pair(LI->first, LI->second));
391 // Insert DBG_VALUE instructions for function arguments to the entry block.
392 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
393 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
394 unsigned Reg = MI->getOperand(0).getReg();
395 if (TargetRegisterInfo::isPhysicalRegister(Reg))
396 EntryMBB->insert(EntryMBB->begin(), MI);
398 MachineInstr *Def = RegInfo->getVRegDef(Reg);
399 MachineBasicBlock::iterator InsertPos = Def;
400 // FIXME: VR def may not be in entry block.
401 Def->getParent()->insert(llvm::next(InsertPos), MI);
404 // If Reg is live-in then update debug info to track its copy in a vreg.
405 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
406 if (LDI != LiveInMap.end()) {
407 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
408 MachineBasicBlock::iterator InsertPos = Def;
409 const MDNode *Variable =
410 MI->getOperand(MI->getNumOperands()-1).getMetadata();
411 unsigned Offset = MI->getOperand(1).getImm();
412 // Def is never a terminator here, so it is ok to increment InsertPos.
413 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
414 TII.get(TargetOpcode::DBG_VALUE))
415 .addReg(LDI->second, RegState::Debug)
416 .addImm(Offset).addMetadata(Variable);
418 // If this vreg is directly copied into an exported register then
419 // that COPY instructions also need DBG_VALUE, if it is the only
420 // user of LDI->second.
421 MachineInstr *CopyUseMI = NULL;
422 for (MachineRegisterInfo::use_iterator
423 UI = RegInfo->use_begin(LDI->second);
424 MachineInstr *UseMI = UI.skipInstruction();) {
425 if (UseMI->isDebugValue()) continue;
426 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
427 CopyUseMI = UseMI; continue;
429 // Otherwise this is another use or second copy use.
430 CopyUseMI = NULL; break;
433 MachineInstr *NewMI =
434 BuildMI(*MF, CopyUseMI->getDebugLoc(),
435 TII.get(TargetOpcode::DBG_VALUE))
436 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
437 .addImm(Offset).addMetadata(Variable);
438 MachineBasicBlock::iterator Pos = CopyUseMI;
439 EntryMBB->insertAfter(Pos, NewMI);
444 // Determine if there are any calls in this machine function.
445 MachineFrameInfo *MFI = MF->getFrameInfo();
446 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
449 if (MFI->hasCalls() && MF->hasMSInlineAsm())
452 const MachineBasicBlock *MBB = I;
453 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
455 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
456 if ((MCID.isCall() && !MCID.isReturn()) ||
457 II->isStackAligningInlineAsm()) {
458 MFI->setHasCalls(true);
460 if (II->isMSInlineAsm()) {
461 MF->setHasMSInlineAsm(true);
466 // Determine if there is a call to setjmp in the machine function.
467 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
469 // Replace forward-declared registers with the registers containing
470 // the desired value.
471 MachineRegisterInfo &MRI = MF->getRegInfo();
472 for (DenseMap<unsigned, unsigned>::iterator
473 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
475 unsigned From = I->first;
476 unsigned To = I->second;
477 // If To is also scheduled to be replaced, find what its ultimate
480 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
485 MRI.replaceRegWith(From, To);
488 // Freeze the set of reserved registers now that MachineFrameInfo has been
489 // set up. All the information required by getReservedRegs() should be
491 MRI.freezeReservedRegs(*MF);
493 // Release function-specific state. SDB and CurDAG are already cleared
500 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
501 BasicBlock::const_iterator End,
503 // Lower all of the non-terminator instructions. If a call is emitted
504 // as a tail call, cease emitting nodes for this block. Terminators
505 // are handled below.
506 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
509 // Make sure the root of the DAG is up-to-date.
510 CurDAG->setRoot(SDB->getControlRoot());
511 HadTailCall = SDB->HasTailCall;
514 // Final step, emit the lowered DAG as machine code.
518 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
519 SmallPtrSet<SDNode*, 128> VisitedNodes;
520 SmallVector<SDNode*, 128> Worklist;
522 Worklist.push_back(CurDAG->getRoot().getNode());
528 SDNode *N = Worklist.pop_back_val();
530 // If we've already seen this node, ignore it.
531 if (!VisitedNodes.insert(N))
534 // Otherwise, add all chain operands to the worklist.
535 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
536 if (N->getOperand(i).getValueType() == MVT::Other)
537 Worklist.push_back(N->getOperand(i).getNode());
539 // If this is a CopyToReg with a vreg dest, process it.
540 if (N->getOpcode() != ISD::CopyToReg)
543 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
544 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
547 // Ignore non-scalar or non-integer values.
548 SDValue Src = N->getOperand(2);
549 EVT SrcVT = Src.getValueType();
550 if (!SrcVT.isInteger() || SrcVT.isVector())
553 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
554 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
555 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
556 } while (!Worklist.empty());
559 void SelectionDAGISel::CodeGenAndEmitDAG() {
560 std::string GroupName;
561 if (TimePassesIsEnabled)
562 GroupName = "Instruction Selection and Scheduling";
563 std::string BlockName;
564 int BlockNumber = -1;
567 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
568 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
572 BlockNumber = FuncInfo->MBB->getNumber();
573 BlockName = MF->getName().str() + ":" +
574 FuncInfo->MBB->getBasicBlock()->getName().str();
576 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
577 << " '" << BlockName << "'\n"; CurDAG->dump());
579 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
581 // Run the DAG combiner in pre-legalize mode.
583 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
584 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
587 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
588 << " '" << BlockName << "'\n"; CurDAG->dump());
590 // Second step, hack on the DAG until it only uses operations and types that
591 // the target supports.
592 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
597 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
598 Changed = CurDAG->LegalizeTypes();
601 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
602 << " '" << BlockName << "'\n"; CurDAG->dump());
605 if (ViewDAGCombineLT)
606 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
608 // Run the DAG combiner in post-type-legalize mode.
610 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
611 TimePassesIsEnabled);
612 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
615 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
616 << " '" << BlockName << "'\n"; CurDAG->dump());
620 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
621 Changed = CurDAG->LegalizeVectors();
626 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
627 CurDAG->LegalizeTypes();
630 if (ViewDAGCombineLT)
631 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
633 // Run the DAG combiner in post-type-legalize mode.
635 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
636 TimePassesIsEnabled);
637 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
640 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
641 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
644 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
647 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
651 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
652 << " '" << BlockName << "'\n"; CurDAG->dump());
654 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
656 // Run the DAG combiner in post-legalize mode.
658 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
659 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
662 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
663 << " '" << BlockName << "'\n"; CurDAG->dump());
665 if (OptLevel != CodeGenOpt::None)
666 ComputeLiveOutVRegInfo();
668 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
670 // Third, instruction select all of the operations to machine code, adding the
671 // code to the MachineBasicBlock.
673 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
674 DoInstructionSelection();
677 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
678 << " '" << BlockName << "'\n"; CurDAG->dump());
680 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
682 // Schedule machine code.
683 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
685 NamedRegionTimer T("Instruction Scheduling", GroupName,
686 TimePassesIsEnabled);
687 Scheduler->Run(CurDAG, FuncInfo->MBB);
690 if (ViewSUnitDAGs) Scheduler->viewGraph();
692 // Emit machine code to BB. This can change 'BB' to the last block being
694 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
696 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
698 // FuncInfo->InsertPt is passed by reference and set to the end of the
699 // scheduled instructions.
700 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
703 // If the block was split, make sure we update any references that are used to
704 // update PHI nodes later on.
705 if (FirstMBB != LastMBB)
706 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
708 // Free the scheduler state.
710 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
711 TimePassesIsEnabled);
715 // Free the SelectionDAG state, now that we're finished with it.
720 /// ISelUpdater - helper class to handle updates of the instruction selection
722 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
723 SelectionDAG::allnodes_iterator &ISelPosition;
725 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
726 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
728 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
729 /// deleted is the current ISelPosition node, update ISelPosition.
731 virtual void NodeDeleted(SDNode *N, SDNode *E) {
732 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
736 } // end anonymous namespace
738 void SelectionDAGISel::DoInstructionSelection() {
739 DEBUG(errs() << "===== Instruction selection begins: BB#"
740 << FuncInfo->MBB->getNumber()
741 << " '" << FuncInfo->MBB->getName() << "'\n");
745 // Select target instructions for the DAG.
747 // Number all nodes with a topological order and set DAGSize.
748 DAGSize = CurDAG->AssignTopologicalOrder();
750 // Create a dummy node (which is not added to allnodes), that adds
751 // a reference to the root node, preventing it from being deleted,
752 // and tracking any changes of the root.
753 HandleSDNode Dummy(CurDAG->getRoot());
754 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
757 // Make sure that ISelPosition gets properly updated when nodes are deleted
758 // in calls made from this function.
759 ISelUpdater ISU(*CurDAG, ISelPosition);
761 // The AllNodes list is now topological-sorted. Visit the
762 // nodes by starting at the end of the list (the root of the
763 // graph) and preceding back toward the beginning (the entry
765 while (ISelPosition != CurDAG->allnodes_begin()) {
766 SDNode *Node = --ISelPosition;
767 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
768 // but there are currently some corner cases that it misses. Also, this
769 // makes it theoretically possible to disable the DAGCombiner.
770 if (Node->use_empty())
773 SDNode *ResNode = Select(Node);
775 // FIXME: This is pretty gross. 'Select' should be changed to not return
776 // anything at all and this code should be nuked with a tactical strike.
778 // If node should not be replaced, continue with the next one.
779 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
783 ReplaceUses(Node, ResNode);
785 // If after the replacement this node is not used any more,
786 // remove this dead node.
787 if (Node->use_empty()) // Don't delete EntryToken, etc.
788 CurDAG->RemoveDeadNode(Node);
791 CurDAG->setRoot(Dummy.getValue());
794 DEBUG(errs() << "===== Instruction selection ends:\n");
796 PostprocessISelDAG();
799 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
800 /// do other setup for EH landing-pad blocks.
801 void SelectionDAGISel::PrepareEHLandingPad() {
802 MachineBasicBlock *MBB = FuncInfo->MBB;
804 // Add a label to mark the beginning of the landing pad. Deletion of the
805 // landing pad can thus be detected via the MachineModuleInfo.
806 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
808 // Assign the call site to the landing pad's begin label.
809 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
811 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
812 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
815 // Mark exception register as live in.
816 unsigned Reg = TLI.getExceptionPointerRegister();
817 if (Reg) MBB->addLiveIn(Reg);
819 // Mark exception selector register as live in.
820 Reg = TLI.getExceptionSelectorRegister();
821 if (Reg) MBB->addLiveIn(Reg);
824 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
825 /// load into the specified FoldInst. Note that we could have a sequence where
826 /// multiple LLVM IR instructions are folded into the same machineinstr. For
827 /// example we could have:
828 /// A: x = load i32 *P
829 /// B: y = icmp A, 42
832 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
833 /// any other folded instructions) because it is between A and C.
835 /// If we succeed in folding the load into the operation, return true.
837 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
838 const Instruction *FoldInst,
840 // We know that the load has a single use, but don't know what it is. If it
841 // isn't one of the folded instructions, then we can't succeed here. Handle
842 // this by scanning the single-use users of the load until we get to FoldInst.
843 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
845 const Instruction *TheUser = LI->use_back();
846 while (TheUser != FoldInst && // Scan up until we find FoldInst.
847 // Stay in the right block.
848 TheUser->getParent() == FoldInst->getParent() &&
849 --MaxUsers) { // Don't scan too far.
850 // If there are multiple or no uses of this instruction, then bail out.
851 if (!TheUser->hasOneUse())
854 TheUser = TheUser->use_back();
857 // If we didn't find the fold instruction, then we failed to collapse the
859 if (TheUser != FoldInst)
862 // Don't try to fold volatile loads. Target has to deal with alignment
864 if (LI->isVolatile()) return false;
866 // Figure out which vreg this is going into. If there is no assigned vreg yet
867 // then there actually was no reference to it. Perhaps the load is referenced
868 // by a dead instruction.
869 unsigned LoadReg = FastIS->getRegForValue(LI);
873 // Check to see what the uses of this vreg are. If it has no uses, or more
874 // than one use (at the machine instr level) then we can't fold it.
875 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
876 if (RI == RegInfo->reg_end())
879 // See if there is exactly one use of the vreg. If there are multiple uses,
880 // then the instruction got lowered to multiple machine instructions or the
881 // use of the loaded value ended up being multiple operands of the result, in
882 // either case, we can't fold this.
883 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
884 if (PostRI != RegInfo->reg_end())
887 assert(RI.getOperand().isUse() &&
888 "The only use of the vreg must be a use, we haven't emitted the def!");
890 MachineInstr *User = &*RI;
892 // Set the insertion point properly. Folding the load can cause generation of
893 // other random instructions (like sign extends) for addressing modes, make
894 // sure they get inserted in a logical place before the new instruction.
895 FuncInfo->InsertPt = User;
896 FuncInfo->MBB = User->getParent();
898 // Ask the target to try folding the load.
899 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
902 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
903 /// side-effect free and is either dead or folded into a generated instruction.
904 /// Return false if it needs to be emitted.
905 static bool isFoldedOrDeadInstruction(const Instruction *I,
906 FunctionLoweringInfo *FuncInfo) {
907 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
908 !isa<TerminatorInst>(I) && // Terminators aren't folded.
909 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
910 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
911 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
915 // Collect per Instruction statistics for fast-isel misses. Only those
916 // instructions that cause the bail are accounted for. It does not account for
917 // instructions higher in the block. Thus, summing the per instructions stats
918 // will not add up to what is reported by NumFastIselFailures.
919 static void collectFailStats(const Instruction *I) {
920 switch (I->getOpcode()) {
921 default: assert (0 && "<Invalid operator> ");
924 case Instruction::Ret: NumFastIselFailRet++; return;
925 case Instruction::Br: NumFastIselFailBr++; return;
926 case Instruction::Switch: NumFastIselFailSwitch++; return;
927 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
928 case Instruction::Invoke: NumFastIselFailInvoke++; return;
929 case Instruction::Resume: NumFastIselFailResume++; return;
930 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
932 // Standard binary operators...
933 case Instruction::Add: NumFastIselFailAdd++; return;
934 case Instruction::FAdd: NumFastIselFailFAdd++; return;
935 case Instruction::Sub: NumFastIselFailSub++; return;
936 case Instruction::FSub: NumFastIselFailFSub++; return;
937 case Instruction::Mul: NumFastIselFailMul++; return;
938 case Instruction::FMul: NumFastIselFailFMul++; return;
939 case Instruction::UDiv: NumFastIselFailUDiv++; return;
940 case Instruction::SDiv: NumFastIselFailSDiv++; return;
941 case Instruction::FDiv: NumFastIselFailFDiv++; return;
942 case Instruction::URem: NumFastIselFailURem++; return;
943 case Instruction::SRem: NumFastIselFailSRem++; return;
944 case Instruction::FRem: NumFastIselFailFRem++; return;
946 // Logical operators...
947 case Instruction::And: NumFastIselFailAnd++; return;
948 case Instruction::Or: NumFastIselFailOr++; return;
949 case Instruction::Xor: NumFastIselFailXor++; return;
951 // Memory instructions...
952 case Instruction::Alloca: NumFastIselFailAlloca++; return;
953 case Instruction::Load: NumFastIselFailLoad++; return;
954 case Instruction::Store: NumFastIselFailStore++; return;
955 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
956 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
957 case Instruction::Fence: NumFastIselFailFence++; return;
958 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
960 // Convert instructions...
961 case Instruction::Trunc: NumFastIselFailTrunc++; return;
962 case Instruction::ZExt: NumFastIselFailZExt++; return;
963 case Instruction::SExt: NumFastIselFailSExt++; return;
964 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
965 case Instruction::FPExt: NumFastIselFailFPExt++; return;
966 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
967 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
968 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
969 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
970 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
971 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
972 case Instruction::BitCast: NumFastIselFailBitCast++; return;
974 // Other instructions...
975 case Instruction::ICmp: NumFastIselFailICmp++; return;
976 case Instruction::FCmp: NumFastIselFailFCmp++; return;
977 case Instruction::PHI: NumFastIselFailPHI++; return;
978 case Instruction::Select: NumFastIselFailSelect++; return;
979 case Instruction::Call: NumFastIselFailCall++; return;
980 case Instruction::Shl: NumFastIselFailShl++; return;
981 case Instruction::LShr: NumFastIselFailLShr++; return;
982 case Instruction::AShr: NumFastIselFailAShr++; return;
983 case Instruction::VAArg: NumFastIselFailVAArg++; return;
984 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
985 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
986 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
987 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
988 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
989 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
994 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
995 // Initialize the Fast-ISel state, if needed.
996 FastISel *FastIS = 0;
997 if (TM.Options.EnableFastISel)
998 FastIS = TLI.createFastISel(*FuncInfo, LibInfo);
1000 // Iterate over all basic blocks in the function.
1001 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1002 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1003 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1004 const BasicBlock *LLVMBB = *I;
1006 if (OptLevel != CodeGenOpt::None) {
1007 bool AllPredsVisited = true;
1008 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1010 if (!FuncInfo->VisitedBBs.count(*PI)) {
1011 AllPredsVisited = false;
1016 if (AllPredsVisited) {
1017 for (BasicBlock::const_iterator I = LLVMBB->begin();
1018 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1019 FuncInfo->ComputePHILiveOutRegInfo(PN);
1021 for (BasicBlock::const_iterator I = LLVMBB->begin();
1022 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1023 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1026 FuncInfo->VisitedBBs.insert(LLVMBB);
1029 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1030 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1032 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1033 BasicBlock::const_iterator const End = LLVMBB->end();
1034 BasicBlock::const_iterator BI = End;
1036 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1038 // Setup an EH landing-pad block.
1039 if (FuncInfo->MBB->isLandingPad())
1040 PrepareEHLandingPad();
1042 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1044 FastIS->startNewBlock();
1046 // Emit code for any incoming arguments. This must happen before
1047 // beginning FastISel on the entry block.
1048 if (LLVMBB == &Fn.getEntryBlock()) {
1049 // Lower any arguments needed in this block if this is the entry block.
1050 if (!FastIS->LowerArguments()) {
1051 // Call target indepedent SDISel argument lowering code if the target
1052 // specific routine is not successful.
1053 LowerArguments(LLVMBB);
1054 CurDAG->setRoot(SDB->getControlRoot());
1056 CodeGenAndEmitDAG();
1059 // If we inserted any instructions at the beginning, make a note of
1060 // where they are, so we can be sure to emit subsequent instructions
1062 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1063 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1065 FastIS->setLastLocalValue(0);
1068 unsigned NumFastIselRemaining = std::distance(Begin, End);
1069 // Do FastISel on as many instructions as possible.
1070 for (; BI != Begin; --BI) {
1071 const Instruction *Inst = llvm::prior(BI);
1073 // If we no longer require this instruction, skip it.
1074 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1075 --NumFastIselRemaining;
1079 // Bottom-up: reset the insert pos at the top, after any local-value
1081 FastIS->recomputeInsertPt();
1083 // Try to select the instruction with FastISel.
1084 if (FastIS->SelectInstruction(Inst)) {
1085 --NumFastIselRemaining;
1086 ++NumFastIselSuccess;
1087 // If fast isel succeeded, skip over all the folded instructions, and
1088 // then see if there is a load right before the selected instructions.
1089 // Try to fold the load if so.
1090 const Instruction *BeforeInst = Inst;
1091 while (BeforeInst != Begin) {
1092 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1093 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1096 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1097 BeforeInst->hasOneUse() &&
1098 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1099 // If we succeeded, don't re-select the load.
1100 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1101 --NumFastIselRemaining;
1102 ++NumFastIselSuccess;
1108 if (EnableFastISelVerbose2)
1109 collectFailStats(Inst);
1112 // Then handle certain instructions as single-LLVM-Instruction blocks.
1113 if (isa<CallInst>(Inst)) {
1115 if (EnableFastISelVerbose || EnableFastISelAbort) {
1116 dbgs() << "FastISel missed call: ";
1120 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1121 unsigned &R = FuncInfo->ValueMap[Inst];
1123 R = FuncInfo->CreateRegs(Inst->getType());
1126 bool HadTailCall = false;
1127 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1128 SelectBasicBlock(Inst, BI, HadTailCall);
1130 // If the call was emitted as a tail call, we're done with the block.
1131 // We also need to delete any previously emitted instructions.
1133 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1138 // Recompute NumFastIselRemaining as Selection DAG instruction
1139 // selection may have handled the call, input args, etc.
1140 unsigned RemainingNow = std::distance(Begin, BI);
1141 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1142 NumFastIselRemaining = RemainingNow;
1146 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1147 // Don't abort, and use a different message for terminator misses.
1148 NumFastIselFailures += NumFastIselRemaining;
1149 if (EnableFastISelVerbose || EnableFastISelAbort) {
1150 dbgs() << "FastISel missed terminator: ";
1154 NumFastIselFailures += NumFastIselRemaining;
1155 if (EnableFastISelVerbose || EnableFastISelAbort) {
1156 dbgs() << "FastISel miss: ";
1159 if (EnableFastISelAbort)
1160 // The "fast" selector couldn't handle something and bailed.
1161 // For the purpose of debugging, just abort.
1162 llvm_unreachable("FastISel didn't select the entire block");
1167 FastIS->recomputeInsertPt();
1169 // Lower any arguments needed in this block if this is the entry block.
1170 if (LLVMBB == &Fn.getEntryBlock())
1171 LowerArguments(LLVMBB);
1177 ++NumFastIselBlocks;
1180 // Run SelectionDAG instruction selection on the remainder of the block
1181 // not handled by FastISel. If FastISel is not run, this is the entire
1184 SelectBasicBlock(Begin, BI, HadTailCall);
1188 FuncInfo->PHINodesToUpdate.clear();
1192 SDB->clearDanglingDebugInfo();
1196 SelectionDAGISel::FinishBasicBlock() {
1198 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1199 << FuncInfo->PHINodesToUpdate.size() << "\n";
1200 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1201 dbgs() << "Node " << i << " : ("
1202 << FuncInfo->PHINodesToUpdate[i].first
1203 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1205 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1206 // PHI nodes in successors.
1207 if (SDB->SwitchCases.empty() &&
1208 SDB->JTCases.empty() &&
1209 SDB->BitTestCases.empty()) {
1210 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1211 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1212 assert(PHI->isPHI() &&
1213 "This is not a machine PHI node that we are updating!");
1214 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1216 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1221 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1222 // Lower header first, if it wasn't already lowered
1223 if (!SDB->BitTestCases[i].Emitted) {
1224 // Set the current basic block to the mbb we wish to insert the code into
1225 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1226 FuncInfo->InsertPt = FuncInfo->MBB->end();
1228 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1229 CurDAG->setRoot(SDB->getRoot());
1231 CodeGenAndEmitDAG();
1234 uint32_t UnhandledWeight = 0;
1235 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1236 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1238 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1239 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1240 // Set the current basic block to the mbb we wish to insert the code into
1241 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1242 FuncInfo->InsertPt = FuncInfo->MBB->end();
1245 SDB->visitBitTestCase(SDB->BitTestCases[i],
1246 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1248 SDB->BitTestCases[i].Reg,
1249 SDB->BitTestCases[i].Cases[j],
1252 SDB->visitBitTestCase(SDB->BitTestCases[i],
1253 SDB->BitTestCases[i].Default,
1255 SDB->BitTestCases[i].Reg,
1256 SDB->BitTestCases[i].Cases[j],
1260 CurDAG->setRoot(SDB->getRoot());
1262 CodeGenAndEmitDAG();
1266 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1268 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1269 MachineBasicBlock *PHIBB = PHI->getParent();
1270 assert(PHI->isPHI() &&
1271 "This is not a machine PHI node that we are updating!");
1272 // This is "default" BB. We have two jumps to it. From "header" BB and
1273 // from last "case" BB.
1274 if (PHIBB == SDB->BitTestCases[i].Default)
1275 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1276 .addMBB(SDB->BitTestCases[i].Parent)
1277 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1278 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1279 // One of "cases" BB.
1280 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1282 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1283 if (cBB->isSuccessor(PHIBB))
1284 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1288 SDB->BitTestCases.clear();
1290 // If the JumpTable record is filled in, then we need to emit a jump table.
1291 // Updating the PHI nodes is tricky in this case, since we need to determine
1292 // whether the PHI is a successor of the range check MBB or the jump table MBB
1293 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1294 // Lower header first, if it wasn't already lowered
1295 if (!SDB->JTCases[i].first.Emitted) {
1296 // Set the current basic block to the mbb we wish to insert the code into
1297 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1298 FuncInfo->InsertPt = FuncInfo->MBB->end();
1300 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1302 CurDAG->setRoot(SDB->getRoot());
1304 CodeGenAndEmitDAG();
1307 // Set the current basic block to the mbb we wish to insert the code into
1308 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1309 FuncInfo->InsertPt = FuncInfo->MBB->end();
1311 SDB->visitJumpTable(SDB->JTCases[i].second);
1312 CurDAG->setRoot(SDB->getRoot());
1314 CodeGenAndEmitDAG();
1317 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1319 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1320 MachineBasicBlock *PHIBB = PHI->getParent();
1321 assert(PHI->isPHI() &&
1322 "This is not a machine PHI node that we are updating!");
1323 // "default" BB. We can go there only from header BB.
1324 if (PHIBB == SDB->JTCases[i].second.Default)
1325 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1326 .addMBB(SDB->JTCases[i].first.HeaderBB);
1327 // JT BB. Just iterate over successors here
1328 if (FuncInfo->MBB->isSuccessor(PHIBB))
1329 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1332 SDB->JTCases.clear();
1334 // If the switch block involved a branch to one of the actual successors, we
1335 // need to update PHI nodes in that block.
1336 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1337 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1338 assert(PHI->isPHI() &&
1339 "This is not a machine PHI node that we are updating!");
1340 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1341 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1344 // If we generated any switch lowering information, build and codegen any
1345 // additional DAGs necessary.
1346 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1347 // Set the current basic block to the mbb we wish to insert the code into
1348 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1349 FuncInfo->InsertPt = FuncInfo->MBB->end();
1351 // Determine the unique successors.
1352 SmallVector<MachineBasicBlock *, 2> Succs;
1353 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1354 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1355 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1357 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1358 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1359 CurDAG->setRoot(SDB->getRoot());
1361 CodeGenAndEmitDAG();
1363 // Remember the last block, now that any splitting is done, for use in
1364 // populating PHI nodes in successors.
1365 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1367 // Handle any PHI nodes in successors of this chunk, as if we were coming
1368 // from the original BB before switch expansion. Note that PHI nodes can
1369 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1370 // handle them the right number of times.
1371 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1372 FuncInfo->MBB = Succs[i];
1373 FuncInfo->InsertPt = FuncInfo->MBB->end();
1374 // FuncInfo->MBB may have been removed from the CFG if a branch was
1376 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1377 for (MachineBasicBlock::iterator
1378 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1379 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1380 MachineInstrBuilder PHI(*MF, MBBI);
1381 // This value for this PHI node is recorded in PHINodesToUpdate.
1382 for (unsigned pn = 0; ; ++pn) {
1383 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1384 "Didn't find PHI entry!");
1385 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1386 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1394 SDB->SwitchCases.clear();
1398 /// Create the scheduler. If a specific scheduler was specified
1399 /// via the SchedulerRegistry, use it, otherwise select the
1400 /// one preferred by the target.
1402 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1403 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1407 RegisterScheduler::setDefault(Ctor);
1410 return Ctor(this, OptLevel);
1413 //===----------------------------------------------------------------------===//
1414 // Helper functions used by the generated instruction selector.
1415 //===----------------------------------------------------------------------===//
1416 // Calls to these methods are generated by tblgen.
1418 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1419 /// the dag combiner simplified the 255, we still want to match. RHS is the
1420 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1421 /// specified in the .td file (e.g. 255).
1422 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1423 int64_t DesiredMaskS) const {
1424 const APInt &ActualMask = RHS->getAPIntValue();
1425 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1427 // If the actual mask exactly matches, success!
1428 if (ActualMask == DesiredMask)
1431 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1432 if (ActualMask.intersects(~DesiredMask))
1435 // Otherwise, the DAG Combiner may have proven that the value coming in is
1436 // either already zero or is not demanded. Check for known zero input bits.
1437 APInt NeededMask = DesiredMask & ~ActualMask;
1438 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1441 // TODO: check to see if missing bits are just not demanded.
1443 // Otherwise, this pattern doesn't match.
1447 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1448 /// the dag combiner simplified the 255, we still want to match. RHS is the
1449 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1450 /// specified in the .td file (e.g. 255).
1451 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1452 int64_t DesiredMaskS) const {
1453 const APInt &ActualMask = RHS->getAPIntValue();
1454 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1456 // If the actual mask exactly matches, success!
1457 if (ActualMask == DesiredMask)
1460 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1461 if (ActualMask.intersects(~DesiredMask))
1464 // Otherwise, the DAG Combiner may have proven that the value coming in is
1465 // either already zero or is not demanded. Check for known zero input bits.
1466 APInt NeededMask = DesiredMask & ~ActualMask;
1468 APInt KnownZero, KnownOne;
1469 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1471 // If all the missing bits in the or are already known to be set, match!
1472 if ((NeededMask & KnownOne) == NeededMask)
1475 // TODO: check to see if missing bits are just not demanded.
1477 // Otherwise, this pattern doesn't match.
1482 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1483 /// by tblgen. Others should not call it.
1484 void SelectionDAGISel::
1485 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1486 std::vector<SDValue> InOps;
1487 std::swap(InOps, Ops);
1489 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1490 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1491 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1492 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1494 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1495 if (InOps[e-1].getValueType() == MVT::Glue)
1496 --e; // Don't process a glue operand if it is here.
1499 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1500 if (!InlineAsm::isMemKind(Flags)) {
1501 // Just skip over this operand, copying the operands verbatim.
1502 Ops.insert(Ops.end(), InOps.begin()+i,
1503 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1504 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1506 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1507 "Memory operand with multiple values?");
1508 // Otherwise, this is a memory operand. Ask the target to select it.
1509 std::vector<SDValue> SelOps;
1510 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1511 report_fatal_error("Could not match memory address. Inline asm"
1514 // Add this to the output node.
1516 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1517 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1518 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1523 // Add the glue input back if present.
1524 if (e != InOps.size())
1525 Ops.push_back(InOps.back());
1528 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1531 static SDNode *findGlueUse(SDNode *N) {
1532 unsigned FlagResNo = N->getNumValues()-1;
1533 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1534 SDUse &Use = I.getUse();
1535 if (Use.getResNo() == FlagResNo)
1536 return Use.getUser();
1541 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1542 /// This function recursively traverses up the operand chain, ignoring
1544 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1545 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1546 bool IgnoreChains) {
1547 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1548 // greater than all of its (recursive) operands. If we scan to a point where
1549 // 'use' is smaller than the node we're scanning for, then we know we will
1552 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1553 // happen because we scan down to newly selected nodes in the case of glue
1555 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1558 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1559 // won't fail if we scan it again.
1560 if (!Visited.insert(Use))
1563 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1564 // Ignore chain uses, they are validated by HandleMergeInputChains.
1565 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1568 SDNode *N = Use->getOperand(i).getNode();
1570 if (Use == ImmedUse || Use == Root)
1571 continue; // We are not looking for immediate use.
1576 // Traverse up the operand chain.
1577 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1583 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1584 /// operand node N of U during instruction selection that starts at Root.
1585 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1586 SDNode *Root) const {
1587 if (OptLevel == CodeGenOpt::None) return false;
1588 return N.hasOneUse();
1591 /// IsLegalToFold - Returns true if the specific operand node N of
1592 /// U can be folded during instruction selection that starts at Root.
1593 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1594 CodeGenOpt::Level OptLevel,
1595 bool IgnoreChains) {
1596 if (OptLevel == CodeGenOpt::None) return false;
1598 // If Root use can somehow reach N through a path that that doesn't contain
1599 // U then folding N would create a cycle. e.g. In the following
1600 // diagram, Root can reach N through X. If N is folded into into Root, then
1601 // X is both a predecessor and a successor of U.
1612 // * indicates nodes to be folded together.
1614 // If Root produces glue, then it gets (even more) interesting. Since it
1615 // will be "glued" together with its glue use in the scheduler, we need to
1616 // check if it might reach N.
1635 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1636 // (call it Fold), then X is a predecessor of GU and a successor of
1637 // Fold. But since Fold and GU are glued together, this will create
1638 // a cycle in the scheduling graph.
1640 // If the node has glue, walk down the graph to the "lowest" node in the
1642 EVT VT = Root->getValueType(Root->getNumValues()-1);
1643 while (VT == MVT::Glue) {
1644 SDNode *GU = findGlueUse(Root);
1648 VT = Root->getValueType(Root->getNumValues()-1);
1650 // If our query node has a glue result with a use, we've walked up it. If
1651 // the user (which has already been selected) has a chain or indirectly uses
1652 // the chain, our WalkChainUsers predicate will not consider it. Because of
1653 // this, we cannot ignore chains in this predicate.
1654 IgnoreChains = false;
1658 SmallPtrSet<SDNode*, 16> Visited;
1659 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1662 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1663 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1664 SelectInlineAsmMemoryOperands(Ops);
1666 std::vector<EVT> VTs;
1667 VTs.push_back(MVT::Other);
1668 VTs.push_back(MVT::Glue);
1669 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1670 VTs, &Ops[0], Ops.size());
1672 return New.getNode();
1675 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1676 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1679 /// GetVBR - decode a vbr encoding whose top bit is set.
1680 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1681 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1682 assert(Val >= 128 && "Not a VBR");
1683 Val &= 127; // Remove first vbr bit.
1688 NextBits = MatcherTable[Idx++];
1689 Val |= (NextBits&127) << Shift;
1691 } while (NextBits & 128);
1697 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1698 /// interior glue and chain results to use the new glue and chain results.
1699 void SelectionDAGISel::
1700 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1701 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1703 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1704 bool isMorphNodeTo) {
1705 SmallVector<SDNode*, 4> NowDeadNodes;
1707 // Now that all the normal results are replaced, we replace the chain and
1708 // glue results if present.
1709 if (!ChainNodesMatched.empty()) {
1710 assert(InputChain.getNode() != 0 &&
1711 "Matched input chains but didn't produce a chain");
1712 // Loop over all of the nodes we matched that produced a chain result.
1713 // Replace all the chain results with the final chain we ended up with.
1714 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1715 SDNode *ChainNode = ChainNodesMatched[i];
1717 // If this node was already deleted, don't look at it.
1718 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1721 // Don't replace the results of the root node if we're doing a
1723 if (ChainNode == NodeToMatch && isMorphNodeTo)
1726 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1727 if (ChainVal.getValueType() == MVT::Glue)
1728 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1729 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1730 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1732 // If the node became dead and we haven't already seen it, delete it.
1733 if (ChainNode->use_empty() &&
1734 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1735 NowDeadNodes.push_back(ChainNode);
1739 // If the result produces glue, update any glue results in the matched
1740 // pattern with the glue result.
1741 if (InputGlue.getNode() != 0) {
1742 // Handle any interior nodes explicitly marked.
1743 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1744 SDNode *FRN = GlueResultNodesMatched[i];
1746 // If this node was already deleted, don't look at it.
1747 if (FRN->getOpcode() == ISD::DELETED_NODE)
1750 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1751 "Doesn't have a glue result");
1752 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1755 // If the node became dead and we haven't already seen it, delete it.
1756 if (FRN->use_empty() &&
1757 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1758 NowDeadNodes.push_back(FRN);
1762 if (!NowDeadNodes.empty())
1763 CurDAG->RemoveDeadNodes(NowDeadNodes);
1765 DEBUG(errs() << "ISEL: Match complete!\n");
1771 CR_LeadsToInteriorNode
1774 /// WalkChainUsers - Walk down the users of the specified chained node that is
1775 /// part of the pattern we're matching, looking at all of the users we find.
1776 /// This determines whether something is an interior node, whether we have a
1777 /// non-pattern node in between two pattern nodes (which prevent folding because
1778 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1779 /// between pattern nodes (in which case the TF becomes part of the pattern).
1781 /// The walk we do here is guaranteed to be small because we quickly get down to
1782 /// already selected nodes "below" us.
1784 WalkChainUsers(const SDNode *ChainedNode,
1785 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1786 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1787 ChainResult Result = CR_Simple;
1789 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1790 E = ChainedNode->use_end(); UI != E; ++UI) {
1791 // Make sure the use is of the chain, not some other value we produce.
1792 if (UI.getUse().getValueType() != MVT::Other) continue;
1796 // If we see an already-selected machine node, then we've gone beyond the
1797 // pattern that we're selecting down into the already selected chunk of the
1799 if (User->isMachineOpcode() ||
1800 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1803 unsigned UserOpcode = User->getOpcode();
1804 if (UserOpcode == ISD::CopyToReg ||
1805 UserOpcode == ISD::CopyFromReg ||
1806 UserOpcode == ISD::INLINEASM ||
1807 UserOpcode == ISD::EH_LABEL ||
1808 UserOpcode == ISD::LIFETIME_START ||
1809 UserOpcode == ISD::LIFETIME_END) {
1810 // If their node ID got reset to -1 then they've already been selected.
1811 // Treat them like a MachineOpcode.
1812 if (User->getNodeId() == -1)
1816 // If we have a TokenFactor, we handle it specially.
1817 if (User->getOpcode() != ISD::TokenFactor) {
1818 // If the node isn't a token factor and isn't part of our pattern, then it
1819 // must be a random chained node in between two nodes we're selecting.
1820 // This happens when we have something like:
1825 // Because we structurally match the load/store as a read/modify/write,
1826 // but the call is chained between them. We cannot fold in this case
1827 // because it would induce a cycle in the graph.
1828 if (!std::count(ChainedNodesInPattern.begin(),
1829 ChainedNodesInPattern.end(), User))
1830 return CR_InducesCycle;
1832 // Otherwise we found a node that is part of our pattern. For example in:
1836 // This would happen when we're scanning down from the load and see the
1837 // store as a user. Record that there is a use of ChainedNode that is
1838 // part of the pattern and keep scanning uses.
1839 Result = CR_LeadsToInteriorNode;
1840 InteriorChainedNodes.push_back(User);
1844 // If we found a TokenFactor, there are two cases to consider: first if the
1845 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1846 // uses of the TF are in our pattern) we just want to ignore it. Second,
1847 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1853 // | \ DAG's like cheese
1856 // [TokenFactor] [Op]
1863 // In this case, the TokenFactor becomes part of our match and we rewrite it
1864 // as a new TokenFactor.
1866 // To distinguish these two cases, do a recursive walk down the uses.
1867 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1869 // If the uses of the TokenFactor are just already-selected nodes, ignore
1870 // it, it is "below" our pattern.
1872 case CR_InducesCycle:
1873 // If the uses of the TokenFactor lead to nodes that are not part of our
1874 // pattern that are not selected, folding would turn this into a cycle,
1876 return CR_InducesCycle;
1877 case CR_LeadsToInteriorNode:
1878 break; // Otherwise, keep processing.
1881 // Okay, we know we're in the interesting interior case. The TokenFactor
1882 // is now going to be considered part of the pattern so that we rewrite its
1883 // uses (it may have uses that are not part of the pattern) with the
1884 // ultimate chain result of the generated code. We will also add its chain
1885 // inputs as inputs to the ultimate TokenFactor we create.
1886 Result = CR_LeadsToInteriorNode;
1887 ChainedNodesInPattern.push_back(User);
1888 InteriorChainedNodes.push_back(User);
1895 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1896 /// operation for when the pattern matched at least one node with a chains. The
1897 /// input vector contains a list of all of the chained nodes that we match. We
1898 /// must determine if this is a valid thing to cover (i.e. matching it won't
1899 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1900 /// be used as the input node chain for the generated nodes.
1902 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1903 SelectionDAG *CurDAG) {
1904 // Walk all of the chained nodes we've matched, recursively scanning down the
1905 // users of the chain result. This adds any TokenFactor nodes that are caught
1906 // in between chained nodes to the chained and interior nodes list.
1907 SmallVector<SDNode*, 3> InteriorChainedNodes;
1908 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1909 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1910 InteriorChainedNodes) == CR_InducesCycle)
1911 return SDValue(); // Would induce a cycle.
1914 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1915 // that we are interested in. Form our input TokenFactor node.
1916 SmallVector<SDValue, 3> InputChains;
1917 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1918 // Add the input chain of this node to the InputChains list (which will be
1919 // the operands of the generated TokenFactor) if it's not an interior node.
1920 SDNode *N = ChainNodesMatched[i];
1921 if (N->getOpcode() != ISD::TokenFactor) {
1922 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1925 // Otherwise, add the input chain.
1926 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1927 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1928 InputChains.push_back(InChain);
1932 // If we have a token factor, we want to add all inputs of the token factor
1933 // that are not part of the pattern we're matching.
1934 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1935 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1936 N->getOperand(op).getNode()))
1937 InputChains.push_back(N->getOperand(op));
1942 if (InputChains.size() == 1)
1943 return InputChains[0];
1944 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1945 MVT::Other, &InputChains[0], InputChains.size());
1948 /// MorphNode - Handle morphing a node in place for the selector.
1949 SDNode *SelectionDAGISel::
1950 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1951 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1952 // It is possible we're using MorphNodeTo to replace a node with no
1953 // normal results with one that has a normal result (or we could be
1954 // adding a chain) and the input could have glue and chains as well.
1955 // In this case we need to shift the operands down.
1956 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1957 // than the old isel though.
1958 int OldGlueResultNo = -1, OldChainResultNo = -1;
1960 unsigned NTMNumResults = Node->getNumValues();
1961 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1962 OldGlueResultNo = NTMNumResults-1;
1963 if (NTMNumResults != 1 &&
1964 Node->getValueType(NTMNumResults-2) == MVT::Other)
1965 OldChainResultNo = NTMNumResults-2;
1966 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1967 OldChainResultNo = NTMNumResults-1;
1969 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1970 // that this deletes operands of the old node that become dead.
1971 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1973 // MorphNodeTo can operate in two ways: if an existing node with the
1974 // specified operands exists, it can just return it. Otherwise, it
1975 // updates the node in place to have the requested operands.
1977 // If we updated the node in place, reset the node ID. To the isel,
1978 // this should be just like a newly allocated machine node.
1982 unsigned ResNumResults = Res->getNumValues();
1983 // Move the glue if needed.
1984 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1985 (unsigned)OldGlueResultNo != ResNumResults-1)
1986 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1987 SDValue(Res, ResNumResults-1));
1989 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1992 // Move the chain reference if needed.
1993 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1994 (unsigned)OldChainResultNo != ResNumResults-1)
1995 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1996 SDValue(Res, ResNumResults-1));
1998 // Otherwise, no replacement happened because the node already exists. Replace
1999 // Uses of the old node with the new one.
2001 CurDAG->ReplaceAllUsesWith(Node, Res);
2006 /// CheckSame - Implements OP_CheckSame.
2007 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2008 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2010 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2011 // Accept if it is exactly the same as a previously recorded node.
2012 unsigned RecNo = MatcherTable[MatcherIndex++];
2013 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2014 return N == RecordedNodes[RecNo].first;
2017 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2018 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2019 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2020 const SelectionDAGISel &SDISel) {
2021 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2024 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2025 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2026 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2027 const SelectionDAGISel &SDISel, SDNode *N) {
2028 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2031 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2032 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2034 uint16_t Opc = MatcherTable[MatcherIndex++];
2035 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2036 return N->getOpcode() == Opc;
2039 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2040 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2041 SDValue N, const TargetLowering &TLI) {
2042 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2043 if (N.getValueType() == VT) return true;
2045 // Handle the case when VT is iPTR.
2046 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2049 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2050 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2051 SDValue N, const TargetLowering &TLI,
2053 if (ChildNo >= N.getNumOperands())
2054 return false; // Match fails if out of range child #.
2055 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2059 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2060 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2062 return cast<CondCodeSDNode>(N)->get() ==
2063 (ISD::CondCode)MatcherTable[MatcherIndex++];
2066 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2067 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2068 SDValue N, const TargetLowering &TLI) {
2069 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2070 if (cast<VTSDNode>(N)->getVT() == VT)
2073 // Handle the case when VT is iPTR.
2074 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2077 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2078 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2080 int64_t Val = MatcherTable[MatcherIndex++];
2082 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2084 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2085 return C != 0 && C->getSExtValue() == Val;
2088 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2089 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2090 SDValue N, const SelectionDAGISel &SDISel) {
2091 int64_t Val = MatcherTable[MatcherIndex++];
2093 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2095 if (N->getOpcode() != ISD::AND) return false;
2097 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2098 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2101 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2102 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2103 SDValue N, const SelectionDAGISel &SDISel) {
2104 int64_t Val = MatcherTable[MatcherIndex++];
2106 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2108 if (N->getOpcode() != ISD::OR) return false;
2110 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2111 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2114 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2115 /// scope, evaluate the current node. If the current predicate is known to
2116 /// fail, set Result=true and return anything. If the current predicate is
2117 /// known to pass, set Result=false and return the MatcherIndex to continue
2118 /// with. If the current predicate is unknown, set Result=false and return the
2119 /// MatcherIndex to continue with.
2120 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2121 unsigned Index, SDValue N,
2123 const SelectionDAGISel &SDISel,
2124 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2125 switch (Table[Index++]) {
2128 return Index-1; // Could not evaluate this predicate.
2129 case SelectionDAGISel::OPC_CheckSame:
2130 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2132 case SelectionDAGISel::OPC_CheckPatternPredicate:
2133 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2135 case SelectionDAGISel::OPC_CheckPredicate:
2136 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2138 case SelectionDAGISel::OPC_CheckOpcode:
2139 Result = !::CheckOpcode(Table, Index, N.getNode());
2141 case SelectionDAGISel::OPC_CheckType:
2142 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2144 case SelectionDAGISel::OPC_CheckChild0Type:
2145 case SelectionDAGISel::OPC_CheckChild1Type:
2146 case SelectionDAGISel::OPC_CheckChild2Type:
2147 case SelectionDAGISel::OPC_CheckChild3Type:
2148 case SelectionDAGISel::OPC_CheckChild4Type:
2149 case SelectionDAGISel::OPC_CheckChild5Type:
2150 case SelectionDAGISel::OPC_CheckChild6Type:
2151 case SelectionDAGISel::OPC_CheckChild7Type:
2152 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2153 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2155 case SelectionDAGISel::OPC_CheckCondCode:
2156 Result = !::CheckCondCode(Table, Index, N);
2158 case SelectionDAGISel::OPC_CheckValueType:
2159 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2161 case SelectionDAGISel::OPC_CheckInteger:
2162 Result = !::CheckInteger(Table, Index, N);
2164 case SelectionDAGISel::OPC_CheckAndImm:
2165 Result = !::CheckAndImm(Table, Index, N, SDISel);
2167 case SelectionDAGISel::OPC_CheckOrImm:
2168 Result = !::CheckOrImm(Table, Index, N, SDISel);
2176 /// FailIndex - If this match fails, this is the index to continue with.
2179 /// NodeStack - The node stack when the scope was formed.
2180 SmallVector<SDValue, 4> NodeStack;
2182 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2183 unsigned NumRecordedNodes;
2185 /// NumMatchedMemRefs - The number of matched memref entries.
2186 unsigned NumMatchedMemRefs;
2188 /// InputChain/InputGlue - The current chain/glue
2189 SDValue InputChain, InputGlue;
2191 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2192 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2197 SDNode *SelectionDAGISel::
2198 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2199 unsigned TableSize) {
2200 // FIXME: Should these even be selected? Handle these cases in the caller?
2201 switch (NodeToMatch->getOpcode()) {
2204 case ISD::EntryToken: // These nodes remain the same.
2205 case ISD::BasicBlock:
2207 case ISD::RegisterMask:
2208 //case ISD::VALUETYPE:
2209 //case ISD::CONDCODE:
2210 case ISD::HANDLENODE:
2211 case ISD::MDNODE_SDNODE:
2212 case ISD::TargetConstant:
2213 case ISD::TargetConstantFP:
2214 case ISD::TargetConstantPool:
2215 case ISD::TargetFrameIndex:
2216 case ISD::TargetExternalSymbol:
2217 case ISD::TargetBlockAddress:
2218 case ISD::TargetJumpTable:
2219 case ISD::TargetGlobalTLSAddress:
2220 case ISD::TargetGlobalAddress:
2221 case ISD::TokenFactor:
2222 case ISD::CopyFromReg:
2223 case ISD::CopyToReg:
2225 case ISD::LIFETIME_START:
2226 case ISD::LIFETIME_END:
2227 NodeToMatch->setNodeId(-1); // Mark selected.
2229 case ISD::AssertSext:
2230 case ISD::AssertZext:
2231 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2232 NodeToMatch->getOperand(0));
2234 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2235 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2238 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2240 // Set up the node stack with NodeToMatch as the only node on the stack.
2241 SmallVector<SDValue, 8> NodeStack;
2242 SDValue N = SDValue(NodeToMatch, 0);
2243 NodeStack.push_back(N);
2245 // MatchScopes - Scopes used when matching, if a match failure happens, this
2246 // indicates where to continue checking.
2247 SmallVector<MatchScope, 8> MatchScopes;
2249 // RecordedNodes - This is the set of nodes that have been recorded by the
2250 // state machine. The second value is the parent of the node, or null if the
2251 // root is recorded.
2252 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2254 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2256 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2258 // These are the current input chain and glue for use when generating nodes.
2259 // Various Emit operations change these. For example, emitting a copytoreg
2260 // uses and updates these.
2261 SDValue InputChain, InputGlue;
2263 // ChainNodesMatched - If a pattern matches nodes that have input/output
2264 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2265 // which ones they are. The result is captured into this list so that we can
2266 // update the chain results when the pattern is complete.
2267 SmallVector<SDNode*, 3> ChainNodesMatched;
2268 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2270 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2271 NodeToMatch->dump(CurDAG);
2274 // Determine where to start the interpreter. Normally we start at opcode #0,
2275 // but if the state machine starts with an OPC_SwitchOpcode, then we
2276 // accelerate the first lookup (which is guaranteed to be hot) with the
2277 // OpcodeOffset table.
2278 unsigned MatcherIndex = 0;
2280 if (!OpcodeOffset.empty()) {
2281 // Already computed the OpcodeOffset table, just index into it.
2282 if (N.getOpcode() < OpcodeOffset.size())
2283 MatcherIndex = OpcodeOffset[N.getOpcode()];
2284 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2286 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2287 // Otherwise, the table isn't computed, but the state machine does start
2288 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2289 // is the first time we're selecting an instruction.
2292 // Get the size of this case.
2293 unsigned CaseSize = MatcherTable[Idx++];
2295 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2296 if (CaseSize == 0) break;
2298 // Get the opcode, add the index to the table.
2299 uint16_t Opc = MatcherTable[Idx++];
2300 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2301 if (Opc >= OpcodeOffset.size())
2302 OpcodeOffset.resize((Opc+1)*2);
2303 OpcodeOffset[Opc] = Idx;
2307 // Okay, do the lookup for the first opcode.
2308 if (N.getOpcode() < OpcodeOffset.size())
2309 MatcherIndex = OpcodeOffset[N.getOpcode()];
2313 assert(MatcherIndex < TableSize && "Invalid index");
2315 unsigned CurrentOpcodeIndex = MatcherIndex;
2317 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2320 // Okay, the semantics of this operation are that we should push a scope
2321 // then evaluate the first child. However, pushing a scope only to have
2322 // the first check fail (which then pops it) is inefficient. If we can
2323 // determine immediately that the first check (or first several) will
2324 // immediately fail, don't even bother pushing a scope for them.
2328 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2329 if (NumToSkip & 128)
2330 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2331 // Found the end of the scope with no match.
2332 if (NumToSkip == 0) {
2337 FailIndex = MatcherIndex+NumToSkip;
2339 unsigned MatcherIndexOfPredicate = MatcherIndex;
2340 (void)MatcherIndexOfPredicate; // silence warning.
2342 // If we can't evaluate this predicate without pushing a scope (e.g. if
2343 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2344 // push the scope and evaluate the full predicate chain.
2346 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2347 Result, *this, RecordedNodes);
2351 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2352 << "index " << MatcherIndexOfPredicate
2353 << ", continuing at " << FailIndex << "\n");
2354 ++NumDAGIselRetries;
2356 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2357 // move to the next case.
2358 MatcherIndex = FailIndex;
2361 // If the whole scope failed to match, bail.
2362 if (FailIndex == 0) break;
2364 // Push a MatchScope which indicates where to go if the first child fails
2366 MatchScope NewEntry;
2367 NewEntry.FailIndex = FailIndex;
2368 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2369 NewEntry.NumRecordedNodes = RecordedNodes.size();
2370 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2371 NewEntry.InputChain = InputChain;
2372 NewEntry.InputGlue = InputGlue;
2373 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2374 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2375 MatchScopes.push_back(NewEntry);
2378 case OPC_RecordNode: {
2379 // Remember this node, it may end up being an operand in the pattern.
2381 if (NodeStack.size() > 1)
2382 Parent = NodeStack[NodeStack.size()-2].getNode();
2383 RecordedNodes.push_back(std::make_pair(N, Parent));
2387 case OPC_RecordChild0: case OPC_RecordChild1:
2388 case OPC_RecordChild2: case OPC_RecordChild3:
2389 case OPC_RecordChild4: case OPC_RecordChild5:
2390 case OPC_RecordChild6: case OPC_RecordChild7: {
2391 unsigned ChildNo = Opcode-OPC_RecordChild0;
2392 if (ChildNo >= N.getNumOperands())
2393 break; // Match fails if out of range child #.
2395 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2399 case OPC_RecordMemRef:
2400 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2403 case OPC_CaptureGlueInput:
2404 // If the current node has an input glue, capture it in InputGlue.
2405 if (N->getNumOperands() != 0 &&
2406 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2407 InputGlue = N->getOperand(N->getNumOperands()-1);
2410 case OPC_MoveChild: {
2411 unsigned ChildNo = MatcherTable[MatcherIndex++];
2412 if (ChildNo >= N.getNumOperands())
2413 break; // Match fails if out of range child #.
2414 N = N.getOperand(ChildNo);
2415 NodeStack.push_back(N);
2419 case OPC_MoveParent:
2420 // Pop the current node off the NodeStack.
2421 NodeStack.pop_back();
2422 assert(!NodeStack.empty() && "Node stack imbalance!");
2423 N = NodeStack.back();
2427 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2429 case OPC_CheckPatternPredicate:
2430 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2432 case OPC_CheckPredicate:
2433 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2437 case OPC_CheckComplexPat: {
2438 unsigned CPNum = MatcherTable[MatcherIndex++];
2439 unsigned RecNo = MatcherTable[MatcherIndex++];
2440 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2441 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2442 RecordedNodes[RecNo].first, CPNum,
2447 case OPC_CheckOpcode:
2448 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2452 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2455 case OPC_SwitchOpcode: {
2456 unsigned CurNodeOpcode = N.getOpcode();
2457 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2460 // Get the size of this case.
2461 CaseSize = MatcherTable[MatcherIndex++];
2463 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2464 if (CaseSize == 0) break;
2466 uint16_t Opc = MatcherTable[MatcherIndex++];
2467 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2469 // If the opcode matches, then we will execute this case.
2470 if (CurNodeOpcode == Opc)
2473 // Otherwise, skip over this case.
2474 MatcherIndex += CaseSize;
2477 // If no cases matched, bail out.
2478 if (CaseSize == 0) break;
2480 // Otherwise, execute the case we found.
2481 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2482 << " to " << MatcherIndex << "\n");
2486 case OPC_SwitchType: {
2487 MVT CurNodeVT = N.getValueType().getSimpleVT();
2488 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2491 // Get the size of this case.
2492 CaseSize = MatcherTable[MatcherIndex++];
2494 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2495 if (CaseSize == 0) break;
2497 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2498 if (CaseVT == MVT::iPTR)
2499 CaseVT = TLI.getPointerTy();
2501 // If the VT matches, then we will execute this case.
2502 if (CurNodeVT == CaseVT)
2505 // Otherwise, skip over this case.
2506 MatcherIndex += CaseSize;
2509 // If no cases matched, bail out.
2510 if (CaseSize == 0) break;
2512 // Otherwise, execute the case we found.
2513 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2514 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2517 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2518 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2519 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2520 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2521 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2522 Opcode-OPC_CheckChild0Type))
2525 case OPC_CheckCondCode:
2526 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2528 case OPC_CheckValueType:
2529 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2531 case OPC_CheckInteger:
2532 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2534 case OPC_CheckAndImm:
2535 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2537 case OPC_CheckOrImm:
2538 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2541 case OPC_CheckFoldableChainNode: {
2542 assert(NodeStack.size() != 1 && "No parent node");
2543 // Verify that all intermediate nodes between the root and this one have
2545 bool HasMultipleUses = false;
2546 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2547 if (!NodeStack[i].hasOneUse()) {
2548 HasMultipleUses = true;
2551 if (HasMultipleUses) break;
2553 // Check to see that the target thinks this is profitable to fold and that
2554 // we can fold it without inducing cycles in the graph.
2555 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2557 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2558 NodeToMatch, OptLevel,
2559 true/*We validate our own chains*/))
2564 case OPC_EmitInteger: {
2565 MVT::SimpleValueType VT =
2566 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2567 int64_t Val = MatcherTable[MatcherIndex++];
2569 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2570 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2571 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2574 case OPC_EmitRegister: {
2575 MVT::SimpleValueType VT =
2576 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2577 unsigned RegNo = MatcherTable[MatcherIndex++];
2578 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2579 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2582 case OPC_EmitRegister2: {
2583 // For targets w/ more than 256 register names, the register enum
2584 // values are stored in two bytes in the matcher table (just like
2586 MVT::SimpleValueType VT =
2587 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2588 unsigned RegNo = MatcherTable[MatcherIndex++];
2589 RegNo |= MatcherTable[MatcherIndex++] << 8;
2590 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2591 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2595 case OPC_EmitConvertToTarget: {
2596 // Convert from IMM/FPIMM to target version.
2597 unsigned RecNo = MatcherTable[MatcherIndex++];
2598 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2599 SDValue Imm = RecordedNodes[RecNo].first;
2601 if (Imm->getOpcode() == ISD::Constant) {
2602 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2603 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2604 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2605 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2606 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2609 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2613 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2614 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2615 // These are space-optimized forms of OPC_EmitMergeInputChains.
2616 assert(InputChain.getNode() == 0 &&
2617 "EmitMergeInputChains should be the first chain producing node");
2618 assert(ChainNodesMatched.empty() &&
2619 "Should only have one EmitMergeInputChains per match");
2621 // Read all of the chained nodes.
2622 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2623 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2624 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2626 // FIXME: What if other value results of the node have uses not matched
2628 if (ChainNodesMatched.back() != NodeToMatch &&
2629 !RecordedNodes[RecNo].first.hasOneUse()) {
2630 ChainNodesMatched.clear();
2634 // Merge the input chains if they are not intra-pattern references.
2635 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2637 if (InputChain.getNode() == 0)
2638 break; // Failed to merge.
2642 case OPC_EmitMergeInputChains: {
2643 assert(InputChain.getNode() == 0 &&
2644 "EmitMergeInputChains should be the first chain producing node");
2645 // This node gets a list of nodes we matched in the input that have
2646 // chains. We want to token factor all of the input chains to these nodes
2647 // together. However, if any of the input chains is actually one of the
2648 // nodes matched in this pattern, then we have an intra-match reference.
2649 // Ignore these because the newly token factored chain should not refer to
2651 unsigned NumChains = MatcherTable[MatcherIndex++];
2652 assert(NumChains != 0 && "Can't TF zero chains");
2654 assert(ChainNodesMatched.empty() &&
2655 "Should only have one EmitMergeInputChains per match");
2657 // Read all of the chained nodes.
2658 for (unsigned i = 0; i != NumChains; ++i) {
2659 unsigned RecNo = MatcherTable[MatcherIndex++];
2660 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2661 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2663 // FIXME: What if other value results of the node have uses not matched
2665 if (ChainNodesMatched.back() != NodeToMatch &&
2666 !RecordedNodes[RecNo].first.hasOneUse()) {
2667 ChainNodesMatched.clear();
2672 // If the inner loop broke out, the match fails.
2673 if (ChainNodesMatched.empty())
2676 // Merge the input chains if they are not intra-pattern references.
2677 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2679 if (InputChain.getNode() == 0)
2680 break; // Failed to merge.
2685 case OPC_EmitCopyToReg: {
2686 unsigned RecNo = MatcherTable[MatcherIndex++];
2687 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2688 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2690 if (InputChain.getNode() == 0)
2691 InputChain = CurDAG->getEntryNode();
2693 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2694 DestPhysReg, RecordedNodes[RecNo].first,
2697 InputGlue = InputChain.getValue(1);
2701 case OPC_EmitNodeXForm: {
2702 unsigned XFormNo = MatcherTable[MatcherIndex++];
2703 unsigned RecNo = MatcherTable[MatcherIndex++];
2704 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2705 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2706 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2711 case OPC_MorphNodeTo: {
2712 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2713 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2714 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2715 // Get the result VT list.
2716 unsigned NumVTs = MatcherTable[MatcherIndex++];
2717 SmallVector<EVT, 4> VTs;
2718 for (unsigned i = 0; i != NumVTs; ++i) {
2719 MVT::SimpleValueType VT =
2720 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2721 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2725 if (EmitNodeInfo & OPFL_Chain)
2726 VTs.push_back(MVT::Other);
2727 if (EmitNodeInfo & OPFL_GlueOutput)
2728 VTs.push_back(MVT::Glue);
2730 // This is hot code, so optimize the two most common cases of 1 and 2
2733 if (VTs.size() == 1)
2734 VTList = CurDAG->getVTList(VTs[0]);
2735 else if (VTs.size() == 2)
2736 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2738 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2740 // Get the operand list.
2741 unsigned NumOps = MatcherTable[MatcherIndex++];
2742 SmallVector<SDValue, 8> Ops;
2743 for (unsigned i = 0; i != NumOps; ++i) {
2744 unsigned RecNo = MatcherTable[MatcherIndex++];
2746 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2748 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2749 Ops.push_back(RecordedNodes[RecNo].first);
2752 // If there are variadic operands to add, handle them now.
2753 if (EmitNodeInfo & OPFL_VariadicInfo) {
2754 // Determine the start index to copy from.
2755 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2756 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2757 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2758 "Invalid variadic node");
2759 // Copy all of the variadic operands, not including a potential glue
2761 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2763 SDValue V = NodeToMatch->getOperand(i);
2764 if (V.getValueType() == MVT::Glue) break;
2769 // If this has chain/glue inputs, add them.
2770 if (EmitNodeInfo & OPFL_Chain)
2771 Ops.push_back(InputChain);
2772 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2773 Ops.push_back(InputGlue);
2777 if (Opcode != OPC_MorphNodeTo) {
2778 // If this is a normal EmitNode command, just create the new node and
2779 // add the results to the RecordedNodes list.
2780 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2781 VTList, Ops.data(), Ops.size());
2783 // Add all the non-glue/non-chain results to the RecordedNodes list.
2784 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2785 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2786 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2790 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2791 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2794 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2795 // We will visit the equivalent node later.
2796 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2800 // If the node had chain/glue results, update our notion of the current
2802 if (EmitNodeInfo & OPFL_GlueOutput) {
2803 InputGlue = SDValue(Res, VTs.size()-1);
2804 if (EmitNodeInfo & OPFL_Chain)
2805 InputChain = SDValue(Res, VTs.size()-2);
2806 } else if (EmitNodeInfo & OPFL_Chain)
2807 InputChain = SDValue(Res, VTs.size()-1);
2809 // If the OPFL_MemRefs glue is set on this node, slap all of the
2810 // accumulated memrefs onto it.
2812 // FIXME: This is vastly incorrect for patterns with multiple outputs
2813 // instructions that access memory and for ComplexPatterns that match
2815 if (EmitNodeInfo & OPFL_MemRefs) {
2816 // Only attach load or store memory operands if the generated
2817 // instruction may load or store.
2818 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2819 bool mayLoad = MCID.mayLoad();
2820 bool mayStore = MCID.mayStore();
2822 unsigned NumMemRefs = 0;
2823 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2824 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2825 if ((*I)->isLoad()) {
2828 } else if ((*I)->isStore()) {
2836 MachineSDNode::mmo_iterator MemRefs =
2837 MF->allocateMemRefsArray(NumMemRefs);
2839 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2840 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2841 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2842 if ((*I)->isLoad()) {
2845 } else if ((*I)->isStore()) {
2853 cast<MachineSDNode>(Res)
2854 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2858 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2859 << " node: "; Res->dump(CurDAG); errs() << "\n");
2861 // If this was a MorphNodeTo then we're completely done!
2862 if (Opcode == OPC_MorphNodeTo) {
2863 // Update chain and glue uses.
2864 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2865 InputGlue, GlueResultNodesMatched, true);
2872 case OPC_MarkGlueResults: {
2873 unsigned NumNodes = MatcherTable[MatcherIndex++];
2875 // Read and remember all the glue-result nodes.
2876 for (unsigned i = 0; i != NumNodes; ++i) {
2877 unsigned RecNo = MatcherTable[MatcherIndex++];
2879 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2881 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2882 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2887 case OPC_CompleteMatch: {
2888 // The match has been completed, and any new nodes (if any) have been
2889 // created. Patch up references to the matched dag to use the newly
2891 unsigned NumResults = MatcherTable[MatcherIndex++];
2893 for (unsigned i = 0; i != NumResults; ++i) {
2894 unsigned ResSlot = MatcherTable[MatcherIndex++];
2896 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2898 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2899 SDValue Res = RecordedNodes[ResSlot].first;
2901 assert(i < NodeToMatch->getNumValues() &&
2902 NodeToMatch->getValueType(i) != MVT::Other &&
2903 NodeToMatch->getValueType(i) != MVT::Glue &&
2904 "Invalid number of results to complete!");
2905 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2906 NodeToMatch->getValueType(i) == MVT::iPTR ||
2907 Res.getValueType() == MVT::iPTR ||
2908 NodeToMatch->getValueType(i).getSizeInBits() ==
2909 Res.getValueType().getSizeInBits()) &&
2910 "invalid replacement");
2911 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2914 // If the root node defines glue, add it to the glue nodes to update list.
2915 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2916 GlueResultNodesMatched.push_back(NodeToMatch);
2918 // Update chain and glue uses.
2919 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2920 InputGlue, GlueResultNodesMatched, false);
2922 assert(NodeToMatch->use_empty() &&
2923 "Didn't replace all uses of the node?");
2925 // FIXME: We just return here, which interacts correctly with SelectRoot
2926 // above. We should fix this to not return an SDNode* anymore.
2931 // If the code reached this point, then the match failed. See if there is
2932 // another child to try in the current 'Scope', otherwise pop it until we
2933 // find a case to check.
2934 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2935 ++NumDAGIselRetries;
2937 if (MatchScopes.empty()) {
2938 CannotYetSelect(NodeToMatch);
2942 // Restore the interpreter state back to the point where the scope was
2944 MatchScope &LastScope = MatchScopes.back();
2945 RecordedNodes.resize(LastScope.NumRecordedNodes);
2947 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2948 N = NodeStack.back();
2950 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2951 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2952 MatcherIndex = LastScope.FailIndex;
2954 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2956 InputChain = LastScope.InputChain;
2957 InputGlue = LastScope.InputGlue;
2958 if (!LastScope.HasChainNodesMatched)
2959 ChainNodesMatched.clear();
2960 if (!LastScope.HasGlueResultNodesMatched)
2961 GlueResultNodesMatched.clear();
2963 // Check to see what the offset is at the new MatcherIndex. If it is zero
2964 // we have reached the end of this scope, otherwise we have another child
2965 // in the current scope to try.
2966 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2967 if (NumToSkip & 128)
2968 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2970 // If we have another child in this scope to match, update FailIndex and
2972 if (NumToSkip != 0) {
2973 LastScope.FailIndex = MatcherIndex+NumToSkip;
2977 // End of this scope, pop it and try the next child in the containing
2979 MatchScopes.pop_back();
2986 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2988 raw_string_ostream Msg(msg);
2989 Msg << "Cannot select: ";
2991 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2992 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2993 N->getOpcode() != ISD::INTRINSIC_VOID) {
2994 N->printrFull(Msg, CurDAG);
2995 Msg << "\nIn function: " << MF->getName();
2997 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2999 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3000 if (iid < Intrinsic::num_intrinsics)
3001 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3002 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3003 Msg << "target intrinsic %" << TII->getName(iid);
3005 Msg << "unknown intrinsic #" << iid;
3007 report_fatal_error(Msg.str());
3010 char SelectionDAGISel::ID = 0;