1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
42 #include "llvm/CodeGen/SchedulerRegistry.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/CodeGen/DwarfWriter.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
48 #include "llvm/Target/TargetIntrinsicInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetLowering.h"
51 #include "llvm/Target/TargetMachine.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/Timer.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/ADT/Statistic.h"
63 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
66 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
67 cl::desc("Enable verbose messages in the \"fast\" "
68 "instruction selector"));
70 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
71 cl::desc("Enable abort calls when \"fast\" instruction fails"));
73 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
74 cl::desc("Schedule copies of livein registers"),
79 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
80 cl::desc("Pop up a window to show dags before the first "
83 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize types"));
86 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before legalize"));
89 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
90 cl::desc("Pop up a window to show dags before the second "
93 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
94 cl::desc("Pop up a window to show dags before the post legalize types"
95 " dag combine pass"));
97 ViewISelDAGs("view-isel-dags", cl::Hidden,
98 cl::desc("Pop up a window to show isel dags as they are selected"));
100 ViewSchedDAGs("view-sched-dags", cl::Hidden,
101 cl::desc("Pop up a window to show sched dags as they are processed"));
103 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
104 cl::desc("Pop up a window to show SUnit dags after they are processed"));
106 static const bool ViewDAGCombine1 = false,
107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
108 ViewDAGCombine2 = false,
109 ViewDAGCombineLT = false,
110 ViewISelDAGs = false, ViewSchedDAGs = false,
111 ViewSUnitDAGs = false;
114 //===---------------------------------------------------------------------===//
116 /// RegisterScheduler class - Track the registration of instruction schedulers.
118 //===---------------------------------------------------------------------===//
119 MachinePassRegistry RegisterScheduler::Registry;
121 //===---------------------------------------------------------------------===//
123 /// ISHeuristic command line option for instruction schedulers.
125 //===---------------------------------------------------------------------===//
126 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
127 RegisterPassParser<RegisterScheduler> >
128 ISHeuristic("pre-RA-sched",
129 cl::init(&createDefaultScheduler),
130 cl::desc("Instruction schedulers available (before register"
133 static RegisterScheduler
134 defaultListDAGScheduler("default", "Best scheduler for the target",
135 createDefaultScheduler);
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
142 CodeGenOpt::Level OptLevel) {
143 const TargetLowering &TLI = IS->getTargetLowering();
145 if (OptLevel == CodeGenOpt::None)
146 return createFastDAGScheduler(IS, OptLevel);
147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
148 return createTDListDAGScheduler(IS, OptLevel);
149 assert(TLI.getSchedulingPreference() ==
150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
151 return createBURRListDAGScheduler(IS, OptLevel);
155 // EmitInstrWithCustomInserter - This method should be implemented by targets
156 // that mark instructions with the 'usesCustomInserter' flag. These
157 // instructions are special in various ways, which require special support to
158 // insert. The specified MachineInstr is created but not inserted into any
159 // basic blocks, and this method is called to expand it into a sequence of
160 // instructions, potentially also creating new basic blocks and control flow.
161 // When new basic blocks are inserted and the edges from MBB to its successors
162 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
164 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
165 MachineBasicBlock *MBB,
166 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
168 dbgs() << "If a target marks an instruction with "
169 "'usesCustomInserter', it must implement "
170 "TargetLowering::EmitInstrWithCustomInserter!";
176 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
177 /// physical register has only a single copy use, then coalesced the copy
179 static void EmitLiveInCopy(MachineBasicBlock *MBB,
180 MachineBasicBlock::iterator &InsertPos,
181 unsigned VirtReg, unsigned PhysReg,
182 const TargetRegisterClass *RC,
183 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
184 const MachineRegisterInfo &MRI,
185 const TargetRegisterInfo &TRI,
186 const TargetInstrInfo &TII) {
187 unsigned NumUses = 0;
188 MachineInstr *UseMI = NULL;
189 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
190 UE = MRI.use_end(); UI != UE; ++UI) {
196 // If the number of uses is not one, or the use is not a move instruction,
197 // don't coalesce. Also, only coalesce away a virtual register to virtual
199 bool Coalesced = false;
200 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
202 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
203 TargetRegisterInfo::isVirtualRegister(DstReg)) {
208 // Now find an ideal location to insert the copy.
209 MachineBasicBlock::iterator Pos = InsertPos;
210 while (Pos != MBB->begin()) {
211 MachineInstr *PrevMI = prior(Pos);
212 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
213 // copyRegToReg might emit multiple instructions to do a copy.
214 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
215 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
216 // This is what the BB looks like right now:
221 // We want to insert "r1025 = mov r1". Inserting this copy below the
222 // move to r1024 makes it impossible for that move to be coalesced.
229 break; // Woot! Found a good location.
233 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
234 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
237 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
239 if (&*InsertPos == UseMI) ++InsertPos;
244 /// EmitLiveInCopies - If this is the first basic block in the function,
245 /// and if it has live ins that need to be copied into vregs, emit the
246 /// copies into the block.
247 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
248 const MachineRegisterInfo &MRI,
249 const TargetRegisterInfo &TRI,
250 const TargetInstrInfo &TII) {
251 if (SchedLiveInCopies) {
252 // Emit the copies at a heuristically-determined location in the block.
253 DenseMap<MachineInstr*, unsigned> CopyRegMap;
254 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
255 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
256 E = MRI.livein_end(); LI != E; ++LI)
258 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
259 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
260 RC, CopyRegMap, MRI, TRI, TII);
263 // Emit the copies into the top of the block.
264 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
265 E = MRI.livein_end(); LI != E; ++LI)
267 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
268 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
269 LI->second, LI->first, RC, RC);
270 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
276 //===----------------------------------------------------------------------===//
277 // SelectionDAGISel code
278 //===----------------------------------------------------------------------===//
280 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
281 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
282 FuncInfo(new FunctionLoweringInfo(TLI)),
283 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
284 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
290 SelectionDAGISel::~SelectionDAGISel() {
296 unsigned SelectionDAGISel::MakeReg(EVT VT) {
297 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
300 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
301 AU.addRequired<AliasAnalysis>();
302 AU.addPreserved<AliasAnalysis>();
303 AU.addRequired<GCModuleInfo>();
304 AU.addPreserved<GCModuleInfo>();
305 AU.addRequired<DwarfWriter>();
306 AU.addPreserved<DwarfWriter>();
307 MachineFunctionPass::getAnalysisUsage(AU);
310 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
311 Function &Fn = *mf.getFunction();
313 // Do some sanity-checking on the command-line options.
314 assert((!EnableFastISelVerbose || EnableFastISel) &&
315 "-fast-isel-verbose requires -fast-isel");
316 assert((!EnableFastISelAbort || EnableFastISel) &&
317 "-fast-isel-abort requires -fast-isel");
319 // Get alias analysis for load/store combining.
320 AA = &getAnalysis<AliasAnalysis>();
323 const TargetInstrInfo &TII = *TM.getInstrInfo();
324 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
327 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
330 RegInfo = &MF->getRegInfo();
331 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
333 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
334 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
335 CurDAG->init(*MF, MMI, DW);
336 FuncInfo->set(Fn, *MF, EnableFastISel);
339 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
340 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
342 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
344 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII);
346 // If the first basic block in the function has live ins that need to be
347 // copied into vregs, emit the copies into the top of the block before
348 // emitting the code for the block.
349 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
351 // Add function live-ins to entry block live-in set.
352 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
353 E = RegInfo->livein_end(); I != E; ++I)
354 MF->begin()->addLiveIn(I->first);
357 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
358 "Not all catch info was assigned to a landing pad!");
366 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
367 /// attached with this instruction.
368 static void SetDebugLoc(unsigned MDDbgKind, Instruction *I,
369 SelectionDAGBuilder *SDB,
370 FastISel *FastIS, MachineFunction *MF) {
371 if (isa<DbgInfoIntrinsic>(I)) return;
373 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) {
374 DILocation DILoc(Dbg);
375 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
377 SDB->setCurDebugLoc(Loc);
380 FastIS->setCurDebugLoc(Loc);
382 // If the function doesn't have a default debug location yet, set
383 // it. This is kind of a hack.
384 if (MF->getDefaultDebugLoc().isUnknown())
385 MF->setDefaultDebugLoc(Loc);
389 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
390 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
391 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc());
393 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc());
396 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
397 BasicBlock::iterator Begin,
398 BasicBlock::iterator End,
400 SDB->setCurrentBasicBlock(BB);
401 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg");
403 // Lower all of the non-terminator instructions. If a call is emitted
404 // as a tail call, cease emitting nodes for this block.
405 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
406 SetDebugLoc(MDDbgKind, I, SDB, 0, MF);
408 if (!isa<TerminatorInst>(I)) {
411 // Set the current debug location back to "unknown" so that it doesn't
412 // spuriously apply to subsequent instructions.
413 ResetDebugLoc(SDB, 0);
417 if (!SDB->HasTailCall) {
418 // Ensure that all instructions which are used outside of their defining
419 // blocks are available as virtual registers. Invoke is handled elsewhere.
420 for (BasicBlock::iterator I = Begin; I != End; ++I)
421 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
422 SDB->CopyToExportRegsIfNeeded(I);
424 // Handle PHI nodes in successor blocks.
425 if (End == LLVMBB->end()) {
426 HandlePHINodesInSuccessorBlocks(LLVMBB);
428 // Lower the terminator after the copies are emitted.
429 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF);
430 SDB->visit(*LLVMBB->getTerminator());
431 ResetDebugLoc(SDB, 0);
435 // Make sure the root of the DAG is up-to-date.
436 CurDAG->setRoot(SDB->getControlRoot());
438 // Final step, emit the lowered DAG as machine code.
440 HadTailCall = SDB->HasTailCall;
445 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
446 /// nodes from the worklist.
447 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
448 SmallVector<SDNode*, 128> &Worklist;
450 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl) : Worklist(wl) {}
452 virtual void NodeDeleted(SDNode *N, SDNode *E) {
453 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N),
457 virtual void NodeUpdated(SDNode *N) {
463 /// TrivialTruncElim - Eliminate some trivial nops that can result from
464 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
465 static bool TrivialTruncElim(SDValue Op,
466 TargetLowering::TargetLoweringOpt &TLO) {
467 SDValue N0 = Op.getOperand(0);
468 EVT VT = Op.getValueType();
469 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
470 N0.getOpcode() == ISD::SIGN_EXTEND ||
471 N0.getOpcode() == ISD::ANY_EXTEND) &&
472 N0.getOperand(0).getValueType() == VT) {
473 return TLO.CombineTo(Op, N0.getOperand(0));
478 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
479 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
480 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
481 void SelectionDAGISel::ShrinkDemandedOps() {
482 SmallVector<SDNode*, 128> Worklist;
484 // Add all the dag nodes to the worklist.
485 Worklist.reserve(CurDAG->allnodes_size());
486 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
487 E = CurDAG->allnodes_end(); I != E; ++I)
488 Worklist.push_back(I);
494 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
495 while (!Worklist.empty()) {
496 SDNode *N = Worklist.pop_back_val();
498 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
499 CurDAG->DeleteNode(N);
503 // Run ShrinkDemandedOp on scalar binary operations.
504 if (N->getNumValues() == 1 &&
505 N->getValueType(0).isSimple() && N->getValueType(0).isInteger()) {
506 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
507 APInt Demanded = APInt::getAllOnesValue(BitWidth);
508 APInt KnownZero, KnownOne;
509 if (TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
510 KnownZero, KnownOne, TLO) ||
511 (N->getOpcode() == ISD::TRUNCATE &&
512 TrivialTruncElim(SDValue(N, 0), TLO))) {
514 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N),
516 Worklist.push_back(N);
518 // Replace the old value with the new one.
519 DEBUG(errs() << "\nReplacing ";
520 TLO.Old.getNode()->dump(CurDAG);
521 errs() << "\nWith: ";
522 TLO.New.getNode()->dump(CurDAG);
525 Worklist.push_back(TLO.New.getNode());
527 SDOPsWorkListRemover DeadNodes(Worklist);
528 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
530 if (TLO.Old.getNode()->use_empty()) {
531 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
533 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
534 if (OpNode->hasOneUse()) {
535 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(),
536 OpNode), Worklist.end());
537 Worklist.push_back(OpNode);
541 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(),
542 TLO.Old.getNode()), Worklist.end());
543 CurDAG->DeleteNode(TLO.Old.getNode());
550 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
551 SmallPtrSet<SDNode*, 128> VisitedNodes;
552 SmallVector<SDNode*, 128> Worklist;
554 Worklist.push_back(CurDAG->getRoot().getNode());
561 SDNode *N = Worklist.pop_back_val();
563 // If we've already seen this node, ignore it.
564 if (!VisitedNodes.insert(N))
567 // Otherwise, add all chain operands to the worklist.
568 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
569 if (N->getOperand(i).getValueType() == MVT::Other)
570 Worklist.push_back(N->getOperand(i).getNode());
572 // If this is a CopyToReg with a vreg dest, process it.
573 if (N->getOpcode() != ISD::CopyToReg)
576 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
577 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
580 // Ignore non-scalar or non-integer values.
581 SDValue Src = N->getOperand(2);
582 EVT SrcVT = Src.getValueType();
583 if (!SrcVT.isInteger() || SrcVT.isVector())
586 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
587 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
588 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
590 // Only install this information if it tells us something.
591 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
592 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
593 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
594 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
595 FunctionLoweringInfo::LiveOutInfo &LOI =
596 FuncInfo->LiveOutRegInfo[DestReg];
597 LOI.NumSignBits = NumSignBits;
598 LOI.KnownOne = KnownOne;
599 LOI.KnownZero = KnownZero;
601 } while (!Worklist.empty());
604 void SelectionDAGISel::CodeGenAndEmitDAG() {
605 std::string GroupName;
606 if (TimePassesIsEnabled)
607 GroupName = "Instruction Selection and Scheduling";
608 std::string BlockName;
609 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
610 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
612 BlockName = MF->getFunction()->getNameStr() + ":" +
613 BB->getBasicBlock()->getNameStr();
615 DEBUG(dbgs() << "Initial selection DAG:\n");
616 DEBUG(CurDAG->dump());
618 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
620 // Run the DAG combiner in pre-legalize mode.
621 if (TimePassesIsEnabled) {
622 NamedRegionTimer T("DAG Combining 1", GroupName);
623 CurDAG->Combine(Unrestricted, *AA, OptLevel);
625 CurDAG->Combine(Unrestricted, *AA, OptLevel);
628 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
629 DEBUG(CurDAG->dump());
631 // Second step, hack on the DAG until it only uses operations and types that
632 // the target supports.
633 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
637 if (TimePassesIsEnabled) {
638 NamedRegionTimer T("Type Legalization", GroupName);
639 Changed = CurDAG->LegalizeTypes();
641 Changed = CurDAG->LegalizeTypes();
644 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
645 DEBUG(CurDAG->dump());
648 if (ViewDAGCombineLT)
649 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
651 // Run the DAG combiner in post-type-legalize mode.
652 if (TimePassesIsEnabled) {
653 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
654 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
656 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
659 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
660 DEBUG(CurDAG->dump());
663 if (TimePassesIsEnabled) {
664 NamedRegionTimer T("Vector Legalization", GroupName);
665 Changed = CurDAG->LegalizeVectors();
667 Changed = CurDAG->LegalizeVectors();
671 if (TimePassesIsEnabled) {
672 NamedRegionTimer T("Type Legalization 2", GroupName);
673 CurDAG->LegalizeTypes();
675 CurDAG->LegalizeTypes();
678 if (ViewDAGCombineLT)
679 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
681 // Run the DAG combiner in post-type-legalize mode.
682 if (TimePassesIsEnabled) {
683 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
684 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
686 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
689 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
690 DEBUG(CurDAG->dump());
693 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
695 if (TimePassesIsEnabled) {
696 NamedRegionTimer T("DAG Legalization", GroupName);
697 CurDAG->Legalize(OptLevel);
699 CurDAG->Legalize(OptLevel);
702 DEBUG(dbgs() << "Legalized selection DAG:\n");
703 DEBUG(CurDAG->dump());
705 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
707 // Run the DAG combiner in post-legalize mode.
708 if (TimePassesIsEnabled) {
709 NamedRegionTimer T("DAG Combining 2", GroupName);
710 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
712 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
715 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
716 DEBUG(CurDAG->dump());
718 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
720 if (OptLevel != CodeGenOpt::None) {
722 ComputeLiveOutVRegInfo();
725 // Third, instruction select all of the operations to machine code, adding the
726 // code to the MachineBasicBlock.
727 if (TimePassesIsEnabled) {
728 NamedRegionTimer T("Instruction Selection", GroupName);
729 DoInstructionSelection();
731 DoInstructionSelection();
734 DEBUG(dbgs() << "Selected selection DAG:\n");
735 DEBUG(CurDAG->dump());
737 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
739 // Schedule machine code.
740 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
741 if (TimePassesIsEnabled) {
742 NamedRegionTimer T("Instruction Scheduling", GroupName);
743 Scheduler->Run(CurDAG, BB, BB->end());
745 Scheduler->Run(CurDAG, BB, BB->end());
748 if (ViewSUnitDAGs) Scheduler->viewGraph();
750 // Emit machine code to BB. This can change 'BB' to the last block being
752 if (TimePassesIsEnabled) {
753 NamedRegionTimer T("Instruction Creation", GroupName);
754 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
756 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
759 // Free the scheduler state.
760 if (TimePassesIsEnabled) {
761 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
767 DEBUG(dbgs() << "Selected machine code:\n");
771 void SelectionDAGISel::DoInstructionSelection() {
772 DEBUG(errs() << "===== Instruction selection begins:\n");
776 // Select target instructions for the DAG.
778 // Number all nodes with a topological order and set DAGSize.
779 DAGSize = CurDAG->AssignTopologicalOrder();
781 // Create a dummy node (which is not added to allnodes), that adds
782 // a reference to the root node, preventing it from being deleted,
783 // and tracking any changes of the root.
784 HandleSDNode Dummy(CurDAG->getRoot());
785 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
788 // The AllNodes list is now topological-sorted. Visit the
789 // nodes by starting at the end of the list (the root of the
790 // graph) and preceding back toward the beginning (the entry
792 while (ISelPosition != CurDAG->allnodes_begin()) {
793 SDNode *Node = --ISelPosition;
794 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
795 // but there are currently some corner cases that it misses. Also, this
796 // makes it theoretically possible to disable the DAGCombiner.
797 if (Node->use_empty())
800 SDNode *ResNode = Select(Node);
802 // FIXME: This is pretty gross. 'Select' should be changed to not return
803 // anything at all and this code should be nuked with a tactical strike.
805 // If node should not be replaced, continue with the next one.
806 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
810 ReplaceUses(Node, ResNode);
812 // If after the replacement this node is not used any more,
813 // remove this dead node.
814 if (Node->use_empty()) { // Don't delete EntryToken, etc.
815 ISelUpdater ISU(ISelPosition);
816 CurDAG->RemoveDeadNode(Node, &ISU);
820 CurDAG->setRoot(Dummy.getValue());
822 DEBUG(errs() << "===== Instruction selection ends:\n");
824 PostprocessISelDAG();
826 // FIXME: This shouldn't be needed, remove it.
827 CurDAG->RemoveDeadNodes();
831 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
833 MachineModuleInfo *MMI,
835 const TargetInstrInfo &TII) {
836 // Initialize the Fast-ISel state, if needed.
837 FastISel *FastIS = 0;
839 FastIS = TLI.createFastISel(MF, MMI, DW,
842 FuncInfo->StaticAllocaMap
844 , FuncInfo->CatchInfoLost
848 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg");
850 // Iterate over all basic blocks in the function.
851 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
852 BasicBlock *LLVMBB = &*I;
853 BB = FuncInfo->MBBMap[LLVMBB];
855 BasicBlock::iterator const Begin = LLVMBB->begin();
856 BasicBlock::iterator const End = LLVMBB->end();
857 BasicBlock::iterator BI = Begin;
859 // Lower any arguments needed in this block if this is the entry block.
860 bool SuppressFastISel = false;
861 if (LLVMBB == &Fn.getEntryBlock()) {
862 LowerArguments(LLVMBB);
864 // If any of the arguments has the byval attribute, forgo
865 // fast-isel in the entry block.
868 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
870 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
871 if (EnableFastISelVerbose || EnableFastISelAbort)
872 dbgs() << "FastISel skips entry block due to byval argument\n";
873 SuppressFastISel = true;
879 if (MMI && BB->isLandingPad()) {
880 // Add a label to mark the beginning of the landing pad. Deletion of the
881 // landing pad can thus be detected via the MachineModuleInfo.
882 unsigned LabelID = MMI->addLandingPad(BB);
884 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
885 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID);
887 // Mark exception register as live in.
888 unsigned Reg = TLI.getExceptionAddressRegister();
889 if (Reg) BB->addLiveIn(Reg);
891 // Mark exception selector register as live in.
892 Reg = TLI.getExceptionSelectorRegister();
893 if (Reg) BB->addLiveIn(Reg);
895 // FIXME: Hack around an exception handling flaw (PR1508): the personality
896 // function and list of typeids logically belong to the invoke (or, if you
897 // like, the basic block containing the invoke), and need to be associated
898 // with it in the dwarf exception handling tables. Currently however the
899 // information is provided by an intrinsic (eh.selector) that can be moved
900 // to unexpected places by the optimizers: if the unwind edge is critical,
901 // then breaking it can result in the intrinsics being in the successor of
902 // the landing pad, not the landing pad itself. This results
903 // in exceptions not being caught because no typeids are associated with
904 // the invoke. This may not be the only way things can go wrong, but it
905 // is the only way we try to work around for the moment.
906 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
908 if (Br && Br->isUnconditional()) { // Critical edge?
909 BasicBlock::iterator I, E;
910 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
911 if (isa<EHSelectorInst>(I))
915 // No catch info found - try to extract some from the successor.
916 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
920 // Before doing SelectionDAG ISel, see if FastISel has been requested.
921 if (FastIS && !SuppressFastISel) {
922 // Emit code for any incoming arguments. This must happen before
923 // beginning FastISel on the entry block.
924 if (LLVMBB == &Fn.getEntryBlock()) {
925 CurDAG->setRoot(SDB->getControlRoot());
929 FastIS->startNewBlock(BB);
930 // Do FastISel on as many instructions as possible.
931 for (; BI != End; ++BI) {
932 // Just before the terminator instruction, insert instructions to
933 // feed PHI nodes in successor blocks.
934 if (isa<TerminatorInst>(BI))
935 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
936 ++NumFastIselFailures;
937 ResetDebugLoc(SDB, FastIS);
938 if (EnableFastISelVerbose || EnableFastISelAbort) {
939 dbgs() << "FastISel miss: ";
942 assert(!EnableFastISelAbort &&
943 "FastISel didn't handle a PHI in a successor");
947 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF);
949 // Try to select the instruction with FastISel.
950 if (FastIS->SelectInstruction(BI)) {
951 ResetDebugLoc(SDB, FastIS);
955 // Clear out the debug location so that it doesn't carry over to
956 // unrelated instructions.
957 ResetDebugLoc(SDB, FastIS);
959 // Then handle certain instructions as single-LLVM-Instruction blocks.
960 if (isa<CallInst>(BI)) {
961 ++NumFastIselFailures;
962 if (EnableFastISelVerbose || EnableFastISelAbort) {
963 dbgs() << "FastISel missed call: ";
967 if (!BI->getType()->isVoidTy()) {
968 unsigned &R = FuncInfo->ValueMap[BI];
970 R = FuncInfo->CreateRegForValue(BI);
973 bool HadTailCall = false;
974 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
976 // If the call was emitted as a tail call, we're done with the block.
982 // If the instruction was codegen'd with multiple blocks,
983 // inform the FastISel object where to resume inserting.
984 FastIS->setCurrentBlock(BB);
988 // Otherwise, give up on FastISel for the rest of the block.
989 // For now, be a little lenient about non-branch terminators.
990 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
991 ++NumFastIselFailures;
992 if (EnableFastISelVerbose || EnableFastISelAbort) {
993 dbgs() << "FastISel miss: ";
996 if (EnableFastISelAbort)
997 // The "fast" selector couldn't handle something and bailed.
998 // For the purpose of debugging, just abort.
999 llvm_unreachable("FastISel didn't select the entire block");
1005 // Run SelectionDAG instruction selection on the remainder of the block
1006 // not handled by FastISel. If FastISel is not run, this is the entire
1010 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
1020 SelectionDAGISel::FinishBasicBlock() {
1022 DEBUG(dbgs() << "Target-post-processed machine code:\n");
1025 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1026 << SDB->PHINodesToUpdate.size() << "\n");
1027 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
1028 dbgs() << "Node " << i << " : ("
1029 << SDB->PHINodesToUpdate[i].first
1030 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
1032 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1033 // PHI nodes in successors.
1034 if (SDB->SwitchCases.empty() &&
1035 SDB->JTCases.empty() &&
1036 SDB->BitTestCases.empty()) {
1037 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1038 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1039 assert(PHI->isPHI() &&
1040 "This is not a machine PHI node that we are updating!");
1041 if (!BB->isSuccessor(PHI->getParent()))
1043 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1045 PHI->addOperand(MachineOperand::CreateMBB(BB));
1047 SDB->PHINodesToUpdate.clear();
1051 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1052 // Lower header first, if it wasn't already lowered
1053 if (!SDB->BitTestCases[i].Emitted) {
1054 // Set the current basic block to the mbb we wish to insert the code into
1055 BB = SDB->BitTestCases[i].Parent;
1056 SDB->setCurrentBasicBlock(BB);
1058 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
1059 CurDAG->setRoot(SDB->getRoot());
1060 CodeGenAndEmitDAG();
1064 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1065 // Set the current basic block to the mbb we wish to insert the code into
1066 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
1067 SDB->setCurrentBasicBlock(BB);
1070 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
1071 SDB->BitTestCases[i].Reg,
1072 SDB->BitTestCases[i].Cases[j]);
1074 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
1075 SDB->BitTestCases[i].Reg,
1076 SDB->BitTestCases[i].Cases[j]);
1079 CurDAG->setRoot(SDB->getRoot());
1080 CodeGenAndEmitDAG();
1085 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1086 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1087 MachineBasicBlock *PHIBB = PHI->getParent();
1088 assert(PHI->isPHI() &&
1089 "This is not a machine PHI node that we are updating!");
1090 // This is "default" BB. We have two jumps to it. From "header" BB and
1091 // from last "case" BB.
1092 if (PHIBB == SDB->BitTestCases[i].Default) {
1093 PHI->addOperand(MachineOperand::
1094 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1095 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1096 PHI->addOperand(MachineOperand::
1097 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1098 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1101 // One of "cases" BB.
1102 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1104 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1105 if (cBB->isSuccessor(PHIBB)) {
1106 PHI->addOperand(MachineOperand::
1107 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1108 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1113 SDB->BitTestCases.clear();
1115 // If the JumpTable record is filled in, then we need to emit a jump table.
1116 // Updating the PHI nodes is tricky in this case, since we need to determine
1117 // whether the PHI is a successor of the range check MBB or the jump table MBB
1118 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1119 // Lower header first, if it wasn't already lowered
1120 if (!SDB->JTCases[i].first.Emitted) {
1121 // Set the current basic block to the mbb we wish to insert the code into
1122 BB = SDB->JTCases[i].first.HeaderBB;
1123 SDB->setCurrentBasicBlock(BB);
1125 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1126 CurDAG->setRoot(SDB->getRoot());
1127 CodeGenAndEmitDAG();
1131 // Set the current basic block to the mbb we wish to insert the code into
1132 BB = SDB->JTCases[i].second.MBB;
1133 SDB->setCurrentBasicBlock(BB);
1135 SDB->visitJumpTable(SDB->JTCases[i].second);
1136 CurDAG->setRoot(SDB->getRoot());
1137 CodeGenAndEmitDAG();
1141 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1142 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1143 MachineBasicBlock *PHIBB = PHI->getParent();
1144 assert(PHI->isPHI() &&
1145 "This is not a machine PHI node that we are updating!");
1146 // "default" BB. We can go there only from header BB.
1147 if (PHIBB == SDB->JTCases[i].second.Default) {
1149 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1151 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1153 // JT BB. Just iterate over successors here
1154 if (BB->isSuccessor(PHIBB)) {
1156 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1157 PHI->addOperand(MachineOperand::CreateMBB(BB));
1161 SDB->JTCases.clear();
1163 // If the switch block involved a branch to one of the actual successors, we
1164 // need to update PHI nodes in that block.
1165 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1166 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1167 assert(PHI->isPHI() &&
1168 "This is not a machine PHI node that we are updating!");
1169 if (BB->isSuccessor(PHI->getParent())) {
1170 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1172 PHI->addOperand(MachineOperand::CreateMBB(BB));
1176 // If we generated any switch lowering information, build and codegen any
1177 // additional DAGs necessary.
1178 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1179 // Set the current basic block to the mbb we wish to insert the code into
1180 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1181 SDB->setCurrentBasicBlock(BB);
1184 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1185 CurDAG->setRoot(SDB->getRoot());
1186 CodeGenAndEmitDAG();
1188 // Handle any PHI nodes in successors of this chunk, as if we were coming
1189 // from the original BB before switch expansion. Note that PHI nodes can
1190 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1191 // handle them the right number of times.
1192 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1193 // If new BB's are created during scheduling, the edges may have been
1194 // updated. That is, the edge from ThisBB to BB may have been split and
1195 // BB's predecessor is now another block.
1196 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1197 SDB->EdgeMapping.find(BB);
1198 if (EI != SDB->EdgeMapping.end())
1199 ThisBB = EI->second;
1201 // BB may have been removed from the CFG if a branch was constant folded.
1202 if (ThisBB->isSuccessor(BB)) {
1203 for (MachineBasicBlock::iterator Phi = BB->begin();
1204 Phi != BB->end() && Phi->isPHI();
1206 // This value for this PHI node is recorded in PHINodesToUpdate.
1207 for (unsigned pn = 0; ; ++pn) {
1208 assert(pn != SDB->PHINodesToUpdate.size() &&
1209 "Didn't find PHI entry!");
1210 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1211 Phi->addOperand(MachineOperand::
1212 CreateReg(SDB->PHINodesToUpdate[pn].second,
1214 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1221 // Don't process RHS if same block as LHS.
1222 if (BB == SDB->SwitchCases[i].FalseBB)
1223 SDB->SwitchCases[i].FalseBB = 0;
1225 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1226 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1227 SDB->SwitchCases[i].FalseBB = 0;
1229 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1232 SDB->SwitchCases.clear();
1234 SDB->PHINodesToUpdate.clear();
1238 /// Create the scheduler. If a specific scheduler was specified
1239 /// via the SchedulerRegistry, use it, otherwise select the
1240 /// one preferred by the target.
1242 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1243 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1247 RegisterScheduler::setDefault(Ctor);
1250 return Ctor(this, OptLevel);
1253 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1254 return new ScheduleHazardRecognizer();
1257 //===----------------------------------------------------------------------===//
1258 // Helper functions used by the generated instruction selector.
1259 //===----------------------------------------------------------------------===//
1260 // Calls to these methods are generated by tblgen.
1262 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1263 /// the dag combiner simplified the 255, we still want to match. RHS is the
1264 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1265 /// specified in the .td file (e.g. 255).
1266 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1267 int64_t DesiredMaskS) const {
1268 const APInt &ActualMask = RHS->getAPIntValue();
1269 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1271 // If the actual mask exactly matches, success!
1272 if (ActualMask == DesiredMask)
1275 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1276 if (ActualMask.intersects(~DesiredMask))
1279 // Otherwise, the DAG Combiner may have proven that the value coming in is
1280 // either already zero or is not demanded. Check for known zero input bits.
1281 APInt NeededMask = DesiredMask & ~ActualMask;
1282 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1285 // TODO: check to see if missing bits are just not demanded.
1287 // Otherwise, this pattern doesn't match.
1291 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1292 /// the dag combiner simplified the 255, we still want to match. RHS is the
1293 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1294 /// specified in the .td file (e.g. 255).
1295 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1296 int64_t DesiredMaskS) const {
1297 const APInt &ActualMask = RHS->getAPIntValue();
1298 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1300 // If the actual mask exactly matches, success!
1301 if (ActualMask == DesiredMask)
1304 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1305 if (ActualMask.intersects(~DesiredMask))
1308 // Otherwise, the DAG Combiner may have proven that the value coming in is
1309 // either already zero or is not demanded. Check for known zero input bits.
1310 APInt NeededMask = DesiredMask & ~ActualMask;
1312 APInt KnownZero, KnownOne;
1313 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1315 // If all the missing bits in the or are already known to be set, match!
1316 if ((NeededMask & KnownOne) == NeededMask)
1319 // TODO: check to see if missing bits are just not demanded.
1321 // Otherwise, this pattern doesn't match.
1326 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1327 /// by tblgen. Others should not call it.
1328 void SelectionDAGISel::
1329 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1330 std::vector<SDValue> InOps;
1331 std::swap(InOps, Ops);
1333 Ops.push_back(InOps[0]); // input chain.
1334 Ops.push_back(InOps[1]); // input asm string.
1336 unsigned i = 2, e = InOps.size();
1337 if (InOps[e-1].getValueType() == MVT::Flag)
1338 --e; // Don't process a flag operand if it is here.
1341 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1342 if ((Flags & 7) != 4 /*MEM*/) {
1343 // Just skip over this operand, copying the operands verbatim.
1344 Ops.insert(Ops.end(), InOps.begin()+i,
1345 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1346 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1348 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1349 "Memory operand with multiple values?");
1350 // Otherwise, this is a memory operand. Ask the target to select it.
1351 std::vector<SDValue> SelOps;
1352 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1353 llvm_report_error("Could not match memory address. Inline asm"
1357 // Add this to the output node.
1358 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1360 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1365 // Add the flag input back if present.
1366 if (e != InOps.size())
1367 Ops.push_back(InOps.back());
1370 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1373 static SDNode *findFlagUse(SDNode *N) {
1374 unsigned FlagResNo = N->getNumValues()-1;
1375 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1376 SDUse &Use = I.getUse();
1377 if (Use.getResNo() == FlagResNo)
1378 return Use.getUser();
1383 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1384 /// This function recursively traverses up the operand chain, ignoring
1386 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1387 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1388 bool IgnoreChains) {
1389 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1390 // greater than all of its (recursive) operands. If we scan to a point where
1391 // 'use' is smaller than the node we're scanning for, then we know we will
1394 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1395 // happen because we scan down to newly selected nodes in the case of flag
1397 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1400 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1401 // won't fail if we scan it again.
1402 if (!Visited.insert(Use))
1405 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1406 // Ignore chain uses, they are validated by HandleMergeInputChains.
1407 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1410 SDNode *N = Use->getOperand(i).getNode();
1412 if (Use == ImmedUse || Use == Root)
1413 continue; // We are not looking for immediate use.
1418 // Traverse up the operand chain.
1419 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1425 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1426 /// operand node N of U during instruction selection that starts at Root.
1427 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1428 SDNode *Root) const {
1429 if (OptLevel == CodeGenOpt::None) return false;
1430 return N.hasOneUse();
1433 /// IsLegalToFold - Returns true if the specific operand node N of
1434 /// U can be folded during instruction selection that starts at Root.
1435 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1436 bool IgnoreChains) const {
1437 if (OptLevel == CodeGenOpt::None) return false;
1439 // If Root use can somehow reach N through a path that that doesn't contain
1440 // U then folding N would create a cycle. e.g. In the following
1441 // diagram, Root can reach N through X. If N is folded into into Root, then
1442 // X is both a predecessor and a successor of U.
1453 // * indicates nodes to be folded together.
1455 // If Root produces a flag, then it gets (even more) interesting. Since it
1456 // will be "glued" together with its flag use in the scheduler, we need to
1457 // check if it might reach N.
1476 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1477 // (call it Fold), then X is a predecessor of FU and a successor of
1478 // Fold. But since Fold and FU are flagged together, this will create
1479 // a cycle in the scheduling graph.
1481 // If the node has flags, walk down the graph to the "lowest" node in the
1483 EVT VT = Root->getValueType(Root->getNumValues()-1);
1484 while (VT == MVT::Flag) {
1485 SDNode *FU = findFlagUse(Root);
1489 VT = Root->getValueType(Root->getNumValues()-1);
1491 // If our query node has a flag result with a use, we've walked up it. If
1492 // the user (which has already been selected) has a chain or indirectly uses
1493 // the chain, our WalkChainUsers predicate will not consider it. Because of
1494 // this, we cannot ignore chains in this predicate.
1495 IgnoreChains = false;
1499 SmallPtrSet<SDNode*, 16> Visited;
1500 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1503 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1504 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1505 SelectInlineAsmMemoryOperands(Ops);
1507 std::vector<EVT> VTs;
1508 VTs.push_back(MVT::Other);
1509 VTs.push_back(MVT::Flag);
1510 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1511 VTs, &Ops[0], Ops.size());
1513 return New.getNode();
1516 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1517 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1520 SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) {
1521 SDValue Chain = N->getOperand(0);
1522 unsigned C = cast<LabelSDNode>(N)->getLabelID();
1523 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);
1524 return CurDAG->SelectNodeTo(N, TargetOpcode::EH_LABEL,
1525 MVT::Other, Tmp, Chain);
1528 /// GetVBR - decode a vbr encoding whose top bit is set.
1529 ALWAYS_INLINE static uint64_t
1530 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1531 assert(Val >= 128 && "Not a VBR");
1532 Val &= 127; // Remove first vbr bit.
1537 NextBits = MatcherTable[Idx++];
1538 Val |= (NextBits&127) << Shift;
1540 } while (NextBits & 128);
1546 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1547 /// interior flag and chain results to use the new flag and chain results.
1548 void SelectionDAGISel::
1549 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1550 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1552 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1553 bool isMorphNodeTo) {
1554 SmallVector<SDNode*, 4> NowDeadNodes;
1556 ISelUpdater ISU(ISelPosition);
1558 // Now that all the normal results are replaced, we replace the chain and
1559 // flag results if present.
1560 if (!ChainNodesMatched.empty()) {
1561 assert(InputChain.getNode() != 0 &&
1562 "Matched input chains but didn't produce a chain");
1563 // Loop over all of the nodes we matched that produced a chain result.
1564 // Replace all the chain results with the final chain we ended up with.
1565 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1566 SDNode *ChainNode = ChainNodesMatched[i];
1568 // If this node was already deleted, don't look at it.
1569 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1572 // Don't replace the results of the root node if we're doing a
1574 if (ChainNode == NodeToMatch && isMorphNodeTo)
1577 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1578 if (ChainVal.getValueType() == MVT::Flag)
1579 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1580 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1581 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1583 // If the node became dead, delete it.
1584 if (ChainNode->use_empty())
1585 NowDeadNodes.push_back(ChainNode);
1589 // If the result produces a flag, update any flag results in the matched
1590 // pattern with the flag result.
1591 if (InputFlag.getNode() != 0) {
1592 // Handle any interior nodes explicitly marked.
1593 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1594 SDNode *FRN = FlagResultNodesMatched[i];
1596 // If this node was already deleted, don't look at it.
1597 if (FRN->getOpcode() == ISD::DELETED_NODE)
1600 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1601 "Doesn't have a flag result");
1602 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1605 // If the node became dead, delete it.
1606 if (FRN->use_empty())
1607 NowDeadNodes.push_back(FRN);
1611 if (!NowDeadNodes.empty())
1612 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1614 DEBUG(errs() << "ISEL: Match complete!\n");
1620 CR_LeadsToInteriorNode
1623 /// WalkChainUsers - Walk down the users of the specified chained node that is
1624 /// part of the pattern we're matching, looking at all of the users we find.
1625 /// This determines whether something is an interior node, whether we have a
1626 /// non-pattern node in between two pattern nodes (which prevent folding because
1627 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1628 /// between pattern nodes (in which case the TF becomes part of the pattern).
1630 /// The walk we do here is guaranteed to be small because we quickly get down to
1631 /// already selected nodes "below" us.
1633 WalkChainUsers(SDNode *ChainedNode,
1634 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1635 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1636 ChainResult Result = CR_Simple;
1638 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1639 E = ChainedNode->use_end(); UI != E; ++UI) {
1640 // Make sure the use is of the chain, not some other value we produce.
1641 if (UI.getUse().getValueType() != MVT::Other) continue;
1645 // If we see an already-selected machine node, then we've gone beyond the
1646 // pattern that we're selecting down into the already selected chunk of the
1648 if (User->isMachineOpcode() ||
1649 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1652 if (User->getOpcode() == ISD::CopyToReg ||
1653 User->getOpcode() == ISD::CopyFromReg ||
1654 User->getOpcode() == ISD::INLINEASM) {
1655 // If their node ID got reset to -1 then they've already been selected.
1656 // Treat them like a MachineOpcode.
1657 if (User->getNodeId() == -1)
1661 // If we have a TokenFactor, we handle it specially.
1662 if (User->getOpcode() != ISD::TokenFactor) {
1663 // If the node isn't a token factor and isn't part of our pattern, then it
1664 // must be a random chained node in between two nodes we're selecting.
1665 // This happens when we have something like:
1670 // Because we structurally match the load/store as a read/modify/write,
1671 // but the call is chained between them. We cannot fold in this case
1672 // because it would induce a cycle in the graph.
1673 if (!std::count(ChainedNodesInPattern.begin(),
1674 ChainedNodesInPattern.end(), User))
1675 return CR_InducesCycle;
1677 // Otherwise we found a node that is part of our pattern. For example in:
1681 // This would happen when we're scanning down from the load and see the
1682 // store as a user. Record that there is a use of ChainedNode that is
1683 // part of the pattern and keep scanning uses.
1684 Result = CR_LeadsToInteriorNode;
1685 InteriorChainedNodes.push_back(User);
1689 // If we found a TokenFactor, there are two cases to consider: first if the
1690 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1691 // uses of the TF are in our pattern) we just want to ignore it. Second,
1692 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1698 // | \ DAG's like cheese
1701 // [TokenFactor] [Op]
1708 // In this case, the TokenFactor becomes part of our match and we rewrite it
1709 // as a new TokenFactor.
1711 // To distinguish these two cases, do a recursive walk down the uses.
1712 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1714 // If the uses of the TokenFactor are just already-selected nodes, ignore
1715 // it, it is "below" our pattern.
1717 case CR_InducesCycle:
1718 // If the uses of the TokenFactor lead to nodes that are not part of our
1719 // pattern that are not selected, folding would turn this into a cycle,
1721 return CR_InducesCycle;
1722 case CR_LeadsToInteriorNode:
1723 break; // Otherwise, keep processing.
1726 // Okay, we know we're in the interesting interior case. The TokenFactor
1727 // is now going to be considered part of the pattern so that we rewrite its
1728 // uses (it may have uses that are not part of the pattern) with the
1729 // ultimate chain result of the generated code. We will also add its chain
1730 // inputs as inputs to the ultimate TokenFactor we create.
1731 Result = CR_LeadsToInteriorNode;
1732 ChainedNodesInPattern.push_back(User);
1733 InteriorChainedNodes.push_back(User);
1740 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1741 /// operation for when the pattern matched at least one node with a chains. The
1742 /// input vector contains a list of all of the chained nodes that we match. We
1743 /// must determine if this is a valid thing to cover (i.e. matching it won't
1744 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1745 /// be used as the input node chain for the generated nodes.
1747 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1748 SelectionDAG *CurDAG) {
1749 // Walk all of the chained nodes we've matched, recursively scanning down the
1750 // users of the chain result. This adds any TokenFactor nodes that are caught
1751 // in between chained nodes to the chained and interior nodes list.
1752 SmallVector<SDNode*, 3> InteriorChainedNodes;
1753 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1754 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1755 InteriorChainedNodes) == CR_InducesCycle)
1756 return SDValue(); // Would induce a cycle.
1759 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1760 // that we are interested in. Form our input TokenFactor node.
1761 SmallVector<SDValue, 3> InputChains;
1762 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1763 // Add the input chain of this node to the InputChains list (which will be
1764 // the operands of the generated TokenFactor) if it's not an interior node.
1765 SDNode *N = ChainNodesMatched[i];
1766 if (N->getOpcode() != ISD::TokenFactor) {
1767 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1770 // Otherwise, add the input chain.
1771 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1772 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1773 InputChains.push_back(InChain);
1777 // If we have a token factor, we want to add all inputs of the token factor
1778 // that are not part of the pattern we're matching.
1779 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1780 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1781 N->getOperand(op).getNode()))
1782 InputChains.push_back(N->getOperand(op));
1787 if (InputChains.size() == 1)
1788 return InputChains[0];
1789 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1790 MVT::Other, &InputChains[0], InputChains.size());
1793 /// MorphNode - Handle morphing a node in place for the selector.
1794 SDNode *SelectionDAGISel::
1795 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1796 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1797 // It is possible we're using MorphNodeTo to replace a node with no
1798 // normal results with one that has a normal result (or we could be
1799 // adding a chain) and the input could have flags and chains as well.
1800 // In this case we need to shifting the operands down.
1801 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1802 // than the old isel though. We should sink this into MorphNodeTo.
1803 int OldFlagResultNo = -1, OldChainResultNo = -1;
1805 unsigned NTMNumResults = Node->getNumValues();
1806 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1807 OldFlagResultNo = NTMNumResults-1;
1808 if (NTMNumResults != 1 &&
1809 Node->getValueType(NTMNumResults-2) == MVT::Other)
1810 OldChainResultNo = NTMNumResults-2;
1811 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1812 OldChainResultNo = NTMNumResults-1;
1814 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1815 // that this deletes operands of the old node that become dead.
1816 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1818 // MorphNodeTo can operate in two ways: if an existing node with the
1819 // specified operands exists, it can just return it. Otherwise, it
1820 // updates the node in place to have the requested operands.
1822 // If we updated the node in place, reset the node ID. To the isel,
1823 // this should be just like a newly allocated machine node.
1827 unsigned ResNumResults = Res->getNumValues();
1828 // Move the flag if needed.
1829 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1830 (unsigned)OldFlagResultNo != ResNumResults-1)
1831 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1832 SDValue(Res, ResNumResults-1));
1834 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1837 // Move the chain reference if needed.
1838 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1839 (unsigned)OldChainResultNo != ResNumResults-1)
1840 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1841 SDValue(Res, ResNumResults-1));
1843 // Otherwise, no replacement happened because the node already exists. Replace
1844 // Uses of the old node with the new one.
1846 CurDAG->ReplaceAllUsesWith(Node, Res);
1851 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1852 ALWAYS_INLINE static bool
1853 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1854 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1855 // Accept if it is exactly the same as a previously recorded node.
1856 unsigned RecNo = MatcherTable[MatcherIndex++];
1857 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1858 return N == RecordedNodes[RecNo];
1861 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1862 ALWAYS_INLINE static bool
1863 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1864 SelectionDAGISel &SDISel) {
1865 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1868 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1869 ALWAYS_INLINE static bool
1870 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1871 SelectionDAGISel &SDISel, SDNode *N) {
1872 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1875 ALWAYS_INLINE static bool
1876 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1878 return N->getOpcode() == MatcherTable[MatcherIndex++];
1881 ALWAYS_INLINE static bool
1882 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1883 SDValue N, const TargetLowering &TLI) {
1884 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1885 if (N.getValueType() == VT) return true;
1887 // Handle the case when VT is iPTR.
1888 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1891 ALWAYS_INLINE static bool
1892 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1893 SDValue N, const TargetLowering &TLI,
1895 if (ChildNo >= N.getNumOperands())
1896 return false; // Match fails if out of range child #.
1897 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1901 ALWAYS_INLINE static bool
1902 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1904 return cast<CondCodeSDNode>(N)->get() ==
1905 (ISD::CondCode)MatcherTable[MatcherIndex++];
1908 ALWAYS_INLINE static bool
1909 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1910 SDValue N, const TargetLowering &TLI) {
1911 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1912 if (cast<VTSDNode>(N)->getVT() == VT)
1915 // Handle the case when VT is iPTR.
1916 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1919 ALWAYS_INLINE static bool
1920 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1922 int64_t Val = MatcherTable[MatcherIndex++];
1924 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1926 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1927 return C != 0 && C->getSExtValue() == Val;
1930 ALWAYS_INLINE static bool
1931 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1932 SDValue N, SelectionDAGISel &SDISel) {
1933 int64_t Val = MatcherTable[MatcherIndex++];
1935 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1937 if (N->getOpcode() != ISD::AND) return false;
1939 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1940 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1943 ALWAYS_INLINE static bool
1944 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1945 SDValue N, SelectionDAGISel &SDISel) {
1946 int64_t Val = MatcherTable[MatcherIndex++];
1948 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1950 if (N->getOpcode() != ISD::OR) return false;
1952 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1953 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1956 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1957 /// scope, evaluate the current node. If the current predicate is known to
1958 /// fail, set Result=true and return anything. If the current predicate is
1959 /// known to pass, set Result=false and return the MatcherIndex to continue
1960 /// with. If the current predicate is unknown, set Result=false and return the
1961 /// MatcherIndex to continue with.
1962 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1963 unsigned Index, SDValue N,
1964 bool &Result, SelectionDAGISel &SDISel,
1965 SmallVectorImpl<SDValue> &RecordedNodes){
1966 switch (Table[Index++]) {
1969 return Index-1; // Could not evaluate this predicate.
1970 case SelectionDAGISel::OPC_CheckSame:
1971 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1973 case SelectionDAGISel::OPC_CheckPatternPredicate:
1974 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1976 case SelectionDAGISel::OPC_CheckPredicate:
1977 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1979 case SelectionDAGISel::OPC_CheckOpcode:
1980 Result = !::CheckOpcode(Table, Index, N.getNode());
1982 case SelectionDAGISel::OPC_CheckType:
1983 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1985 case SelectionDAGISel::OPC_CheckChild0Type:
1986 case SelectionDAGISel::OPC_CheckChild1Type:
1987 case SelectionDAGISel::OPC_CheckChild2Type:
1988 case SelectionDAGISel::OPC_CheckChild3Type:
1989 case SelectionDAGISel::OPC_CheckChild4Type:
1990 case SelectionDAGISel::OPC_CheckChild5Type:
1991 case SelectionDAGISel::OPC_CheckChild6Type:
1992 case SelectionDAGISel::OPC_CheckChild7Type:
1993 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1994 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1996 case SelectionDAGISel::OPC_CheckCondCode:
1997 Result = !::CheckCondCode(Table, Index, N);
1999 case SelectionDAGISel::OPC_CheckValueType:
2000 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2002 case SelectionDAGISel::OPC_CheckInteger:
2003 Result = !::CheckInteger(Table, Index, N);
2005 case SelectionDAGISel::OPC_CheckAndImm:
2006 Result = !::CheckAndImm(Table, Index, N, SDISel);
2008 case SelectionDAGISel::OPC_CheckOrImm:
2009 Result = !::CheckOrImm(Table, Index, N, SDISel);
2016 /// FailIndex - If this match fails, this is the index to continue with.
2019 /// NodeStack - The node stack when the scope was formed.
2020 SmallVector<SDValue, 4> NodeStack;
2022 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2023 unsigned NumRecordedNodes;
2025 /// NumMatchedMemRefs - The number of matched memref entries.
2026 unsigned NumMatchedMemRefs;
2028 /// InputChain/InputFlag - The current chain/flag
2029 SDValue InputChain, InputFlag;
2031 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2032 bool HasChainNodesMatched, HasFlagResultNodesMatched;
2035 SDNode *SelectionDAGISel::
2036 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2037 unsigned TableSize) {
2038 // FIXME: Should these even be selected? Handle these cases in the caller?
2039 switch (NodeToMatch->getOpcode()) {
2042 case ISD::EntryToken: // These nodes remain the same.
2043 case ISD::BasicBlock:
2045 case ISD::HANDLENODE:
2046 case ISD::TargetConstant:
2047 case ISD::TargetConstantFP:
2048 case ISD::TargetConstantPool:
2049 case ISD::TargetFrameIndex:
2050 case ISD::TargetExternalSymbol:
2051 case ISD::TargetBlockAddress:
2052 case ISD::TargetJumpTable:
2053 case ISD::TargetGlobalTLSAddress:
2054 case ISD::TargetGlobalAddress:
2055 case ISD::TokenFactor:
2056 case ISD::CopyFromReg:
2057 case ISD::CopyToReg:
2058 NodeToMatch->setNodeId(-1); // Mark selected.
2060 case ISD::AssertSext:
2061 case ISD::AssertZext:
2062 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2063 NodeToMatch->getOperand(0));
2065 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2066 case ISD::EH_LABEL: return Select_EH_LABEL(NodeToMatch);
2067 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2070 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2072 // Set up the node stack with NodeToMatch as the only node on the stack.
2073 SmallVector<SDValue, 8> NodeStack;
2074 SDValue N = SDValue(NodeToMatch, 0);
2075 NodeStack.push_back(N);
2077 // MatchScopes - Scopes used when matching, if a match failure happens, this
2078 // indicates where to continue checking.
2079 SmallVector<MatchScope, 8> MatchScopes;
2081 // RecordedNodes - This is the set of nodes that have been recorded by the
2083 SmallVector<SDValue, 8> RecordedNodes;
2085 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2087 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2089 // These are the current input chain and flag for use when generating nodes.
2090 // Various Emit operations change these. For example, emitting a copytoreg
2091 // uses and updates these.
2092 SDValue InputChain, InputFlag;
2094 // ChainNodesMatched - If a pattern matches nodes that have input/output
2095 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2096 // which ones they are. The result is captured into this list so that we can
2097 // update the chain results when the pattern is complete.
2098 SmallVector<SDNode*, 3> ChainNodesMatched;
2099 SmallVector<SDNode*, 3> FlagResultNodesMatched;
2101 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2102 NodeToMatch->dump(CurDAG);
2105 // Determine where to start the interpreter. Normally we start at opcode #0,
2106 // but if the state machine starts with an OPC_SwitchOpcode, then we
2107 // accelerate the first lookup (which is guaranteed to be hot) with the
2108 // OpcodeOffset table.
2109 unsigned MatcherIndex = 0;
2111 if (!OpcodeOffset.empty()) {
2112 // Already computed the OpcodeOffset table, just index into it.
2113 if (N.getOpcode() < OpcodeOffset.size())
2114 MatcherIndex = OpcodeOffset[N.getOpcode()];
2115 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2117 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2118 // Otherwise, the table isn't computed, but the state machine does start
2119 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2120 // is the first time we're selecting an instruction.
2123 // Get the size of this case.
2124 unsigned CaseSize = MatcherTable[Idx++];
2126 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2127 if (CaseSize == 0) break;
2129 // Get the opcode, add the index to the table.
2130 unsigned Opc = MatcherTable[Idx++];
2131 if (Opc >= OpcodeOffset.size())
2132 OpcodeOffset.resize((Opc+1)*2);
2133 OpcodeOffset[Opc] = Idx;
2137 // Okay, do the lookup for the first opcode.
2138 if (N.getOpcode() < OpcodeOffset.size())
2139 MatcherIndex = OpcodeOffset[N.getOpcode()];
2143 assert(MatcherIndex < TableSize && "Invalid index");
2145 unsigned CurrentOpcodeIndex = MatcherIndex;
2147 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2150 // Okay, the semantics of this operation are that we should push a scope
2151 // then evaluate the first child. However, pushing a scope only to have
2152 // the first check fail (which then pops it) is inefficient. If we can
2153 // determine immediately that the first check (or first several) will
2154 // immediately fail, don't even bother pushing a scope for them.
2158 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2159 if (NumToSkip & 128)
2160 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2161 // Found the end of the scope with no match.
2162 if (NumToSkip == 0) {
2167 FailIndex = MatcherIndex+NumToSkip;
2169 // If we can't evaluate this predicate without pushing a scope (e.g. if
2170 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2171 // push the scope and evaluate the full predicate chain.
2173 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2174 Result, *this, RecordedNodes);
2178 DEBUG(errs() << " Skipped scope entry at index " << MatcherIndex
2179 << " continuing at " << FailIndex << "\n");
2182 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2183 // move to the next case.
2184 MatcherIndex = FailIndex;
2187 // If the whole scope failed to match, bail.
2188 if (FailIndex == 0) break;
2190 // Push a MatchScope which indicates where to go if the first child fails
2192 MatchScope NewEntry;
2193 NewEntry.FailIndex = FailIndex;
2194 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2195 NewEntry.NumRecordedNodes = RecordedNodes.size();
2196 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2197 NewEntry.InputChain = InputChain;
2198 NewEntry.InputFlag = InputFlag;
2199 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2200 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2201 MatchScopes.push_back(NewEntry);
2204 case OPC_RecordNode:
2205 // Remember this node, it may end up being an operand in the pattern.
2206 RecordedNodes.push_back(N);
2209 case OPC_RecordChild0: case OPC_RecordChild1:
2210 case OPC_RecordChild2: case OPC_RecordChild3:
2211 case OPC_RecordChild4: case OPC_RecordChild5:
2212 case OPC_RecordChild6: case OPC_RecordChild7: {
2213 unsigned ChildNo = Opcode-OPC_RecordChild0;
2214 if (ChildNo >= N.getNumOperands())
2215 break; // Match fails if out of range child #.
2217 RecordedNodes.push_back(N->getOperand(ChildNo));
2220 case OPC_RecordMemRef:
2221 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2224 case OPC_CaptureFlagInput:
2225 // If the current node has an input flag, capture it in InputFlag.
2226 if (N->getNumOperands() != 0 &&
2227 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2228 InputFlag = N->getOperand(N->getNumOperands()-1);
2231 case OPC_MoveChild: {
2232 unsigned ChildNo = MatcherTable[MatcherIndex++];
2233 if (ChildNo >= N.getNumOperands())
2234 break; // Match fails if out of range child #.
2235 N = N.getOperand(ChildNo);
2236 NodeStack.push_back(N);
2240 case OPC_MoveParent:
2241 // Pop the current node off the NodeStack.
2242 NodeStack.pop_back();
2243 assert(!NodeStack.empty() && "Node stack imbalance!");
2244 N = NodeStack.back();
2248 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2250 case OPC_CheckPatternPredicate:
2251 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2253 case OPC_CheckPredicate:
2254 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2258 case OPC_CheckComplexPat: {
2259 unsigned CPNum = MatcherTable[MatcherIndex++];
2260 unsigned RecNo = MatcherTable[MatcherIndex++];
2261 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2262 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2267 case OPC_CheckOpcode:
2268 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2272 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2275 case OPC_SwitchOpcode: {
2276 unsigned CurNodeOpcode = N.getOpcode();
2277 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2280 // Get the size of this case.
2281 CaseSize = MatcherTable[MatcherIndex++];
2283 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2284 if (CaseSize == 0) break;
2286 // If the opcode matches, then we will execute this case.
2287 if (CurNodeOpcode == MatcherTable[MatcherIndex++])
2290 // Otherwise, skip over this case.
2291 MatcherIndex += CaseSize;
2294 // If no cases matched, bail out.
2295 if (CaseSize == 0) break;
2297 // Otherwise, execute the case we found.
2298 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2299 << " to " << MatcherIndex << "\n");
2303 case OPC_SwitchType: {
2304 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2305 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2308 // Get the size of this case.
2309 CaseSize = MatcherTable[MatcherIndex++];
2311 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2312 if (CaseSize == 0) break;
2314 MVT::SimpleValueType CaseVT =
2315 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2316 if (CaseVT == MVT::iPTR)
2317 CaseVT = TLI.getPointerTy().SimpleTy;
2319 // If the VT matches, then we will execute this case.
2320 if (CurNodeVT == CaseVT)
2323 // Otherwise, skip over this case.
2324 MatcherIndex += CaseSize;
2327 // If no cases matched, bail out.
2328 if (CaseSize == 0) break;
2330 // Otherwise, execute the case we found.
2331 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2332 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2335 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2336 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2337 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2338 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2339 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2340 Opcode-OPC_CheckChild0Type))
2343 case OPC_CheckCondCode:
2344 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2346 case OPC_CheckValueType:
2347 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2349 case OPC_CheckInteger:
2350 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2352 case OPC_CheckAndImm:
2353 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2355 case OPC_CheckOrImm:
2356 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2359 case OPC_CheckFoldableChainNode: {
2360 assert(NodeStack.size() != 1 && "No parent node");
2361 // Verify that all intermediate nodes between the root and this one have
2363 bool HasMultipleUses = false;
2364 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2365 if (!NodeStack[i].hasOneUse()) {
2366 HasMultipleUses = true;
2369 if (HasMultipleUses) break;
2371 // Check to see that the target thinks this is profitable to fold and that
2372 // we can fold it without inducing cycles in the graph.
2373 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2375 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2376 NodeToMatch, true/*We validate our own chains*/))
2381 case OPC_EmitInteger: {
2382 MVT::SimpleValueType VT =
2383 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2384 int64_t Val = MatcherTable[MatcherIndex++];
2386 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2387 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2390 case OPC_EmitRegister: {
2391 MVT::SimpleValueType VT =
2392 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2393 unsigned RegNo = MatcherTable[MatcherIndex++];
2394 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2398 case OPC_EmitConvertToTarget: {
2399 // Convert from IMM/FPIMM to target version.
2400 unsigned RecNo = MatcherTable[MatcherIndex++];
2401 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2402 SDValue Imm = RecordedNodes[RecNo];
2404 if (Imm->getOpcode() == ISD::Constant) {
2405 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2406 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2407 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2408 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2409 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2412 RecordedNodes.push_back(Imm);
2416 case OPC_EmitMergeInputChains: {
2417 assert(InputChain.getNode() == 0 &&
2418 "EmitMergeInputChains should be the first chain producing node");
2419 // This node gets a list of nodes we matched in the input that have
2420 // chains. We want to token factor all of the input chains to these nodes
2421 // together. However, if any of the input chains is actually one of the
2422 // nodes matched in this pattern, then we have an intra-match reference.
2423 // Ignore these because the newly token factored chain should not refer to
2425 unsigned NumChains = MatcherTable[MatcherIndex++];
2426 assert(NumChains != 0 && "Can't TF zero chains");
2428 assert(ChainNodesMatched.empty() &&
2429 "Should only have one EmitMergeInputChains per match");
2431 // Read all of the chained nodes.
2432 for (unsigned i = 0; i != NumChains; ++i) {
2433 unsigned RecNo = MatcherTable[MatcherIndex++];
2434 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2435 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2437 // FIXME: What if other value results of the node have uses not matched
2439 if (ChainNodesMatched.back() != NodeToMatch &&
2440 !RecordedNodes[RecNo].hasOneUse()) {
2441 ChainNodesMatched.clear();
2446 // If the inner loop broke out, the match fails.
2447 if (ChainNodesMatched.empty())
2450 // Merge the input chains if they are not intra-pattern references.
2451 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2453 if (InputChain.getNode() == 0)
2454 break; // Failed to merge.
2459 case OPC_EmitCopyToReg: {
2460 unsigned RecNo = MatcherTable[MatcherIndex++];
2461 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2462 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2464 if (InputChain.getNode() == 0)
2465 InputChain = CurDAG->getEntryNode();
2467 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2468 DestPhysReg, RecordedNodes[RecNo],
2471 InputFlag = InputChain.getValue(1);
2475 case OPC_EmitNodeXForm: {
2476 unsigned XFormNo = MatcherTable[MatcherIndex++];
2477 unsigned RecNo = MatcherTable[MatcherIndex++];
2478 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2479 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2484 case OPC_MorphNodeTo: {
2485 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2486 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2487 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2488 // Get the result VT list.
2489 unsigned NumVTs = MatcherTable[MatcherIndex++];
2490 SmallVector<EVT, 4> VTs;
2491 for (unsigned i = 0; i != NumVTs; ++i) {
2492 MVT::SimpleValueType VT =
2493 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2494 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2498 if (EmitNodeInfo & OPFL_Chain)
2499 VTs.push_back(MVT::Other);
2500 if (EmitNodeInfo & OPFL_FlagOutput)
2501 VTs.push_back(MVT::Flag);
2503 // This is hot code, so optimize the two most common cases of 1 and 2
2506 if (VTs.size() == 1)
2507 VTList = CurDAG->getVTList(VTs[0]);
2508 else if (VTs.size() == 2)
2509 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2511 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2513 // Get the operand list.
2514 unsigned NumOps = MatcherTable[MatcherIndex++];
2515 SmallVector<SDValue, 8> Ops;
2516 for (unsigned i = 0; i != NumOps; ++i) {
2517 unsigned RecNo = MatcherTable[MatcherIndex++];
2519 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2521 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2522 Ops.push_back(RecordedNodes[RecNo]);
2525 // If there are variadic operands to add, handle them now.
2526 if (EmitNodeInfo & OPFL_VariadicInfo) {
2527 // Determine the start index to copy from.
2528 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2529 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2530 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2531 "Invalid variadic node");
2532 // Copy all of the variadic operands, not including a potential flag
2534 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2536 SDValue V = NodeToMatch->getOperand(i);
2537 if (V.getValueType() == MVT::Flag) break;
2542 // If this has chain/flag inputs, add them.
2543 if (EmitNodeInfo & OPFL_Chain)
2544 Ops.push_back(InputChain);
2545 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2546 Ops.push_back(InputFlag);
2550 if (Opcode != OPC_MorphNodeTo) {
2551 // If this is a normal EmitNode command, just create the new node and
2552 // add the results to the RecordedNodes list.
2553 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2554 VTList, Ops.data(), Ops.size());
2556 // Add all the non-flag/non-chain results to the RecordedNodes list.
2557 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2558 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2559 RecordedNodes.push_back(SDValue(Res, i));
2563 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2567 // If the node had chain/flag results, update our notion of the current
2569 if (EmitNodeInfo & OPFL_FlagOutput) {
2570 InputFlag = SDValue(Res, VTs.size()-1);
2571 if (EmitNodeInfo & OPFL_Chain)
2572 InputChain = SDValue(Res, VTs.size()-2);
2573 } else if (EmitNodeInfo & OPFL_Chain)
2574 InputChain = SDValue(Res, VTs.size()-1);
2576 // If the OPFL_MemRefs flag is set on this node, slap all of the
2577 // accumulated memrefs onto it.
2579 // FIXME: This is vastly incorrect for patterns with multiple outputs
2580 // instructions that access memory and for ComplexPatterns that match
2582 if (EmitNodeInfo & OPFL_MemRefs) {
2583 MachineSDNode::mmo_iterator MemRefs =
2584 MF->allocateMemRefsArray(MatchedMemRefs.size());
2585 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2586 cast<MachineSDNode>(Res)
2587 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2591 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2592 << " node: "; Res->dump(CurDAG); errs() << "\n");
2594 // If this was a MorphNodeTo then we're completely done!
2595 if (Opcode == OPC_MorphNodeTo) {
2596 // Update chain and flag uses.
2597 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2598 InputFlag, FlagResultNodesMatched, true);
2605 case OPC_MarkFlagResults: {
2606 unsigned NumNodes = MatcherTable[MatcherIndex++];
2608 // Read and remember all the flag-result nodes.
2609 for (unsigned i = 0; i != NumNodes; ++i) {
2610 unsigned RecNo = MatcherTable[MatcherIndex++];
2612 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2614 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2615 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2620 case OPC_CompleteMatch: {
2621 // The match has been completed, and any new nodes (if any) have been
2622 // created. Patch up references to the matched dag to use the newly
2624 unsigned NumResults = MatcherTable[MatcherIndex++];
2626 for (unsigned i = 0; i != NumResults; ++i) {
2627 unsigned ResSlot = MatcherTable[MatcherIndex++];
2629 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2631 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2632 SDValue Res = RecordedNodes[ResSlot];
2634 // FIXME2: Eliminate this horrible hack by fixing the 'Gen' program
2635 // after (parallel) on input patterns are removed. This would also
2636 // allow us to stop encoding #results in OPC_CompleteMatch's table
2638 if (NodeToMatch->getNumValues() <= i ||
2639 NodeToMatch->getValueType(i) == MVT::Other ||
2640 NodeToMatch->getValueType(i) == MVT::Flag)
2642 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2643 NodeToMatch->getValueType(i) == MVT::iPTR ||
2644 Res.getValueType() == MVT::iPTR ||
2645 NodeToMatch->getValueType(i).getSizeInBits() ==
2646 Res.getValueType().getSizeInBits()) &&
2647 "invalid replacement");
2648 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2651 // If the root node defines a flag, add it to the flag nodes to update
2653 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2654 FlagResultNodesMatched.push_back(NodeToMatch);
2656 // Update chain and flag uses.
2657 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2658 InputFlag, FlagResultNodesMatched, false);
2660 assert(NodeToMatch->use_empty() &&
2661 "Didn't replace all uses of the node?");
2663 // FIXME: We just return here, which interacts correctly with SelectRoot
2664 // above. We should fix this to not return an SDNode* anymore.
2669 // If the code reached this point, then the match failed. See if there is
2670 // another child to try in the current 'Scope', otherwise pop it until we
2671 // find a case to check.
2672 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2674 if (MatchScopes.empty()) {
2675 CannotYetSelect(NodeToMatch);
2679 // Restore the interpreter state back to the point where the scope was
2681 MatchScope &LastScope = MatchScopes.back();
2682 RecordedNodes.resize(LastScope.NumRecordedNodes);
2684 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2685 N = NodeStack.back();
2687 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2688 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2689 MatcherIndex = LastScope.FailIndex;
2691 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2693 InputChain = LastScope.InputChain;
2694 InputFlag = LastScope.InputFlag;
2695 if (!LastScope.HasChainNodesMatched)
2696 ChainNodesMatched.clear();
2697 if (!LastScope.HasFlagResultNodesMatched)
2698 FlagResultNodesMatched.clear();
2700 // Check to see what the offset is at the new MatcherIndex. If it is zero
2701 // we have reached the end of this scope, otherwise we have another child
2702 // in the current scope to try.
2703 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2704 if (NumToSkip & 128)
2705 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2707 // If we have another child in this scope to match, update FailIndex and
2709 if (NumToSkip != 0) {
2710 LastScope.FailIndex = MatcherIndex+NumToSkip;
2714 // End of this scope, pop it and try the next child in the containing
2716 MatchScopes.pop_back();
2723 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2725 raw_string_ostream Msg(msg);
2726 Msg << "Cannot yet select: ";
2728 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2729 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2730 N->getOpcode() != ISD::INTRINSIC_VOID) {
2731 N->printrFull(Msg, CurDAG);
2733 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2735 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2736 if (iid < Intrinsic::num_intrinsics)
2737 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2738 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2739 Msg << "target intrinsic %" << TII->getName(iid);
2741 Msg << "unknown intrinsic #" << iid;
2743 llvm_report_error(Msg.str());
2746 char SelectionDAGISel::ID = 0;