1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/ADT/Statistic.h"
55 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
56 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
59 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
60 cl::desc("Enable verbose messages in the \"fast\" "
61 "instruction selector"));
63 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
64 cl::desc("Enable abort calls when \"fast\" instruction fails"));
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before the post legalize types"
84 " dag combine pass"));
86 ViewISelDAGs("view-isel-dags", cl::Hidden,
87 cl::desc("Pop up a window to show isel dags as they are selected"));
89 ViewSchedDAGs("view-sched-dags", cl::Hidden,
90 cl::desc("Pop up a window to show sched dags as they are processed"));
92 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
93 cl::desc("Pop up a window to show SUnit dags after they are processed"));
95 static const bool ViewDAGCombine1 = false,
96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
97 ViewDAGCombine2 = false,
98 ViewDAGCombineLT = false,
99 ViewISelDAGs = false, ViewSchedDAGs = false,
100 ViewSUnitDAGs = false;
103 //===---------------------------------------------------------------------===//
105 /// RegisterScheduler class - Track the registration of instruction schedulers.
107 //===---------------------------------------------------------------------===//
108 MachinePassRegistry RegisterScheduler::Registry;
110 //===---------------------------------------------------------------------===//
112 /// ISHeuristic command line option for instruction schedulers.
114 //===---------------------------------------------------------------------===//
115 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
116 RegisterPassParser<RegisterScheduler> >
117 ISHeuristic("pre-RA-sched",
118 cl::init(&createDefaultScheduler),
119 cl::desc("Instruction schedulers available (before register"
122 static RegisterScheduler
123 defaultListDAGScheduler("default", "Best scheduler for the target",
124 createDefaultScheduler);
127 //===--------------------------------------------------------------------===//
128 /// createDefaultScheduler - This creates an instruction scheduler appropriate
130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
131 CodeGenOpt::Level OptLevel) {
132 const TargetLowering &TLI = IS->getTargetLowering();
134 if (OptLevel == CodeGenOpt::None)
135 return createSourceListDAGScheduler(IS, OptLevel);
136 if (TLI.getSchedulingPreference() == Sched::Latency)
137 return createTDListDAGScheduler(IS, OptLevel);
138 if (TLI.getSchedulingPreference() == Sched::RegPressure)
139 return createBURRListDAGScheduler(IS, OptLevel);
140 if (TLI.getSchedulingPreference() == Sched::Hybrid)
141 return createHybridListDAGScheduler(IS, OptLevel);
142 assert(TLI.getSchedulingPreference() == Sched::ILP &&
143 "Unknown sched type!");
144 return createILPListDAGScheduler(IS, OptLevel);
148 // EmitInstrWithCustomInserter - This method should be implemented by targets
149 // that mark instructions with the 'usesCustomInserter' flag. These
150 // instructions are special in various ways, which require special support to
151 // insert. The specified MachineInstr is created but not inserted into any
152 // basic blocks, and this method is called to expand it into a sequence of
153 // instructions, potentially also creating new basic blocks and control flow.
154 // When new basic blocks are inserted and the edges from MBB to its successors
155 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
158 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
159 MachineBasicBlock *MBB) const {
161 dbgs() << "If a target marks an instruction with "
162 "'usesCustomInserter', it must implement "
163 "TargetLowering::EmitInstrWithCustomInserter!";
169 //===----------------------------------------------------------------------===//
170 // SelectionDAGISel code
171 //===----------------------------------------------------------------------===//
173 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
174 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
175 FuncInfo(new FunctionLoweringInfo(TLI)),
176 CurDAG(new SelectionDAG(tm)),
177 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
181 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
182 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
185 SelectionDAGISel::~SelectionDAGISel() {
191 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
192 AU.addRequired<AliasAnalysis>();
193 AU.addPreserved<AliasAnalysis>();
194 AU.addRequired<GCModuleInfo>();
195 AU.addPreserved<GCModuleInfo>();
196 MachineFunctionPass::getAnalysisUsage(AU);
199 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
200 /// other function that gcc recognizes as "returning twice". This is used to
201 /// limit code-gen optimizations on the machine function.
203 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
204 static bool FunctionCallsSetJmp(const Function *F) {
205 const Module *M = F->getParent();
206 static const char *ReturnsTwiceFns[] = {
215 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
217 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
218 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
219 if (!Callee->use_empty())
220 for (Value::const_use_iterator
221 I = Callee->use_begin(), E = Callee->use_end();
223 if (const CallInst *CI = dyn_cast<CallInst>(*I))
224 if (CI->getParent()->getParent() == F)
229 #undef NUM_RETURNS_TWICE_FNS
232 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
233 // Do some sanity-checking on the command-line options.
234 assert((!EnableFastISelVerbose || EnableFastISel) &&
235 "-fast-isel-verbose requires -fast-isel");
236 assert((!EnableFastISelAbort || EnableFastISel) &&
237 "-fast-isel-abort requires -fast-isel");
239 const Function &Fn = *mf.getFunction();
240 const TargetInstrInfo &TII = *TM.getInstrInfo();
241 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
244 RegInfo = &MF->getRegInfo();
245 AA = &getAnalysis<AliasAnalysis>();
246 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
248 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
251 FuncInfo->set(Fn, *MF);
254 SelectAllBasicBlocks(Fn);
256 // If the first basic block in the function has live ins that need to be
257 // copied into vregs, emit the copies into the top of the block before
258 // emitting the code for the block.
259 MachineBasicBlock *EntryMBB = MF->begin();
260 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
262 DenseMap<unsigned, unsigned> LiveInMap;
263 if (!FuncInfo->ArgDbgValues.empty())
264 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
265 E = RegInfo->livein_end(); LI != E; ++LI)
267 LiveInMap.insert(std::make_pair(LI->first, LI->second));
269 // Insert DBG_VALUE instructions for function arguments to the entry block.
270 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
271 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
272 unsigned Reg = MI->getOperand(0).getReg();
273 if (TargetRegisterInfo::isPhysicalRegister(Reg))
274 EntryMBB->insert(EntryMBB->begin(), MI);
276 MachineInstr *Def = RegInfo->getVRegDef(Reg);
277 MachineBasicBlock::iterator InsertPos = Def;
278 // FIXME: VR def may not be in entry block.
279 Def->getParent()->insert(llvm::next(InsertPos), MI);
282 // If Reg is live-in then update debug info to track its copy in a vreg.
283 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
284 if (LDI != LiveInMap.end()) {
285 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
286 MachineBasicBlock::iterator InsertPos = Def;
287 const MDNode *Variable =
288 MI->getOperand(MI->getNumOperands()-1).getMetadata();
289 unsigned Offset = MI->getOperand(1).getImm();
290 // Def is never a terminator here, so it is ok to increment InsertPos.
291 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
292 TII.get(TargetOpcode::DBG_VALUE))
293 .addReg(LDI->second, RegState::Debug)
294 .addImm(Offset).addMetadata(Variable);
296 // If this vreg is directly copied into an exported register then
297 // that COPY instructions also need DBG_VALUE, if it is the only
298 // user of LDI->second.
299 MachineInstr *CopyUseMI = NULL;
300 for (MachineRegisterInfo::use_iterator
301 UI = RegInfo->use_begin(LDI->second);
302 MachineInstr *UseMI = UI.skipInstruction();) {
303 if (UseMI->isDebugValue()) continue;
304 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
305 CopyUseMI = UseMI; continue;
307 // Otherwise this is another use or second copy use.
308 CopyUseMI = NULL; break;
311 MachineInstr *NewMI =
312 BuildMI(*MF, CopyUseMI->getDebugLoc(),
313 TII.get(TargetOpcode::DBG_VALUE))
314 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
315 .addImm(Offset).addMetadata(Variable);
316 EntryMBB->insertAfter(CopyUseMI, NewMI);
321 // Determine if there are any calls in this machine function.
322 MachineFrameInfo *MFI = MF->getFrameInfo();
323 if (!MFI->hasCalls()) {
324 for (MachineFunction::const_iterator
325 I = MF->begin(), E = MF->end(); I != E; ++I) {
326 const MachineBasicBlock *MBB = I;
327 for (MachineBasicBlock::const_iterator
328 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
329 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
331 // Operand 1 of an inline asm instruction indicates whether the asm
332 // needs stack or not.
333 if ((II->isInlineAsm() && II->getOperand(1).getImm()) ||
334 (TID.isCall() && !TID.isReturn())) {
335 MFI->setHasCalls(true);
343 // Determine if there is a call to setjmp in the machine function.
344 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
346 // Replace forward-declared registers with the registers containing
347 // the desired value.
348 MachineRegisterInfo &MRI = MF->getRegInfo();
349 for (DenseMap<unsigned, unsigned>::iterator
350 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
352 unsigned From = I->first;
353 unsigned To = I->second;
354 // If To is also scheduled to be replaced, find what its ultimate
357 DenseMap<unsigned, unsigned>::iterator J =
358 FuncInfo->RegFixups.find(To);
363 MRI.replaceRegWith(From, To);
366 // Release function-specific state. SDB and CurDAG are already cleared
374 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
375 BasicBlock::const_iterator End,
377 // Lower all of the non-terminator instructions. If a call is emitted
378 // as a tail call, cease emitting nodes for this block. Terminators
379 // are handled below.
380 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
383 // Make sure the root of the DAG is up-to-date.
384 CurDAG->setRoot(SDB->getControlRoot());
385 HadTailCall = SDB->HasTailCall;
388 // Final step, emit the lowered DAG as machine code.
392 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
393 SmallPtrSet<SDNode*, 128> VisitedNodes;
394 SmallVector<SDNode*, 128> Worklist;
396 Worklist.push_back(CurDAG->getRoot().getNode());
403 SDNode *N = Worklist.pop_back_val();
405 // If we've already seen this node, ignore it.
406 if (!VisitedNodes.insert(N))
409 // Otherwise, add all chain operands to the worklist.
410 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
411 if (N->getOperand(i).getValueType() == MVT::Other)
412 Worklist.push_back(N->getOperand(i).getNode());
414 // If this is a CopyToReg with a vreg dest, process it.
415 if (N->getOpcode() != ISD::CopyToReg)
418 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
419 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
422 // Ignore non-scalar or non-integer values.
423 SDValue Src = N->getOperand(2);
424 EVT SrcVT = Src.getValueType();
425 if (!SrcVT.isInteger() || SrcVT.isVector())
428 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
429 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
430 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
432 // Only install this information if it tells us something.
433 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
434 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
435 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
436 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
437 FunctionLoweringInfo::LiveOutInfo &LOI =
438 FuncInfo->LiveOutRegInfo[DestReg];
439 LOI.NumSignBits = NumSignBits;
440 LOI.KnownOne = KnownOne;
441 LOI.KnownZero = KnownZero;
443 } while (!Worklist.empty());
446 void SelectionDAGISel::CodeGenAndEmitDAG() {
447 std::string GroupName;
448 if (TimePassesIsEnabled)
449 GroupName = "Instruction Selection and Scheduling";
450 std::string BlockName;
451 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
452 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
454 BlockName = MF->getFunction()->getNameStr() + ":" +
455 FuncInfo->MBB->getBasicBlock()->getNameStr();
457 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
459 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
461 // Run the DAG combiner in pre-legalize mode.
463 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
464 CurDAG->Combine(Unrestricted, *AA, OptLevel);
467 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
469 // Second step, hack on the DAG until it only uses operations and types that
470 // the target supports.
471 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
476 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
477 Changed = CurDAG->LegalizeTypes();
480 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
483 if (ViewDAGCombineLT)
484 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
486 // Run the DAG combiner in post-type-legalize mode.
488 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
489 TimePassesIsEnabled);
490 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
493 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
498 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
499 Changed = CurDAG->LegalizeVectors();
504 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
505 CurDAG->LegalizeTypes();
508 if (ViewDAGCombineLT)
509 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
511 // Run the DAG combiner in post-type-legalize mode.
513 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
514 TimePassesIsEnabled);
515 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
518 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
522 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
525 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
526 CurDAG->Legalize(OptLevel);
529 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
531 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
533 // Run the DAG combiner in post-legalize mode.
535 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
536 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
539 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
541 if (OptLevel != CodeGenOpt::None)
542 ComputeLiveOutVRegInfo();
544 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
546 // Third, instruction select all of the operations to machine code, adding the
547 // code to the MachineBasicBlock.
549 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
550 DoInstructionSelection();
553 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
555 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
557 // Schedule machine code.
558 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
560 NamedRegionTimer T("Instruction Scheduling", GroupName,
561 TimePassesIsEnabled);
562 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
565 if (ViewSUnitDAGs) Scheduler->viewGraph();
567 // Emit machine code to BB. This can change 'BB' to the last block being
569 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
571 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
573 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
574 FuncInfo->InsertPt = Scheduler->InsertPos;
577 // If the block was split, make sure we update any references that are used to
578 // update PHI nodes later on.
579 if (FirstMBB != LastMBB)
580 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
582 // Free the scheduler state.
584 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
585 TimePassesIsEnabled);
589 // Free the SelectionDAG state, now that we're finished with it.
593 void SelectionDAGISel::DoInstructionSelection() {
594 DEBUG(errs() << "===== Instruction selection begins:\n");
598 // Select target instructions for the DAG.
600 // Number all nodes with a topological order and set DAGSize.
601 DAGSize = CurDAG->AssignTopologicalOrder();
603 // Create a dummy node (which is not added to allnodes), that adds
604 // a reference to the root node, preventing it from being deleted,
605 // and tracking any changes of the root.
606 HandleSDNode Dummy(CurDAG->getRoot());
607 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
610 // The AllNodes list is now topological-sorted. Visit the
611 // nodes by starting at the end of the list (the root of the
612 // graph) and preceding back toward the beginning (the entry
614 while (ISelPosition != CurDAG->allnodes_begin()) {
615 SDNode *Node = --ISelPosition;
616 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
617 // but there are currently some corner cases that it misses. Also, this
618 // makes it theoretically possible to disable the DAGCombiner.
619 if (Node->use_empty())
622 SDNode *ResNode = Select(Node);
624 // FIXME: This is pretty gross. 'Select' should be changed to not return
625 // anything at all and this code should be nuked with a tactical strike.
627 // If node should not be replaced, continue with the next one.
628 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
632 ReplaceUses(Node, ResNode);
634 // If after the replacement this node is not used any more,
635 // remove this dead node.
636 if (Node->use_empty()) { // Don't delete EntryToken, etc.
637 ISelUpdater ISU(ISelPosition);
638 CurDAG->RemoveDeadNode(Node, &ISU);
642 CurDAG->setRoot(Dummy.getValue());
645 DEBUG(errs() << "===== Instruction selection ends:\n");
647 PostprocessISelDAG();
650 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
651 /// do other setup for EH landing-pad blocks.
652 void SelectionDAGISel::PrepareEHLandingPad() {
653 // Add a label to mark the beginning of the landing pad. Deletion of the
654 // landing pad can thus be detected via the MachineModuleInfo.
655 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
657 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
658 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
661 // Mark exception register as live in.
662 unsigned Reg = TLI.getExceptionAddressRegister();
663 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
665 // Mark exception selector register as live in.
666 Reg = TLI.getExceptionSelectorRegister();
667 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
669 // FIXME: Hack around an exception handling flaw (PR1508): the personality
670 // function and list of typeids logically belong to the invoke (or, if you
671 // like, the basic block containing the invoke), and need to be associated
672 // with it in the dwarf exception handling tables. Currently however the
673 // information is provided by an intrinsic (eh.selector) that can be moved
674 // to unexpected places by the optimizers: if the unwind edge is critical,
675 // then breaking it can result in the intrinsics being in the successor of
676 // the landing pad, not the landing pad itself. This results
677 // in exceptions not being caught because no typeids are associated with
678 // the invoke. This may not be the only way things can go wrong, but it
679 // is the only way we try to work around for the moment.
680 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
681 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
683 if (Br && Br->isUnconditional()) { // Critical edge?
684 BasicBlock::const_iterator I, E;
685 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
686 if (isa<EHSelectorInst>(I))
690 // No catch info found - try to extract some from the successor.
691 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
698 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
700 // Don't try to fold volatile loads. Target has to deal with alignment
702 if (LI->isVolatile()) return false;
704 // Figure out which vreg this is going into.
705 unsigned LoadReg = FastIS->getRegForValue(LI);
706 assert(LoadReg && "Load isn't already assigned a vreg? ");
708 // Check to see what the uses of this vreg are. If it has no uses, or more
709 // than one use (at the machine instr level) then we can't fold it.
710 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
711 if (RI == RegInfo->reg_end())
714 // See if there is exactly one use of the vreg. If there are multiple uses,
715 // then the instruction got lowered to multiple machine instructions or the
716 // use of the loaded value ended up being multiple operands of the result, in
717 // either case, we can't fold this.
718 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
719 if (PostRI != RegInfo->reg_end())
722 assert(RI.getOperand().isUse() &&
723 "The only use of the vreg must be a use, we haven't emitted the def!");
725 // Ask the target to try folding the load.
726 return FastIS->TryToFoldLoad(&*RI, RI.getOperandNo(), LI);
732 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
733 // Initialize the Fast-ISel state, if needed.
734 FastISel *FastIS = 0;
736 FastIS = TLI.createFastISel(*FuncInfo);
738 // Iterate over all basic blocks in the function.
739 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
740 const BasicBlock *LLVMBB = &*I;
741 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
742 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
744 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
745 BasicBlock::const_iterator const End = LLVMBB->end();
746 BasicBlock::const_iterator BI = End;
748 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
750 // Setup an EH landing-pad block.
751 if (FuncInfo->MBB->isLandingPad())
752 PrepareEHLandingPad();
754 // Lower any arguments needed in this block if this is the entry block.
755 if (LLVMBB == &Fn.getEntryBlock())
756 LowerArguments(LLVMBB);
758 // Before doing SelectionDAG ISel, see if FastISel has been requested.
760 FastIS->startNewBlock();
762 // Emit code for any incoming arguments. This must happen before
763 // beginning FastISel on the entry block.
764 if (LLVMBB == &Fn.getEntryBlock()) {
765 CurDAG->setRoot(SDB->getControlRoot());
769 // If we inserted any instructions at the beginning, make a note of
770 // where they are, so we can be sure to emit subsequent instructions
772 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
773 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
775 FastIS->setLastLocalValue(0);
778 // Do FastISel on as many instructions as possible.
779 for (; BI != Begin; --BI) {
780 const Instruction *Inst = llvm::prior(BI);
782 // If we no longer require this instruction, skip it.
783 if (!Inst->mayWriteToMemory() &&
784 !isa<TerminatorInst>(Inst) &&
785 !isa<DbgInfoIntrinsic>(Inst) &&
786 !FuncInfo->isExportedInst(Inst))
789 // Bottom-up: reset the insert pos at the top, after any local-value
791 FastIS->recomputeInsertPt();
793 // Try to select the instruction with FastISel.
794 if (FastIS->SelectInstruction(Inst)) {
795 // If fast isel succeeded, check to see if there is a single-use
796 // non-volatile load right before the selected instruction, and see if
797 // the load is used by the instruction. If so, try to fold it.
798 const Instruction *BeforeInst = 0;
800 BeforeInst = llvm::prior(llvm::prior(BI));
801 if (BeforeInst && isa<LoadInst>(BeforeInst) &&
802 BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst &&
803 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), FastIS)) {
804 // If we succeeded, don't re-select the load.
810 // Then handle certain instructions as single-LLVM-Instruction blocks.
811 if (isa<CallInst>(Inst)) {
812 ++NumFastIselFailures;
813 if (EnableFastISelVerbose || EnableFastISelAbort) {
814 dbgs() << "FastISel missed call: ";
818 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
819 unsigned &R = FuncInfo->ValueMap[Inst];
821 R = FuncInfo->CreateRegs(Inst->getType());
824 bool HadTailCall = false;
825 SelectBasicBlock(Inst, BI, HadTailCall);
827 // If the call was emitted as a tail call, we're done with the block.
836 // Otherwise, give up on FastISel for the rest of the block.
837 // For now, be a little lenient about non-branch terminators.
838 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
839 ++NumFastIselFailures;
840 if (EnableFastISelVerbose || EnableFastISelAbort) {
841 dbgs() << "FastISel miss: ";
844 if (EnableFastISelAbort)
845 // The "fast" selector couldn't handle something and bailed.
846 // For the purpose of debugging, just abort.
847 llvm_unreachable("FastISel didn't select the entire block");
852 FastIS->recomputeInsertPt();
855 // Run SelectionDAG instruction selection on the remainder of the block
856 // not handled by FastISel. If FastISel is not run, this is the entire
859 SelectBasicBlock(Begin, BI, HadTailCall);
862 FuncInfo->PHINodesToUpdate.clear();
869 SelectionDAGISel::FinishBasicBlock() {
871 DEBUG(dbgs() << "Total amount of phi nodes to update: "
872 << FuncInfo->PHINodesToUpdate.size() << "\n";
873 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
874 dbgs() << "Node " << i << " : ("
875 << FuncInfo->PHINodesToUpdate[i].first
876 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
878 // Next, now that we know what the last MBB the LLVM BB expanded is, update
879 // PHI nodes in successors.
880 if (SDB->SwitchCases.empty() &&
881 SDB->JTCases.empty() &&
882 SDB->BitTestCases.empty()) {
883 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
884 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
885 assert(PHI->isPHI() &&
886 "This is not a machine PHI node that we are updating!");
887 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
890 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
891 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
896 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
897 // Lower header first, if it wasn't already lowered
898 if (!SDB->BitTestCases[i].Emitted) {
899 // Set the current basic block to the mbb we wish to insert the code into
900 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
901 FuncInfo->InsertPt = FuncInfo->MBB->end();
903 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
904 CurDAG->setRoot(SDB->getRoot());
909 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
910 // Set the current basic block to the mbb we wish to insert the code into
911 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
912 FuncInfo->InsertPt = FuncInfo->MBB->end();
915 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
916 SDB->BitTestCases[i].Reg,
917 SDB->BitTestCases[i].Cases[j],
920 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
921 SDB->BitTestCases[i].Reg,
922 SDB->BitTestCases[i].Cases[j],
926 CurDAG->setRoot(SDB->getRoot());
932 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
934 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
935 MachineBasicBlock *PHIBB = PHI->getParent();
936 assert(PHI->isPHI() &&
937 "This is not a machine PHI node that we are updating!");
938 // This is "default" BB. We have two jumps to it. From "header" BB and
939 // from last "case" BB.
940 if (PHIBB == SDB->BitTestCases[i].Default) {
941 PHI->addOperand(MachineOperand::
942 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
944 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
945 PHI->addOperand(MachineOperand::
946 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
948 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
951 // One of "cases" BB.
952 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
954 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
955 if (cBB->isSuccessor(PHIBB)) {
956 PHI->addOperand(MachineOperand::
957 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
959 PHI->addOperand(MachineOperand::CreateMBB(cBB));
964 SDB->BitTestCases.clear();
966 // If the JumpTable record is filled in, then we need to emit a jump table.
967 // Updating the PHI nodes is tricky in this case, since we need to determine
968 // whether the PHI is a successor of the range check MBB or the jump table MBB
969 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
970 // Lower header first, if it wasn't already lowered
971 if (!SDB->JTCases[i].first.Emitted) {
972 // Set the current basic block to the mbb we wish to insert the code into
973 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
974 FuncInfo->InsertPt = FuncInfo->MBB->end();
976 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
978 CurDAG->setRoot(SDB->getRoot());
983 // Set the current basic block to the mbb we wish to insert the code into
984 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
985 FuncInfo->InsertPt = FuncInfo->MBB->end();
987 SDB->visitJumpTable(SDB->JTCases[i].second);
988 CurDAG->setRoot(SDB->getRoot());
993 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
995 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
996 MachineBasicBlock *PHIBB = PHI->getParent();
997 assert(PHI->isPHI() &&
998 "This is not a machine PHI node that we are updating!");
999 // "default" BB. We can go there only from header BB.
1000 if (PHIBB == SDB->JTCases[i].second.Default) {
1002 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1005 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1007 // JT BB. Just iterate over successors here
1008 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1010 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1012 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1016 SDB->JTCases.clear();
1018 // If the switch block involved a branch to one of the actual successors, we
1019 // need to update PHI nodes in that block.
1020 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1021 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1022 assert(PHI->isPHI() &&
1023 "This is not a machine PHI node that we are updating!");
1024 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1026 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1027 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1031 // If we generated any switch lowering information, build and codegen any
1032 // additional DAGs necessary.
1033 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1034 // Set the current basic block to the mbb we wish to insert the code into
1035 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1036 FuncInfo->InsertPt = FuncInfo->MBB->end();
1038 // Determine the unique successors.
1039 SmallVector<MachineBasicBlock *, 2> Succs;
1040 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1041 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1042 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1044 // Emit the code. Note that this could result in ThisBB being split, so
1045 // we need to check for updates.
1046 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1047 CurDAG->setRoot(SDB->getRoot());
1049 CodeGenAndEmitDAG();
1050 ThisBB = FuncInfo->MBB;
1052 // Handle any PHI nodes in successors of this chunk, as if we were coming
1053 // from the original BB before switch expansion. Note that PHI nodes can
1054 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1055 // handle them the right number of times.
1056 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1057 FuncInfo->MBB = Succs[i];
1058 FuncInfo->InsertPt = FuncInfo->MBB->end();
1059 // FuncInfo->MBB may have been removed from the CFG if a branch was
1061 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1062 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1063 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1065 // This value for this PHI node is recorded in PHINodesToUpdate.
1066 for (unsigned pn = 0; ; ++pn) {
1067 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1068 "Didn't find PHI entry!");
1069 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1070 Phi->addOperand(MachineOperand::
1071 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1073 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1081 SDB->SwitchCases.clear();
1085 /// Create the scheduler. If a specific scheduler was specified
1086 /// via the SchedulerRegistry, use it, otherwise select the
1087 /// one preferred by the target.
1089 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1090 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1094 RegisterScheduler::setDefault(Ctor);
1097 return Ctor(this, OptLevel);
1100 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1101 return new ScheduleHazardRecognizer();
1104 //===----------------------------------------------------------------------===//
1105 // Helper functions used by the generated instruction selector.
1106 //===----------------------------------------------------------------------===//
1107 // Calls to these methods are generated by tblgen.
1109 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1110 /// the dag combiner simplified the 255, we still want to match. RHS is the
1111 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1112 /// specified in the .td file (e.g. 255).
1113 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1114 int64_t DesiredMaskS) const {
1115 const APInt &ActualMask = RHS->getAPIntValue();
1116 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1118 // If the actual mask exactly matches, success!
1119 if (ActualMask == DesiredMask)
1122 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1123 if (ActualMask.intersects(~DesiredMask))
1126 // Otherwise, the DAG Combiner may have proven that the value coming in is
1127 // either already zero or is not demanded. Check for known zero input bits.
1128 APInt NeededMask = DesiredMask & ~ActualMask;
1129 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1132 // TODO: check to see if missing bits are just not demanded.
1134 // Otherwise, this pattern doesn't match.
1138 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1139 /// the dag combiner simplified the 255, we still want to match. RHS is the
1140 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1141 /// specified in the .td file (e.g. 255).
1142 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1143 int64_t DesiredMaskS) const {
1144 const APInt &ActualMask = RHS->getAPIntValue();
1145 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1147 // If the actual mask exactly matches, success!
1148 if (ActualMask == DesiredMask)
1151 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1152 if (ActualMask.intersects(~DesiredMask))
1155 // Otherwise, the DAG Combiner may have proven that the value coming in is
1156 // either already zero or is not demanded. Check for known zero input bits.
1157 APInt NeededMask = DesiredMask & ~ActualMask;
1159 APInt KnownZero, KnownOne;
1160 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1162 // If all the missing bits in the or are already known to be set, match!
1163 if ((NeededMask & KnownOne) == NeededMask)
1166 // TODO: check to see if missing bits are just not demanded.
1168 // Otherwise, this pattern doesn't match.
1173 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1174 /// by tblgen. Others should not call it.
1175 void SelectionDAGISel::
1176 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1177 std::vector<SDValue> InOps;
1178 std::swap(InOps, Ops);
1180 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1181 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1182 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1183 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
1185 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1186 if (InOps[e-1].getValueType() == MVT::Flag)
1187 --e; // Don't process a flag operand if it is here.
1190 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1191 if (!InlineAsm::isMemKind(Flags)) {
1192 // Just skip over this operand, copying the operands verbatim.
1193 Ops.insert(Ops.end(), InOps.begin()+i,
1194 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1195 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1197 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1198 "Memory operand with multiple values?");
1199 // Otherwise, this is a memory operand. Ask the target to select it.
1200 std::vector<SDValue> SelOps;
1201 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1202 report_fatal_error("Could not match memory address. Inline asm"
1205 // Add this to the output node.
1207 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1208 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1209 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1214 // Add the flag input back if present.
1215 if (e != InOps.size())
1216 Ops.push_back(InOps.back());
1219 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1222 static SDNode *findFlagUse(SDNode *N) {
1223 unsigned FlagResNo = N->getNumValues()-1;
1224 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1225 SDUse &Use = I.getUse();
1226 if (Use.getResNo() == FlagResNo)
1227 return Use.getUser();
1232 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1233 /// This function recursively traverses up the operand chain, ignoring
1235 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1236 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1237 bool IgnoreChains) {
1238 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1239 // greater than all of its (recursive) operands. If we scan to a point where
1240 // 'use' is smaller than the node we're scanning for, then we know we will
1243 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1244 // happen because we scan down to newly selected nodes in the case of flag
1246 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1249 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1250 // won't fail if we scan it again.
1251 if (!Visited.insert(Use))
1254 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1255 // Ignore chain uses, they are validated by HandleMergeInputChains.
1256 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1259 SDNode *N = Use->getOperand(i).getNode();
1261 if (Use == ImmedUse || Use == Root)
1262 continue; // We are not looking for immediate use.
1267 // Traverse up the operand chain.
1268 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1274 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1275 /// operand node N of U during instruction selection that starts at Root.
1276 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1277 SDNode *Root) const {
1278 if (OptLevel == CodeGenOpt::None) return false;
1279 return N.hasOneUse();
1282 /// IsLegalToFold - Returns true if the specific operand node N of
1283 /// U can be folded during instruction selection that starts at Root.
1284 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1285 CodeGenOpt::Level OptLevel,
1286 bool IgnoreChains) {
1287 if (OptLevel == CodeGenOpt::None) return false;
1289 // If Root use can somehow reach N through a path that that doesn't contain
1290 // U then folding N would create a cycle. e.g. In the following
1291 // diagram, Root can reach N through X. If N is folded into into Root, then
1292 // X is both a predecessor and a successor of U.
1303 // * indicates nodes to be folded together.
1305 // If Root produces a flag, then it gets (even more) interesting. Since it
1306 // will be "glued" together with its flag use in the scheduler, we need to
1307 // check if it might reach N.
1326 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1327 // (call it Fold), then X is a predecessor of FU and a successor of
1328 // Fold. But since Fold and FU are flagged together, this will create
1329 // a cycle in the scheduling graph.
1331 // If the node has flags, walk down the graph to the "lowest" node in the
1333 EVT VT = Root->getValueType(Root->getNumValues()-1);
1334 while (VT == MVT::Flag) {
1335 SDNode *FU = findFlagUse(Root);
1339 VT = Root->getValueType(Root->getNumValues()-1);
1341 // If our query node has a flag result with a use, we've walked up it. If
1342 // the user (which has already been selected) has a chain or indirectly uses
1343 // the chain, our WalkChainUsers predicate will not consider it. Because of
1344 // this, we cannot ignore chains in this predicate.
1345 IgnoreChains = false;
1349 SmallPtrSet<SDNode*, 16> Visited;
1350 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1353 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1354 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1355 SelectInlineAsmMemoryOperands(Ops);
1357 std::vector<EVT> VTs;
1358 VTs.push_back(MVT::Other);
1359 VTs.push_back(MVT::Flag);
1360 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1361 VTs, &Ops[0], Ops.size());
1363 return New.getNode();
1366 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1367 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1370 /// GetVBR - decode a vbr encoding whose top bit is set.
1371 ALWAYS_INLINE static uint64_t
1372 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1373 assert(Val >= 128 && "Not a VBR");
1374 Val &= 127; // Remove first vbr bit.
1379 NextBits = MatcherTable[Idx++];
1380 Val |= (NextBits&127) << Shift;
1382 } while (NextBits & 128);
1388 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1389 /// interior flag and chain results to use the new flag and chain results.
1390 void SelectionDAGISel::
1391 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1392 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1394 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1395 bool isMorphNodeTo) {
1396 SmallVector<SDNode*, 4> NowDeadNodes;
1398 ISelUpdater ISU(ISelPosition);
1400 // Now that all the normal results are replaced, we replace the chain and
1401 // flag results if present.
1402 if (!ChainNodesMatched.empty()) {
1403 assert(InputChain.getNode() != 0 &&
1404 "Matched input chains but didn't produce a chain");
1405 // Loop over all of the nodes we matched that produced a chain result.
1406 // Replace all the chain results with the final chain we ended up with.
1407 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1408 SDNode *ChainNode = ChainNodesMatched[i];
1410 // If this node was already deleted, don't look at it.
1411 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1414 // Don't replace the results of the root node if we're doing a
1416 if (ChainNode == NodeToMatch && isMorphNodeTo)
1419 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1420 if (ChainVal.getValueType() == MVT::Flag)
1421 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1422 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1423 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1425 // If the node became dead and we haven't already seen it, delete it.
1426 if (ChainNode->use_empty() &&
1427 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1428 NowDeadNodes.push_back(ChainNode);
1432 // If the result produces a flag, update any flag results in the matched
1433 // pattern with the flag result.
1434 if (InputFlag.getNode() != 0) {
1435 // Handle any interior nodes explicitly marked.
1436 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1437 SDNode *FRN = FlagResultNodesMatched[i];
1439 // If this node was already deleted, don't look at it.
1440 if (FRN->getOpcode() == ISD::DELETED_NODE)
1443 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1444 "Doesn't have a flag result");
1445 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1448 // If the node became dead and we haven't already seen it, delete it.
1449 if (FRN->use_empty() &&
1450 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1451 NowDeadNodes.push_back(FRN);
1455 if (!NowDeadNodes.empty())
1456 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1458 DEBUG(errs() << "ISEL: Match complete!\n");
1464 CR_LeadsToInteriorNode
1467 /// WalkChainUsers - Walk down the users of the specified chained node that is
1468 /// part of the pattern we're matching, looking at all of the users we find.
1469 /// This determines whether something is an interior node, whether we have a
1470 /// non-pattern node in between two pattern nodes (which prevent folding because
1471 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1472 /// between pattern nodes (in which case the TF becomes part of the pattern).
1474 /// The walk we do here is guaranteed to be small because we quickly get down to
1475 /// already selected nodes "below" us.
1477 WalkChainUsers(SDNode *ChainedNode,
1478 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1479 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1480 ChainResult Result = CR_Simple;
1482 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1483 E = ChainedNode->use_end(); UI != E; ++UI) {
1484 // Make sure the use is of the chain, not some other value we produce.
1485 if (UI.getUse().getValueType() != MVT::Other) continue;
1489 // If we see an already-selected machine node, then we've gone beyond the
1490 // pattern that we're selecting down into the already selected chunk of the
1492 if (User->isMachineOpcode() ||
1493 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1496 if (User->getOpcode() == ISD::CopyToReg ||
1497 User->getOpcode() == ISD::CopyFromReg ||
1498 User->getOpcode() == ISD::INLINEASM ||
1499 User->getOpcode() == ISD::EH_LABEL) {
1500 // If their node ID got reset to -1 then they've already been selected.
1501 // Treat them like a MachineOpcode.
1502 if (User->getNodeId() == -1)
1506 // If we have a TokenFactor, we handle it specially.
1507 if (User->getOpcode() != ISD::TokenFactor) {
1508 // If the node isn't a token factor and isn't part of our pattern, then it
1509 // must be a random chained node in between two nodes we're selecting.
1510 // This happens when we have something like:
1515 // Because we structurally match the load/store as a read/modify/write,
1516 // but the call is chained between them. We cannot fold in this case
1517 // because it would induce a cycle in the graph.
1518 if (!std::count(ChainedNodesInPattern.begin(),
1519 ChainedNodesInPattern.end(), User))
1520 return CR_InducesCycle;
1522 // Otherwise we found a node that is part of our pattern. For example in:
1526 // This would happen when we're scanning down from the load and see the
1527 // store as a user. Record that there is a use of ChainedNode that is
1528 // part of the pattern and keep scanning uses.
1529 Result = CR_LeadsToInteriorNode;
1530 InteriorChainedNodes.push_back(User);
1534 // If we found a TokenFactor, there are two cases to consider: first if the
1535 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1536 // uses of the TF are in our pattern) we just want to ignore it. Second,
1537 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1543 // | \ DAG's like cheese
1546 // [TokenFactor] [Op]
1553 // In this case, the TokenFactor becomes part of our match and we rewrite it
1554 // as a new TokenFactor.
1556 // To distinguish these two cases, do a recursive walk down the uses.
1557 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1559 // If the uses of the TokenFactor are just already-selected nodes, ignore
1560 // it, it is "below" our pattern.
1562 case CR_InducesCycle:
1563 // If the uses of the TokenFactor lead to nodes that are not part of our
1564 // pattern that are not selected, folding would turn this into a cycle,
1566 return CR_InducesCycle;
1567 case CR_LeadsToInteriorNode:
1568 break; // Otherwise, keep processing.
1571 // Okay, we know we're in the interesting interior case. The TokenFactor
1572 // is now going to be considered part of the pattern so that we rewrite its
1573 // uses (it may have uses that are not part of the pattern) with the
1574 // ultimate chain result of the generated code. We will also add its chain
1575 // inputs as inputs to the ultimate TokenFactor we create.
1576 Result = CR_LeadsToInteriorNode;
1577 ChainedNodesInPattern.push_back(User);
1578 InteriorChainedNodes.push_back(User);
1585 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1586 /// operation for when the pattern matched at least one node with a chains. The
1587 /// input vector contains a list of all of the chained nodes that we match. We
1588 /// must determine if this is a valid thing to cover (i.e. matching it won't
1589 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1590 /// be used as the input node chain for the generated nodes.
1592 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1593 SelectionDAG *CurDAG) {
1594 // Walk all of the chained nodes we've matched, recursively scanning down the
1595 // users of the chain result. This adds any TokenFactor nodes that are caught
1596 // in between chained nodes to the chained and interior nodes list.
1597 SmallVector<SDNode*, 3> InteriorChainedNodes;
1598 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1599 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1600 InteriorChainedNodes) == CR_InducesCycle)
1601 return SDValue(); // Would induce a cycle.
1604 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1605 // that we are interested in. Form our input TokenFactor node.
1606 SmallVector<SDValue, 3> InputChains;
1607 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1608 // Add the input chain of this node to the InputChains list (which will be
1609 // the operands of the generated TokenFactor) if it's not an interior node.
1610 SDNode *N = ChainNodesMatched[i];
1611 if (N->getOpcode() != ISD::TokenFactor) {
1612 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1615 // Otherwise, add the input chain.
1616 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1617 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1618 InputChains.push_back(InChain);
1622 // If we have a token factor, we want to add all inputs of the token factor
1623 // that are not part of the pattern we're matching.
1624 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1625 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1626 N->getOperand(op).getNode()))
1627 InputChains.push_back(N->getOperand(op));
1632 if (InputChains.size() == 1)
1633 return InputChains[0];
1634 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1635 MVT::Other, &InputChains[0], InputChains.size());
1638 /// MorphNode - Handle morphing a node in place for the selector.
1639 SDNode *SelectionDAGISel::
1640 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1641 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1642 // It is possible we're using MorphNodeTo to replace a node with no
1643 // normal results with one that has a normal result (or we could be
1644 // adding a chain) and the input could have flags and chains as well.
1645 // In this case we need to shift the operands down.
1646 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1647 // than the old isel though.
1648 int OldFlagResultNo = -1, OldChainResultNo = -1;
1650 unsigned NTMNumResults = Node->getNumValues();
1651 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1652 OldFlagResultNo = NTMNumResults-1;
1653 if (NTMNumResults != 1 &&
1654 Node->getValueType(NTMNumResults-2) == MVT::Other)
1655 OldChainResultNo = NTMNumResults-2;
1656 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1657 OldChainResultNo = NTMNumResults-1;
1659 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1660 // that this deletes operands of the old node that become dead.
1661 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1663 // MorphNodeTo can operate in two ways: if an existing node with the
1664 // specified operands exists, it can just return it. Otherwise, it
1665 // updates the node in place to have the requested operands.
1667 // If we updated the node in place, reset the node ID. To the isel,
1668 // this should be just like a newly allocated machine node.
1672 unsigned ResNumResults = Res->getNumValues();
1673 // Move the flag if needed.
1674 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1675 (unsigned)OldFlagResultNo != ResNumResults-1)
1676 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1677 SDValue(Res, ResNumResults-1));
1679 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1682 // Move the chain reference if needed.
1683 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1684 (unsigned)OldChainResultNo != ResNumResults-1)
1685 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1686 SDValue(Res, ResNumResults-1));
1688 // Otherwise, no replacement happened because the node already exists. Replace
1689 // Uses of the old node with the new one.
1691 CurDAG->ReplaceAllUsesWith(Node, Res);
1696 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1697 ALWAYS_INLINE static bool
1698 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1700 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1701 // Accept if it is exactly the same as a previously recorded node.
1702 unsigned RecNo = MatcherTable[MatcherIndex++];
1703 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1704 return N == RecordedNodes[RecNo].first;
1707 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1708 ALWAYS_INLINE static bool
1709 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1710 SelectionDAGISel &SDISel) {
1711 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1714 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1715 ALWAYS_INLINE static bool
1716 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1717 SelectionDAGISel &SDISel, SDNode *N) {
1718 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1721 ALWAYS_INLINE static bool
1722 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1724 uint16_t Opc = MatcherTable[MatcherIndex++];
1725 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1726 return N->getOpcode() == Opc;
1729 ALWAYS_INLINE static bool
1730 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1731 SDValue N, const TargetLowering &TLI) {
1732 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1733 if (N.getValueType() == VT) return true;
1735 // Handle the case when VT is iPTR.
1736 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1739 ALWAYS_INLINE static bool
1740 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1741 SDValue N, const TargetLowering &TLI,
1743 if (ChildNo >= N.getNumOperands())
1744 return false; // Match fails if out of range child #.
1745 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1749 ALWAYS_INLINE static bool
1750 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1752 return cast<CondCodeSDNode>(N)->get() ==
1753 (ISD::CondCode)MatcherTable[MatcherIndex++];
1756 ALWAYS_INLINE static bool
1757 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1758 SDValue N, const TargetLowering &TLI) {
1759 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1760 if (cast<VTSDNode>(N)->getVT() == VT)
1763 // Handle the case when VT is iPTR.
1764 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1767 ALWAYS_INLINE static bool
1768 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1770 int64_t Val = MatcherTable[MatcherIndex++];
1772 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1774 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1775 return C != 0 && C->getSExtValue() == Val;
1778 ALWAYS_INLINE static bool
1779 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1780 SDValue N, SelectionDAGISel &SDISel) {
1781 int64_t Val = MatcherTable[MatcherIndex++];
1783 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1785 if (N->getOpcode() != ISD::AND) return false;
1787 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1788 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1791 ALWAYS_INLINE static bool
1792 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1793 SDValue N, SelectionDAGISel &SDISel) {
1794 int64_t Val = MatcherTable[MatcherIndex++];
1796 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1798 if (N->getOpcode() != ISD::OR) return false;
1800 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1801 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1804 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1805 /// scope, evaluate the current node. If the current predicate is known to
1806 /// fail, set Result=true and return anything. If the current predicate is
1807 /// known to pass, set Result=false and return the MatcherIndex to continue
1808 /// with. If the current predicate is unknown, set Result=false and return the
1809 /// MatcherIndex to continue with.
1810 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1811 unsigned Index, SDValue N,
1812 bool &Result, SelectionDAGISel &SDISel,
1813 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1814 switch (Table[Index++]) {
1817 return Index-1; // Could not evaluate this predicate.
1818 case SelectionDAGISel::OPC_CheckSame:
1819 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1821 case SelectionDAGISel::OPC_CheckPatternPredicate:
1822 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1824 case SelectionDAGISel::OPC_CheckPredicate:
1825 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1827 case SelectionDAGISel::OPC_CheckOpcode:
1828 Result = !::CheckOpcode(Table, Index, N.getNode());
1830 case SelectionDAGISel::OPC_CheckType:
1831 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1833 case SelectionDAGISel::OPC_CheckChild0Type:
1834 case SelectionDAGISel::OPC_CheckChild1Type:
1835 case SelectionDAGISel::OPC_CheckChild2Type:
1836 case SelectionDAGISel::OPC_CheckChild3Type:
1837 case SelectionDAGISel::OPC_CheckChild4Type:
1838 case SelectionDAGISel::OPC_CheckChild5Type:
1839 case SelectionDAGISel::OPC_CheckChild6Type:
1840 case SelectionDAGISel::OPC_CheckChild7Type:
1841 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1842 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1844 case SelectionDAGISel::OPC_CheckCondCode:
1845 Result = !::CheckCondCode(Table, Index, N);
1847 case SelectionDAGISel::OPC_CheckValueType:
1848 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1850 case SelectionDAGISel::OPC_CheckInteger:
1851 Result = !::CheckInteger(Table, Index, N);
1853 case SelectionDAGISel::OPC_CheckAndImm:
1854 Result = !::CheckAndImm(Table, Index, N, SDISel);
1856 case SelectionDAGISel::OPC_CheckOrImm:
1857 Result = !::CheckOrImm(Table, Index, N, SDISel);
1865 /// FailIndex - If this match fails, this is the index to continue with.
1868 /// NodeStack - The node stack when the scope was formed.
1869 SmallVector<SDValue, 4> NodeStack;
1871 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1872 unsigned NumRecordedNodes;
1874 /// NumMatchedMemRefs - The number of matched memref entries.
1875 unsigned NumMatchedMemRefs;
1877 /// InputChain/InputFlag - The current chain/flag
1878 SDValue InputChain, InputFlag;
1880 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1881 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1886 SDNode *SelectionDAGISel::
1887 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1888 unsigned TableSize) {
1889 // FIXME: Should these even be selected? Handle these cases in the caller?
1890 switch (NodeToMatch->getOpcode()) {
1893 case ISD::EntryToken: // These nodes remain the same.
1894 case ISD::BasicBlock:
1896 //case ISD::VALUETYPE:
1897 //case ISD::CONDCODE:
1898 case ISD::HANDLENODE:
1899 case ISD::MDNODE_SDNODE:
1900 case ISD::TargetConstant:
1901 case ISD::TargetConstantFP:
1902 case ISD::TargetConstantPool:
1903 case ISD::TargetFrameIndex:
1904 case ISD::TargetExternalSymbol:
1905 case ISD::TargetBlockAddress:
1906 case ISD::TargetJumpTable:
1907 case ISD::TargetGlobalTLSAddress:
1908 case ISD::TargetGlobalAddress:
1909 case ISD::TokenFactor:
1910 case ISD::CopyFromReg:
1911 case ISD::CopyToReg:
1913 NodeToMatch->setNodeId(-1); // Mark selected.
1915 case ISD::AssertSext:
1916 case ISD::AssertZext:
1917 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1918 NodeToMatch->getOperand(0));
1920 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1921 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1924 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1926 // Set up the node stack with NodeToMatch as the only node on the stack.
1927 SmallVector<SDValue, 8> NodeStack;
1928 SDValue N = SDValue(NodeToMatch, 0);
1929 NodeStack.push_back(N);
1931 // MatchScopes - Scopes used when matching, if a match failure happens, this
1932 // indicates where to continue checking.
1933 SmallVector<MatchScope, 8> MatchScopes;
1935 // RecordedNodes - This is the set of nodes that have been recorded by the
1936 // state machine. The second value is the parent of the node, or null if the
1937 // root is recorded.
1938 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
1940 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1942 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1944 // These are the current input chain and flag for use when generating nodes.
1945 // Various Emit operations change these. For example, emitting a copytoreg
1946 // uses and updates these.
1947 SDValue InputChain, InputFlag;
1949 // ChainNodesMatched - If a pattern matches nodes that have input/output
1950 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1951 // which ones they are. The result is captured into this list so that we can
1952 // update the chain results when the pattern is complete.
1953 SmallVector<SDNode*, 3> ChainNodesMatched;
1954 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1956 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1957 NodeToMatch->dump(CurDAG);
1960 // Determine where to start the interpreter. Normally we start at opcode #0,
1961 // but if the state machine starts with an OPC_SwitchOpcode, then we
1962 // accelerate the first lookup (which is guaranteed to be hot) with the
1963 // OpcodeOffset table.
1964 unsigned MatcherIndex = 0;
1966 if (!OpcodeOffset.empty()) {
1967 // Already computed the OpcodeOffset table, just index into it.
1968 if (N.getOpcode() < OpcodeOffset.size())
1969 MatcherIndex = OpcodeOffset[N.getOpcode()];
1970 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1972 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1973 // Otherwise, the table isn't computed, but the state machine does start
1974 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1975 // is the first time we're selecting an instruction.
1978 // Get the size of this case.
1979 unsigned CaseSize = MatcherTable[Idx++];
1981 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1982 if (CaseSize == 0) break;
1984 // Get the opcode, add the index to the table.
1985 uint16_t Opc = MatcherTable[Idx++];
1986 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1987 if (Opc >= OpcodeOffset.size())
1988 OpcodeOffset.resize((Opc+1)*2);
1989 OpcodeOffset[Opc] = Idx;
1993 // Okay, do the lookup for the first opcode.
1994 if (N.getOpcode() < OpcodeOffset.size())
1995 MatcherIndex = OpcodeOffset[N.getOpcode()];
1999 assert(MatcherIndex < TableSize && "Invalid index");
2001 unsigned CurrentOpcodeIndex = MatcherIndex;
2003 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2006 // Okay, the semantics of this operation are that we should push a scope
2007 // then evaluate the first child. However, pushing a scope only to have
2008 // the first check fail (which then pops it) is inefficient. If we can
2009 // determine immediately that the first check (or first several) will
2010 // immediately fail, don't even bother pushing a scope for them.
2014 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2015 if (NumToSkip & 128)
2016 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2017 // Found the end of the scope with no match.
2018 if (NumToSkip == 0) {
2023 FailIndex = MatcherIndex+NumToSkip;
2025 unsigned MatcherIndexOfPredicate = MatcherIndex;
2026 (void)MatcherIndexOfPredicate; // silence warning.
2028 // If we can't evaluate this predicate without pushing a scope (e.g. if
2029 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2030 // push the scope and evaluate the full predicate chain.
2032 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2033 Result, *this, RecordedNodes);
2037 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2038 << "index " << MatcherIndexOfPredicate
2039 << ", continuing at " << FailIndex << "\n");
2040 ++NumDAGIselRetries;
2042 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2043 // move to the next case.
2044 MatcherIndex = FailIndex;
2047 // If the whole scope failed to match, bail.
2048 if (FailIndex == 0) break;
2050 // Push a MatchScope which indicates where to go if the first child fails
2052 MatchScope NewEntry;
2053 NewEntry.FailIndex = FailIndex;
2054 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2055 NewEntry.NumRecordedNodes = RecordedNodes.size();
2056 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2057 NewEntry.InputChain = InputChain;
2058 NewEntry.InputFlag = InputFlag;
2059 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2060 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2061 MatchScopes.push_back(NewEntry);
2064 case OPC_RecordNode: {
2065 // Remember this node, it may end up being an operand in the pattern.
2067 if (NodeStack.size() > 1)
2068 Parent = NodeStack[NodeStack.size()-2].getNode();
2069 RecordedNodes.push_back(std::make_pair(N, Parent));
2073 case OPC_RecordChild0: case OPC_RecordChild1:
2074 case OPC_RecordChild2: case OPC_RecordChild3:
2075 case OPC_RecordChild4: case OPC_RecordChild5:
2076 case OPC_RecordChild6: case OPC_RecordChild7: {
2077 unsigned ChildNo = Opcode-OPC_RecordChild0;
2078 if (ChildNo >= N.getNumOperands())
2079 break; // Match fails if out of range child #.
2081 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2085 case OPC_RecordMemRef:
2086 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2089 case OPC_CaptureFlagInput:
2090 // If the current node has an input flag, capture it in InputFlag.
2091 if (N->getNumOperands() != 0 &&
2092 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2093 InputFlag = N->getOperand(N->getNumOperands()-1);
2096 case OPC_MoveChild: {
2097 unsigned ChildNo = MatcherTable[MatcherIndex++];
2098 if (ChildNo >= N.getNumOperands())
2099 break; // Match fails if out of range child #.
2100 N = N.getOperand(ChildNo);
2101 NodeStack.push_back(N);
2105 case OPC_MoveParent:
2106 // Pop the current node off the NodeStack.
2107 NodeStack.pop_back();
2108 assert(!NodeStack.empty() && "Node stack imbalance!");
2109 N = NodeStack.back();
2113 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2115 case OPC_CheckPatternPredicate:
2116 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2118 case OPC_CheckPredicate:
2119 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2123 case OPC_CheckComplexPat: {
2124 unsigned CPNum = MatcherTable[MatcherIndex++];
2125 unsigned RecNo = MatcherTable[MatcherIndex++];
2126 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2127 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2128 RecordedNodes[RecNo].first, CPNum,
2133 case OPC_CheckOpcode:
2134 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2138 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2141 case OPC_SwitchOpcode: {
2142 unsigned CurNodeOpcode = N.getOpcode();
2143 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2146 // Get the size of this case.
2147 CaseSize = MatcherTable[MatcherIndex++];
2149 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2150 if (CaseSize == 0) break;
2152 uint16_t Opc = MatcherTable[MatcherIndex++];
2153 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2155 // If the opcode matches, then we will execute this case.
2156 if (CurNodeOpcode == Opc)
2159 // Otherwise, skip over this case.
2160 MatcherIndex += CaseSize;
2163 // If no cases matched, bail out.
2164 if (CaseSize == 0) break;
2166 // Otherwise, execute the case we found.
2167 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2168 << " to " << MatcherIndex << "\n");
2172 case OPC_SwitchType: {
2173 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2174 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2177 // Get the size of this case.
2178 CaseSize = MatcherTable[MatcherIndex++];
2180 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2181 if (CaseSize == 0) break;
2183 MVT::SimpleValueType CaseVT =
2184 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2185 if (CaseVT == MVT::iPTR)
2186 CaseVT = TLI.getPointerTy().SimpleTy;
2188 // If the VT matches, then we will execute this case.
2189 if (CurNodeVT == CaseVT)
2192 // Otherwise, skip over this case.
2193 MatcherIndex += CaseSize;
2196 // If no cases matched, bail out.
2197 if (CaseSize == 0) break;
2199 // Otherwise, execute the case we found.
2200 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2201 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2204 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2205 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2206 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2207 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2208 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2209 Opcode-OPC_CheckChild0Type))
2212 case OPC_CheckCondCode:
2213 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2215 case OPC_CheckValueType:
2216 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2218 case OPC_CheckInteger:
2219 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2221 case OPC_CheckAndImm:
2222 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2224 case OPC_CheckOrImm:
2225 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2228 case OPC_CheckFoldableChainNode: {
2229 assert(NodeStack.size() != 1 && "No parent node");
2230 // Verify that all intermediate nodes between the root and this one have
2232 bool HasMultipleUses = false;
2233 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2234 if (!NodeStack[i].hasOneUse()) {
2235 HasMultipleUses = true;
2238 if (HasMultipleUses) break;
2240 // Check to see that the target thinks this is profitable to fold and that
2241 // we can fold it without inducing cycles in the graph.
2242 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2244 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2245 NodeToMatch, OptLevel,
2246 true/*We validate our own chains*/))
2251 case OPC_EmitInteger: {
2252 MVT::SimpleValueType VT =
2253 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2254 int64_t Val = MatcherTable[MatcherIndex++];
2256 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2257 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2258 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2261 case OPC_EmitRegister: {
2262 MVT::SimpleValueType VT =
2263 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2264 unsigned RegNo = MatcherTable[MatcherIndex++];
2265 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2266 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2270 case OPC_EmitConvertToTarget: {
2271 // Convert from IMM/FPIMM to target version.
2272 unsigned RecNo = MatcherTable[MatcherIndex++];
2273 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2274 SDValue Imm = RecordedNodes[RecNo].first;
2276 if (Imm->getOpcode() == ISD::Constant) {
2277 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2278 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2279 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2280 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2281 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2284 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2288 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2289 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2290 // These are space-optimized forms of OPC_EmitMergeInputChains.
2291 assert(InputChain.getNode() == 0 &&
2292 "EmitMergeInputChains should be the first chain producing node");
2293 assert(ChainNodesMatched.empty() &&
2294 "Should only have one EmitMergeInputChains per match");
2296 // Read all of the chained nodes.
2297 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2298 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2299 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2301 // FIXME: What if other value results of the node have uses not matched
2303 if (ChainNodesMatched.back() != NodeToMatch &&
2304 !RecordedNodes[RecNo].first.hasOneUse()) {
2305 ChainNodesMatched.clear();
2309 // Merge the input chains if they are not intra-pattern references.
2310 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2312 if (InputChain.getNode() == 0)
2313 break; // Failed to merge.
2317 case OPC_EmitMergeInputChains: {
2318 assert(InputChain.getNode() == 0 &&
2319 "EmitMergeInputChains should be the first chain producing node");
2320 // This node gets a list of nodes we matched in the input that have
2321 // chains. We want to token factor all of the input chains to these nodes
2322 // together. However, if any of the input chains is actually one of the
2323 // nodes matched in this pattern, then we have an intra-match reference.
2324 // Ignore these because the newly token factored chain should not refer to
2326 unsigned NumChains = MatcherTable[MatcherIndex++];
2327 assert(NumChains != 0 && "Can't TF zero chains");
2329 assert(ChainNodesMatched.empty() &&
2330 "Should only have one EmitMergeInputChains per match");
2332 // Read all of the chained nodes.
2333 for (unsigned i = 0; i != NumChains; ++i) {
2334 unsigned RecNo = MatcherTable[MatcherIndex++];
2335 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2336 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2338 // FIXME: What if other value results of the node have uses not matched
2340 if (ChainNodesMatched.back() != NodeToMatch &&
2341 !RecordedNodes[RecNo].first.hasOneUse()) {
2342 ChainNodesMatched.clear();
2347 // If the inner loop broke out, the match fails.
2348 if (ChainNodesMatched.empty())
2351 // Merge the input chains if they are not intra-pattern references.
2352 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2354 if (InputChain.getNode() == 0)
2355 break; // Failed to merge.
2360 case OPC_EmitCopyToReg: {
2361 unsigned RecNo = MatcherTable[MatcherIndex++];
2362 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2363 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2365 if (InputChain.getNode() == 0)
2366 InputChain = CurDAG->getEntryNode();
2368 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2369 DestPhysReg, RecordedNodes[RecNo].first,
2372 InputFlag = InputChain.getValue(1);
2376 case OPC_EmitNodeXForm: {
2377 unsigned XFormNo = MatcherTable[MatcherIndex++];
2378 unsigned RecNo = MatcherTable[MatcherIndex++];
2379 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2380 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2381 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2386 case OPC_MorphNodeTo: {
2387 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2388 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2389 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2390 // Get the result VT list.
2391 unsigned NumVTs = MatcherTable[MatcherIndex++];
2392 SmallVector<EVT, 4> VTs;
2393 for (unsigned i = 0; i != NumVTs; ++i) {
2394 MVT::SimpleValueType VT =
2395 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2396 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2400 if (EmitNodeInfo & OPFL_Chain)
2401 VTs.push_back(MVT::Other);
2402 if (EmitNodeInfo & OPFL_FlagOutput)
2403 VTs.push_back(MVT::Flag);
2405 // This is hot code, so optimize the two most common cases of 1 and 2
2408 if (VTs.size() == 1)
2409 VTList = CurDAG->getVTList(VTs[0]);
2410 else if (VTs.size() == 2)
2411 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2413 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2415 // Get the operand list.
2416 unsigned NumOps = MatcherTable[MatcherIndex++];
2417 SmallVector<SDValue, 8> Ops;
2418 for (unsigned i = 0; i != NumOps; ++i) {
2419 unsigned RecNo = MatcherTable[MatcherIndex++];
2421 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2423 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2424 Ops.push_back(RecordedNodes[RecNo].first);
2427 // If there are variadic operands to add, handle them now.
2428 if (EmitNodeInfo & OPFL_VariadicInfo) {
2429 // Determine the start index to copy from.
2430 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2431 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2432 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2433 "Invalid variadic node");
2434 // Copy all of the variadic operands, not including a potential flag
2436 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2438 SDValue V = NodeToMatch->getOperand(i);
2439 if (V.getValueType() == MVT::Flag) break;
2444 // If this has chain/flag inputs, add them.
2445 if (EmitNodeInfo & OPFL_Chain)
2446 Ops.push_back(InputChain);
2447 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2448 Ops.push_back(InputFlag);
2452 if (Opcode != OPC_MorphNodeTo) {
2453 // If this is a normal EmitNode command, just create the new node and
2454 // add the results to the RecordedNodes list.
2455 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2456 VTList, Ops.data(), Ops.size());
2458 // Add all the non-flag/non-chain results to the RecordedNodes list.
2459 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2460 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2461 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2466 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2470 // If the node had chain/flag results, update our notion of the current
2472 if (EmitNodeInfo & OPFL_FlagOutput) {
2473 InputFlag = SDValue(Res, VTs.size()-1);
2474 if (EmitNodeInfo & OPFL_Chain)
2475 InputChain = SDValue(Res, VTs.size()-2);
2476 } else if (EmitNodeInfo & OPFL_Chain)
2477 InputChain = SDValue(Res, VTs.size()-1);
2479 // If the OPFL_MemRefs flag is set on this node, slap all of the
2480 // accumulated memrefs onto it.
2482 // FIXME: This is vastly incorrect for patterns with multiple outputs
2483 // instructions that access memory and for ComplexPatterns that match
2485 if (EmitNodeInfo & OPFL_MemRefs) {
2486 MachineSDNode::mmo_iterator MemRefs =
2487 MF->allocateMemRefsArray(MatchedMemRefs.size());
2488 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2489 cast<MachineSDNode>(Res)
2490 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2494 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2495 << " node: "; Res->dump(CurDAG); errs() << "\n");
2497 // If this was a MorphNodeTo then we're completely done!
2498 if (Opcode == OPC_MorphNodeTo) {
2499 // Update chain and flag uses.
2500 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2501 InputFlag, FlagResultNodesMatched, true);
2508 case OPC_MarkFlagResults: {
2509 unsigned NumNodes = MatcherTable[MatcherIndex++];
2511 // Read and remember all the flag-result nodes.
2512 for (unsigned i = 0; i != NumNodes; ++i) {
2513 unsigned RecNo = MatcherTable[MatcherIndex++];
2515 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2517 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2518 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2523 case OPC_CompleteMatch: {
2524 // The match has been completed, and any new nodes (if any) have been
2525 // created. Patch up references to the matched dag to use the newly
2527 unsigned NumResults = MatcherTable[MatcherIndex++];
2529 for (unsigned i = 0; i != NumResults; ++i) {
2530 unsigned ResSlot = MatcherTable[MatcherIndex++];
2532 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2534 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2535 SDValue Res = RecordedNodes[ResSlot].first;
2537 assert(i < NodeToMatch->getNumValues() &&
2538 NodeToMatch->getValueType(i) != MVT::Other &&
2539 NodeToMatch->getValueType(i) != MVT::Flag &&
2540 "Invalid number of results to complete!");
2541 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2542 NodeToMatch->getValueType(i) == MVT::iPTR ||
2543 Res.getValueType() == MVT::iPTR ||
2544 NodeToMatch->getValueType(i).getSizeInBits() ==
2545 Res.getValueType().getSizeInBits()) &&
2546 "invalid replacement");
2547 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2550 // If the root node defines a flag, add it to the flag nodes to update
2552 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2553 FlagResultNodesMatched.push_back(NodeToMatch);
2555 // Update chain and flag uses.
2556 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2557 InputFlag, FlagResultNodesMatched, false);
2559 assert(NodeToMatch->use_empty() &&
2560 "Didn't replace all uses of the node?");
2562 // FIXME: We just return here, which interacts correctly with SelectRoot
2563 // above. We should fix this to not return an SDNode* anymore.
2568 // If the code reached this point, then the match failed. See if there is
2569 // another child to try in the current 'Scope', otherwise pop it until we
2570 // find a case to check.
2571 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2572 ++NumDAGIselRetries;
2574 if (MatchScopes.empty()) {
2575 CannotYetSelect(NodeToMatch);
2579 // Restore the interpreter state back to the point where the scope was
2581 MatchScope &LastScope = MatchScopes.back();
2582 RecordedNodes.resize(LastScope.NumRecordedNodes);
2584 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2585 N = NodeStack.back();
2587 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2588 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2589 MatcherIndex = LastScope.FailIndex;
2591 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2593 InputChain = LastScope.InputChain;
2594 InputFlag = LastScope.InputFlag;
2595 if (!LastScope.HasChainNodesMatched)
2596 ChainNodesMatched.clear();
2597 if (!LastScope.HasFlagResultNodesMatched)
2598 FlagResultNodesMatched.clear();
2600 // Check to see what the offset is at the new MatcherIndex. If it is zero
2601 // we have reached the end of this scope, otherwise we have another child
2602 // in the current scope to try.
2603 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2604 if (NumToSkip & 128)
2605 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2607 // If we have another child in this scope to match, update FailIndex and
2609 if (NumToSkip != 0) {
2610 LastScope.FailIndex = MatcherIndex+NumToSkip;
2614 // End of this scope, pop it and try the next child in the containing
2616 MatchScopes.pop_back();
2623 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2625 raw_string_ostream Msg(msg);
2626 Msg << "Cannot yet select: ";
2628 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2629 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2630 N->getOpcode() != ISD::INTRINSIC_VOID) {
2631 N->printrFull(Msg, CurDAG);
2633 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2635 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2636 if (iid < Intrinsic::num_intrinsics)
2637 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2638 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2639 Msg << "target intrinsic %" << TII->getName(iid);
2641 Msg << "unknown intrinsic #" << iid;
2643 report_fatal_error(Msg.str());
2646 char SelectionDAGISel::ID = 0;