1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetIntrinsicInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/ADT/Statistic.h"
53 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
54 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
57 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
58 cl::desc("Enable verbose messages in the \"fast\" "
59 "instruction selector"));
61 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
62 cl::desc("Enable abort calls when \"fast\" instruction fails"));
66 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
67 cl::desc("Pop up a window to show dags before the first "
70 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before legalize types"));
73 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
74 cl::desc("Pop up a window to show dags before legalize"));
76 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the second "
80 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the post legalize types"
82 " dag combine pass"));
84 ViewISelDAGs("view-isel-dags", cl::Hidden,
85 cl::desc("Pop up a window to show isel dags as they are selected"));
87 ViewSchedDAGs("view-sched-dags", cl::Hidden,
88 cl::desc("Pop up a window to show sched dags as they are processed"));
90 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
91 cl::desc("Pop up a window to show SUnit dags after they are processed"));
93 static const bool ViewDAGCombine1 = false,
94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
95 ViewDAGCombine2 = false,
96 ViewDAGCombineLT = false,
97 ViewISelDAGs = false, ViewSchedDAGs = false,
98 ViewSUnitDAGs = false;
101 //===---------------------------------------------------------------------===//
103 /// RegisterScheduler class - Track the registration of instruction schedulers.
105 //===---------------------------------------------------------------------===//
106 MachinePassRegistry RegisterScheduler::Registry;
108 //===---------------------------------------------------------------------===//
110 /// ISHeuristic command line option for instruction schedulers.
112 //===---------------------------------------------------------------------===//
113 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
114 RegisterPassParser<RegisterScheduler> >
115 ISHeuristic("pre-RA-sched",
116 cl::init(&createDefaultScheduler),
117 cl::desc("Instruction schedulers available (before register"
120 static RegisterScheduler
121 defaultListDAGScheduler("default", "Best scheduler for the target",
122 createDefaultScheduler);
125 //===--------------------------------------------------------------------===//
126 /// createDefaultScheduler - This creates an instruction scheduler appropriate
128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
129 CodeGenOpt::Level OptLevel) {
130 const TargetLowering &TLI = IS->getTargetLowering();
132 if (OptLevel == CodeGenOpt::None)
133 return createFastDAGScheduler(IS, OptLevel);
134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
135 return createTDListDAGScheduler(IS, OptLevel);
136 assert(TLI.getSchedulingPreference() ==
137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
138 return createBURRListDAGScheduler(IS, OptLevel);
142 // EmitInstrWithCustomInserter - This method should be implemented by targets
143 // that mark instructions with the 'usesCustomInserter' flag. These
144 // instructions are special in various ways, which require special support to
145 // insert. The specified MachineInstr is created but not inserted into any
146 // basic blocks, and this method is called to expand it into a sequence of
147 // instructions, potentially also creating new basic blocks and control flow.
148 // When new basic blocks are inserted and the edges from MBB to its successors
149 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
151 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
152 MachineBasicBlock *MBB,
153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
155 dbgs() << "If a target marks an instruction with "
156 "'usesCustomInserter', it must implement "
157 "TargetLowering::EmitInstrWithCustomInserter!";
163 //===----------------------------------------------------------------------===//
164 // SelectionDAGISel code
165 //===----------------------------------------------------------------------===//
167 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
169 FuncInfo(new FunctionLoweringInfo(TLI)),
170 CurDAG(new SelectionDAG(tm, *FuncInfo)),
171 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
177 SelectionDAGISel::~SelectionDAGISel() {
183 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
184 AU.addRequired<AliasAnalysis>();
185 AU.addPreserved<AliasAnalysis>();
186 AU.addRequired<GCModuleInfo>();
187 AU.addPreserved<GCModuleInfo>();
188 MachineFunctionPass::getAnalysisUsage(AU);
191 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
192 // Do some sanity-checking on the command-line options.
193 assert((!EnableFastISelVerbose || EnableFastISel) &&
194 "-fast-isel-verbose requires -fast-isel");
195 assert((!EnableFastISelAbort || EnableFastISel) &&
196 "-fast-isel-abort requires -fast-isel");
198 const Function &Fn = *mf.getFunction();
199 const TargetInstrInfo &TII = *TM.getInstrInfo();
200 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
203 RegInfo = &MF->getRegInfo();
204 AA = &getAnalysis<AliasAnalysis>();
205 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
207 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
210 FuncInfo->set(Fn, *MF, EnableFastISel);
213 SelectAllBasicBlocks(Fn);
215 // If the first basic block in the function has live ins that need to be
216 // copied into vregs, emit the copies into the top of the block before
217 // emitting the code for the block.
218 MachineBasicBlock *EntryMBB = MF->begin();
219 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
221 // Insert DBG_VALUE instructions for function arguments to the entry block.
222 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
223 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
224 unsigned Reg = MI->getOperand(0).getReg();
225 if (TargetRegisterInfo::isPhysicalRegister(Reg))
226 EntryMBB->insert(EntryMBB->begin(), MI);
228 MachineInstr *Def = RegInfo->getVRegDef(Reg);
229 MachineBasicBlock::iterator InsertPos = Def;
230 EntryMBB->insert(llvm::next(InsertPos), MI);
234 // Release function-specific state. SDB and CurDAG are already cleared
242 SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
243 const BasicBlock *LLVMBB,
244 BasicBlock::const_iterator Begin,
245 BasicBlock::const_iterator End,
247 // Lower all of the non-terminator instructions. If a call is emitted
248 // as a tail call, cease emitting nodes for this block. Terminators
249 // are handled below.
250 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
253 // Make sure the root of the DAG is up-to-date.
254 CurDAG->setRoot(SDB->getControlRoot());
256 // Final step, emit the lowered DAG as machine code.
257 BB = CodeGenAndEmitDAG(BB);
258 HadTailCall = SDB->HasTailCall;
264 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
265 /// nodes from the worklist.
266 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
267 SmallVector<SDNode*, 128> &Worklist;
268 SmallPtrSet<SDNode*, 128> &InWorklist;
270 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
271 SmallPtrSet<SDNode*, 128> &inwl)
272 : Worklist(wl), InWorklist(inwl) {}
274 void RemoveFromWorklist(SDNode *N) {
275 if (!InWorklist.erase(N)) return;
277 SmallVector<SDNode*, 128>::iterator I =
278 std::find(Worklist.begin(), Worklist.end(), N);
279 assert(I != Worklist.end() && "Not in worklist");
281 *I = Worklist.back();
285 virtual void NodeDeleted(SDNode *N, SDNode *E) {
286 RemoveFromWorklist(N);
289 virtual void NodeUpdated(SDNode *N) {
295 /// TrivialTruncElim - Eliminate some trivial nops that can result from
296 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
297 static bool TrivialTruncElim(SDValue Op,
298 TargetLowering::TargetLoweringOpt &TLO) {
299 SDValue N0 = Op.getOperand(0);
300 EVT VT = Op.getValueType();
301 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
302 N0.getOpcode() == ISD::SIGN_EXTEND ||
303 N0.getOpcode() == ISD::ANY_EXTEND) &&
304 N0.getOperand(0).getValueType() == VT) {
305 return TLO.CombineTo(Op, N0.getOperand(0));
310 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
311 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
312 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
313 void SelectionDAGISel::ShrinkDemandedOps() {
314 SmallVector<SDNode*, 128> Worklist;
315 SmallPtrSet<SDNode*, 128> InWorklist;
317 // Add all the dag nodes to the worklist.
318 Worklist.reserve(CurDAG->allnodes_size());
319 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
320 E = CurDAG->allnodes_end(); I != E; ++I) {
321 Worklist.push_back(I);
322 InWorklist.insert(I);
325 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true);
326 while (!Worklist.empty()) {
327 SDNode *N = Worklist.pop_back_val();
330 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
331 // Deleting this node may make its operands dead, add them to the worklist
332 // if they aren't already there.
333 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
334 if (InWorklist.insert(N->getOperand(i).getNode()))
335 Worklist.push_back(N->getOperand(i).getNode());
337 CurDAG->DeleteNode(N);
341 // Run ShrinkDemandedOp on scalar binary operations.
342 if (N->getNumValues() != 1 ||
343 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
346 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
347 APInt Demanded = APInt::getAllOnesValue(BitWidth);
348 APInt KnownZero, KnownOne;
349 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
350 KnownZero, KnownOne, TLO) &&
351 (N->getOpcode() != ISD::TRUNCATE ||
352 !TrivialTruncElim(SDValue(N, 0), TLO)))
356 assert(!InWorklist.count(N) && "Already in worklist");
357 Worklist.push_back(N);
358 InWorklist.insert(N);
360 // Replace the old value with the new one.
361 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
362 TLO.Old.getNode()->dump(CurDAG);
363 errs() << "\nWith: ";
364 TLO.New.getNode()->dump(CurDAG);
367 if (InWorklist.insert(TLO.New.getNode()))
368 Worklist.push_back(TLO.New.getNode());
370 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
371 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
373 if (!TLO.Old.getNode()->use_empty()) continue;
375 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
377 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
378 if (OpNode->hasOneUse()) {
379 // Add OpNode to the end of the list to revisit.
380 DeadNodes.RemoveFromWorklist(OpNode);
381 Worklist.push_back(OpNode);
382 InWorklist.insert(OpNode);
386 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
387 CurDAG->DeleteNode(TLO.Old.getNode());
391 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
392 SmallPtrSet<SDNode*, 128> VisitedNodes;
393 SmallVector<SDNode*, 128> Worklist;
395 Worklist.push_back(CurDAG->getRoot().getNode());
402 SDNode *N = Worklist.pop_back_val();
404 // If we've already seen this node, ignore it.
405 if (!VisitedNodes.insert(N))
408 // Otherwise, add all chain operands to the worklist.
409 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
410 if (N->getOperand(i).getValueType() == MVT::Other)
411 Worklist.push_back(N->getOperand(i).getNode());
413 // If this is a CopyToReg with a vreg dest, process it.
414 if (N->getOpcode() != ISD::CopyToReg)
417 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
418 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
421 // Ignore non-scalar or non-integer values.
422 SDValue Src = N->getOperand(2);
423 EVT SrcVT = Src.getValueType();
424 if (!SrcVT.isInteger() || SrcVT.isVector())
427 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
428 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
429 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
431 // Only install this information if it tells us something.
432 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
433 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
434 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
435 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
436 FunctionLoweringInfo::LiveOutInfo &LOI =
437 FuncInfo->LiveOutRegInfo[DestReg];
438 LOI.NumSignBits = NumSignBits;
439 LOI.KnownOne = KnownOne;
440 LOI.KnownZero = KnownZero;
442 } while (!Worklist.empty());
445 MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
446 std::string GroupName;
447 if (TimePassesIsEnabled)
448 GroupName = "Instruction Selection and Scheduling";
449 std::string BlockName;
450 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
451 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
453 BlockName = MF->getFunction()->getNameStr() + ":" +
454 BB->getBasicBlock()->getNameStr();
456 DEBUG(dbgs() << "Initial selection DAG:\n");
457 DEBUG(CurDAG->dump());
459 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
461 // Run the DAG combiner in pre-legalize mode.
462 if (TimePassesIsEnabled) {
463 NamedRegionTimer T("DAG Combining 1", GroupName);
464 CurDAG->Combine(Unrestricted, *AA, OptLevel);
466 CurDAG->Combine(Unrestricted, *AA, OptLevel);
469 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
470 DEBUG(CurDAG->dump());
472 // Second step, hack on the DAG until it only uses operations and types that
473 // the target supports.
474 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
478 if (TimePassesIsEnabled) {
479 NamedRegionTimer T("Type Legalization", GroupName);
480 Changed = CurDAG->LegalizeTypes();
482 Changed = CurDAG->LegalizeTypes();
485 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
486 DEBUG(CurDAG->dump());
489 if (ViewDAGCombineLT)
490 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
492 // Run the DAG combiner in post-type-legalize mode.
493 if (TimePassesIsEnabled) {
494 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
495 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
497 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
500 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
501 DEBUG(CurDAG->dump());
504 if (TimePassesIsEnabled) {
505 NamedRegionTimer T("Vector Legalization", GroupName);
506 Changed = CurDAG->LegalizeVectors();
508 Changed = CurDAG->LegalizeVectors();
512 if (TimePassesIsEnabled) {
513 NamedRegionTimer T("Type Legalization 2", GroupName);
514 CurDAG->LegalizeTypes();
516 CurDAG->LegalizeTypes();
519 if (ViewDAGCombineLT)
520 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
522 // Run the DAG combiner in post-type-legalize mode.
523 if (TimePassesIsEnabled) {
524 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
525 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
527 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
530 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
531 DEBUG(CurDAG->dump());
534 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
536 if (TimePassesIsEnabled) {
537 NamedRegionTimer T("DAG Legalization", GroupName);
538 CurDAG->Legalize(OptLevel);
540 CurDAG->Legalize(OptLevel);
543 DEBUG(dbgs() << "Legalized selection DAG:\n");
544 DEBUG(CurDAG->dump());
546 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
548 // Run the DAG combiner in post-legalize mode.
549 if (TimePassesIsEnabled) {
550 NamedRegionTimer T("DAG Combining 2", GroupName);
551 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
553 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
556 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
557 DEBUG(CurDAG->dump());
559 if (OptLevel != CodeGenOpt::None) {
561 ComputeLiveOutVRegInfo();
564 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
566 // Third, instruction select all of the operations to machine code, adding the
567 // code to the MachineBasicBlock.
568 if (TimePassesIsEnabled) {
569 NamedRegionTimer T("Instruction Selection", GroupName);
570 DoInstructionSelection();
572 DoInstructionSelection();
575 DEBUG(dbgs() << "Selected selection DAG:\n");
576 DEBUG(CurDAG->dump());
578 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
580 // Schedule machine code.
581 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
582 if (TimePassesIsEnabled) {
583 NamedRegionTimer T("Instruction Scheduling", GroupName);
584 Scheduler->Run(CurDAG, BB, BB->end());
586 Scheduler->Run(CurDAG, BB, BB->end());
589 if (ViewSUnitDAGs) Scheduler->viewGraph();
591 // Emit machine code to BB. This can change 'BB' to the last block being
593 if (TimePassesIsEnabled) {
594 NamedRegionTimer T("Instruction Creation", GroupName);
595 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
597 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
600 // Free the scheduler state.
601 if (TimePassesIsEnabled) {
602 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
611 void SelectionDAGISel::DoInstructionSelection() {
612 DEBUG(errs() << "===== Instruction selection begins:\n");
616 // Select target instructions for the DAG.
618 // Number all nodes with a topological order and set DAGSize.
619 DAGSize = CurDAG->AssignTopologicalOrder();
621 // Create a dummy node (which is not added to allnodes), that adds
622 // a reference to the root node, preventing it from being deleted,
623 // and tracking any changes of the root.
624 HandleSDNode Dummy(CurDAG->getRoot());
625 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
628 // The AllNodes list is now topological-sorted. Visit the
629 // nodes by starting at the end of the list (the root of the
630 // graph) and preceding back toward the beginning (the entry
632 while (ISelPosition != CurDAG->allnodes_begin()) {
633 SDNode *Node = --ISelPosition;
634 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
635 // but there are currently some corner cases that it misses. Also, this
636 // makes it theoretically possible to disable the DAGCombiner.
637 if (Node->use_empty())
640 SDNode *ResNode = Select(Node);
642 // FIXME: This is pretty gross. 'Select' should be changed to not return
643 // anything at all and this code should be nuked with a tactical strike.
645 // If node should not be replaced, continue with the next one.
646 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
650 ReplaceUses(Node, ResNode);
652 // If after the replacement this node is not used any more,
653 // remove this dead node.
654 if (Node->use_empty()) { // Don't delete EntryToken, etc.
655 ISelUpdater ISU(ISelPosition);
656 CurDAG->RemoveDeadNode(Node, &ISU);
660 CurDAG->setRoot(Dummy.getValue());
662 DEBUG(errs() << "===== Instruction selection ends:\n");
664 PostprocessISelDAG();
667 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
668 /// do other setup for EH landing-pad blocks.
669 void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
670 // Add a label to mark the beginning of the landing pad. Deletion of the
671 // landing pad can thus be detected via the MachineModuleInfo.
672 MCSymbol *Label = MF->getMMI().addLandingPad(BB);
674 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
675 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
677 // Mark exception register as live in.
678 unsigned Reg = TLI.getExceptionAddressRegister();
679 if (Reg) BB->addLiveIn(Reg);
681 // Mark exception selector register as live in.
682 Reg = TLI.getExceptionSelectorRegister();
683 if (Reg) BB->addLiveIn(Reg);
685 // FIXME: Hack around an exception handling flaw (PR1508): the personality
686 // function and list of typeids logically belong to the invoke (or, if you
687 // like, the basic block containing the invoke), and need to be associated
688 // with it in the dwarf exception handling tables. Currently however the
689 // information is provided by an intrinsic (eh.selector) that can be moved
690 // to unexpected places by the optimizers: if the unwind edge is critical,
691 // then breaking it can result in the intrinsics being in the successor of
692 // the landing pad, not the landing pad itself. This results
693 // in exceptions not being caught because no typeids are associated with
694 // the invoke. This may not be the only way things can go wrong, but it
695 // is the only way we try to work around for the moment.
696 const BasicBlock *LLVMBB = BB->getBasicBlock();
697 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
699 if (Br && Br->isUnconditional()) { // Critical edge?
700 BasicBlock::const_iterator I, E;
701 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
702 if (isa<EHSelectorInst>(I))
706 // No catch info found - try to extract some from the successor.
707 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
711 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
712 // Initialize the Fast-ISel state, if needed.
713 FastISel *FastIS = 0;
715 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
716 FuncInfo->StaticAllocaMap,
717 FuncInfo->PHINodesToUpdate
719 , FuncInfo->CatchInfoLost
723 // Iterate over all basic blocks in the function.
724 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
725 const BasicBlock *LLVMBB = &*I;
726 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
728 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
729 BasicBlock::const_iterator const End = LLVMBB->end();
730 BasicBlock::const_iterator BI = Begin;
732 // Lower any arguments needed in this block if this is the entry block.
733 bool SuppressFastISel = false;
734 if (LLVMBB == &Fn.getEntryBlock()) {
735 LowerArguments(LLVMBB);
737 // If any of the arguments has the byval attribute, forgo
738 // fast-isel in the entry block.
741 for (Function::const_arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
743 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
744 if (EnableFastISelVerbose || EnableFastISelAbort)
745 dbgs() << "FastISel skips entry block due to byval argument\n";
746 SuppressFastISel = true;
752 // Setup an EH landing-pad block.
753 if (BB->isLandingPad())
754 PrepareEHLandingPad(BB);
756 // Before doing SelectionDAG ISel, see if FastISel has been requested.
757 if (FastIS && !SuppressFastISel) {
758 // Emit code for any incoming arguments. This must happen before
759 // beginning FastISel on the entry block.
760 if (LLVMBB == &Fn.getEntryBlock()) {
761 CurDAG->setRoot(SDB->getControlRoot());
762 BB = CodeGenAndEmitDAG(BB);
765 FastIS->startNewBlock(BB);
766 // Do FastISel on as many instructions as possible.
767 for (; BI != End; ++BI) {
768 // Try to select the instruction with FastISel.
769 if (FastIS->SelectInstruction(BI))
772 // Then handle certain instructions as single-LLVM-Instruction blocks.
773 if (isa<CallInst>(BI)) {
774 ++NumFastIselFailures;
775 if (EnableFastISelVerbose || EnableFastISelAbort) {
776 dbgs() << "FastISel missed call: ";
780 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
781 unsigned &R = FuncInfo->ValueMap[BI];
783 R = FuncInfo->CreateRegForValue(BI);
786 bool HadTailCall = false;
787 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall);
789 // If the call was emitted as a tail call, we're done with the block.
795 // If the instruction was codegen'd with multiple blocks,
796 // inform the FastISel object where to resume inserting.
797 FastIS->setCurrentBlock(BB);
801 // Otherwise, give up on FastISel for the rest of the block.
802 // For now, be a little lenient about non-branch terminators.
803 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
804 ++NumFastIselFailures;
805 if (EnableFastISelVerbose || EnableFastISelAbort) {
806 dbgs() << "FastISel miss: ";
809 if (EnableFastISelAbort)
810 // The "fast" selector couldn't handle something and bailed.
811 // For the purpose of debugging, just abort.
812 llvm_unreachable("FastISel didn't select the entire block");
818 // Run SelectionDAG instruction selection on the remainder of the block
819 // not handled by FastISel. If FastISel is not run, this is the entire
823 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall);
826 FinishBasicBlock(BB);
827 FuncInfo->PHINodesToUpdate.clear();
834 SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
836 DEBUG(dbgs() << "Target-post-processed machine code:\n");
839 DEBUG(dbgs() << "Total amount of phi nodes to update: "
840 << FuncInfo->PHINodesToUpdate.size() << "\n");
841 DEBUG(for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
842 dbgs() << "Node " << i << " : ("
843 << FuncInfo->PHINodesToUpdate[i].first
844 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
846 // Next, now that we know what the last MBB the LLVM BB expanded is, update
847 // PHI nodes in successors.
848 if (SDB->SwitchCases.empty() &&
849 SDB->JTCases.empty() &&
850 SDB->BitTestCases.empty()) {
851 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
852 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
853 assert(PHI->isPHI() &&
854 "This is not a machine PHI node that we are updating!");
855 if (!BB->isSuccessor(PHI->getParent()))
858 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
859 PHI->addOperand(MachineOperand::CreateMBB(BB));
864 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
865 // Lower header first, if it wasn't already lowered
866 if (!SDB->BitTestCases[i].Emitted) {
867 // Set the current basic block to the mbb we wish to insert the code into
868 BB = SDB->BitTestCases[i].Parent;
870 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
871 CurDAG->setRoot(SDB->getRoot());
872 BB = CodeGenAndEmitDAG(BB);
876 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
877 // Set the current basic block to the mbb we wish to insert the code into
878 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
881 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
882 SDB->BitTestCases[i].Reg,
883 SDB->BitTestCases[i].Cases[j],
886 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
887 SDB->BitTestCases[i].Reg,
888 SDB->BitTestCases[i].Cases[j],
892 CurDAG->setRoot(SDB->getRoot());
893 BB = CodeGenAndEmitDAG(BB);
898 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
900 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
901 MachineBasicBlock *PHIBB = PHI->getParent();
902 assert(PHI->isPHI() &&
903 "This is not a machine PHI node that we are updating!");
904 // This is "default" BB. We have two jumps to it. From "header" BB and
905 // from last "case" BB.
906 if (PHIBB == SDB->BitTestCases[i].Default) {
907 PHI->addOperand(MachineOperand::
908 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
910 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
911 PHI->addOperand(MachineOperand::
912 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
914 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
917 // One of "cases" BB.
918 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
920 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
921 if (cBB->isSuccessor(PHIBB)) {
922 PHI->addOperand(MachineOperand::
923 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
925 PHI->addOperand(MachineOperand::CreateMBB(cBB));
930 SDB->BitTestCases.clear();
932 // If the JumpTable record is filled in, then we need to emit a jump table.
933 // Updating the PHI nodes is tricky in this case, since we need to determine
934 // whether the PHI is a successor of the range check MBB or the jump table MBB
935 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
936 // Lower header first, if it wasn't already lowered
937 if (!SDB->JTCases[i].first.Emitted) {
938 // Set the current basic block to the mbb we wish to insert the code into
939 BB = SDB->JTCases[i].first.HeaderBB;
941 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
943 CurDAG->setRoot(SDB->getRoot());
944 BB = CodeGenAndEmitDAG(BB);
948 // Set the current basic block to the mbb we wish to insert the code into
949 BB = SDB->JTCases[i].second.MBB;
951 SDB->visitJumpTable(SDB->JTCases[i].second);
952 CurDAG->setRoot(SDB->getRoot());
953 BB = CodeGenAndEmitDAG(BB);
957 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
959 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
960 MachineBasicBlock *PHIBB = PHI->getParent();
961 assert(PHI->isPHI() &&
962 "This is not a machine PHI node that we are updating!");
963 // "default" BB. We can go there only from header BB.
964 if (PHIBB == SDB->JTCases[i].second.Default) {
966 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
969 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
971 // JT BB. Just iterate over successors here
972 if (BB->isSuccessor(PHIBB)) {
974 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
976 PHI->addOperand(MachineOperand::CreateMBB(BB));
980 SDB->JTCases.clear();
982 // If the switch block involved a branch to one of the actual successors, we
983 // need to update PHI nodes in that block.
984 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
985 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
986 assert(PHI->isPHI() &&
987 "This is not a machine PHI node that we are updating!");
988 if (BB->isSuccessor(PHI->getParent())) {
990 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
991 PHI->addOperand(MachineOperand::CreateMBB(BB));
995 // If we generated any switch lowering information, build and codegen any
996 // additional DAGs necessary.
997 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
998 // Set the current basic block to the mbb we wish to insert the code into
999 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1002 SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
1003 CurDAG->setRoot(SDB->getRoot());
1004 BB = CodeGenAndEmitDAG(BB);
1006 // Handle any PHI nodes in successors of this chunk, as if we were coming
1007 // from the original BB before switch expansion. Note that PHI nodes can
1008 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1009 // handle them the right number of times.
1010 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1011 // If new BB's are created during scheduling, the edges may have been
1012 // updated. That is, the edge from ThisBB to BB may have been split and
1013 // BB's predecessor is now another block.
1014 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1015 SDB->EdgeMapping.find(BB);
1016 if (EI != SDB->EdgeMapping.end())
1017 ThisBB = EI->second;
1019 // BB may have been removed from the CFG if a branch was constant folded.
1020 if (ThisBB->isSuccessor(BB)) {
1021 for (MachineBasicBlock::iterator Phi = BB->begin();
1022 Phi != BB->end() && Phi->isPHI();
1024 // This value for this PHI node is recorded in PHINodesToUpdate.
1025 for (unsigned pn = 0; ; ++pn) {
1026 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1027 "Didn't find PHI entry!");
1028 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1029 Phi->addOperand(MachineOperand::
1030 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1032 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1039 // Don't process RHS if same block as LHS.
1040 if (BB == SDB->SwitchCases[i].FalseBB)
1041 SDB->SwitchCases[i].FalseBB = 0;
1043 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1044 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1045 SDB->SwitchCases[i].FalseBB = 0;
1047 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1050 SDB->SwitchCases.clear();
1054 /// Create the scheduler. If a specific scheduler was specified
1055 /// via the SchedulerRegistry, use it, otherwise select the
1056 /// one preferred by the target.
1058 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1059 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1063 RegisterScheduler::setDefault(Ctor);
1066 return Ctor(this, OptLevel);
1069 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1070 return new ScheduleHazardRecognizer();
1073 //===----------------------------------------------------------------------===//
1074 // Helper functions used by the generated instruction selector.
1075 //===----------------------------------------------------------------------===//
1076 // Calls to these methods are generated by tblgen.
1078 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1079 /// the dag combiner simplified the 255, we still want to match. RHS is the
1080 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1081 /// specified in the .td file (e.g. 255).
1082 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1083 int64_t DesiredMaskS) const {
1084 const APInt &ActualMask = RHS->getAPIntValue();
1085 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1087 // If the actual mask exactly matches, success!
1088 if (ActualMask == DesiredMask)
1091 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1092 if (ActualMask.intersects(~DesiredMask))
1095 // Otherwise, the DAG Combiner may have proven that the value coming in is
1096 // either already zero or is not demanded. Check for known zero input bits.
1097 APInt NeededMask = DesiredMask & ~ActualMask;
1098 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1101 // TODO: check to see if missing bits are just not demanded.
1103 // Otherwise, this pattern doesn't match.
1107 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1108 /// the dag combiner simplified the 255, we still want to match. RHS is the
1109 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1110 /// specified in the .td file (e.g. 255).
1111 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1112 int64_t DesiredMaskS) const {
1113 const APInt &ActualMask = RHS->getAPIntValue();
1114 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1116 // If the actual mask exactly matches, success!
1117 if (ActualMask == DesiredMask)
1120 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1121 if (ActualMask.intersects(~DesiredMask))
1124 // Otherwise, the DAG Combiner may have proven that the value coming in is
1125 // either already zero or is not demanded. Check for known zero input bits.
1126 APInt NeededMask = DesiredMask & ~ActualMask;
1128 APInt KnownZero, KnownOne;
1129 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1131 // If all the missing bits in the or are already known to be set, match!
1132 if ((NeededMask & KnownOne) == NeededMask)
1135 // TODO: check to see if missing bits are just not demanded.
1137 // Otherwise, this pattern doesn't match.
1142 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1143 /// by tblgen. Others should not call it.
1144 void SelectionDAGISel::
1145 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1146 std::vector<SDValue> InOps;
1147 std::swap(InOps, Ops);
1149 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1150 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1151 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1153 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1154 if (InOps[e-1].getValueType() == MVT::Flag)
1155 --e; // Don't process a flag operand if it is here.
1158 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1159 if (!InlineAsm::isMemKind(Flags)) {
1160 // Just skip over this operand, copying the operands verbatim.
1161 Ops.insert(Ops.end(), InOps.begin()+i,
1162 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1163 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1165 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1166 "Memory operand with multiple values?");
1167 // Otherwise, this is a memory operand. Ask the target to select it.
1168 std::vector<SDValue> SelOps;
1169 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1170 report_fatal_error("Could not match memory address. Inline asm"
1173 // Add this to the output node.
1175 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1176 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1177 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1182 // Add the flag input back if present.
1183 if (e != InOps.size())
1184 Ops.push_back(InOps.back());
1187 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1190 static SDNode *findFlagUse(SDNode *N) {
1191 unsigned FlagResNo = N->getNumValues()-1;
1192 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1193 SDUse &Use = I.getUse();
1194 if (Use.getResNo() == FlagResNo)
1195 return Use.getUser();
1200 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1201 /// This function recursively traverses up the operand chain, ignoring
1203 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1204 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1205 bool IgnoreChains) {
1206 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1207 // greater than all of its (recursive) operands. If we scan to a point where
1208 // 'use' is smaller than the node we're scanning for, then we know we will
1211 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1212 // happen because we scan down to newly selected nodes in the case of flag
1214 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1217 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1218 // won't fail if we scan it again.
1219 if (!Visited.insert(Use))
1222 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1223 // Ignore chain uses, they are validated by HandleMergeInputChains.
1224 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1227 SDNode *N = Use->getOperand(i).getNode();
1229 if (Use == ImmedUse || Use == Root)
1230 continue; // We are not looking for immediate use.
1235 // Traverse up the operand chain.
1236 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1242 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1243 /// operand node N of U during instruction selection that starts at Root.
1244 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1245 SDNode *Root) const {
1246 if (OptLevel == CodeGenOpt::None) return false;
1247 return N.hasOneUse();
1250 /// IsLegalToFold - Returns true if the specific operand node N of
1251 /// U can be folded during instruction selection that starts at Root.
1252 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1253 CodeGenOpt::Level OptLevel,
1254 bool IgnoreChains) {
1255 if (OptLevel == CodeGenOpt::None) return false;
1257 // If Root use can somehow reach N through a path that that doesn't contain
1258 // U then folding N would create a cycle. e.g. In the following
1259 // diagram, Root can reach N through X. If N is folded into into Root, then
1260 // X is both a predecessor and a successor of U.
1271 // * indicates nodes to be folded together.
1273 // If Root produces a flag, then it gets (even more) interesting. Since it
1274 // will be "glued" together with its flag use in the scheduler, we need to
1275 // check if it might reach N.
1294 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1295 // (call it Fold), then X is a predecessor of FU and a successor of
1296 // Fold. But since Fold and FU are flagged together, this will create
1297 // a cycle in the scheduling graph.
1299 // If the node has flags, walk down the graph to the "lowest" node in the
1301 EVT VT = Root->getValueType(Root->getNumValues()-1);
1302 while (VT == MVT::Flag) {
1303 SDNode *FU = findFlagUse(Root);
1307 VT = Root->getValueType(Root->getNumValues()-1);
1309 // If our query node has a flag result with a use, we've walked up it. If
1310 // the user (which has already been selected) has a chain or indirectly uses
1311 // the chain, our WalkChainUsers predicate will not consider it. Because of
1312 // this, we cannot ignore chains in this predicate.
1313 IgnoreChains = false;
1317 SmallPtrSet<SDNode*, 16> Visited;
1318 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1321 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1322 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1323 SelectInlineAsmMemoryOperands(Ops);
1325 std::vector<EVT> VTs;
1326 VTs.push_back(MVT::Other);
1327 VTs.push_back(MVT::Flag);
1328 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1329 VTs, &Ops[0], Ops.size());
1331 return New.getNode();
1334 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1335 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1338 /// GetVBR - decode a vbr encoding whose top bit is set.
1339 ALWAYS_INLINE static uint64_t
1340 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1341 assert(Val >= 128 && "Not a VBR");
1342 Val &= 127; // Remove first vbr bit.
1347 NextBits = MatcherTable[Idx++];
1348 Val |= (NextBits&127) << Shift;
1350 } while (NextBits & 128);
1356 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1357 /// interior flag and chain results to use the new flag and chain results.
1358 void SelectionDAGISel::
1359 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1360 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1362 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1363 bool isMorphNodeTo) {
1364 SmallVector<SDNode*, 4> NowDeadNodes;
1366 ISelUpdater ISU(ISelPosition);
1368 // Now that all the normal results are replaced, we replace the chain and
1369 // flag results if present.
1370 if (!ChainNodesMatched.empty()) {
1371 assert(InputChain.getNode() != 0 &&
1372 "Matched input chains but didn't produce a chain");
1373 // Loop over all of the nodes we matched that produced a chain result.
1374 // Replace all the chain results with the final chain we ended up with.
1375 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1376 SDNode *ChainNode = ChainNodesMatched[i];
1378 // If this node was already deleted, don't look at it.
1379 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1382 // Don't replace the results of the root node if we're doing a
1384 if (ChainNode == NodeToMatch && isMorphNodeTo)
1387 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1388 if (ChainVal.getValueType() == MVT::Flag)
1389 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1390 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1391 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1393 // If the node became dead and we haven't already seen it, delete it.
1394 if (ChainNode->use_empty() &&
1395 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1396 NowDeadNodes.push_back(ChainNode);
1400 // If the result produces a flag, update any flag results in the matched
1401 // pattern with the flag result.
1402 if (InputFlag.getNode() != 0) {
1403 // Handle any interior nodes explicitly marked.
1404 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1405 SDNode *FRN = FlagResultNodesMatched[i];
1407 // If this node was already deleted, don't look at it.
1408 if (FRN->getOpcode() == ISD::DELETED_NODE)
1411 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1412 "Doesn't have a flag result");
1413 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1416 // If the node became dead and we haven't already seen it, delete it.
1417 if (FRN->use_empty() &&
1418 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1419 NowDeadNodes.push_back(FRN);
1423 if (!NowDeadNodes.empty())
1424 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1426 DEBUG(errs() << "ISEL: Match complete!\n");
1432 CR_LeadsToInteriorNode
1435 /// WalkChainUsers - Walk down the users of the specified chained node that is
1436 /// part of the pattern we're matching, looking at all of the users we find.
1437 /// This determines whether something is an interior node, whether we have a
1438 /// non-pattern node in between two pattern nodes (which prevent folding because
1439 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1440 /// between pattern nodes (in which case the TF becomes part of the pattern).
1442 /// The walk we do here is guaranteed to be small because we quickly get down to
1443 /// already selected nodes "below" us.
1445 WalkChainUsers(SDNode *ChainedNode,
1446 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1447 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1448 ChainResult Result = CR_Simple;
1450 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1451 E = ChainedNode->use_end(); UI != E; ++UI) {
1452 // Make sure the use is of the chain, not some other value we produce.
1453 if (UI.getUse().getValueType() != MVT::Other) continue;
1457 // If we see an already-selected machine node, then we've gone beyond the
1458 // pattern that we're selecting down into the already selected chunk of the
1460 if (User->isMachineOpcode() ||
1461 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1464 if (User->getOpcode() == ISD::CopyToReg ||
1465 User->getOpcode() == ISD::CopyFromReg ||
1466 User->getOpcode() == ISD::INLINEASM ||
1467 User->getOpcode() == ISD::EH_LABEL) {
1468 // If their node ID got reset to -1 then they've already been selected.
1469 // Treat them like a MachineOpcode.
1470 if (User->getNodeId() == -1)
1474 // If we have a TokenFactor, we handle it specially.
1475 if (User->getOpcode() != ISD::TokenFactor) {
1476 // If the node isn't a token factor and isn't part of our pattern, then it
1477 // must be a random chained node in between two nodes we're selecting.
1478 // This happens when we have something like:
1483 // Because we structurally match the load/store as a read/modify/write,
1484 // but the call is chained between them. We cannot fold in this case
1485 // because it would induce a cycle in the graph.
1486 if (!std::count(ChainedNodesInPattern.begin(),
1487 ChainedNodesInPattern.end(), User))
1488 return CR_InducesCycle;
1490 // Otherwise we found a node that is part of our pattern. For example in:
1494 // This would happen when we're scanning down from the load and see the
1495 // store as a user. Record that there is a use of ChainedNode that is
1496 // part of the pattern and keep scanning uses.
1497 Result = CR_LeadsToInteriorNode;
1498 InteriorChainedNodes.push_back(User);
1502 // If we found a TokenFactor, there are two cases to consider: first if the
1503 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1504 // uses of the TF are in our pattern) we just want to ignore it. Second,
1505 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1511 // | \ DAG's like cheese
1514 // [TokenFactor] [Op]
1521 // In this case, the TokenFactor becomes part of our match and we rewrite it
1522 // as a new TokenFactor.
1524 // To distinguish these two cases, do a recursive walk down the uses.
1525 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1527 // If the uses of the TokenFactor are just already-selected nodes, ignore
1528 // it, it is "below" our pattern.
1530 case CR_InducesCycle:
1531 // If the uses of the TokenFactor lead to nodes that are not part of our
1532 // pattern that are not selected, folding would turn this into a cycle,
1534 return CR_InducesCycle;
1535 case CR_LeadsToInteriorNode:
1536 break; // Otherwise, keep processing.
1539 // Okay, we know we're in the interesting interior case. The TokenFactor
1540 // is now going to be considered part of the pattern so that we rewrite its
1541 // uses (it may have uses that are not part of the pattern) with the
1542 // ultimate chain result of the generated code. We will also add its chain
1543 // inputs as inputs to the ultimate TokenFactor we create.
1544 Result = CR_LeadsToInteriorNode;
1545 ChainedNodesInPattern.push_back(User);
1546 InteriorChainedNodes.push_back(User);
1553 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1554 /// operation for when the pattern matched at least one node with a chains. The
1555 /// input vector contains a list of all of the chained nodes that we match. We
1556 /// must determine if this is a valid thing to cover (i.e. matching it won't
1557 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1558 /// be used as the input node chain for the generated nodes.
1560 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1561 SelectionDAG *CurDAG) {
1562 // Walk all of the chained nodes we've matched, recursively scanning down the
1563 // users of the chain result. This adds any TokenFactor nodes that are caught
1564 // in between chained nodes to the chained and interior nodes list.
1565 SmallVector<SDNode*, 3> InteriorChainedNodes;
1566 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1567 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1568 InteriorChainedNodes) == CR_InducesCycle)
1569 return SDValue(); // Would induce a cycle.
1572 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1573 // that we are interested in. Form our input TokenFactor node.
1574 SmallVector<SDValue, 3> InputChains;
1575 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1576 // Add the input chain of this node to the InputChains list (which will be
1577 // the operands of the generated TokenFactor) if it's not an interior node.
1578 SDNode *N = ChainNodesMatched[i];
1579 if (N->getOpcode() != ISD::TokenFactor) {
1580 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1583 // Otherwise, add the input chain.
1584 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1585 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1586 InputChains.push_back(InChain);
1590 // If we have a token factor, we want to add all inputs of the token factor
1591 // that are not part of the pattern we're matching.
1592 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1593 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1594 N->getOperand(op).getNode()))
1595 InputChains.push_back(N->getOperand(op));
1600 if (InputChains.size() == 1)
1601 return InputChains[0];
1602 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1603 MVT::Other, &InputChains[0], InputChains.size());
1606 /// MorphNode - Handle morphing a node in place for the selector.
1607 SDNode *SelectionDAGISel::
1608 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1609 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1610 // It is possible we're using MorphNodeTo to replace a node with no
1611 // normal results with one that has a normal result (or we could be
1612 // adding a chain) and the input could have flags and chains as well.
1613 // In this case we need to shift the operands down.
1614 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1615 // than the old isel though.
1616 int OldFlagResultNo = -1, OldChainResultNo = -1;
1618 unsigned NTMNumResults = Node->getNumValues();
1619 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1620 OldFlagResultNo = NTMNumResults-1;
1621 if (NTMNumResults != 1 &&
1622 Node->getValueType(NTMNumResults-2) == MVT::Other)
1623 OldChainResultNo = NTMNumResults-2;
1624 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1625 OldChainResultNo = NTMNumResults-1;
1627 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1628 // that this deletes operands of the old node that become dead.
1629 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1631 // MorphNodeTo can operate in two ways: if an existing node with the
1632 // specified operands exists, it can just return it. Otherwise, it
1633 // updates the node in place to have the requested operands.
1635 // If we updated the node in place, reset the node ID. To the isel,
1636 // this should be just like a newly allocated machine node.
1640 unsigned ResNumResults = Res->getNumValues();
1641 // Move the flag if needed.
1642 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1643 (unsigned)OldFlagResultNo != ResNumResults-1)
1644 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1645 SDValue(Res, ResNumResults-1));
1647 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1650 // Move the chain reference if needed.
1651 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1652 (unsigned)OldChainResultNo != ResNumResults-1)
1653 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1654 SDValue(Res, ResNumResults-1));
1656 // Otherwise, no replacement happened because the node already exists. Replace
1657 // Uses of the old node with the new one.
1659 CurDAG->ReplaceAllUsesWith(Node, Res);
1664 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1665 ALWAYS_INLINE static bool
1666 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1667 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1668 // Accept if it is exactly the same as a previously recorded node.
1669 unsigned RecNo = MatcherTable[MatcherIndex++];
1670 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1671 return N == RecordedNodes[RecNo];
1674 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1675 ALWAYS_INLINE static bool
1676 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1677 SelectionDAGISel &SDISel) {
1678 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1681 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1682 ALWAYS_INLINE static bool
1683 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1684 SelectionDAGISel &SDISel, SDNode *N) {
1685 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1688 ALWAYS_INLINE static bool
1689 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1691 uint16_t Opc = MatcherTable[MatcherIndex++];
1692 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1693 return N->getOpcode() == Opc;
1696 ALWAYS_INLINE static bool
1697 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1698 SDValue N, const TargetLowering &TLI) {
1699 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1700 if (N.getValueType() == VT) return true;
1702 // Handle the case when VT is iPTR.
1703 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1706 ALWAYS_INLINE static bool
1707 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1708 SDValue N, const TargetLowering &TLI,
1710 if (ChildNo >= N.getNumOperands())
1711 return false; // Match fails if out of range child #.
1712 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1716 ALWAYS_INLINE static bool
1717 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1719 return cast<CondCodeSDNode>(N)->get() ==
1720 (ISD::CondCode)MatcherTable[MatcherIndex++];
1723 ALWAYS_INLINE static bool
1724 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1725 SDValue N, const TargetLowering &TLI) {
1726 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1727 if (cast<VTSDNode>(N)->getVT() == VT)
1730 // Handle the case when VT is iPTR.
1731 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1734 ALWAYS_INLINE static bool
1735 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1737 int64_t Val = MatcherTable[MatcherIndex++];
1739 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1741 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1742 return C != 0 && C->getSExtValue() == Val;
1745 ALWAYS_INLINE static bool
1746 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1747 SDValue N, SelectionDAGISel &SDISel) {
1748 int64_t Val = MatcherTable[MatcherIndex++];
1750 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1752 if (N->getOpcode() != ISD::AND) return false;
1754 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1755 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1758 ALWAYS_INLINE static bool
1759 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1760 SDValue N, SelectionDAGISel &SDISel) {
1761 int64_t Val = MatcherTable[MatcherIndex++];
1763 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1765 if (N->getOpcode() != ISD::OR) return false;
1767 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1768 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1771 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1772 /// scope, evaluate the current node. If the current predicate is known to
1773 /// fail, set Result=true and return anything. If the current predicate is
1774 /// known to pass, set Result=false and return the MatcherIndex to continue
1775 /// with. If the current predicate is unknown, set Result=false and return the
1776 /// MatcherIndex to continue with.
1777 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1778 unsigned Index, SDValue N,
1779 bool &Result, SelectionDAGISel &SDISel,
1780 SmallVectorImpl<SDValue> &RecordedNodes){
1781 switch (Table[Index++]) {
1784 return Index-1; // Could not evaluate this predicate.
1785 case SelectionDAGISel::OPC_CheckSame:
1786 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1788 case SelectionDAGISel::OPC_CheckPatternPredicate:
1789 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1791 case SelectionDAGISel::OPC_CheckPredicate:
1792 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1794 case SelectionDAGISel::OPC_CheckOpcode:
1795 Result = !::CheckOpcode(Table, Index, N.getNode());
1797 case SelectionDAGISel::OPC_CheckType:
1798 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1800 case SelectionDAGISel::OPC_CheckChild0Type:
1801 case SelectionDAGISel::OPC_CheckChild1Type:
1802 case SelectionDAGISel::OPC_CheckChild2Type:
1803 case SelectionDAGISel::OPC_CheckChild3Type:
1804 case SelectionDAGISel::OPC_CheckChild4Type:
1805 case SelectionDAGISel::OPC_CheckChild5Type:
1806 case SelectionDAGISel::OPC_CheckChild6Type:
1807 case SelectionDAGISel::OPC_CheckChild7Type:
1808 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1809 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1811 case SelectionDAGISel::OPC_CheckCondCode:
1812 Result = !::CheckCondCode(Table, Index, N);
1814 case SelectionDAGISel::OPC_CheckValueType:
1815 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1817 case SelectionDAGISel::OPC_CheckInteger:
1818 Result = !::CheckInteger(Table, Index, N);
1820 case SelectionDAGISel::OPC_CheckAndImm:
1821 Result = !::CheckAndImm(Table, Index, N, SDISel);
1823 case SelectionDAGISel::OPC_CheckOrImm:
1824 Result = !::CheckOrImm(Table, Index, N, SDISel);
1832 /// FailIndex - If this match fails, this is the index to continue with.
1835 /// NodeStack - The node stack when the scope was formed.
1836 SmallVector<SDValue, 4> NodeStack;
1838 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1839 unsigned NumRecordedNodes;
1841 /// NumMatchedMemRefs - The number of matched memref entries.
1842 unsigned NumMatchedMemRefs;
1844 /// InputChain/InputFlag - The current chain/flag
1845 SDValue InputChain, InputFlag;
1847 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1848 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1853 SDNode *SelectionDAGISel::
1854 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1855 unsigned TableSize) {
1856 // FIXME: Should these even be selected? Handle these cases in the caller?
1857 switch (NodeToMatch->getOpcode()) {
1860 case ISD::EntryToken: // These nodes remain the same.
1861 case ISD::BasicBlock:
1863 //case ISD::VALUETYPE:
1864 //case ISD::CONDCODE:
1865 case ISD::HANDLENODE:
1866 case ISD::MDNODE_SDNODE:
1867 case ISD::TargetConstant:
1868 case ISD::TargetConstantFP:
1869 case ISD::TargetConstantPool:
1870 case ISD::TargetFrameIndex:
1871 case ISD::TargetExternalSymbol:
1872 case ISD::TargetBlockAddress:
1873 case ISD::TargetJumpTable:
1874 case ISD::TargetGlobalTLSAddress:
1875 case ISD::TargetGlobalAddress:
1876 case ISD::TokenFactor:
1877 case ISD::CopyFromReg:
1878 case ISD::CopyToReg:
1880 NodeToMatch->setNodeId(-1); // Mark selected.
1882 case ISD::AssertSext:
1883 case ISD::AssertZext:
1884 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1885 NodeToMatch->getOperand(0));
1887 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1888 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1891 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1893 // Set up the node stack with NodeToMatch as the only node on the stack.
1894 SmallVector<SDValue, 8> NodeStack;
1895 SDValue N = SDValue(NodeToMatch, 0);
1896 NodeStack.push_back(N);
1898 // MatchScopes - Scopes used when matching, if a match failure happens, this
1899 // indicates where to continue checking.
1900 SmallVector<MatchScope, 8> MatchScopes;
1902 // RecordedNodes - This is the set of nodes that have been recorded by the
1904 SmallVector<SDValue, 8> RecordedNodes;
1906 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1908 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1910 // These are the current input chain and flag for use when generating nodes.
1911 // Various Emit operations change these. For example, emitting a copytoreg
1912 // uses and updates these.
1913 SDValue InputChain, InputFlag;
1915 // ChainNodesMatched - If a pattern matches nodes that have input/output
1916 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1917 // which ones they are. The result is captured into this list so that we can
1918 // update the chain results when the pattern is complete.
1919 SmallVector<SDNode*, 3> ChainNodesMatched;
1920 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1922 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1923 NodeToMatch->dump(CurDAG);
1926 // Determine where to start the interpreter. Normally we start at opcode #0,
1927 // but if the state machine starts with an OPC_SwitchOpcode, then we
1928 // accelerate the first lookup (which is guaranteed to be hot) with the
1929 // OpcodeOffset table.
1930 unsigned MatcherIndex = 0;
1932 if (!OpcodeOffset.empty()) {
1933 // Already computed the OpcodeOffset table, just index into it.
1934 if (N.getOpcode() < OpcodeOffset.size())
1935 MatcherIndex = OpcodeOffset[N.getOpcode()];
1936 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1938 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1939 // Otherwise, the table isn't computed, but the state machine does start
1940 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1941 // is the first time we're selecting an instruction.
1944 // Get the size of this case.
1945 unsigned CaseSize = MatcherTable[Idx++];
1947 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1948 if (CaseSize == 0) break;
1950 // Get the opcode, add the index to the table.
1951 uint16_t Opc = MatcherTable[Idx++];
1952 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1953 if (Opc >= OpcodeOffset.size())
1954 OpcodeOffset.resize((Opc+1)*2);
1955 OpcodeOffset[Opc] = Idx;
1959 // Okay, do the lookup for the first opcode.
1960 if (N.getOpcode() < OpcodeOffset.size())
1961 MatcherIndex = OpcodeOffset[N.getOpcode()];
1965 assert(MatcherIndex < TableSize && "Invalid index");
1967 unsigned CurrentOpcodeIndex = MatcherIndex;
1969 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1972 // Okay, the semantics of this operation are that we should push a scope
1973 // then evaluate the first child. However, pushing a scope only to have
1974 // the first check fail (which then pops it) is inefficient. If we can
1975 // determine immediately that the first check (or first several) will
1976 // immediately fail, don't even bother pushing a scope for them.
1980 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1981 if (NumToSkip & 128)
1982 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1983 // Found the end of the scope with no match.
1984 if (NumToSkip == 0) {
1989 FailIndex = MatcherIndex+NumToSkip;
1991 unsigned MatcherIndexOfPredicate = MatcherIndex;
1992 (void)MatcherIndexOfPredicate; // silence warning.
1994 // If we can't evaluate this predicate without pushing a scope (e.g. if
1995 // it is a 'MoveParent') or if the predicate succeeds on this node, we
1996 // push the scope and evaluate the full predicate chain.
1998 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
1999 Result, *this, RecordedNodes);
2003 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2004 << "index " << MatcherIndexOfPredicate
2005 << ", continuing at " << FailIndex << "\n");
2006 ++NumDAGIselRetries;
2008 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2009 // move to the next case.
2010 MatcherIndex = FailIndex;
2013 // If the whole scope failed to match, bail.
2014 if (FailIndex == 0) break;
2016 // Push a MatchScope which indicates where to go if the first child fails
2018 MatchScope NewEntry;
2019 NewEntry.FailIndex = FailIndex;
2020 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2021 NewEntry.NumRecordedNodes = RecordedNodes.size();
2022 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2023 NewEntry.InputChain = InputChain;
2024 NewEntry.InputFlag = InputFlag;
2025 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2026 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2027 MatchScopes.push_back(NewEntry);
2030 case OPC_RecordNode:
2031 // Remember this node, it may end up being an operand in the pattern.
2032 RecordedNodes.push_back(N);
2035 case OPC_RecordChild0: case OPC_RecordChild1:
2036 case OPC_RecordChild2: case OPC_RecordChild3:
2037 case OPC_RecordChild4: case OPC_RecordChild5:
2038 case OPC_RecordChild6: case OPC_RecordChild7: {
2039 unsigned ChildNo = Opcode-OPC_RecordChild0;
2040 if (ChildNo >= N.getNumOperands())
2041 break; // Match fails if out of range child #.
2043 RecordedNodes.push_back(N->getOperand(ChildNo));
2046 case OPC_RecordMemRef:
2047 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2050 case OPC_CaptureFlagInput:
2051 // If the current node has an input flag, capture it in InputFlag.
2052 if (N->getNumOperands() != 0 &&
2053 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2054 InputFlag = N->getOperand(N->getNumOperands()-1);
2057 case OPC_MoveChild: {
2058 unsigned ChildNo = MatcherTable[MatcherIndex++];
2059 if (ChildNo >= N.getNumOperands())
2060 break; // Match fails if out of range child #.
2061 N = N.getOperand(ChildNo);
2062 NodeStack.push_back(N);
2066 case OPC_MoveParent:
2067 // Pop the current node off the NodeStack.
2068 NodeStack.pop_back();
2069 assert(!NodeStack.empty() && "Node stack imbalance!");
2070 N = NodeStack.back();
2074 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2076 case OPC_CheckPatternPredicate:
2077 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2079 case OPC_CheckPredicate:
2080 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2084 case OPC_CheckComplexPat: {
2085 unsigned CPNum = MatcherTable[MatcherIndex++];
2086 unsigned RecNo = MatcherTable[MatcherIndex++];
2087 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2088 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2093 case OPC_CheckOpcode:
2094 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2098 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2101 case OPC_SwitchOpcode: {
2102 unsigned CurNodeOpcode = N.getOpcode();
2103 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2106 // Get the size of this case.
2107 CaseSize = MatcherTable[MatcherIndex++];
2109 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2110 if (CaseSize == 0) break;
2112 uint16_t Opc = MatcherTable[MatcherIndex++];
2113 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2115 // If the opcode matches, then we will execute this case.
2116 if (CurNodeOpcode == Opc)
2119 // Otherwise, skip over this case.
2120 MatcherIndex += CaseSize;
2123 // If no cases matched, bail out.
2124 if (CaseSize == 0) break;
2126 // Otherwise, execute the case we found.
2127 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2128 << " to " << MatcherIndex << "\n");
2132 case OPC_SwitchType: {
2133 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2134 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2137 // Get the size of this case.
2138 CaseSize = MatcherTable[MatcherIndex++];
2140 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2141 if (CaseSize == 0) break;
2143 MVT::SimpleValueType CaseVT =
2144 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2145 if (CaseVT == MVT::iPTR)
2146 CaseVT = TLI.getPointerTy().SimpleTy;
2148 // If the VT matches, then we will execute this case.
2149 if (CurNodeVT == CaseVT)
2152 // Otherwise, skip over this case.
2153 MatcherIndex += CaseSize;
2156 // If no cases matched, bail out.
2157 if (CaseSize == 0) break;
2159 // Otherwise, execute the case we found.
2160 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2161 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2164 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2165 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2166 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2167 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2168 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2169 Opcode-OPC_CheckChild0Type))
2172 case OPC_CheckCondCode:
2173 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2175 case OPC_CheckValueType:
2176 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2178 case OPC_CheckInteger:
2179 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2181 case OPC_CheckAndImm:
2182 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2184 case OPC_CheckOrImm:
2185 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2188 case OPC_CheckFoldableChainNode: {
2189 assert(NodeStack.size() != 1 && "No parent node");
2190 // Verify that all intermediate nodes between the root and this one have
2192 bool HasMultipleUses = false;
2193 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2194 if (!NodeStack[i].hasOneUse()) {
2195 HasMultipleUses = true;
2198 if (HasMultipleUses) break;
2200 // Check to see that the target thinks this is profitable to fold and that
2201 // we can fold it without inducing cycles in the graph.
2202 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2204 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2205 NodeToMatch, OptLevel,
2206 true/*We validate our own chains*/))
2211 case OPC_EmitInteger: {
2212 MVT::SimpleValueType VT =
2213 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2214 int64_t Val = MatcherTable[MatcherIndex++];
2216 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2217 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2220 case OPC_EmitRegister: {
2221 MVT::SimpleValueType VT =
2222 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2223 unsigned RegNo = MatcherTable[MatcherIndex++];
2224 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2228 case OPC_EmitConvertToTarget: {
2229 // Convert from IMM/FPIMM to target version.
2230 unsigned RecNo = MatcherTable[MatcherIndex++];
2231 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2232 SDValue Imm = RecordedNodes[RecNo];
2234 if (Imm->getOpcode() == ISD::Constant) {
2235 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2236 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2237 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2238 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2239 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2242 RecordedNodes.push_back(Imm);
2246 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2247 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2248 // These are space-optimized forms of OPC_EmitMergeInputChains.
2249 assert(InputChain.getNode() == 0 &&
2250 "EmitMergeInputChains should be the first chain producing node");
2251 assert(ChainNodesMatched.empty() &&
2252 "Should only have one EmitMergeInputChains per match");
2254 // Read all of the chained nodes.
2255 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2256 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2257 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2259 // FIXME: What if other value results of the node have uses not matched
2261 if (ChainNodesMatched.back() != NodeToMatch &&
2262 !RecordedNodes[RecNo].hasOneUse()) {
2263 ChainNodesMatched.clear();
2267 // Merge the input chains if they are not intra-pattern references.
2268 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2270 if (InputChain.getNode() == 0)
2271 break; // Failed to merge.
2275 case OPC_EmitMergeInputChains: {
2276 assert(InputChain.getNode() == 0 &&
2277 "EmitMergeInputChains should be the first chain producing node");
2278 // This node gets a list of nodes we matched in the input that have
2279 // chains. We want to token factor all of the input chains to these nodes
2280 // together. However, if any of the input chains is actually one of the
2281 // nodes matched in this pattern, then we have an intra-match reference.
2282 // Ignore these because the newly token factored chain should not refer to
2284 unsigned NumChains = MatcherTable[MatcherIndex++];
2285 assert(NumChains != 0 && "Can't TF zero chains");
2287 assert(ChainNodesMatched.empty() &&
2288 "Should only have one EmitMergeInputChains per match");
2290 // Read all of the chained nodes.
2291 for (unsigned i = 0; i != NumChains; ++i) {
2292 unsigned RecNo = MatcherTable[MatcherIndex++];
2293 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2294 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2296 // FIXME: What if other value results of the node have uses not matched
2298 if (ChainNodesMatched.back() != NodeToMatch &&
2299 !RecordedNodes[RecNo].hasOneUse()) {
2300 ChainNodesMatched.clear();
2305 // If the inner loop broke out, the match fails.
2306 if (ChainNodesMatched.empty())
2309 // Merge the input chains if they are not intra-pattern references.
2310 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2312 if (InputChain.getNode() == 0)
2313 break; // Failed to merge.
2318 case OPC_EmitCopyToReg: {
2319 unsigned RecNo = MatcherTable[MatcherIndex++];
2320 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2321 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2323 if (InputChain.getNode() == 0)
2324 InputChain = CurDAG->getEntryNode();
2326 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2327 DestPhysReg, RecordedNodes[RecNo],
2330 InputFlag = InputChain.getValue(1);
2334 case OPC_EmitNodeXForm: {
2335 unsigned XFormNo = MatcherTable[MatcherIndex++];
2336 unsigned RecNo = MatcherTable[MatcherIndex++];
2337 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2338 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2343 case OPC_MorphNodeTo: {
2344 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2345 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2346 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2347 // Get the result VT list.
2348 unsigned NumVTs = MatcherTable[MatcherIndex++];
2349 SmallVector<EVT, 4> VTs;
2350 for (unsigned i = 0; i != NumVTs; ++i) {
2351 MVT::SimpleValueType VT =
2352 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2353 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2357 if (EmitNodeInfo & OPFL_Chain)
2358 VTs.push_back(MVT::Other);
2359 if (EmitNodeInfo & OPFL_FlagOutput)
2360 VTs.push_back(MVT::Flag);
2362 // This is hot code, so optimize the two most common cases of 1 and 2
2365 if (VTs.size() == 1)
2366 VTList = CurDAG->getVTList(VTs[0]);
2367 else if (VTs.size() == 2)
2368 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2370 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2372 // Get the operand list.
2373 unsigned NumOps = MatcherTable[MatcherIndex++];
2374 SmallVector<SDValue, 8> Ops;
2375 for (unsigned i = 0; i != NumOps; ++i) {
2376 unsigned RecNo = MatcherTable[MatcherIndex++];
2378 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2380 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2381 Ops.push_back(RecordedNodes[RecNo]);
2384 // If there are variadic operands to add, handle them now.
2385 if (EmitNodeInfo & OPFL_VariadicInfo) {
2386 // Determine the start index to copy from.
2387 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2388 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2389 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2390 "Invalid variadic node");
2391 // Copy all of the variadic operands, not including a potential flag
2393 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2395 SDValue V = NodeToMatch->getOperand(i);
2396 if (V.getValueType() == MVT::Flag) break;
2401 // If this has chain/flag inputs, add them.
2402 if (EmitNodeInfo & OPFL_Chain)
2403 Ops.push_back(InputChain);
2404 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2405 Ops.push_back(InputFlag);
2409 if (Opcode != OPC_MorphNodeTo) {
2410 // If this is a normal EmitNode command, just create the new node and
2411 // add the results to the RecordedNodes list.
2412 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2413 VTList, Ops.data(), Ops.size());
2415 // Add all the non-flag/non-chain results to the RecordedNodes list.
2416 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2417 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2418 RecordedNodes.push_back(SDValue(Res, i));
2422 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2426 // If the node had chain/flag results, update our notion of the current
2428 if (EmitNodeInfo & OPFL_FlagOutput) {
2429 InputFlag = SDValue(Res, VTs.size()-1);
2430 if (EmitNodeInfo & OPFL_Chain)
2431 InputChain = SDValue(Res, VTs.size()-2);
2432 } else if (EmitNodeInfo & OPFL_Chain)
2433 InputChain = SDValue(Res, VTs.size()-1);
2435 // If the OPFL_MemRefs flag is set on this node, slap all of the
2436 // accumulated memrefs onto it.
2438 // FIXME: This is vastly incorrect for patterns with multiple outputs
2439 // instructions that access memory and for ComplexPatterns that match
2441 if (EmitNodeInfo & OPFL_MemRefs) {
2442 MachineSDNode::mmo_iterator MemRefs =
2443 MF->allocateMemRefsArray(MatchedMemRefs.size());
2444 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2445 cast<MachineSDNode>(Res)
2446 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2450 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2451 << " node: "; Res->dump(CurDAG); errs() << "\n");
2453 // If this was a MorphNodeTo then we're completely done!
2454 if (Opcode == OPC_MorphNodeTo) {
2455 // Update chain and flag uses.
2456 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2457 InputFlag, FlagResultNodesMatched, true);
2464 case OPC_MarkFlagResults: {
2465 unsigned NumNodes = MatcherTable[MatcherIndex++];
2467 // Read and remember all the flag-result nodes.
2468 for (unsigned i = 0; i != NumNodes; ++i) {
2469 unsigned RecNo = MatcherTable[MatcherIndex++];
2471 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2473 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2474 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2479 case OPC_CompleteMatch: {
2480 // The match has been completed, and any new nodes (if any) have been
2481 // created. Patch up references to the matched dag to use the newly
2483 unsigned NumResults = MatcherTable[MatcherIndex++];
2485 for (unsigned i = 0; i != NumResults; ++i) {
2486 unsigned ResSlot = MatcherTable[MatcherIndex++];
2488 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2490 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2491 SDValue Res = RecordedNodes[ResSlot];
2493 assert(i < NodeToMatch->getNumValues() &&
2494 NodeToMatch->getValueType(i) != MVT::Other &&
2495 NodeToMatch->getValueType(i) != MVT::Flag &&
2496 "Invalid number of results to complete!");
2497 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2498 NodeToMatch->getValueType(i) == MVT::iPTR ||
2499 Res.getValueType() == MVT::iPTR ||
2500 NodeToMatch->getValueType(i).getSizeInBits() ==
2501 Res.getValueType().getSizeInBits()) &&
2502 "invalid replacement");
2503 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2506 // If the root node defines a flag, add it to the flag nodes to update
2508 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2509 FlagResultNodesMatched.push_back(NodeToMatch);
2511 // Update chain and flag uses.
2512 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2513 InputFlag, FlagResultNodesMatched, false);
2515 assert(NodeToMatch->use_empty() &&
2516 "Didn't replace all uses of the node?");
2518 // FIXME: We just return here, which interacts correctly with SelectRoot
2519 // above. We should fix this to not return an SDNode* anymore.
2524 // If the code reached this point, then the match failed. See if there is
2525 // another child to try in the current 'Scope', otherwise pop it until we
2526 // find a case to check.
2527 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2528 ++NumDAGIselRetries;
2530 if (MatchScopes.empty()) {
2531 CannotYetSelect(NodeToMatch);
2535 // Restore the interpreter state back to the point where the scope was
2537 MatchScope &LastScope = MatchScopes.back();
2538 RecordedNodes.resize(LastScope.NumRecordedNodes);
2540 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2541 N = NodeStack.back();
2543 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2544 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2545 MatcherIndex = LastScope.FailIndex;
2547 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2549 InputChain = LastScope.InputChain;
2550 InputFlag = LastScope.InputFlag;
2551 if (!LastScope.HasChainNodesMatched)
2552 ChainNodesMatched.clear();
2553 if (!LastScope.HasFlagResultNodesMatched)
2554 FlagResultNodesMatched.clear();
2556 // Check to see what the offset is at the new MatcherIndex. If it is zero
2557 // we have reached the end of this scope, otherwise we have another child
2558 // in the current scope to try.
2559 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2560 if (NumToSkip & 128)
2561 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2563 // If we have another child in this scope to match, update FailIndex and
2565 if (NumToSkip != 0) {
2566 LastScope.FailIndex = MatcherIndex+NumToSkip;
2570 // End of this scope, pop it and try the next child in the containing
2572 MatchScopes.pop_back();
2579 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2581 raw_string_ostream Msg(msg);
2582 Msg << "Cannot yet select: ";
2584 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2585 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2586 N->getOpcode() != ISD::INTRINSIC_VOID) {
2587 N->printrFull(Msg, CurDAG);
2589 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2591 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2592 if (iid < Intrinsic::num_intrinsics)
2593 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2594 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2595 Msg << "target intrinsic %" << TII->getName(iid);
2597 Msg << "unknown intrinsic #" << iid;
2599 report_fatal_error(Msg.str());
2602 char SelectionDAGISel::ID = 0;