1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/DebugInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetIntrinsicInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/ADT/PostOrderIterator.h"
54 #include "llvm/ADT/Statistic.h"
58 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
59 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
60 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
61 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
62 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
65 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
66 cl::desc("Enable verbose messages in the \"fast\" "
67 "instruction selector"));
69 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
70 cl::desc("Enable abort calls when \"fast\" instruction fails"));
74 cl::desc("use Machine Branch Probability Info"),
75 cl::init(true), cl::Hidden);
79 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
80 cl::desc("Pop up a window to show dags before the first "
83 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize types"));
86 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before legalize"));
89 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
90 cl::desc("Pop up a window to show dags before the second "
93 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
94 cl::desc("Pop up a window to show dags before the post legalize types"
95 " dag combine pass"));
97 ViewISelDAGs("view-isel-dags", cl::Hidden,
98 cl::desc("Pop up a window to show isel dags as they are selected"));
100 ViewSchedDAGs("view-sched-dags", cl::Hidden,
101 cl::desc("Pop up a window to show sched dags as they are processed"));
103 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
104 cl::desc("Pop up a window to show SUnit dags after they are processed"));
106 static const bool ViewDAGCombine1 = false,
107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
108 ViewDAGCombine2 = false,
109 ViewDAGCombineLT = false,
110 ViewISelDAGs = false, ViewSchedDAGs = false,
111 ViewSUnitDAGs = false;
114 //===---------------------------------------------------------------------===//
116 /// RegisterScheduler class - Track the registration of instruction schedulers.
118 //===---------------------------------------------------------------------===//
119 MachinePassRegistry RegisterScheduler::Registry;
121 //===---------------------------------------------------------------------===//
123 /// ISHeuristic command line option for instruction schedulers.
125 //===---------------------------------------------------------------------===//
126 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
127 RegisterPassParser<RegisterScheduler> >
128 ISHeuristic("pre-RA-sched",
129 cl::init(&createDefaultScheduler),
130 cl::desc("Instruction schedulers available (before register"
133 static RegisterScheduler
134 defaultListDAGScheduler("default", "Best scheduler for the target",
135 createDefaultScheduler);
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
142 CodeGenOpt::Level OptLevel) {
143 const TargetLowering &TLI = IS->getTargetLowering();
145 if (OptLevel == CodeGenOpt::None)
146 return createSourceListDAGScheduler(IS, OptLevel);
147 if (TLI.getSchedulingPreference() == Sched::Latency)
148 return createTDListDAGScheduler(IS, OptLevel);
149 if (TLI.getSchedulingPreference() == Sched::RegPressure)
150 return createBURRListDAGScheduler(IS, OptLevel);
151 if (TLI.getSchedulingPreference() == Sched::Hybrid)
152 return createHybridListDAGScheduler(IS, OptLevel);
153 assert(TLI.getSchedulingPreference() == Sched::ILP &&
154 "Unknown sched type!");
155 return createILPListDAGScheduler(IS, OptLevel);
159 // EmitInstrWithCustomInserter - This method should be implemented by targets
160 // that mark instructions with the 'usesCustomInserter' flag. These
161 // instructions are special in various ways, which require special support to
162 // insert. The specified MachineInstr is created but not inserted into any
163 // basic blocks, and this method is called to expand it into a sequence of
164 // instructions, potentially also creating new basic blocks and control flow.
165 // When new basic blocks are inserted and the edges from MBB to its successors
166 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
169 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
170 MachineBasicBlock *MBB) const {
172 dbgs() << "If a target marks an instruction with "
173 "'usesCustomInserter', it must implement "
174 "TargetLowering::EmitInstrWithCustomInserter!";
180 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
181 SDNode *Node) const {
182 assert(!MI->getDesc().hasPostISelHook() &&
183 "If a target marks an instruction with 'hasPostISelHook', "
184 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
187 //===----------------------------------------------------------------------===//
188 // SelectionDAGISel code
189 //===----------------------------------------------------------------------===//
191 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
192 CodeGenOpt::Level OL) :
193 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
194 FuncInfo(new FunctionLoweringInfo(TLI)),
195 CurDAG(new SelectionDAG(tm)),
196 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
200 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
201 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
202 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
205 SelectionDAGISel::~SelectionDAGISel() {
211 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
212 AU.addRequired<AliasAnalysis>();
213 AU.addPreserved<AliasAnalysis>();
214 AU.addRequired<GCModuleInfo>();
215 AU.addPreserved<GCModuleInfo>();
216 if (UseMBPI && OptLevel != CodeGenOpt::None)
217 AU.addRequired<BranchProbabilityInfo>();
218 MachineFunctionPass::getAnalysisUsage(AU);
221 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
222 /// may trap on it. In this case we have to split the edge so that the path
223 /// through the predecessor block that doesn't go to the phi block doesn't
224 /// execute the possibly trapping instruction.
226 /// This is required for correctness, so it must be done at -O0.
228 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
229 // Loop for blocks with phi nodes.
230 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
231 PHINode *PN = dyn_cast<PHINode>(BB->begin());
232 if (PN == 0) continue;
235 // For each block with a PHI node, check to see if any of the input values
236 // are potentially trapping constant expressions. Constant expressions are
237 // the only potentially trapping value that can occur as the argument to a
239 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
240 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
241 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
242 if (CE == 0 || !CE->canTrap()) continue;
244 // The only case we have to worry about is when the edge is critical.
245 // Since this block has a PHI Node, we assume it has multiple input
246 // edges: check to see if the pred has multiple successors.
247 BasicBlock *Pred = PN->getIncomingBlock(i);
248 if (Pred->getTerminator()->getNumSuccessors() == 1)
251 // Okay, we have to split this edge.
252 SplitCriticalEdge(Pred->getTerminator(),
253 GetSuccessorNumber(Pred, BB), SDISel, true);
259 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
260 // Do some sanity-checking on the command-line options.
261 assert((!EnableFastISelVerbose || EnableFastISel) &&
262 "-fast-isel-verbose requires -fast-isel");
263 assert((!EnableFastISelAbort || EnableFastISel) &&
264 "-fast-isel-abort requires -fast-isel");
266 const Function &Fn = *mf.getFunction();
267 const TargetInstrInfo &TII = *TM.getInstrInfo();
268 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
271 RegInfo = &MF->getRegInfo();
272 AA = &getAnalysis<AliasAnalysis>();
273 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
275 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
277 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
280 FuncInfo->set(Fn, *MF);
282 if (UseMBPI && OptLevel != CodeGenOpt::None)
283 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
289 SelectAllBasicBlocks(Fn);
291 // If the first basic block in the function has live ins that need to be
292 // copied into vregs, emit the copies into the top of the block before
293 // emitting the code for the block.
294 MachineBasicBlock *EntryMBB = MF->begin();
295 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
297 DenseMap<unsigned, unsigned> LiveInMap;
298 if (!FuncInfo->ArgDbgValues.empty())
299 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
300 E = RegInfo->livein_end(); LI != E; ++LI)
302 LiveInMap.insert(std::make_pair(LI->first, LI->second));
304 // Insert DBG_VALUE instructions for function arguments to the entry block.
305 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
306 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
307 unsigned Reg = MI->getOperand(0).getReg();
308 if (TargetRegisterInfo::isPhysicalRegister(Reg))
309 EntryMBB->insert(EntryMBB->begin(), MI);
311 MachineInstr *Def = RegInfo->getVRegDef(Reg);
312 MachineBasicBlock::iterator InsertPos = Def;
313 // FIXME: VR def may not be in entry block.
314 Def->getParent()->insert(llvm::next(InsertPos), MI);
317 // If Reg is live-in then update debug info to track its copy in a vreg.
318 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
319 if (LDI != LiveInMap.end()) {
320 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
321 MachineBasicBlock::iterator InsertPos = Def;
322 const MDNode *Variable =
323 MI->getOperand(MI->getNumOperands()-1).getMetadata();
324 unsigned Offset = MI->getOperand(1).getImm();
325 // Def is never a terminator here, so it is ok to increment InsertPos.
326 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
327 TII.get(TargetOpcode::DBG_VALUE))
328 .addReg(LDI->second, RegState::Debug)
329 .addImm(Offset).addMetadata(Variable);
331 // If this vreg is directly copied into an exported register then
332 // that COPY instructions also need DBG_VALUE, if it is the only
333 // user of LDI->second.
334 MachineInstr *CopyUseMI = NULL;
335 for (MachineRegisterInfo::use_iterator
336 UI = RegInfo->use_begin(LDI->second);
337 MachineInstr *UseMI = UI.skipInstruction();) {
338 if (UseMI->isDebugValue()) continue;
339 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
340 CopyUseMI = UseMI; continue;
342 // Otherwise this is another use or second copy use.
343 CopyUseMI = NULL; break;
346 MachineInstr *NewMI =
347 BuildMI(*MF, CopyUseMI->getDebugLoc(),
348 TII.get(TargetOpcode::DBG_VALUE))
349 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
350 .addImm(Offset).addMetadata(Variable);
351 EntryMBB->insertAfter(CopyUseMI, NewMI);
356 // Determine if there are any calls in this machine function.
357 MachineFrameInfo *MFI = MF->getFrameInfo();
358 if (!MFI->hasCalls()) {
359 for (MachineFunction::const_iterator
360 I = MF->begin(), E = MF->end(); I != E; ++I) {
361 const MachineBasicBlock *MBB = I;
362 for (MachineBasicBlock::const_iterator
363 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
364 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
366 if ((MCID.isCall() && !MCID.isReturn()) ||
367 II->isStackAligningInlineAsm()) {
368 MFI->setHasCalls(true);
376 // Determine if there is a call to setjmp in the machine function.
377 MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice());
379 // Replace forward-declared registers with the registers containing
380 // the desired value.
381 MachineRegisterInfo &MRI = MF->getRegInfo();
382 for (DenseMap<unsigned, unsigned>::iterator
383 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
385 unsigned From = I->first;
386 unsigned To = I->second;
387 // If To is also scheduled to be replaced, find what its ultimate
390 DenseMap<unsigned, unsigned>::iterator J =
391 FuncInfo->RegFixups.find(To);
396 MRI.replaceRegWith(From, To);
399 // Release function-specific state. SDB and CurDAG are already cleared
406 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
407 BasicBlock::const_iterator End,
409 // Lower all of the non-terminator instructions. If a call is emitted
410 // as a tail call, cease emitting nodes for this block. Terminators
411 // are handled below.
412 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
415 // Make sure the root of the DAG is up-to-date.
416 CurDAG->setRoot(SDB->getControlRoot());
417 HadTailCall = SDB->HasTailCall;
420 // Final step, emit the lowered DAG as machine code.
424 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
425 SmallPtrSet<SDNode*, 128> VisitedNodes;
426 SmallVector<SDNode*, 128> Worklist;
428 Worklist.push_back(CurDAG->getRoot().getNode());
435 SDNode *N = Worklist.pop_back_val();
437 // If we've already seen this node, ignore it.
438 if (!VisitedNodes.insert(N))
441 // Otherwise, add all chain operands to the worklist.
442 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
443 if (N->getOperand(i).getValueType() == MVT::Other)
444 Worklist.push_back(N->getOperand(i).getNode());
446 // If this is a CopyToReg with a vreg dest, process it.
447 if (N->getOpcode() != ISD::CopyToReg)
450 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
451 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
454 // Ignore non-scalar or non-integer values.
455 SDValue Src = N->getOperand(2);
456 EVT SrcVT = Src.getValueType();
457 if (!SrcVT.isInteger() || SrcVT.isVector())
460 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
461 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
462 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
463 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
464 } while (!Worklist.empty());
467 void SelectionDAGISel::CodeGenAndEmitDAG() {
468 std::string GroupName;
469 if (TimePassesIsEnabled)
470 GroupName = "Instruction Selection and Scheduling";
471 std::string BlockName;
472 int BlockNumber = -1;
475 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
476 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
480 BlockNumber = FuncInfo->MBB->getNumber();
481 BlockName = MF->getFunction()->getNameStr() + ":" +
482 FuncInfo->MBB->getBasicBlock()->getNameStr();
484 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
485 << " '" << BlockName << "'\n"; CurDAG->dump());
487 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
489 // Run the DAG combiner in pre-legalize mode.
491 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
492 CurDAG->Combine(Unrestricted, *AA, OptLevel);
495 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
496 << " '" << BlockName << "'\n"; CurDAG->dump());
498 // Second step, hack on the DAG until it only uses operations and types that
499 // the target supports.
500 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
505 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
506 Changed = CurDAG->LegalizeTypes();
509 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
510 << " '" << BlockName << "'\n"; CurDAG->dump());
513 if (ViewDAGCombineLT)
514 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
516 // Run the DAG combiner in post-type-legalize mode.
518 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
519 TimePassesIsEnabled);
520 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
523 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
524 << " '" << BlockName << "'\n"; CurDAG->dump());
528 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
529 Changed = CurDAG->LegalizeVectors();
534 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
535 CurDAG->LegalizeTypes();
538 if (ViewDAGCombineLT)
539 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
541 // Run the DAG combiner in post-type-legalize mode.
543 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
544 TimePassesIsEnabled);
545 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
548 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
549 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
552 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
555 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
559 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
560 << " '" << BlockName << "'\n"; CurDAG->dump());
562 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
564 // Run the DAG combiner in post-legalize mode.
566 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
567 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
570 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
571 << " '" << BlockName << "'\n"; CurDAG->dump());
573 if (OptLevel != CodeGenOpt::None)
574 ComputeLiveOutVRegInfo();
576 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
578 // Third, instruction select all of the operations to machine code, adding the
579 // code to the MachineBasicBlock.
581 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
582 DoInstructionSelection();
585 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
586 << " '" << BlockName << "'\n"; CurDAG->dump());
588 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
590 // Schedule machine code.
591 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
593 NamedRegionTimer T("Instruction Scheduling", GroupName,
594 TimePassesIsEnabled);
595 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
598 if (ViewSUnitDAGs) Scheduler->viewGraph();
600 // Emit machine code to BB. This can change 'BB' to the last block being
602 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
604 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
606 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
607 FuncInfo->InsertPt = Scheduler->InsertPos;
610 // If the block was split, make sure we update any references that are used to
611 // update PHI nodes later on.
612 if (FirstMBB != LastMBB)
613 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
615 // Free the scheduler state.
617 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
618 TimePassesIsEnabled);
622 // Free the SelectionDAG state, now that we're finished with it.
626 void SelectionDAGISel::DoInstructionSelection() {
627 DEBUG(errs() << "===== Instruction selection begins: BB#"
628 << FuncInfo->MBB->getNumber()
629 << " '" << FuncInfo->MBB->getName() << "'\n");
633 // Select target instructions for the DAG.
635 // Number all nodes with a topological order and set DAGSize.
636 DAGSize = CurDAG->AssignTopologicalOrder();
638 // Create a dummy node (which is not added to allnodes), that adds
639 // a reference to the root node, preventing it from being deleted,
640 // and tracking any changes of the root.
641 HandleSDNode Dummy(CurDAG->getRoot());
642 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
645 // The AllNodes list is now topological-sorted. Visit the
646 // nodes by starting at the end of the list (the root of the
647 // graph) and preceding back toward the beginning (the entry
649 while (ISelPosition != CurDAG->allnodes_begin()) {
650 SDNode *Node = --ISelPosition;
651 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
652 // but there are currently some corner cases that it misses. Also, this
653 // makes it theoretically possible to disable the DAGCombiner.
654 if (Node->use_empty())
657 SDNode *ResNode = Select(Node);
659 // FIXME: This is pretty gross. 'Select' should be changed to not return
660 // anything at all and this code should be nuked with a tactical strike.
662 // If node should not be replaced, continue with the next one.
663 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
667 ReplaceUses(Node, ResNode);
669 // If after the replacement this node is not used any more,
670 // remove this dead node.
671 if (Node->use_empty()) { // Don't delete EntryToken, etc.
672 ISelUpdater ISU(ISelPosition);
673 CurDAG->RemoveDeadNode(Node, &ISU);
677 CurDAG->setRoot(Dummy.getValue());
680 DEBUG(errs() << "===== Instruction selection ends:\n");
682 PostprocessISelDAG();
685 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
686 /// do other setup for EH landing-pad blocks.
687 void SelectionDAGISel::PrepareEHLandingPad() {
688 MachineBasicBlock *MBB = FuncInfo->MBB;
690 // Add a label to mark the beginning of the landing pad. Deletion of the
691 // landing pad can thus be detected via the MachineModuleInfo.
692 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
694 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
695 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
698 // Mark exception register as live in.
699 unsigned Reg = TLI.getExceptionAddressRegister();
700 if (Reg) MBB->addLiveIn(Reg);
702 // Mark exception selector register as live in.
703 Reg = TLI.getExceptionSelectorRegister();
704 if (Reg) MBB->addLiveIn(Reg);
706 // FIXME: Hack around an exception handling flaw (PR1508): the personality
707 // function and list of typeids logically belong to the invoke (or, if you
708 // like, the basic block containing the invoke), and need to be associated
709 // with it in the dwarf exception handling tables. Currently however the
710 // information is provided by an intrinsic (eh.selector) that can be moved
711 // to unexpected places by the optimizers: if the unwind edge is critical,
712 // then breaking it can result in the intrinsics being in the successor of
713 // the landing pad, not the landing pad itself. This results
714 // in exceptions not being caught because no typeids are associated with
715 // the invoke. This may not be the only way things can go wrong, but it
716 // is the only way we try to work around for the moment.
717 const BasicBlock *LLVMBB = MBB->getBasicBlock();
718 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
720 if (Br && Br->isUnconditional()) { // Critical edge?
721 BasicBlock::const_iterator I, E;
722 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
723 if (isa<EHSelectorInst>(I))
727 // No catch info found - try to extract some from the successor.
728 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
732 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
733 /// load into the specified FoldInst. Note that we could have a sequence where
734 /// multiple LLVM IR instructions are folded into the same machineinstr. For
735 /// example we could have:
736 /// A: x = load i32 *P
737 /// B: y = icmp A, 42
740 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
741 /// any other folded instructions) because it is between A and C.
743 /// If we succeed in folding the load into the operation, return true.
745 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
746 const Instruction *FoldInst,
748 // We know that the load has a single use, but don't know what it is. If it
749 // isn't one of the folded instructions, then we can't succeed here. Handle
750 // this by scanning the single-use users of the load until we get to FoldInst.
751 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
753 const Instruction *TheUser = LI->use_back();
754 while (TheUser != FoldInst && // Scan up until we find FoldInst.
755 // Stay in the right block.
756 TheUser->getParent() == FoldInst->getParent() &&
757 --MaxUsers) { // Don't scan too far.
758 // If there are multiple or no uses of this instruction, then bail out.
759 if (!TheUser->hasOneUse())
762 TheUser = TheUser->use_back();
765 // If we didn't find the fold instruction, then we failed to collapse the
767 if (TheUser != FoldInst)
770 // Don't try to fold volatile loads. Target has to deal with alignment
772 if (LI->isVolatile()) return false;
774 // Figure out which vreg this is going into. If there is no assigned vreg yet
775 // then there actually was no reference to it. Perhaps the load is referenced
776 // by a dead instruction.
777 unsigned LoadReg = FastIS->getRegForValue(LI);
781 // Check to see what the uses of this vreg are. If it has no uses, or more
782 // than one use (at the machine instr level) then we can't fold it.
783 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
784 if (RI == RegInfo->reg_end())
787 // See if there is exactly one use of the vreg. If there are multiple uses,
788 // then the instruction got lowered to multiple machine instructions or the
789 // use of the loaded value ended up being multiple operands of the result, in
790 // either case, we can't fold this.
791 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
792 if (PostRI != RegInfo->reg_end())
795 assert(RI.getOperand().isUse() &&
796 "The only use of the vreg must be a use, we haven't emitted the def!");
798 MachineInstr *User = &*RI;
800 // Set the insertion point properly. Folding the load can cause generation of
801 // other random instructions (like sign extends) for addressing modes, make
802 // sure they get inserted in a logical place before the new instruction.
803 FuncInfo->InsertPt = User;
804 FuncInfo->MBB = User->getParent();
806 // Ask the target to try folding the load.
807 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
810 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
811 /// side-effect free and is either dead or folded into a generated instruction.
812 /// Return false if it needs to be emitted.
813 static bool isFoldedOrDeadInstruction(const Instruction *I,
814 FunctionLoweringInfo *FuncInfo) {
815 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
816 !isa<TerminatorInst>(I) && // Terminators aren't folded.
817 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
818 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
819 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
822 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
823 // Initialize the Fast-ISel state, if needed.
824 FastISel *FastIS = 0;
826 FastIS = TLI.createFastISel(*FuncInfo);
828 // Iterate over all basic blocks in the function.
829 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
830 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
831 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
832 const BasicBlock *LLVMBB = *I;
834 if (OptLevel != CodeGenOpt::None) {
835 bool AllPredsVisited = true;
836 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
838 if (!FuncInfo->VisitedBBs.count(*PI)) {
839 AllPredsVisited = false;
844 if (AllPredsVisited) {
845 for (BasicBlock::const_iterator I = LLVMBB->begin();
846 isa<PHINode>(I); ++I)
847 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
849 for (BasicBlock::const_iterator I = LLVMBB->begin();
850 isa<PHINode>(I); ++I)
851 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
854 FuncInfo->VisitedBBs.insert(LLVMBB);
857 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
858 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
860 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
861 BasicBlock::const_iterator const End = LLVMBB->end();
862 BasicBlock::const_iterator BI = End;
864 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
866 // Setup an EH landing-pad block.
867 if (FuncInfo->MBB->isLandingPad())
868 PrepareEHLandingPad();
870 // Lower any arguments needed in this block if this is the entry block.
871 if (LLVMBB == &Fn.getEntryBlock())
872 LowerArguments(LLVMBB);
874 // Before doing SelectionDAG ISel, see if FastISel has been requested.
876 FastIS->startNewBlock();
878 // Emit code for any incoming arguments. This must happen before
879 // beginning FastISel on the entry block.
880 if (LLVMBB == &Fn.getEntryBlock()) {
881 CurDAG->setRoot(SDB->getControlRoot());
885 // If we inserted any instructions at the beginning, make a note of
886 // where they are, so we can be sure to emit subsequent instructions
888 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
889 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
891 FastIS->setLastLocalValue(0);
894 // Do FastISel on as many instructions as possible.
895 for (; BI != Begin; --BI) {
896 const Instruction *Inst = llvm::prior(BI);
898 // If we no longer require this instruction, skip it.
899 if (isFoldedOrDeadInstruction(Inst, FuncInfo))
902 // Bottom-up: reset the insert pos at the top, after any local-value
904 FastIS->recomputeInsertPt();
906 // Try to select the instruction with FastISel.
907 if (FastIS->SelectInstruction(Inst)) {
908 ++NumFastIselSuccess;
909 // If fast isel succeeded, skip over all the folded instructions, and
910 // then see if there is a load right before the selected instructions.
911 // Try to fold the load if so.
912 const Instruction *BeforeInst = Inst;
913 while (BeforeInst != Begin) {
914 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
915 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
918 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
919 BeforeInst->hasOneUse() &&
920 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS))
921 // If we succeeded, don't re-select the load.
922 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
926 // Then handle certain instructions as single-LLVM-Instruction blocks.
927 if (isa<CallInst>(Inst)) {
928 ++NumFastIselFailures;
929 if (EnableFastISelVerbose || EnableFastISelAbort) {
930 dbgs() << "FastISel missed call: ";
934 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
935 unsigned &R = FuncInfo->ValueMap[Inst];
937 R = FuncInfo->CreateRegs(Inst->getType());
940 bool HadTailCall = false;
941 SelectBasicBlock(Inst, BI, HadTailCall);
943 // If the call was emitted as a tail call, we're done with the block.
952 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
953 // Don't abort, and use a different message for terminator misses.
954 ++NumFastIselFailures;
955 if (EnableFastISelVerbose || EnableFastISelAbort) {
956 dbgs() << "FastISel missed terminator: ";
960 ++NumFastIselFailures;
961 if (EnableFastISelVerbose || EnableFastISelAbort) {
962 dbgs() << "FastISel miss: ";
965 if (EnableFastISelAbort)
966 // The "fast" selector couldn't handle something and bailed.
967 // For the purpose of debugging, just abort.
968 llvm_unreachable("FastISel didn't select the entire block");
973 FastIS->recomputeInsertPt();
982 // Run SelectionDAG instruction selection on the remainder of the block
983 // not handled by FastISel. If FastISel is not run, this is the entire
986 SelectBasicBlock(Begin, BI, HadTailCall);
990 FuncInfo->PHINodesToUpdate.clear();
994 SDB->clearDanglingDebugInfo();
998 SelectionDAGISel::FinishBasicBlock() {
1000 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1001 << FuncInfo->PHINodesToUpdate.size() << "\n";
1002 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1003 dbgs() << "Node " << i << " : ("
1004 << FuncInfo->PHINodesToUpdate[i].first
1005 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1007 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1008 // PHI nodes in successors.
1009 if (SDB->SwitchCases.empty() &&
1010 SDB->JTCases.empty() &&
1011 SDB->BitTestCases.empty()) {
1012 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1013 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1014 assert(PHI->isPHI() &&
1015 "This is not a machine PHI node that we are updating!");
1016 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1019 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1020 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1025 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1026 // Lower header first, if it wasn't already lowered
1027 if (!SDB->BitTestCases[i].Emitted) {
1028 // Set the current basic block to the mbb we wish to insert the code into
1029 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1030 FuncInfo->InsertPt = FuncInfo->MBB->end();
1032 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1033 CurDAG->setRoot(SDB->getRoot());
1035 CodeGenAndEmitDAG();
1038 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1039 // Set the current basic block to the mbb we wish to insert the code into
1040 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1041 FuncInfo->InsertPt = FuncInfo->MBB->end();
1044 SDB->visitBitTestCase(SDB->BitTestCases[i],
1045 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1046 SDB->BitTestCases[i].Reg,
1047 SDB->BitTestCases[i].Cases[j],
1050 SDB->visitBitTestCase(SDB->BitTestCases[i],
1051 SDB->BitTestCases[i].Default,
1052 SDB->BitTestCases[i].Reg,
1053 SDB->BitTestCases[i].Cases[j],
1057 CurDAG->setRoot(SDB->getRoot());
1059 CodeGenAndEmitDAG();
1063 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1065 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1066 MachineBasicBlock *PHIBB = PHI->getParent();
1067 assert(PHI->isPHI() &&
1068 "This is not a machine PHI node that we are updating!");
1069 // This is "default" BB. We have two jumps to it. From "header" BB and
1070 // from last "case" BB.
1071 if (PHIBB == SDB->BitTestCases[i].Default) {
1072 PHI->addOperand(MachineOperand::
1073 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1075 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1076 PHI->addOperand(MachineOperand::
1077 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1079 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1082 // One of "cases" BB.
1083 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1085 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1086 if (cBB->isSuccessor(PHIBB)) {
1087 PHI->addOperand(MachineOperand::
1088 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1090 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1095 SDB->BitTestCases.clear();
1097 // If the JumpTable record is filled in, then we need to emit a jump table.
1098 // Updating the PHI nodes is tricky in this case, since we need to determine
1099 // whether the PHI is a successor of the range check MBB or the jump table MBB
1100 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1101 // Lower header first, if it wasn't already lowered
1102 if (!SDB->JTCases[i].first.Emitted) {
1103 // Set the current basic block to the mbb we wish to insert the code into
1104 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1105 FuncInfo->InsertPt = FuncInfo->MBB->end();
1107 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1109 CurDAG->setRoot(SDB->getRoot());
1111 CodeGenAndEmitDAG();
1114 // Set the current basic block to the mbb we wish to insert the code into
1115 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1116 FuncInfo->InsertPt = FuncInfo->MBB->end();
1118 SDB->visitJumpTable(SDB->JTCases[i].second);
1119 CurDAG->setRoot(SDB->getRoot());
1121 CodeGenAndEmitDAG();
1124 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1126 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1127 MachineBasicBlock *PHIBB = PHI->getParent();
1128 assert(PHI->isPHI() &&
1129 "This is not a machine PHI node that we are updating!");
1130 // "default" BB. We can go there only from header BB.
1131 if (PHIBB == SDB->JTCases[i].second.Default) {
1133 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1136 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1138 // JT BB. Just iterate over successors here
1139 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1141 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1143 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1147 SDB->JTCases.clear();
1149 // If the switch block involved a branch to one of the actual successors, we
1150 // need to update PHI nodes in that block.
1151 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1152 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1153 assert(PHI->isPHI() &&
1154 "This is not a machine PHI node that we are updating!");
1155 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1157 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1158 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1162 // If we generated any switch lowering information, build and codegen any
1163 // additional DAGs necessary.
1164 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1165 // Set the current basic block to the mbb we wish to insert the code into
1166 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1167 FuncInfo->InsertPt = FuncInfo->MBB->end();
1169 // Determine the unique successors.
1170 SmallVector<MachineBasicBlock *, 2> Succs;
1171 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1172 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1173 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1175 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1176 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1177 CurDAG->setRoot(SDB->getRoot());
1179 CodeGenAndEmitDAG();
1181 // Remember the last block, now that any splitting is done, for use in
1182 // populating PHI nodes in successors.
1183 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1185 // Handle any PHI nodes in successors of this chunk, as if we were coming
1186 // from the original BB before switch expansion. Note that PHI nodes can
1187 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1188 // handle them the right number of times.
1189 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1190 FuncInfo->MBB = Succs[i];
1191 FuncInfo->InsertPt = FuncInfo->MBB->end();
1192 // FuncInfo->MBB may have been removed from the CFG if a branch was
1194 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1195 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1196 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1198 // This value for this PHI node is recorded in PHINodesToUpdate.
1199 for (unsigned pn = 0; ; ++pn) {
1200 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1201 "Didn't find PHI entry!");
1202 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1203 Phi->addOperand(MachineOperand::
1204 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1206 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1214 SDB->SwitchCases.clear();
1218 /// Create the scheduler. If a specific scheduler was specified
1219 /// via the SchedulerRegistry, use it, otherwise select the
1220 /// one preferred by the target.
1222 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1223 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1227 RegisterScheduler::setDefault(Ctor);
1230 return Ctor(this, OptLevel);
1233 //===----------------------------------------------------------------------===//
1234 // Helper functions used by the generated instruction selector.
1235 //===----------------------------------------------------------------------===//
1236 // Calls to these methods are generated by tblgen.
1238 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1239 /// the dag combiner simplified the 255, we still want to match. RHS is the
1240 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1241 /// specified in the .td file (e.g. 255).
1242 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1243 int64_t DesiredMaskS) const {
1244 const APInt &ActualMask = RHS->getAPIntValue();
1245 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1247 // If the actual mask exactly matches, success!
1248 if (ActualMask == DesiredMask)
1251 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1252 if (ActualMask.intersects(~DesiredMask))
1255 // Otherwise, the DAG Combiner may have proven that the value coming in is
1256 // either already zero or is not demanded. Check for known zero input bits.
1257 APInt NeededMask = DesiredMask & ~ActualMask;
1258 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1261 // TODO: check to see if missing bits are just not demanded.
1263 // Otherwise, this pattern doesn't match.
1267 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1268 /// the dag combiner simplified the 255, we still want to match. RHS is the
1269 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1270 /// specified in the .td file (e.g. 255).
1271 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1272 int64_t DesiredMaskS) const {
1273 const APInt &ActualMask = RHS->getAPIntValue();
1274 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1276 // If the actual mask exactly matches, success!
1277 if (ActualMask == DesiredMask)
1280 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1281 if (ActualMask.intersects(~DesiredMask))
1284 // Otherwise, the DAG Combiner may have proven that the value coming in is
1285 // either already zero or is not demanded. Check for known zero input bits.
1286 APInt NeededMask = DesiredMask & ~ActualMask;
1288 APInt KnownZero, KnownOne;
1289 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1291 // If all the missing bits in the or are already known to be set, match!
1292 if ((NeededMask & KnownOne) == NeededMask)
1295 // TODO: check to see if missing bits are just not demanded.
1297 // Otherwise, this pattern doesn't match.
1302 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1303 /// by tblgen. Others should not call it.
1304 void SelectionDAGISel::
1305 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1306 std::vector<SDValue> InOps;
1307 std::swap(InOps, Ops);
1309 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1310 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1311 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1312 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1314 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1315 if (InOps[e-1].getValueType() == MVT::Glue)
1316 --e; // Don't process a glue operand if it is here.
1319 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1320 if (!InlineAsm::isMemKind(Flags)) {
1321 // Just skip over this operand, copying the operands verbatim.
1322 Ops.insert(Ops.end(), InOps.begin()+i,
1323 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1324 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1326 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1327 "Memory operand with multiple values?");
1328 // Otherwise, this is a memory operand. Ask the target to select it.
1329 std::vector<SDValue> SelOps;
1330 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1331 report_fatal_error("Could not match memory address. Inline asm"
1334 // Add this to the output node.
1336 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1337 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1338 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1343 // Add the glue input back if present.
1344 if (e != InOps.size())
1345 Ops.push_back(InOps.back());
1348 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1351 static SDNode *findGlueUse(SDNode *N) {
1352 unsigned FlagResNo = N->getNumValues()-1;
1353 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1354 SDUse &Use = I.getUse();
1355 if (Use.getResNo() == FlagResNo)
1356 return Use.getUser();
1361 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1362 /// This function recursively traverses up the operand chain, ignoring
1364 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1365 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1366 bool IgnoreChains) {
1367 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1368 // greater than all of its (recursive) operands. If we scan to a point where
1369 // 'use' is smaller than the node we're scanning for, then we know we will
1372 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1373 // happen because we scan down to newly selected nodes in the case of glue
1375 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1378 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1379 // won't fail if we scan it again.
1380 if (!Visited.insert(Use))
1383 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1384 // Ignore chain uses, they are validated by HandleMergeInputChains.
1385 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1388 SDNode *N = Use->getOperand(i).getNode();
1390 if (Use == ImmedUse || Use == Root)
1391 continue; // We are not looking for immediate use.
1396 // Traverse up the operand chain.
1397 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1403 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1404 /// operand node N of U during instruction selection that starts at Root.
1405 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1406 SDNode *Root) const {
1407 if (OptLevel == CodeGenOpt::None) return false;
1408 return N.hasOneUse();
1411 /// IsLegalToFold - Returns true if the specific operand node N of
1412 /// U can be folded during instruction selection that starts at Root.
1413 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1414 CodeGenOpt::Level OptLevel,
1415 bool IgnoreChains) {
1416 if (OptLevel == CodeGenOpt::None) return false;
1418 // If Root use can somehow reach N through a path that that doesn't contain
1419 // U then folding N would create a cycle. e.g. In the following
1420 // diagram, Root can reach N through X. If N is folded into into Root, then
1421 // X is both a predecessor and a successor of U.
1432 // * indicates nodes to be folded together.
1434 // If Root produces glue, then it gets (even more) interesting. Since it
1435 // will be "glued" together with its glue use in the scheduler, we need to
1436 // check if it might reach N.
1455 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1456 // (call it Fold), then X is a predecessor of GU and a successor of
1457 // Fold. But since Fold and GU are glued together, this will create
1458 // a cycle in the scheduling graph.
1460 // If the node has glue, walk down the graph to the "lowest" node in the
1462 EVT VT = Root->getValueType(Root->getNumValues()-1);
1463 while (VT == MVT::Glue) {
1464 SDNode *GU = findGlueUse(Root);
1468 VT = Root->getValueType(Root->getNumValues()-1);
1470 // If our query node has a glue result with a use, we've walked up it. If
1471 // the user (which has already been selected) has a chain or indirectly uses
1472 // the chain, our WalkChainUsers predicate will not consider it. Because of
1473 // this, we cannot ignore chains in this predicate.
1474 IgnoreChains = false;
1478 SmallPtrSet<SDNode*, 16> Visited;
1479 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1482 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1483 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1484 SelectInlineAsmMemoryOperands(Ops);
1486 std::vector<EVT> VTs;
1487 VTs.push_back(MVT::Other);
1488 VTs.push_back(MVT::Glue);
1489 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1490 VTs, &Ops[0], Ops.size());
1492 return New.getNode();
1495 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1496 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1499 /// GetVBR - decode a vbr encoding whose top bit is set.
1500 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1501 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1502 assert(Val >= 128 && "Not a VBR");
1503 Val &= 127; // Remove first vbr bit.
1508 NextBits = MatcherTable[Idx++];
1509 Val |= (NextBits&127) << Shift;
1511 } while (NextBits & 128);
1517 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1518 /// interior glue and chain results to use the new glue and chain results.
1519 void SelectionDAGISel::
1520 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1521 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1523 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1524 bool isMorphNodeTo) {
1525 SmallVector<SDNode*, 4> NowDeadNodes;
1527 ISelUpdater ISU(ISelPosition);
1529 // Now that all the normal results are replaced, we replace the chain and
1530 // glue results if present.
1531 if (!ChainNodesMatched.empty()) {
1532 assert(InputChain.getNode() != 0 &&
1533 "Matched input chains but didn't produce a chain");
1534 // Loop over all of the nodes we matched that produced a chain result.
1535 // Replace all the chain results with the final chain we ended up with.
1536 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1537 SDNode *ChainNode = ChainNodesMatched[i];
1539 // If this node was already deleted, don't look at it.
1540 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1543 // Don't replace the results of the root node if we're doing a
1545 if (ChainNode == NodeToMatch && isMorphNodeTo)
1548 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1549 if (ChainVal.getValueType() == MVT::Glue)
1550 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1551 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1552 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1554 // If the node became dead and we haven't already seen it, delete it.
1555 if (ChainNode->use_empty() &&
1556 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1557 NowDeadNodes.push_back(ChainNode);
1561 // If the result produces glue, update any glue results in the matched
1562 // pattern with the glue result.
1563 if (InputGlue.getNode() != 0) {
1564 // Handle any interior nodes explicitly marked.
1565 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1566 SDNode *FRN = GlueResultNodesMatched[i];
1568 // If this node was already deleted, don't look at it.
1569 if (FRN->getOpcode() == ISD::DELETED_NODE)
1572 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1573 "Doesn't have a glue result");
1574 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1577 // If the node became dead and we haven't already seen it, delete it.
1578 if (FRN->use_empty() &&
1579 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1580 NowDeadNodes.push_back(FRN);
1584 if (!NowDeadNodes.empty())
1585 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1587 DEBUG(errs() << "ISEL: Match complete!\n");
1593 CR_LeadsToInteriorNode
1596 /// WalkChainUsers - Walk down the users of the specified chained node that is
1597 /// part of the pattern we're matching, looking at all of the users we find.
1598 /// This determines whether something is an interior node, whether we have a
1599 /// non-pattern node in between two pattern nodes (which prevent folding because
1600 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1601 /// between pattern nodes (in which case the TF becomes part of the pattern).
1603 /// The walk we do here is guaranteed to be small because we quickly get down to
1604 /// already selected nodes "below" us.
1606 WalkChainUsers(SDNode *ChainedNode,
1607 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1608 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1609 ChainResult Result = CR_Simple;
1611 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1612 E = ChainedNode->use_end(); UI != E; ++UI) {
1613 // Make sure the use is of the chain, not some other value we produce.
1614 if (UI.getUse().getValueType() != MVT::Other) continue;
1618 // If we see an already-selected machine node, then we've gone beyond the
1619 // pattern that we're selecting down into the already selected chunk of the
1621 if (User->isMachineOpcode() ||
1622 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1625 if (User->getOpcode() == ISD::CopyToReg ||
1626 User->getOpcode() == ISD::CopyFromReg ||
1627 User->getOpcode() == ISD::INLINEASM ||
1628 User->getOpcode() == ISD::EH_LABEL) {
1629 // If their node ID got reset to -1 then they've already been selected.
1630 // Treat them like a MachineOpcode.
1631 if (User->getNodeId() == -1)
1635 // If we have a TokenFactor, we handle it specially.
1636 if (User->getOpcode() != ISD::TokenFactor) {
1637 // If the node isn't a token factor and isn't part of our pattern, then it
1638 // must be a random chained node in between two nodes we're selecting.
1639 // This happens when we have something like:
1644 // Because we structurally match the load/store as a read/modify/write,
1645 // but the call is chained between them. We cannot fold in this case
1646 // because it would induce a cycle in the graph.
1647 if (!std::count(ChainedNodesInPattern.begin(),
1648 ChainedNodesInPattern.end(), User))
1649 return CR_InducesCycle;
1651 // Otherwise we found a node that is part of our pattern. For example in:
1655 // This would happen when we're scanning down from the load and see the
1656 // store as a user. Record that there is a use of ChainedNode that is
1657 // part of the pattern and keep scanning uses.
1658 Result = CR_LeadsToInteriorNode;
1659 InteriorChainedNodes.push_back(User);
1663 // If we found a TokenFactor, there are two cases to consider: first if the
1664 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1665 // uses of the TF are in our pattern) we just want to ignore it. Second,
1666 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1672 // | \ DAG's like cheese
1675 // [TokenFactor] [Op]
1682 // In this case, the TokenFactor becomes part of our match and we rewrite it
1683 // as a new TokenFactor.
1685 // To distinguish these two cases, do a recursive walk down the uses.
1686 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1688 // If the uses of the TokenFactor are just already-selected nodes, ignore
1689 // it, it is "below" our pattern.
1691 case CR_InducesCycle:
1692 // If the uses of the TokenFactor lead to nodes that are not part of our
1693 // pattern that are not selected, folding would turn this into a cycle,
1695 return CR_InducesCycle;
1696 case CR_LeadsToInteriorNode:
1697 break; // Otherwise, keep processing.
1700 // Okay, we know we're in the interesting interior case. The TokenFactor
1701 // is now going to be considered part of the pattern so that we rewrite its
1702 // uses (it may have uses that are not part of the pattern) with the
1703 // ultimate chain result of the generated code. We will also add its chain
1704 // inputs as inputs to the ultimate TokenFactor we create.
1705 Result = CR_LeadsToInteriorNode;
1706 ChainedNodesInPattern.push_back(User);
1707 InteriorChainedNodes.push_back(User);
1714 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1715 /// operation for when the pattern matched at least one node with a chains. The
1716 /// input vector contains a list of all of the chained nodes that we match. We
1717 /// must determine if this is a valid thing to cover (i.e. matching it won't
1718 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1719 /// be used as the input node chain for the generated nodes.
1721 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1722 SelectionDAG *CurDAG) {
1723 // Walk all of the chained nodes we've matched, recursively scanning down the
1724 // users of the chain result. This adds any TokenFactor nodes that are caught
1725 // in between chained nodes to the chained and interior nodes list.
1726 SmallVector<SDNode*, 3> InteriorChainedNodes;
1727 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1728 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1729 InteriorChainedNodes) == CR_InducesCycle)
1730 return SDValue(); // Would induce a cycle.
1733 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1734 // that we are interested in. Form our input TokenFactor node.
1735 SmallVector<SDValue, 3> InputChains;
1736 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1737 // Add the input chain of this node to the InputChains list (which will be
1738 // the operands of the generated TokenFactor) if it's not an interior node.
1739 SDNode *N = ChainNodesMatched[i];
1740 if (N->getOpcode() != ISD::TokenFactor) {
1741 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1744 // Otherwise, add the input chain.
1745 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1746 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1747 InputChains.push_back(InChain);
1751 // If we have a token factor, we want to add all inputs of the token factor
1752 // that are not part of the pattern we're matching.
1753 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1754 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1755 N->getOperand(op).getNode()))
1756 InputChains.push_back(N->getOperand(op));
1761 if (InputChains.size() == 1)
1762 return InputChains[0];
1763 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1764 MVT::Other, &InputChains[0], InputChains.size());
1767 /// MorphNode - Handle morphing a node in place for the selector.
1768 SDNode *SelectionDAGISel::
1769 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1770 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1771 // It is possible we're using MorphNodeTo to replace a node with no
1772 // normal results with one that has a normal result (or we could be
1773 // adding a chain) and the input could have glue and chains as well.
1774 // In this case we need to shift the operands down.
1775 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1776 // than the old isel though.
1777 int OldGlueResultNo = -1, OldChainResultNo = -1;
1779 unsigned NTMNumResults = Node->getNumValues();
1780 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1781 OldGlueResultNo = NTMNumResults-1;
1782 if (NTMNumResults != 1 &&
1783 Node->getValueType(NTMNumResults-2) == MVT::Other)
1784 OldChainResultNo = NTMNumResults-2;
1785 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1786 OldChainResultNo = NTMNumResults-1;
1788 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1789 // that this deletes operands of the old node that become dead.
1790 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1792 // MorphNodeTo can operate in two ways: if an existing node with the
1793 // specified operands exists, it can just return it. Otherwise, it
1794 // updates the node in place to have the requested operands.
1796 // If we updated the node in place, reset the node ID. To the isel,
1797 // this should be just like a newly allocated machine node.
1801 unsigned ResNumResults = Res->getNumValues();
1802 // Move the glue if needed.
1803 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1804 (unsigned)OldGlueResultNo != ResNumResults-1)
1805 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1806 SDValue(Res, ResNumResults-1));
1808 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1811 // Move the chain reference if needed.
1812 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1813 (unsigned)OldChainResultNo != ResNumResults-1)
1814 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1815 SDValue(Res, ResNumResults-1));
1817 // Otherwise, no replacement happened because the node already exists. Replace
1818 // Uses of the old node with the new one.
1820 CurDAG->ReplaceAllUsesWith(Node, Res);
1825 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1826 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1827 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1829 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1830 // Accept if it is exactly the same as a previously recorded node.
1831 unsigned RecNo = MatcherTable[MatcherIndex++];
1832 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1833 return N == RecordedNodes[RecNo].first;
1836 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1837 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1838 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1839 SelectionDAGISel &SDISel) {
1840 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1843 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1844 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1845 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1846 SelectionDAGISel &SDISel, SDNode *N) {
1847 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1850 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1851 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1853 uint16_t Opc = MatcherTable[MatcherIndex++];
1854 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1855 return N->getOpcode() == Opc;
1858 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1859 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1860 SDValue N, const TargetLowering &TLI) {
1861 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1862 if (N.getValueType() == VT) return true;
1864 // Handle the case when VT is iPTR.
1865 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1868 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1869 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1870 SDValue N, const TargetLowering &TLI,
1872 if (ChildNo >= N.getNumOperands())
1873 return false; // Match fails if out of range child #.
1874 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1878 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1879 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1881 return cast<CondCodeSDNode>(N)->get() ==
1882 (ISD::CondCode)MatcherTable[MatcherIndex++];
1885 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1886 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1887 SDValue N, const TargetLowering &TLI) {
1888 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1889 if (cast<VTSDNode>(N)->getVT() == VT)
1892 // Handle the case when VT is iPTR.
1893 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1896 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1897 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1899 int64_t Val = MatcherTable[MatcherIndex++];
1901 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1903 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1904 return C != 0 && C->getSExtValue() == Val;
1907 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1908 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1909 SDValue N, SelectionDAGISel &SDISel) {
1910 int64_t Val = MatcherTable[MatcherIndex++];
1912 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1914 if (N->getOpcode() != ISD::AND) return false;
1916 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1917 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1920 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1921 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1922 SDValue N, SelectionDAGISel &SDISel) {
1923 int64_t Val = MatcherTable[MatcherIndex++];
1925 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1927 if (N->getOpcode() != ISD::OR) return false;
1929 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1930 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1933 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1934 /// scope, evaluate the current node. If the current predicate is known to
1935 /// fail, set Result=true and return anything. If the current predicate is
1936 /// known to pass, set Result=false and return the MatcherIndex to continue
1937 /// with. If the current predicate is unknown, set Result=false and return the
1938 /// MatcherIndex to continue with.
1939 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1940 unsigned Index, SDValue N,
1941 bool &Result, SelectionDAGISel &SDISel,
1942 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1943 switch (Table[Index++]) {
1946 return Index-1; // Could not evaluate this predicate.
1947 case SelectionDAGISel::OPC_CheckSame:
1948 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1950 case SelectionDAGISel::OPC_CheckPatternPredicate:
1951 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1953 case SelectionDAGISel::OPC_CheckPredicate:
1954 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1956 case SelectionDAGISel::OPC_CheckOpcode:
1957 Result = !::CheckOpcode(Table, Index, N.getNode());
1959 case SelectionDAGISel::OPC_CheckType:
1960 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1962 case SelectionDAGISel::OPC_CheckChild0Type:
1963 case SelectionDAGISel::OPC_CheckChild1Type:
1964 case SelectionDAGISel::OPC_CheckChild2Type:
1965 case SelectionDAGISel::OPC_CheckChild3Type:
1966 case SelectionDAGISel::OPC_CheckChild4Type:
1967 case SelectionDAGISel::OPC_CheckChild5Type:
1968 case SelectionDAGISel::OPC_CheckChild6Type:
1969 case SelectionDAGISel::OPC_CheckChild7Type:
1970 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1971 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1973 case SelectionDAGISel::OPC_CheckCondCode:
1974 Result = !::CheckCondCode(Table, Index, N);
1976 case SelectionDAGISel::OPC_CheckValueType:
1977 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1979 case SelectionDAGISel::OPC_CheckInteger:
1980 Result = !::CheckInteger(Table, Index, N);
1982 case SelectionDAGISel::OPC_CheckAndImm:
1983 Result = !::CheckAndImm(Table, Index, N, SDISel);
1985 case SelectionDAGISel::OPC_CheckOrImm:
1986 Result = !::CheckOrImm(Table, Index, N, SDISel);
1994 /// FailIndex - If this match fails, this is the index to continue with.
1997 /// NodeStack - The node stack when the scope was formed.
1998 SmallVector<SDValue, 4> NodeStack;
2000 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2001 unsigned NumRecordedNodes;
2003 /// NumMatchedMemRefs - The number of matched memref entries.
2004 unsigned NumMatchedMemRefs;
2006 /// InputChain/InputGlue - The current chain/glue
2007 SDValue InputChain, InputGlue;
2009 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2010 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2015 SDNode *SelectionDAGISel::
2016 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2017 unsigned TableSize) {
2018 // FIXME: Should these even be selected? Handle these cases in the caller?
2019 switch (NodeToMatch->getOpcode()) {
2022 case ISD::EntryToken: // These nodes remain the same.
2023 case ISD::BasicBlock:
2025 //case ISD::VALUETYPE:
2026 //case ISD::CONDCODE:
2027 case ISD::HANDLENODE:
2028 case ISD::MDNODE_SDNODE:
2029 case ISD::TargetConstant:
2030 case ISD::TargetConstantFP:
2031 case ISD::TargetConstantPool:
2032 case ISD::TargetFrameIndex:
2033 case ISD::TargetExternalSymbol:
2034 case ISD::TargetBlockAddress:
2035 case ISD::TargetJumpTable:
2036 case ISD::TargetGlobalTLSAddress:
2037 case ISD::TargetGlobalAddress:
2038 case ISD::TokenFactor:
2039 case ISD::CopyFromReg:
2040 case ISD::CopyToReg:
2042 NodeToMatch->setNodeId(-1); // Mark selected.
2044 case ISD::AssertSext:
2045 case ISD::AssertZext:
2046 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2047 NodeToMatch->getOperand(0));
2049 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2050 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2053 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2055 // Set up the node stack with NodeToMatch as the only node on the stack.
2056 SmallVector<SDValue, 8> NodeStack;
2057 SDValue N = SDValue(NodeToMatch, 0);
2058 NodeStack.push_back(N);
2060 // MatchScopes - Scopes used when matching, if a match failure happens, this
2061 // indicates where to continue checking.
2062 SmallVector<MatchScope, 8> MatchScopes;
2064 // RecordedNodes - This is the set of nodes that have been recorded by the
2065 // state machine. The second value is the parent of the node, or null if the
2066 // root is recorded.
2067 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2069 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2071 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2073 // These are the current input chain and glue for use when generating nodes.
2074 // Various Emit operations change these. For example, emitting a copytoreg
2075 // uses and updates these.
2076 SDValue InputChain, InputGlue;
2078 // ChainNodesMatched - If a pattern matches nodes that have input/output
2079 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2080 // which ones they are. The result is captured into this list so that we can
2081 // update the chain results when the pattern is complete.
2082 SmallVector<SDNode*, 3> ChainNodesMatched;
2083 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2085 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2086 NodeToMatch->dump(CurDAG);
2089 // Determine where to start the interpreter. Normally we start at opcode #0,
2090 // but if the state machine starts with an OPC_SwitchOpcode, then we
2091 // accelerate the first lookup (which is guaranteed to be hot) with the
2092 // OpcodeOffset table.
2093 unsigned MatcherIndex = 0;
2095 if (!OpcodeOffset.empty()) {
2096 // Already computed the OpcodeOffset table, just index into it.
2097 if (N.getOpcode() < OpcodeOffset.size())
2098 MatcherIndex = OpcodeOffset[N.getOpcode()];
2099 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2101 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2102 // Otherwise, the table isn't computed, but the state machine does start
2103 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2104 // is the first time we're selecting an instruction.
2107 // Get the size of this case.
2108 unsigned CaseSize = MatcherTable[Idx++];
2110 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2111 if (CaseSize == 0) break;
2113 // Get the opcode, add the index to the table.
2114 uint16_t Opc = MatcherTable[Idx++];
2115 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2116 if (Opc >= OpcodeOffset.size())
2117 OpcodeOffset.resize((Opc+1)*2);
2118 OpcodeOffset[Opc] = Idx;
2122 // Okay, do the lookup for the first opcode.
2123 if (N.getOpcode() < OpcodeOffset.size())
2124 MatcherIndex = OpcodeOffset[N.getOpcode()];
2128 assert(MatcherIndex < TableSize && "Invalid index");
2130 unsigned CurrentOpcodeIndex = MatcherIndex;
2132 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2135 // Okay, the semantics of this operation are that we should push a scope
2136 // then evaluate the first child. However, pushing a scope only to have
2137 // the first check fail (which then pops it) is inefficient. If we can
2138 // determine immediately that the first check (or first several) will
2139 // immediately fail, don't even bother pushing a scope for them.
2143 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2144 if (NumToSkip & 128)
2145 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2146 // Found the end of the scope with no match.
2147 if (NumToSkip == 0) {
2152 FailIndex = MatcherIndex+NumToSkip;
2154 unsigned MatcherIndexOfPredicate = MatcherIndex;
2155 (void)MatcherIndexOfPredicate; // silence warning.
2157 // If we can't evaluate this predicate without pushing a scope (e.g. if
2158 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2159 // push the scope and evaluate the full predicate chain.
2161 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2162 Result, *this, RecordedNodes);
2166 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2167 << "index " << MatcherIndexOfPredicate
2168 << ", continuing at " << FailIndex << "\n");
2169 ++NumDAGIselRetries;
2171 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2172 // move to the next case.
2173 MatcherIndex = FailIndex;
2176 // If the whole scope failed to match, bail.
2177 if (FailIndex == 0) break;
2179 // Push a MatchScope which indicates where to go if the first child fails
2181 MatchScope NewEntry;
2182 NewEntry.FailIndex = FailIndex;
2183 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2184 NewEntry.NumRecordedNodes = RecordedNodes.size();
2185 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2186 NewEntry.InputChain = InputChain;
2187 NewEntry.InputGlue = InputGlue;
2188 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2189 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2190 MatchScopes.push_back(NewEntry);
2193 case OPC_RecordNode: {
2194 // Remember this node, it may end up being an operand in the pattern.
2196 if (NodeStack.size() > 1)
2197 Parent = NodeStack[NodeStack.size()-2].getNode();
2198 RecordedNodes.push_back(std::make_pair(N, Parent));
2202 case OPC_RecordChild0: case OPC_RecordChild1:
2203 case OPC_RecordChild2: case OPC_RecordChild3:
2204 case OPC_RecordChild4: case OPC_RecordChild5:
2205 case OPC_RecordChild6: case OPC_RecordChild7: {
2206 unsigned ChildNo = Opcode-OPC_RecordChild0;
2207 if (ChildNo >= N.getNumOperands())
2208 break; // Match fails if out of range child #.
2210 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2214 case OPC_RecordMemRef:
2215 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2218 case OPC_CaptureGlueInput:
2219 // If the current node has an input glue, capture it in InputGlue.
2220 if (N->getNumOperands() != 0 &&
2221 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2222 InputGlue = N->getOperand(N->getNumOperands()-1);
2225 case OPC_MoveChild: {
2226 unsigned ChildNo = MatcherTable[MatcherIndex++];
2227 if (ChildNo >= N.getNumOperands())
2228 break; // Match fails if out of range child #.
2229 N = N.getOperand(ChildNo);
2230 NodeStack.push_back(N);
2234 case OPC_MoveParent:
2235 // Pop the current node off the NodeStack.
2236 NodeStack.pop_back();
2237 assert(!NodeStack.empty() && "Node stack imbalance!");
2238 N = NodeStack.back();
2242 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2244 case OPC_CheckPatternPredicate:
2245 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2247 case OPC_CheckPredicate:
2248 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2252 case OPC_CheckComplexPat: {
2253 unsigned CPNum = MatcherTable[MatcherIndex++];
2254 unsigned RecNo = MatcherTable[MatcherIndex++];
2255 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2256 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2257 RecordedNodes[RecNo].first, CPNum,
2262 case OPC_CheckOpcode:
2263 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2267 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2270 case OPC_SwitchOpcode: {
2271 unsigned CurNodeOpcode = N.getOpcode();
2272 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2275 // Get the size of this case.
2276 CaseSize = MatcherTable[MatcherIndex++];
2278 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2279 if (CaseSize == 0) break;
2281 uint16_t Opc = MatcherTable[MatcherIndex++];
2282 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2284 // If the opcode matches, then we will execute this case.
2285 if (CurNodeOpcode == Opc)
2288 // Otherwise, skip over this case.
2289 MatcherIndex += CaseSize;
2292 // If no cases matched, bail out.
2293 if (CaseSize == 0) break;
2295 // Otherwise, execute the case we found.
2296 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2297 << " to " << MatcherIndex << "\n");
2301 case OPC_SwitchType: {
2302 MVT CurNodeVT = N.getValueType().getSimpleVT();
2303 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2306 // Get the size of this case.
2307 CaseSize = MatcherTable[MatcherIndex++];
2309 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2310 if (CaseSize == 0) break;
2312 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2313 if (CaseVT == MVT::iPTR)
2314 CaseVT = TLI.getPointerTy();
2316 // If the VT matches, then we will execute this case.
2317 if (CurNodeVT == CaseVT)
2320 // Otherwise, skip over this case.
2321 MatcherIndex += CaseSize;
2324 // If no cases matched, bail out.
2325 if (CaseSize == 0) break;
2327 // Otherwise, execute the case we found.
2328 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2329 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2332 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2333 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2334 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2335 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2336 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2337 Opcode-OPC_CheckChild0Type))
2340 case OPC_CheckCondCode:
2341 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2343 case OPC_CheckValueType:
2344 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2346 case OPC_CheckInteger:
2347 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2349 case OPC_CheckAndImm:
2350 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2352 case OPC_CheckOrImm:
2353 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2356 case OPC_CheckFoldableChainNode: {
2357 assert(NodeStack.size() != 1 && "No parent node");
2358 // Verify that all intermediate nodes between the root and this one have
2360 bool HasMultipleUses = false;
2361 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2362 if (!NodeStack[i].hasOneUse()) {
2363 HasMultipleUses = true;
2366 if (HasMultipleUses) break;
2368 // Check to see that the target thinks this is profitable to fold and that
2369 // we can fold it without inducing cycles in the graph.
2370 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2372 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2373 NodeToMatch, OptLevel,
2374 true/*We validate our own chains*/))
2379 case OPC_EmitInteger: {
2380 MVT::SimpleValueType VT =
2381 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2382 int64_t Val = MatcherTable[MatcherIndex++];
2384 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2385 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2386 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2389 case OPC_EmitRegister: {
2390 MVT::SimpleValueType VT =
2391 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2392 unsigned RegNo = MatcherTable[MatcherIndex++];
2393 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2394 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2397 case OPC_EmitRegister2: {
2398 // For targets w/ more than 256 register names, the register enum
2399 // values are stored in two bytes in the matcher table (just like
2401 MVT::SimpleValueType VT =
2402 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2403 unsigned RegNo = MatcherTable[MatcherIndex++];
2404 RegNo |= MatcherTable[MatcherIndex++] << 8;
2405 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2406 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2410 case OPC_EmitConvertToTarget: {
2411 // Convert from IMM/FPIMM to target version.
2412 unsigned RecNo = MatcherTable[MatcherIndex++];
2413 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2414 SDValue Imm = RecordedNodes[RecNo].first;
2416 if (Imm->getOpcode() == ISD::Constant) {
2417 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2418 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2419 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2420 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2421 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2424 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2428 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2429 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2430 // These are space-optimized forms of OPC_EmitMergeInputChains.
2431 assert(InputChain.getNode() == 0 &&
2432 "EmitMergeInputChains should be the first chain producing node");
2433 assert(ChainNodesMatched.empty() &&
2434 "Should only have one EmitMergeInputChains per match");
2436 // Read all of the chained nodes.
2437 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2438 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2439 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2441 // FIXME: What if other value results of the node have uses not matched
2443 if (ChainNodesMatched.back() != NodeToMatch &&
2444 !RecordedNodes[RecNo].first.hasOneUse()) {
2445 ChainNodesMatched.clear();
2449 // Merge the input chains if they are not intra-pattern references.
2450 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2452 if (InputChain.getNode() == 0)
2453 break; // Failed to merge.
2457 case OPC_EmitMergeInputChains: {
2458 assert(InputChain.getNode() == 0 &&
2459 "EmitMergeInputChains should be the first chain producing node");
2460 // This node gets a list of nodes we matched in the input that have
2461 // chains. We want to token factor all of the input chains to these nodes
2462 // together. However, if any of the input chains is actually one of the
2463 // nodes matched in this pattern, then we have an intra-match reference.
2464 // Ignore these because the newly token factored chain should not refer to
2466 unsigned NumChains = MatcherTable[MatcherIndex++];
2467 assert(NumChains != 0 && "Can't TF zero chains");
2469 assert(ChainNodesMatched.empty() &&
2470 "Should only have one EmitMergeInputChains per match");
2472 // Read all of the chained nodes.
2473 for (unsigned i = 0; i != NumChains; ++i) {
2474 unsigned RecNo = MatcherTable[MatcherIndex++];
2475 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2476 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2478 // FIXME: What if other value results of the node have uses not matched
2480 if (ChainNodesMatched.back() != NodeToMatch &&
2481 !RecordedNodes[RecNo].first.hasOneUse()) {
2482 ChainNodesMatched.clear();
2487 // If the inner loop broke out, the match fails.
2488 if (ChainNodesMatched.empty())
2491 // Merge the input chains if they are not intra-pattern references.
2492 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2494 if (InputChain.getNode() == 0)
2495 break; // Failed to merge.
2500 case OPC_EmitCopyToReg: {
2501 unsigned RecNo = MatcherTable[MatcherIndex++];
2502 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2503 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2505 if (InputChain.getNode() == 0)
2506 InputChain = CurDAG->getEntryNode();
2508 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2509 DestPhysReg, RecordedNodes[RecNo].first,
2512 InputGlue = InputChain.getValue(1);
2516 case OPC_EmitNodeXForm: {
2517 unsigned XFormNo = MatcherTable[MatcherIndex++];
2518 unsigned RecNo = MatcherTable[MatcherIndex++];
2519 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2520 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2521 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2526 case OPC_MorphNodeTo: {
2527 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2528 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2529 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2530 // Get the result VT list.
2531 unsigned NumVTs = MatcherTable[MatcherIndex++];
2532 SmallVector<EVT, 4> VTs;
2533 for (unsigned i = 0; i != NumVTs; ++i) {
2534 MVT::SimpleValueType VT =
2535 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2536 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2540 if (EmitNodeInfo & OPFL_Chain)
2541 VTs.push_back(MVT::Other);
2542 if (EmitNodeInfo & OPFL_GlueOutput)
2543 VTs.push_back(MVT::Glue);
2545 // This is hot code, so optimize the two most common cases of 1 and 2
2548 if (VTs.size() == 1)
2549 VTList = CurDAG->getVTList(VTs[0]);
2550 else if (VTs.size() == 2)
2551 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2553 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2555 // Get the operand list.
2556 unsigned NumOps = MatcherTable[MatcherIndex++];
2557 SmallVector<SDValue, 8> Ops;
2558 for (unsigned i = 0; i != NumOps; ++i) {
2559 unsigned RecNo = MatcherTable[MatcherIndex++];
2561 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2563 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2564 Ops.push_back(RecordedNodes[RecNo].first);
2567 // If there are variadic operands to add, handle them now.
2568 if (EmitNodeInfo & OPFL_VariadicInfo) {
2569 // Determine the start index to copy from.
2570 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2571 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2572 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2573 "Invalid variadic node");
2574 // Copy all of the variadic operands, not including a potential glue
2576 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2578 SDValue V = NodeToMatch->getOperand(i);
2579 if (V.getValueType() == MVT::Glue) break;
2584 // If this has chain/glue inputs, add them.
2585 if (EmitNodeInfo & OPFL_Chain)
2586 Ops.push_back(InputChain);
2587 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2588 Ops.push_back(InputGlue);
2592 if (Opcode != OPC_MorphNodeTo) {
2593 // If this is a normal EmitNode command, just create the new node and
2594 // add the results to the RecordedNodes list.
2595 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2596 VTList, Ops.data(), Ops.size());
2598 // Add all the non-glue/non-chain results to the RecordedNodes list.
2599 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2600 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2601 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2606 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2610 // If the node had chain/glue results, update our notion of the current
2612 if (EmitNodeInfo & OPFL_GlueOutput) {
2613 InputGlue = SDValue(Res, VTs.size()-1);
2614 if (EmitNodeInfo & OPFL_Chain)
2615 InputChain = SDValue(Res, VTs.size()-2);
2616 } else if (EmitNodeInfo & OPFL_Chain)
2617 InputChain = SDValue(Res, VTs.size()-1);
2619 // If the OPFL_MemRefs glue is set on this node, slap all of the
2620 // accumulated memrefs onto it.
2622 // FIXME: This is vastly incorrect for patterns with multiple outputs
2623 // instructions that access memory and for ComplexPatterns that match
2625 if (EmitNodeInfo & OPFL_MemRefs) {
2626 // Only attach load or store memory operands if the generated
2627 // instruction may load or store.
2628 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2629 bool mayLoad = MCID.mayLoad();
2630 bool mayStore = MCID.mayStore();
2632 unsigned NumMemRefs = 0;
2633 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2634 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2635 if ((*I)->isLoad()) {
2638 } else if ((*I)->isStore()) {
2646 MachineSDNode::mmo_iterator MemRefs =
2647 MF->allocateMemRefsArray(NumMemRefs);
2649 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2650 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2651 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2652 if ((*I)->isLoad()) {
2655 } else if ((*I)->isStore()) {
2663 cast<MachineSDNode>(Res)
2664 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2668 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2669 << " node: "; Res->dump(CurDAG); errs() << "\n");
2671 // If this was a MorphNodeTo then we're completely done!
2672 if (Opcode == OPC_MorphNodeTo) {
2673 // Update chain and glue uses.
2674 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2675 InputGlue, GlueResultNodesMatched, true);
2682 case OPC_MarkGlueResults: {
2683 unsigned NumNodes = MatcherTable[MatcherIndex++];
2685 // Read and remember all the glue-result nodes.
2686 for (unsigned i = 0; i != NumNodes; ++i) {
2687 unsigned RecNo = MatcherTable[MatcherIndex++];
2689 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2691 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2692 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2697 case OPC_CompleteMatch: {
2698 // The match has been completed, and any new nodes (if any) have been
2699 // created. Patch up references to the matched dag to use the newly
2701 unsigned NumResults = MatcherTable[MatcherIndex++];
2703 for (unsigned i = 0; i != NumResults; ++i) {
2704 unsigned ResSlot = MatcherTable[MatcherIndex++];
2706 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2708 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2709 SDValue Res = RecordedNodes[ResSlot].first;
2711 assert(i < NodeToMatch->getNumValues() &&
2712 NodeToMatch->getValueType(i) != MVT::Other &&
2713 NodeToMatch->getValueType(i) != MVT::Glue &&
2714 "Invalid number of results to complete!");
2715 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2716 NodeToMatch->getValueType(i) == MVT::iPTR ||
2717 Res.getValueType() == MVT::iPTR ||
2718 NodeToMatch->getValueType(i).getSizeInBits() ==
2719 Res.getValueType().getSizeInBits()) &&
2720 "invalid replacement");
2721 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2724 // If the root node defines glue, add it to the glue nodes to update list.
2725 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2726 GlueResultNodesMatched.push_back(NodeToMatch);
2728 // Update chain and glue uses.
2729 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2730 InputGlue, GlueResultNodesMatched, false);
2732 assert(NodeToMatch->use_empty() &&
2733 "Didn't replace all uses of the node?");
2735 // FIXME: We just return here, which interacts correctly with SelectRoot
2736 // above. We should fix this to not return an SDNode* anymore.
2741 // If the code reached this point, then the match failed. See if there is
2742 // another child to try in the current 'Scope', otherwise pop it until we
2743 // find a case to check.
2744 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2745 ++NumDAGIselRetries;
2747 if (MatchScopes.empty()) {
2748 CannotYetSelect(NodeToMatch);
2752 // Restore the interpreter state back to the point where the scope was
2754 MatchScope &LastScope = MatchScopes.back();
2755 RecordedNodes.resize(LastScope.NumRecordedNodes);
2757 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2758 N = NodeStack.back();
2760 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2761 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2762 MatcherIndex = LastScope.FailIndex;
2764 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2766 InputChain = LastScope.InputChain;
2767 InputGlue = LastScope.InputGlue;
2768 if (!LastScope.HasChainNodesMatched)
2769 ChainNodesMatched.clear();
2770 if (!LastScope.HasGlueResultNodesMatched)
2771 GlueResultNodesMatched.clear();
2773 // Check to see what the offset is at the new MatcherIndex. If it is zero
2774 // we have reached the end of this scope, otherwise we have another child
2775 // in the current scope to try.
2776 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2777 if (NumToSkip & 128)
2778 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2780 // If we have another child in this scope to match, update FailIndex and
2782 if (NumToSkip != 0) {
2783 LastScope.FailIndex = MatcherIndex+NumToSkip;
2787 // End of this scope, pop it and try the next child in the containing
2789 MatchScopes.pop_back();
2796 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2798 raw_string_ostream Msg(msg);
2799 Msg << "Cannot select: ";
2801 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2802 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2803 N->getOpcode() != ISD::INTRINSIC_VOID) {
2804 N->printrFull(Msg, CurDAG);
2806 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2808 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2809 if (iid < Intrinsic::num_intrinsics)
2810 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2811 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2812 Msg << "target intrinsic %" << TII->getName(iid);
2814 Msg << "unknown intrinsic #" << iid;
2816 report_fatal_error(Msg.str());
2819 char SelectionDAGISel::ID = 0;