1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/Timer.h"
53 EnableValueProp("enable-value-prop", cl::Hidden, cl::init(false));
58 ViewISelDAGs("view-isel-dags", cl::Hidden,
59 cl::desc("Pop up a window to show isel dags as they are selected"));
61 ViewSchedDAGs("view-sched-dags", cl::Hidden,
62 cl::desc("Pop up a window to show sched dags as they are processed"));
64 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
65 cl::desc("Pop up a window to show SUnit dags after they are processed"));
67 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
70 //===---------------------------------------------------------------------===//
72 /// RegisterScheduler class - Track the registration of instruction schedulers.
74 //===---------------------------------------------------------------------===//
75 MachinePassRegistry RegisterScheduler::Registry;
77 //===---------------------------------------------------------------------===//
79 /// ISHeuristic command line option for instruction schedulers.
81 //===---------------------------------------------------------------------===//
82 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
83 RegisterPassParser<RegisterScheduler> >
84 ISHeuristic("pre-RA-sched",
85 cl::init(&createDefaultScheduler),
86 cl::desc("Instruction schedulers available (before register"
89 static RegisterScheduler
90 defaultListDAGScheduler("default", " Best scheduler for the target",
91 createDefaultScheduler);
93 namespace { struct SDISelAsmOperandInfo; }
95 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
96 /// insertvalue or extractvalue indices that identify a member, return
97 /// the linearized index of the start of the member.
99 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
100 const unsigned *Indices,
101 const unsigned *IndicesEnd,
102 unsigned CurIndex = 0) {
103 // Base case: We're done.
104 if (Indices && Indices == IndicesEnd)
107 // Given a struct type, recursively traverse the elements.
108 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
109 for (StructType::element_iterator EB = STy->element_begin(),
111 EE = STy->element_end();
113 if (Indices && *Indices == unsigned(EI - EB))
114 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
115 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
118 // Given an array type, recursively traverse the elements.
119 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
120 const Type *EltTy = ATy->getElementType();
121 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
122 if (Indices && *Indices == i)
123 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
124 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
127 // We haven't found the type we're looking for, so keep searching.
131 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
132 /// MVTs that represent all the individual underlying
133 /// non-aggregate types that comprise it.
135 /// If Offsets is non-null, it points to a vector to be filled in
136 /// with the in-memory offsets of each of the individual values.
138 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
139 SmallVectorImpl<MVT> &ValueVTs,
140 SmallVectorImpl<uint64_t> *Offsets = 0,
141 uint64_t StartingOffset = 0) {
142 // Given a struct type, recursively traverse the elements.
143 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
144 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
145 for (StructType::element_iterator EB = STy->element_begin(),
147 EE = STy->element_end();
149 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
150 StartingOffset + SL->getElementOffset(EI - EB));
153 // Given an array type, recursively traverse the elements.
154 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
155 const Type *EltTy = ATy->getElementType();
156 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
157 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
158 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
159 StartingOffset + i * EltSize);
162 // Base case: we can get an MVT for this LLVM IR type.
163 ValueVTs.push_back(TLI.getValueType(Ty));
165 Offsets->push_back(StartingOffset);
169 /// RegsForValue - This struct represents the registers (physical or virtual)
170 /// that a particular set of values is assigned, and the type information about
171 /// the value. The most common situation is to represent one value at a time,
172 /// but struct or array values are handled element-wise as multiple values.
173 /// The splitting of aggregates is performed recursively, so that we never
174 /// have aggregate-typed registers. The values at this point do not necessarily
175 /// have legal types, so each value may require one or more registers of some
178 struct VISIBILITY_HIDDEN RegsForValue {
179 /// TLI - The TargetLowering object.
181 const TargetLowering *TLI;
183 /// ValueVTs - The value types of the values, which may not be legal, and
184 /// may need be promoted or synthesized from one or more registers.
186 SmallVector<MVT, 4> ValueVTs;
188 /// RegVTs - The value types of the registers. This is the same size as
189 /// ValueVTs and it records, for each value, what the type of the assigned
190 /// register or registers are. (Individual values are never synthesized
191 /// from more than one type of register.)
193 /// With virtual registers, the contents of RegVTs is redundant with TLI's
194 /// getRegisterType member function, however when with physical registers
195 /// it is necessary to have a separate record of the types.
197 SmallVector<MVT, 4> RegVTs;
199 /// Regs - This list holds the registers assigned to the values.
200 /// Each legal or promoted value requires one register, and each
201 /// expanded value requires multiple registers.
203 SmallVector<unsigned, 4> Regs;
205 RegsForValue() : TLI(0) {}
207 RegsForValue(const TargetLowering &tli,
208 const SmallVector<unsigned, 4> ®s,
209 MVT regvt, MVT valuevt)
210 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
211 RegsForValue(const TargetLowering &tli,
212 const SmallVector<unsigned, 4> ®s,
213 const SmallVector<MVT, 4> ®vts,
214 const SmallVector<MVT, 4> &valuevts)
215 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
216 RegsForValue(const TargetLowering &tli,
217 unsigned Reg, const Type *Ty) : TLI(&tli) {
218 ComputeValueVTs(tli, Ty, ValueVTs);
220 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
221 MVT ValueVT = ValueVTs[Value];
222 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
223 MVT RegisterVT = TLI->getRegisterType(ValueVT);
224 for (unsigned i = 0; i != NumRegs; ++i)
225 Regs.push_back(Reg + i);
226 RegVTs.push_back(RegisterVT);
231 /// append - Add the specified values to this one.
232 void append(const RegsForValue &RHS) {
234 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
235 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
236 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
240 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
241 /// this value and returns the result as a ValueVTs value. This uses
242 /// Chain/Flag as the input and updates them for the output Chain/Flag.
243 /// If the Flag pointer is NULL, no flag is used.
244 SDOperand getCopyFromRegs(SelectionDAG &DAG,
245 SDOperand &Chain, SDOperand *Flag) const;
247 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
248 /// specified value into the registers specified by this object. This uses
249 /// Chain/Flag as the input and updates them for the output Chain/Flag.
250 /// If the Flag pointer is NULL, no flag is used.
251 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
252 SDOperand &Chain, SDOperand *Flag) const;
254 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
255 /// operand list. This adds the code marker and includes the number of
256 /// values added into it.
257 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
258 std::vector<SDOperand> &Ops) const;
263 //===--------------------------------------------------------------------===//
264 /// createDefaultScheduler - This creates an instruction scheduler appropriate
266 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
268 MachineBasicBlock *BB,
270 TargetLowering &TLI = IS->getTargetLowering();
272 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
273 return createTDListDAGScheduler(IS, DAG, BB, Fast);
275 assert(TLI.getSchedulingPreference() ==
276 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
277 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
282 //===--------------------------------------------------------------------===//
283 /// FunctionLoweringInfo - This contains information that is global to a
284 /// function that is used when lowering a region of the function.
285 class FunctionLoweringInfo {
290 MachineRegisterInfo &RegInfo;
292 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
294 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
295 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
297 /// ValueMap - Since we emit code for the function a basic block at a time,
298 /// we must remember which virtual registers hold the values for
299 /// cross-basic-block values.
300 DenseMap<const Value*, unsigned> ValueMap;
302 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
303 /// the entry block. This allows the allocas to be efficiently referenced
304 /// anywhere in the function.
305 std::map<const AllocaInst*, int> StaticAllocaMap;
308 SmallSet<Instruction*, 8> CatchInfoLost;
309 SmallSet<Instruction*, 8> CatchInfoFound;
312 unsigned MakeReg(MVT VT) {
313 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
316 /// isExportedInst - Return true if the specified value is an instruction
317 /// exported from its block.
318 bool isExportedInst(const Value *V) {
319 return ValueMap.count(V);
322 unsigned CreateRegForValue(const Value *V);
324 unsigned InitializeRegForValue(const Value *V) {
325 unsigned &R = ValueMap[V];
326 assert(R == 0 && "Already initialized this value register!");
327 return R = CreateRegForValue(V);
331 unsigned NumSignBits;
332 APInt KnownOne, KnownZero;
333 LiveOutInfo() : NumSignBits(0) {}
336 /// LiveOutRegInfo - Information about live out vregs, indexed by their
337 /// register number offset by 'FirstVirtualRegister'.
338 std::vector<LiveOutInfo> LiveOutRegInfo;
342 /// isSelector - Return true if this instruction is a call to the
343 /// eh.selector intrinsic.
344 static bool isSelector(Instruction *I) {
345 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
346 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
347 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
351 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
352 /// PHI nodes or outside of the basic block that defines it, or used by a
353 /// switch or atomic instruction, which may expand to multiple basic blocks.
354 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
355 if (isa<PHINode>(I)) return true;
356 BasicBlock *BB = I->getParent();
357 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
358 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
359 // FIXME: Remove switchinst special case.
360 isa<SwitchInst>(*UI))
365 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
366 /// entry block, return true. This includes arguments used by switches, since
367 /// the switch may expand into multiple basic blocks.
368 static bool isOnlyUsedInEntryBlock(Argument *A) {
369 BasicBlock *Entry = A->getParent()->begin();
370 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
371 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
372 return false; // Use not in entry block.
376 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
377 Function &fn, MachineFunction &mf)
378 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
380 // Create a vreg for each argument register that is not dead and is used
381 // outside of the entry block for the function.
382 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
384 if (!isOnlyUsedInEntryBlock(AI))
385 InitializeRegForValue(AI);
387 // Initialize the mapping of values to registers. This is only set up for
388 // instruction values that are used outside of the block that defines
390 Function::iterator BB = Fn.begin(), EB = Fn.end();
391 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
392 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
393 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
394 const Type *Ty = AI->getAllocatedType();
395 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
397 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
400 TySize *= CUI->getZExtValue(); // Get total allocated size.
401 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
402 StaticAllocaMap[AI] =
403 MF.getFrameInfo()->CreateStackObject(TySize, Align);
406 for (; BB != EB; ++BB)
407 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
408 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
409 if (!isa<AllocaInst>(I) ||
410 !StaticAllocaMap.count(cast<AllocaInst>(I)))
411 InitializeRegForValue(I);
413 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
414 // also creates the initial PHI MachineInstrs, though none of the input
415 // operands are populated.
416 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
417 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
421 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
424 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
425 if (PN->use_empty()) continue;
427 MVT VT = TLI.getValueType(PN->getType());
428 unsigned NumRegisters = TLI.getNumRegisters(VT);
429 unsigned PHIReg = ValueMap[PN];
430 assert(PHIReg && "PHI node does not have an assigned virtual register!");
431 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
432 for (unsigned i = 0; i != NumRegisters; ++i)
433 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
438 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
439 /// the correctly promoted or expanded types. Assign these registers
440 /// consecutive vreg numbers and return the first assigned number.
442 /// In the case that the given value has struct or array type, this function
443 /// will assign registers for each member or element.
445 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
446 SmallVector<MVT, 4> ValueVTs;
447 ComputeValueVTs(TLI, V->getType(), ValueVTs);
449 unsigned FirstReg = 0;
450 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
451 MVT ValueVT = ValueVTs[Value];
452 MVT RegisterVT = TLI.getRegisterType(ValueVT);
454 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
455 for (unsigned i = 0; i != NumRegs; ++i) {
456 unsigned R = MakeReg(RegisterVT);
457 if (!FirstReg) FirstReg = R;
463 //===----------------------------------------------------------------------===//
464 /// SelectionDAGLowering - This is the common target-independent lowering
465 /// implementation that is parameterized by a TargetLowering object.
466 /// Also, targets can overload any lowering method.
469 class SelectionDAGLowering {
470 MachineBasicBlock *CurMBB;
472 DenseMap<const Value*, SDOperand> NodeMap;
474 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
475 /// them up and then emit token factor nodes when possible. This allows us to
476 /// get simple disambiguation between loads without worrying about alias
478 SmallVector<SDOperand, 8> PendingLoads;
480 /// PendingExports - CopyToReg nodes that copy values to virtual registers
481 /// for export to other blocks need to be emitted before any terminator
482 /// instruction, but they have no other ordering requirements. We bunch them
483 /// up and the emit a single tokenfactor for them just before terminator
485 std::vector<SDOperand> PendingExports;
487 /// Case - A struct to record the Value for a switch case, and the
488 /// case's target basic block.
492 MachineBasicBlock* BB;
494 Case() : Low(0), High(0), BB(0) { }
495 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
496 Low(low), High(high), BB(bb) { }
497 uint64_t size() const {
498 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
499 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
500 return (rHigh - rLow + 1ULL);
506 MachineBasicBlock* BB;
509 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
510 Mask(mask), BB(bb), Bits(bits) { }
513 typedef std::vector<Case> CaseVector;
514 typedef std::vector<CaseBits> CaseBitsVector;
515 typedef CaseVector::iterator CaseItr;
516 typedef std::pair<CaseItr, CaseItr> CaseRange;
518 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
519 /// of conditional branches.
521 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
522 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
524 /// CaseBB - The MBB in which to emit the compare and branch
525 MachineBasicBlock *CaseBB;
526 /// LT, GE - If nonzero, we know the current case value must be less-than or
527 /// greater-than-or-equal-to these Constants.
530 /// Range - A pair of iterators representing the range of case values to be
531 /// processed at this point in the binary search tree.
535 typedef std::vector<CaseRec> CaseRecVector;
537 /// The comparison function for sorting the switch case values in the vector.
538 /// WARNING: Case ranges should be disjoint!
540 bool operator () (const Case& C1, const Case& C2) {
541 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
542 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
543 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
544 return CI1->getValue().slt(CI2->getValue());
549 bool operator () (const CaseBits& C1, const CaseBits& C2) {
550 return C1.Bits > C2.Bits;
554 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
557 // TLI - This is information that describes the available target features we
558 // need for lowering. This indicates when operations are unavailable,
559 // implemented with a libcall, etc.
562 const TargetData *TD;
565 /// SwitchCases - Vector of CaseBlock structures used to communicate
566 /// SwitchInst code generation information.
567 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
568 /// JTCases - Vector of JumpTable structures used to communicate
569 /// SwitchInst code generation information.
570 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
571 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
573 /// FuncInfo - Information about the function as a whole.
575 FunctionLoweringInfo &FuncInfo;
577 /// GCI - Garbage collection metadata for the function.
578 CollectorMetadata *GCI;
580 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
582 FunctionLoweringInfo &funcinfo,
583 CollectorMetadata *gci)
584 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
585 FuncInfo(funcinfo), GCI(gci) {
588 /// getRoot - Return the current virtual root of the Selection DAG,
589 /// flushing any PendingLoad items. This must be done before emitting
590 /// a store or any other node that may need to be ordered after any
591 /// prior load instructions.
593 SDOperand getRoot() {
594 if (PendingLoads.empty())
595 return DAG.getRoot();
597 if (PendingLoads.size() == 1) {
598 SDOperand Root = PendingLoads[0];
600 PendingLoads.clear();
604 // Otherwise, we have to make a token factor node.
605 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
606 &PendingLoads[0], PendingLoads.size());
607 PendingLoads.clear();
612 /// getControlRoot - Similar to getRoot, but instead of flushing all the
613 /// PendingLoad items, flush all the PendingExports items. It is necessary
614 /// to do this before emitting a terminator instruction.
616 SDOperand getControlRoot() {
617 SDOperand Root = DAG.getRoot();
619 if (PendingExports.empty())
622 // Turn all of the CopyToReg chains into one factored node.
623 if (Root.getOpcode() != ISD::EntryToken) {
624 unsigned i = 0, e = PendingExports.size();
625 for (; i != e; ++i) {
626 assert(PendingExports[i].Val->getNumOperands() > 1);
627 if (PendingExports[i].Val->getOperand(0) == Root)
628 break; // Don't add the root if we already indirectly depend on it.
632 PendingExports.push_back(Root);
635 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
637 PendingExports.size());
638 PendingExports.clear();
643 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
645 void visit(Instruction &I) { visit(I.getOpcode(), I); }
647 void visit(unsigned Opcode, User &I) {
648 // Note: this doesn't use InstVisitor, because it has to work with
649 // ConstantExpr's in addition to instructions.
651 default: assert(0 && "Unknown instruction type encountered!");
653 // Build the switch statement using the Instruction.def file.
654 #define HANDLE_INST(NUM, OPCODE, CLASS) \
655 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
656 #include "llvm/Instruction.def"
660 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
662 SDOperand getValue(const Value *V);
664 void setValue(const Value *V, SDOperand NewN) {
665 SDOperand &N = NodeMap[V];
666 assert(N.Val == 0 && "Already set a value for this node!");
670 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
671 std::set<unsigned> &OutputRegs,
672 std::set<unsigned> &InputRegs);
674 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
675 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
677 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
678 void ExportFromCurrentBlock(Value *V);
679 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
680 MachineBasicBlock *LandingPad = NULL);
682 // Terminator instructions.
683 void visitRet(ReturnInst &I);
684 void visitBr(BranchInst &I);
685 void visitSwitch(SwitchInst &I);
686 void visitUnreachable(UnreachableInst &I) { /* noop */ }
688 // Helpers for visitSwitch
689 bool handleSmallSwitchRange(CaseRec& CR,
690 CaseRecVector& WorkList,
692 MachineBasicBlock* Default);
693 bool handleJTSwitchCase(CaseRec& CR,
694 CaseRecVector& WorkList,
696 MachineBasicBlock* Default);
697 bool handleBTSplitSwitchCase(CaseRec& CR,
698 CaseRecVector& WorkList,
700 MachineBasicBlock* Default);
701 bool handleBitTestsSwitchCase(CaseRec& CR,
702 CaseRecVector& WorkList,
704 MachineBasicBlock* Default);
705 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
706 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
707 void visitBitTestCase(MachineBasicBlock* NextMBB,
709 SelectionDAGISel::BitTestCase &B);
710 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
711 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
712 SelectionDAGISel::JumpTableHeader &JTH);
714 // These all get lowered before this pass.
715 void visitInvoke(InvokeInst &I);
716 void visitUnwind(UnwindInst &I);
718 void visitBinary(User &I, unsigned OpCode);
719 void visitShift(User &I, unsigned Opcode);
720 void visitAdd(User &I) {
721 if (I.getType()->isFPOrFPVector())
722 visitBinary(I, ISD::FADD);
724 visitBinary(I, ISD::ADD);
726 void visitSub(User &I);
727 void visitMul(User &I) {
728 if (I.getType()->isFPOrFPVector())
729 visitBinary(I, ISD::FMUL);
731 visitBinary(I, ISD::MUL);
733 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
734 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
735 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
736 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
737 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
738 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
739 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
740 void visitOr (User &I) { visitBinary(I, ISD::OR); }
741 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
742 void visitShl (User &I) { visitShift(I, ISD::SHL); }
743 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
744 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
745 void visitICmp(User &I);
746 void visitFCmp(User &I);
747 void visitVICmp(User &I);
748 void visitVFCmp(User &I);
749 // Visit the conversion instructions
750 void visitTrunc(User &I);
751 void visitZExt(User &I);
752 void visitSExt(User &I);
753 void visitFPTrunc(User &I);
754 void visitFPExt(User &I);
755 void visitFPToUI(User &I);
756 void visitFPToSI(User &I);
757 void visitUIToFP(User &I);
758 void visitSIToFP(User &I);
759 void visitPtrToInt(User &I);
760 void visitIntToPtr(User &I);
761 void visitBitCast(User &I);
763 void visitExtractElement(User &I);
764 void visitInsertElement(User &I);
765 void visitShuffleVector(User &I);
767 void visitExtractValue(ExtractValueInst &I);
768 void visitInsertValue(InsertValueInst &I);
770 void visitGetElementPtr(User &I);
771 void visitSelect(User &I);
773 void visitMalloc(MallocInst &I);
774 void visitFree(FreeInst &I);
775 void visitAlloca(AllocaInst &I);
776 void visitLoad(LoadInst &I);
777 void visitStore(StoreInst &I);
778 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
779 void visitCall(CallInst &I);
780 void visitInlineAsm(CallSite CS);
781 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
782 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
784 void visitVAStart(CallInst &I);
785 void visitVAArg(VAArgInst &I);
786 void visitVAEnd(CallInst &I);
787 void visitVACopy(CallInst &I);
789 void visitGetResult(GetResultInst &I);
791 void visitUserOp1(Instruction &I) {
792 assert(0 && "UserOp1 should not exist at instruction selection time!");
795 void visitUserOp2(Instruction &I) {
796 assert(0 && "UserOp2 should not exist at instruction selection time!");
801 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
804 } // end namespace llvm
807 /// getCopyFromParts - Create a value that contains the specified legal parts
808 /// combined into the value they represent. If the parts combine to a type
809 /// larger then ValueVT then AssertOp can be used to specify whether the extra
810 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
811 /// (ISD::AssertSext).
812 static SDOperand getCopyFromParts(SelectionDAG &DAG,
813 const SDOperand *Parts,
817 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
818 assert(NumParts > 0 && "No parts to assemble!");
819 TargetLowering &TLI = DAG.getTargetLoweringInfo();
820 SDOperand Val = Parts[0];
823 // Assemble the value from multiple parts.
824 if (!ValueVT.isVector()) {
825 unsigned PartBits = PartVT.getSizeInBits();
826 unsigned ValueBits = ValueVT.getSizeInBits();
828 // Assemble the power of 2 part.
829 unsigned RoundParts = NumParts & (NumParts - 1) ?
830 1 << Log2_32(NumParts) : NumParts;
831 unsigned RoundBits = PartBits * RoundParts;
832 MVT RoundVT = RoundBits == ValueBits ?
833 ValueVT : MVT::getIntegerVT(RoundBits);
836 if (RoundParts > 2) {
837 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
838 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
839 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
845 if (TLI.isBigEndian())
847 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
849 if (RoundParts < NumParts) {
850 // Assemble the trailing non-power-of-2 part.
851 unsigned OddParts = NumParts - RoundParts;
852 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
853 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
855 // Combine the round and odd parts.
857 if (TLI.isBigEndian())
859 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
860 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
861 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
862 DAG.getConstant(Lo.getValueType().getSizeInBits(),
863 TLI.getShiftAmountTy()));
864 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
865 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
868 // Handle a multi-element vector.
869 MVT IntermediateVT, RegisterVT;
870 unsigned NumIntermediates;
872 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
874 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
875 NumParts = NumRegs; // Silence a compiler warning.
876 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
877 assert(RegisterVT == Parts[0].getValueType() &&
878 "Part type doesn't match part!");
880 // Assemble the parts into intermediate operands.
881 SmallVector<SDOperand, 8> Ops(NumIntermediates);
882 if (NumIntermediates == NumParts) {
883 // If the register was not expanded, truncate or copy the value,
885 for (unsigned i = 0; i != NumParts; ++i)
886 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
887 PartVT, IntermediateVT);
888 } else if (NumParts > 0) {
889 // If the intermediate type was expanded, build the intermediate operands
891 assert(NumParts % NumIntermediates == 0 &&
892 "Must expand into a divisible number of parts!");
893 unsigned Factor = NumParts / NumIntermediates;
894 for (unsigned i = 0; i != NumIntermediates; ++i)
895 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
896 PartVT, IntermediateVT);
899 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
901 Val = DAG.getNode(IntermediateVT.isVector() ?
902 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
903 ValueVT, &Ops[0], NumIntermediates);
907 // There is now one part, held in Val. Correct it to match ValueVT.
908 PartVT = Val.getValueType();
910 if (PartVT == ValueVT)
913 if (PartVT.isVector()) {
914 assert(ValueVT.isVector() && "Unknown vector conversion!");
915 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
918 if (ValueVT.isVector()) {
919 assert(ValueVT.getVectorElementType() == PartVT &&
920 ValueVT.getVectorNumElements() == 1 &&
921 "Only trivial scalar-to-vector conversions should get here!");
922 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
925 if (PartVT.isInteger() &&
926 ValueVT.isInteger()) {
927 if (ValueVT.bitsLT(PartVT)) {
928 // For a truncate, see if we have any information to
929 // indicate whether the truncated bits will always be
930 // zero or sign-extension.
931 if (AssertOp != ISD::DELETED_NODE)
932 Val = DAG.getNode(AssertOp, PartVT, Val,
933 DAG.getValueType(ValueVT));
934 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
936 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
940 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
941 if (ValueVT.bitsLT(Val.getValueType()))
942 // FP_ROUND's are always exact here.
943 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
944 DAG.getIntPtrConstant(1));
945 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
948 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
949 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
951 assert(0 && "Unknown mismatch!");
955 /// getCopyToParts - Create a series of nodes that contain the specified value
956 /// split into legal parts. If the parts contain more bits than Val, then, for
957 /// integers, ExtendKind can be used to specify how to generate the extra bits.
958 static void getCopyToParts(SelectionDAG &DAG,
963 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
964 TargetLowering &TLI = DAG.getTargetLoweringInfo();
965 MVT PtrVT = TLI.getPointerTy();
966 MVT ValueVT = Val.getValueType();
967 unsigned PartBits = PartVT.getSizeInBits();
968 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
973 if (!ValueVT.isVector()) {
974 if (PartVT == ValueVT) {
975 assert(NumParts == 1 && "No-op copy with multiple parts!");
980 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
981 // If the parts cover more bits than the value has, promote the value.
982 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
983 assert(NumParts == 1 && "Do not know what to promote to!");
984 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
985 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
986 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
987 Val = DAG.getNode(ExtendKind, ValueVT, Val);
989 assert(0 && "Unknown mismatch!");
991 } else if (PartBits == ValueVT.getSizeInBits()) {
992 // Different types of the same size.
993 assert(NumParts == 1 && PartVT != ValueVT);
994 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
995 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
996 // If the parts cover less bits than value has, truncate the value.
997 if (PartVT.isInteger() && ValueVT.isInteger()) {
998 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
999 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1001 assert(0 && "Unknown mismatch!");
1005 // The value may have changed - recompute ValueVT.
1006 ValueVT = Val.getValueType();
1007 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
1008 "Failed to tile the value with PartVT!");
1010 if (NumParts == 1) {
1011 assert(PartVT == ValueVT && "Type conversion failed!");
1016 // Expand the value into multiple parts.
1017 if (NumParts & (NumParts - 1)) {
1018 // The number of parts is not a power of 2. Split off and copy the tail.
1019 assert(PartVT.isInteger() && ValueVT.isInteger() &&
1020 "Do not know what to expand to!");
1021 unsigned RoundParts = 1 << Log2_32(NumParts);
1022 unsigned RoundBits = RoundParts * PartBits;
1023 unsigned OddParts = NumParts - RoundParts;
1024 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
1025 DAG.getConstant(RoundBits,
1026 TLI.getShiftAmountTy()));
1027 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1028 if (TLI.isBigEndian())
1029 // The odd parts were reversed by getCopyToParts - unreverse them.
1030 std::reverse(Parts + RoundParts, Parts + NumParts);
1031 NumParts = RoundParts;
1032 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1033 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1036 // The number of parts is a power of 2. Repeatedly bisect the value using
1038 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
1039 MVT::getIntegerVT(ValueVT.getSizeInBits()),
1041 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1042 for (unsigned i = 0; i < NumParts; i += StepSize) {
1043 unsigned ThisBits = StepSize * PartBits / 2;
1044 MVT ThisVT = MVT::getIntegerVT (ThisBits);
1045 SDOperand &Part0 = Parts[i];
1046 SDOperand &Part1 = Parts[i+StepSize/2];
1048 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1049 DAG.getConstant(1, PtrVT));
1050 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1051 DAG.getConstant(0, PtrVT));
1053 if (ThisBits == PartBits && ThisVT != PartVT) {
1054 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1055 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1060 if (TLI.isBigEndian())
1061 std::reverse(Parts, Parts + NumParts);
1067 if (NumParts == 1) {
1068 if (PartVT != ValueVT) {
1069 if (PartVT.isVector()) {
1070 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1072 assert(ValueVT.getVectorElementType() == PartVT &&
1073 ValueVT.getVectorNumElements() == 1 &&
1074 "Only trivial vector-to-scalar conversions should get here!");
1075 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1076 DAG.getConstant(0, PtrVT));
1084 // Handle a multi-element vector.
1085 MVT IntermediateVT, RegisterVT;
1086 unsigned NumIntermediates;
1088 DAG.getTargetLoweringInfo()
1089 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1091 unsigned NumElements = ValueVT.getVectorNumElements();
1093 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1094 NumParts = NumRegs; // Silence a compiler warning.
1095 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1097 // Split the vector into intermediate operands.
1098 SmallVector<SDOperand, 8> Ops(NumIntermediates);
1099 for (unsigned i = 0; i != NumIntermediates; ++i)
1100 if (IntermediateVT.isVector())
1101 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1102 IntermediateVT, Val,
1103 DAG.getConstant(i * (NumElements / NumIntermediates),
1106 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1107 IntermediateVT, Val,
1108 DAG.getConstant(i, PtrVT));
1110 // Split the intermediate operands into legal parts.
1111 if (NumParts == NumIntermediates) {
1112 // If the register was not expanded, promote or copy the value,
1114 for (unsigned i = 0; i != NumParts; ++i)
1115 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1116 } else if (NumParts > 0) {
1117 // If the intermediate type was expanded, split each the value into
1119 assert(NumParts % NumIntermediates == 0 &&
1120 "Must expand into a divisible number of parts!");
1121 unsigned Factor = NumParts / NumIntermediates;
1122 for (unsigned i = 0; i != NumIntermediates; ++i)
1123 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1128 SDOperand SelectionDAGLowering::getValue(const Value *V) {
1129 SDOperand &N = NodeMap[V];
1130 if (N.Val) return N;
1132 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1133 MVT VT = TLI.getValueType(V->getType(), true);
1135 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1136 return N = DAG.getConstant(CI->getValue(), VT);
1138 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1139 return N = DAG.getGlobalAddress(GV, VT);
1141 if (isa<ConstantPointerNull>(C))
1142 return N = DAG.getConstant(0, TLI.getPointerTy());
1144 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1145 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1147 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1148 !V->getType()->isAggregateType())
1149 return N = DAG.getNode(ISD::UNDEF, VT);
1151 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1152 visit(CE->getOpcode(), *CE);
1153 SDOperand N1 = NodeMap[V];
1154 assert(N1.Val && "visit didn't populate the ValueMap!");
1158 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1159 SmallVector<SDOperand, 4> Constants;
1160 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1162 SDNode *Val = getValue(*OI).Val;
1163 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1164 Constants.push_back(SDOperand(Val, i));
1166 return DAG.getMergeValues(&Constants[0], Constants.size());
1169 if (const ArrayType *ATy = dyn_cast<ArrayType>(C->getType())) {
1170 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1171 "Unknown array constant!");
1172 unsigned NumElts = ATy->getNumElements();
1174 return SDOperand(); // empty array
1175 MVT EltVT = TLI.getValueType(ATy->getElementType());
1176 SmallVector<SDOperand, 4> Constants(NumElts);
1177 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1178 if (isa<UndefValue>(C))
1179 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1180 else if (EltVT.isFloatingPoint())
1181 Constants[i] = DAG.getConstantFP(0, EltVT);
1183 Constants[i] = DAG.getConstant(0, EltVT);
1185 return DAG.getMergeValues(&Constants[0], Constants.size());
1188 if (const StructType *STy = dyn_cast<StructType>(C->getType())) {
1189 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1190 "Unknown struct constant!");
1191 unsigned NumElts = STy->getNumElements();
1193 return SDOperand(); // empty struct
1194 SmallVector<SDOperand, 4> Constants(NumElts);
1195 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1196 MVT EltVT = TLI.getValueType(STy->getElementType(i));
1197 if (isa<UndefValue>(C))
1198 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1199 else if (EltVT.isFloatingPoint())
1200 Constants[i] = DAG.getConstantFP(0, EltVT);
1202 Constants[i] = DAG.getConstant(0, EltVT);
1204 return DAG.getMergeValues(&Constants[0], Constants.size());
1207 const VectorType *VecTy = cast<VectorType>(V->getType());
1208 unsigned NumElements = VecTy->getNumElements();
1210 // Now that we know the number and type of the elements, get that number of
1211 // elements into the Ops array based on what kind of constant it is.
1212 SmallVector<SDOperand, 16> Ops;
1213 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1214 for (unsigned i = 0; i != NumElements; ++i)
1215 Ops.push_back(getValue(CP->getOperand(i)));
1217 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1218 "Unknown vector constant!");
1219 MVT EltVT = TLI.getValueType(VecTy->getElementType());
1222 if (isa<UndefValue>(C))
1223 Op = DAG.getNode(ISD::UNDEF, EltVT);
1224 else if (EltVT.isFloatingPoint())
1225 Op = DAG.getConstantFP(0, EltVT);
1227 Op = DAG.getConstant(0, EltVT);
1228 Ops.assign(NumElements, Op);
1231 // Create a BUILD_VECTOR node.
1232 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1235 // If this is a static alloca, generate it as the frameindex instead of
1237 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1238 std::map<const AllocaInst*, int>::iterator SI =
1239 FuncInfo.StaticAllocaMap.find(AI);
1240 if (SI != FuncInfo.StaticAllocaMap.end())
1241 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1244 unsigned InReg = FuncInfo.ValueMap[V];
1245 assert(InReg && "Value not in map!");
1247 RegsForValue RFV(TLI, InReg, V->getType());
1248 SDOperand Chain = DAG.getEntryNode();
1249 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1253 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1254 if (I.getNumOperands() == 0) {
1255 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1259 SmallVector<SDOperand, 8> NewValues;
1260 NewValues.push_back(getControlRoot());
1261 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1262 SDOperand RetOp = getValue(I.getOperand(i));
1264 SmallVector<MVT, 4> ValueVTs;
1265 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
1266 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
1267 MVT VT = ValueVTs[j];
1269 // FIXME: C calling convention requires the return type to be promoted to
1270 // at least 32-bit. But this is not necessary for non-C calling conventions.
1271 if (VT.isInteger()) {
1272 MVT MinVT = TLI.getRegisterType(MVT::i32);
1273 if (VT.bitsLT(MinVT))
1277 unsigned NumParts = TLI.getNumRegisters(VT);
1278 MVT PartVT = TLI.getRegisterType(VT);
1279 SmallVector<SDOperand, 4> Parts(NumParts);
1280 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1282 const Function *F = I.getParent()->getParent();
1283 if (F->paramHasAttr(0, ParamAttr::SExt))
1284 ExtendKind = ISD::SIGN_EXTEND;
1285 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1286 ExtendKind = ISD::ZERO_EXTEND;
1288 getCopyToParts(DAG, SDOperand(RetOp.Val, RetOp.ResNo + j),
1289 &Parts[0], NumParts, PartVT, ExtendKind);
1291 for (unsigned i = 0; i < NumParts; ++i) {
1292 NewValues.push_back(Parts[i]);
1293 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1297 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1298 &NewValues[0], NewValues.size()));
1301 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1302 /// the current basic block, add it to ValueMap now so that we'll get a
1304 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1305 // No need to export constants.
1306 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1308 // Already exported?
1309 if (FuncInfo.isExportedInst(V)) return;
1311 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1312 CopyValueToVirtualRegister(V, Reg);
1315 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1316 const BasicBlock *FromBB) {
1317 // The operands of the setcc have to be in this block. We don't know
1318 // how to export them from some other block.
1319 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1320 // Can export from current BB.
1321 if (VI->getParent() == FromBB)
1324 // Is already exported, noop.
1325 return FuncInfo.isExportedInst(V);
1328 // If this is an argument, we can export it if the BB is the entry block or
1329 // if it is already exported.
1330 if (isa<Argument>(V)) {
1331 if (FromBB == &FromBB->getParent()->getEntryBlock())
1334 // Otherwise, can only export this if it is already exported.
1335 return FuncInfo.isExportedInst(V);
1338 // Otherwise, constants can always be exported.
1342 static bool InBlock(const Value *V, const BasicBlock *BB) {
1343 if (const Instruction *I = dyn_cast<Instruction>(V))
1344 return I->getParent() == BB;
1348 /// FindMergedConditions - If Cond is an expression like
1349 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1350 MachineBasicBlock *TBB,
1351 MachineBasicBlock *FBB,
1352 MachineBasicBlock *CurBB,
1354 // If this node is not part of the or/and tree, emit it as a branch.
1355 Instruction *BOp = dyn_cast<Instruction>(Cond);
1357 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1358 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1359 BOp->getParent() != CurBB->getBasicBlock() ||
1360 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1361 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1362 const BasicBlock *BB = CurBB->getBasicBlock();
1364 // If the leaf of the tree is a comparison, merge the condition into
1366 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1367 // The operands of the cmp have to be in this block. We don't know
1368 // how to export them from some other block. If this is the first block
1369 // of the sequence, no exporting is needed.
1371 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1372 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1373 BOp = cast<Instruction>(Cond);
1374 ISD::CondCode Condition;
1375 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1376 switch (IC->getPredicate()) {
1377 default: assert(0 && "Unknown icmp predicate opcode!");
1378 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1379 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1380 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1381 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1382 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1383 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1384 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1385 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1386 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1387 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1389 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1390 ISD::CondCode FPC, FOC;
1391 switch (FC->getPredicate()) {
1392 default: assert(0 && "Unknown fcmp predicate opcode!");
1393 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1394 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1395 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1396 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1397 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1398 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1399 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1400 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1401 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1402 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1403 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1404 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1405 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1406 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1407 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1408 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1410 if (FiniteOnlyFPMath())
1415 Condition = ISD::SETEQ; // silence warning.
1416 assert(0 && "Unknown compare instruction");
1419 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1420 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1421 SwitchCases.push_back(CB);
1425 // Create a CaseBlock record representing this branch.
1426 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1427 NULL, TBB, FBB, CurBB);
1428 SwitchCases.push_back(CB);
1433 // Create TmpBB after CurBB.
1434 MachineFunction::iterator BBI = CurBB;
1435 MachineFunction &MF = DAG.getMachineFunction();
1436 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1437 CurBB->getParent()->insert(++BBI, TmpBB);
1439 if (Opc == Instruction::Or) {
1440 // Codegen X | Y as:
1448 // Emit the LHS condition.
1449 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1451 // Emit the RHS condition into TmpBB.
1452 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1454 assert(Opc == Instruction::And && "Unknown merge op!");
1455 // Codegen X & Y as:
1462 // This requires creation of TmpBB after CurBB.
1464 // Emit the LHS condition.
1465 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1467 // Emit the RHS condition into TmpBB.
1468 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1472 /// If the set of cases should be emitted as a series of branches, return true.
1473 /// If we should emit this as a bunch of and/or'd together conditions, return
1476 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1477 if (Cases.size() != 2) return true;
1479 // If this is two comparisons of the same values or'd or and'd together, they
1480 // will get folded into a single comparison, so don't emit two blocks.
1481 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1482 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1483 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1484 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1491 void SelectionDAGLowering::visitBr(BranchInst &I) {
1492 // Update machine-CFG edges.
1493 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1495 // Figure out which block is immediately after the current one.
1496 MachineBasicBlock *NextBlock = 0;
1497 MachineFunction::iterator BBI = CurMBB;
1498 if (++BBI != CurMBB->getParent()->end())
1501 if (I.isUnconditional()) {
1502 // Update machine-CFG edges.
1503 CurMBB->addSuccessor(Succ0MBB);
1505 // If this is not a fall-through branch, emit the branch.
1506 if (Succ0MBB != NextBlock)
1507 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1508 DAG.getBasicBlock(Succ0MBB)));
1512 // If this condition is one of the special cases we handle, do special stuff
1514 Value *CondVal = I.getCondition();
1515 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1517 // If this is a series of conditions that are or'd or and'd together, emit
1518 // this as a sequence of branches instead of setcc's with and/or operations.
1519 // For example, instead of something like:
1532 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1533 if (BOp->hasOneUse() &&
1534 (BOp->getOpcode() == Instruction::And ||
1535 BOp->getOpcode() == Instruction::Or)) {
1536 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1537 // If the compares in later blocks need to use values not currently
1538 // exported from this block, export them now. This block should always
1539 // be the first entry.
1540 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1542 // Allow some cases to be rejected.
1543 if (ShouldEmitAsBranches(SwitchCases)) {
1544 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1545 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1546 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1549 // Emit the branch for this block.
1550 visitSwitchCase(SwitchCases[0]);
1551 SwitchCases.erase(SwitchCases.begin());
1555 // Okay, we decided not to do this, remove any inserted MBB's and clear
1557 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1558 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1560 SwitchCases.clear();
1564 // Create a CaseBlock record representing this branch.
1565 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1566 NULL, Succ0MBB, Succ1MBB, CurMBB);
1567 // Use visitSwitchCase to actually insert the fast branch sequence for this
1569 visitSwitchCase(CB);
1572 /// visitSwitchCase - Emits the necessary code to represent a single node in
1573 /// the binary search tree resulting from lowering a switch instruction.
1574 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1576 SDOperand CondLHS = getValue(CB.CmpLHS);
1578 // Build the setcc now.
1579 if (CB.CmpMHS == NULL) {
1580 // Fold "(X == true)" to X and "(X == false)" to !X to
1581 // handle common cases produced by branch lowering.
1582 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1584 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1585 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1586 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1588 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1590 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1592 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1593 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1595 SDOperand CmpOp = getValue(CB.CmpMHS);
1596 MVT VT = CmpOp.getValueType();
1598 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1599 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1601 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1602 Cond = DAG.getSetCC(MVT::i1, SUB,
1603 DAG.getConstant(High-Low, VT), ISD::SETULE);
1607 // Update successor info
1608 CurMBB->addSuccessor(CB.TrueBB);
1609 CurMBB->addSuccessor(CB.FalseBB);
1611 // Set NextBlock to be the MBB immediately after the current one, if any.
1612 // This is used to avoid emitting unnecessary branches to the next block.
1613 MachineBasicBlock *NextBlock = 0;
1614 MachineFunction::iterator BBI = CurMBB;
1615 if (++BBI != CurMBB->getParent()->end())
1618 // If the lhs block is the next block, invert the condition so that we can
1619 // fall through to the lhs instead of the rhs block.
1620 if (CB.TrueBB == NextBlock) {
1621 std::swap(CB.TrueBB, CB.FalseBB);
1622 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1623 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1625 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1626 DAG.getBasicBlock(CB.TrueBB));
1627 if (CB.FalseBB == NextBlock)
1628 DAG.setRoot(BrCond);
1630 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1631 DAG.getBasicBlock(CB.FalseBB)));
1634 /// visitJumpTable - Emit JumpTable node in the current MBB
1635 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1636 // Emit the code for the jump table
1637 assert(JT.Reg != -1U && "Should lower JT Header first!");
1638 MVT PTy = TLI.getPointerTy();
1639 SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1640 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1641 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1646 /// visitJumpTableHeader - This function emits necessary code to produce index
1647 /// in the JumpTable from switch case.
1648 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1649 SelectionDAGISel::JumpTableHeader &JTH) {
1650 // Subtract the lowest switch case value from the value being switched on
1651 // and conditional branch to default mbb if the result is greater than the
1652 // difference between smallest and largest cases.
1653 SDOperand SwitchOp = getValue(JTH.SValue);
1654 MVT VT = SwitchOp.getValueType();
1655 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1656 DAG.getConstant(JTH.First, VT));
1658 // The SDNode we just created, which holds the value being switched on
1659 // minus the the smallest case value, needs to be copied to a virtual
1660 // register so it can be used as an index into the jump table in a
1661 // subsequent basic block. This value may be smaller or larger than the
1662 // target's pointer type, and therefore require extension or truncating.
1663 if (VT.bitsGT(TLI.getPointerTy()))
1664 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1666 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1668 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1669 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1670 JT.Reg = JumpTableReg;
1672 // Emit the range check for the jump table, and branch to the default
1673 // block for the switch statement if the value being switched on exceeds
1674 // the largest case in the switch.
1675 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1676 DAG.getConstant(JTH.Last-JTH.First,VT),
1679 // Set NextBlock to be the MBB immediately after the current one, if any.
1680 // This is used to avoid emitting unnecessary branches to the next block.
1681 MachineBasicBlock *NextBlock = 0;
1682 MachineFunction::iterator BBI = CurMBB;
1683 if (++BBI != CurMBB->getParent()->end())
1686 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1687 DAG.getBasicBlock(JT.Default));
1689 if (JT.MBB == NextBlock)
1690 DAG.setRoot(BrCond);
1692 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1693 DAG.getBasicBlock(JT.MBB)));
1698 /// visitBitTestHeader - This function emits necessary code to produce value
1699 /// suitable for "bit tests"
1700 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1701 // Subtract the minimum value
1702 SDOperand SwitchOp = getValue(B.SValue);
1703 MVT VT = SwitchOp.getValueType();
1704 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1705 DAG.getConstant(B.First, VT));
1708 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1709 DAG.getConstant(B.Range, VT),
1713 if (VT.bitsGT(TLI.getShiftAmountTy()))
1714 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1716 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1718 // Make desired shift
1719 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1720 DAG.getConstant(1, TLI.getPointerTy()),
1723 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1724 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1727 // Set NextBlock to be the MBB immediately after the current one, if any.
1728 // This is used to avoid emitting unnecessary branches to the next block.
1729 MachineBasicBlock *NextBlock = 0;
1730 MachineFunction::iterator BBI = CurMBB;
1731 if (++BBI != CurMBB->getParent()->end())
1734 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1736 CurMBB->addSuccessor(B.Default);
1737 CurMBB->addSuccessor(MBB);
1739 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1740 DAG.getBasicBlock(B.Default));
1742 if (MBB == NextBlock)
1743 DAG.setRoot(BrRange);
1745 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1746 DAG.getBasicBlock(MBB)));
1751 /// visitBitTestCase - this function produces one "bit test"
1752 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1754 SelectionDAGISel::BitTestCase &B) {
1755 // Emit bit tests and jumps
1756 SDOperand SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1757 TLI.getPointerTy());
1759 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1760 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1761 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1762 DAG.getConstant(0, TLI.getPointerTy()),
1765 CurMBB->addSuccessor(B.TargetBB);
1766 CurMBB->addSuccessor(NextMBB);
1768 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1769 AndCmp, DAG.getBasicBlock(B.TargetBB));
1771 // Set NextBlock to be the MBB immediately after the current one, if any.
1772 // This is used to avoid emitting unnecessary branches to the next block.
1773 MachineBasicBlock *NextBlock = 0;
1774 MachineFunction::iterator BBI = CurMBB;
1775 if (++BBI != CurMBB->getParent()->end())
1778 if (NextMBB == NextBlock)
1781 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1782 DAG.getBasicBlock(NextMBB)));
1787 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1788 // Retrieve successors.
1789 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1790 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1792 if (isa<InlineAsm>(I.getCalledValue()))
1795 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1797 // If the value of the invoke is used outside of its defining block, make it
1798 // available as a virtual register.
1799 if (!I.use_empty()) {
1800 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1801 if (VMI != FuncInfo.ValueMap.end())
1802 CopyValueToVirtualRegister(&I, VMI->second);
1805 // Update successor info
1806 CurMBB->addSuccessor(Return);
1807 CurMBB->addSuccessor(LandingPad);
1809 // Drop into normal successor.
1810 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1811 DAG.getBasicBlock(Return)));
1814 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1817 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1818 /// small case ranges).
1819 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1820 CaseRecVector& WorkList,
1822 MachineBasicBlock* Default) {
1823 Case& BackCase = *(CR.Range.second-1);
1825 // Size is the number of Cases represented by this range.
1826 unsigned Size = CR.Range.second - CR.Range.first;
1830 // Get the MachineFunction which holds the current MBB. This is used when
1831 // inserting any additional MBBs necessary to represent the switch.
1832 MachineFunction *CurMF = CurMBB->getParent();
1834 // Figure out which block is immediately after the current one.
1835 MachineBasicBlock *NextBlock = 0;
1836 MachineFunction::iterator BBI = CR.CaseBB;
1838 if (++BBI != CurMBB->getParent()->end())
1841 // TODO: If any two of the cases has the same destination, and if one value
1842 // is the same as the other, but has one bit unset that the other has set,
1843 // use bit manipulation to do two compares at once. For example:
1844 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1846 // Rearrange the case blocks so that the last one falls through if possible.
1847 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1848 // The last case block won't fall through into 'NextBlock' if we emit the
1849 // branches in this order. See if rearranging a case value would help.
1850 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1851 if (I->BB == NextBlock) {
1852 std::swap(*I, BackCase);
1858 // Create a CaseBlock record representing a conditional branch to
1859 // the Case's target mbb if the value being switched on SV is equal
1861 MachineBasicBlock *CurBlock = CR.CaseBB;
1862 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1863 MachineBasicBlock *FallThrough;
1865 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1866 CurMF->insert(BBI, FallThrough);
1868 // If the last case doesn't match, go to the default block.
1869 FallThrough = Default;
1872 Value *RHS, *LHS, *MHS;
1874 if (I->High == I->Low) {
1875 // This is just small small case range :) containing exactly 1 case
1877 LHS = SV; RHS = I->High; MHS = NULL;
1880 LHS = I->Low; MHS = SV; RHS = I->High;
1882 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1883 I->BB, FallThrough, CurBlock);
1885 // If emitting the first comparison, just call visitSwitchCase to emit the
1886 // code into the current block. Otherwise, push the CaseBlock onto the
1887 // vector to be later processed by SDISel, and insert the node's MBB
1888 // before the next MBB.
1889 if (CurBlock == CurMBB)
1890 visitSwitchCase(CB);
1892 SwitchCases.push_back(CB);
1894 CurBlock = FallThrough;
1900 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1901 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1902 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1905 /// handleJTSwitchCase - Emit jumptable for current switch case range
1906 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1907 CaseRecVector& WorkList,
1909 MachineBasicBlock* Default) {
1910 Case& FrontCase = *CR.Range.first;
1911 Case& BackCase = *(CR.Range.second-1);
1913 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1914 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1917 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1921 if (!areJTsAllowed(TLI) || TSize <= 3)
1924 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1928 DOUT << "Lowering jump table\n"
1929 << "First entry: " << First << ". Last entry: " << Last << "\n"
1930 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1932 // Get the MachineFunction which holds the current MBB. This is used when
1933 // inserting any additional MBBs necessary to represent the switch.
1934 MachineFunction *CurMF = CurMBB->getParent();
1936 // Figure out which block is immediately after the current one.
1937 MachineBasicBlock *NextBlock = 0;
1938 MachineFunction::iterator BBI = CR.CaseBB;
1940 if (++BBI != CurMBB->getParent()->end())
1943 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1945 // Create a new basic block to hold the code for loading the address
1946 // of the jump table, and jumping to it. Update successor information;
1947 // we will either branch to the default case for the switch, or the jump
1949 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1950 CurMF->insert(BBI, JumpTableBB);
1951 CR.CaseBB->addSuccessor(Default);
1952 CR.CaseBB->addSuccessor(JumpTableBB);
1954 // Build a vector of destination BBs, corresponding to each target
1955 // of the jump table. If the value of the jump table slot corresponds to
1956 // a case statement, push the case's BB onto the vector, otherwise, push
1958 std::vector<MachineBasicBlock*> DestBBs;
1959 int64_t TEI = First;
1960 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1961 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1962 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1964 if ((Low <= TEI) && (TEI <= High)) {
1965 DestBBs.push_back(I->BB);
1969 DestBBs.push_back(Default);
1973 // Update successor info. Add one edge to each unique successor.
1974 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1975 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1976 E = DestBBs.end(); I != E; ++I) {
1977 if (!SuccsHandled[(*I)->getNumber()]) {
1978 SuccsHandled[(*I)->getNumber()] = true;
1979 JumpTableBB->addSuccessor(*I);
1983 // Create a jump table index for this jump table, or return an existing
1985 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1987 // Set the jump table information so that we can codegen it as a second
1988 // MachineBasicBlock
1989 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1990 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1991 (CR.CaseBB == CurMBB));
1992 if (CR.CaseBB == CurMBB)
1993 visitJumpTableHeader(JT, JTH);
1995 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
2000 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2002 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
2003 CaseRecVector& WorkList,
2005 MachineBasicBlock* Default) {
2006 // Get the MachineFunction which holds the current MBB. This is used when
2007 // inserting any additional MBBs necessary to represent the switch.
2008 MachineFunction *CurMF = CurMBB->getParent();
2010 // Figure out which block is immediately after the current one.
2011 MachineBasicBlock *NextBlock = 0;
2012 MachineFunction::iterator BBI = CR.CaseBB;
2014 if (++BBI != CurMBB->getParent()->end())
2017 Case& FrontCase = *CR.Range.first;
2018 Case& BackCase = *(CR.Range.second-1);
2019 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2021 // Size is the number of Cases represented by this range.
2022 unsigned Size = CR.Range.second - CR.Range.first;
2024 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2025 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2027 CaseItr Pivot = CR.Range.first + Size/2;
2029 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2030 // (heuristically) allow us to emit JumpTable's later.
2032 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2036 uint64_t LSize = FrontCase.size();
2037 uint64_t RSize = TSize-LSize;
2038 DOUT << "Selecting best pivot: \n"
2039 << "First: " << First << ", Last: " << Last <<"\n"
2040 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
2041 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2043 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2044 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
2045 assert((RBegin-LEnd>=1) && "Invalid case distance");
2046 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2047 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
2048 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
2049 // Should always split in some non-trivial place
2051 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2052 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2053 << "Metric: " << Metric << "\n";
2054 if (FMetric < Metric) {
2057 DOUT << "Current metric set to: " << FMetric << "\n";
2063 if (areJTsAllowed(TLI)) {
2064 // If our case is dense we *really* should handle it earlier!
2065 assert((FMetric > 0) && "Should handle dense range earlier!");
2067 Pivot = CR.Range.first + Size/2;
2070 CaseRange LHSR(CR.Range.first, Pivot);
2071 CaseRange RHSR(Pivot, CR.Range.second);
2072 Constant *C = Pivot->Low;
2073 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2075 // We know that we branch to the LHS if the Value being switched on is
2076 // less than the Pivot value, C. We use this to optimize our binary
2077 // tree a bit, by recognizing that if SV is greater than or equal to the
2078 // LHS's Case Value, and that Case Value is exactly one less than the
2079 // Pivot's Value, then we can branch directly to the LHS's Target,
2080 // rather than creating a leaf node for it.
2081 if ((LHSR.second - LHSR.first) == 1 &&
2082 LHSR.first->High == CR.GE &&
2083 cast<ConstantInt>(C)->getSExtValue() ==
2084 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2085 TrueBB = LHSR.first->BB;
2087 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2088 CurMF->insert(BBI, TrueBB);
2089 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2092 // Similar to the optimization above, if the Value being switched on is
2093 // known to be less than the Constant CR.LT, and the current Case Value
2094 // is CR.LT - 1, then we can branch directly to the target block for
2095 // the current Case Value, rather than emitting a RHS leaf node for it.
2096 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2097 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2098 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2099 FalseBB = RHSR.first->BB;
2101 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2102 CurMF->insert(BBI, FalseBB);
2103 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2106 // Create a CaseBlock record representing a conditional branch to
2107 // the LHS node if the value being switched on SV is less than C.
2108 // Otherwise, branch to LHS.
2109 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
2110 TrueBB, FalseBB, CR.CaseBB);
2112 if (CR.CaseBB == CurMBB)
2113 visitSwitchCase(CB);
2115 SwitchCases.push_back(CB);
2120 /// handleBitTestsSwitchCase - if current case range has few destination and
2121 /// range span less, than machine word bitwidth, encode case range into series
2122 /// of masks and emit bit tests with these masks.
2123 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2124 CaseRecVector& WorkList,
2126 MachineBasicBlock* Default){
2127 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
2129 Case& FrontCase = *CR.Range.first;
2130 Case& BackCase = *(CR.Range.second-1);
2132 // Get the MachineFunction which holds the current MBB. This is used when
2133 // inserting any additional MBBs necessary to represent the switch.
2134 MachineFunction *CurMF = CurMBB->getParent();
2136 unsigned numCmps = 0;
2137 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2139 // Single case counts one, case range - two.
2140 if (I->Low == I->High)
2146 // Count unique destinations
2147 SmallSet<MachineBasicBlock*, 4> Dests;
2148 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2149 Dests.insert(I->BB);
2150 if (Dests.size() > 3)
2151 // Don't bother the code below, if there are too much unique destinations
2154 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2155 << "Total number of comparisons: " << numCmps << "\n";
2157 // Compute span of values.
2158 Constant* minValue = FrontCase.Low;
2159 Constant* maxValue = BackCase.High;
2160 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2161 cast<ConstantInt>(minValue)->getSExtValue();
2162 DOUT << "Compare range: " << range << "\n"
2163 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2164 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2166 if (range>=IntPtrBits ||
2167 (!(Dests.size() == 1 && numCmps >= 3) &&
2168 !(Dests.size() == 2 && numCmps >= 5) &&
2169 !(Dests.size() >= 3 && numCmps >= 6)))
2172 DOUT << "Emitting bit tests\n";
2173 int64_t lowBound = 0;
2175 // Optimize the case where all the case values fit in a
2176 // word without having to subtract minValue. In this case,
2177 // we can optimize away the subtraction.
2178 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2179 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2180 range = cast<ConstantInt>(maxValue)->getSExtValue();
2182 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2185 CaseBitsVector CasesBits;
2186 unsigned i, count = 0;
2188 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2189 MachineBasicBlock* Dest = I->BB;
2190 for (i = 0; i < count; ++i)
2191 if (Dest == CasesBits[i].BB)
2195 assert((count < 3) && "Too much destinations to test!");
2196 CasesBits.push_back(CaseBits(0, Dest, 0));
2200 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2201 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2203 for (uint64_t j = lo; j <= hi; j++) {
2204 CasesBits[i].Mask |= 1ULL << j;
2205 CasesBits[i].Bits++;
2209 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2211 SelectionDAGISel::BitTestInfo BTC;
2213 // Figure out which block is immediately after the current one.
2214 MachineFunction::iterator BBI = CR.CaseBB;
2217 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2220 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2221 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2222 << ", BB: " << CasesBits[i].BB << "\n";
2224 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2225 CurMF->insert(BBI, CaseBB);
2226 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2231 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2232 -1U, (CR.CaseBB == CurMBB),
2233 CR.CaseBB, Default, BTC);
2235 if (CR.CaseBB == CurMBB)
2236 visitBitTestHeader(BTB);
2238 BitTestCases.push_back(BTB);
2244 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2245 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2246 const SwitchInst& SI) {
2247 unsigned numCmps = 0;
2249 // Start with "simple" cases
2250 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2251 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2252 Cases.push_back(Case(SI.getSuccessorValue(i),
2253 SI.getSuccessorValue(i),
2256 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2258 // Merge case into clusters
2259 if (Cases.size()>=2)
2260 // Must recompute end() each iteration because it may be
2261 // invalidated by erase if we hold on to it
2262 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2263 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2264 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2265 MachineBasicBlock* nextBB = J->BB;
2266 MachineBasicBlock* currentBB = I->BB;
2268 // If the two neighboring cases go to the same destination, merge them
2269 // into a single case.
2270 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2278 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2279 if (I->Low != I->High)
2280 // A range counts double, since it requires two compares.
2287 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2288 // Figure out which block is immediately after the current one.
2289 MachineBasicBlock *NextBlock = 0;
2290 MachineFunction::iterator BBI = CurMBB;
2292 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2294 // If there is only the default destination, branch to it if it is not the
2295 // next basic block. Otherwise, just fall through.
2296 if (SI.getNumOperands() == 2) {
2297 // Update machine-CFG edges.
2299 // If this is not a fall-through branch, emit the branch.
2300 CurMBB->addSuccessor(Default);
2301 if (Default != NextBlock)
2302 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2303 DAG.getBasicBlock(Default)));
2308 // If there are any non-default case statements, create a vector of Cases
2309 // representing each one, and sort the vector so that we can efficiently
2310 // create a binary search tree from them.
2312 unsigned numCmps = Clusterify(Cases, SI);
2313 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2314 << ". Total compares: " << numCmps << "\n";
2316 // Get the Value to be switched on and default basic blocks, which will be
2317 // inserted into CaseBlock records, representing basic blocks in the binary
2319 Value *SV = SI.getOperand(0);
2321 // Push the initial CaseRec onto the worklist
2322 CaseRecVector WorkList;
2323 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2325 while (!WorkList.empty()) {
2326 // Grab a record representing a case range to process off the worklist
2327 CaseRec CR = WorkList.back();
2328 WorkList.pop_back();
2330 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2333 // If the range has few cases (two or less) emit a series of specific
2335 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2338 // If the switch has more than 5 blocks, and at least 40% dense, and the
2339 // target supports indirect branches, then emit a jump table rather than
2340 // lowering the switch to a binary tree of conditional branches.
2341 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2344 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2345 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2346 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2351 void SelectionDAGLowering::visitSub(User &I) {
2352 // -0.0 - X --> fneg
2353 const Type *Ty = I.getType();
2354 if (isa<VectorType>(Ty)) {
2355 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2356 const VectorType *DestTy = cast<VectorType>(I.getType());
2357 const Type *ElTy = DestTy->getElementType();
2358 if (ElTy->isFloatingPoint()) {
2359 unsigned VL = DestTy->getNumElements();
2360 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2361 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2363 SDOperand Op2 = getValue(I.getOperand(1));
2364 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2370 if (Ty->isFloatingPoint()) {
2371 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2372 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2373 SDOperand Op2 = getValue(I.getOperand(1));
2374 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2379 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2382 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2383 SDOperand Op1 = getValue(I.getOperand(0));
2384 SDOperand Op2 = getValue(I.getOperand(1));
2386 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2389 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2390 SDOperand Op1 = getValue(I.getOperand(0));
2391 SDOperand Op2 = getValue(I.getOperand(1));
2393 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2394 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2395 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2396 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2398 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2401 void SelectionDAGLowering::visitICmp(User &I) {
2402 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2403 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2404 predicate = IC->getPredicate();
2405 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2406 predicate = ICmpInst::Predicate(IC->getPredicate());
2407 SDOperand Op1 = getValue(I.getOperand(0));
2408 SDOperand Op2 = getValue(I.getOperand(1));
2409 ISD::CondCode Opcode;
2410 switch (predicate) {
2411 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2412 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2413 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2414 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2415 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2416 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2417 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2418 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2419 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2420 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2422 assert(!"Invalid ICmp predicate value");
2423 Opcode = ISD::SETEQ;
2426 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2429 void SelectionDAGLowering::visitFCmp(User &I) {
2430 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2431 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2432 predicate = FC->getPredicate();
2433 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2434 predicate = FCmpInst::Predicate(FC->getPredicate());
2435 SDOperand Op1 = getValue(I.getOperand(0));
2436 SDOperand Op2 = getValue(I.getOperand(1));
2437 ISD::CondCode Condition, FOC, FPC;
2438 switch (predicate) {
2439 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2440 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2441 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2442 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2443 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2444 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2445 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2446 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2447 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2448 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2449 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2450 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2451 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2452 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2453 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2454 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2456 assert(!"Invalid FCmp predicate value");
2457 FOC = FPC = ISD::SETFALSE;
2460 if (FiniteOnlyFPMath())
2464 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2467 void SelectionDAGLowering::visitVICmp(User &I) {
2468 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2469 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2470 predicate = IC->getPredicate();
2471 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2472 predicate = ICmpInst::Predicate(IC->getPredicate());
2473 SDOperand Op1 = getValue(I.getOperand(0));
2474 SDOperand Op2 = getValue(I.getOperand(1));
2475 ISD::CondCode Opcode;
2476 switch (predicate) {
2477 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2478 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2479 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2480 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2481 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2482 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2483 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2484 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2485 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2486 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2488 assert(!"Invalid ICmp predicate value");
2489 Opcode = ISD::SETEQ;
2492 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2495 void SelectionDAGLowering::visitVFCmp(User &I) {
2496 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2497 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2498 predicate = FC->getPredicate();
2499 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2500 predicate = FCmpInst::Predicate(FC->getPredicate());
2501 SDOperand Op1 = getValue(I.getOperand(0));
2502 SDOperand Op2 = getValue(I.getOperand(1));
2503 ISD::CondCode Condition, FOC, FPC;
2504 switch (predicate) {
2505 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2506 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2507 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2508 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2509 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2510 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2511 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2512 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2513 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2514 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2515 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2516 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2517 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2518 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2519 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2520 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2522 assert(!"Invalid VFCmp predicate value");
2523 FOC = FPC = ISD::SETFALSE;
2526 if (FiniteOnlyFPMath())
2531 MVT DestVT = TLI.getValueType(I.getType());
2533 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2536 void SelectionDAGLowering::visitSelect(User &I) {
2537 SDOperand Cond = getValue(I.getOperand(0));
2538 SDOperand TrueVal = getValue(I.getOperand(1));
2539 SDOperand FalseVal = getValue(I.getOperand(2));
2540 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2541 TrueVal, FalseVal));
2545 void SelectionDAGLowering::visitTrunc(User &I) {
2546 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2547 SDOperand N = getValue(I.getOperand(0));
2548 MVT DestVT = TLI.getValueType(I.getType());
2549 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2552 void SelectionDAGLowering::visitZExt(User &I) {
2553 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2554 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2555 SDOperand N = getValue(I.getOperand(0));
2556 MVT DestVT = TLI.getValueType(I.getType());
2557 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2560 void SelectionDAGLowering::visitSExt(User &I) {
2561 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2562 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2563 SDOperand N = getValue(I.getOperand(0));
2564 MVT DestVT = TLI.getValueType(I.getType());
2565 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2568 void SelectionDAGLowering::visitFPTrunc(User &I) {
2569 // FPTrunc is never a no-op cast, no need to check
2570 SDOperand N = getValue(I.getOperand(0));
2571 MVT DestVT = TLI.getValueType(I.getType());
2572 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2575 void SelectionDAGLowering::visitFPExt(User &I){
2576 // FPTrunc is never a no-op cast, no need to check
2577 SDOperand N = getValue(I.getOperand(0));
2578 MVT DestVT = TLI.getValueType(I.getType());
2579 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2582 void SelectionDAGLowering::visitFPToUI(User &I) {
2583 // FPToUI is never a no-op cast, no need to check
2584 SDOperand N = getValue(I.getOperand(0));
2585 MVT DestVT = TLI.getValueType(I.getType());
2586 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2589 void SelectionDAGLowering::visitFPToSI(User &I) {
2590 // FPToSI is never a no-op cast, no need to check
2591 SDOperand N = getValue(I.getOperand(0));
2592 MVT DestVT = TLI.getValueType(I.getType());
2593 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2596 void SelectionDAGLowering::visitUIToFP(User &I) {
2597 // UIToFP is never a no-op cast, no need to check
2598 SDOperand N = getValue(I.getOperand(0));
2599 MVT DestVT = TLI.getValueType(I.getType());
2600 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2603 void SelectionDAGLowering::visitSIToFP(User &I){
2604 // UIToFP is never a no-op cast, no need to check
2605 SDOperand N = getValue(I.getOperand(0));
2606 MVT DestVT = TLI.getValueType(I.getType());
2607 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2610 void SelectionDAGLowering::visitPtrToInt(User &I) {
2611 // What to do depends on the size of the integer and the size of the pointer.
2612 // We can either truncate, zero extend, or no-op, accordingly.
2613 SDOperand N = getValue(I.getOperand(0));
2614 MVT SrcVT = N.getValueType();
2615 MVT DestVT = TLI.getValueType(I.getType());
2617 if (DestVT.bitsLT(SrcVT))
2618 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2620 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2621 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2622 setValue(&I, Result);
2625 void SelectionDAGLowering::visitIntToPtr(User &I) {
2626 // What to do depends on the size of the integer and the size of the pointer.
2627 // We can either truncate, zero extend, or no-op, accordingly.
2628 SDOperand N = getValue(I.getOperand(0));
2629 MVT SrcVT = N.getValueType();
2630 MVT DestVT = TLI.getValueType(I.getType());
2631 if (DestVT.bitsLT(SrcVT))
2632 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2634 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2635 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2638 void SelectionDAGLowering::visitBitCast(User &I) {
2639 SDOperand N = getValue(I.getOperand(0));
2640 MVT DestVT = TLI.getValueType(I.getType());
2642 // BitCast assures us that source and destination are the same size so this
2643 // is either a BIT_CONVERT or a no-op.
2644 if (DestVT != N.getValueType())
2645 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2647 setValue(&I, N); // noop cast.
2650 void SelectionDAGLowering::visitInsertElement(User &I) {
2651 SDOperand InVec = getValue(I.getOperand(0));
2652 SDOperand InVal = getValue(I.getOperand(1));
2653 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2654 getValue(I.getOperand(2)));
2656 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2657 TLI.getValueType(I.getType()),
2658 InVec, InVal, InIdx));
2661 void SelectionDAGLowering::visitExtractElement(User &I) {
2662 SDOperand InVec = getValue(I.getOperand(0));
2663 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2664 getValue(I.getOperand(1)));
2665 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2666 TLI.getValueType(I.getType()), InVec, InIdx));
2669 void SelectionDAGLowering::visitShuffleVector(User &I) {
2670 SDOperand V1 = getValue(I.getOperand(0));
2671 SDOperand V2 = getValue(I.getOperand(1));
2672 SDOperand Mask = getValue(I.getOperand(2));
2674 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2675 TLI.getValueType(I.getType()),
2679 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2680 const Value *Op0 = I.getOperand(0);
2681 const Value *Op1 = I.getOperand(1);
2682 const Type *AggTy = I.getType();
2683 const Type *ValTy = Op1->getType();
2684 bool IntoUndef = isa<UndefValue>(Op0);
2685 bool FromUndef = isa<UndefValue>(Op1);
2687 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2688 I.idx_begin(), I.idx_end());
2690 SmallVector<MVT, 4> AggValueVTs;
2691 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2692 SmallVector<MVT, 4> ValValueVTs;
2693 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2695 unsigned NumAggValues = AggValueVTs.size();
2696 unsigned NumValValues = ValValueVTs.size();
2697 SmallVector<SDOperand, 4> Values(NumAggValues);
2699 SDOperand Agg = getValue(Op0);
2700 SDOperand Val = getValue(Op1);
2702 // Copy the beginning value(s) from the original aggregate.
2703 for (; i != LinearIndex; ++i)
2704 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2705 SDOperand(Agg.Val, Agg.ResNo + i);
2706 // Copy values from the inserted value(s).
2707 for (; i != LinearIndex + NumValValues; ++i)
2708 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2709 SDOperand(Val.Val, Val.ResNo + i - LinearIndex);
2710 // Copy remaining value(s) from the original aggregate.
2711 for (; i != NumAggValues; ++i)
2712 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2713 SDOperand(Agg.Val, Agg.ResNo + i);
2715 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2716 &Values[0], NumAggValues));
2719 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2720 const Value *Op0 = I.getOperand(0);
2721 const Type *AggTy = Op0->getType();
2722 const Type *ValTy = I.getType();
2723 bool OutOfUndef = isa<UndefValue>(Op0);
2725 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2726 I.idx_begin(), I.idx_end());
2728 SmallVector<MVT, 4> ValValueVTs;
2729 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2731 unsigned NumValValues = ValValueVTs.size();
2732 SmallVector<SDOperand, 4> Values(NumValValues);
2734 SDOperand Agg = getValue(Op0);
2735 // Copy out the selected value(s).
2736 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2737 Values[i - LinearIndex] =
2738 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
2739 SDOperand(Agg.Val, Agg.ResNo + i);
2741 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2742 &Values[0], NumValValues));
2746 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2747 SDOperand N = getValue(I.getOperand(0));
2748 const Type *Ty = I.getOperand(0)->getType();
2750 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2753 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2754 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2757 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2758 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2759 DAG.getIntPtrConstant(Offset));
2761 Ty = StTy->getElementType(Field);
2763 Ty = cast<SequentialType>(Ty)->getElementType();
2765 // If this is a constant subscript, handle it quickly.
2766 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2767 if (CI->getZExtValue() == 0) continue;
2769 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2770 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2771 DAG.getIntPtrConstant(Offs));
2775 // N = N + Idx * ElementSize;
2776 uint64_t ElementSize = TD->getABITypeSize(Ty);
2777 SDOperand IdxN = getValue(Idx);
2779 // If the index is smaller or larger than intptr_t, truncate or extend
2781 if (IdxN.getValueType().bitsLT(N.getValueType())) {
2782 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2783 } else if (IdxN.getValueType().bitsGT(N.getValueType()))
2784 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2786 // If this is a multiply by a power of two, turn it into a shl
2787 // immediately. This is a very common case.
2788 if (isPowerOf2_64(ElementSize)) {
2789 unsigned Amt = Log2_64(ElementSize);
2790 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2791 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2792 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2796 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2797 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2798 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2804 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2805 // If this is a fixed sized alloca in the entry block of the function,
2806 // allocate it statically on the stack.
2807 if (FuncInfo.StaticAllocaMap.count(&I))
2808 return; // getValue will auto-populate this.
2810 const Type *Ty = I.getAllocatedType();
2811 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2813 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2816 SDOperand AllocSize = getValue(I.getArraySize());
2817 MVT IntPtr = TLI.getPointerTy();
2818 if (IntPtr.bitsLT(AllocSize.getValueType()))
2819 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2820 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2821 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2823 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2824 DAG.getIntPtrConstant(TySize));
2826 // Handle alignment. If the requested alignment is less than or equal to
2827 // the stack alignment, ignore it. If the size is greater than or equal to
2828 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2829 unsigned StackAlign =
2830 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2831 if (Align <= StackAlign)
2834 // Round the size of the allocation up to the stack alignment size
2835 // by add SA-1 to the size.
2836 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2837 DAG.getIntPtrConstant(StackAlign-1));
2838 // Mask out the low bits for alignment purposes.
2839 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2840 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2842 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2843 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2845 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2847 DAG.setRoot(DSA.getValue(1));
2849 // Inform the Frame Information that we have just allocated a variable-sized
2851 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2854 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2855 const Value *SV = I.getOperand(0);
2856 SDOperand Ptr = getValue(SV);
2858 const Type *Ty = I.getType();
2859 bool isVolatile = I.isVolatile();
2860 unsigned Alignment = I.getAlignment();
2862 SmallVector<MVT, 4> ValueVTs;
2863 SmallVector<uint64_t, 4> Offsets;
2864 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2865 unsigned NumValues = ValueVTs.size();
2873 // Do not serialize non-volatile loads against each other.
2874 Root = DAG.getRoot();
2877 SmallVector<SDOperand, 4> Values(NumValues);
2878 SmallVector<SDOperand, 4> Chains(NumValues);
2879 MVT PtrVT = Ptr.getValueType();
2880 for (unsigned i = 0; i != NumValues; ++i) {
2881 SDOperand L = DAG.getLoad(ValueVTs[i], Root,
2882 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2883 DAG.getConstant(Offsets[i], PtrVT)),
2885 isVolatile, Alignment);
2887 Chains[i] = L.getValue(1);
2890 SDOperand Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2891 &Chains[0], NumValues);
2895 PendingLoads.push_back(Chain);
2897 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2898 &Values[0], NumValues));
2902 void SelectionDAGLowering::visitStore(StoreInst &I) {
2903 Value *SrcV = I.getOperand(0);
2904 SDOperand Src = getValue(SrcV);
2905 Value *PtrV = I.getOperand(1);
2906 SDOperand Ptr = getValue(PtrV);
2908 SmallVector<MVT, 4> ValueVTs;
2909 SmallVector<uint64_t, 4> Offsets;
2910 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2911 unsigned NumValues = ValueVTs.size();
2915 SDOperand Root = getRoot();
2916 SmallVector<SDOperand, 4> Chains(NumValues);
2917 MVT PtrVT = Ptr.getValueType();
2918 bool isVolatile = I.isVolatile();
2919 unsigned Alignment = I.getAlignment();
2920 for (unsigned i = 0; i != NumValues; ++i)
2921 Chains[i] = DAG.getStore(Root, SDOperand(Src.Val, Src.ResNo + i),
2922 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2923 DAG.getConstant(Offsets[i], PtrVT)),
2925 isVolatile, Alignment);
2927 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2930 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2932 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2933 unsigned Intrinsic) {
2934 bool HasChain = !I.doesNotAccessMemory();
2935 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2937 // Build the operand list.
2938 SmallVector<SDOperand, 8> Ops;
2939 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2941 // We don't need to serialize loads against other loads.
2942 Ops.push_back(DAG.getRoot());
2944 Ops.push_back(getRoot());
2948 // Add the intrinsic ID as an integer operand.
2949 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2951 // Add all operands of the call to the operand list.
2952 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2953 SDOperand Op = getValue(I.getOperand(i));
2954 assert(TLI.isTypeLegal(Op.getValueType()) &&
2955 "Intrinsic uses a non-legal type?");
2959 std::vector<MVT> VTs;
2960 if (I.getType() != Type::VoidTy) {
2961 MVT VT = TLI.getValueType(I.getType());
2962 if (VT.isVector()) {
2963 const VectorType *DestTy = cast<VectorType>(I.getType());
2964 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2966 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2967 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2970 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2974 VTs.push_back(MVT::Other);
2976 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2981 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2982 &Ops[0], Ops.size());
2983 else if (I.getType() != Type::VoidTy)
2984 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2985 &Ops[0], Ops.size());
2987 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2988 &Ops[0], Ops.size());
2991 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2993 PendingLoads.push_back(Chain);
2997 if (I.getType() != Type::VoidTy) {
2998 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2999 MVT VT = TLI.getValueType(PTy);
3000 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
3002 setValue(&I, Result);
3006 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3007 static GlobalVariable *ExtractTypeInfo (Value *V) {
3008 V = V->stripPointerCasts();
3009 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3010 assert ((GV || isa<ConstantPointerNull>(V)) &&
3011 "TypeInfo must be a global variable or NULL");
3015 /// addCatchInfo - Extract the personality and type infos from an eh.selector
3016 /// call, and add them to the specified machine basic block.
3017 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3018 MachineBasicBlock *MBB) {
3019 // Inform the MachineModuleInfo of the personality for this landing pad.
3020 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3021 assert(CE->getOpcode() == Instruction::BitCast &&
3022 isa<Function>(CE->getOperand(0)) &&
3023 "Personality should be a function");
3024 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3026 // Gather all the type infos for this landing pad and pass them along to
3027 // MachineModuleInfo.
3028 std::vector<GlobalVariable *> TyInfo;
3029 unsigned N = I.getNumOperands();
3031 for (unsigned i = N - 1; i > 2; --i) {
3032 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3033 unsigned FilterLength = CI->getZExtValue();
3034 unsigned FirstCatch = i + FilterLength + !FilterLength;
3035 assert (FirstCatch <= N && "Invalid filter length");
3037 if (FirstCatch < N) {
3038 TyInfo.reserve(N - FirstCatch);
3039 for (unsigned j = FirstCatch; j < N; ++j)
3040 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3041 MMI->addCatchTypeInfo(MBB, TyInfo);
3045 if (!FilterLength) {
3047 MMI->addCleanup(MBB);
3050 TyInfo.reserve(FilterLength - 1);
3051 for (unsigned j = i + 1; j < FirstCatch; ++j)
3052 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3053 MMI->addFilterTypeInfo(MBB, TyInfo);
3062 TyInfo.reserve(N - 3);
3063 for (unsigned j = 3; j < N; ++j)
3064 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3065 MMI->addCatchTypeInfo(MBB, TyInfo);
3070 /// Inlined utility function to implement binary input atomic intrinsics for
3071 // visitIntrinsicCall: I is a call instruction
3072 // Op is the associated NodeType for I
3074 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3075 SDOperand Root = getRoot();
3076 SDOperand L = DAG.getAtomic(Op, Root,
3077 getValue(I.getOperand(1)),
3078 getValue(I.getOperand(2)),
3081 DAG.setRoot(L.getValue(1));
3085 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3086 /// we want to emit this as a call to a named external function, return the name
3087 /// otherwise lower it and return null.
3089 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3090 switch (Intrinsic) {
3092 // By default, turn this into a target intrinsic node.
3093 visitTargetIntrinsic(I, Intrinsic);
3095 case Intrinsic::vastart: visitVAStart(I); return 0;
3096 case Intrinsic::vaend: visitVAEnd(I); return 0;
3097 case Intrinsic::vacopy: visitVACopy(I); return 0;
3098 case Intrinsic::returnaddress:
3099 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3100 getValue(I.getOperand(1))));
3102 case Intrinsic::frameaddress:
3103 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3104 getValue(I.getOperand(1))));
3106 case Intrinsic::setjmp:
3107 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3109 case Intrinsic::longjmp:
3110 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3112 case Intrinsic::memcpy_i32:
3113 case Intrinsic::memcpy_i64: {
3114 SDOperand Op1 = getValue(I.getOperand(1));
3115 SDOperand Op2 = getValue(I.getOperand(2));
3116 SDOperand Op3 = getValue(I.getOperand(3));
3117 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3118 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3119 I.getOperand(1), 0, I.getOperand(2), 0));
3122 case Intrinsic::memset_i32:
3123 case Intrinsic::memset_i64: {
3124 SDOperand Op1 = getValue(I.getOperand(1));
3125 SDOperand Op2 = getValue(I.getOperand(2));
3126 SDOperand Op3 = getValue(I.getOperand(3));
3127 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3128 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3129 I.getOperand(1), 0));
3132 case Intrinsic::memmove_i32:
3133 case Intrinsic::memmove_i64: {
3134 SDOperand Op1 = getValue(I.getOperand(1));
3135 SDOperand Op2 = getValue(I.getOperand(2));
3136 SDOperand Op3 = getValue(I.getOperand(3));
3137 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3139 // If the source and destination are known to not be aliases, we can
3140 // lower memmove as memcpy.
3141 uint64_t Size = -1ULL;
3142 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3143 Size = C->getValue();
3144 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3145 AliasAnalysis::NoAlias) {
3146 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3147 I.getOperand(1), 0, I.getOperand(2), 0));
3151 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3152 I.getOperand(1), 0, I.getOperand(2), 0));
3155 case Intrinsic::dbg_stoppoint: {
3156 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3157 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3158 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3159 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3160 assert(DD && "Not a debug information descriptor");
3161 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3164 cast<CompileUnitDesc>(DD)));
3169 case Intrinsic::dbg_region_start: {
3170 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3171 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3172 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3173 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3174 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3179 case Intrinsic::dbg_region_end: {
3180 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3181 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3182 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3183 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3184 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3189 case Intrinsic::dbg_func_start: {
3190 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3192 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3193 Value *SP = FSI.getSubprogram();
3194 if (SP && MMI->Verify(SP)) {
3195 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3196 // what (most?) gdb expects.
3197 DebugInfoDesc *DD = MMI->getDescFor(SP);
3198 assert(DD && "Not a debug information descriptor");
3199 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3200 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3201 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3202 // Record the source line but does create a label. It will be emitted
3203 // at asm emission time.
3204 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3209 case Intrinsic::dbg_declare: {
3210 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3211 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3212 Value *Variable = DI.getVariable();
3213 if (MMI && Variable && MMI->Verify(Variable))
3214 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3215 getValue(DI.getAddress()), getValue(Variable)));
3219 case Intrinsic::eh_exception: {
3220 if (!CurMBB->isLandingPad()) {
3221 // FIXME: Mark exception register as live in. Hack for PR1508.
3222 unsigned Reg = TLI.getExceptionAddressRegister();
3223 if (Reg) CurMBB->addLiveIn(Reg);
3225 // Insert the EXCEPTIONADDR instruction.
3226 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3228 Ops[0] = DAG.getRoot();
3229 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3231 DAG.setRoot(Op.getValue(1));
3235 case Intrinsic::eh_selector_i32:
3236 case Intrinsic::eh_selector_i64: {
3237 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3238 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3239 MVT::i32 : MVT::i64);
3242 if (CurMBB->isLandingPad())
3243 addCatchInfo(I, MMI, CurMBB);
3246 FuncInfo.CatchInfoLost.insert(&I);
3248 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3249 unsigned Reg = TLI.getExceptionSelectorRegister();
3250 if (Reg) CurMBB->addLiveIn(Reg);
3253 // Insert the EHSELECTION instruction.
3254 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3256 Ops[0] = getValue(I.getOperand(1));
3258 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3260 DAG.setRoot(Op.getValue(1));
3262 setValue(&I, DAG.getConstant(0, VT));
3268 case Intrinsic::eh_typeid_for_i32:
3269 case Intrinsic::eh_typeid_for_i64: {
3270 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3271 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3272 MVT::i32 : MVT::i64);
3275 // Find the type id for the given typeinfo.
3276 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3278 unsigned TypeID = MMI->getTypeIDFor(GV);
3279 setValue(&I, DAG.getConstant(TypeID, VT));
3281 // Return something different to eh_selector.
3282 setValue(&I, DAG.getConstant(1, VT));
3288 case Intrinsic::eh_return: {
3289 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3292 MMI->setCallsEHReturn(true);
3293 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3296 getValue(I.getOperand(1)),
3297 getValue(I.getOperand(2))));
3299 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3305 case Intrinsic::eh_unwind_init: {
3306 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3307 MMI->setCallsUnwindInit(true);
3313 case Intrinsic::eh_dwarf_cfa: {
3314 MVT VT = getValue(I.getOperand(1)).getValueType();
3316 if (VT.bitsGT(TLI.getPointerTy()))
3317 CfaArg = DAG.getNode(ISD::TRUNCATE,
3318 TLI.getPointerTy(), getValue(I.getOperand(1)));
3320 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3321 TLI.getPointerTy(), getValue(I.getOperand(1)));
3323 SDOperand Offset = DAG.getNode(ISD::ADD,
3325 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3326 TLI.getPointerTy()),
3328 setValue(&I, DAG.getNode(ISD::ADD,
3330 DAG.getNode(ISD::FRAMEADDR,
3333 TLI.getPointerTy())),
3338 case Intrinsic::sqrt:
3339 setValue(&I, DAG.getNode(ISD::FSQRT,
3340 getValue(I.getOperand(1)).getValueType(),
3341 getValue(I.getOperand(1))));
3343 case Intrinsic::powi:
3344 setValue(&I, DAG.getNode(ISD::FPOWI,
3345 getValue(I.getOperand(1)).getValueType(),
3346 getValue(I.getOperand(1)),
3347 getValue(I.getOperand(2))));
3349 case Intrinsic::sin:
3350 setValue(&I, DAG.getNode(ISD::FSIN,
3351 getValue(I.getOperand(1)).getValueType(),
3352 getValue(I.getOperand(1))));
3354 case Intrinsic::cos:
3355 setValue(&I, DAG.getNode(ISD::FCOS,
3356 getValue(I.getOperand(1)).getValueType(),
3357 getValue(I.getOperand(1))));
3359 case Intrinsic::pow:
3360 setValue(&I, DAG.getNode(ISD::FPOW,
3361 getValue(I.getOperand(1)).getValueType(),
3362 getValue(I.getOperand(1)),
3363 getValue(I.getOperand(2))));
3365 case Intrinsic::pcmarker: {
3366 SDOperand Tmp = getValue(I.getOperand(1));
3367 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3370 case Intrinsic::readcyclecounter: {
3371 SDOperand Op = getRoot();
3372 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3373 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3376 DAG.setRoot(Tmp.getValue(1));
3379 case Intrinsic::part_select: {
3380 // Currently not implemented: just abort
3381 assert(0 && "part_select intrinsic not implemented");
3384 case Intrinsic::part_set: {
3385 // Currently not implemented: just abort
3386 assert(0 && "part_set intrinsic not implemented");
3389 case Intrinsic::bswap:
3390 setValue(&I, DAG.getNode(ISD::BSWAP,
3391 getValue(I.getOperand(1)).getValueType(),
3392 getValue(I.getOperand(1))));
3394 case Intrinsic::cttz: {
3395 SDOperand Arg = getValue(I.getOperand(1));
3396 MVT Ty = Arg.getValueType();
3397 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3398 setValue(&I, result);
3401 case Intrinsic::ctlz: {
3402 SDOperand Arg = getValue(I.getOperand(1));
3403 MVT Ty = Arg.getValueType();
3404 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3405 setValue(&I, result);
3408 case Intrinsic::ctpop: {
3409 SDOperand Arg = getValue(I.getOperand(1));
3410 MVT Ty = Arg.getValueType();
3411 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3412 setValue(&I, result);
3415 case Intrinsic::stacksave: {
3416 SDOperand Op = getRoot();
3417 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
3418 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3420 DAG.setRoot(Tmp.getValue(1));
3423 case Intrinsic::stackrestore: {
3424 SDOperand Tmp = getValue(I.getOperand(1));
3425 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3428 case Intrinsic::var_annotation:
3429 // Discard annotate attributes
3432 case Intrinsic::init_trampoline: {
3433 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3437 Ops[1] = getValue(I.getOperand(1));
3438 Ops[2] = getValue(I.getOperand(2));
3439 Ops[3] = getValue(I.getOperand(3));
3440 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3441 Ops[5] = DAG.getSrcValue(F);
3443 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
3444 DAG.getNodeValueTypes(TLI.getPointerTy(),
3449 DAG.setRoot(Tmp.getValue(1));
3453 case Intrinsic::gcroot:
3455 Value *Alloca = I.getOperand(1);
3456 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3458 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3459 GCI->addStackRoot(FI->getIndex(), TypeMap);
3463 case Intrinsic::gcread:
3464 case Intrinsic::gcwrite:
3465 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3468 case Intrinsic::flt_rounds: {
3469 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3473 case Intrinsic::trap: {
3474 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3477 case Intrinsic::prefetch: {
3480 Ops[1] = getValue(I.getOperand(1));
3481 Ops[2] = getValue(I.getOperand(2));
3482 Ops[3] = getValue(I.getOperand(3));
3483 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3487 case Intrinsic::memory_barrier: {
3490 for (int x = 1; x < 6; ++x)
3491 Ops[x] = getValue(I.getOperand(x));
3493 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3496 case Intrinsic::atomic_cmp_swap: {
3497 SDOperand Root = getRoot();
3498 SDOperand L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
3499 getValue(I.getOperand(1)),
3500 getValue(I.getOperand(2)),
3501 getValue(I.getOperand(3)),
3504 DAG.setRoot(L.getValue(1));
3507 case Intrinsic::atomic_load_add:
3508 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
3509 case Intrinsic::atomic_load_sub:
3510 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
3511 case Intrinsic::atomic_load_and:
3512 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3513 case Intrinsic::atomic_load_or:
3514 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3515 case Intrinsic::atomic_load_xor:
3516 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
3517 case Intrinsic::atomic_load_nand:
3518 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
3519 case Intrinsic::atomic_load_min:
3520 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3521 case Intrinsic::atomic_load_max:
3522 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3523 case Intrinsic::atomic_load_umin:
3524 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3525 case Intrinsic::atomic_load_umax:
3526 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3527 case Intrinsic::atomic_swap:
3528 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
3533 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
3535 MachineBasicBlock *LandingPad) {
3536 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3537 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3538 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3539 unsigned BeginLabel = 0, EndLabel = 0;
3541 TargetLowering::ArgListTy Args;
3542 TargetLowering::ArgListEntry Entry;
3543 Args.reserve(CS.arg_size());
3544 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3546 SDOperand ArgNode = getValue(*i);
3547 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3549 unsigned attrInd = i - CS.arg_begin() + 1;
3550 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3551 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3552 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3553 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3554 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3555 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3556 Entry.Alignment = CS.getParamAlignment(attrInd);
3557 Args.push_back(Entry);
3560 if (LandingPad && MMI) {
3561 // Insert a label before the invoke call to mark the try range. This can be
3562 // used to detect deletion of the invoke via the MachineModuleInfo.
3563 BeginLabel = MMI->NextLabelID();
3564 // Both PendingLoads and PendingExports must be flushed here;
3565 // this call might not return.
3567 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
3570 std::pair<SDOperand,SDOperand> Result =
3571 TLI.LowerCallTo(getRoot(), CS.getType(),
3572 CS.paramHasAttr(0, ParamAttr::SExt),
3573 CS.paramHasAttr(0, ParamAttr::ZExt),
3574 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3576 if (CS.getType() != Type::VoidTy)
3577 setValue(CS.getInstruction(), Result.first);
3578 DAG.setRoot(Result.second);
3580 if (LandingPad && MMI) {
3581 // Insert a label at the end of the invoke call to mark the try range. This
3582 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3583 EndLabel = MMI->NextLabelID();
3584 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
3586 // Inform MachineModuleInfo of range.
3587 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3592 void SelectionDAGLowering::visitCall(CallInst &I) {
3593 const char *RenameFn = 0;
3594 if (Function *F = I.getCalledFunction()) {
3595 if (F->isDeclaration()) {
3596 if (unsigned IID = F->getIntrinsicID()) {
3597 RenameFn = visitIntrinsicCall(I, IID);
3603 // Check for well-known libc/libm calls. If the function is internal, it
3604 // can't be a library call.
3605 unsigned NameLen = F->getNameLen();
3606 if (!F->hasInternalLinkage() && NameLen) {
3607 const char *NameStr = F->getNameStart();
3608 if (NameStr[0] == 'c' &&
3609 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3610 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3611 if (I.getNumOperands() == 3 && // Basic sanity checks.
3612 I.getOperand(1)->getType()->isFloatingPoint() &&
3613 I.getType() == I.getOperand(1)->getType() &&
3614 I.getType() == I.getOperand(2)->getType()) {
3615 SDOperand LHS = getValue(I.getOperand(1));
3616 SDOperand RHS = getValue(I.getOperand(2));
3617 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3621 } else if (NameStr[0] == 'f' &&
3622 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3623 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3624 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3625 if (I.getNumOperands() == 2 && // Basic sanity checks.
3626 I.getOperand(1)->getType()->isFloatingPoint() &&
3627 I.getType() == I.getOperand(1)->getType()) {
3628 SDOperand Tmp = getValue(I.getOperand(1));
3629 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3632 } else if (NameStr[0] == 's' &&
3633 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3634 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3635 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3636 if (I.getNumOperands() == 2 && // Basic sanity checks.
3637 I.getOperand(1)->getType()->isFloatingPoint() &&
3638 I.getType() == I.getOperand(1)->getType()) {
3639 SDOperand Tmp = getValue(I.getOperand(1));
3640 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3643 } else if (NameStr[0] == 'c' &&
3644 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3645 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3646 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3647 if (I.getNumOperands() == 2 && // Basic sanity checks.
3648 I.getOperand(1)->getType()->isFloatingPoint() &&
3649 I.getType() == I.getOperand(1)->getType()) {
3650 SDOperand Tmp = getValue(I.getOperand(1));
3651 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3656 } else if (isa<InlineAsm>(I.getOperand(0))) {
3663 Callee = getValue(I.getOperand(0));
3665 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3667 LowerCallTo(&I, Callee, I.isTailCall());
3671 void SelectionDAGLowering::visitGetResult(GetResultInst &I) {
3672 if (isa<UndefValue>(I.getOperand(0))) {
3673 SDOperand Undef = DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType()));
3674 setValue(&I, Undef);
3678 // To add support for individual return values with aggregate types,
3679 // we'd need a way to take a getresult index and determine which
3680 // values of the Call SDNode are associated with it.
3681 assert(TLI.getValueType(I.getType(), true) != MVT::Other &&
3682 "Individual return values must not be aggregates!");
3684 SDOperand Call = getValue(I.getOperand(0));
3685 setValue(&I, SDOperand(Call.Val, I.getIndex()));
3689 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3690 /// this value and returns the result as a ValueVT value. This uses
3691 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3692 /// If the Flag pointer is NULL, no flag is used.
3693 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3695 SDOperand *Flag) const {
3696 // Assemble the legal parts into the final values.
3697 SmallVector<SDOperand, 4> Values(ValueVTs.size());
3698 SmallVector<SDOperand, 8> Parts;
3699 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3700 // Copy the legal parts from the registers.
3701 MVT ValueVT = ValueVTs[Value];
3702 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3703 MVT RegisterVT = RegVTs[Value];
3705 Parts.resize(NumRegs);
3706 for (unsigned i = 0; i != NumRegs; ++i) {
3709 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3711 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3712 *Flag = P.getValue(2);
3714 Chain = P.getValue(1);
3716 // If the source register was virtual and if we know something about it,
3717 // add an assert node.
3718 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
3719 RegisterVT.isInteger() && !RegisterVT.isVector()) {
3720 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
3721 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
3722 if (FLI.LiveOutRegInfo.size() > SlotNo) {
3723 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
3725 unsigned RegSize = RegisterVT.getSizeInBits();
3726 unsigned NumSignBits = LOI.NumSignBits;
3727 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
3729 // FIXME: We capture more information than the dag can represent. For
3730 // now, just use the tightest assertzext/assertsext possible.
3732 MVT FromVT(MVT::Other);
3733 if (NumSignBits == RegSize)
3734 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
3735 else if (NumZeroBits >= RegSize-1)
3736 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
3737 else if (NumSignBits > RegSize-8)
3738 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
3739 else if (NumZeroBits >= RegSize-9)
3740 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
3741 else if (NumSignBits > RegSize-16)
3742 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
3743 else if (NumZeroBits >= RegSize-17)
3744 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
3745 else if (NumSignBits > RegSize-32)
3746 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
3747 else if (NumZeroBits >= RegSize-33)
3748 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
3750 if (FromVT != MVT::Other) {
3751 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
3752 RegisterVT, P, DAG.getValueType(FromVT));
3761 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3766 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3767 &Values[0], ValueVTs.size());
3770 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3771 /// specified value into the registers specified by this object. This uses
3772 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3773 /// If the Flag pointer is NULL, no flag is used.
3774 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3775 SDOperand &Chain, SDOperand *Flag) const {
3776 // Get the list of the values's legal parts.
3777 unsigned NumRegs = Regs.size();
3778 SmallVector<SDOperand, 8> Parts(NumRegs);
3779 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3780 MVT ValueVT = ValueVTs[Value];
3781 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3782 MVT RegisterVT = RegVTs[Value];
3784 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3785 &Parts[Part], NumParts, RegisterVT);
3789 // Copy the parts into the registers.
3790 SmallVector<SDOperand, 8> Chains(NumRegs);
3791 for (unsigned i = 0; i != NumRegs; ++i) {
3794 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3796 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3797 *Flag = Part.getValue(1);
3799 Chains[i] = Part.getValue(0);
3802 if (NumRegs == 1 || Flag)
3803 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3804 // flagged to it. That is the CopyToReg nodes and the user are considered
3805 // a single scheduling unit. If we create a TokenFactor and return it as
3806 // chain, then the TokenFactor is both a predecessor (operand) of the
3807 // user as well as a successor (the TF operands are flagged to the user).
3808 // c1, f1 = CopyToReg
3809 // c2, f2 = CopyToReg
3810 // c3 = TokenFactor c1, c2
3813 Chain = Chains[NumRegs-1];
3815 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3818 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3819 /// operand list. This adds the code marker and includes the number of
3820 /// values added into it.
3821 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3822 std::vector<SDOperand> &Ops) const {
3823 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3824 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3825 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3826 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3827 MVT RegisterVT = RegVTs[Value];
3828 for (unsigned i = 0; i != NumRegs; ++i)
3829 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3833 /// isAllocatableRegister - If the specified register is safe to allocate,
3834 /// i.e. it isn't a stack pointer or some other special register, return the
3835 /// register class for the register. Otherwise, return null.
3836 static const TargetRegisterClass *
3837 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3838 const TargetLowering &TLI,
3839 const TargetRegisterInfo *TRI) {
3840 MVT FoundVT = MVT::Other;
3841 const TargetRegisterClass *FoundRC = 0;
3842 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3843 E = TRI->regclass_end(); RCI != E; ++RCI) {
3844 MVT ThisVT = MVT::Other;
3846 const TargetRegisterClass *RC = *RCI;
3847 // If none of the the value types for this register class are valid, we
3848 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3849 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3851 if (TLI.isTypeLegal(*I)) {
3852 // If we have already found this register in a different register class,
3853 // choose the one with the largest VT specified. For example, on
3854 // PowerPC, we favor f64 register classes over f32.
3855 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
3862 if (ThisVT == MVT::Other) continue;
3864 // NOTE: This isn't ideal. In particular, this might allocate the
3865 // frame pointer in functions that need it (due to them not being taken
3866 // out of allocation, because a variable sized allocation hasn't been seen
3867 // yet). This is a slight code pessimization, but should still work.
3868 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3869 E = RC->allocation_order_end(MF); I != E; ++I)
3871 // We found a matching register class. Keep looking at others in case
3872 // we find one with larger registers that this physreg is also in.
3883 /// AsmOperandInfo - This contains information for each constraint that we are
3885 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3886 /// CallOperand - If this is the result output operand or a clobber
3887 /// this is null, otherwise it is the incoming operand to the CallInst.
3888 /// This gets modified as the asm is processed.
3889 SDOperand CallOperand;
3891 /// AssignedRegs - If this is a register or register class operand, this
3892 /// contains the set of register corresponding to the operand.
3893 RegsForValue AssignedRegs;
3895 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3896 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3899 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3900 /// busy in OutputRegs/InputRegs.
3901 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3902 std::set<unsigned> &OutputRegs,
3903 std::set<unsigned> &InputRegs,
3904 const TargetRegisterInfo &TRI) const {
3906 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3907 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3910 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3911 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3916 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3918 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3919 const TargetRegisterInfo &TRI) {
3920 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3922 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3923 for (; *Aliases; ++Aliases)
3924 Regs.insert(*Aliases);
3927 } // end anon namespace.
3930 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3931 /// specified operand. We prefer to assign virtual registers, to allow the
3932 /// register allocator handle the assignment process. However, if the asm uses
3933 /// features that we can't model on machineinstrs, we have SDISel do the
3934 /// allocation. This produces generally horrible, but correct, code.
3936 /// OpInfo describes the operand.
3937 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3938 /// or any explicitly clobbered registers.
3939 /// Input and OutputRegs are the set of already allocated physical registers.
3941 void SelectionDAGLowering::
3942 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3943 std::set<unsigned> &OutputRegs,
3944 std::set<unsigned> &InputRegs) {
3945 // Compute whether this value requires an input register, an output register,
3947 bool isOutReg = false;
3948 bool isInReg = false;
3949 switch (OpInfo.Type) {
3950 case InlineAsm::isOutput:
3953 // If this is an early-clobber output, or if there is an input
3954 // constraint that matches this, we need to reserve the input register
3955 // so no other inputs allocate to it.
3956 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3958 case InlineAsm::isInput:
3962 case InlineAsm::isClobber:
3969 MachineFunction &MF = DAG.getMachineFunction();
3970 SmallVector<unsigned, 4> Regs;
3972 // If this is a constraint for a single physreg, or a constraint for a
3973 // register class, find it.
3974 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3975 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3976 OpInfo.ConstraintVT);
3978 unsigned NumRegs = 1;
3979 if (OpInfo.ConstraintVT != MVT::Other)
3980 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3982 MVT ValueVT = OpInfo.ConstraintVT;
3985 // If this is a constraint for a specific physical register, like {r17},
3987 if (PhysReg.first) {
3988 if (OpInfo.ConstraintVT == MVT::Other)
3989 ValueVT = *PhysReg.second->vt_begin();
3991 // Get the actual register value type. This is important, because the user
3992 // may have asked for (e.g.) the AX register in i32 type. We need to
3993 // remember that AX is actually i16 to get the right extension.
3994 RegVT = *PhysReg.second->vt_begin();
3996 // This is a explicit reference to a physical register.
3997 Regs.push_back(PhysReg.first);
3999 // If this is an expanded reference, add the rest of the regs to Regs.
4001 TargetRegisterClass::iterator I = PhysReg.second->begin();
4002 for (; *I != PhysReg.first; ++I)
4003 assert(I != PhysReg.second->end() && "Didn't find reg!");
4005 // Already added the first reg.
4007 for (; NumRegs; --NumRegs, ++I) {
4008 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4012 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4013 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4014 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4018 // Otherwise, if this was a reference to an LLVM register class, create vregs
4019 // for this reference.
4020 std::vector<unsigned> RegClassRegs;
4021 const TargetRegisterClass *RC = PhysReg.second;
4023 // If this is an early clobber or tied register, our regalloc doesn't know
4024 // how to maintain the constraint. If it isn't, go ahead and create vreg
4025 // and let the regalloc do the right thing.
4026 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4027 // If there is some other early clobber and this is an input register,
4028 // then we are forced to pre-allocate the input reg so it doesn't
4029 // conflict with the earlyclobber.
4030 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
4031 RegVT = *PhysReg.second->vt_begin();
4033 if (OpInfo.ConstraintVT == MVT::Other)
4036 // Create the appropriate number of virtual registers.
4037 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4038 for (; NumRegs; --NumRegs)
4039 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4041 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4045 // Otherwise, we can't allocate it. Let the code below figure out how to
4046 // maintain these constraints.
4047 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4050 // This is a reference to a register class that doesn't directly correspond
4051 // to an LLVM register class. Allocate NumRegs consecutive, available,
4052 // registers from the class.
4053 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4054 OpInfo.ConstraintVT);
4057 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4058 unsigned NumAllocated = 0;
4059 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4060 unsigned Reg = RegClassRegs[i];
4061 // See if this register is available.
4062 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4063 (isInReg && InputRegs.count(Reg))) { // Already used.
4064 // Make sure we find consecutive registers.
4069 // Check to see if this register is allocatable (i.e. don't give out the
4072 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4073 if (!RC) { // Couldn't allocate this register.
4074 // Reset NumAllocated to make sure we return consecutive registers.
4080 // Okay, this register is good, we can use it.
4083 // If we allocated enough consecutive registers, succeed.
4084 if (NumAllocated == NumRegs) {
4085 unsigned RegStart = (i-NumAllocated)+1;
4086 unsigned RegEnd = i+1;
4087 // Mark all of the allocated registers used.
4088 for (unsigned i = RegStart; i != RegEnd; ++i)
4089 Regs.push_back(RegClassRegs[i]);
4091 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4092 OpInfo.ConstraintVT);
4093 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4098 // Otherwise, we couldn't allocate enough registers for this.
4102 /// visitInlineAsm - Handle a call to an InlineAsm object.
4104 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4105 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4107 /// ConstraintOperands - Information about all of the constraints.
4108 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4110 SDOperand Chain = getRoot();
4113 std::set<unsigned> OutputRegs, InputRegs;
4115 // Do a prepass over the constraints, canonicalizing them, and building up the
4116 // ConstraintOperands list.
4117 std::vector<InlineAsm::ConstraintInfo>
4118 ConstraintInfos = IA->ParseConstraints();
4120 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4121 // constraint. If so, we can't let the register allocator allocate any input
4122 // registers, because it will not know to avoid the earlyclobbered output reg.
4123 bool SawEarlyClobber = false;
4125 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4126 unsigned ResNo = 0; // ResNo - The result number of the next output.
4127 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4128 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4129 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4131 MVT OpVT = MVT::Other;
4133 // Compute the value type for each operand.
4134 switch (OpInfo.Type) {
4135 case InlineAsm::isOutput:
4136 // Indirect outputs just consume an argument.
4137 if (OpInfo.isIndirect) {
4138 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4141 // The return value of the call is this value. As such, there is no
4142 // corresponding argument.
4143 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4144 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4145 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4147 assert(ResNo == 0 && "Asm only has one result!");
4148 OpVT = TLI.getValueType(CS.getType());
4152 case InlineAsm::isInput:
4153 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4155 case InlineAsm::isClobber:
4160 // If this is an input or an indirect output, process the call argument.
4161 // BasicBlocks are labels, currently appearing only in asm's.
4162 if (OpInfo.CallOperandVal) {
4163 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4164 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4166 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4167 const Type *OpTy = OpInfo.CallOperandVal->getType();
4168 // If this is an indirect operand, the operand is a pointer to the
4170 if (OpInfo.isIndirect)
4171 OpTy = cast<PointerType>(OpTy)->getElementType();
4173 // If OpTy is not a single value, it may be a struct/union that we
4174 // can tile with integers.
4175 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4176 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4184 OpTy = IntegerType::get(BitSize);
4189 OpVT = TLI.getValueType(OpTy, true);
4193 OpInfo.ConstraintVT = OpVT;
4195 // Compute the constraint code and ConstraintType to use.
4196 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
4198 // Keep track of whether we see an earlyclobber.
4199 SawEarlyClobber |= OpInfo.isEarlyClobber;
4201 // If we see a clobber of a register, it is an early clobber.
4202 if (!SawEarlyClobber &&
4203 OpInfo.Type == InlineAsm::isClobber &&
4204 OpInfo.ConstraintType == TargetLowering::C_Register) {
4205 // Note that we want to ignore things that we don't trick here, like
4206 // dirflag, fpsr, flags, etc.
4207 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4208 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4209 OpInfo.ConstraintVT);
4210 if (PhysReg.first || PhysReg.second) {
4211 // This is a register we know of.
4212 SawEarlyClobber = true;
4216 // If this is a memory input, and if the operand is not indirect, do what we
4217 // need to to provide an address for the memory input.
4218 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4219 !OpInfo.isIndirect) {
4220 assert(OpInfo.Type == InlineAsm::isInput &&
4221 "Can only indirectify direct input operands!");
4223 // Memory operands really want the address of the value. If we don't have
4224 // an indirect input, put it in the constpool if we can, otherwise spill
4225 // it to a stack slot.
4227 // If the operand is a float, integer, or vector constant, spill to a
4228 // constant pool entry to get its address.
4229 Value *OpVal = OpInfo.CallOperandVal;
4230 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4231 isa<ConstantVector>(OpVal)) {
4232 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4233 TLI.getPointerTy());
4235 // Otherwise, create a stack slot and emit a store to it before the
4237 const Type *Ty = OpVal->getType();
4238 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4239 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4240 MachineFunction &MF = DAG.getMachineFunction();
4241 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4242 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4243 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4244 OpInfo.CallOperand = StackSlot;
4247 // There is no longer a Value* corresponding to this operand.
4248 OpInfo.CallOperandVal = 0;
4249 // It is now an indirect operand.
4250 OpInfo.isIndirect = true;
4253 // If this constraint is for a specific register, allocate it before
4255 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4256 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4258 ConstraintInfos.clear();
4261 // Second pass - Loop over all of the operands, assigning virtual or physregs
4262 // to registerclass operands.
4263 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4264 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4266 // C_Register operands have already been allocated, Other/Memory don't need
4268 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4269 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4272 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4273 std::vector<SDOperand> AsmNodeOperands;
4274 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
4275 AsmNodeOperands.push_back(
4276 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4279 // Loop over all of the inputs, copying the operand values into the
4280 // appropriate registers and processing the output regs.
4281 RegsForValue RetValRegs;
4283 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4284 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4286 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4287 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4289 switch (OpInfo.Type) {
4290 case InlineAsm::isOutput: {
4291 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4292 OpInfo.ConstraintType != TargetLowering::C_Register) {
4293 // Memory output, or 'other' output (e.g. 'X' constraint).
4294 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4296 // Add information to the INLINEASM node to know about this output.
4297 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4298 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4299 TLI.getPointerTy()));
4300 AsmNodeOperands.push_back(OpInfo.CallOperand);
4304 // Otherwise, this is a register or register class output.
4306 // Copy the output from the appropriate register. Find a register that
4308 if (OpInfo.AssignedRegs.Regs.empty()) {
4309 cerr << "Couldn't allocate output reg for constraint '"
4310 << OpInfo.ConstraintCode << "'!\n";
4314 // If this is an indirect operand, store through the pointer after the
4316 if (OpInfo.isIndirect) {
4317 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4318 OpInfo.CallOperandVal));
4320 // This is the result value of the call.
4321 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4322 // Concatenate this output onto the outputs list.
4323 RetValRegs.append(OpInfo.AssignedRegs);
4326 // Add information to the INLINEASM node to know that this register is
4328 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4332 case InlineAsm::isInput: {
4333 SDOperand InOperandVal = OpInfo.CallOperand;
4335 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4336 // If this is required to match an output register we have already set,
4337 // just use its register.
4338 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4340 // Scan until we find the definition we already emitted of this operand.
4341 // When we find it, create a RegsForValue operand.
4342 unsigned CurOp = 2; // The first operand.
4343 for (; OperandNo; --OperandNo) {
4344 // Advance to the next operand.
4346 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4347 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4348 (NumOps & 7) == 4 /*MEM*/) &&
4349 "Skipped past definitions?");
4350 CurOp += (NumOps>>3)+1;
4354 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4355 if ((NumOps & 7) == 2 /*REGDEF*/) {
4356 // Add NumOps>>3 registers to MatchedRegs.
4357 RegsForValue MatchedRegs;
4358 MatchedRegs.TLI = &TLI;
4359 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4360 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4361 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4363 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4364 MatchedRegs.Regs.push_back(Reg);
4367 // Use the produced MatchedRegs object to
4368 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4369 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4372 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4373 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4374 // Add information to the INLINEASM node to know about this input.
4375 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4376 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4377 TLI.getPointerTy()));
4378 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4383 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4384 assert(!OpInfo.isIndirect &&
4385 "Don't know how to handle indirect other inputs yet!");
4387 std::vector<SDOperand> Ops;
4388 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4391 cerr << "Invalid operand for inline asm constraint '"
4392 << OpInfo.ConstraintCode << "'!\n";
4396 // Add information to the INLINEASM node to know about this input.
4397 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4398 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4399 TLI.getPointerTy()));
4400 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4402 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4403 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4404 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4405 "Memory operands expect pointer values");
4407 // Add information to the INLINEASM node to know about this input.
4408 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4409 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4410 TLI.getPointerTy()));
4411 AsmNodeOperands.push_back(InOperandVal);
4415 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4416 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4417 "Unknown constraint type!");
4418 assert(!OpInfo.isIndirect &&
4419 "Don't know how to handle indirect register inputs yet!");
4421 // Copy the input into the appropriate registers.
4422 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4423 "Couldn't allocate input reg!");
4425 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4427 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4431 case InlineAsm::isClobber: {
4432 // Add the clobbered value to the operand list, so that the register
4433 // allocator is aware that the physreg got clobbered.
4434 if (!OpInfo.AssignedRegs.Regs.empty())
4435 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4442 // Finish up input operands.
4443 AsmNodeOperands[0] = Chain;
4444 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4446 Chain = DAG.getNode(ISD::INLINEASM,
4447 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4448 &AsmNodeOperands[0], AsmNodeOperands.size());
4449 Flag = Chain.getValue(1);
4451 // If this asm returns a register value, copy the result from that register
4452 // and set it as the value of the call.
4453 if (!RetValRegs.Regs.empty()) {
4454 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4456 // If any of the results of the inline asm is a vector, it may have the
4457 // wrong width/num elts. This can happen for register classes that can
4458 // contain multiple different value types. The preg or vreg allocated may
4459 // not have the same VT as was expected. Convert it to the right type with
4461 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4462 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4463 if (Val.Val->getValueType(i).isVector())
4464 Val = DAG.getNode(ISD::BIT_CONVERT,
4465 TLI.getValueType(ResSTy->getElementType(i)), Val);
4468 if (Val.getValueType().isVector())
4469 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4473 setValue(CS.getInstruction(), Val);
4476 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
4478 // Process indirect outputs, first output all of the flagged copies out of
4480 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4481 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4482 Value *Ptr = IndirectStoresToEmit[i].second;
4483 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4484 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4487 // Emit the non-flagged stores from the physregs.
4488 SmallVector<SDOperand, 8> OutChains;
4489 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4490 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4491 getValue(StoresToEmit[i].second),
4492 StoresToEmit[i].second, 0));
4493 if (!OutChains.empty())
4494 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4495 &OutChains[0], OutChains.size());
4500 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4501 SDOperand Src = getValue(I.getOperand(0));
4503 MVT IntPtr = TLI.getPointerTy();
4505 if (IntPtr.bitsLT(Src.getValueType()))
4506 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4507 else if (IntPtr.bitsGT(Src.getValueType()))
4508 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4510 // Scale the source by the type size.
4511 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4512 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4513 Src, DAG.getIntPtrConstant(ElementSize));
4515 TargetLowering::ArgListTy Args;
4516 TargetLowering::ArgListEntry Entry;
4518 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4519 Args.push_back(Entry);
4521 std::pair<SDOperand,SDOperand> Result =
4522 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4523 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4524 setValue(&I, Result.first); // Pointers always fit in registers
4525 DAG.setRoot(Result.second);
4528 void SelectionDAGLowering::visitFree(FreeInst &I) {
4529 TargetLowering::ArgListTy Args;
4530 TargetLowering::ArgListEntry Entry;
4531 Entry.Node = getValue(I.getOperand(0));
4532 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4533 Args.push_back(Entry);
4534 MVT IntPtr = TLI.getPointerTy();
4535 std::pair<SDOperand,SDOperand> Result =
4536 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4537 CallingConv::C, true,
4538 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4539 DAG.setRoot(Result.second);
4542 // EmitInstrWithCustomInserter - This method should be implemented by targets
4543 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4544 // instructions are special in various ways, which require special support to
4545 // insert. The specified MachineInstr is created but not inserted into any
4546 // basic blocks, and the scheduler passes ownership of it to this method.
4547 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4548 MachineBasicBlock *MBB) {
4549 cerr << "If a target marks an instruction with "
4550 << "'usesCustomDAGSchedInserter', it must implement "
4551 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4556 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4557 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4558 getValue(I.getOperand(1)),
4559 DAG.getSrcValue(I.getOperand(1))));
4562 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4563 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4564 getValue(I.getOperand(0)),
4565 DAG.getSrcValue(I.getOperand(0)));
4567 DAG.setRoot(V.getValue(1));
4570 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4571 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4572 getValue(I.getOperand(1)),
4573 DAG.getSrcValue(I.getOperand(1))));
4576 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4577 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4578 getValue(I.getOperand(1)),
4579 getValue(I.getOperand(2)),
4580 DAG.getSrcValue(I.getOperand(1)),
4581 DAG.getSrcValue(I.getOperand(2))));
4584 /// TargetLowering::LowerArguments - This is the default LowerArguments
4585 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4586 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4587 /// integrated into SDISel.
4588 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
4589 SmallVectorImpl<SDOperand> &ArgValues) {
4590 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4591 SmallVector<SDOperand, 3+16> Ops;
4592 Ops.push_back(DAG.getRoot());
4593 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4594 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4596 // Add one result value for each formal argument.
4597 SmallVector<MVT, 16> RetVals;
4599 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4601 SmallVector<MVT, 4> ValueVTs;
4602 ComputeValueVTs(*this, I->getType(), ValueVTs);
4603 for (unsigned Value = 0, NumValues = ValueVTs.size();
4604 Value != NumValues; ++Value) {
4605 MVT VT = ValueVTs[Value];
4606 const Type *ArgTy = VT.getTypeForMVT();
4607 ISD::ArgFlagsTy Flags;
4608 unsigned OriginalAlignment =
4609 getTargetData()->getABITypeAlignment(ArgTy);
4611 if (F.paramHasAttr(j, ParamAttr::ZExt))
4613 if (F.paramHasAttr(j, ParamAttr::SExt))
4615 if (F.paramHasAttr(j, ParamAttr::InReg))
4617 if (F.paramHasAttr(j, ParamAttr::StructRet))
4619 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4621 const PointerType *Ty = cast<PointerType>(I->getType());
4622 const Type *ElementTy = Ty->getElementType();
4623 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4624 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4625 // For ByVal, alignment should be passed from FE. BE will guess if
4626 // this info is not there but there are cases it cannot get right.
4627 if (F.getParamAlignment(j))
4628 FrameAlign = F.getParamAlignment(j);
4629 Flags.setByValAlign(FrameAlign);
4630 Flags.setByValSize(FrameSize);
4632 if (F.paramHasAttr(j, ParamAttr::Nest))
4634 Flags.setOrigAlign(OriginalAlignment);
4636 MVT RegisterVT = getRegisterType(VT);
4637 unsigned NumRegs = getNumRegisters(VT);
4638 for (unsigned i = 0; i != NumRegs; ++i) {
4639 RetVals.push_back(RegisterVT);
4640 ISD::ArgFlagsTy MyFlags = Flags;
4641 if (NumRegs > 1 && i == 0)
4643 // if it isn't first piece, alignment must be 1
4645 MyFlags.setOrigAlign(1);
4646 Ops.push_back(DAG.getArgFlags(MyFlags));
4651 RetVals.push_back(MVT::Other);
4654 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4655 DAG.getVTList(&RetVals[0], RetVals.size()),
4656 &Ops[0], Ops.size()).Val;
4658 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4659 // allows exposing the loads that may be part of the argument access to the
4660 // first DAGCombiner pass.
4661 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
4663 // The number of results should match up, except that the lowered one may have
4664 // an extra flag result.
4665 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4666 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4667 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4668 && "Lowering produced unexpected number of results!");
4669 Result = TmpRes.Val;
4671 unsigned NumArgRegs = Result->getNumValues() - 1;
4672 DAG.setRoot(SDOperand(Result, NumArgRegs));
4674 // Set up the return result vector.
4677 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4679 SmallVector<MVT, 4> ValueVTs;
4680 ComputeValueVTs(*this, I->getType(), ValueVTs);
4681 for (unsigned Value = 0, NumValues = ValueVTs.size();
4682 Value != NumValues; ++Value) {
4683 MVT VT = ValueVTs[Value];
4684 MVT PartVT = getRegisterType(VT);
4686 unsigned NumParts = getNumRegisters(VT);
4687 SmallVector<SDOperand, 4> Parts(NumParts);
4688 for (unsigned j = 0; j != NumParts; ++j)
4689 Parts[j] = SDOperand(Result, i++);
4691 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4692 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4693 AssertOp = ISD::AssertSext;
4694 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4695 AssertOp = ISD::AssertZext;
4697 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4701 assert(i == NumArgRegs && "Argument register count mismatch!");
4705 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4706 /// implementation, which just inserts an ISD::CALL node, which is later custom
4707 /// lowered by the target to something concrete. FIXME: When all targets are
4708 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4709 std::pair<SDOperand, SDOperand>
4710 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4711 bool RetSExt, bool RetZExt, bool isVarArg,
4712 unsigned CallingConv, bool isTailCall,
4714 ArgListTy &Args, SelectionDAG &DAG) {
4715 SmallVector<SDOperand, 32> Ops;
4716 Ops.push_back(Chain); // Op#0 - Chain
4717 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4718 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4719 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4720 Ops.push_back(Callee);
4722 // Handle all of the outgoing arguments.
4723 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4724 SmallVector<MVT, 4> ValueVTs;
4725 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
4726 for (unsigned Value = 0, NumValues = ValueVTs.size();
4727 Value != NumValues; ++Value) {
4728 MVT VT = ValueVTs[Value];
4729 const Type *ArgTy = VT.getTypeForMVT();
4730 SDOperand Op = SDOperand(Args[i].Node.Val, Args[i].Node.ResNo + Value);
4731 ISD::ArgFlagsTy Flags;
4732 unsigned OriginalAlignment =
4733 getTargetData()->getABITypeAlignment(ArgTy);
4739 if (Args[i].isInReg)
4743 if (Args[i].isByVal) {
4745 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4746 const Type *ElementTy = Ty->getElementType();
4747 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4748 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4749 // For ByVal, alignment should come from FE. BE will guess if this
4750 // info is not there but there are cases it cannot get right.
4751 if (Args[i].Alignment)
4752 FrameAlign = Args[i].Alignment;
4753 Flags.setByValAlign(FrameAlign);
4754 Flags.setByValSize(FrameSize);
4758 Flags.setOrigAlign(OriginalAlignment);
4760 MVT PartVT = getRegisterType(VT);
4761 unsigned NumParts = getNumRegisters(VT);
4762 SmallVector<SDOperand, 4> Parts(NumParts);
4763 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4766 ExtendKind = ISD::SIGN_EXTEND;
4767 else if (Args[i].isZExt)
4768 ExtendKind = ISD::ZERO_EXTEND;
4770 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4772 for (unsigned i = 0; i != NumParts; ++i) {
4773 // if it isn't first piece, alignment must be 1
4774 ISD::ArgFlagsTy MyFlags = Flags;
4775 if (NumParts > 1 && i == 0)
4778 MyFlags.setOrigAlign(1);
4780 Ops.push_back(Parts[i]);
4781 Ops.push_back(DAG.getArgFlags(MyFlags));
4786 // Figure out the result value types. We start by making a list of
4787 // the potentially illegal return value types.
4788 SmallVector<MVT, 4> LoweredRetTys;
4789 SmallVector<MVT, 4> RetTys;
4790 ComputeValueVTs(*this, RetTy, RetTys);
4792 // Then we translate that to a list of legal types.
4793 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4795 MVT RegisterVT = getRegisterType(VT);
4796 unsigned NumRegs = getNumRegisters(VT);
4797 for (unsigned i = 0; i != NumRegs; ++i)
4798 LoweredRetTys.push_back(RegisterVT);
4801 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4803 // Create the CALL node.
4804 SDOperand Res = DAG.getNode(ISD::CALL,
4805 DAG.getVTList(&LoweredRetTys[0],
4806 LoweredRetTys.size()),
4807 &Ops[0], Ops.size());
4808 Chain = Res.getValue(LoweredRetTys.size() - 1);
4810 // Gather up the call result into a single value.
4811 if (RetTy != Type::VoidTy) {
4812 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4815 AssertOp = ISD::AssertSext;
4817 AssertOp = ISD::AssertZext;
4819 SmallVector<SDOperand, 4> ReturnValues;
4821 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4823 MVT RegisterVT = getRegisterType(VT);
4824 unsigned NumRegs = getNumRegisters(VT);
4825 unsigned RegNoEnd = NumRegs + RegNo;
4826 SmallVector<SDOperand, 4> Results;
4827 for (; RegNo != RegNoEnd; ++RegNo)
4828 Results.push_back(Res.getValue(RegNo));
4829 SDOperand ReturnValue =
4830 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4832 ReturnValues.push_back(ReturnValue);
4834 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
4835 &ReturnValues[0], ReturnValues.size());
4838 return std::make_pair(Res, Chain);
4841 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4842 assert(0 && "LowerOperation not implemented for this target!");
4848 //===----------------------------------------------------------------------===//
4849 // SelectionDAGISel code
4850 //===----------------------------------------------------------------------===//
4852 unsigned SelectionDAGISel::MakeReg(MVT VT) {
4853 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4856 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4857 AU.addRequired<AliasAnalysis>();
4858 AU.addRequired<CollectorModuleMetadata>();
4859 AU.setPreservesAll();
4862 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4863 // Get alias analysis for load/store combining.
4864 AA = &getAnalysis<AliasAnalysis>();
4866 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4867 if (MF.getFunction()->hasCollector())
4868 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4871 RegInfo = &MF.getRegInfo();
4872 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4874 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4876 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4877 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4878 // Mark landing pad.
4879 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4881 SelectAllBasicBlocks(Fn, MF, FuncInfo);
4883 // Add function live-ins to entry block live-in set.
4884 BasicBlock *EntryBB = &Fn.getEntryBlock();
4885 BB = FuncInfo.MBBMap[EntryBB];
4886 if (!RegInfo->livein_empty())
4887 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4888 E = RegInfo->livein_end(); I != E; ++I)
4889 BB->addLiveIn(I->first);
4892 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4893 "Not all catch info was assigned to a landing pad!");
4899 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4900 SDOperand Op = getValue(V);
4901 assert((Op.getOpcode() != ISD::CopyFromReg ||
4902 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4903 "Copy from a reg to the same reg!");
4904 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4906 RegsForValue RFV(TLI, Reg, V->getType());
4907 SDOperand Chain = DAG.getEntryNode();
4908 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4909 PendingExports.push_back(Chain);
4912 void SelectionDAGISel::
4913 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4914 // If this is the entry block, emit arguments.
4915 Function &F = *LLVMBB->getParent();
4916 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4917 SDOperand OldRoot = SDL.DAG.getRoot();
4918 SmallVector<SDOperand, 16> Args;
4919 TLI.LowerArguments(F, SDL.DAG, Args);
4922 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4924 SmallVector<MVT, 4> ValueVTs;
4925 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
4926 unsigned NumValues = ValueVTs.size();
4927 if (!AI->use_empty()) {
4928 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues));
4929 // If this argument is live outside of the entry block, insert a copy from
4930 // whereever we got it to the vreg that other BB's will reference it as.
4931 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4932 if (VMI != FuncInfo.ValueMap.end()) {
4933 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4939 // Finally, if the target has anything special to do, allow it to do so.
4940 // FIXME: this should insert code into the DAG!
4941 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4944 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4945 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4946 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4947 if (isSelector(I)) {
4948 // Apply the catch info to DestBB.
4949 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4951 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4952 FLI.CatchInfoFound.insert(I);
4957 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4958 /// whether object offset >= 0.
4960 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDOperand Op) {
4961 if (!isa<FrameIndexSDNode>(Op)) return false;
4963 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
4964 int FrameIdx = FrameIdxNode->getIndex();
4965 return MFI->isFixedObjectIndex(FrameIdx) &&
4966 MFI->getObjectOffset(FrameIdx) >= 0;
4969 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
4970 /// possibly be overwritten when lowering the outgoing arguments in a tail
4971 /// call. Currently the implementation of this call is very conservative and
4972 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
4973 /// virtual registers would be overwritten by direct lowering.
4974 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op,
4975 MachineFrameInfo * MFI) {
4976 RegisterSDNode * OpReg = NULL;
4977 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
4978 (Op.getOpcode()== ISD::CopyFromReg &&
4979 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
4980 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
4981 (Op.getOpcode() == ISD::LOAD &&
4982 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
4983 (Op.getOpcode() == ISD::MERGE_VALUES &&
4984 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
4985 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
4991 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4992 /// DAG and fixes their tailcall attribute operand.
4993 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4994 TargetLowering& TLI) {
4995 SDNode * Ret = NULL;
4996 SDOperand Terminator = DAG.getRoot();
4999 if (Terminator.getOpcode() == ISD::RET) {
5000 Ret = Terminator.Val;
5003 // Fix tail call attribute of CALL nodes.
5004 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
5005 BI = DAG.allnodes_end(); BI != BE; ) {
5007 if (BI->getOpcode() == ISD::CALL) {
5008 SDOperand OpRet(Ret, 0);
5009 SDOperand OpCall(BI, 0);
5010 bool isMarkedTailCall =
5011 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5012 // If CALL node has tail call attribute set to true and the call is not
5013 // eligible (no RET or the target rejects) the attribute is fixed to
5014 // false. The TargetLowering::IsEligibleForTailCallOptimization function
5015 // must correctly identify tail call optimizable calls.
5016 if (!isMarkedTailCall) continue;
5018 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5019 // Not eligible. Mark CALL node as non tail call.
5020 SmallVector<SDOperand, 32> Ops;
5022 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5023 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5027 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5029 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5031 // Look for tail call clobbered arguments. Emit a series of
5032 // copyto/copyfrom virtual register nodes to protect them.
5033 SmallVector<SDOperand, 32> Ops;
5034 SDOperand Chain = OpCall.getOperand(0), InFlag;
5036 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5037 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5039 if (idx > 4 && (idx % 2)) {
5040 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5041 getArgFlags().isByVal();
5042 MachineFunction &MF = DAG.getMachineFunction();
5043 MachineFrameInfo *MFI = MF.getFrameInfo();
5045 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
5046 MVT VT = Arg.getValueType();
5047 unsigned VReg = MF.getRegInfo().
5048 createVirtualRegister(TLI.getRegClassFor(VT));
5049 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5050 InFlag = Chain.getValue(1);
5051 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5052 Chain = Arg.getValue(1);
5053 InFlag = Arg.getValue(2);
5058 // Link in chain of CopyTo/CopyFromReg.
5060 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5066 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
5067 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5068 FunctionLoweringInfo &FuncInfo) {
5069 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
5071 // Lower any arguments needed in this block if this is the entry block.
5072 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
5073 LowerArguments(LLVMBB, SDL);
5075 BB = FuncInfo.MBBMap[LLVMBB];
5076 SDL.setCurrentBasicBlock(BB);
5078 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
5080 if (MMI && BB->isLandingPad()) {
5081 // Add a label to mark the beginning of the landing pad. Deletion of the
5082 // landing pad can thus be detected via the MachineModuleInfo.
5083 unsigned LabelID = MMI->addLandingPad(BB);
5084 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID));
5086 // Mark exception register as live in.
5087 unsigned Reg = TLI.getExceptionAddressRegister();
5088 if (Reg) BB->addLiveIn(Reg);
5090 // Mark exception selector register as live in.
5091 Reg = TLI.getExceptionSelectorRegister();
5092 if (Reg) BB->addLiveIn(Reg);
5094 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5095 // function and list of typeids logically belong to the invoke (or, if you
5096 // like, the basic block containing the invoke), and need to be associated
5097 // with it in the dwarf exception handling tables. Currently however the
5098 // information is provided by an intrinsic (eh.selector) that can be moved
5099 // to unexpected places by the optimizers: if the unwind edge is critical,
5100 // then breaking it can result in the intrinsics being in the successor of
5101 // the landing pad, not the landing pad itself. This results in exceptions
5102 // not being caught because no typeids are associated with the invoke.
5103 // This may not be the only way things can go wrong, but it is the only way
5104 // we try to work around for the moment.
5105 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5107 if (Br && Br->isUnconditional()) { // Critical edge?
5108 BasicBlock::iterator I, E;
5109 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5114 // No catch info found - try to extract some from the successor.
5115 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5119 // Lower all of the non-terminator instructions.
5120 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
5124 // Ensure that all instructions which are used outside of their defining
5125 // blocks are available as virtual registers. Invoke is handled elsewhere.
5126 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
5127 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
5128 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
5129 if (VMI != FuncInfo.ValueMap.end())
5130 SDL.CopyValueToVirtualRegister(I, VMI->second);
5133 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5134 // ensure constants are generated when needed. Remember the virtual registers
5135 // that need to be added to the Machine PHI nodes as input. We cannot just
5136 // directly add them, because expansion might result in multiple MBB's for one
5137 // BB. As such, the start of the BB might correspond to a different MBB than
5140 TerminatorInst *TI = LLVMBB->getTerminator();
5142 // Emit constants only once even if used by multiple PHI nodes.
5143 std::map<Constant*, unsigned> ConstantsOut;
5145 // Vector bool would be better, but vector<bool> is really slow.
5146 std::vector<unsigned char> SuccsHandled;
5147 if (TI->getNumSuccessors())
5148 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
5150 // Check successor nodes' PHI nodes that expect a constant to be available
5152 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5153 BasicBlock *SuccBB = TI->getSuccessor(succ);
5154 if (!isa<PHINode>(SuccBB->begin())) continue;
5155 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
5157 // If this terminator has multiple identical successors (common for
5158 // switches), only handle each succ once.
5159 unsigned SuccMBBNo = SuccMBB->getNumber();
5160 if (SuccsHandled[SuccMBBNo]) continue;
5161 SuccsHandled[SuccMBBNo] = true;
5163 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5166 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5167 // nodes and Machine PHI nodes, but the incoming operands have not been
5169 for (BasicBlock::iterator I = SuccBB->begin();
5170 (PN = dyn_cast<PHINode>(I)); ++I) {
5171 // Ignore dead phi's.
5172 if (PN->use_empty()) continue;
5175 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5177 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5178 unsigned &RegOut = ConstantsOut[C];
5180 RegOut = FuncInfo.CreateRegForValue(C);
5181 SDL.CopyValueToVirtualRegister(C, RegOut);
5185 Reg = FuncInfo.ValueMap[PHIOp];
5187 assert(isa<AllocaInst>(PHIOp) &&
5188 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5189 "Didn't codegen value into a register!??");
5190 Reg = FuncInfo.CreateRegForValue(PHIOp);
5191 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
5195 // Remember that this register needs to added to the machine PHI node as
5196 // the input for this MBB.
5197 MVT VT = TLI.getValueType(PN->getType());
5198 unsigned NumRegisters = TLI.getNumRegisters(VT);
5199 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5200 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5203 ConstantsOut.clear();
5205 // Lower the terminator after the copies are emitted.
5206 SDL.visit(*LLVMBB->getTerminator());
5208 // Copy over any CaseBlock records that may now exist due to SwitchInst
5209 // lowering, as well as any jump table information.
5210 SwitchCases.clear();
5211 SwitchCases = SDL.SwitchCases;
5213 JTCases = SDL.JTCases;
5214 BitTestCases.clear();
5215 BitTestCases = SDL.BitTestCases;
5217 // Make sure the root of the DAG is up-to-date.
5218 DAG.setRoot(SDL.getControlRoot());
5220 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5221 // with correct tailcall attribute so that the target can rely on the tailcall
5222 // attribute indicating whether the call is really eligible for tail call
5224 CheckDAGForTailCallsAndFixThem(DAG, TLI);
5227 void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
5228 SmallPtrSet<SDNode*, 128> VisitedNodes;
5229 SmallVector<SDNode*, 128> Worklist;
5231 Worklist.push_back(DAG.getRoot().Val);
5237 while (!Worklist.empty()) {
5238 SDNode *N = Worklist.back();
5239 Worklist.pop_back();
5241 // If we've already seen this node, ignore it.
5242 if (!VisitedNodes.insert(N))
5245 // Otherwise, add all chain operands to the worklist.
5246 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5247 if (N->getOperand(i).getValueType() == MVT::Other)
5248 Worklist.push_back(N->getOperand(i).Val);
5250 // If this is a CopyToReg with a vreg dest, process it.
5251 if (N->getOpcode() != ISD::CopyToReg)
5254 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5255 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5258 // Ignore non-scalar or non-integer values.
5259 SDOperand Src = N->getOperand(2);
5260 MVT SrcVT = Src.getValueType();
5261 if (!SrcVT.isInteger() || SrcVT.isVector())
5264 unsigned NumSignBits = DAG.ComputeNumSignBits(Src);
5265 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5266 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5268 // Only install this information if it tells us something.
5269 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5270 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5271 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5272 if (DestReg >= FLI.LiveOutRegInfo.size())
5273 FLI.LiveOutRegInfo.resize(DestReg+1);
5274 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5275 LOI.NumSignBits = NumSignBits;
5276 LOI.KnownOne = NumSignBits;
5277 LOI.KnownZero = NumSignBits;
5282 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
5283 DOUT << "Lowered selection DAG:\n";
5286 // Run the DAG combiner in pre-legalize mode.
5287 if (TimePassesIsEnabled) {
5288 NamedRegionTimer T("DAG Combining 1");
5289 DAG.Combine(false, *AA);
5291 DAG.Combine(false, *AA);
5294 DOUT << "Optimized lowered selection DAG:\n";
5297 // Second step, hack on the DAG until it only uses operations and types that
5298 // the target supports.
5299 #if 0 // Enable this some day.
5300 DAG.LegalizeTypes();
5301 // Someday even later, enable a dag combine pass here.
5303 if (TimePassesIsEnabled) {
5304 NamedRegionTimer T("DAG Legalization");
5310 DOUT << "Legalized selection DAG:\n";
5313 // Run the DAG combiner in post-legalize mode.
5314 if (TimePassesIsEnabled) {
5315 NamedRegionTimer T("DAG Combining 2");
5316 DAG.Combine(true, *AA);
5318 DAG.Combine(true, *AA);
5321 DOUT << "Optimized legalized selection DAG:\n";
5324 if (ViewISelDAGs) DAG.viewGraph();
5326 if (!FastISel && EnableValueProp)
5327 ComputeLiveOutVRegInfo(DAG);
5329 // Third, instruction select all of the operations to machine code, adding the
5330 // code to the MachineBasicBlock.
5331 if (TimePassesIsEnabled) {
5332 NamedRegionTimer T("Instruction Selection");
5333 InstructionSelect(DAG);
5335 InstructionSelect(DAG);
5338 // Emit machine code to BB. This can change 'BB' to the last block being
5340 if (TimePassesIsEnabled) {
5341 NamedRegionTimer T("Instruction Scheduling");
5342 ScheduleAndEmitDAG(DAG);
5344 ScheduleAndEmitDAG(DAG);
5347 // Perform target specific isel post processing.
5348 if (TimePassesIsEnabled) {
5349 NamedRegionTimer T("Instruction Selection Post Processing");
5350 InstructionSelectPostProcessing(DAG);
5352 InstructionSelectPostProcessing(DAG);
5355 DOUT << "Selected machine code:\n";
5359 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
5360 FunctionLoweringInfo &FuncInfo) {
5361 // Define AllNodes here so that memory allocation is reused for
5362 // each basic block.
5363 alist<SDNode, LargestSDNode> AllNodes;
5365 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
5366 SelectBasicBlock(I, MF, FuncInfo, AllNodes);
5371 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5372 FunctionLoweringInfo &FuncInfo,
5373 alist<SDNode, LargestSDNode> &AllNodes) {
5374 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5376 SelectionDAG DAG(TLI, MF, FuncInfo,
5377 getAnalysisToUpdate<MachineModuleInfo>(),
5381 // First step, lower LLVM code to some DAG. This DAG may use operations and
5382 // types that are not supported by the target.
5383 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5385 // Second step, emit the lowered DAG as machine code.
5386 CodeGenAndEmitDAG(DAG);
5389 DOUT << "Total amount of phi nodes to update: "
5390 << PHINodesToUpdate.size() << "\n";
5391 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5392 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5393 << ", " << PHINodesToUpdate[i].second << ")\n";);
5395 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5396 // PHI nodes in successors.
5397 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
5398 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5399 MachineInstr *PHI = PHINodesToUpdate[i].first;
5400 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5401 "This is not a machine PHI node that we are updating!");
5402 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5404 PHI->addOperand(MachineOperand::CreateMBB(BB));
5409 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5410 // Lower header first, if it wasn't already lowered
5411 if (!BitTestCases[i].Emitted) {
5412 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5413 getAnalysisToUpdate<MachineModuleInfo>(),
5416 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5417 // Set the current basic block to the mbb we wish to insert the code into
5418 BB = BitTestCases[i].Parent;
5419 HSDL.setCurrentBasicBlock(BB);
5421 HSDL.visitBitTestHeader(BitTestCases[i]);
5422 HSDAG.setRoot(HSDL.getRoot());
5423 CodeGenAndEmitDAG(HSDAG);
5426 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5427 SelectionDAG BSDAG(TLI, MF, FuncInfo,
5428 getAnalysisToUpdate<MachineModuleInfo>(),
5431 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
5432 // Set the current basic block to the mbb we wish to insert the code into
5433 BB = BitTestCases[i].Cases[j].ThisBB;
5434 BSDL.setCurrentBasicBlock(BB);
5437 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5438 BitTestCases[i].Reg,
5439 BitTestCases[i].Cases[j]);
5441 BSDL.visitBitTestCase(BitTestCases[i].Default,
5442 BitTestCases[i].Reg,
5443 BitTestCases[i].Cases[j]);
5446 BSDAG.setRoot(BSDL.getRoot());
5447 CodeGenAndEmitDAG(BSDAG);
5451 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5452 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5453 MachineBasicBlock *PHIBB = PHI->getParent();
5454 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5455 "This is not a machine PHI node that we are updating!");
5456 // This is "default" BB. We have two jumps to it. From "header" BB and
5457 // from last "case" BB.
5458 if (PHIBB == BitTestCases[i].Default) {
5459 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5461 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5462 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5464 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5467 // One of "cases" BB.
5468 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5469 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5470 if (cBB->succ_end() !=
5471 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5472 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5474 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5480 // If the JumpTable record is filled in, then we need to emit a jump table.
5481 // Updating the PHI nodes is tricky in this case, since we need to determine
5482 // whether the PHI is a successor of the range check MBB or the jump table MBB
5483 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5484 // Lower header first, if it wasn't already lowered
5485 if (!JTCases[i].first.Emitted) {
5486 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5487 getAnalysisToUpdate<MachineModuleInfo>(),
5490 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5491 // Set the current basic block to the mbb we wish to insert the code into
5492 BB = JTCases[i].first.HeaderBB;
5493 HSDL.setCurrentBasicBlock(BB);
5495 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5496 HSDAG.setRoot(HSDL.getRoot());
5497 CodeGenAndEmitDAG(HSDAG);
5500 SelectionDAG JSDAG(TLI, MF, FuncInfo,
5501 getAnalysisToUpdate<MachineModuleInfo>(),
5504 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5505 // Set the current basic block to the mbb we wish to insert the code into
5506 BB = JTCases[i].second.MBB;
5507 JSDL.setCurrentBasicBlock(BB);
5509 JSDL.visitJumpTable(JTCases[i].second);
5510 JSDAG.setRoot(JSDL.getRoot());
5511 CodeGenAndEmitDAG(JSDAG);
5514 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5515 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5516 MachineBasicBlock *PHIBB = PHI->getParent();
5517 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5518 "This is not a machine PHI node that we are updating!");
5519 // "default" BB. We can go there only from header BB.
5520 if (PHIBB == JTCases[i].second.Default) {
5521 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5523 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5525 // JT BB. Just iterate over successors here
5526 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5527 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5529 PHI->addOperand(MachineOperand::CreateMBB(BB));
5534 // If the switch block involved a branch to one of the actual successors, we
5535 // need to update PHI nodes in that block.
5536 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5537 MachineInstr *PHI = PHINodesToUpdate[i].first;
5538 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5539 "This is not a machine PHI node that we are updating!");
5540 if (BB->isSuccessor(PHI->getParent())) {
5541 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5543 PHI->addOperand(MachineOperand::CreateMBB(BB));
5547 // If we generated any switch lowering information, build and codegen any
5548 // additional DAGs necessary.
5549 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5550 SelectionDAG SDAG(TLI, MF, FuncInfo,
5551 getAnalysisToUpdate<MachineModuleInfo>(),
5554 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5556 // Set the current basic block to the mbb we wish to insert the code into
5557 BB = SwitchCases[i].ThisBB;
5558 SDL.setCurrentBasicBlock(BB);
5561 SDL.visitSwitchCase(SwitchCases[i]);
5562 SDAG.setRoot(SDL.getRoot());
5563 CodeGenAndEmitDAG(SDAG);
5565 // Handle any PHI nodes in successors of this chunk, as if we were coming
5566 // from the original BB before switch expansion. Note that PHI nodes can
5567 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5568 // handle them the right number of times.
5569 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5570 for (MachineBasicBlock::iterator Phi = BB->begin();
5571 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5572 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5573 for (unsigned pn = 0; ; ++pn) {
5574 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5575 if (PHINodesToUpdate[pn].first == Phi) {
5576 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5578 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5584 // Don't process RHS if same block as LHS.
5585 if (BB == SwitchCases[i].FalseBB)
5586 SwitchCases[i].FalseBB = 0;
5588 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5589 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5590 SwitchCases[i].FalseBB = 0;
5592 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5597 //===----------------------------------------------------------------------===//
5598 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
5599 /// target node in the graph.
5600 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
5601 if (ViewSchedDAGs) DAG.viewGraph();
5603 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5607 RegisterScheduler::setDefault(Ctor);
5610 ScheduleDAG *SL = Ctor(this, &DAG, BB, FastISel);
5613 if (ViewSUnitDAGs) SL->viewGraph();
5619 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5620 return new HazardRecognizer();
5623 //===----------------------------------------------------------------------===//
5624 // Helper functions used by the generated instruction selector.
5625 //===----------------------------------------------------------------------===//
5626 // Calls to these methods are generated by tblgen.
5628 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5629 /// the dag combiner simplified the 255, we still want to match. RHS is the
5630 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5631 /// specified in the .td file (e.g. 255).
5632 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5633 int64_t DesiredMaskS) const {
5634 const APInt &ActualMask = RHS->getAPIntValue();
5635 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5637 // If the actual mask exactly matches, success!
5638 if (ActualMask == DesiredMask)
5641 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5642 if (ActualMask.intersects(~DesiredMask))
5645 // Otherwise, the DAG Combiner may have proven that the value coming in is
5646 // either already zero or is not demanded. Check for known zero input bits.
5647 APInt NeededMask = DesiredMask & ~ActualMask;
5648 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5651 // TODO: check to see if missing bits are just not demanded.
5653 // Otherwise, this pattern doesn't match.
5657 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5658 /// the dag combiner simplified the 255, we still want to match. RHS is the
5659 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5660 /// specified in the .td file (e.g. 255).
5661 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5662 int64_t DesiredMaskS) const {
5663 const APInt &ActualMask = RHS->getAPIntValue();
5664 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5666 // If the actual mask exactly matches, success!
5667 if (ActualMask == DesiredMask)
5670 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5671 if (ActualMask.intersects(~DesiredMask))
5674 // Otherwise, the DAG Combiner may have proven that the value coming in is
5675 // either already zero or is not demanded. Check for known zero input bits.
5676 APInt NeededMask = DesiredMask & ~ActualMask;
5678 APInt KnownZero, KnownOne;
5679 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5681 // If all the missing bits in the or are already known to be set, match!
5682 if ((NeededMask & KnownOne) == NeededMask)
5685 // TODO: check to see if missing bits are just not demanded.
5687 // Otherwise, this pattern doesn't match.
5692 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5693 /// by tblgen. Others should not call it.
5694 void SelectionDAGISel::
5695 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5696 std::vector<SDOperand> InOps;
5697 std::swap(InOps, Ops);
5699 Ops.push_back(InOps[0]); // input chain.
5700 Ops.push_back(InOps[1]); // input asm string.
5702 unsigned i = 2, e = InOps.size();
5703 if (InOps[e-1].getValueType() == MVT::Flag)
5704 --e; // Don't process a flag operand if it is here.
5707 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5708 if ((Flags & 7) != 4 /*MEM*/) {
5709 // Just skip over this operand, copying the operands verbatim.
5710 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5711 i += (Flags >> 3) + 1;
5713 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5714 // Otherwise, this is a memory operand. Ask the target to select it.
5715 std::vector<SDOperand> SelOps;
5716 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5717 cerr << "Could not match memory address. Inline asm failure!\n";
5721 // Add this to the output node.
5722 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5723 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5725 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5730 // Add the flag input back if present.
5731 if (e != InOps.size())
5732 Ops.push_back(InOps.back());
5735 char SelectionDAGISel::ID = 0;